2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/config.h>
18 #include <linux/init.h>
21 #include <linux/irq.h>
22 #include <linux/delay.h>
23 #include <linux/bootmem.h>
24 #include <linux/smp_lock.h>
25 #include <linux/interrupt.h>
26 #include <linux/mc146818rtc.h>
27 #include <linux/kernel_stat.h>
28 #include <linux/sysdev.h>
30 #include <asm/atomic.h>
33 #include <asm/mpspec.h>
34 #include <asm/pgalloc.h>
35 #include <asm/mach_apic.h>
40 int disable_apic_timer __initdata;
42 /* Using APIC to generate smp_local_timer_interrupt? */
43 int using_apic_timer = 0;
45 static DEFINE_PER_CPU(int, prof_multiplier) = 1;
46 static DEFINE_PER_CPU(int, prof_old_multiplier) = 1;
47 static DEFINE_PER_CPU(int, prof_counter) = 1;
49 static void apic_pm_activate(void);
51 void enable_NMI_through_LVT0 (void * dummy)
55 ver = apic_read(APIC_LVR);
56 ver = GET_APIC_VERSION(ver);
57 v = APIC_DM_NMI; /* unmask and set to NMI */
58 apic_write_around(APIC_LVT0, v);
63 unsigned int v, ver, maxlvt;
65 v = apic_read(APIC_LVR);
66 ver = GET_APIC_VERSION(v);
67 maxlvt = GET_APIC_MAXLVT(v);
71 void clear_local_APIC(void)
76 maxlvt = get_maxlvt();
79 * Masking an LVT entry on a P6 can trigger a local APIC error
80 * if the vector is zero. Mask LVTERR first to prevent this.
83 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
84 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
87 * Careful: we have to set masks only first to deassert
88 * any level-triggered sources.
90 v = apic_read(APIC_LVTT);
91 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
92 v = apic_read(APIC_LVT0);
93 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
94 v = apic_read(APIC_LVT1);
95 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
97 v = apic_read(APIC_LVTPC);
98 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
102 * Clean APIC state for other OSs:
104 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
105 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
106 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
108 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
110 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
111 v = GET_APIC_VERSION(apic_read(APIC_LVR));
112 if (APIC_INTEGRATED(v)) { /* !82489DX */
113 if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */
114 apic_write(APIC_ESR, 0);
119 void __init connect_bsp_APIC(void)
123 * Do not trust the local APIC being empty at bootup.
127 * PIC mode, enable APIC mode in the IMCR, i.e.
128 * connect BSP's local APIC to INT and NMI lines.
130 apic_printk(APIC_VERBOSE, "leaving PIC mode, enabling APIC mode.\n");
136 void disconnect_bsp_APIC(int virt_wire_setup)
140 * Put the board back into PIC mode (has an effect
141 * only on certain older boards). Note that APIC
142 * interrupts, including IPIs, won't work beyond
143 * this point! The only exception are INIT IPIs.
145 apic_printk(APIC_QUIET, "disabling APIC mode, entering PIC mode.\n");
150 /* Go back to Virtual Wire compatibility mode */
153 /* For the spurious interrupt use vector F, and enable it */
154 value = apic_read(APIC_SPIV);
155 value &= ~APIC_VECTOR_MASK;
156 value |= APIC_SPIV_APIC_ENABLED;
158 apic_write_around(APIC_SPIV, value);
160 if (!virt_wire_setup) {
161 /* For LVT0 make it edge triggered, active high, external and enabled */
162 value = apic_read(APIC_LVT0);
163 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
164 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
165 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
166 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
167 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
168 apic_write_around(APIC_LVT0, value);
172 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
175 /* For LVT1 make it edge triggered, active high, nmi and enabled */
176 value = apic_read(APIC_LVT1);
178 APIC_MODE_MASK | APIC_SEND_PENDING |
179 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
180 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
181 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
182 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
183 apic_write_around(APIC_LVT1, value);
187 void disable_local_APIC(void)
194 * Disable APIC (implies clearing of registers
197 value = apic_read(APIC_SPIV);
198 value &= ~APIC_SPIV_APIC_ENABLED;
199 apic_write_around(APIC_SPIV, value);
203 * This is to verify that we're looking at a real local APIC.
204 * Check these against your board if the CPUs aren't getting
205 * started for no apparent reason.
207 int __init verify_local_APIC(void)
209 unsigned int reg0, reg1;
212 * The version register is read-only in a real APIC.
214 reg0 = apic_read(APIC_LVR);
215 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
216 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
217 reg1 = apic_read(APIC_LVR);
218 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
221 * The two version reads above should print the same
222 * numbers. If the second one is different, then we
223 * poke at a non-APIC.
229 * Check if the version looks reasonably.
231 reg1 = GET_APIC_VERSION(reg0);
232 if (reg1 == 0x00 || reg1 == 0xff)
235 if (reg1 < 0x02 || reg1 == 0xff)
239 * The ID register is read/write in a real APIC.
241 reg0 = apic_read(APIC_ID);
242 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
243 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
244 reg1 = apic_read(APIC_ID);
245 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
246 apic_write(APIC_ID, reg0);
247 if (reg1 != (reg0 ^ APIC_ID_MASK))
251 * The next two are just to see if we have sane values.
252 * They're only really relevant if we're in Virtual Wire
253 * compatibility mode, but most boxes are anymore.
255 reg0 = apic_read(APIC_LVT0);
256 apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0);
257 reg1 = apic_read(APIC_LVT1);
258 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
263 void __init sync_Arb_IDs(void)
265 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
266 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
267 if (ver >= 0x14) /* P4 or higher */
273 apic_wait_icr_idle();
275 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
276 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
280 extern void __error_in_apic_c (void);
283 * An initial setup of the virtual wire mode.
285 void __init init_bsp_APIC(void)
287 unsigned int value, ver;
290 * Don't do the setup now if we have a SMP BIOS as the
291 * through-I/O-APIC virtual wire mode might be active.
293 if (smp_found_config || !cpu_has_apic)
296 value = apic_read(APIC_LVR);
297 ver = GET_APIC_VERSION(value);
300 * Do not trust the local APIC being empty at bootup.
307 value = apic_read(APIC_SPIV);
308 value &= ~APIC_VECTOR_MASK;
309 value |= APIC_SPIV_APIC_ENABLED;
310 value |= APIC_SPIV_FOCUS_DISABLED;
311 value |= SPURIOUS_APIC_VECTOR;
312 apic_write_around(APIC_SPIV, value);
315 * Set up the virtual wire mode.
317 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
319 if (!APIC_INTEGRATED(ver)) /* 82489DX */
320 value |= APIC_LVT_LEVEL_TRIGGER;
321 apic_write_around(APIC_LVT1, value);
324 void __cpuinit setup_local_APIC (void)
326 unsigned int value, ver, maxlvt;
328 value = apic_read(APIC_LVR);
329 ver = GET_APIC_VERSION(value);
331 if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
335 * Double-check whether this APIC is really registered.
336 * This is meaningless in clustered apic mode, so we skip it.
338 if (!apic_id_registered())
342 * Intel recommends to set DFR, LDR and TPR before enabling
343 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
344 * document number 292116). So here it goes...
349 * Set Task Priority to 'accept all'. We never change this
352 value = apic_read(APIC_TASKPRI);
353 value &= ~APIC_TPRI_MASK;
354 apic_write_around(APIC_TASKPRI, value);
357 * Now that we are all set up, enable the APIC
359 value = apic_read(APIC_SPIV);
360 value &= ~APIC_VECTOR_MASK;
364 value |= APIC_SPIV_APIC_ENABLED;
367 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
368 * certain networking cards. If high frequency interrupts are
369 * happening on a particular IOAPIC pin, plus the IOAPIC routing
370 * entry is masked/unmasked at a high rate as well then sooner or
371 * later IOAPIC line gets 'stuck', no more interrupts are received
372 * from the device. If focus CPU is disabled then the hang goes
375 * [ This bug can be reproduced easily with a level-triggered
376 * PCI Ne2000 networking cards and PII/PIII processors, dual
380 * Actually disabling the focus CPU check just makes the hang less
381 * frequent as it makes the interrupt distributon model be more
382 * like LRU than MRU (the short-term load is more even across CPUs).
383 * See also the comment in end_level_ioapic_irq(). --macro
386 /* Enable focus processor (bit==0) */
387 value &= ~APIC_SPIV_FOCUS_DISABLED;
389 /* Disable focus processor (bit==1) */
390 value |= APIC_SPIV_FOCUS_DISABLED;
393 * Set spurious IRQ vector
395 value |= SPURIOUS_APIC_VECTOR;
396 apic_write_around(APIC_SPIV, value);
401 * set up through-local-APIC on the BP's LINT0. This is not
402 * strictly necessary in pure symmetric-IO mode, but sometimes
403 * we delegate interrupts to the 8259A.
406 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
408 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
409 if (!smp_processor_id() && (pic_mode || !value)) {
410 value = APIC_DM_EXTINT;
411 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id());
413 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
414 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id());
416 apic_write_around(APIC_LVT0, value);
419 * only the BP should see the LINT1 NMI signal, obviously.
421 if (!smp_processor_id())
424 value = APIC_DM_NMI | APIC_LVT_MASKED;
425 if (!APIC_INTEGRATED(ver)) /* 82489DX */
426 value |= APIC_LVT_LEVEL_TRIGGER;
427 apic_write_around(APIC_LVT1, value);
431 maxlvt = get_maxlvt();
432 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
433 apic_write(APIC_ESR, 0);
434 oldvalue = apic_read(APIC_ESR);
435 value = ERROR_APIC_VECTOR; // enables sending errors
436 apic_write_around(APIC_LVTERR, value);
438 * spec says clear errors after enabling vector.
441 apic_write(APIC_ESR, 0);
442 value = apic_read(APIC_ESR);
443 if (value != oldvalue)
444 apic_printk(APIC_VERBOSE,
445 "ESR value after enabling vector: %08x, after %08x\n",
449 nmi_watchdog_default();
450 if (nmi_watchdog == NMI_LOCAL_APIC)
451 setup_apic_nmi_watchdog();
458 /* 'active' is true if the local APIC was enabled by us and
459 not the BIOS; this signifies that we are also responsible
460 for disabling it before entering apm/acpi suspend */
462 /* r/w apic fields */
463 unsigned int apic_id;
464 unsigned int apic_taskpri;
465 unsigned int apic_ldr;
466 unsigned int apic_dfr;
467 unsigned int apic_spiv;
468 unsigned int apic_lvtt;
469 unsigned int apic_lvtpc;
470 unsigned int apic_lvt0;
471 unsigned int apic_lvt1;
472 unsigned int apic_lvterr;
473 unsigned int apic_tmict;
474 unsigned int apic_tdcr;
475 unsigned int apic_thmr;
478 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
482 if (!apic_pm_state.active)
485 apic_pm_state.apic_id = apic_read(APIC_ID);
486 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
487 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
488 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
489 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
490 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
491 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
492 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
493 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
494 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
495 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
496 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
497 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
498 local_save_flags(flags);
500 disable_local_APIC();
501 local_irq_restore(flags);
505 static int lapic_resume(struct sys_device *dev)
510 if (!apic_pm_state.active)
513 /* XXX: Pavel needs this for S3 resume, but can't explain why */
514 set_fixmap_nocache(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE);
516 local_irq_save(flags);
517 rdmsr(MSR_IA32_APICBASE, l, h);
518 l &= ~MSR_IA32_APICBASE_BASE;
519 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
520 wrmsr(MSR_IA32_APICBASE, l, h);
521 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
522 apic_write(APIC_ID, apic_pm_state.apic_id);
523 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
524 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
525 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
526 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
527 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
528 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
529 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
530 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
531 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
532 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
533 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
534 apic_write(APIC_ESR, 0);
536 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
537 apic_write(APIC_ESR, 0);
539 local_irq_restore(flags);
543 static struct sysdev_class lapic_sysclass = {
544 set_kset_name("lapic"),
545 .resume = lapic_resume,
546 .suspend = lapic_suspend,
549 static struct sys_device device_lapic = {
551 .cls = &lapic_sysclass,
554 static void __cpuinit apic_pm_activate(void)
556 apic_pm_state.active = 1;
559 static int __init init_lapic_sysfs(void)
564 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
565 error = sysdev_class_register(&lapic_sysclass);
567 error = sysdev_register(&device_lapic);
570 device_initcall(init_lapic_sysfs);
572 #else /* CONFIG_PM */
574 static void apic_pm_activate(void) { }
576 #endif /* CONFIG_PM */
578 static int __init apic_set_verbosity(char *str)
580 if (strcmp("debug", str) == 0)
581 apic_verbosity = APIC_DEBUG;
582 else if (strcmp("verbose", str) == 0)
583 apic_verbosity = APIC_VERBOSE;
585 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
586 " use apic=verbose or apic=debug", str);
591 __setup("apic=", apic_set_verbosity);
594 * Detect and enable local APICs on non-SMP boards.
595 * Original code written by Keir Fraser.
596 * On AMD64 we trust the BIOS - if it says no APIC it is likely
597 * not correctly set up (usually the APIC timer won't work etc.)
600 static int __init detect_init_APIC (void)
603 printk(KERN_INFO "No local APIC present\n");
607 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
612 void __init init_apic_mappings(void)
614 unsigned long apic_phys;
617 * If no local APIC can be found then set up a fake all
618 * zeroes page to simulate the local APIC and another
619 * one for the IO-APIC.
621 if (!smp_found_config && detect_init_APIC()) {
622 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
623 apic_phys = __pa(apic_phys);
625 apic_phys = mp_lapic_addr;
627 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
628 apic_printk(APIC_VERBOSE,"mapped APIC to %16lx (%16lx)\n", APIC_BASE, apic_phys);
631 * Fetch the APIC ID of the BSP in case we have a
632 * default configuration (or the MP table is broken).
634 if (boot_cpu_id == -1U)
635 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
637 #ifdef CONFIG_X86_IO_APIC
639 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
642 for (i = 0; i < nr_ioapics; i++) {
643 if (smp_found_config) {
644 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
646 ioapic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
647 ioapic_phys = __pa(ioapic_phys);
649 set_fixmap_nocache(idx, ioapic_phys);
650 apic_printk(APIC_VERBOSE,"mapped IOAPIC to %016lx (%016lx)\n",
651 __fix_to_virt(idx), ioapic_phys);
659 * This function sets up the local APIC timer, with a timeout of
660 * 'clocks' APIC bus clock. During calibration we actually call
661 * this function twice on the boot CPU, once with a bogus timeout
662 * value, second time for real. The other (noncalibrating) CPUs
663 * call this function only once, with the real, calibrated value.
665 * We do reads before writes even if unnecessary, to get around the
666 * P5 APIC double write bug.
669 #define APIC_DIVISOR 16
671 static void __setup_APIC_LVTT(unsigned int clocks)
673 unsigned int lvtt_value, tmp_value, ver;
675 ver = GET_APIC_VERSION(apic_read(APIC_LVR));
676 lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR;
677 if (!APIC_INTEGRATED(ver))
678 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
679 apic_write_around(APIC_LVTT, lvtt_value);
684 tmp_value = apic_read(APIC_TDCR);
685 apic_write_around(APIC_TDCR, (tmp_value
686 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
689 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
692 static void setup_APIC_timer(unsigned int clocks)
696 local_irq_save(flags);
698 /* For some reasons this doesn't work on Simics, so fake it for now */
699 if (!strstr(boot_cpu_data.x86_model_id, "Screwdriver")) {
700 __setup_APIC_LVTT(clocks);
704 /* wait for irq slice */
705 if (vxtime.hpet_address) {
706 int trigger = hpet_readl(HPET_T0_CMP);
707 while (hpet_readl(HPET_COUNTER) >= trigger)
709 while (hpet_readl(HPET_COUNTER) < trigger)
715 c2 |= inb_p(0x40) << 8;
720 c2 |= inb_p(0x40) << 8;
721 } while (c2 - c1 < 300);
724 __setup_APIC_LVTT(clocks);
726 local_irq_restore(flags);
730 * In this function we calibrate APIC bus clocks to the external
731 * timer. Unfortunately we cannot use jiffies and the timer irq
732 * to calibrate, since some later bootup code depends on getting
733 * the first irq? Ugh.
735 * We want to do the calibration only once since we
736 * want to have local timer irqs syncron. CPUs connected
737 * by the same APIC bus have the very same bus frequency.
738 * And we want to have irqs off anyways, no accidental
742 #define TICK_COUNT 100000000
744 static int __init calibrate_APIC_clock(void)
746 int apic, apic_start, tsc, tsc_start;
749 * Put whatever arbitrary (but long enough) timeout
750 * value into the APIC clock, we just want to get the
751 * counter running for calibration.
753 __setup_APIC_LVTT(1000000000);
755 apic_start = apic_read(APIC_TMCCT);
759 apic = apic_read(APIC_TMCCT);
761 } while ((tsc - tsc_start) < TICK_COUNT && (apic - apic_start) < TICK_COUNT);
763 result = (apic_start - apic) * 1000L * cpu_khz / (tsc - tsc_start);
765 printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
766 result / 1000 / 1000, result / 1000 % 1000);
768 return result * APIC_DIVISOR / HZ;
771 static unsigned int calibration_result;
773 void __init setup_boot_APIC_clock (void)
775 if (disable_apic_timer) {
776 printk(KERN_INFO "Disabling APIC timer\n");
780 printk(KERN_INFO "Using local APIC timer interrupts.\n");
781 using_apic_timer = 1;
785 calibration_result = calibrate_APIC_clock();
787 * Now set up the timer for real.
789 setup_APIC_timer(calibration_result);
794 void __cpuinit setup_secondary_APIC_clock(void)
796 local_irq_disable(); /* FIXME: Do we need this? --RR */
797 setup_APIC_timer(calibration_result);
801 void __cpuinit disable_APIC_timer(void)
803 if (using_apic_timer) {
806 v = apic_read(APIC_LVTT);
807 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
811 void enable_APIC_timer(void)
813 if (using_apic_timer) {
816 v = apic_read(APIC_LVTT);
817 apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED);
822 * the frequency of the profiling timer can be changed
823 * by writing a multiplier value into /proc/profile.
825 int setup_profiling_timer(unsigned int multiplier)
830 * Sanity check. [at least 500 APIC cycles should be
831 * between APIC interrupts as a rule of thumb, to avoid
834 if ( (!multiplier) || (calibration_result/multiplier < 500))
838 * Set the new multiplier for each CPU. CPUs don't start using the
839 * new values until the next timer interrupt in which they do process
840 * accounting. At that time they also adjust their APIC timers
843 for (i = 0; i < NR_CPUS; ++i)
844 per_cpu(prof_multiplier, i) = multiplier;
852 * Local timer interrupt handler. It does both profiling and
853 * process statistics/rescheduling.
855 * We do profiling in every local tick, statistics/rescheduling
856 * happen only every 'profiling multiplier' ticks. The default
857 * multiplier is 1 and it can be changed by writing the new multiplier
858 * value into /proc/profile.
861 void smp_local_timer_interrupt(struct pt_regs *regs)
863 int cpu = smp_processor_id();
865 profile_tick(CPU_PROFILING, regs);
866 if (--per_cpu(prof_counter, cpu) <= 0) {
868 * The multiplier may have changed since the last time we got
869 * to this point as a result of the user writing to
870 * /proc/profile. In this case we need to adjust the APIC
873 * Interrupts are already masked off at this point.
875 per_cpu(prof_counter, cpu) = per_cpu(prof_multiplier, cpu);
876 if (per_cpu(prof_counter, cpu) !=
877 per_cpu(prof_old_multiplier, cpu)) {
878 __setup_APIC_LVTT(calibration_result/
879 per_cpu(prof_counter, cpu));
880 per_cpu(prof_old_multiplier, cpu) =
881 per_cpu(prof_counter, cpu);
885 update_process_times(user_mode(regs));
890 * We take the 'long' return path, and there every subsystem
891 * grabs the appropriate locks (kernel lock/ irq lock).
893 * we might want to decouple profiling from the 'long path',
894 * and do the profiling totally in assembly.
896 * Currently this isn't too much of an issue (performance wise),
897 * we can take more than 100K local irqs per second on a 100 MHz P5.
902 * Local APIC timer interrupt. This is the most natural way for doing
903 * local interrupts, but local timer interrupts can be emulated by
904 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
906 * [ if a single-CPU system runs an SMP kernel then we call the local
907 * interrupt as well. Thus we cannot inline the local irq ... ]
909 void smp_apic_timer_interrupt(struct pt_regs *regs)
912 * the NMI deadlock-detector uses this.
914 add_pda(apic_timer_irqs, 1);
917 * NOTE! We'd better ACK the irq immediately,
918 * because timer handling can be slow.
922 * update_process_times() expects us to have done irq_enter().
923 * Besides, if we don't timer interrupts ignore the global
924 * interrupt lock, which is the WrongThing (tm) to do.
927 smp_local_timer_interrupt(regs);
932 * oem_force_hpet_timer -- force HPET mode for some boxes.
934 * Thus far, the major user of this is IBM's Summit2 series:
936 * Clustered boxes may have unsynced TSC problems if they are
937 * multi-chassis. Use available data to take a good guess.
938 * If in doubt, go HPET.
940 __init int oem_force_hpet_timer(void)
942 int i, clusters, zeros;
944 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
946 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
948 for (i = 0; i < NR_CPUS; i++) {
949 id = bios_cpu_apicid[i];
950 if (id != BAD_APICID)
951 __set_bit(APIC_CLUSTERID(id), clustermap);
954 /* Problem: Partially populated chassis may not have CPUs in some of
955 * the APIC clusters they have been allocated. Only present CPUs have
956 * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since
957 * clusters are allocated sequentially, count zeros only if they are
962 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
963 if (test_bit(i, clustermap)) {
964 clusters += 1 + zeros;
971 * If clusters > 2, then should be multi-chassis. Return 1 for HPET.
972 * Else return 0 to use TSC.
973 * May have to revisit this when multi-core + hyperthreaded CPUs come
974 * out, but AFAIK this will work even for them.
976 return (clusters > 2);
980 * This interrupt should _never_ happen with our APIC/SMP architecture
982 asmlinkage void smp_spurious_interrupt(void)
987 * Check if this really is a spurious interrupt and ACK it
988 * if it is a vectored one. Just in case...
989 * Spurious interrupts should not be ACKed.
991 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
992 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
996 static unsigned long last_warning;
997 static unsigned long skipped;
999 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1000 if (time_before(last_warning+30*HZ,jiffies)) {
1001 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, %ld skipped.\n",
1002 smp_processor_id(), skipped);
1003 last_warning = jiffies;
1013 * This interrupt should never happen with our APIC/SMP architecture
1016 asmlinkage void smp_error_interrupt(void)
1021 /* First tickle the hardware, only then report what went on. -- REW */
1022 v = apic_read(APIC_ESR);
1023 apic_write(APIC_ESR, 0);
1024 v1 = apic_read(APIC_ESR);
1026 atomic_inc(&irq_err_count);
1028 /* Here is what the APIC error bits mean:
1031 2: Send accept error
1032 3: Receive accept error
1034 5: Send illegal vector
1035 6: Received illegal vector
1036 7: Illegal register address
1038 printk (KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
1039 smp_processor_id(), v , v1);
1046 * This initializes the IO-APIC and APIC hardware if this is
1049 int __init APIC_init_uniprocessor (void)
1052 printk(KERN_INFO "Apic disabled\n");
1055 if (!cpu_has_apic) {
1057 printk(KERN_INFO "Apic disabled by BIOS\n");
1061 verify_local_APIC();
1065 phys_cpu_present_map = physid_mask_of_physid(0);
1066 apic_write_around(APIC_ID, boot_cpu_id);
1070 #ifdef CONFIG_X86_IO_APIC
1071 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1076 setup_boot_APIC_clock();
1077 check_nmi_watchdog();
1081 static __init int setup_disableapic(char *str)
1087 static __init int setup_nolapic(char *str)
1093 static __init int setup_noapictimer(char *str)
1095 disable_apic_timer = 1;
1099 /* dummy parsing: see setup.c */
1101 __setup("disableapic", setup_disableapic);
1102 __setup("nolapic", setup_nolapic); /* same as disableapic, for compatibility */
1104 __setup("noapictimer", setup_noapictimer);
1106 /* no "lapic" flag - we only use the lapic when the BIOS tells us so. */