arch/x86/platform/uv/uv_time.c

   1 /*
   2  * SGI RTC clock/timer routines.
   3  *
   4  *  This program is free software; you can redistribute it and/or modify
   5  *  it under the terms of the GNU General Public License as published by
   6  *  the Free Software Foundation; either version 2 of the License, or
   7  *  (at your option) any later version.
   8  *
   9  *  This program is distributed in the hope that it will be useful,
  10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *  GNU General Public License for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License
  15  *  along with this program; if not, write to the Free Software
  16  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  17  *
  18  *  Copyright (c) 2009 Silicon Graphics, Inc.  All Rights Reserved.
  19  *  Copyright (c) Dimitri Sivanich
  20  */
  21 #include <linux/clockchips.h>
  22 #include <linux/slab.h>
  23
  24 #include <asm/uv/uv_mmrs.h>
  25 #include <asm/uv/uv_hub.h>
  26 #include <asm/uv/bios.h>
  27 #include <asm/uv/uv.h>
  28 #include <asm/apic.h>
  29 #include <asm/cpu.h>
  30
  31 #define RTC_NAME                "sgi_rtc"
  32
  33 static cycle_t uv_read_rtc(struct clocksource *cs);
  34 static int uv_rtc_next_event(unsigned long, struct clock_event_device *);
  35 static void uv_rtc_timer_setup(enum clock_event_mode,
  36                                 struct clock_event_device *);
  37
  38 static struct clocksource clocksource_uv = {
  39         .name           = RTC_NAME,
  40         .rating         = 400,
  41         .read           = uv_read_rtc,
  42         .mask           = (cycle_t)UVH_RTC_REAL_TIME_CLOCK_MASK,
  43         .shift          = 10,
  44         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  45 };
  46
  47 static struct clock_event_device clock_event_device_uv = {
  48         .name           = RTC_NAME,
  49         .features       = CLOCK_EVT_FEAT_ONESHOT,
  50         .shift          = 20,
  51         .rating         = 400,
  52         .irq            = -1,
  53         .set_next_event = uv_rtc_next_event,
  54         .set_mode       = uv_rtc_timer_setup,
  55         .event_handler  = NULL,
  56 };
  57
  58 static DEFINE_PER_CPU(struct clock_event_device, cpu_ced);
  59
  60 /* There is one of these allocated per node */
  61 struct uv_rtc_timer_head {
  62         spinlock_t      lock;
  63         /* next cpu waiting for timer, local node relative: */
  64         int             next_cpu;
  65         /* number of cpus on this node: */
  66         int             ncpus;
  67         struct {
  68                 int     lcpu;           /* systemwide logical cpu number */
  69                 u64     expires;        /* next timer expiration for this cpu */
  70         } cpu[1];
  71 };
  72
  73 /*
  74  * Access to uv_rtc_timer_head via blade id.
  75  */
  76 static struct uv_rtc_timer_head         **blade_info __read_mostly;
  77
  78 static int                              uv_rtc_evt_enable;
  79
  80 /*
  81  * Hardware interface routines
  82  */
  83
  84 /* Send IPIs to another node */
  85 static void uv_rtc_send_IPI(int cpu)
  86 {
  87         unsigned long apicid, val;
  88         int pnode;
  89
  90         apicid = cpu_physical_id(cpu);
  91         pnode = uv_apicid_to_pnode(apicid);
  92         apicid |= uv_apicid_hibits;
  93         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
  94               (apicid << UVH_IPI_INT_APIC_ID_SHFT) |
  95               (X86_PLATFORM_IPI_VECTOR << UVH_IPI_INT_VECTOR_SHFT);
  96
  97         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
  98 }
  99
 100 /* Check for an RTC interrupt pending */
 101 static int uv_intr_pending(int pnode)
 102 {
 103         return uv_read_global_mmr64(pnode, UVH_EVENT_OCCURRED0) &
 104                 UVH_EVENT_OCCURRED0_RTC1_MASK;
 105 }
 106
 107 /* Setup interrupt and return non-zero if early expiration occurred. */
 108 static int uv_setup_intr(int cpu, u64 expires)
 109 {
 110         u64 val;
 111         unsigned long apicid = cpu_physical_id(cpu) | uv_apicid_hibits;
 112         int pnode = uv_cpu_to_pnode(cpu);
 113
 114         uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG,
 115                 UVH_RTC1_INT_CONFIG_M_MASK);
 116         uv_write_global_mmr64(pnode, UVH_INT_CMPB, -1L);
 117
 118         uv_write_global_mmr64(pnode, UVH_EVENT_OCCURRED0_ALIAS,
 119                 UVH_EVENT_OCCURRED0_RTC1_MASK);
 120
 121         val = (X86_PLATFORM_IPI_VECTOR << UVH_RTC1_INT_CONFIG_VECTOR_SHFT) |
 122                 ((u64)apicid << UVH_RTC1_INT_CONFIG_APIC_ID_SHFT);
 123
 124         /* Set configuration */
 125         uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, val);
 126         /* Initialize comparator value */
 127         uv_write_global_mmr64(pnode, UVH_INT_CMPB, expires);
 128
 129         if (uv_read_rtc(NULL) <= expires)
 130                 return 0;
 131
 132         return !uv_intr_pending(pnode);
 133 }
 134
 135 /*
 136  * Per-cpu timer tracking routines
 137  */
 138
 139 static __init void uv_rtc_deallocate_timers(void)
 140 {
 141         int bid;
 142
 143         for_each_possible_blade(bid) {
 144                 kfree(blade_info[bid]);
 145         }
 146         kfree(blade_info);
 147 }
 148
 149 /* Allocate per-node list of cpu timer expiration times. */
 150 static __init int uv_rtc_allocate_timers(void)
 151 {
 152         int cpu;
 153
 154         blade_info = kmalloc(uv_possible_blades * sizeof(void *), GFP_KERNEL);
 155         if (!blade_info)
 156                 return -ENOMEM;
 157         memset(blade_info, 0, uv_possible_blades * sizeof(void *));
 158
 159         for_each_present_cpu(cpu) {
 160                 int nid = cpu_to_node(cpu);
 161                 int bid = uv_cpu_to_blade_id(cpu);
 162                 int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
 163                 struct uv_rtc_timer_head *head = blade_info[bid];
 164
 165                 if (!head) {
 166                         head = kmalloc_node(sizeof(struct uv_rtc_timer_head) +
 167                                 (uv_blade_nr_possible_cpus(bid) *
 168                                         2 * sizeof(u64)),
 169                                 GFP_KERNEL, nid);
 170                         if (!head) {
 171                                 uv_rtc_deallocate_timers();
 172                                 return -ENOMEM;
 173                         }
 174                         spin_lock_init(&head->lock);
 175                         head->ncpus = uv_blade_nr_possible_cpus(bid);
 176                         head->next_cpu = -1;
 177                         blade_info[bid] = head;
 178                 }
 179
 180                 head->cpu[bcpu].lcpu = cpu;
 181                 head->cpu[bcpu].expires = ULLONG_MAX;
 182         }
 183
 184         return 0;
 185 }
 186
 187 /* Find and set the next expiring timer.  */
 188 static void uv_rtc_find_next_timer(struct uv_rtc_timer_head *head, int pnode)
 189 {
 190         u64 lowest = ULLONG_MAX;
 191         int c, bcpu = -1;
 192
 193         head->next_cpu = -1;
 194         for (c = 0; c < head->ncpus; c++) {
 195                 u64 exp = head->cpu[c].expires;
 196                 if (exp < lowest) {
 197                         bcpu = c;
 198                         lowest = exp;
 199                 }
 200         }
 201         if (bcpu >= 0) {
 202                 head->next_cpu = bcpu;
 203                 c = head->cpu[bcpu].lcpu;
 204                 if (uv_setup_intr(c, lowest))
 205                         /* If we didn't set it up in time, trigger */
 206                         uv_rtc_send_IPI(c);
 207         } else {
 208                 uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG,
 209                         UVH_RTC1_INT_CONFIG_M_MASK);
 210         }
 211 }
 212
 213 /*
 214  * Set expiration time for current cpu.
 215  *
 216  * Returns 1 if we missed the expiration time.
 217  */
 218 static int uv_rtc_set_timer(int cpu, u64 expires)
 219 {
 220         int pnode = uv_cpu_to_pnode(cpu);
 221         int bid = uv_cpu_to_blade_id(cpu);
 222         struct uv_rtc_timer_head *head = blade_info[bid];
 223         int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
 224         u64 *t = &head->cpu[bcpu].expires;
 225         unsigned long flags;
 226         int next_cpu;
 227
 228         spin_lock_irqsave(&head->lock, flags);
 229
 230         next_cpu = head->next_cpu;
 231         *t = expires;
 232
 233         /* Will this one be next to go off? */
 234         if (next_cpu < 0 || bcpu == next_cpu ||
 235                         expires < head->cpu[next_cpu].expires) {
 236                 head->next_cpu = bcpu;
 237                 if (uv_setup_intr(cpu, expires)) {
 238                         *t = ULLONG_MAX;
 239                         uv_rtc_find_next_timer(head, pnode);
 240                         spin_unlock_irqrestore(&head->lock, flags);
 241                         return -ETIME;
 242                 }
 243         }
 244
 245         spin_unlock_irqrestore(&head->lock, flags);
 246         return 0;
 247 }
 248
 249 /*
 250  * Unset expiration time for current cpu.
 251  *
 252  * Returns 1 if this timer was pending.
 253  */
 254 static int uv_rtc_unset_timer(int cpu, int force)
 255 {
 256         int pnode = uv_cpu_to_pnode(cpu);
 257         int bid = uv_cpu_to_blade_id(cpu);
 258         struct uv_rtc_timer_head *head = blade_info[bid];
 259         int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
 260         u64 *t = &head->cpu[bcpu].expires;
 261         unsigned long flags;
 262         int rc = 0;
 263
 264         spin_lock_irqsave(&head->lock, flags);
 265
 266         if ((head->next_cpu == bcpu && uv_read_rtc(NULL) >= *t) || force)
 267                 rc = 1;
 268
 269         if (rc) {
 270                 *t = ULLONG_MAX;
 271                 /* Was the hardware setup for this timer? */
 272                 if (head->next_cpu == bcpu)
 273                         uv_rtc_find_next_timer(head, pnode);
 274         }
 275
 276         spin_unlock_irqrestore(&head->lock, flags);
 277
 278         return rc;
 279 }
 280
 281
 282 /*
 283  * Kernel interface routines.
 284  */
 285
 286 /*
 287  * Read the RTC.
 288  *
 289  * Starting with HUB rev 2.0, the UV RTC register is replicated across all
 290  * cachelines of it's own page.  This allows faster simultaneous reads
 291  * from a given socket.
 292  */
 293 static cycle_t uv_read_rtc(struct clocksource *cs)
 294 {
 295         unsigned long offset;
 296
 297         if (uv_get_min_hub_revision_id() == 1)
 298                 offset = 0;
 299         else
 300                 offset = (uv_blade_processor_id() * L1_CACHE_BYTES) % PAGE_SIZE;
 301
 302         return (cycle_t)uv_read_local_mmr(UVH_RTC | offset);
 303 }
 304
 305 /*
 306  * Program the next event, relative to now
 307  */
 308 static int uv_rtc_next_event(unsigned long delta,
 309                              struct clock_event_device *ced)
 310 {
 311         int ced_cpu = cpumask_first(ced->cpumask);
 312
 313         return uv_rtc_set_timer(ced_cpu, delta + uv_read_rtc(NULL));
 314 }
 315
 316 /*
 317  * Setup the RTC timer in oneshot mode
 318  */
 319 static void uv_rtc_timer_setup(enum clock_event_mode mode,
 320                                struct clock_event_device *evt)
 321 {
 322         int ced_cpu = cpumask_first(evt->cpumask);
 323
 324         switch (mode) {
 325         case CLOCK_EVT_MODE_PERIODIC:
 326         case CLOCK_EVT_MODE_ONESHOT:
 327         case CLOCK_EVT_MODE_RESUME:
 328                 /* Nothing to do here yet */
 329                 break;
 330         case CLOCK_EVT_MODE_UNUSED:
 331         case CLOCK_EVT_MODE_SHUTDOWN:
 332                 uv_rtc_unset_timer(ced_cpu, 1);
 333                 break;
 334         }
 335 }
 336
 337 static void uv_rtc_interrupt(void)
 338 {
 339         int cpu = smp_processor_id();
 340         struct clock_event_device *ced = &per_cpu(cpu_ced, cpu);
 341
 342         if (!ced || !ced->event_handler)
 343                 return;
 344
 345         if (uv_rtc_unset_timer(cpu, 0) != 1)
 346                 return;
 347
 348         ced->event_handler(ced);
 349 }
 350
 351 static int __init uv_enable_evt_rtc(char *str)
 352 {
 353         uv_rtc_evt_enable = 1;
 354
 355         return 1;
 356 }
 357 __setup("uvrtcevt", uv_enable_evt_rtc);
 358
 359 static __init void uv_rtc_register_clockevents(struct work_struct *dummy)
 360 {
 361         struct clock_event_device *ced = &__get_cpu_var(cpu_ced);
 362
 363         *ced = clock_event_device_uv;
 364         ced->cpumask = cpumask_of(smp_processor_id());
 365         clockevents_register_device(ced);
 366 }
 367
 368 static __init int uv_rtc_setup_clock(void)
 369 {
 370         int rc;
 371
 372         if (!is_uv_system())
 373                 return -ENODEV;
 374
 375         clocksource_uv.mult = clocksource_hz2mult(sn_rtc_cycles_per_second,
 376                                 clocksource_uv.shift);
 377
 378         /* If single blade, prefer tsc */
 379         if (uv_num_possible_blades() == 1)
 380                 clocksource_uv.rating = 250;
 381
 382         rc = clocksource_register(&clocksource_uv);
 383         if (rc)
 384                 printk(KERN_INFO "UV RTC clocksource failed rc %d\n", rc);
 385         else
 386                 printk(KERN_INFO "UV RTC clocksource registered freq %lu MHz\n",
 387                         sn_rtc_cycles_per_second/(unsigned long)1E6);
 388
 389         if (rc || !uv_rtc_evt_enable || x86_platform_ipi_callback)
 390                 return rc;
 391
 392         /* Setup and register clockevents */
 393         rc = uv_rtc_allocate_timers();
 394         if (rc)
 395                 goto error;
 396
 397         x86_platform_ipi_callback = uv_rtc_interrupt;
 398
 399         clock_event_device_uv.mult = div_sc(sn_rtc_cycles_per_second,
 400                                 NSEC_PER_SEC, clock_event_device_uv.shift);
 401
 402         clock_event_device_uv.min_delta_ns = NSEC_PER_SEC /
 403                                                 sn_rtc_cycles_per_second;
 404
 405         clock_event_device_uv.max_delta_ns = clocksource_uv.mask *
 406                                 (NSEC_PER_SEC / sn_rtc_cycles_per_second);
 407
 408         rc = schedule_on_each_cpu(uv_rtc_register_clockevents);
 409         if (rc) {
 410                 x86_platform_ipi_callback = NULL;
 411                 uv_rtc_deallocate_timers();
 412                 goto error;
 413         }
 414
 415         printk(KERN_INFO "UV RTC clockevents registered\n");
 416
 417         return 0;
 418
 419 error:
 420         clocksource_unregister(&clocksource_uv);
 421         printk(KERN_INFO "UV RTC clockevents failed rc %d\n", rc);
 422
 423         return rc;
 424 }
 425 arch_initcall(uv_rtc_setup_clock);