2 * SGI RTC clock/timer routines.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 * Copyright (c) 2009 Silicon Graphics, Inc. All Rights Reserved.
19 * Copyright (c) Dimitri Sivanich
21 #include <linux/clockchips.h>
22 #include <linux/slab.h>
24 #include <asm/uv/uv_mmrs.h>
25 #include <asm/uv/uv_hub.h>
26 #include <asm/uv/bios.h>
27 #include <asm/uv/uv.h>
31 #define RTC_NAME "sgi_rtc"
33 static cycle_t uv_read_rtc(struct clocksource *cs);
34 static int uv_rtc_next_event(unsigned long, struct clock_event_device *);
35 static void uv_rtc_timer_setup(enum clock_event_mode,
36 struct clock_event_device *);
38 static struct clocksource clocksource_uv = {
42 .mask = (cycle_t)UVH_RTC_REAL_TIME_CLOCK_MASK,
43 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
46 static struct clock_event_device clock_event_device_uv = {
48 .features = CLOCK_EVT_FEAT_ONESHOT,
52 .set_next_event = uv_rtc_next_event,
53 .set_mode = uv_rtc_timer_setup,
54 .event_handler = NULL,
57 static DEFINE_PER_CPU(struct clock_event_device, cpu_ced);
59 /* There is one of these allocated per node */
60 struct uv_rtc_timer_head {
62 /* next cpu waiting for timer, local node relative: */
64 /* number of cpus on this node: */
67 int lcpu; /* systemwide logical cpu number */
68 u64 expires; /* next timer expiration for this cpu */
73 * Access to uv_rtc_timer_head via blade id.
75 static struct uv_rtc_timer_head **blade_info __read_mostly;
77 static int uv_rtc_evt_enable;
80 * Hardware interface routines
83 /* Send IPIs to another node */
84 static void uv_rtc_send_IPI(int cpu)
86 unsigned long apicid, val;
89 apicid = cpu_physical_id(cpu);
90 pnode = uv_apicid_to_pnode(apicid);
91 apicid |= uv_apicid_hibits;
92 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
93 (apicid << UVH_IPI_INT_APIC_ID_SHFT) |
94 (X86_PLATFORM_IPI_VECTOR << UVH_IPI_INT_VECTOR_SHFT);
96 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
99 /* Check for an RTC interrupt pending */
100 static int uv_intr_pending(int pnode)
102 return uv_read_global_mmr64(pnode, UVH_EVENT_OCCURRED0) &
103 UVH_EVENT_OCCURRED0_RTC1_MASK;
106 /* Setup interrupt and return non-zero if early expiration occurred. */
107 static int uv_setup_intr(int cpu, u64 expires)
110 unsigned long apicid = cpu_physical_id(cpu) | uv_apicid_hibits;
111 int pnode = uv_cpu_to_pnode(cpu);
113 uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG,
114 UVH_RTC1_INT_CONFIG_M_MASK);
115 uv_write_global_mmr64(pnode, UVH_INT_CMPB, -1L);
117 uv_write_global_mmr64(pnode, UVH_EVENT_OCCURRED0_ALIAS,
118 UVH_EVENT_OCCURRED0_RTC1_MASK);
120 val = (X86_PLATFORM_IPI_VECTOR << UVH_RTC1_INT_CONFIG_VECTOR_SHFT) |
121 ((u64)apicid << UVH_RTC1_INT_CONFIG_APIC_ID_SHFT);
123 /* Set configuration */
124 uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, val);
125 /* Initialize comparator value */
126 uv_write_global_mmr64(pnode, UVH_INT_CMPB, expires);
128 if (uv_read_rtc(NULL) <= expires)
131 return !uv_intr_pending(pnode);
135 * Per-cpu timer tracking routines
138 static __init void uv_rtc_deallocate_timers(void)
142 for_each_possible_blade(bid) {
143 kfree(blade_info[bid]);
148 /* Allocate per-node list of cpu timer expiration times. */
149 static __init int uv_rtc_allocate_timers(void)
153 blade_info = kmalloc(uv_possible_blades * sizeof(void *), GFP_KERNEL);
156 memset(blade_info, 0, uv_possible_blades * sizeof(void *));
158 for_each_present_cpu(cpu) {
159 int nid = cpu_to_node(cpu);
160 int bid = uv_cpu_to_blade_id(cpu);
161 int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
162 struct uv_rtc_timer_head *head = blade_info[bid];
165 head = kmalloc_node(sizeof(struct uv_rtc_timer_head) +
166 (uv_blade_nr_possible_cpus(bid) *
170 uv_rtc_deallocate_timers();
173 spin_lock_init(&head->lock);
174 head->ncpus = uv_blade_nr_possible_cpus(bid);
176 blade_info[bid] = head;
179 head->cpu[bcpu].lcpu = cpu;
180 head->cpu[bcpu].expires = ULLONG_MAX;
186 /* Find and set the next expiring timer. */
187 static void uv_rtc_find_next_timer(struct uv_rtc_timer_head *head, int pnode)
189 u64 lowest = ULLONG_MAX;
193 for (c = 0; c < head->ncpus; c++) {
194 u64 exp = head->cpu[c].expires;
201 head->next_cpu = bcpu;
202 c = head->cpu[bcpu].lcpu;
203 if (uv_setup_intr(c, lowest))
204 /* If we didn't set it up in time, trigger */
207 uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG,
208 UVH_RTC1_INT_CONFIG_M_MASK);
213 * Set expiration time for current cpu.
215 * Returns 1 if we missed the expiration time.
217 static int uv_rtc_set_timer(int cpu, u64 expires)
219 int pnode = uv_cpu_to_pnode(cpu);
220 int bid = uv_cpu_to_blade_id(cpu);
221 struct uv_rtc_timer_head *head = blade_info[bid];
222 int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
223 u64 *t = &head->cpu[bcpu].expires;
227 spin_lock_irqsave(&head->lock, flags);
229 next_cpu = head->next_cpu;
232 /* Will this one be next to go off? */
233 if (next_cpu < 0 || bcpu == next_cpu ||
234 expires < head->cpu[next_cpu].expires) {
235 head->next_cpu = bcpu;
236 if (uv_setup_intr(cpu, expires)) {
238 uv_rtc_find_next_timer(head, pnode);
239 spin_unlock_irqrestore(&head->lock, flags);
244 spin_unlock_irqrestore(&head->lock, flags);
249 * Unset expiration time for current cpu.
251 * Returns 1 if this timer was pending.
253 static int uv_rtc_unset_timer(int cpu, int force)
255 int pnode = uv_cpu_to_pnode(cpu);
256 int bid = uv_cpu_to_blade_id(cpu);
257 struct uv_rtc_timer_head *head = blade_info[bid];
258 int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
259 u64 *t = &head->cpu[bcpu].expires;
263 spin_lock_irqsave(&head->lock, flags);
265 if ((head->next_cpu == bcpu && uv_read_rtc(NULL) >= *t) || force)
270 /* Was the hardware setup for this timer? */
271 if (head->next_cpu == bcpu)
272 uv_rtc_find_next_timer(head, pnode);
275 spin_unlock_irqrestore(&head->lock, flags);
282 * Kernel interface routines.
288 * Starting with HUB rev 2.0, the UV RTC register is replicated across all
289 * cachelines of it's own page. This allows faster simultaneous reads
290 * from a given socket.
292 static cycle_t uv_read_rtc(struct clocksource *cs)
294 unsigned long offset;
296 if (uv_get_min_hub_revision_id() == 1)
299 offset = (uv_blade_processor_id() * L1_CACHE_BYTES) % PAGE_SIZE;
301 return (cycle_t)uv_read_local_mmr(UVH_RTC | offset);
305 * Program the next event, relative to now
307 static int uv_rtc_next_event(unsigned long delta,
308 struct clock_event_device *ced)
310 int ced_cpu = cpumask_first(ced->cpumask);
312 return uv_rtc_set_timer(ced_cpu, delta + uv_read_rtc(NULL));
316 * Setup the RTC timer in oneshot mode
318 static void uv_rtc_timer_setup(enum clock_event_mode mode,
319 struct clock_event_device *evt)
321 int ced_cpu = cpumask_first(evt->cpumask);
324 case CLOCK_EVT_MODE_PERIODIC:
325 case CLOCK_EVT_MODE_ONESHOT:
326 case CLOCK_EVT_MODE_RESUME:
327 /* Nothing to do here yet */
329 case CLOCK_EVT_MODE_UNUSED:
330 case CLOCK_EVT_MODE_SHUTDOWN:
331 uv_rtc_unset_timer(ced_cpu, 1);
336 static void uv_rtc_interrupt(void)
338 int cpu = smp_processor_id();
339 struct clock_event_device *ced = &per_cpu(cpu_ced, cpu);
341 if (!ced || !ced->event_handler)
344 if (uv_rtc_unset_timer(cpu, 0) != 1)
347 ced->event_handler(ced);
350 static int __init uv_enable_evt_rtc(char *str)
352 uv_rtc_evt_enable = 1;
356 __setup("uvrtcevt", uv_enable_evt_rtc);
358 static __init void uv_rtc_register_clockevents(struct work_struct *dummy)
360 struct clock_event_device *ced = &__get_cpu_var(cpu_ced);
362 *ced = clock_event_device_uv;
363 ced->cpumask = cpumask_of(smp_processor_id());
364 clockevents_register_device(ced);
367 static __init int uv_rtc_setup_clock(void)
374 /* If single blade, prefer tsc */
375 if (uv_num_possible_blades() == 1)
376 clocksource_uv.rating = 250;
378 rc = clocksource_register_hz(&clocksource_uv, sn_rtc_cycles_per_second);
380 printk(KERN_INFO "UV RTC clocksource failed rc %d\n", rc);
382 printk(KERN_INFO "UV RTC clocksource registered freq %lu MHz\n",
383 sn_rtc_cycles_per_second/(unsigned long)1E6);
385 if (rc || !uv_rtc_evt_enable || x86_platform_ipi_callback)
388 /* Setup and register clockevents */
389 rc = uv_rtc_allocate_timers();
393 x86_platform_ipi_callback = uv_rtc_interrupt;
395 clock_event_device_uv.mult = div_sc(sn_rtc_cycles_per_second,
396 NSEC_PER_SEC, clock_event_device_uv.shift);
398 clock_event_device_uv.min_delta_ns = NSEC_PER_SEC /
399 sn_rtc_cycles_per_second;
401 clock_event_device_uv.max_delta_ns = clocksource_uv.mask *
402 (NSEC_PER_SEC / sn_rtc_cycles_per_second);
404 rc = schedule_on_each_cpu(uv_rtc_register_clockevents);
406 x86_platform_ipi_callback = NULL;
407 uv_rtc_deallocate_timers();
411 printk(KERN_INFO "UV RTC clockevents registered\n");
416 clocksource_unregister(&clocksource_uv);
417 printk(KERN_INFO "UV RTC clockevents failed rc %d\n", rc);
421 arch_initcall(uv_rtc_setup_clock);