2 * mrst.c: Intel Moorestown platform specific setup code
4 * (C) Copyright 2008 Intel Corporation
5 * Author: Jacob Pan (jacob.jun.pan@intel.com)
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 #define pr_fmt(fmt) "mrst: " fmt
15 #include <linux/init.h>
16 #include <linux/kernel.h>
17 #include <linux/sfi.h>
18 #include <linux/intel_pmic_gpio.h>
19 #include <linux/spi/spi.h>
20 #include <linux/i2c.h>
21 #include <linux/i2c/pca953x.h>
22 #include <linux/gpio_keys.h>
23 #include <linux/input.h>
24 #include <linux/platform_device.h>
25 #include <linux/irq.h>
26 #include <linux/module.h>
28 #include <asm/setup.h>
29 #include <asm/mpspec_def.h>
30 #include <asm/hw_irq.h>
32 #include <asm/io_apic.h>
35 #include <asm/i8259.h>
36 #include <asm/intel_scu_ipc.h>
37 #include <asm/apb_timer.h>
38 #include <asm/reboot.h>
41 * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
42 * cmdline option x86_mrst_timer can be used to override the configuration
43 * to prefer one or the other.
44 * at runtime, there are basically three timer configurations:
45 * 1. per cpu apbt clock only
46 * 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only
47 * 3. per cpu lapic clock (C3STOP) and one apbt clock, with broadcast.
49 * by default (without cmdline option), platform code first detects cpu type
50 * to see if we are on lincroft or penwell, then set up both lapic or apbt
52 * i.e. by default, medfield uses configuration #2, moorestown uses #1.
53 * config #3 is supported but not recommended on medfield.
55 * rating and feature summary:
56 * lapic (with C3STOP) --------- 100
57 * apbt (always-on) ------------ 110
58 * lapic (always-on,ARAT) ------ 150
61 __cpuinitdata enum mrst_timer_options mrst_timer_options;
63 static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];
64 static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];
65 enum mrst_cpu_type __mrst_cpu_chip;
66 EXPORT_SYMBOL_GPL(__mrst_cpu_chip);
70 struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX];
71 EXPORT_SYMBOL_GPL(sfi_mrtc_array);
74 static inline void assign_to_mp_irq(struct mpc_intsrc *m,
75 struct mpc_intsrc *mp_irq)
77 memcpy(mp_irq, m, sizeof(struct mpc_intsrc));
80 static inline int mp_irq_cmp(struct mpc_intsrc *mp_irq,
83 return memcmp(mp_irq, m, sizeof(struct mpc_intsrc));
86 static void save_mp_irq(struct mpc_intsrc *m)
90 for (i = 0; i < mp_irq_entries; i++) {
91 if (!mp_irq_cmp(&mp_irqs[i], m))
95 assign_to_mp_irq(m, &mp_irqs[mp_irq_entries]);
96 if (++mp_irq_entries == MAX_IRQ_SOURCES)
97 panic("Max # of irq sources exceeded!!\n");
100 /* parse all the mtimer info to a static mtimer array */
101 static int __init sfi_parse_mtmr(struct sfi_table_header *table)
103 struct sfi_table_simple *sb;
104 struct sfi_timer_table_entry *pentry;
105 struct mpc_intsrc mp_irq;
108 sb = (struct sfi_table_simple *)table;
109 if (!sfi_mtimer_num) {
110 sfi_mtimer_num = SFI_GET_NUM_ENTRIES(sb,
111 struct sfi_timer_table_entry);
112 pentry = (struct sfi_timer_table_entry *) sb->pentry;
113 totallen = sfi_mtimer_num * sizeof(*pentry);
114 memcpy(sfi_mtimer_array, pentry, totallen);
117 pr_debug("SFI MTIMER info (num = %d):\n", sfi_mtimer_num);
118 pentry = sfi_mtimer_array;
119 for (totallen = 0; totallen < sfi_mtimer_num; totallen++, pentry++) {
120 pr_debug("timer[%d]: paddr = 0x%08x, freq = %dHz,"
121 " irq = %d\n", totallen, (u32)pentry->phys_addr,
122 pentry->freq_hz, pentry->irq);
125 mp_irq.type = MP_IOAPIC;
126 mp_irq.irqtype = mp_INT;
127 /* triggering mode edge bit 2-3, active high polarity bit 0-1 */
130 mp_irq.srcbusirq = pentry->irq; /* IRQ */
131 mp_irq.dstapic = MP_APIC_ALL;
132 mp_irq.dstirq = pentry->irq;
133 save_mp_irq(&mp_irq);
139 struct sfi_timer_table_entry *sfi_get_mtmr(int hint)
142 if (hint < sfi_mtimer_num) {
143 if (!sfi_mtimer_usage[hint]) {
144 pr_debug("hint taken for timer %d irq %d\n",\
145 hint, sfi_mtimer_array[hint].irq);
146 sfi_mtimer_usage[hint] = 1;
147 return &sfi_mtimer_array[hint];
150 /* take the first timer available */
151 for (i = 0; i < sfi_mtimer_num;) {
152 if (!sfi_mtimer_usage[i]) {
153 sfi_mtimer_usage[i] = 1;
154 return &sfi_mtimer_array[i];
161 void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr)
164 for (i = 0; i < sfi_mtimer_num;) {
165 if (mtmr->irq == sfi_mtimer_array[i].irq) {
166 sfi_mtimer_usage[i] = 0;
173 /* parse all the mrtc info to a global mrtc array */
174 int __init sfi_parse_mrtc(struct sfi_table_header *table)
176 struct sfi_table_simple *sb;
177 struct sfi_rtc_table_entry *pentry;
178 struct mpc_intsrc mp_irq;
182 sb = (struct sfi_table_simple *)table;
184 sfi_mrtc_num = SFI_GET_NUM_ENTRIES(sb,
185 struct sfi_rtc_table_entry);
186 pentry = (struct sfi_rtc_table_entry *)sb->pentry;
187 totallen = sfi_mrtc_num * sizeof(*pentry);
188 memcpy(sfi_mrtc_array, pentry, totallen);
191 pr_debug("SFI RTC info (num = %d):\n", sfi_mrtc_num);
192 pentry = sfi_mrtc_array;
193 for (totallen = 0; totallen < sfi_mrtc_num; totallen++, pentry++) {
194 pr_debug("RTC[%d]: paddr = 0x%08x, irq = %d\n",
195 totallen, (u32)pentry->phys_addr, pentry->irq);
196 mp_irq.type = MP_IOAPIC;
197 mp_irq.irqtype = mp_INT;
198 mp_irq.irqflag = 0xf; /* level trigger and active low */
200 mp_irq.srcbusirq = pentry->irq; /* IRQ */
201 mp_irq.dstapic = MP_APIC_ALL;
202 mp_irq.dstirq = pentry->irq;
203 save_mp_irq(&mp_irq);
208 static unsigned long __init mrst_calibrate_tsc(void)
210 unsigned long flags, fast_calibrate;
212 local_irq_save(flags);
213 fast_calibrate = apbt_quick_calibrate();
214 local_irq_restore(flags);
217 return fast_calibrate;
222 void __init mrst_time_init(void)
224 sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
225 switch (mrst_timer_options) {
226 case MRST_TIMER_APBT_ONLY:
228 case MRST_TIMER_LAPIC_APBT:
229 x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
230 x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
233 if (!boot_cpu_has(X86_FEATURE_ARAT))
235 x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
236 x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
239 /* we need at least one APB timer */
240 pre_init_apic_IRQ0();
244 void __cpuinit mrst_arch_setup(void)
246 if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27)
247 __mrst_cpu_chip = MRST_CPU_CHIP_PENWELL;
248 else if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x26)
249 __mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
251 pr_err("Unknown Moorestown CPU (%d:%d), default to Lincroft\n",
252 boot_cpu_data.x86, boot_cpu_data.x86_model);
253 __mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
255 pr_debug("Moorestown CPU %s identified\n",
256 (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT) ?
257 "Lincroft" : "Penwell");
260 /* MID systems don't have i8042 controller */
261 static int mrst_i8042_detect(void)
266 /* Reboot and power off are handled by the SCU on a MID device */
267 static void mrst_power_off(void)
269 intel_scu_ipc_simple_command(0xf1, 1);
272 static void mrst_reboot(void)
274 intel_scu_ipc_simple_command(0xf1, 0);
278 * Moorestown specific x86_init function overrides and early setup
281 void __init x86_mrst_early_setup(void)
283 x86_init.resources.probe_roms = x86_init_noop;
284 x86_init.resources.reserve_resources = x86_init_noop;
286 x86_init.timers.timer_init = mrst_time_init;
287 x86_init.timers.setup_percpu_clockev = x86_init_noop;
289 x86_init.irqs.pre_vector_init = x86_init_noop;
291 x86_init.oem.arch_setup = mrst_arch_setup;
293 x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock;
295 x86_platform.calibrate_tsc = mrst_calibrate_tsc;
296 x86_platform.i8042_detect = mrst_i8042_detect;
297 x86_init.pci.init = pci_mrst_init;
298 x86_init.pci.fixup_irqs = x86_init_noop;
300 legacy_pic = &null_legacy_pic;
302 /* Moorestown specific power_off/restart method */
303 pm_power_off = mrst_power_off;
304 machine_ops.emergency_restart = mrst_reboot;
306 /* Avoid searching for BIOS MP tables */
307 x86_init.mpparse.find_smp_config = x86_init_noop;
308 x86_init.mpparse.get_smp_config = x86_init_uint_noop;
313 * if user does not want to use per CPU apb timer, just give it a lower rating
314 * than local apic timer and skip the late per cpu timer init.
316 static inline int __init setup_x86_mrst_timer(char *arg)
321 if (strcmp("apbt_only", arg) == 0)
322 mrst_timer_options = MRST_TIMER_APBT_ONLY;
323 else if (strcmp("lapic_and_apbt", arg) == 0)
324 mrst_timer_options = MRST_TIMER_LAPIC_APBT;
326 pr_warning("X86 MRST timer option %s not recognised"
327 " use x86_mrst_timer=apbt_only or lapic_and_apbt\n",
333 __setup("x86_mrst_timer=", setup_x86_mrst_timer);
336 * Parsing GPIO table first, since the DEVS table will need this table
337 * to map the pin name to the actual pin.
339 static struct sfi_gpio_table_entry *gpio_table;
340 static int gpio_num_entry;
342 static int __init sfi_parse_gpio(struct sfi_table_header *table)
344 struct sfi_table_simple *sb;
345 struct sfi_gpio_table_entry *pentry;
350 sb = (struct sfi_table_simple *)table;
351 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_gpio_table_entry);
352 pentry = (struct sfi_gpio_table_entry *)sb->pentry;
354 gpio_table = (struct sfi_gpio_table_entry *)
355 kmalloc(num * sizeof(*pentry), GFP_KERNEL);
358 memcpy(gpio_table, pentry, num * sizeof(*pentry));
359 gpio_num_entry = num;
361 pr_debug("GPIO pin info:\n");
362 for (i = 0; i < num; i++, pentry++)
363 pr_debug("info[%2d]: controller = %16.16s, pin_name = %16.16s,"
365 pentry->controller_name,
371 static int get_gpio_by_name(const char *name)
373 struct sfi_gpio_table_entry *pentry = gpio_table;
378 for (i = 0; i < gpio_num_entry; i++, pentry++) {
379 if (!strncmp(name, pentry->pin_name, SFI_NAME_LEN))
380 return pentry->pin_no;
386 * Here defines the array of devices platform data that IAFW would export
387 * through SFI "DEVS" table, we use name and type to match the device and
391 char name[SFI_NAME_LEN + 1];
394 void *(*get_platform_data)(void *info);
397 /* the offset for the mapping of global gpio pin to irq */
398 #define MRST_IRQ_OFFSET 0x100
400 static void __init *pmic_gpio_platform_data(void *info)
402 static struct intel_pmic_gpio_platform_data pmic_gpio_pdata;
403 int gpio_base = get_gpio_by_name("pmic_gpio_base");
407 pmic_gpio_pdata.gpio_base = gpio_base;
408 pmic_gpio_pdata.irq_base = gpio_base + MRST_IRQ_OFFSET;
409 pmic_gpio_pdata.gpiointr = 0xffffeff8;
411 return &pmic_gpio_pdata;
414 static void __init *max3111_platform_data(void *info)
416 struct spi_board_info *spi_info = info;
417 int intr = get_gpio_by_name("max3111_int");
421 spi_info->irq = intr + MRST_IRQ_OFFSET;
425 /* we have multiple max7315 on the board ... */
426 #define MAX7315_NUM 2
427 static void __init *max7315_platform_data(void *info)
429 static struct pca953x_platform_data max7315_pdata[MAX7315_NUM];
431 struct pca953x_platform_data *max7315 = &max7315_pdata[nr];
432 struct i2c_board_info *i2c_info = info;
434 char base_pin_name[SFI_NAME_LEN + 1];
435 char intr_pin_name[SFI_NAME_LEN + 1];
437 if (nr == MAX7315_NUM) {
438 pr_err("too many max7315s, we only support %d\n",
442 /* we have several max7315 on the board, we only need load several
443 * instances of the same pca953x driver to cover them
445 strcpy(i2c_info->type, "max7315");
447 sprintf(base_pin_name, "max7315_%d_base", nr);
448 sprintf(intr_pin_name, "max7315_%d_int", nr);
450 strcpy(base_pin_name, "max7315_base");
451 strcpy(intr_pin_name, "max7315_int");
454 gpio_base = get_gpio_by_name(base_pin_name);
455 intr = get_gpio_by_name(intr_pin_name);
459 max7315->gpio_base = gpio_base;
461 i2c_info->irq = intr + MRST_IRQ_OFFSET;
462 max7315->irq_base = gpio_base + MRST_IRQ_OFFSET;
465 max7315->irq_base = -1;
470 static void __init *emc1403_platform_data(void *info)
472 static short intr2nd_pdata;
473 struct i2c_board_info *i2c_info = info;
474 int intr = get_gpio_by_name("thermal_int");
475 int intr2nd = get_gpio_by_name("thermal_alert");
477 if (intr == -1 || intr2nd == -1)
480 i2c_info->irq = intr + MRST_IRQ_OFFSET;
481 intr2nd_pdata = intr2nd + MRST_IRQ_OFFSET;
483 return &intr2nd_pdata;
486 static void __init *lis331dl_platform_data(void *info)
488 static short intr2nd_pdata;
489 struct i2c_board_info *i2c_info = info;
490 int intr = get_gpio_by_name("accel_int");
491 int intr2nd = get_gpio_by_name("accel_2");
493 if (intr == -1 || intr2nd == -1)
496 i2c_info->irq = intr + MRST_IRQ_OFFSET;
497 intr2nd_pdata = intr2nd + MRST_IRQ_OFFSET;
499 return &intr2nd_pdata;
502 static void __init *no_platform_data(void *info)
507 static const struct devs_id __initconst device_ids[] = {
508 {"pmic_gpio", SFI_DEV_TYPE_SPI, 1, &pmic_gpio_platform_data},
509 {"spi_max3111", SFI_DEV_TYPE_SPI, 0, &max3111_platform_data},
510 {"i2c_max7315", SFI_DEV_TYPE_I2C, 1, &max7315_platform_data},
511 {"i2c_max7315_2", SFI_DEV_TYPE_I2C, 1, &max7315_platform_data},
512 {"emc1403", SFI_DEV_TYPE_I2C, 1, &emc1403_platform_data},
513 {"i2c_accel", SFI_DEV_TYPE_I2C, 0, &lis331dl_platform_data},
514 {"pmic_audio", SFI_DEV_TYPE_IPC, 1, &no_platform_data},
515 {"msic_audio", SFI_DEV_TYPE_IPC, 1, &no_platform_data},
519 #define MAX_IPCDEVS 24
520 static struct platform_device *ipc_devs[MAX_IPCDEVS];
521 static int ipc_next_dev;
523 #define MAX_SCU_SPI 24
524 static struct spi_board_info *spi_devs[MAX_SCU_SPI];
525 static int spi_next_dev;
527 #define MAX_SCU_I2C 24
528 static struct i2c_board_info *i2c_devs[MAX_SCU_I2C];
529 static int i2c_bus[MAX_SCU_I2C];
530 static int i2c_next_dev;
532 static void __init intel_scu_device_register(struct platform_device *pdev)
534 if(ipc_next_dev == MAX_IPCDEVS)
535 pr_err("too many SCU IPC devices");
537 ipc_devs[ipc_next_dev++] = pdev;
540 static void __init intel_scu_spi_device_register(struct spi_board_info *sdev)
542 struct spi_board_info *new_dev;
544 if (spi_next_dev == MAX_SCU_SPI) {
545 pr_err("too many SCU SPI devices");
549 new_dev = kzalloc(sizeof(*sdev), GFP_KERNEL);
551 pr_err("failed to alloc mem for delayed spi dev %s\n",
555 memcpy(new_dev, sdev, sizeof(*sdev));
557 spi_devs[spi_next_dev++] = new_dev;
560 static void __init intel_scu_i2c_device_register(int bus,
561 struct i2c_board_info *idev)
563 struct i2c_board_info *new_dev;
565 if (i2c_next_dev == MAX_SCU_I2C) {
566 pr_err("too many SCU I2C devices");
570 new_dev = kzalloc(sizeof(*idev), GFP_KERNEL);
572 pr_err("failed to alloc mem for delayed i2c dev %s\n",
576 memcpy(new_dev, idev, sizeof(*idev));
578 i2c_bus[i2c_next_dev] = bus;
579 i2c_devs[i2c_next_dev++] = new_dev;
582 /* Called by IPC driver */
583 void intel_scu_devices_create(void)
587 for (i = 0; i < ipc_next_dev; i++)
588 platform_device_add(ipc_devs[i]);
590 for (i = 0; i < spi_next_dev; i++)
591 spi_register_board_info(spi_devs[i], 1);
593 for (i = 0; i < i2c_next_dev; i++) {
594 struct i2c_adapter *adapter;
595 struct i2c_client *client;
597 adapter = i2c_get_adapter(i2c_bus[i]);
599 client = i2c_new_device(adapter, i2c_devs[i]);
601 pr_err("can't create i2c device %s\n",
604 i2c_register_board_info(i2c_bus[i], i2c_devs[i], 1);
607 EXPORT_SYMBOL_GPL(intel_scu_devices_create);
609 /* Called by IPC driver */
610 void intel_scu_devices_destroy(void)
614 for (i = 0; i < ipc_next_dev; i++)
615 platform_device_del(ipc_devs[i]);
617 EXPORT_SYMBOL_GPL(intel_scu_devices_destroy);
619 static void __init install_irq_resource(struct platform_device *pdev, int irq)
621 /* Single threaded */
622 static struct resource __initdata res = {
624 .flags = IORESOURCE_IRQ,
627 platform_device_add_resources(pdev, &res, 1);
630 static void __init sfi_handle_ipc_dev(struct platform_device *pdev)
632 const struct devs_id *dev = device_ids;
635 while (dev->name[0]) {
636 if (dev->type == SFI_DEV_TYPE_IPC &&
637 !strncmp(dev->name, pdev->name, SFI_NAME_LEN)) {
638 pdata = dev->get_platform_data(pdev);
643 pdev->dev.platform_data = pdata;
644 intel_scu_device_register(pdev);
647 static void __init sfi_handle_spi_dev(struct spi_board_info *spi_info)
649 const struct devs_id *dev = device_ids;
652 while (dev->name[0]) {
653 if (dev->type == SFI_DEV_TYPE_SPI &&
654 !strncmp(dev->name, spi_info->modalias, SFI_NAME_LEN)) {
655 pdata = dev->get_platform_data(spi_info);
660 spi_info->platform_data = pdata;
662 intel_scu_spi_device_register(spi_info);
664 spi_register_board_info(spi_info, 1);
667 static void __init sfi_handle_i2c_dev(int bus, struct i2c_board_info *i2c_info)
669 const struct devs_id *dev = device_ids;
672 while (dev->name[0]) {
673 if (dev->type == SFI_DEV_TYPE_I2C &&
674 !strncmp(dev->name, i2c_info->type, SFI_NAME_LEN)) {
675 pdata = dev->get_platform_data(i2c_info);
680 i2c_info->platform_data = pdata;
683 intel_scu_i2c_device_register(bus, i2c_info);
685 i2c_register_board_info(bus, i2c_info, 1);
689 static int __init sfi_parse_devs(struct sfi_table_header *table)
691 struct sfi_table_simple *sb;
692 struct sfi_device_table_entry *pentry;
693 struct spi_board_info spi_info;
694 struct i2c_board_info i2c_info;
695 struct platform_device *pdev;
698 struct io_apic_irq_attr irq_attr;
700 sb = (struct sfi_table_simple *)table;
701 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_device_table_entry);
702 pentry = (struct sfi_device_table_entry *)sb->pentry;
704 for (i = 0; i < num; i++, pentry++) {
705 if (pentry->irq != (u8)0xff) { /* native RTE case */
706 /* these SPI2 devices are not exposed to system as PCI
707 * devices, but they have separate RTE entry in IOAPIC
708 * so we have to enable them one by one here
710 ioapic = mp_find_ioapic(pentry->irq);
711 irq_attr.ioapic = ioapic;
712 irq_attr.ioapic_pin = pentry->irq;
713 irq_attr.trigger = 1;
714 irq_attr.polarity = 1;
715 io_apic_set_pci_routing(NULL, pentry->irq, &irq_attr);
717 switch (pentry->type) {
718 case SFI_DEV_TYPE_IPC:
719 /* ID as IRQ is a hack that will go away */
720 pdev = platform_device_alloc(pentry->name, pentry->irq);
722 pr_err("out of memory for SFI platform device '%s'.\n",
726 install_irq_resource(pdev, pentry->irq);
727 pr_debug("info[%2d]: IPC bus, name = %16.16s, "
728 "irq = 0x%2x\n", i, pentry->name, pentry->irq);
729 sfi_handle_ipc_dev(pdev);
731 case SFI_DEV_TYPE_SPI:
732 memset(&spi_info, 0, sizeof(spi_info));
733 strncpy(spi_info.modalias, pentry->name, SFI_NAME_LEN);
734 spi_info.irq = pentry->irq;
735 spi_info.bus_num = pentry->host_num;
736 spi_info.chip_select = pentry->addr;
737 spi_info.max_speed_hz = pentry->max_freq;
738 pr_debug("info[%2d]: SPI bus = %d, name = %16.16s, "
739 "irq = 0x%2x, max_freq = %d, cs = %d\n", i,
743 spi_info.max_speed_hz,
744 spi_info.chip_select);
745 sfi_handle_spi_dev(&spi_info);
747 case SFI_DEV_TYPE_I2C:
748 memset(&i2c_info, 0, sizeof(i2c_info));
749 bus = pentry->host_num;
750 strncpy(i2c_info.type, pentry->name, SFI_NAME_LEN);
751 i2c_info.irq = pentry->irq;
752 i2c_info.addr = pentry->addr;
753 pr_debug("info[%2d]: I2C bus = %d, name = %16.16s, "
754 "irq = 0x%2x, addr = 0x%x\n", i, bus,
758 sfi_handle_i2c_dev(bus, &i2c_info);
760 case SFI_DEV_TYPE_UART:
761 case SFI_DEV_TYPE_HSI:
769 static int __init mrst_platform_init(void)
771 sfi_table_parse(SFI_SIG_GPIO, NULL, NULL, sfi_parse_gpio);
772 sfi_table_parse(SFI_SIG_DEVS, NULL, NULL, sfi_parse_devs);
775 arch_initcall(mrst_platform_init);
778 * we will search these buttons in SFI GPIO table (by name)
779 * and register them dynamically. Please add all possible
780 * buttons here, we will shrink them if no GPIO found.
782 static struct gpio_keys_button gpio_button[] = {
783 {KEY_POWER, -1, 1, "power_btn", EV_KEY, 0, 3000},
784 {KEY_PROG1, -1, 1, "prog_btn1", EV_KEY, 0, 20},
785 {KEY_PROG2, -1, 1, "prog_btn2", EV_KEY, 0, 20},
786 {SW_LID, -1, 1, "lid_switch", EV_SW, 0, 20},
787 {KEY_VOLUMEUP, -1, 1, "vol_up", EV_KEY, 0, 20},
788 {KEY_VOLUMEDOWN, -1, 1, "vol_down", EV_KEY, 0, 20},
789 {KEY_CAMERA, -1, 1, "camera_full", EV_KEY, 0, 20},
790 {KEY_CAMERA_FOCUS, -1, 1, "camera_half", EV_KEY, 0, 20},
791 {SW_KEYPAD_SLIDE, -1, 1, "MagSw1", EV_SW, 0, 20},
792 {SW_KEYPAD_SLIDE, -1, 1, "MagSw2", EV_SW, 0, 20},
795 static struct gpio_keys_platform_data mrst_gpio_keys = {
796 .buttons = gpio_button,
798 .nbuttons = -1, /* will fill it after search */
801 static struct platform_device pb_device = {
805 .platform_data = &mrst_gpio_keys,
810 * Shrink the non-existent buttons, register the gpio button
811 * device if there is some
813 static int __init pb_keys_init(void)
815 struct gpio_keys_button *gb = gpio_button;
816 int i, num, good = 0;
818 num = sizeof(gpio_button) / sizeof(struct gpio_keys_button);
819 for (i = 0; i < num; i++) {
820 gb[i].gpio = get_gpio_by_name(gb[i].desc);
821 if (gb[i].gpio == -1)
830 mrst_gpio_keys.nbuttons = good;
831 return platform_device_register(&pb_device);
835 late_initcall(pb_keys_init);