arch/x86/oprofile/op_model_amd.c

   1 /*
   2  * @file op_model_amd.c
   3  * athlon / K7 / K8 / Family 10h model-specific MSR operations
   4  *
   5  * @remark Copyright 2002-2009 OProfile authors
   6  * @remark Read the file COPYING
   7  *
   8  * @author John Levon
   9  * @author Philippe Elie
  10  * @author Graydon Hoare
  11  * @author Robert Richter <robert.richter@amd.com>
  12  * @author Barry Kasindorf <barry.kasindorf@amd.com>
  13  * @author Jason Yeh <jason.yeh@amd.com>
  14  * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
  15  */
  16
  17 #include <linux/oprofile.h>
  18 #include <linux/device.h>
  19 #include <linux/pci.h>
  20 #include <linux/percpu.h>
  21
  22 #include <asm/ptrace.h>
  23 #include <asm/msr.h>
  24 #include <asm/nmi.h>
  25 #include <asm/apic.h>
  26 #include <asm/processor.h>
  27 #include <asm/cpufeature.h>
  28
  29 #include "op_x86_model.h"
  30 #include "op_counter.h"
  31
  32 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
  33 #define NUM_VIRT_COUNTERS       32
  34 #else
  35 #define NUM_VIRT_COUNTERS       0
  36 #endif
  37
  38 #define OP_EVENT_MASK                   0x0FFF
  39 #define OP_CTR_OVERFLOW                 (1ULL<<31)
  40
  41 #define MSR_AMD_EVENTSEL_RESERVED       ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
  42
  43 static int num_counters;
  44 static unsigned long reset_value[OP_MAX_COUNTER];
  45
  46 #define IBS_FETCH_SIZE                  6
  47 #define IBS_OP_SIZE                     12
  48
  49 static u32 ibs_caps;
  50
  51 struct ibs_config {
  52         unsigned long op_enabled;
  53         unsigned long fetch_enabled;
  54         unsigned long max_cnt_fetch;
  55         unsigned long max_cnt_op;
  56         unsigned long rand_en;
  57         unsigned long dispatched_ops;
  58         unsigned long branch_target;
  59 };
  60
  61 struct ibs_state {
  62         u64             ibs_op_ctl;
  63         int             branch_target;
  64         unsigned long   sample_size;
  65 };
  66
  67 static struct ibs_config ibs_config;
  68 static struct ibs_state ibs_state;
  69
  70 /*
  71  * IBS randomization macros
  72  */
  73 #define IBS_RANDOM_BITS                 12
  74 #define IBS_RANDOM_MASK                 ((1ULL << IBS_RANDOM_BITS) - 1)
  75 #define IBS_RANDOM_MAXCNT_OFFSET        (1ULL << (IBS_RANDOM_BITS - 5))
  76
  77 static u32 get_ibs_caps(void)
  78 {
  79         u32 ibs_caps;
  80         unsigned int max_level;
  81
  82         if (!boot_cpu_has(X86_FEATURE_IBS))
  83                 return 0;
  84
  85         /* check IBS cpuid feature flags */
  86         max_level = cpuid_eax(0x80000000);
  87         if (max_level < IBS_CPUID_FEATURES)
  88                 return IBS_CAPS_DEFAULT;
  89
  90         ibs_caps = cpuid_eax(IBS_CPUID_FEATURES);
  91         if (!(ibs_caps & IBS_CAPS_AVAIL))
  92                 /* cpuid flags not valid */
  93                 return IBS_CAPS_DEFAULT;
  94
  95         return ibs_caps;
  96 }
  97
  98 /*
  99  * 16-bit Linear Feedback Shift Register (LFSR)
 100  *
 101  *                       16   14   13    11
 102  * Feedback polynomial = X  + X  + X  +  X  + 1
 103  */
 104 static unsigned int lfsr_random(void)
 105 {
 106         static unsigned int lfsr_value = 0xF00D;
 107         unsigned int bit;
 108
 109         /* Compute next bit to shift in */
 110         bit = ((lfsr_value >> 0) ^
 111                (lfsr_value >> 2) ^
 112                (lfsr_value >> 3) ^
 113                (lfsr_value >> 5)) & 0x0001;
 114
 115         /* Advance to next register value */
 116         lfsr_value = (lfsr_value >> 1) | (bit << 15);
 117
 118         return lfsr_value;
 119 }
 120
 121 /*
 122  * IBS software randomization
 123  *
 124  * The IBS periodic op counter is randomized in software. The lower 12
 125  * bits of the 20 bit counter are randomized. IbsOpCurCnt is
 126  * initialized with a 12 bit random value.
 127  */
 128 static inline u64 op_amd_randomize_ibs_op(u64 val)
 129 {
 130         unsigned int random = lfsr_random();
 131
 132         if (!(ibs_caps & IBS_CAPS_RDWROPCNT))
 133                 /*
 134                  * Work around if the hw can not write to IbsOpCurCnt
 135                  *
 136                  * Randomize the lower 8 bits of the 16 bit
 137                  * IbsOpMaxCnt [15:0] value in the range of -128 to
 138                  * +127 by adding/subtracting an offset to the
 139                  * maximum count (IbsOpMaxCnt).
 140                  *
 141                  * To avoid over or underflows and protect upper bits
 142                  * starting at bit 16, the initial value for
 143                  * IbsOpMaxCnt must fit in the range from 0x0081 to
 144                  * 0xff80.
 145                  */
 146                 val += (s8)(random >> 4);
 147         else
 148                 val |= (u64)(random & IBS_RANDOM_MASK) << 32;
 149
 150         return val;
 151 }
 152
 153 static inline void
 154 op_amd_handle_ibs(struct pt_regs * const regs,
 155                   struct op_msrs const * const msrs)
 156 {
 157         u64 val, ctl;
 158         struct op_entry entry;
 159
 160         if (!ibs_caps)
 161                 return;
 162
 163         if (ibs_config.fetch_enabled) {
 164                 rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
 165                 if (ctl & IBS_FETCH_VAL) {
 166                         rdmsrl(MSR_AMD64_IBSFETCHLINAD, val);
 167                         oprofile_write_reserve(&entry, regs, val,
 168                                                IBS_FETCH_CODE, IBS_FETCH_SIZE);
 169                         oprofile_add_data64(&entry, val);
 170                         oprofile_add_data64(&entry, ctl);
 171                         rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val);
 172                         oprofile_add_data64(&entry, val);
 173                         oprofile_write_commit(&entry);
 174
 175                         /* reenable the IRQ */
 176                         ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT);
 177                         ctl |= IBS_FETCH_ENABLE;
 178                         wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
 179                 }
 180         }
 181
 182         if (ibs_config.op_enabled) {
 183                 rdmsrl(MSR_AMD64_IBSOPCTL, ctl);
 184                 if (ctl & IBS_OP_VAL) {
 185                         rdmsrl(MSR_AMD64_IBSOPRIP, val);
 186                         oprofile_write_reserve(&entry, regs, val, IBS_OP_CODE,
 187                                                ibs_state.sample_size);
 188                         oprofile_add_data64(&entry, val);
 189                         rdmsrl(MSR_AMD64_IBSOPDATA, val);
 190                         oprofile_add_data64(&entry, val);
 191                         rdmsrl(MSR_AMD64_IBSOPDATA2, val);
 192                         oprofile_add_data64(&entry, val);
 193                         rdmsrl(MSR_AMD64_IBSOPDATA3, val);
 194                         oprofile_add_data64(&entry, val);
 195                         rdmsrl(MSR_AMD64_IBSDCLINAD, val);
 196                         oprofile_add_data64(&entry, val);
 197                         rdmsrl(MSR_AMD64_IBSDCPHYSAD, val);
 198                         oprofile_add_data64(&entry, val);
 199                         if (ibs_state.branch_target) {
 200                                 rdmsrl(MSR_AMD64_IBSBRTARGET, val);
 201                                 oprofile_add_data(&entry, (unsigned long)val);
 202                         }
 203                         oprofile_write_commit(&entry);
 204
 205                         /* reenable the IRQ */
 206                         ctl = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl);
 207                         wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
 208                 }
 209         }
 210 }
 211
 212 static inline void op_amd_start_ibs(void)
 213 {
 214         u64 val;
 215
 216         if (!ibs_caps)
 217                 return;
 218
 219         memset(&ibs_state, 0, sizeof(ibs_state));
 220
 221         /*
 222          * Note: Since the max count settings may out of range we
 223          * write back the actual used values so that userland can read
 224          * it.
 225          */
 226
 227         if (ibs_config.fetch_enabled) {
 228                 val = ibs_config.max_cnt_fetch >> 4;
 229                 val = min(val, IBS_FETCH_MAX_CNT);
 230                 ibs_config.max_cnt_fetch = val << 4;
 231                 val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
 232                 val |= IBS_FETCH_ENABLE;
 233                 wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
 234         }
 235
 236         if (ibs_config.op_enabled) {
 237                 val = ibs_config.max_cnt_op >> 4;
 238                 if (!(ibs_caps & IBS_CAPS_RDWROPCNT)) {
 239                         /*
 240                          * IbsOpCurCnt not supported.  See
 241                          * op_amd_randomize_ibs_op() for details.
 242                          */
 243                         val = clamp(val, 0x0081ULL, 0xFF80ULL);
 244                         ibs_config.max_cnt_op = val << 4;
 245                 } else {
 246                         /*
 247                          * The start value is randomized with a
 248                          * positive offset, we need to compensate it
 249                          * with the half of the randomized range. Also
 250                          * avoid underflows.
 251                          */
 252                         val += IBS_RANDOM_MAXCNT_OFFSET;
 253                         if (ibs_caps & IBS_CAPS_OPCNTEXT)
 254                                 val = min(val, IBS_OP_MAX_CNT_EXT);
 255                         else
 256                                 val = min(val, IBS_OP_MAX_CNT);
 257                         ibs_config.max_cnt_op =
 258                                 (val - IBS_RANDOM_MAXCNT_OFFSET) << 4;
 259                 }
 260                 val = ((val & ~IBS_OP_MAX_CNT) << 4) | (val & IBS_OP_MAX_CNT);
 261                 val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0;
 262                 val |= IBS_OP_ENABLE;
 263                 ibs_state.ibs_op_ctl = val;
 264                 ibs_state.sample_size = IBS_OP_SIZE;
 265                 if (ibs_config.branch_target) {
 266                         ibs_state.branch_target = 1;
 267                         ibs_state.sample_size++;
 268                 }
 269                 val = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl);
 270                 wrmsrl(MSR_AMD64_IBSOPCTL, val);
 271         }
 272 }
 273
 274 static void op_amd_stop_ibs(void)
 275 {
 276         if (!ibs_caps)
 277                 return;
 278
 279         if (ibs_config.fetch_enabled)
 280                 /* clear max count and enable */
 281                 wrmsrl(MSR_AMD64_IBSFETCHCTL, 0);
 282
 283         if (ibs_config.op_enabled)
 284                 /* clear max count and enable */
 285                 wrmsrl(MSR_AMD64_IBSOPCTL, 0);
 286 }
 287
 288 static inline int get_eilvt(int offset)
 289 {
 290         return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1);
 291 }
 292
 293 static inline int put_eilvt(int offset)
 294 {
 295         return !setup_APIC_eilvt(offset, 0, 0, 1);
 296 }
 297
 298 static inline int ibs_eilvt_valid(void)
 299 {
 300         int offset;
 301         u64 val;
 302         int valid = 0;
 303
 304         preempt_disable();
 305
 306         rdmsrl(MSR_AMD64_IBSCTL, val);
 307         offset = val & IBSCTL_LVT_OFFSET_MASK;
 308
 309         if (!(val & IBSCTL_LVT_OFFSET_VALID)) {
 310                 pr_err(FW_BUG "cpu %d, invalid IBS interrupt offset %d (MSR%08X=0x%016llx)\n",
 311                        smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
 312                 goto out;
 313         }
 314
 315         if (!get_eilvt(offset)) {
 316                 pr_err(FW_BUG "cpu %d, IBS interrupt offset %d not available (MSR%08X=0x%016llx)\n",
 317                        smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
 318                 goto out;
 319         }
 320
 321         valid = 1;
 322 out:
 323         preempt_enable();
 324
 325         return valid;
 326 }
 327
 328 static inline int get_ibs_offset(void)
 329 {
 330         u64 val;
 331
 332         rdmsrl(MSR_AMD64_IBSCTL, val);
 333         if (!(val & IBSCTL_LVT_OFFSET_VALID))
 334                 return -EINVAL;
 335
 336         return val & IBSCTL_LVT_OFFSET_MASK;
 337 }
 338
 339 static void setup_APIC_ibs(void)
 340 {
 341         int offset;
 342
 343         offset = get_ibs_offset();
 344         if (offset < 0)
 345                 goto failed;
 346
 347         if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0))
 348                 return;
 349 failed:
 350         pr_warn("oprofile: IBS APIC setup failed on cpu #%d\n",
 351                 smp_processor_id());
 352 }
 353
 354 static void clear_APIC_ibs(void)
 355 {
 356         int offset;
 357
 358         offset = get_ibs_offset();
 359         if (offset >= 0)
 360                 setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1);
 361 }
 362
 363 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 364
 365 static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
 366                                struct op_msrs const * const msrs)
 367 {
 368         u64 val;
 369         int i;
 370
 371         /* enable active counters */
 372         for (i = 0; i < num_counters; ++i) {
 373                 int virt = op_x86_phys_to_virt(i);
 374                 if (!reset_value[virt])
 375                         continue;
 376                 rdmsrl(msrs->controls[i].addr, val);
 377                 val &= model->reserved;
 378                 val |= op_x86_get_ctrl(model, &counter_config[virt]);
 379                 wrmsrl(msrs->controls[i].addr, val);
 380         }
 381 }
 382
 383 #endif
 384
 385 /* functions for op_amd_spec */
 386
 387 static void op_amd_shutdown(struct op_msrs const * const msrs)
 388 {
 389         int i;
 390
 391         for (i = 0; i < num_counters; ++i) {
 392                 if (!msrs->counters[i].addr)
 393                         continue;
 394                 release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
 395                 release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
 396         }
 397 }
 398
 399 static int op_amd_fill_in_addresses(struct op_msrs * const msrs)
 400 {
 401         int i;
 402
 403         for (i = 0; i < num_counters; i++) {
 404                 if (!reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
 405                         goto fail;
 406                 if (!reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) {
 407                         release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
 408                         goto fail;
 409                 }
 410                 /* both registers must be reserved */
 411                 if (num_counters == AMD64_NUM_COUNTERS_F15H) {
 412                         msrs->counters[i].addr = MSR_F15H_PERF_CTR + (i << 1);
 413                         msrs->controls[i].addr = MSR_F15H_PERF_CTL + (i << 1);
 414                 } else {
 415                         msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
 416                         msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
 417                 }
 418                 continue;
 419         fail:
 420                 if (!counter_config[i].enabled)
 421                         continue;
 422                 op_x86_warn_reserved(i);
 423                 op_amd_shutdown(msrs);
 424                 return -EBUSY;
 425         }
 426
 427         return 0;
 428 }
 429
 430 static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
 431                               struct op_msrs const * const msrs)
 432 {
 433         u64 val;
 434         int i;
 435
 436         /* setup reset_value */
 437         for (i = 0; i < OP_MAX_COUNTER; ++i) {
 438                 if (counter_config[i].enabled
 439                     && msrs->counters[op_x86_virt_to_phys(i)].addr)
 440                         reset_value[i] = counter_config[i].count;
 441                 else
 442                         reset_value[i] = 0;
 443         }
 444
 445         /* clear all counters */
 446         for (i = 0; i < num_counters; ++i) {
 447                 if (!msrs->controls[i].addr)
 448                         continue;
 449                 rdmsrl(msrs->controls[i].addr, val);
 450                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
 451                         op_x86_warn_in_use(i);
 452                 val &= model->reserved;
 453                 wrmsrl(msrs->controls[i].addr, val);
 454                 /*
 455                  * avoid a false detection of ctr overflows in NMI
 456                  * handler
 457                  */
 458                 wrmsrl(msrs->counters[i].addr, -1LL);
 459         }
 460
 461         /* enable active counters */
 462         for (i = 0; i < num_counters; ++i) {
 463                 int virt = op_x86_phys_to_virt(i);
 464                 if (!reset_value[virt])
 465                         continue;
 466
 467                 /* setup counter registers */
 468                 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
 469
 470                 /* setup control registers */
 471                 rdmsrl(msrs->controls[i].addr, val);
 472                 val &= model->reserved;
 473                 val |= op_x86_get_ctrl(model, &counter_config[virt]);
 474                 wrmsrl(msrs->controls[i].addr, val);
 475         }
 476
 477         if (ibs_caps)
 478                 setup_APIC_ibs();
 479 }
 480
 481 static void op_amd_cpu_shutdown(void)
 482 {
 483         if (ibs_caps)
 484                 clear_APIC_ibs();
 485 }
 486
 487 static int op_amd_check_ctrs(struct pt_regs * const regs,
 488                              struct op_msrs const * const msrs)
 489 {
 490         u64 val;
 491         int i;
 492
 493         for (i = 0; i < num_counters; ++i) {
 494                 int virt = op_x86_phys_to_virt(i);
 495                 if (!reset_value[virt])
 496                         continue;
 497                 rdmsrl(msrs->counters[i].addr, val);
 498                 /* bit is clear if overflowed: */
 499                 if (val & OP_CTR_OVERFLOW)
 500                         continue;
 501                 oprofile_add_sample(regs, virt);
 502                 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
 503         }
 504
 505         op_amd_handle_ibs(regs, msrs);
 506
 507         /* See op_model_ppro.c */
 508         return 1;
 509 }
 510
 511 static void op_amd_start(struct op_msrs const * const msrs)
 512 {
 513         u64 val;
 514         int i;
 515
 516         for (i = 0; i < num_counters; ++i) {
 517                 if (!reset_value[op_x86_phys_to_virt(i)])
 518                         continue;
 519                 rdmsrl(msrs->controls[i].addr, val);
 520                 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
 521                 wrmsrl(msrs->controls[i].addr, val);
 522         }
 523
 524         op_amd_start_ibs();
 525 }
 526
 527 static void op_amd_stop(struct op_msrs const * const msrs)
 528 {
 529         u64 val;
 530         int i;
 531
 532         /*
 533          * Subtle: stop on all counters to avoid race with setting our
 534          * pm callback
 535          */
 536         for (i = 0; i < num_counters; ++i) {
 537                 if (!reset_value[op_x86_phys_to_virt(i)])
 538                         continue;
 539                 rdmsrl(msrs->controls[i].addr, val);
 540                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 541                 wrmsrl(msrs->controls[i].addr, val);
 542         }
 543
 544         op_amd_stop_ibs();
 545 }
 546
 547 static int setup_ibs_ctl(int ibs_eilvt_off)
 548 {
 549         struct pci_dev *cpu_cfg;
 550         int nodes;
 551         u32 value = 0;
 552
 553         nodes = 0;
 554         cpu_cfg = NULL;
 555         do {
 556                 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
 557                                          PCI_DEVICE_ID_AMD_10H_NB_MISC,
 558                                          cpu_cfg);
 559                 if (!cpu_cfg)
 560                         break;
 561                 ++nodes;
 562                 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
 563                                        | IBSCTL_LVT_OFFSET_VALID);
 564                 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
 565                 if (value != (ibs_eilvt_off | IBSCTL_LVT_OFFSET_VALID)) {
 566                         pci_dev_put(cpu_cfg);
 567                         printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
 568                                "IBSCTL = 0x%08x\n", value);
 569                         return -EINVAL;
 570                 }
 571         } while (1);
 572
 573         if (!nodes) {
 574                 printk(KERN_DEBUG "No CPU node configured for IBS\n");
 575                 return -ENODEV;
 576         }
 577
 578         return 0;
 579 }
 580
 581 /*
 582  * This runs only on the current cpu. We try to find an LVT offset and
 583  * setup the local APIC. For this we must disable preemption. On
 584  * success we initialize all nodes with this offset. This updates then
 585  * the offset in the IBS_CTL per-node msr. The per-core APIC setup of
 586  * the IBS interrupt vector is called from op_amd_setup_ctrs()/op_-
 587  * amd_cpu_shutdown() using the new offset.
 588  */
 589 static int force_ibs_eilvt_setup(void)
 590 {
 591         int offset;
 592         int ret;
 593
 594         preempt_disable();
 595         /* find the next free available EILVT entry, skip offset 0 */
 596         for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) {
 597                 if (get_eilvt(offset))
 598                         break;
 599         }
 600         preempt_enable();
 601
 602         if (offset == APIC_EILVT_NR_MAX) {
 603                 printk(KERN_DEBUG "No EILVT entry available\n");
 604                 return -EBUSY;
 605         }
 606
 607         ret = setup_ibs_ctl(offset);
 608         if (ret)
 609                 goto out;
 610
 611         if (!ibs_eilvt_valid()) {
 612                 ret = -EFAULT;
 613                 goto out;
 614         }
 615
 616         pr_err(FW_BUG "using offset %d for IBS interrupts\n", offset);
 617         pr_err(FW_BUG "workaround enabled for IBS LVT offset\n");
 618
 619         return 0;
 620 out:
 621         preempt_disable();
 622         put_eilvt(offset);
 623         preempt_enable();
 624         return ret;
 625 }
 626
 627 /*
 628  * check and reserve APIC extended interrupt LVT offset for IBS if
 629  * available
 630  */
 631
 632 static void init_ibs(void)
 633 {
 634         ibs_caps = get_ibs_caps();
 635
 636         if (!ibs_caps)
 637                 return;
 638
 639         if (ibs_eilvt_valid())
 640                 goto out;
 641
 642         if (!force_ibs_eilvt_setup())
 643                 goto out;
 644
 645         /* Failed to setup ibs */
 646         ibs_caps = 0;
 647         return;
 648
 649 out:
 650         printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n", ibs_caps);
 651 }
 652
 653 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
 654
 655 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
 656 {
 657         struct dentry *dir;
 658         int ret = 0;
 659
 660         /* architecture specific files */
 661         if (create_arch_files)
 662                 ret = create_arch_files(sb, root);
 663
 664         if (ret)
 665                 return ret;
 666
 667         if (!ibs_caps)
 668                 return ret;
 669
 670         /* model specific files */
 671
 672         /* setup some reasonable defaults */
 673         memset(&ibs_config, 0, sizeof(ibs_config));
 674         ibs_config.max_cnt_fetch = 250000;
 675         ibs_config.max_cnt_op = 250000;
 676
 677         if (ibs_caps & IBS_CAPS_FETCHSAM) {
 678                 dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
 679                 oprofilefs_create_ulong(sb, dir, "enable",
 680                                         &ibs_config.fetch_enabled);
 681                 oprofilefs_create_ulong(sb, dir, "max_count",
 682                                         &ibs_config.max_cnt_fetch);
 683                 oprofilefs_create_ulong(sb, dir, "rand_enable",
 684                                         &ibs_config.rand_en);
 685         }
 686
 687         if (ibs_caps & IBS_CAPS_OPSAM) {
 688                 dir = oprofilefs_mkdir(sb, root, "ibs_op");
 689                 oprofilefs_create_ulong(sb, dir, "enable",
 690                                         &ibs_config.op_enabled);
 691                 oprofilefs_create_ulong(sb, dir, "max_count",
 692                                         &ibs_config.max_cnt_op);
 693                 if (ibs_caps & IBS_CAPS_OPCNT)
 694                         oprofilefs_create_ulong(sb, dir, "dispatched_ops",
 695                                                 &ibs_config.dispatched_ops);
 696                 if (ibs_caps & IBS_CAPS_BRNTRGT)
 697                         oprofilefs_create_ulong(sb, dir, "branch_target",
 698                                                 &ibs_config.branch_target);
 699         }
 700
 701         return 0;
 702 }
 703
 704 struct op_x86_model_spec op_amd_spec;
 705
 706 static int op_amd_init(struct oprofile_operations *ops)
 707 {
 708         init_ibs();
 709         create_arch_files = ops->create_files;
 710         ops->create_files = setup_ibs_files;
 711
 712         if (boot_cpu_data.x86 == 0x15) {
 713                 num_counters = AMD64_NUM_COUNTERS_F15H;
 714         } else {
 715                 num_counters = AMD64_NUM_COUNTERS;
 716         }
 717
 718         op_amd_spec.num_counters = num_counters;
 719         op_amd_spec.num_controls = num_counters;
 720         op_amd_spec.num_virt_counters = max(num_counters, NUM_VIRT_COUNTERS);
 721
 722         return 0;
 723 }
 724
 725 struct op_x86_model_spec op_amd_spec = {
 726         /* num_counters/num_controls filled in at runtime */
 727         .reserved               = MSR_AMD_EVENTSEL_RESERVED,
 728         .event_mask             = OP_EVENT_MASK,
 729         .init                   = op_amd_init,
 730         .fill_in_addresses      = &op_amd_fill_in_addresses,
 731         .setup_ctrs             = &op_amd_setup_ctrs,
 732         .cpu_down               = &op_amd_cpu_shutdown,
 733         .check_ctrs             = &op_amd_check_ctrs,
 734         .start                  = &op_amd_start,
 735         .stop                   = &op_amd_stop,
 736         .shutdown               = &op_amd_shutdown,
 737 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 738         .switch_ctrl            = &op_mux_switch_ctrl,
 739 #endif
 740 };