arch/x86/oprofile/op_model_amd.c

   1 /*
   2  * @file op_model_amd.c
   3  * athlon / K7 / K8 / Family 10h model-specific MSR operations
   4  *
   5  * @remark Copyright 2002-2009 OProfile authors
   6  * @remark Read the file COPYING
   7  *
   8  * @author John Levon
   9  * @author Philippe Elie
  10  * @author Graydon Hoare
  11  * @author Robert Richter <robert.richter@amd.com>
  12  * @author Barry Kasindorf <barry.kasindorf@amd.com>
  13  * @author Jason Yeh <jason.yeh@amd.com>
  14  * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
  15  */
  16
  17 #include <linux/oprofile.h>
  18 #include <linux/device.h>
  19 #include <linux/pci.h>
  20 #include <linux/percpu.h>
  21
  22 #include <asm/ptrace.h>
  23 #include <asm/msr.h>
  24 #include <asm/nmi.h>
  25
  26 #include "op_x86_model.h"
  27 #include "op_counter.h"
  28
  29 #define NUM_COUNTERS 4
  30 #define NUM_CONTROLS 4
  31 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
  32 #define NUM_VIRT_COUNTERS 32
  33 #define NUM_VIRT_CONTROLS 32
  34 #else
  35 #define NUM_VIRT_COUNTERS NUM_COUNTERS
  36 #define NUM_VIRT_CONTROLS NUM_CONTROLS
  37 #endif
  38
  39 #define OP_EVENT_MASK                   0x0FFF
  40 #define OP_CTR_OVERFLOW                 (1ULL<<31)
  41
  42 #define MSR_AMD_EVENTSEL_RESERVED       ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
  43
  44 static unsigned long reset_value[NUM_VIRT_COUNTERS];
  45
  46 #ifdef CONFIG_OPROFILE_IBS
  47
  48 /* IbsFetchCtl bits/masks */
  49 #define IBS_FETCH_RAND_EN               (1ULL<<57)
  50 #define IBS_FETCH_VAL                   (1ULL<<49)
  51 #define IBS_FETCH_ENABLE                (1ULL<<48)
  52 #define IBS_FETCH_CNT_MASK              0xFFFF0000ULL
  53
  54 /*IbsOpCtl bits */
  55 #define IBS_OP_CNT_CTL                  (1ULL<<19)
  56 #define IBS_OP_VAL                      (1ULL<<18)
  57 #define IBS_OP_ENABLE                   (1ULL<<17)
  58
  59 #define IBS_FETCH_SIZE                  6
  60 #define IBS_OP_SIZE                     12
  61
  62 static int has_ibs;     /* AMD Family10h and later */
  63
  64 struct op_ibs_config {
  65         unsigned long op_enabled;
  66         unsigned long fetch_enabled;
  67         unsigned long max_cnt_fetch;
  68         unsigned long max_cnt_op;
  69         unsigned long rand_en;
  70         unsigned long dispatched_ops;
  71 };
  72
  73 static struct op_ibs_config ibs_config;
  74
  75 #endif
  76
  77 /* functions for op_amd_spec */
  78
  79 static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
  80 {
  81         int i;
  82
  83         for (i = 0; i < NUM_COUNTERS; i++) {
  84                 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
  85                         msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
  86                 else
  87                         msrs->counters[i].addr = 0;
  88         }
  89
  90         for (i = 0; i < NUM_CONTROLS; i++) {
  91                 if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
  92                         msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
  93                 else
  94                         msrs->controls[i].addr = 0;
  95         }
  96
  97 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
  98         for (i = 0; i < NUM_VIRT_COUNTERS; i++) {
  99                 int hw_counter = i % NUM_COUNTERS;
 100                 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
 101                         msrs->multiplex[i].addr = MSR_K7_PERFCTR0 + hw_counter;
 102                 else
 103                         msrs->multiplex[i].addr = 0;
 104         }
 105 #endif
 106 }
 107
 108 static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
 109                               struct op_msrs const * const msrs)
 110 {
 111         u64 val;
 112         int i;
 113
 114         /* setup reset_value */
 115         for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
 116                 if (counter_config[i].enabled) {
 117                         reset_value[i] = counter_config[i].count;
 118                 } else {
 119                         reset_value[i] = 0;
 120                 }
 121         }
 122
 123         /* clear all counters */
 124         for (i = 0; i < NUM_CONTROLS; ++i) {
 125                 if (unlikely(!msrs->controls[i].addr))
 126                         continue;
 127                 rdmsrl(msrs->controls[i].addr, val);
 128                 val &= model->reserved;
 129                 wrmsrl(msrs->controls[i].addr, val);
 130         }
 131
 132         /* avoid a false detection of ctr overflows in NMI handler */
 133         for (i = 0; i < NUM_COUNTERS; ++i) {
 134                 if (unlikely(!msrs->counters[i].addr))
 135                         continue;
 136                 wrmsrl(msrs->counters[i].addr, -1LL);
 137         }
 138
 139         /* enable active counters */
 140         for (i = 0; i < NUM_COUNTERS; ++i) {
 141                 int virt = op_x86_phys_to_virt(i);
 142                 if (!counter_config[virt].enabled)
 143                         continue;
 144                 if (!msrs->counters[i].addr)
 145                         continue;
 146
 147                 /* setup counter registers */
 148                 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
 149
 150                 /* setup control registers */
 151                 rdmsrl(msrs->controls[i].addr, val);
 152                 val &= model->reserved;
 153                 val |= op_x86_get_ctrl(model, &counter_config[virt]);
 154                 wrmsrl(msrs->controls[i].addr, val);
 155         }
 156 }
 157
 158
 159 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 160
 161 static void op_amd_switch_ctrl(struct op_x86_model_spec const *model,
 162                                struct op_msrs const * const msrs)
 163 {
 164         u64 val;
 165         int i;
 166
 167         /* enable active counters */
 168         for (i = 0; i < NUM_COUNTERS; ++i) {
 169                 int virt = op_x86_phys_to_virt(i);
 170                 if (!counter_config[virt].enabled)
 171                         continue;
 172                 rdmsrl(msrs->controls[i].addr, val);
 173                 val &= model->reserved;
 174                 val |= op_x86_get_ctrl(model, &counter_config[virt]);
 175                 wrmsrl(msrs->controls[i].addr, val);
 176         }
 177 }
 178
 179 #endif
 180
 181
 182 #ifdef CONFIG_OPROFILE_IBS
 183
 184 static inline int
 185 op_amd_handle_ibs(struct pt_regs * const regs,
 186                   struct op_msrs const * const msrs)
 187 {
 188         u64 val, ctl;
 189         struct op_entry entry;
 190
 191         if (!has_ibs)
 192                 return 0;
 193
 194         if (ibs_config.fetch_enabled) {
 195                 rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
 196                 if (ctl & IBS_FETCH_VAL) {
 197                         rdmsrl(MSR_AMD64_IBSFETCHLINAD, val);
 198                         oprofile_write_reserve(&entry, regs, val,
 199                                                IBS_FETCH_CODE, IBS_FETCH_SIZE);
 200                         oprofile_add_data64(&entry, val);
 201                         oprofile_add_data64(&entry, ctl);
 202                         rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val);
 203                         oprofile_add_data64(&entry, val);
 204                         oprofile_write_commit(&entry);
 205
 206                         /* reenable the IRQ */
 207                         ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT_MASK);
 208                         ctl |= IBS_FETCH_ENABLE;
 209                         wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
 210                 }
 211         }
 212
 213         if (ibs_config.op_enabled) {
 214                 rdmsrl(MSR_AMD64_IBSOPCTL, ctl);
 215                 if (ctl & IBS_OP_VAL) {
 216                         rdmsrl(MSR_AMD64_IBSOPRIP, val);
 217                         oprofile_write_reserve(&entry, regs, val,
 218                                                IBS_OP_CODE, IBS_OP_SIZE);
 219                         oprofile_add_data64(&entry, val);
 220                         rdmsrl(MSR_AMD64_IBSOPDATA, val);
 221                         oprofile_add_data64(&entry, val);
 222                         rdmsrl(MSR_AMD64_IBSOPDATA2, val);
 223                         oprofile_add_data64(&entry, val);
 224                         rdmsrl(MSR_AMD64_IBSOPDATA3, val);
 225                         oprofile_add_data64(&entry, val);
 226                         rdmsrl(MSR_AMD64_IBSDCLINAD, val);
 227                         oprofile_add_data64(&entry, val);
 228                         rdmsrl(MSR_AMD64_IBSDCPHYSAD, val);
 229                         oprofile_add_data64(&entry, val);
 230                         oprofile_write_commit(&entry);
 231
 232                         /* reenable the IRQ */
 233                         ctl &= ~IBS_OP_VAL & 0xFFFFFFFF;
 234                         ctl |= IBS_OP_ENABLE;
 235                         wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
 236                 }
 237         }
 238
 239         return 1;
 240 }
 241
 242 static inline void op_amd_start_ibs(void)
 243 {
 244         u64 val;
 245         if (has_ibs && ibs_config.fetch_enabled) {
 246                 val = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
 247                 val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
 248                 val |= IBS_FETCH_ENABLE;
 249                 wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
 250         }
 251
 252         if (has_ibs && ibs_config.op_enabled) {
 253                 val = (ibs_config.max_cnt_op >> 4) & 0xFFFF;
 254                 val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0;
 255                 val |= IBS_OP_ENABLE;
 256                 wrmsrl(MSR_AMD64_IBSOPCTL, val);
 257         }
 258 }
 259
 260 static void op_amd_stop_ibs(void)
 261 {
 262         if (has_ibs && ibs_config.fetch_enabled)
 263                 /* clear max count and enable */
 264                 wrmsrl(MSR_AMD64_IBSFETCHCTL, 0);
 265
 266         if (has_ibs && ibs_config.op_enabled)
 267                 /* clear max count and enable */
 268                 wrmsrl(MSR_AMD64_IBSOPCTL, 0);
 269 }
 270
 271 #else
 272
 273 static inline int op_amd_handle_ibs(struct pt_regs * const regs,
 274                                     struct op_msrs const * const msrs)
 275 {
 276         return 0;
 277 }
 278 static inline void op_amd_start_ibs(void) { }
 279 static inline void op_amd_stop_ibs(void) { }
 280
 281 #endif
 282
 283 static int op_amd_check_ctrs(struct pt_regs * const regs,
 284                              struct op_msrs const * const msrs)
 285 {
 286         u64 val;
 287         int i;
 288
 289         for (i = 0; i < NUM_COUNTERS; ++i) {
 290                 int virt = op_x86_phys_to_virt(i);
 291                 if (!reset_value[virt])
 292                         continue;
 293                 rdmsrl(msrs->counters[i].addr, val);
 294                 /* bit is clear if overflowed: */
 295                 if (val & OP_CTR_OVERFLOW)
 296                         continue;
 297                 oprofile_add_sample(regs, virt);
 298                 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
 299         }
 300
 301         op_amd_handle_ibs(regs, msrs);
 302
 303         /* See op_model_ppro.c */
 304         return 1;
 305 }
 306
 307 static void op_amd_start(struct op_msrs const * const msrs)
 308 {
 309         u64 val;
 310         int i;
 311
 312         for (i = 0; i < NUM_COUNTERS; ++i) {
 313                 if (!reset_value[op_x86_phys_to_virt(i)])
 314                         continue;
 315                 rdmsrl(msrs->controls[i].addr, val);
 316                 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
 317                 wrmsrl(msrs->controls[i].addr, val);
 318         }
 319
 320         op_amd_start_ibs();
 321 }
 322
 323 static void op_amd_stop(struct op_msrs const * const msrs)
 324 {
 325         u64 val;
 326         int i;
 327
 328         /*
 329          * Subtle: stop on all counters to avoid race with setting our
 330          * pm callback
 331          */
 332         for (i = 0; i < NUM_COUNTERS; ++i) {
 333                 if (!reset_value[op_x86_phys_to_virt(i)])
 334                         continue;
 335                 rdmsrl(msrs->controls[i].addr, val);
 336                 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
 337                 wrmsrl(msrs->controls[i].addr, val);
 338         }
 339
 340         op_amd_stop_ibs();
 341 }
 342
 343 static void op_amd_shutdown(struct op_msrs const * const msrs)
 344 {
 345         int i;
 346
 347         for (i = 0; i < NUM_COUNTERS; ++i) {
 348                 if (msrs->counters[i].addr)
 349                         release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
 350         }
 351         for (i = 0; i < NUM_CONTROLS; ++i) {
 352                 if (msrs->controls[i].addr)
 353                         release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
 354         }
 355 }
 356
 357 #ifdef CONFIG_OPROFILE_IBS
 358
 359 static u8 ibs_eilvt_off;
 360
 361 static inline void apic_init_ibs_nmi_per_cpu(void *arg)
 362 {
 363         ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
 364 }
 365
 366 static inline void apic_clear_ibs_nmi_per_cpu(void *arg)
 367 {
 368         setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
 369 }
 370
 371 static int init_ibs_nmi(void)
 372 {
 373 #define IBSCTL_LVTOFFSETVAL             (1 << 8)
 374 #define IBSCTL                          0x1cc
 375         struct pci_dev *cpu_cfg;
 376         int nodes;
 377         u32 value = 0;
 378
 379         /* per CPU setup */
 380         on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1);
 381
 382         nodes = 0;
 383         cpu_cfg = NULL;
 384         do {
 385                 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
 386                                          PCI_DEVICE_ID_AMD_10H_NB_MISC,
 387                                          cpu_cfg);
 388                 if (!cpu_cfg)
 389                         break;
 390                 ++nodes;
 391                 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
 392                                        | IBSCTL_LVTOFFSETVAL);
 393                 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
 394                 if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
 395                         pci_dev_put(cpu_cfg);
 396                         printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
 397                                 "IBSCTL = 0x%08x", value);
 398                         return 1;
 399                 }
 400         } while (1);
 401
 402         if (!nodes) {
 403                 printk(KERN_DEBUG "No CPU node configured for IBS");
 404                 return 1;
 405         }
 406
 407 #ifdef CONFIG_NUMA
 408         /* Sanity check */
 409         /* Works only for 64bit with proper numa implementation. */
 410         if (nodes != num_possible_nodes()) {
 411                 printk(KERN_DEBUG "Failed to setup CPU node(s) for IBS, "
 412                         "found: %d, expected %d",
 413                         nodes, num_possible_nodes());
 414                 return 1;
 415         }
 416 #endif
 417         return 0;
 418 }
 419
 420 /* uninitialize the APIC for the IBS interrupts if needed */
 421 static void clear_ibs_nmi(void)
 422 {
 423         if (has_ibs)
 424                 on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
 425 }
 426
 427 /* initialize the APIC for the IBS interrupts if available */
 428 static void ibs_init(void)
 429 {
 430         has_ibs = boot_cpu_has(X86_FEATURE_IBS);
 431
 432         if (!has_ibs)
 433                 return;
 434
 435         if (init_ibs_nmi()) {
 436                 has_ibs = 0;
 437                 return;
 438         }
 439
 440         printk(KERN_INFO "oprofile: AMD IBS detected\n");
 441 }
 442
 443 static void ibs_exit(void)
 444 {
 445         if (!has_ibs)
 446                 return;
 447
 448         clear_ibs_nmi();
 449 }
 450
 451 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
 452
 453 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
 454 {
 455         struct dentry *dir;
 456         int ret = 0;
 457
 458         /* architecture specific files */
 459         if (create_arch_files)
 460                 ret = create_arch_files(sb, root);
 461
 462         if (ret)
 463                 return ret;
 464
 465         if (!has_ibs)
 466                 return ret;
 467
 468         /* model specific files */
 469
 470         /* setup some reasonable defaults */
 471         ibs_config.max_cnt_fetch = 250000;
 472         ibs_config.fetch_enabled = 0;
 473         ibs_config.max_cnt_op = 250000;
 474         ibs_config.op_enabled = 0;
 475         ibs_config.dispatched_ops = 1;
 476
 477         dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
 478         oprofilefs_create_ulong(sb, dir, "enable",
 479                                 &ibs_config.fetch_enabled);
 480         oprofilefs_create_ulong(sb, dir, "max_count",
 481                                 &ibs_config.max_cnt_fetch);
 482         oprofilefs_create_ulong(sb, dir, "rand_enable",
 483                                 &ibs_config.rand_en);
 484
 485         dir = oprofilefs_mkdir(sb, root, "ibs_op");
 486         oprofilefs_create_ulong(sb, dir, "enable",
 487                                 &ibs_config.op_enabled);
 488         oprofilefs_create_ulong(sb, dir, "max_count",
 489                                 &ibs_config.max_cnt_op);
 490         oprofilefs_create_ulong(sb, dir, "dispatched_ops",
 491                                 &ibs_config.dispatched_ops);
 492
 493         return 0;
 494 }
 495
 496 static int op_amd_init(struct oprofile_operations *ops)
 497 {
 498         ibs_init();
 499         create_arch_files = ops->create_files;
 500         ops->create_files = setup_ibs_files;
 501         return 0;
 502 }
 503
 504 static void op_amd_exit(void)
 505 {
 506         ibs_exit();
 507 }
 508
 509 #else
 510
 511 /* no IBS support */
 512
 513 static int op_amd_init(struct oprofile_operations *ops)
 514 {
 515         return 0;
 516 }
 517
 518 static void op_amd_exit(void) {}
 519
 520 #endif /* CONFIG_OPROFILE_IBS */
 521
 522 struct op_x86_model_spec const op_amd_spec = {
 523         .num_counters           = NUM_COUNTERS,
 524         .num_controls           = NUM_CONTROLS,
 525         .num_virt_counters      = NUM_VIRT_COUNTERS,
 526         .num_virt_controls      = NUM_VIRT_CONTROLS,
 527         .reserved               = MSR_AMD_EVENTSEL_RESERVED,
 528         .event_mask             = OP_EVENT_MASK,
 529         .init                   = op_amd_init,
 530         .exit                   = op_amd_exit,
 531         .fill_in_addresses      = &op_amd_fill_in_addresses,
 532         .setup_ctrs             = &op_amd_setup_ctrs,
 533         .check_ctrs             = &op_amd_check_ctrs,
 534         .start                  = &op_amd_start,
 535         .stop                   = &op_amd_stop,
 536         .shutdown               = &op_amd_shutdown,
 537 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 538         .switch_ctrl            = &op_amd_switch_ctrl,
 539 #endif
 540 };