arch/x86/oprofile/op_model_amd.c

   1 /*
   2  * @file op_model_amd.c
   3  * athlon / K7 / K8 / Family 10h model-specific MSR operations
   4  *
   5  * @remark Copyright 2002-2009 OProfile authors
   6  * @remark Read the file COPYING
   7  *
   8  * @author John Levon
   9  * @author Philippe Elie
  10  * @author Graydon Hoare
  11  * @author Robert Richter <robert.richter@amd.com>
  12  * @author Barry Kasindorf
  13  */
  14
  15 #include <linux/oprofile.h>
  16 #include <linux/device.h>
  17 #include <linux/pci.h>
  18
  19 #include <asm/ptrace.h>
  20 #include <asm/msr.h>
  21 #include <asm/nmi.h>
  22
  23 #include "op_x86_model.h"
  24 #include "op_counter.h"
  25
  26 #define NUM_COUNTERS 4
  27 #define NUM_CONTROLS 4
  28
  29 #define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0)
  30 #define CTR_READ(l, h, msrs, c) do {rdmsr(msrs->counters[(c)].addr, (l), (h)); } while (0)
  31 #define CTR_WRITE(l, msrs, c) do {wrmsr(msrs->counters[(c)].addr, -(unsigned int)(l), -1); } while (0)
  32 #define CTR_OVERFLOWED(n) (!((n) & (1U<<31)))
  33
  34 #define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0)
  35 #define CTRL_READ(l, h, msrs, c) do {rdmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)
  36 #define CTRL_WRITE(l, h, msrs, c) do {wrmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)
  37 #define CTRL_SET_ACTIVE(n) (n |= (1<<22))
  38 #define CTRL_SET_INACTIVE(n) (n &= ~(1<<22))
  39 #define CTRL_CLEAR_LO(x) (x &= (1<<21))
  40 #define CTRL_CLEAR_HI(x) (x &= 0xfffffcf0)
  41 #define CTRL_SET_ENABLE(val) (val |= 1<<20)
  42 #define CTRL_SET_USR(val, u) (val |= ((u & 1) << 16))
  43 #define CTRL_SET_KERN(val, k) (val |= ((k & 1) << 17))
  44 #define CTRL_SET_UM(val, m) (val |= (m << 8))
  45 #define CTRL_SET_EVENT_LOW(val, e) (val |= (e & 0xff))
  46 #define CTRL_SET_EVENT_HIGH(val, e) (val |= ((e >> 8) & 0xf))
  47 #define CTRL_SET_HOST_ONLY(val, h) (val |= ((h & 1) << 9))
  48 #define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 1) << 8))
  49
  50 static unsigned long reset_value[NUM_COUNTERS];
  51
  52 #ifdef CONFIG_OPROFILE_IBS
  53
  54 /* IbsFetchCtl bits/masks */
  55 #define IBS_FETCH_HIGH_VALID_BIT        (1UL << 17)     /* bit 49 */
  56 #define IBS_FETCH_HIGH_ENABLE           (1UL << 16)     /* bit 48 */
  57 #define IBS_FETCH_LOW_MAX_CNT_MASK      0x0000FFFFUL    /* MaxCnt mask */
  58
  59 /*IbsOpCtl bits */
  60 #define IBS_OP_LOW_VALID_BIT            (1ULL<<18)      /* bit 18 */
  61 #define IBS_OP_LOW_ENABLE               (1ULL<<17)      /* bit 17 */
  62
  63 #define IBS_FETCH_SIZE  6
  64 #define IBS_OP_SIZE     12
  65
  66 static int has_ibs;     /* AMD Family10h and later */
  67
  68 struct op_ibs_config {
  69         unsigned long op_enabled;
  70         unsigned long fetch_enabled;
  71         unsigned long max_cnt_fetch;
  72         unsigned long max_cnt_op;
  73         unsigned long rand_en;
  74         unsigned long dispatched_ops;
  75 };
  76
  77 static struct op_ibs_config ibs_config;
  78
  79 #endif
  80
  81 /* functions for op_amd_spec */
  82
  83 static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
  84 {
  85         int i;
  86
  87         for (i = 0; i < NUM_COUNTERS; i++) {
  88                 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
  89                         msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
  90                 else
  91                         msrs->counters[i].addr = 0;
  92         }
  93
  94         for (i = 0; i < NUM_CONTROLS; i++) {
  95                 if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
  96                         msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
  97                 else
  98                         msrs->controls[i].addr = 0;
  99         }
 100 }
 101
 102
 103 static void op_amd_setup_ctrs(struct op_msrs const * const msrs)
 104 {
 105         unsigned int low, high;
 106         int i;
 107
 108         /* clear all counters */
 109         for (i = 0 ; i < NUM_CONTROLS; ++i) {
 110                 if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
 111                         continue;
 112                 CTRL_READ(low, high, msrs, i);
 113                 CTRL_CLEAR_LO(low);
 114                 CTRL_CLEAR_HI(high);
 115                 CTRL_WRITE(low, high, msrs, i);
 116         }
 117
 118         /* avoid a false detection of ctr overflows in NMI handler */
 119         for (i = 0; i < NUM_COUNTERS; ++i) {
 120                 if (unlikely(!CTR_IS_RESERVED(msrs, i)))
 121                         continue;
 122                 CTR_WRITE(1, msrs, i);
 123         }
 124
 125         /* enable active counters */
 126         for (i = 0; i < NUM_COUNTERS; ++i) {
 127                 if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) {
 128                         reset_value[i] = counter_config[i].count;
 129
 130                         CTR_WRITE(counter_config[i].count, msrs, i);
 131
 132                         CTRL_READ(low, high, msrs, i);
 133                         CTRL_CLEAR_LO(low);
 134                         CTRL_CLEAR_HI(high);
 135                         CTRL_SET_ENABLE(low);
 136                         CTRL_SET_USR(low, counter_config[i].user);
 137                         CTRL_SET_KERN(low, counter_config[i].kernel);
 138                         CTRL_SET_UM(low, counter_config[i].unit_mask);
 139                         CTRL_SET_EVENT_LOW(low, counter_config[i].event);
 140                         CTRL_SET_EVENT_HIGH(high, counter_config[i].event);
 141                         CTRL_SET_HOST_ONLY(high, 0);
 142                         CTRL_SET_GUEST_ONLY(high, 0);
 143
 144                         CTRL_WRITE(low, high, msrs, i);
 145                 } else {
 146                         reset_value[i] = 0;
 147                 }
 148         }
 149 }
 150
 151 #ifdef CONFIG_OPROFILE_IBS
 152
 153 static inline int
 154 op_amd_handle_ibs(struct pt_regs * const regs,
 155                   struct op_msrs const * const msrs)
 156 {
 157         u32 low, high;
 158         u64 msr;
 159         struct op_entry entry;
 160
 161         if (!has_ibs)
 162                 return 1;
 163
 164         if (ibs_config.fetch_enabled) {
 165                 rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
 166                 if (high & IBS_FETCH_HIGH_VALID_BIT) {
 167                         rdmsrl(MSR_AMD64_IBSFETCHLINAD, msr);
 168                         oprofile_write_reserve(&entry, regs, msr,
 169                                                IBS_FETCH_CODE, IBS_FETCH_SIZE);
 170                         oprofile_add_data(&entry, (u32)msr);
 171                         oprofile_add_data(&entry, (u32)(msr >> 32));
 172                         oprofile_add_data(&entry, low);
 173                         oprofile_add_data(&entry, high);
 174                         rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, msr);
 175                         oprofile_add_data(&entry, (u32)msr);
 176                         oprofile_add_data(&entry, (u32)(msr >> 32));
 177                         oprofile_write_commit(&entry);
 178
 179                         /* reenable the IRQ */
 180                         high &= ~IBS_FETCH_HIGH_VALID_BIT;
 181                         high |= IBS_FETCH_HIGH_ENABLE;
 182                         low &= IBS_FETCH_LOW_MAX_CNT_MASK;
 183                         wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
 184                 }
 185         }
 186
 187         if (ibs_config.op_enabled) {
 188                 rdmsr(MSR_AMD64_IBSOPCTL, low, high);
 189                 if (low & IBS_OP_LOW_VALID_BIT) {
 190                         rdmsrl(MSR_AMD64_IBSOPRIP, msr);
 191                         oprofile_write_reserve(&entry, regs, msr,
 192                                                IBS_OP_CODE, IBS_OP_SIZE);
 193                         oprofile_add_data(&entry, (u32)msr);
 194                         oprofile_add_data(&entry, (u32)(msr >> 32));
 195                         rdmsrl(MSR_AMD64_IBSOPDATA, msr);
 196                         oprofile_add_data(&entry, (u32)msr);
 197                         oprofile_add_data(&entry, (u32)(msr >> 32));
 198                         rdmsrl(MSR_AMD64_IBSOPDATA2, msr);
 199                         oprofile_add_data(&entry, (u32)msr);
 200                         oprofile_add_data(&entry, (u32)(msr >> 32));
 201                         rdmsrl(MSR_AMD64_IBSOPDATA3, msr);
 202                         oprofile_add_data(&entry, (u32)msr);
 203                         oprofile_add_data(&entry, (u32)(msr >> 32));
 204                         rdmsrl(MSR_AMD64_IBSDCLINAD, msr);
 205                         oprofile_add_data(&entry, (u32)msr);
 206                         oprofile_add_data(&entry, (u32)(msr >> 32));
 207                         rdmsrl(MSR_AMD64_IBSDCPHYSAD, msr);
 208                         oprofile_add_data(&entry, (u32)msr);
 209                         oprofile_add_data(&entry, (u32)(msr >> 32));
 210                         oprofile_write_commit(&entry);
 211
 212                         /* reenable the IRQ */
 213                         high = 0;
 214                         low &= ~IBS_OP_LOW_VALID_BIT;
 215                         low |= IBS_OP_LOW_ENABLE;
 216                         wrmsr(MSR_AMD64_IBSOPCTL, low, high);
 217                 }
 218         }
 219
 220         return 1;
 221 }
 222
 223 static inline void op_amd_start_ibs(void)
 224 {
 225         unsigned int low, high;
 226         if (has_ibs && ibs_config.fetch_enabled) {
 227                 low = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
 228                 high = ((ibs_config.rand_en & 0x1) << 25) /* bit 57 */
 229                         + IBS_FETCH_HIGH_ENABLE;
 230                 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
 231         }
 232
 233         if (has_ibs && ibs_config.op_enabled) {
 234                 low = ((ibs_config.max_cnt_op >> 4) & 0xFFFF)
 235                         + ((ibs_config.dispatched_ops & 0x1) << 19) /* bit 19 */
 236                         + IBS_OP_LOW_ENABLE;
 237                 high = 0;
 238                 wrmsr(MSR_AMD64_IBSOPCTL, low, high);
 239         }
 240 }
 241
 242 static void op_amd_stop_ibs(void)
 243 {
 244         unsigned int low, high;
 245         if (has_ibs && ibs_config.fetch_enabled) {
 246                 /* clear max count and enable */
 247                 low = 0;
 248                 high = 0;
 249                 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
 250         }
 251
 252         if (has_ibs && ibs_config.op_enabled) {
 253                 /* clear max count and enable */
 254                 low = 0;
 255                 high = 0;
 256                 wrmsr(MSR_AMD64_IBSOPCTL, low, high);
 257         }
 258 }
 259
 260 #else
 261
 262 static inline int op_amd_handle_ibs(struct pt_regs * const regs,
 263                                     struct op_msrs const * const msrs) { }
 264 static inline void op_amd_start_ibs(void) { }
 265 static inline void op_amd_stop_ibs(void) { }
 266
 267 #endif
 268
 269 static int op_amd_check_ctrs(struct pt_regs * const regs,
 270                              struct op_msrs const * const msrs)
 271 {
 272         unsigned int low, high;
 273         int i;
 274
 275         for (i = 0 ; i < NUM_COUNTERS; ++i) {
 276                 if (!reset_value[i])
 277                         continue;
 278                 CTR_READ(low, high, msrs, i);
 279                 if (CTR_OVERFLOWED(low)) {
 280                         oprofile_add_sample(regs, i);
 281                         CTR_WRITE(reset_value[i], msrs, i);
 282                 }
 283         }
 284
 285         op_amd_handle_ibs(regs, msrs);
 286
 287         /* See op_model_ppro.c */
 288         return 1;
 289 }
 290
 291 static void op_amd_start(struct op_msrs const * const msrs)
 292 {
 293         unsigned int low, high;
 294         int i;
 295         for (i = 0 ; i < NUM_COUNTERS ; ++i) {
 296                 if (reset_value[i]) {
 297                         CTRL_READ(low, high, msrs, i);
 298                         CTRL_SET_ACTIVE(low);
 299                         CTRL_WRITE(low, high, msrs, i);
 300                 }
 301         }
 302
 303         op_amd_start_ibs();
 304 }
 305
 306 static void op_amd_stop(struct op_msrs const * const msrs)
 307 {
 308         unsigned int low, high;
 309         int i;
 310
 311         /*
 312          * Subtle: stop on all counters to avoid race with setting our
 313          * pm callback
 314          */
 315         for (i = 0 ; i < NUM_COUNTERS ; ++i) {
 316                 if (!reset_value[i])
 317                         continue;
 318                 CTRL_READ(low, high, msrs, i);
 319                 CTRL_SET_INACTIVE(low);
 320                 CTRL_WRITE(low, high, msrs, i);
 321         }
 322
 323         op_amd_stop_ibs();
 324 }
 325
 326 static void op_amd_shutdown(struct op_msrs const * const msrs)
 327 {
 328         int i;
 329
 330         for (i = 0 ; i < NUM_COUNTERS ; ++i) {
 331                 if (CTR_IS_RESERVED(msrs, i))
 332                         release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
 333         }
 334         for (i = 0 ; i < NUM_CONTROLS ; ++i) {
 335                 if (CTRL_IS_RESERVED(msrs, i))
 336                         release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
 337         }
 338 }
 339
 340 #ifdef CONFIG_OPROFILE_IBS
 341
 342 static u8 ibs_eilvt_off;
 343
 344 static inline void apic_init_ibs_nmi_per_cpu(void *arg)
 345 {
 346         ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
 347 }
 348
 349 static inline void apic_clear_ibs_nmi_per_cpu(void *arg)
 350 {
 351         setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
 352 }
 353
 354 static int init_ibs_nmi(void)
 355 {
 356 #define IBSCTL_LVTOFFSETVAL             (1 << 8)
 357 #define IBSCTL                          0x1cc
 358         struct pci_dev *cpu_cfg;
 359         int nodes;
 360         u32 value = 0;
 361
 362         /* per CPU setup */
 363         on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1);
 364
 365         nodes = 0;
 366         cpu_cfg = NULL;
 367         do {
 368                 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
 369                                          PCI_DEVICE_ID_AMD_10H_NB_MISC,
 370                                          cpu_cfg);
 371                 if (!cpu_cfg)
 372                         break;
 373                 ++nodes;
 374                 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
 375                                        | IBSCTL_LVTOFFSETVAL);
 376                 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
 377                 if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
 378                         pci_dev_put(cpu_cfg);
 379                         printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
 380                                 "IBSCTL = 0x%08x", value);
 381                         return 1;
 382                 }
 383         } while (1);
 384
 385         if (!nodes) {
 386                 printk(KERN_DEBUG "No CPU node configured for IBS");
 387                 return 1;
 388         }
 389
 390 #ifdef CONFIG_NUMA
 391         /* Sanity check */
 392         /* Works only for 64bit with proper numa implementation. */
 393         if (nodes != num_possible_nodes()) {
 394                 printk(KERN_DEBUG "Failed to setup CPU node(s) for IBS, "
 395                         "found: %d, expected %d",
 396                         nodes, num_possible_nodes());
 397                 return 1;
 398         }
 399 #endif
 400         return 0;
 401 }
 402
 403 /* uninitialize the APIC for the IBS interrupts if needed */
 404 static void clear_ibs_nmi(void)
 405 {
 406         if (has_ibs)
 407                 on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
 408 }
 409
 410 /* initialize the APIC for the IBS interrupts if available */
 411 static void ibs_init(void)
 412 {
 413         has_ibs = boot_cpu_has(X86_FEATURE_IBS);
 414
 415         if (!has_ibs)
 416                 return;
 417
 418         if (init_ibs_nmi()) {
 419                 has_ibs = 0;
 420                 return;
 421         }
 422
 423         printk(KERN_INFO "oprofile: AMD IBS detected\n");
 424 }
 425
 426 static void ibs_exit(void)
 427 {
 428         if (!has_ibs)
 429                 return;
 430
 431         clear_ibs_nmi();
 432 }
 433
 434 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
 435
 436 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
 437 {
 438         struct dentry *dir;
 439         int ret = 0;
 440
 441         /* architecture specific files */
 442         if (create_arch_files)
 443                 ret = create_arch_files(sb, root);
 444
 445         if (ret)
 446                 return ret;
 447
 448         if (!has_ibs)
 449                 return ret;
 450
 451         /* model specific files */
 452
 453         /* setup some reasonable defaults */
 454         ibs_config.max_cnt_fetch = 250000;
 455         ibs_config.fetch_enabled = 0;
 456         ibs_config.max_cnt_op = 250000;
 457         ibs_config.op_enabled = 0;
 458         ibs_config.dispatched_ops = 1;
 459
 460         dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
 461         oprofilefs_create_ulong(sb, dir, "enable",
 462                                 &ibs_config.fetch_enabled);
 463         oprofilefs_create_ulong(sb, dir, "max_count",
 464                                 &ibs_config.max_cnt_fetch);
 465         oprofilefs_create_ulong(sb, dir, "rand_enable",
 466                                 &ibs_config.rand_en);
 467
 468         dir = oprofilefs_mkdir(sb, root, "ibs_op");
 469         oprofilefs_create_ulong(sb, dir, "enable",
 470                                 &ibs_config.op_enabled);
 471         oprofilefs_create_ulong(sb, dir, "max_count",
 472                                 &ibs_config.max_cnt_op);
 473         oprofilefs_create_ulong(sb, dir, "dispatched_ops",
 474                                 &ibs_config.dispatched_ops);
 475
 476         return 0;
 477 }
 478
 479 static int op_amd_init(struct oprofile_operations *ops)
 480 {
 481         ibs_init();
 482         create_arch_files = ops->create_files;
 483         ops->create_files = setup_ibs_files;
 484         return 0;
 485 }
 486
 487 static void op_amd_exit(void)
 488 {
 489         ibs_exit();
 490 }
 491
 492 #else
 493
 494 /* no IBS support */
 495
 496 static int op_amd_init(struct oprofile_operations *ops)
 497 {
 498         return 0;
 499 }
 500
 501 static void op_amd_exit(void) {}
 502
 503 #endif /* CONFIG_OPROFILE_IBS */
 504
 505 struct op_x86_model_spec const op_amd_spec = {
 506         .init                   = op_amd_init,
 507         .exit                   = op_amd_exit,
 508         .num_counters           = NUM_COUNTERS,
 509         .num_controls           = NUM_CONTROLS,
 510         .fill_in_addresses      = &op_amd_fill_in_addresses,
 511         .setup_ctrs             = &op_amd_setup_ctrs,
 512         .check_ctrs             = &op_amd_check_ctrs,
 513         .start                  = &op_amd_start,
 514         .stop                   = &op_amd_stop,
 515         .shutdown               = &op_amd_shutdown
 516 };