1 /* -*- mode: c; c-basic-offset: 8 -*- */
3 /* Copyright (C) 1999,2001
5 * Author: J.E.J.Bottomley@HansenPartnership.com
7 * This file provides all the same external entries as smp.c but uses
8 * the voyager hal to provide the functionality
10 #include <linux/cpu.h>
11 #include <linux/module.h>
13 #include <linux/kernel_stat.h>
14 #include <linux/delay.h>
15 #include <linux/mc146818rtc.h>
16 #include <linux/cache.h>
17 #include <linux/interrupt.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/bootmem.h>
21 #include <linux/completion.h>
23 #include <asm/voyager.h>
26 #include <asm/pgalloc.h>
27 #include <asm/tlbflush.h>
28 #include <asm/arch_hooks.h>
29 #include <asm/trampoline.h>
31 /* TLB state -- visible externally, indexed physically */
32 DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate) = { &init_mm, 0 };
34 /* CPU IRQ affinity -- set to all ones initially */
35 static unsigned long cpu_irq_affinity[NR_CPUS] __cacheline_aligned =
36 {[0 ... NR_CPUS-1] = ~0UL };
38 /* per CPU data structure (for /proc/cpuinfo et al), visible externally
39 * indexed physically */
40 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
41 EXPORT_PER_CPU_SYMBOL(cpu_info);
43 /* physical ID of the CPU used to boot the system */
44 unsigned char boot_cpu_id;
46 /* The memory line addresses for the Quad CPIs */
47 struct voyager_qic_cpi *voyager_quad_cpi_addr[NR_CPUS] __cacheline_aligned;
49 /* The masks for the Extended VIC processors, filled in by cat_init */
50 __u32 voyager_extended_vic_processors = 0;
52 /* Masks for the extended Quad processors which cannot be VIC booted */
53 __u32 voyager_allowed_boot_processors = 0;
55 /* The mask for the Quad Processors (both extended and non-extended) */
56 __u32 voyager_quad_processors = 0;
58 /* Total count of live CPUs, used in process.c to display
59 * the CPU information and in irq.c for the per CPU irq
60 * activity count. Finally exported by i386_ksyms.c */
61 static int voyager_extended_cpus = 1;
63 /* Used for the invalidate map that's also checked in the spinlock */
64 static volatile unsigned long smp_invalidate_needed;
66 /* Bitmask of CPUs present in the system - exported by i386_syms.c, used
67 * by scheduler but indexed physically */
68 cpumask_t phys_cpu_present_map = CPU_MASK_NONE;
70 /* The internal functions */
71 static void send_CPI(__u32 cpuset, __u8 cpi);
72 static void ack_CPI(__u8 cpi);
73 static int ack_QIC_CPI(__u8 cpi);
74 static void ack_special_QIC_CPI(__u8 cpi);
75 static void ack_VIC_CPI(__u8 cpi);
76 static void send_CPI_allbutself(__u8 cpi);
77 static void mask_vic_irq(unsigned int irq);
78 static void unmask_vic_irq(unsigned int irq);
79 static unsigned int startup_vic_irq(unsigned int irq);
80 static void enable_local_vic_irq(unsigned int irq);
81 static void disable_local_vic_irq(unsigned int irq);
82 static void before_handle_vic_irq(unsigned int irq);
83 static void after_handle_vic_irq(unsigned int irq);
84 static void set_vic_irq_affinity(unsigned int irq, cpumask_t mask);
85 static void ack_vic_irq(unsigned int irq);
86 static void vic_enable_cpi(void);
87 static void do_boot_cpu(__u8 cpuid);
88 static void do_quad_bootstrap(void);
89 static void initialize_secondary(void);
91 int hard_smp_processor_id(void);
92 int safe_smp_processor_id(void);
94 /* Inline functions */
95 static inline void send_one_QIC_CPI(__u8 cpu, __u8 cpi)
97 voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi =
98 (smp_processor_id() << 16) + cpi;
101 static inline void send_QIC_CPI(__u32 cpuset, __u8 cpi)
105 for_each_online_cpu(cpu) {
106 if (cpuset & (1 << cpu)) {
108 if (!cpu_online(cpu))
109 VDEBUG(("CPU%d sending cpi %d to CPU%d not in "
111 hard_smp_processor_id(), cpi, cpu));
113 send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);
118 static inline void wrapper_smp_local_timer_interrupt(void)
121 smp_local_timer_interrupt();
125 static inline void send_one_CPI(__u8 cpu, __u8 cpi)
127 if (voyager_quad_processors & (1 << cpu))
128 send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);
130 send_CPI(1 << cpu, cpi);
133 static inline void send_CPI_allbutself(__u8 cpi)
135 __u8 cpu = smp_processor_id();
136 __u32 mask = cpus_addr(cpu_online_map)[0] & ~(1 << cpu);
140 static inline int is_cpu_quad(void)
142 __u8 cpumask = inb(VIC_PROC_WHO_AM_I);
143 return ((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER);
146 static inline int is_cpu_extended(void)
148 __u8 cpu = hard_smp_processor_id();
150 return (voyager_extended_vic_processors & (1 << cpu));
153 static inline int is_cpu_vic_boot(void)
155 __u8 cpu = hard_smp_processor_id();
157 return (voyager_extended_vic_processors
158 & voyager_allowed_boot_processors & (1 << cpu));
161 static inline void ack_CPI(__u8 cpi)
164 case VIC_CPU_BOOT_CPI:
165 if (is_cpu_quad() && !is_cpu_vic_boot())
172 /* These are slightly strange. Even on the Quad card,
173 * They are vectored as VIC CPIs */
175 ack_special_QIC_CPI(cpi);
180 printk("VOYAGER ERROR: CPI%d is in common CPI code\n", cpi);
185 /* local variables */
187 /* The VIC IRQ descriptors -- these look almost identical to the
188 * 8259 IRQs except that masks and things must be kept per processor
190 static struct irq_chip vic_chip = {
192 .startup = startup_vic_irq,
193 .mask = mask_vic_irq,
194 .unmask = unmask_vic_irq,
195 .set_affinity = set_vic_irq_affinity,
198 /* used to count up as CPUs are brought on line (starts at 0) */
199 static int cpucount = 0;
201 /* The per cpu profile stuff - used in smp_local_timer_interrupt */
202 static DEFINE_PER_CPU(int, prof_multiplier) = 1;
203 static DEFINE_PER_CPU(int, prof_old_multiplier) = 1;
204 static DEFINE_PER_CPU(int, prof_counter) = 1;
206 /* the map used to check if a CPU has booted */
207 static __u32 cpu_booted_map;
209 /* the synchronize flag used to hold all secondary CPUs spinning in
210 * a tight loop until the boot sequence is ready for them */
211 static cpumask_t smp_commenced_mask = CPU_MASK_NONE;
213 /* This is for the new dynamic CPU boot code */
214 cpumask_t cpu_callin_map = CPU_MASK_NONE;
215 cpumask_t cpu_callout_map = CPU_MASK_NONE;
217 /* The per processor IRQ masks (these are usually kept in sync) */
218 static __u16 vic_irq_mask[NR_CPUS] __cacheline_aligned;
220 /* the list of IRQs to be enabled by the VIC_ENABLE_IRQ_CPI */
221 static __u16 vic_irq_enable_mask[NR_CPUS] __cacheline_aligned = { 0 };
223 /* Lock for enable/disable of VIC interrupts */
224 static __cacheline_aligned DEFINE_SPINLOCK(vic_irq_lock);
226 /* The boot processor is correctly set up in PC mode when it
227 * comes up, but the secondaries need their master/slave 8259
228 * pairs initializing correctly */
230 /* Interrupt counters (per cpu) and total - used to try to
231 * even up the interrupt handling routines */
232 static long vic_intr_total = 0;
233 static long vic_intr_count[NR_CPUS] __cacheline_aligned = { 0 };
234 static unsigned long vic_tick[NR_CPUS] __cacheline_aligned = { 0 };
236 /* Since we can only use CPI0, we fake all the other CPIs */
237 static unsigned long vic_cpi_mailbox[NR_CPUS] __cacheline_aligned;
239 /* debugging routine to read the isr of the cpu's pic */
240 static inline __u16 vic_read_isr(void)
245 isr = inb(0xa0) << 8;
252 static __init void qic_setup(void)
254 if (!is_cpu_quad()) {
255 /* not a quad, no setup */
258 outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);
259 outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);
261 if (is_cpu_extended()) {
262 /* the QIC duplicate of the VIC base register */
263 outb(VIC_DEFAULT_CPI_BASE, QIC_VIC_CPI_BASE_REGISTER);
264 outb(QIC_DEFAULT_CPI_BASE, QIC_CPI_BASE_REGISTER);
266 /* FIXME: should set up the QIC timer and memory parity
267 * error vectors here */
271 static __init void vic_setup_pic(void)
273 outb(1, VIC_REDIRECT_REGISTER_1);
274 /* clear the claim registers for dynamic routing */
275 outb(0, VIC_CLAIM_REGISTER_0);
276 outb(0, VIC_CLAIM_REGISTER_1);
278 outb(0, VIC_PRIORITY_REGISTER);
279 /* Set the Primary and Secondary Microchannel vector
280 * bases to be the same as the ordinary interrupts
282 * FIXME: This would be more efficient using separate
284 outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);
285 outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);
286 /* Now initiallise the master PIC belonging to this CPU by
287 * sending the four ICWs */
289 /* ICW1: level triggered, ICW4 needed */
292 /* ICW2: vector base */
293 outb(FIRST_EXTERNAL_VECTOR, 0x21);
295 /* ICW3: slave at line 2 */
298 /* ICW4: 8086 mode */
301 /* now the same for the slave PIC */
303 /* ICW1: level trigger, ICW4 needed */
306 /* ICW2: slave vector base */
307 outb(FIRST_EXTERNAL_VECTOR + 8, 0xA1);
312 /* ICW4: 8086 mode */
316 static void do_quad_bootstrap(void)
318 if (is_cpu_quad() && is_cpu_vic_boot()) {
321 __u8 cpuid = hard_smp_processor_id();
323 local_irq_save(flags);
325 for (i = 0; i < 4; i++) {
326 /* FIXME: this would be >>3 &0x7 on the 32 way */
327 if (((cpuid >> 2) & 0x03) == i)
328 /* don't lower our own mask! */
331 /* masquerade as local Quad CPU */
332 outb(QIC_CPUID_ENABLE | i, QIC_PROCESSOR_ID);
333 /* enable the startup CPI */
334 outb(QIC_BOOT_CPI_MASK, QIC_MASK_REGISTER1);
336 outb(0, QIC_PROCESSOR_ID);
338 local_irq_restore(flags);
342 void prefill_possible_map(void)
344 /* This is empty on voyager because we need a much
345 * earlier detection which is done in find_smp_config */
348 /* Set up all the basic stuff: read the SMP config and make all the
349 * SMP information reflect only the boot cpu. All others will be
350 * brought on-line later. */
351 void __init find_smp_config(void)
355 boot_cpu_id = hard_smp_processor_id();
357 printk("VOYAGER SMP: Boot cpu is %d\n", boot_cpu_id);
359 /* initialize the CPU structures (moved from smp_boot_cpus) */
360 for (i = 0; i < nr_cpu_ids; i++)
361 cpu_irq_affinity[i] = ~0;
362 cpu_online_map = cpumask_of_cpu(boot_cpu_id);
364 /* The boot CPU must be extended */
365 voyager_extended_vic_processors = 1 << boot_cpu_id;
366 /* initially, all of the first 8 CPUs can boot */
367 voyager_allowed_boot_processors = 0xff;
368 /* set up everything for just this CPU, we can alter
369 * this as we start the other CPUs later */
370 /* now get the CPU disposition from the extended CMOS */
371 cpus_addr(phys_cpu_present_map)[0] =
372 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK);
373 cpus_addr(phys_cpu_present_map)[0] |=
374 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 1) << 8;
375 cpus_addr(phys_cpu_present_map)[0] |=
376 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK +
378 cpus_addr(phys_cpu_present_map)[0] |=
379 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK +
381 cpu_possible_map = phys_cpu_present_map;
382 printk("VOYAGER SMP: phys_cpu_present_map = 0x%lx\n",
383 cpus_addr(phys_cpu_present_map)[0]);
384 /* Here we set up the VIC to enable SMP */
385 /* enable the CPIs by writing the base vector to their register */
386 outb(VIC_DEFAULT_CPI_BASE, VIC_CPI_BASE_REGISTER);
387 outb(1, VIC_REDIRECT_REGISTER_1);
388 /* set the claim registers for static routing --- Boot CPU gets
389 * all interrupts untill all other CPUs started */
390 outb(0xff, VIC_CLAIM_REGISTER_0);
391 outb(0xff, VIC_CLAIM_REGISTER_1);
392 /* Set the Primary and Secondary Microchannel vector
393 * bases to be the same as the ordinary interrupts
395 * FIXME: This would be more efficient using separate
397 outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);
398 outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);
400 /* Finally tell the firmware that we're driving */
401 outb(inb(VOYAGER_SUS_IN_CONTROL_PORT) | VOYAGER_IN_CONTROL_FLAG,
402 VOYAGER_SUS_IN_CONTROL_PORT);
404 current_thread_info()->cpu = boot_cpu_id;
405 percpu_write(cpu_number, boot_cpu_id);
409 * The bootstrap kernel entry code has set these up. Save them
410 * for a given CPU, id is physical */
411 void __init smp_store_cpu_info(int id)
413 struct cpuinfo_x86 *c = &cpu_data(id);
418 identify_secondary_cpu(c);
421 /* Routine initially called when a non-boot CPU is brought online */
422 static void __init start_secondary(void *unused)
424 __u8 cpuid = hard_smp_processor_id();
428 /* OK, we're in the routine */
429 ack_CPI(VIC_CPU_BOOT_CPI);
431 /* setup the 8259 master slave pair belonging to this CPU ---
432 * we won't actually receive any until the boot CPU
433 * relinquishes it's static routing mask */
438 if (is_cpu_quad() && !is_cpu_vic_boot()) {
439 /* clear the boot CPI */
443 voyager_quad_cpi_addr[cpuid]->qic_cpi[VIC_CPU_BOOT_CPI].cpi;
444 printk("read dummy %d\n", dummy);
447 /* lower the mask to receive CPIs */
450 VDEBUG(("VOYAGER SMP: CPU%d, stack at about %p\n", cpuid, &cpuid));
452 notify_cpu_starting(cpuid);
454 /* enable interrupts */
457 /* get our bogomips */
460 /* save our processor parameters */
461 smp_store_cpu_info(cpuid);
463 /* if we're a quad, we may need to bootstrap other CPUs */
466 /* FIXME: this is rather a poor hack to prevent the CPU
467 * activating softirqs while it's supposed to be waiting for
468 * permission to proceed. Without this, the new per CPU stuff
469 * in the softirqs will fail */
471 cpu_set(cpuid, cpu_callin_map);
473 /* signal that we're done */
476 while (!cpu_isset(cpuid, smp_commenced_mask))
482 cpu_set(cpuid, cpu_online_map);
487 /* Routine to kick start the given CPU and wait for it to report ready
488 * (or timeout in startup). When this routine returns, the requested
489 * CPU is either fully running and configured or known to be dead.
491 * We call this routine sequentially 1 CPU at a time, so no need for
494 static void __init do_boot_cpu(__u8 cpu)
496 struct task_struct *idle;
499 int quad_boot = (1 << cpu) & voyager_quad_processors
500 & ~(voyager_extended_vic_processors
501 & voyager_allowed_boot_processors);
503 /* This is the format of the CPI IDT gate (in real mode) which
504 * we're hijacking to boot the CPU */
513 __u32 *hijack_vector;
514 __u32 start_phys_address = setup_trampoline();
516 /* There's a clever trick to this: The linux trampoline is
517 * compiled to begin at absolute location zero, so make the
518 * address zero but have the data segment selector compensate
519 * for the actual address */
520 hijack_source.idt.Offset = start_phys_address & 0x000F;
521 hijack_source.idt.Segment = (start_phys_address >> 4) & 0xFFFF;
524 alternatives_smp_switch(1);
526 idle = fork_idle(cpu);
528 panic("failed fork for CPU%d", cpu);
529 idle->thread.ip = (unsigned long)start_secondary;
530 /* init_tasks (in sched.c) is indexed logically */
531 stack_start.sp = (void *)idle->thread.sp;
533 per_cpu(current_task, cpu) = idle;
534 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
537 /* Note: Don't modify initial ss override */
538 VDEBUG(("VOYAGER SMP: Booting CPU%d at 0x%lx[%x:%x], stack %p\n", cpu,
539 (unsigned long)hijack_source.val, hijack_source.idt.Segment,
540 hijack_source.idt.Offset, stack_start.sp));
542 /* init lowmem identity mapping */
543 clone_pgd_range(swapper_pg_dir, swapper_pg_dir + KERNEL_PGD_BOUNDARY,
544 min_t(unsigned long, KERNEL_PGD_PTRS, KERNEL_PGD_BOUNDARY));
548 printk("CPU %d: non extended Quad boot\n", cpu);
551 phys_to_virt((VIC_CPU_BOOT_CPI + QIC_DEFAULT_CPI_BASE) * 4);
552 *hijack_vector = hijack_source.val;
554 printk("CPU%d: extended VIC boot\n", cpu);
557 phys_to_virt((VIC_CPU_BOOT_CPI + VIC_DEFAULT_CPI_BASE) * 4);
558 *hijack_vector = hijack_source.val;
559 /* VIC errata, may also receive interrupt at this address */
562 phys_to_virt((VIC_CPU_BOOT_ERRATA_CPI +
563 VIC_DEFAULT_CPI_BASE) * 4);
564 *hijack_vector = hijack_source.val;
566 /* All non-boot CPUs start with interrupts fully masked. Need
567 * to lower the mask of the CPI we're about to send. We do
568 * this in the VIC by masquerading as the processor we're
569 * about to boot and lowering its interrupt mask */
570 local_irq_save(flags);
572 send_one_QIC_CPI(cpu, VIC_CPU_BOOT_CPI);
574 outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID);
575 /* here we're altering registers belonging to `cpu' */
577 outb(VIC_BOOT_INTERRUPT_MASK, 0x21);
578 /* now go back to our original identity */
579 outb(boot_cpu_id, VIC_PROCESSOR_ID);
581 /* and boot the CPU */
583 send_CPI((1 << cpu), VIC_CPU_BOOT_CPI);
586 local_irq_restore(flags);
588 /* now wait for it to become ready (or timeout) */
589 for (timeout = 0; timeout < 50000; timeout++) {
594 /* reset the page table */
597 if (cpu_booted_map) {
598 VDEBUG(("CPU%d: Booted successfully, back in CPU %d\n",
599 cpu, smp_processor_id()));
601 printk("CPU%d: ", cpu);
602 print_cpu_info(&cpu_data(cpu));
604 cpu_set(cpu, cpu_callout_map);
605 cpu_set(cpu, cpu_present_map);
607 printk("CPU%d FAILED TO BOOT: ", cpu);
609 ((volatile unsigned char *)phys_to_virt(start_phys_address))
613 printk("Not responding.\n");
619 void __init smp_boot_cpus(void)
623 /* CAT BUS initialisation must be done after the memory */
624 /* FIXME: The L4 has a catbus too, it just needs to be
625 * accessed in a totally different way */
626 if (voyager_level == 5) {
629 /* now that the cat has probed the Voyager System Bus, sanity
630 * check the cpu map */
631 if (((voyager_quad_processors | voyager_extended_vic_processors)
632 & cpus_addr(phys_cpu_present_map)[0]) !=
633 cpus_addr(phys_cpu_present_map)[0]) {
635 printk("\n\n***WARNING*** "
636 "Sanity check of CPU present map FAILED\n");
638 } else if (voyager_level == 4)
639 voyager_extended_vic_processors =
640 cpus_addr(phys_cpu_present_map)[0];
642 /* this sets up the idle task to run on the current cpu */
643 voyager_extended_cpus = 1;
644 /* Remove the global_irq_holder setting, it triggers a BUG() on
645 * schedule at the moment */
646 //global_irq_holder = boot_cpu_id;
648 /* FIXME: Need to do something about this but currently only works
649 * on CPUs with a tsc which none of mine have.
650 smp_tune_scheduling();
652 smp_store_cpu_info(boot_cpu_id);
653 /* setup the jump vector */
654 initial_code = (unsigned long)initialize_secondary;
655 printk("CPU%d: ", boot_cpu_id);
656 print_cpu_info(&cpu_data(boot_cpu_id));
659 /* booting on a Quad CPU */
660 printk("VOYAGER SMP: Boot CPU is Quad\n");
665 /* enable our own CPIs */
668 cpu_set(boot_cpu_id, cpu_online_map);
669 cpu_set(boot_cpu_id, cpu_callout_map);
671 /* loop over all the extended VIC CPUs and boot them. The
672 * Quad CPUs must be bootstrapped by their extended VIC cpu */
673 for (i = 0; i < nr_cpu_ids; i++) {
674 if (i == boot_cpu_id || !cpu_isset(i, phys_cpu_present_map))
677 /* This udelay seems to be needed for the Quad boots
678 * don't remove unless you know what you're doing */
681 /* we could compute the total bogomips here, but why bother?,
682 * Code added from smpboot.c */
684 unsigned long bogosum = 0;
686 for_each_online_cpu(i)
687 bogosum += cpu_data(i).loops_per_jiffy;
688 printk(KERN_INFO "Total of %d processors activated "
689 "(%lu.%02lu BogoMIPS).\n",
690 cpucount + 1, bogosum / (500000 / HZ),
691 (bogosum / (5000 / HZ)) % 100);
693 voyager_extended_cpus = hweight32(voyager_extended_vic_processors);
694 printk("VOYAGER: Extended (interrupt handling CPUs): "
695 "%d, non-extended: %d\n", voyager_extended_cpus,
696 num_booting_cpus() - voyager_extended_cpus);
697 /* that's it, switch to symmetric mode */
698 outb(0, VIC_PRIORITY_REGISTER);
699 outb(0, VIC_CLAIM_REGISTER_0);
700 outb(0, VIC_CLAIM_REGISTER_1);
702 VDEBUG(("VOYAGER SMP: Booted with %d CPUs\n", num_booting_cpus()));
705 /* Reload the secondary CPUs task structure (this function does not
707 static void __init initialize_secondary(void)
711 set_current(hard_get_current());
715 * We don't actually need to load the full TSS,
716 * basically just the stack pointer and the eip.
719 asm volatile ("movl %0,%%esp\n\t"
720 "jmp *%1"::"r" (current->thread.sp),
721 "r"(current->thread.ip));
724 /* handle a Voyager SYS_INT -- If we don't, the base board will
727 * System interrupts occur because some problem was detected on the
728 * various busses. To find out what you have to probe all the
729 * hardware via the CAT bus. FIXME: At the moment we do nothing. */
730 void smp_vic_sys_interrupt(struct pt_regs *regs)
732 ack_CPI(VIC_SYS_INT);
733 printk("Voyager SYSTEM INTERRUPT\n");
736 /* Handle a voyager CMN_INT; These interrupts occur either because of
737 * a system status change or because a single bit memory error
738 * occurred. FIXME: At the moment, ignore all this. */
739 void smp_vic_cmn_interrupt(struct pt_regs *regs)
741 static __u8 in_cmn_int = 0;
742 static DEFINE_SPINLOCK(cmn_int_lock);
744 /* common ints are broadcast, so make sure we only do this once */
745 _raw_spin_lock(&cmn_int_lock);
750 _raw_spin_unlock(&cmn_int_lock);
752 VDEBUG(("Voyager COMMON INTERRUPT\n"));
754 if (voyager_level == 5)
755 voyager_cat_do_common_interrupt();
757 _raw_spin_lock(&cmn_int_lock);
760 _raw_spin_unlock(&cmn_int_lock);
761 ack_CPI(VIC_CMN_INT);
765 * Reschedule call back. Nothing to do, all the work is done
766 * automatically when we return from the interrupt. */
767 static void smp_reschedule_interrupt(void)
772 static struct mm_struct *flush_mm;
773 static unsigned long flush_va;
774 static DEFINE_SPINLOCK(tlbstate_lock);
777 * We cannot call mmdrop() because we are in interrupt context,
778 * instead update mm->cpu_vm_mask.
780 * We need to reload %cr3 since the page tables may be going
781 * away from under us..
783 static inline void voyager_leave_mm(unsigned long cpu)
785 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK)
787 cpu_clear(cpu, per_cpu(cpu_tlbstate, cpu).active_mm->cpu_vm_mask);
788 load_cr3(swapper_pg_dir);
792 * Invalidate call-back
794 static void smp_invalidate_interrupt(void)
796 __u8 cpu = smp_processor_id();
798 if (!test_bit(cpu, &smp_invalidate_needed))
800 /* This will flood messages. Don't uncomment unless you see
801 * Problems with cross cpu invalidation
802 VDEBUG(("VOYAGER SMP: CPU%d received INVALIDATE_CPI\n",
803 smp_processor_id()));
806 if (flush_mm == per_cpu(cpu_tlbstate, cpu).active_mm) {
807 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) {
808 if (flush_va == TLB_FLUSH_ALL)
811 __flush_tlb_one(flush_va);
813 voyager_leave_mm(cpu);
815 smp_mb__before_clear_bit();
816 clear_bit(cpu, &smp_invalidate_needed);
817 smp_mb__after_clear_bit();
820 /* All the new flush operations for 2.4 */
822 /* This routine is called with a physical cpu mask */
824 voyager_flush_tlb_others(unsigned long cpumask, struct mm_struct *mm,
831 if ((cpumask & cpus_addr(cpu_online_map)[0]) != cpumask)
833 if (cpumask & (1 << smp_processor_id()))
838 spin_lock(&tlbstate_lock);
842 atomic_set_mask(cpumask, &smp_invalidate_needed);
844 * We have to send the CPI only to
847 send_CPI(cpumask, VIC_INVALIDATE_CPI);
849 while (smp_invalidate_needed) {
852 printk("***WARNING*** Stuck doing invalidate CPI "
853 "(CPU%d)\n", smp_processor_id());
858 /* Uncomment only to debug invalidation problems
859 VDEBUG(("VOYAGER SMP: Completed invalidate CPI (CPU%d)\n", cpu));
864 spin_unlock(&tlbstate_lock);
867 void flush_tlb_current_task(void)
869 struct mm_struct *mm = current->mm;
870 unsigned long cpu_mask;
874 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
877 voyager_flush_tlb_others(cpu_mask, mm, TLB_FLUSH_ALL);
882 void flush_tlb_mm(struct mm_struct *mm)
884 unsigned long cpu_mask;
888 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
890 if (current->active_mm == mm) {
894 voyager_leave_mm(smp_processor_id());
897 voyager_flush_tlb_others(cpu_mask, mm, TLB_FLUSH_ALL);
902 void flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
904 struct mm_struct *mm = vma->vm_mm;
905 unsigned long cpu_mask;
909 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
910 if (current->active_mm == mm) {
914 voyager_leave_mm(smp_processor_id());
918 voyager_flush_tlb_others(cpu_mask, mm, va);
923 EXPORT_SYMBOL(flush_tlb_page);
925 /* enable the requested IRQs */
926 static void smp_enable_irq_interrupt(void)
929 __u8 cpu = get_cpu();
931 VDEBUG(("VOYAGER SMP: CPU%d enabling irq mask 0x%x\n", cpu,
932 vic_irq_enable_mask[cpu]));
934 spin_lock(&vic_irq_lock);
935 for (irq = 0; irq < 16; irq++) {
936 if (vic_irq_enable_mask[cpu] & (1 << irq))
937 enable_local_vic_irq(irq);
939 vic_irq_enable_mask[cpu] = 0;
940 spin_unlock(&vic_irq_lock);
942 put_cpu_no_resched();
948 static void smp_stop_cpu_function(void *dummy)
950 VDEBUG(("VOYAGER SMP: CPU%d is STOPPING\n", smp_processor_id()));
951 cpu_clear(smp_processor_id(), cpu_online_map);
957 /* execute a thread on a new CPU. The function to be called must be
958 * previously set up. This is used to schedule a function for
959 * execution on all CPUs - set up the function then broadcast a
960 * function_interrupt CPI to come here on each CPU */
961 static void smp_call_function_interrupt(void)
964 generic_smp_call_function_interrupt();
965 __get_cpu_var(irq_stat).irq_call_count++;
969 static void smp_call_function_single_interrupt(void)
972 generic_smp_call_function_single_interrupt();
973 __get_cpu_var(irq_stat).irq_call_count++;
977 /* Sorry about the name. In an APIC based system, the APICs
978 * themselves are programmed to send a timer interrupt. This is used
979 * by linux to reschedule the processor. Voyager doesn't have this,
980 * so we use the system clock to interrupt one processor, which in
981 * turn, broadcasts a timer CPI to all the others --- we receive that
982 * CPI here. We don't use this actually for counting so losing
983 * ticks doesn't matter
985 * FIXME: For those CPUs which actually have a local APIC, we could
986 * try to use it to trigger this interrupt instead of having to
987 * broadcast the timer tick. Unfortunately, all my pentium DYADs have
988 * no local APIC, so I can't do this
990 * This function is currently a placeholder and is unused in the code */
991 void smp_apic_timer_interrupt(struct pt_regs *regs)
993 struct pt_regs *old_regs = set_irq_regs(regs);
994 wrapper_smp_local_timer_interrupt();
995 set_irq_regs(old_regs);
998 /* All of the QUAD interrupt GATES */
999 void smp_qic_timer_interrupt(struct pt_regs *regs)
1001 struct pt_regs *old_regs = set_irq_regs(regs);
1002 ack_QIC_CPI(QIC_TIMER_CPI);
1003 wrapper_smp_local_timer_interrupt();
1004 set_irq_regs(old_regs);
1007 void smp_qic_invalidate_interrupt(struct pt_regs *regs)
1009 ack_QIC_CPI(QIC_INVALIDATE_CPI);
1010 smp_invalidate_interrupt();
1013 void smp_qic_reschedule_interrupt(struct pt_regs *regs)
1015 ack_QIC_CPI(QIC_RESCHEDULE_CPI);
1016 smp_reschedule_interrupt();
1019 void smp_qic_enable_irq_interrupt(struct pt_regs *regs)
1021 ack_QIC_CPI(QIC_ENABLE_IRQ_CPI);
1022 smp_enable_irq_interrupt();
1025 void smp_qic_call_function_interrupt(struct pt_regs *regs)
1027 ack_QIC_CPI(QIC_CALL_FUNCTION_CPI);
1028 smp_call_function_interrupt();
1031 void smp_qic_call_function_single_interrupt(struct pt_regs *regs)
1033 ack_QIC_CPI(QIC_CALL_FUNCTION_SINGLE_CPI);
1034 smp_call_function_single_interrupt();
1037 void smp_vic_cpi_interrupt(struct pt_regs *regs)
1039 struct pt_regs *old_regs = set_irq_regs(regs);
1040 __u8 cpu = smp_processor_id();
1043 ack_QIC_CPI(VIC_CPI_LEVEL0);
1045 ack_VIC_CPI(VIC_CPI_LEVEL0);
1047 if (test_and_clear_bit(VIC_TIMER_CPI, &vic_cpi_mailbox[cpu]))
1048 wrapper_smp_local_timer_interrupt();
1049 if (test_and_clear_bit(VIC_INVALIDATE_CPI, &vic_cpi_mailbox[cpu]))
1050 smp_invalidate_interrupt();
1051 if (test_and_clear_bit(VIC_RESCHEDULE_CPI, &vic_cpi_mailbox[cpu]))
1052 smp_reschedule_interrupt();
1053 if (test_and_clear_bit(VIC_ENABLE_IRQ_CPI, &vic_cpi_mailbox[cpu]))
1054 smp_enable_irq_interrupt();
1055 if (test_and_clear_bit(VIC_CALL_FUNCTION_CPI, &vic_cpi_mailbox[cpu]))
1056 smp_call_function_interrupt();
1057 if (test_and_clear_bit(VIC_CALL_FUNCTION_SINGLE_CPI, &vic_cpi_mailbox[cpu]))
1058 smp_call_function_single_interrupt();
1059 set_irq_regs(old_regs);
1062 static void do_flush_tlb_all(void *info)
1064 unsigned long cpu = smp_processor_id();
1067 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_LAZY)
1068 voyager_leave_mm(cpu);
1071 /* flush the TLB of every active CPU in the system */
1072 void flush_tlb_all(void)
1074 on_each_cpu(do_flush_tlb_all, 0, 1);
1077 /* send a reschedule CPI to one CPU by physical CPU number*/
1078 static void voyager_smp_send_reschedule(int cpu)
1080 send_one_CPI(cpu, VIC_RESCHEDULE_CPI);
1083 int hard_smp_processor_id(void)
1086 __u8 cpumask = inb(VIC_PROC_WHO_AM_I);
1087 if ((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER)
1088 return cpumask & 0x1F;
1090 for (i = 0; i < 8; i++) {
1091 if (cpumask & (1 << i))
1094 printk("** WARNING ** Illegal cpuid returned by VIC: %d", cpumask);
1098 int safe_smp_processor_id(void)
1100 return hard_smp_processor_id();
1103 /* broadcast a halt to all other CPUs */
1104 static void voyager_smp_send_stop(void)
1106 smp_call_function(smp_stop_cpu_function, NULL, 1);
1109 /* this function is triggered in time.c when a clock tick fires
1110 * we need to re-broadcast the tick to all CPUs */
1111 void smp_vic_timer_interrupt(void)
1113 send_CPI_allbutself(VIC_TIMER_CPI);
1114 smp_local_timer_interrupt();
1117 /* local (per CPU) timer interrupt. It does both profiling and
1118 * process statistics/rescheduling.
1120 * We do profiling in every local tick, statistics/rescheduling
1121 * happen only every 'profiling multiplier' ticks. The default
1122 * multiplier is 1 and it can be changed by writing the new multiplier
1123 * value into /proc/profile.
1125 void smp_local_timer_interrupt(void)
1127 int cpu = smp_processor_id();
1130 profile_tick(CPU_PROFILING);
1131 if (--per_cpu(prof_counter, cpu) <= 0) {
1133 * The multiplier may have changed since the last time we got
1134 * to this point as a result of the user writing to
1135 * /proc/profile. In this case we need to adjust the APIC
1136 * timer accordingly.
1138 * Interrupts are already masked off at this point.
1140 per_cpu(prof_counter, cpu) = per_cpu(prof_multiplier, cpu);
1141 if (per_cpu(prof_counter, cpu) !=
1142 per_cpu(prof_old_multiplier, cpu)) {
1143 /* FIXME: need to update the vic timer tick here */
1144 per_cpu(prof_old_multiplier, cpu) =
1145 per_cpu(prof_counter, cpu);
1148 update_process_times(user_mode_vm(get_irq_regs()));
1151 if (((1 << cpu) & voyager_extended_vic_processors) == 0)
1152 /* only extended VIC processors participate in
1153 * interrupt distribution */
1157 * We take the 'long' return path, and there every subsystem
1158 * grabs the appropriate locks (kernel lock/ irq lock).
1160 * we might want to decouple profiling from the 'long path',
1161 * and do the profiling totally in assembly.
1163 * Currently this isn't too much of an issue (performance wise),
1164 * we can take more than 100K local irqs per second on a 100 MHz P5.
1167 if ((++vic_tick[cpu] & 0x7) != 0)
1169 /* get here every 16 ticks (about every 1/6 of a second) */
1171 /* Change our priority to give someone else a chance at getting
1172 * the IRQ. The algorithm goes like this:
1174 * In the VIC, the dynamically routed interrupt is always
1175 * handled by the lowest priority eligible (i.e. receiving
1176 * interrupts) CPU. If >1 eligible CPUs are equal lowest, the
1177 * lowest processor number gets it.
1179 * The priority of a CPU is controlled by a special per-CPU
1180 * VIC priority register which is 3 bits wide 0 being lowest
1181 * and 7 highest priority..
1183 * Therefore we subtract the average number of interrupts from
1184 * the number we've fielded. If this number is negative, we
1185 * lower the activity count and if it is positive, we raise
1188 * I'm afraid this still leads to odd looking interrupt counts:
1189 * the totals are all roughly equal, but the individual ones
1190 * look rather skewed.
1192 * FIXME: This algorithm is total crap when mixed with SMP
1193 * affinity code since we now try to even up the interrupt
1194 * counts when an affinity binding is keeping them on a
1196 weight = (vic_intr_count[cpu] * voyager_extended_cpus
1197 - vic_intr_total) >> 4;
1204 outb((__u8) weight, VIC_PRIORITY_REGISTER);
1206 #ifdef VOYAGER_DEBUG
1207 if ((vic_tick[cpu] & 0xFFF) == 0) {
1208 /* print this message roughly every 25 secs */
1209 printk("VOYAGER SMP: vic_tick[%d] = %lu, weight = %ld\n",
1210 cpu, vic_tick[cpu], weight);
1215 /* setup the profiling timer */
1216 int setup_profiling_timer(unsigned int multiplier)
1224 * Set the new multiplier for each CPU. CPUs don't start using the
1225 * new values until the next timer interrupt in which they do process
1228 for (i = 0; i < nr_cpu_ids; ++i)
1229 per_cpu(prof_multiplier, i) = multiplier;
1234 /* This is a bit of a mess, but forced on us by the genirq changes
1235 * there's no genirq handler that really does what voyager wants
1236 * so hack it up with the simple IRQ handler */
1237 static void handle_vic_irq(unsigned int irq, struct irq_desc *desc)
1239 before_handle_vic_irq(irq);
1240 handle_simple_irq(irq, desc);
1241 after_handle_vic_irq(irq);
1244 /* The CPIs are handled in the per cpu 8259s, so they must be
1245 * enabled to be received: FIX: enabling the CPIs in the early
1246 * boot sequence interferes with bug checking; enable them later
1248 #define VIC_SET_GATE(cpi, vector) \
1249 set_intr_gate((cpi) + VIC_DEFAULT_CPI_BASE, (vector))
1250 #define QIC_SET_GATE(cpi, vector) \
1251 set_intr_gate((cpi) + QIC_DEFAULT_CPI_BASE, (vector))
1253 void __init voyager_smp_intr_init(void)
1257 /* initialize the per cpu irq mask to all disabled */
1258 for (i = 0; i < nr_cpu_ids; i++)
1259 vic_irq_mask[i] = 0xFFFF;
1261 VIC_SET_GATE(VIC_CPI_LEVEL0, vic_cpi_interrupt);
1263 VIC_SET_GATE(VIC_SYS_INT, vic_sys_interrupt);
1264 VIC_SET_GATE(VIC_CMN_INT, vic_cmn_interrupt);
1266 QIC_SET_GATE(QIC_TIMER_CPI, qic_timer_interrupt);
1267 QIC_SET_GATE(QIC_INVALIDATE_CPI, qic_invalidate_interrupt);
1268 QIC_SET_GATE(QIC_RESCHEDULE_CPI, qic_reschedule_interrupt);
1269 QIC_SET_GATE(QIC_ENABLE_IRQ_CPI, qic_enable_irq_interrupt);
1270 QIC_SET_GATE(QIC_CALL_FUNCTION_CPI, qic_call_function_interrupt);
1272 /* now put the VIC descriptor into the first 48 IRQs
1274 * This is for later: first 16 correspond to PC IRQs; next 16
1275 * are Primary MC IRQs and final 16 are Secondary MC IRQs */
1276 for (i = 0; i < 48; i++)
1277 set_irq_chip_and_handler(i, &vic_chip, handle_vic_irq);
1280 /* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per
1281 * processor to receive CPI */
1282 static void send_CPI(__u32 cpuset, __u8 cpi)
1285 __u32 quad_cpuset = (cpuset & voyager_quad_processors);
1287 if (cpi < VIC_START_FAKE_CPI) {
1288 /* fake CPI are only used for booting, so send to the
1289 * extended quads as well---Quads must be VIC booted */
1290 outb((__u8) (cpuset), VIC_CPI_Registers[cpi]);
1294 send_QIC_CPI(quad_cpuset, cpi);
1295 cpuset &= ~quad_cpuset;
1296 cpuset &= 0xff; /* only first 8 CPUs vaild for VIC CPI */
1299 for_each_online_cpu(cpu) {
1300 if (cpuset & (1 << cpu))
1301 set_bit(cpi, &vic_cpi_mailbox[cpu]);
1304 outb((__u8) cpuset, VIC_CPI_Registers[VIC_CPI_LEVEL0]);
1307 /* Acknowledge receipt of CPI in the QIC, clear in QIC hardware and
1308 * set the cache line to shared by reading it.
1310 * DON'T make this inline otherwise the cache line read will be
1313 static int ack_QIC_CPI(__u8 cpi)
1315 __u8 cpu = hard_smp_processor_id();
1319 outb(1 << cpi, QIC_INTERRUPT_CLEAR1);
1320 return voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi;
1323 static void ack_special_QIC_CPI(__u8 cpi)
1327 outb(QIC_CMN_INT, QIC_INTERRUPT_CLEAR0);
1330 outb(QIC_SYS_INT, QIC_INTERRUPT_CLEAR0);
1333 /* also clear at the VIC, just in case (nop for non-extended proc) */
1337 /* Acknowledge receipt of CPI in the VIC (essentially an EOI) */
1338 static void ack_VIC_CPI(__u8 cpi)
1340 #ifdef VOYAGER_DEBUG
1341 unsigned long flags;
1343 __u8 cpu = smp_processor_id();
1345 local_irq_save(flags);
1346 isr = vic_read_isr();
1347 if ((isr & (1 << (cpi & 7))) == 0) {
1348 printk("VOYAGER SMP: CPU%d lost CPI%d\n", cpu, cpi);
1351 /* send specific EOI; the two system interrupts have
1352 * bit 4 set for a separate vector but behave as the
1353 * corresponding 3 bit intr */
1354 outb_p(0x60 | (cpi & 7), 0x20);
1356 #ifdef VOYAGER_DEBUG
1357 if ((vic_read_isr() & (1 << (cpi & 7))) != 0) {
1358 printk("VOYAGER SMP: CPU%d still asserting CPI%d\n", cpu, cpi);
1360 local_irq_restore(flags);
1364 /* cribbed with thanks from irq.c */
1365 #define __byte(x,y) (((unsigned char *)&(y))[x])
1366 #define cached_21(cpu) (__byte(0,vic_irq_mask[cpu]))
1367 #define cached_A1(cpu) (__byte(1,vic_irq_mask[cpu]))
1369 static unsigned int startup_vic_irq(unsigned int irq)
1371 unmask_vic_irq(irq);
1376 /* The enable and disable routines. This is where we run into
1377 * conflicting architectural philosophy. Fundamentally, the voyager
1378 * architecture does not expect to have to disable interrupts globally
1379 * (the IRQ controllers belong to each CPU). The processor masquerade
1380 * which is used to start the system shouldn't be used in a running OS
1381 * since it will cause great confusion if two separate CPUs drive to
1382 * the same IRQ controller (I know, I've tried it).
1384 * The solution is a variant on the NCR lazy SPL design:
1386 * 1) To disable an interrupt, do nothing (other than set the
1387 * IRQ_DISABLED flag). This dares the interrupt actually to arrive.
1389 * 2) If the interrupt dares to come in, raise the local mask against
1390 * it (this will result in all the CPU masks being raised
1393 * 3) To enable the interrupt, lower the mask on the local CPU and
1394 * broadcast an Interrupt enable CPI which causes all other CPUs to
1395 * adjust their masks accordingly. */
1397 static void unmask_vic_irq(unsigned int irq)
1399 /* linux doesn't to processor-irq affinity, so enable on
1400 * all CPUs we know about */
1401 int cpu = smp_processor_id(), real_cpu;
1402 __u16 mask = (1 << irq);
1403 __u32 processorList = 0;
1404 unsigned long flags;
1406 VDEBUG(("VOYAGER: unmask_vic_irq(%d) CPU%d affinity 0x%lx\n",
1407 irq, cpu, cpu_irq_affinity[cpu]));
1408 spin_lock_irqsave(&vic_irq_lock, flags);
1409 for_each_online_cpu(real_cpu) {
1410 if (!(voyager_extended_vic_processors & (1 << real_cpu)))
1412 if (!(cpu_irq_affinity[real_cpu] & mask)) {
1413 /* irq has no affinity for this CPU, ignore */
1416 if (real_cpu == cpu) {
1417 enable_local_vic_irq(irq);
1418 } else if (vic_irq_mask[real_cpu] & mask) {
1419 vic_irq_enable_mask[real_cpu] |= mask;
1420 processorList |= (1 << real_cpu);
1423 spin_unlock_irqrestore(&vic_irq_lock, flags);
1425 send_CPI(processorList, VIC_ENABLE_IRQ_CPI);
1428 static void mask_vic_irq(unsigned int irq)
1430 /* lazy disable, do nothing */
1433 static void enable_local_vic_irq(unsigned int irq)
1435 __u8 cpu = smp_processor_id();
1436 __u16 mask = ~(1 << irq);
1437 __u16 old_mask = vic_irq_mask[cpu];
1439 vic_irq_mask[cpu] &= mask;
1440 if (vic_irq_mask[cpu] == old_mask)
1443 VDEBUG(("VOYAGER DEBUG: Enabling irq %d in hardware on CPU %d\n",
1447 outb_p(cached_A1(cpu), 0xA1);
1450 outb_p(cached_21(cpu), 0x21);
1455 static void disable_local_vic_irq(unsigned int irq)
1457 __u8 cpu = smp_processor_id();
1458 __u16 mask = (1 << irq);
1459 __u16 old_mask = vic_irq_mask[cpu];
1464 vic_irq_mask[cpu] |= mask;
1465 if (old_mask == vic_irq_mask[cpu])
1468 VDEBUG(("VOYAGER DEBUG: Disabling irq %d in hardware on CPU %d\n",
1472 outb_p(cached_A1(cpu), 0xA1);
1475 outb_p(cached_21(cpu), 0x21);
1480 /* The VIC is level triggered, so the ack can only be issued after the
1481 * interrupt completes. However, we do Voyager lazy interrupt
1482 * handling here: It is an extremely expensive operation to mask an
1483 * interrupt in the vic, so we merely set a flag (IRQ_DISABLED). If
1484 * this interrupt actually comes in, then we mask and ack here to push
1485 * the interrupt off to another CPU */
1486 static void before_handle_vic_irq(unsigned int irq)
1488 irq_desc_t *desc = irq_to_desc(irq);
1489 __u8 cpu = smp_processor_id();
1491 _raw_spin_lock(&vic_irq_lock);
1493 vic_intr_count[cpu]++;
1495 if (!(cpu_irq_affinity[cpu] & (1 << irq))) {
1496 /* The irq is not in our affinity mask, push it off
1497 * onto another CPU */
1498 VDEBUG(("VOYAGER DEBUG: affinity triggered disable of irq %d "
1499 "on cpu %d\n", irq, cpu));
1500 disable_local_vic_irq(irq);
1501 /* set IRQ_INPROGRESS to prevent the handler in irq.c from
1502 * actually calling the interrupt routine */
1503 desc->status |= IRQ_REPLAY | IRQ_INPROGRESS;
1504 } else if (desc->status & IRQ_DISABLED) {
1505 /* Damn, the interrupt actually arrived, do the lazy
1506 * disable thing. The interrupt routine in irq.c will
1507 * not handle a IRQ_DISABLED interrupt, so nothing more
1508 * need be done here */
1509 VDEBUG(("VOYAGER DEBUG: lazy disable of irq %d on CPU %d\n",
1511 disable_local_vic_irq(irq);
1512 desc->status |= IRQ_REPLAY;
1514 desc->status &= ~IRQ_REPLAY;
1517 _raw_spin_unlock(&vic_irq_lock);
1520 /* Finish the VIC interrupt: basically mask */
1521 static void after_handle_vic_irq(unsigned int irq)
1523 irq_desc_t *desc = irq_to_desc(irq);
1525 _raw_spin_lock(&vic_irq_lock);
1527 unsigned int status = desc->status & ~IRQ_INPROGRESS;
1528 #ifdef VOYAGER_DEBUG
1532 desc->status = status;
1533 if ((status & IRQ_DISABLED))
1534 disable_local_vic_irq(irq);
1535 #ifdef VOYAGER_DEBUG
1536 /* DEBUG: before we ack, check what's in progress */
1537 isr = vic_read_isr();
1538 if ((isr & (1 << irq) && !(status & IRQ_REPLAY)) == 0) {
1540 __u8 cpu = smp_processor_id();
1542 int mask; /* Um... initialize me??? --RR */
1544 printk("VOYAGER SMP: CPU%d lost interrupt %d\n",
1546 for_each_possible_cpu(real_cpu, mask) {
1548 outb(VIC_CPU_MASQUERADE_ENABLE | real_cpu,
1550 isr = vic_read_isr();
1551 if (isr & (1 << irq)) {
1553 ("VOYAGER SMP: CPU%d ack irq %d\n",
1557 outb(cpu, VIC_PROCESSOR_ID);
1560 #endif /* VOYAGER_DEBUG */
1561 /* as soon as we ack, the interrupt is eligible for
1562 * receipt by another CPU so everything must be in
1565 if (status & IRQ_REPLAY) {
1566 /* replay is set if we disable the interrupt
1567 * in the before_handle_vic_irq() routine, so
1568 * clear the in progress bit here to allow the
1569 * next CPU to handle this correctly */
1570 desc->status &= ~(IRQ_REPLAY | IRQ_INPROGRESS);
1572 #ifdef VOYAGER_DEBUG
1573 isr = vic_read_isr();
1574 if ((isr & (1 << irq)) != 0)
1575 printk("VOYAGER SMP: after_handle_vic_irq() after "
1576 "ack irq=%d, isr=0x%x\n", irq, isr);
1577 #endif /* VOYAGER_DEBUG */
1579 _raw_spin_unlock(&vic_irq_lock);
1581 /* All code after this point is out of the main path - the IRQ
1582 * may be intercepted by another CPU if reasserted */
1585 /* Linux processor - interrupt affinity manipulations.
1587 * For each processor, we maintain a 32 bit irq affinity mask.
1588 * Initially it is set to all 1's so every processor accepts every
1589 * interrupt. In this call, we change the processor's affinity mask:
1591 * Change from enable to disable:
1593 * If the interrupt ever comes in to the processor, we will disable it
1594 * and ack it to push it off to another CPU, so just accept the mask here.
1596 * Change from disable to enable:
1598 * change the mask and then do an interrupt enable CPI to re-enable on
1599 * the selected processors */
1601 void set_vic_irq_affinity(unsigned int irq, cpumask_t mask)
1603 /* Only extended processors handle interrupts */
1604 unsigned long real_mask;
1605 unsigned long irq_mask = 1 << irq;
1608 real_mask = cpus_addr(mask)[0] & voyager_extended_vic_processors;
1610 if (cpus_addr(mask)[0] == 0)
1611 /* can't have no CPUs to accept the interrupt -- extremely
1612 * bad things will happen */
1616 /* can't change the affinity of the timer IRQ. This
1617 * is due to the constraint in the voyager
1618 * architecture that the CPI also comes in on and IRQ
1619 * line and we have chosen IRQ0 for this. If you
1620 * raise the mask on this interrupt, the processor
1621 * will no-longer be able to accept VIC CPIs */
1625 /* You can only have 32 interrupts in a voyager system
1626 * (and 32 only if you have a secondary microchannel
1630 for_each_online_cpu(cpu) {
1631 unsigned long cpu_mask = 1 << cpu;
1633 if (cpu_mask & real_mask) {
1634 /* enable the interrupt for this cpu */
1635 cpu_irq_affinity[cpu] |= irq_mask;
1637 /* disable the interrupt for this cpu */
1638 cpu_irq_affinity[cpu] &= ~irq_mask;
1641 /* this is magic, we now have the correct affinity maps, so
1642 * enable the interrupt. This will send an enable CPI to
1643 * those CPUs who need to enable it in their local masks,
1644 * causing them to correct for the new affinity . If the
1645 * interrupt is currently globally disabled, it will simply be
1646 * disabled again as it comes in (voyager lazy disable). If
1647 * the affinity map is tightened to disable the interrupt on a
1648 * cpu, it will be pushed off when it comes in */
1649 unmask_vic_irq(irq);
1652 static void ack_vic_irq(unsigned int irq)
1655 outb(0x62, 0x20); /* Specific EOI to cascade */
1656 outb(0x60 | (irq & 7), 0xA0);
1658 outb(0x60 | (irq & 7), 0x20);
1662 /* enable the CPIs. In the VIC, the CPIs are delivered by the 8259
1663 * but are not vectored by it. This means that the 8259 mask must be
1664 * lowered to receive them */
1665 static __init void vic_enable_cpi(void)
1667 __u8 cpu = smp_processor_id();
1669 /* just take a copy of the current mask (nop for boot cpu) */
1670 vic_irq_mask[cpu] = vic_irq_mask[boot_cpu_id];
1672 enable_local_vic_irq(VIC_CPI_LEVEL0);
1673 enable_local_vic_irq(VIC_CPI_LEVEL1);
1674 /* for sys int and cmn int */
1675 enable_local_vic_irq(7);
1677 if (is_cpu_quad()) {
1678 outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);
1679 outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);
1680 VDEBUG(("VOYAGER SMP: QIC ENABLE CPI: CPU%d: MASK 0x%x\n",
1681 cpu, QIC_CPI_ENABLE));
1684 VDEBUG(("VOYAGER SMP: ENABLE CPI: CPU%d: MASK 0x%x\n",
1685 cpu, vic_irq_mask[cpu]));
1688 void voyager_smp_dump()
1690 int old_cpu = smp_processor_id(), cpu;
1692 /* dump the interrupt masks of each processor */
1693 for_each_online_cpu(cpu) {
1694 __u16 imr, isr, irr;
1695 unsigned long flags;
1697 local_irq_save(flags);
1698 outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID);
1699 imr = (inb(0xa1) << 8) | inb(0x21);
1701 irr = inb(0xa0) << 8;
1705 isr = inb(0xa0) << 8;
1708 outb(old_cpu, VIC_PROCESSOR_ID);
1709 local_irq_restore(flags);
1710 printk("\tCPU%d: mask=0x%x, IMR=0x%x, IRR=0x%x, ISR=0x%x\n",
1711 cpu, vic_irq_mask[cpu], imr, irr, isr);
1713 /* These lines are put in to try to unstick an un ack'd irq */
1716 for (irq = 0; irq < 16; irq++) {
1717 if (isr & (1 << irq)) {
1718 printk("\tCPU%d: ack irq %d\n",
1720 local_irq_save(flags);
1721 outb(VIC_CPU_MASQUERADE_ENABLE | cpu,
1724 outb(old_cpu, VIC_PROCESSOR_ID);
1725 local_irq_restore(flags);
1733 void smp_voyager_power_off(void *dummy)
1735 if (smp_processor_id() == boot_cpu_id)
1736 voyager_power_off();
1738 smp_stop_cpu_function(NULL);
1741 static void __init voyager_smp_prepare_cpus(unsigned int max_cpus)
1743 /* FIXME: ignore max_cpus for now */
1747 static void __cpuinit voyager_smp_prepare_boot_cpu(void)
1749 int cpu = smp_processor_id();
1750 switch_to_new_gdt(cpu);
1752 cpu_set(cpu, cpu_online_map);
1753 cpu_set(cpu, cpu_callout_map);
1754 cpu_set(cpu, cpu_possible_map);
1755 cpu_set(cpu, cpu_present_map);
1758 static int __cpuinit voyager_cpu_up(unsigned int cpu)
1760 /* This only works at boot for x86. See "rewrite" above. */
1761 if (cpu_isset(cpu, smp_commenced_mask))
1764 /* In case one didn't come up */
1765 if (!cpu_isset(cpu, cpu_callin_map))
1767 /* Unleash the CPU! */
1768 cpu_set(cpu, smp_commenced_mask);
1769 while (!cpu_online(cpu))
1774 static void __init voyager_smp_cpus_done(unsigned int max_cpus)
1779 void __init smp_setup_processor_id(void)
1781 current_thread_info()->cpu = hard_smp_processor_id();
1784 static void voyager_send_call_func(cpumask_t callmask)
1786 __u32 mask = cpus_addr(callmask)[0] & ~(1 << smp_processor_id());
1787 send_CPI(mask, VIC_CALL_FUNCTION_CPI);
1790 static void voyager_send_call_func_single(int cpu)
1792 send_CPI(1 << cpu, VIC_CALL_FUNCTION_SINGLE_CPI);
1795 struct smp_ops smp_ops = {
1796 .smp_prepare_boot_cpu = voyager_smp_prepare_boot_cpu,
1797 .smp_prepare_cpus = voyager_smp_prepare_cpus,
1798 .cpu_up = voyager_cpu_up,
1799 .smp_cpus_done = voyager_smp_cpus_done,
1801 .smp_send_stop = voyager_smp_send_stop,
1802 .smp_send_reschedule = voyager_smp_send_reschedule,
1804 .send_call_func_ipi = voyager_send_call_func,
1805 .send_call_func_single_ipi = voyager_send_call_func_single,