2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
30 #include <linux/clocksource.h>
31 #include <linux/interrupt.h>
32 #include <linux/kvm.h>
34 #include <linux/vmalloc.h>
35 #include <linux/module.h>
36 #include <linux/mman.h>
37 #include <linux/highmem.h>
38 #include <linux/iommu.h>
39 #include <linux/intel-iommu.h>
40 #include <linux/cpufreq.h>
41 #include <linux/user-return-notifier.h>
42 #include <linux/srcu.h>
43 #include <linux/slab.h>
44 #include <linux/perf_event.h>
45 #include <linux/uaccess.h>
46 #include <linux/hash.h>
47 #include <linux/pci.h>
48 #include <trace/events/kvm.h>
50 #define CREATE_TRACE_POINTS
53 #include <asm/debugreg.h>
60 #include <asm/pvclock.h>
61 #include <asm/div64.h>
63 #define MAX_IO_MSRS 256
64 #define KVM_MAX_MCE_BANKS 32
65 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
67 #define emul_to_vcpu(ctxt) \
68 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
71 * - enable syscall per default because its emulated by KVM
72 * - enable LME and LMA per default on 64 bit KVM
76 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
78 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
81 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
82 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
84 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
85 static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
86 struct kvm_cpuid_entry2 __user *entries);
87 static void process_nmi(struct kvm_vcpu *vcpu);
89 struct kvm_x86_ops *kvm_x86_ops;
90 EXPORT_SYMBOL_GPL(kvm_x86_ops);
93 module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
95 unsigned int min_timer_period_us = 500;
96 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
98 bool kvm_has_tsc_control;
99 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
100 u32 kvm_max_guest_tsc_khz;
101 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
103 #define KVM_NR_SHARED_MSRS 16
105 struct kvm_shared_msrs_global {
107 u32 msrs[KVM_NR_SHARED_MSRS];
110 struct kvm_shared_msrs {
111 struct user_return_notifier urn;
113 struct kvm_shared_msr_values {
116 } values[KVM_NR_SHARED_MSRS];
119 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
120 static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
122 struct kvm_stats_debugfs_item debugfs_entries[] = {
123 { "pf_fixed", VCPU_STAT(pf_fixed) },
124 { "pf_guest", VCPU_STAT(pf_guest) },
125 { "tlb_flush", VCPU_STAT(tlb_flush) },
126 { "invlpg", VCPU_STAT(invlpg) },
127 { "exits", VCPU_STAT(exits) },
128 { "io_exits", VCPU_STAT(io_exits) },
129 { "mmio_exits", VCPU_STAT(mmio_exits) },
130 { "signal_exits", VCPU_STAT(signal_exits) },
131 { "irq_window", VCPU_STAT(irq_window_exits) },
132 { "nmi_window", VCPU_STAT(nmi_window_exits) },
133 { "halt_exits", VCPU_STAT(halt_exits) },
134 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
135 { "hypercalls", VCPU_STAT(hypercalls) },
136 { "request_irq", VCPU_STAT(request_irq_exits) },
137 { "irq_exits", VCPU_STAT(irq_exits) },
138 { "host_state_reload", VCPU_STAT(host_state_reload) },
139 { "efer_reload", VCPU_STAT(efer_reload) },
140 { "fpu_reload", VCPU_STAT(fpu_reload) },
141 { "insn_emulation", VCPU_STAT(insn_emulation) },
142 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
143 { "irq_injections", VCPU_STAT(irq_injections) },
144 { "nmi_injections", VCPU_STAT(nmi_injections) },
145 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
146 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
147 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
148 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
149 { "mmu_flooded", VM_STAT(mmu_flooded) },
150 { "mmu_recycled", VM_STAT(mmu_recycled) },
151 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
152 { "mmu_unsync", VM_STAT(mmu_unsync) },
153 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
154 { "largepages", VM_STAT(lpages) },
158 u64 __read_mostly host_xcr0;
160 int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
162 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
165 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
166 vcpu->arch.apf.gfns[i] = ~0;
169 static void kvm_on_user_return(struct user_return_notifier *urn)
172 struct kvm_shared_msrs *locals
173 = container_of(urn, struct kvm_shared_msrs, urn);
174 struct kvm_shared_msr_values *values;
176 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
177 values = &locals->values[slot];
178 if (values->host != values->curr) {
179 wrmsrl(shared_msrs_global.msrs[slot], values->host);
180 values->curr = values->host;
183 locals->registered = false;
184 user_return_notifier_unregister(urn);
187 static void shared_msr_update(unsigned slot, u32 msr)
189 struct kvm_shared_msrs *smsr;
192 smsr = &__get_cpu_var(shared_msrs);
193 /* only read, and nobody should modify it at this time,
194 * so don't need lock */
195 if (slot >= shared_msrs_global.nr) {
196 printk(KERN_ERR "kvm: invalid MSR slot!");
199 rdmsrl_safe(msr, &value);
200 smsr->values[slot].host = value;
201 smsr->values[slot].curr = value;
204 void kvm_define_shared_msr(unsigned slot, u32 msr)
206 if (slot >= shared_msrs_global.nr)
207 shared_msrs_global.nr = slot + 1;
208 shared_msrs_global.msrs[slot] = msr;
209 /* we need ensured the shared_msr_global have been updated */
212 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
214 static void kvm_shared_msr_cpu_online(void)
218 for (i = 0; i < shared_msrs_global.nr; ++i)
219 shared_msr_update(i, shared_msrs_global.msrs[i]);
222 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
224 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
226 if (((value ^ smsr->values[slot].curr) & mask) == 0)
228 smsr->values[slot].curr = value;
229 wrmsrl(shared_msrs_global.msrs[slot], value);
230 if (!smsr->registered) {
231 smsr->urn.on_user_return = kvm_on_user_return;
232 user_return_notifier_register(&smsr->urn);
233 smsr->registered = true;
236 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
238 static void drop_user_return_notifiers(void *ignore)
240 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
242 if (smsr->registered)
243 kvm_on_user_return(&smsr->urn);
246 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
248 if (irqchip_in_kernel(vcpu->kvm))
249 return vcpu->arch.apic_base;
251 return vcpu->arch.apic_base;
253 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
255 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
257 /* TODO: reserve bits check */
258 if (irqchip_in_kernel(vcpu->kvm))
259 kvm_lapic_set_base(vcpu, data);
261 vcpu->arch.apic_base = data;
263 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
265 #define EXCPT_BENIGN 0
266 #define EXCPT_CONTRIBUTORY 1
269 static int exception_class(int vector)
279 return EXCPT_CONTRIBUTORY;
286 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
287 unsigned nr, bool has_error, u32 error_code,
293 kvm_make_request(KVM_REQ_EVENT, vcpu);
295 if (!vcpu->arch.exception.pending) {
297 vcpu->arch.exception.pending = true;
298 vcpu->arch.exception.has_error_code = has_error;
299 vcpu->arch.exception.nr = nr;
300 vcpu->arch.exception.error_code = error_code;
301 vcpu->arch.exception.reinject = reinject;
305 /* to check exception */
306 prev_nr = vcpu->arch.exception.nr;
307 if (prev_nr == DF_VECTOR) {
308 /* triple fault -> shutdown */
309 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
312 class1 = exception_class(prev_nr);
313 class2 = exception_class(nr);
314 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
315 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
316 /* generate double fault per SDM Table 5-5 */
317 vcpu->arch.exception.pending = true;
318 vcpu->arch.exception.has_error_code = true;
319 vcpu->arch.exception.nr = DF_VECTOR;
320 vcpu->arch.exception.error_code = 0;
322 /* replace previous exception with a new one in a hope
323 that instruction re-execution will regenerate lost
328 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
330 kvm_multiple_exception(vcpu, nr, false, 0, false);
332 EXPORT_SYMBOL_GPL(kvm_queue_exception);
334 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
336 kvm_multiple_exception(vcpu, nr, false, 0, true);
338 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
340 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
343 kvm_inject_gp(vcpu, 0);
345 kvm_x86_ops->skip_emulated_instruction(vcpu);
347 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
349 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
351 ++vcpu->stat.pf_guest;
352 vcpu->arch.cr2 = fault->address;
353 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
355 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
357 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
359 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
360 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
362 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
365 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
367 atomic_inc(&vcpu->arch.nmi_queued);
368 kvm_make_request(KVM_REQ_NMI, vcpu);
370 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
372 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
374 kvm_multiple_exception(vcpu, nr, true, error_code, false);
376 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
378 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
380 kvm_multiple_exception(vcpu, nr, true, error_code, true);
382 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
385 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
386 * a #GP and return false.
388 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
390 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
392 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
395 EXPORT_SYMBOL_GPL(kvm_require_cpl);
398 * This function will be used to read from the physical memory of the currently
399 * running guest. The difference to kvm_read_guest_page is that this function
400 * can read from guest physical or from the guest's guest physical memory.
402 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
403 gfn_t ngfn, void *data, int offset, int len,
409 ngpa = gfn_to_gpa(ngfn);
410 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
411 if (real_gfn == UNMAPPED_GVA)
414 real_gfn = gpa_to_gfn(real_gfn);
416 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
418 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
420 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
421 void *data, int offset, int len, u32 access)
423 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
424 data, offset, len, access);
428 * Load the pae pdptrs. Return true is they are all valid.
430 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
432 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
433 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
436 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
438 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
439 offset * sizeof(u64), sizeof(pdpte),
440 PFERR_USER_MASK|PFERR_WRITE_MASK);
445 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
446 if (is_present_gpte(pdpte[i]) &&
447 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
454 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
455 __set_bit(VCPU_EXREG_PDPTR,
456 (unsigned long *)&vcpu->arch.regs_avail);
457 __set_bit(VCPU_EXREG_PDPTR,
458 (unsigned long *)&vcpu->arch.regs_dirty);
463 EXPORT_SYMBOL_GPL(load_pdptrs);
465 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
467 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
473 if (is_long_mode(vcpu) || !is_pae(vcpu))
476 if (!test_bit(VCPU_EXREG_PDPTR,
477 (unsigned long *)&vcpu->arch.regs_avail))
480 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
481 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
482 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
483 PFERR_USER_MASK | PFERR_WRITE_MASK);
486 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
492 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
494 unsigned long old_cr0 = kvm_read_cr0(vcpu);
495 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
496 X86_CR0_CD | X86_CR0_NW;
501 if (cr0 & 0xffffffff00000000UL)
505 cr0 &= ~CR0_RESERVED_BITS;
507 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
510 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
513 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
515 if ((vcpu->arch.efer & EFER_LME)) {
520 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
525 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
530 kvm_x86_ops->set_cr0(vcpu, cr0);
532 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
533 kvm_clear_async_pf_completion_queue(vcpu);
534 kvm_async_pf_hash_reset(vcpu);
537 if ((cr0 ^ old_cr0) & update_bits)
538 kvm_mmu_reset_context(vcpu);
541 EXPORT_SYMBOL_GPL(kvm_set_cr0);
543 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
545 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
547 EXPORT_SYMBOL_GPL(kvm_lmsw);
549 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
553 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
554 if (index != XCR_XFEATURE_ENABLED_MASK)
557 if (!(xcr0 & XSTATE_FP))
559 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
561 if (xcr0 & ~host_xcr0)
563 vcpu->arch.xcr0 = xcr0;
564 vcpu->guest_xcr0_loaded = 0;
568 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
570 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
571 __kvm_set_xcr(vcpu, index, xcr)) {
572 kvm_inject_gp(vcpu, 0);
577 EXPORT_SYMBOL_GPL(kvm_set_xcr);
579 static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
581 struct kvm_cpuid_entry2 *best;
583 if (!static_cpu_has(X86_FEATURE_XSAVE))
586 best = kvm_find_cpuid_entry(vcpu, 1, 0);
587 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
590 static bool guest_cpuid_has_smep(struct kvm_vcpu *vcpu)
592 struct kvm_cpuid_entry2 *best;
594 best = kvm_find_cpuid_entry(vcpu, 7, 0);
595 return best && (best->ebx & bit(X86_FEATURE_SMEP));
598 static bool guest_cpuid_has_fsgsbase(struct kvm_vcpu *vcpu)
600 struct kvm_cpuid_entry2 *best;
602 best = kvm_find_cpuid_entry(vcpu, 7, 0);
603 return best && (best->ebx & bit(X86_FEATURE_FSGSBASE));
606 static void update_cpuid(struct kvm_vcpu *vcpu)
608 struct kvm_cpuid_entry2 *best;
609 struct kvm_lapic *apic = vcpu->arch.apic;
611 best = kvm_find_cpuid_entry(vcpu, 1, 0);
615 /* Update OSXSAVE bit */
616 if (cpu_has_xsave && best->function == 0x1) {
617 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
618 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
619 best->ecx |= bit(X86_FEATURE_OSXSAVE);
623 if (best->ecx & bit(X86_FEATURE_TSC_DEADLINE_TIMER))
624 apic->lapic_timer.timer_mode_mask = 3 << 17;
626 apic->lapic_timer.timer_mode_mask = 1 << 17;
630 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
632 unsigned long old_cr4 = kvm_read_cr4(vcpu);
633 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
634 X86_CR4_PAE | X86_CR4_SMEP;
635 if (cr4 & CR4_RESERVED_BITS)
638 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
641 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
644 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
647 if (is_long_mode(vcpu)) {
648 if (!(cr4 & X86_CR4_PAE))
650 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
651 && ((cr4 ^ old_cr4) & pdptr_bits)
652 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
656 if (kvm_x86_ops->set_cr4(vcpu, cr4))
659 if ((cr4 ^ old_cr4) & pdptr_bits)
660 kvm_mmu_reset_context(vcpu);
662 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
667 EXPORT_SYMBOL_GPL(kvm_set_cr4);
669 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
671 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
672 kvm_mmu_sync_roots(vcpu);
673 kvm_mmu_flush_tlb(vcpu);
677 if (is_long_mode(vcpu)) {
678 if (cr3 & CR3_L_MODE_RESERVED_BITS)
682 if (cr3 & CR3_PAE_RESERVED_BITS)
684 if (is_paging(vcpu) &&
685 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
689 * We don't check reserved bits in nonpae mode, because
690 * this isn't enforced, and VMware depends on this.
695 * Does the new cr3 value map to physical memory? (Note, we
696 * catch an invalid cr3 even in real-mode, because it would
697 * cause trouble later on when we turn on paging anyway.)
699 * A real CPU would silently accept an invalid cr3 and would
700 * attempt to use it - with largely undefined (and often hard
701 * to debug) behavior on the guest side.
703 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
705 vcpu->arch.cr3 = cr3;
706 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
707 vcpu->arch.mmu.new_cr3(vcpu);
710 EXPORT_SYMBOL_GPL(kvm_set_cr3);
712 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
714 if (cr8 & CR8_RESERVED_BITS)
716 if (irqchip_in_kernel(vcpu->kvm))
717 kvm_lapic_set_tpr(vcpu, cr8);
719 vcpu->arch.cr8 = cr8;
722 EXPORT_SYMBOL_GPL(kvm_set_cr8);
724 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
726 if (irqchip_in_kernel(vcpu->kvm))
727 return kvm_lapic_get_cr8(vcpu);
729 return vcpu->arch.cr8;
731 EXPORT_SYMBOL_GPL(kvm_get_cr8);
733 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
737 vcpu->arch.db[dr] = val;
738 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
739 vcpu->arch.eff_db[dr] = val;
742 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
746 if (val & 0xffffffff00000000ULL)
748 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
751 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
755 if (val & 0xffffffff00000000ULL)
757 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
758 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
759 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
760 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
768 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
772 res = __kvm_set_dr(vcpu, dr, val);
774 kvm_queue_exception(vcpu, UD_VECTOR);
776 kvm_inject_gp(vcpu, 0);
780 EXPORT_SYMBOL_GPL(kvm_set_dr);
782 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
786 *val = vcpu->arch.db[dr];
789 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
793 *val = vcpu->arch.dr6;
796 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
800 *val = vcpu->arch.dr7;
807 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
809 if (_kvm_get_dr(vcpu, dr, val)) {
810 kvm_queue_exception(vcpu, UD_VECTOR);
815 EXPORT_SYMBOL_GPL(kvm_get_dr);
818 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
819 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
821 * This list is modified at module load time to reflect the
822 * capabilities of the host cpu. This capabilities test skips MSRs that are
823 * kvm-specific. Those are put in the beginning of the list.
826 #define KVM_SAVE_MSRS_BEGIN 9
827 static u32 msrs_to_save[] = {
828 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
829 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
830 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
831 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
832 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
835 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
837 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
841 static unsigned num_msrs_to_save;
843 static u32 emulated_msrs[] = {
844 MSR_IA32_TSCDEADLINE,
845 MSR_IA32_MISC_ENABLE,
850 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
852 u64 old_efer = vcpu->arch.efer;
854 if (efer & efer_reserved_bits)
858 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
861 if (efer & EFER_FFXSR) {
862 struct kvm_cpuid_entry2 *feat;
864 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
865 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
869 if (efer & EFER_SVME) {
870 struct kvm_cpuid_entry2 *feat;
872 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
873 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
878 efer |= vcpu->arch.efer & EFER_LMA;
880 kvm_x86_ops->set_efer(vcpu, efer);
882 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
884 /* Update reserved bits */
885 if ((efer ^ old_efer) & EFER_NX)
886 kvm_mmu_reset_context(vcpu);
891 void kvm_enable_efer_bits(u64 mask)
893 efer_reserved_bits &= ~mask;
895 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
898 * Writes msr value into into the appropriate "register".
899 * Returns 0 on success, non-0 otherwise.
900 * Assumes vcpu_load() was already called.
902 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
907 case MSR_KERNEL_GS_BASE:
910 if (is_noncanonical_address(data))
913 case MSR_IA32_SYSENTER_EIP:
914 case MSR_IA32_SYSENTER_ESP:
916 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
917 * non-canonical address is written on Intel but not on
918 * AMD (which ignores the top 32-bits, because it does
919 * not implement 64-bit SYSENTER).
921 * 64-bit code should hence be able to write a non-canonical
922 * value on AMD. Making the address canonical ensures that
923 * vmentry does not fail on Intel after writing a non-canonical
924 * value, and that something deterministic happens if the guest
925 * invokes 64-bit SYSENTER.
927 data = get_canonical(data);
929 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
931 EXPORT_SYMBOL_GPL(kvm_set_msr);
934 * Adapt set_msr() to msr_io()'s calling convention
936 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
938 return kvm_set_msr(vcpu, index, *data);
941 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
945 struct pvclock_wall_clock wc;
946 struct timespec boot;
951 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
956 ++version; /* first time write, random junk */
960 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
963 * The guest calculates current wall clock time by adding
964 * system time (updated by kvm_guest_time_update below) to the
965 * wall clock specified here. guest system time equals host
966 * system time for us, thus we must fill in host boot time here.
970 wc.sec = boot.tv_sec;
971 wc.nsec = boot.tv_nsec;
972 wc.version = version;
974 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
977 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
980 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
982 uint32_t quotient, remainder;
984 /* Don't try to replace with do_div(), this one calculates
985 * "(dividend << 32) / divisor" */
987 : "=a" (quotient), "=d" (remainder)
988 : "0" (0), "1" (dividend), "r" (divisor) );
992 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
993 s8 *pshift, u32 *pmultiplier)
1000 tps64 = base_khz * 1000LL;
1001 scaled64 = scaled_khz * 1000LL;
1002 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1007 tps32 = (uint32_t)tps64;
1008 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1009 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1017 *pmultiplier = div_frac(scaled64, tps32);
1019 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1020 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1023 static inline u64 get_kernel_ns(void)
1027 WARN_ON(preemptible());
1029 monotonic_to_bootbased(&ts);
1030 return timespec_to_ns(&ts);
1033 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1034 unsigned long max_tsc_khz;
1036 static inline int kvm_tsc_changes_freq(void)
1038 int cpu = get_cpu();
1039 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
1040 cpufreq_quick_get(cpu) != 0;
1045 u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu)
1047 if (vcpu->arch.virtual_tsc_khz)
1048 return vcpu->arch.virtual_tsc_khz;
1050 return __this_cpu_read(cpu_tsc_khz);
1053 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1057 WARN_ON(preemptible());
1058 if (kvm_tsc_changes_freq())
1059 printk_once(KERN_WARNING
1060 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
1061 ret = nsec * vcpu_tsc_khz(vcpu);
1062 do_div(ret, USEC_PER_SEC);
1066 static void kvm_init_tsc_catchup(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1068 /* Compute a scale to convert nanoseconds in TSC cycles */
1069 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1070 &vcpu->arch.tsc_catchup_shift,
1071 &vcpu->arch.tsc_catchup_mult);
1074 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1076 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1077 vcpu->arch.tsc_catchup_mult,
1078 vcpu->arch.tsc_catchup_shift);
1079 tsc += vcpu->arch.last_tsc_write;
1083 void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1085 struct kvm *kvm = vcpu->kvm;
1086 u64 offset, ns, elapsed;
1087 unsigned long flags;
1090 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1091 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1092 ns = get_kernel_ns();
1093 elapsed = ns - kvm->arch.last_tsc_nsec;
1094 sdiff = data - kvm->arch.last_tsc_write;
1099 * Special case: close write to TSC within 5 seconds of
1100 * another CPU is interpreted as an attempt to synchronize
1101 * The 5 seconds is to accommodate host load / swapping as
1102 * well as any reset of TSC during the boot process.
1104 * In that case, for a reliable TSC, we can match TSC offsets,
1105 * or make a best guest using elapsed value.
1107 if (sdiff < nsec_to_cycles(vcpu, 5ULL * NSEC_PER_SEC) &&
1108 elapsed < 5ULL * NSEC_PER_SEC) {
1109 if (!check_tsc_unstable()) {
1110 offset = kvm->arch.last_tsc_offset;
1111 pr_debug("kvm: matched tsc offset for %llu\n", data);
1113 u64 delta = nsec_to_cycles(vcpu, elapsed);
1115 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1117 ns = kvm->arch.last_tsc_nsec;
1119 kvm->arch.last_tsc_nsec = ns;
1120 kvm->arch.last_tsc_write = data;
1121 kvm->arch.last_tsc_offset = offset;
1122 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1123 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1125 /* Reset of TSC must disable overshoot protection below */
1126 vcpu->arch.hv_clock.tsc_timestamp = 0;
1127 vcpu->arch.last_tsc_write = data;
1128 vcpu->arch.last_tsc_nsec = ns;
1130 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1132 static int kvm_guest_time_update(struct kvm_vcpu *v)
1134 unsigned long flags;
1135 struct kvm_vcpu_arch *vcpu = &v->arch;
1136 unsigned long this_tsc_khz;
1137 s64 kernel_ns, max_kernel_ns;
1140 /* Keep irq disabled to prevent changes to the clock */
1141 local_irq_save(flags);
1142 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
1143 kernel_ns = get_kernel_ns();
1144 this_tsc_khz = vcpu_tsc_khz(v);
1145 if (unlikely(this_tsc_khz == 0)) {
1146 local_irq_restore(flags);
1147 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1152 * We may have to catch up the TSC to match elapsed wall clock
1153 * time for two reasons, even if kvmclock is used.
1154 * 1) CPU could have been running below the maximum TSC rate
1155 * 2) Broken TSC compensation resets the base at each VCPU
1156 * entry to avoid unknown leaps of TSC even when running
1157 * again on the same CPU. This may cause apparent elapsed
1158 * time to disappear, and the guest to stand still or run
1161 if (vcpu->tsc_catchup) {
1162 u64 tsc = compute_guest_tsc(v, kernel_ns);
1163 if (tsc > tsc_timestamp) {
1164 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1165 tsc_timestamp = tsc;
1169 local_irq_restore(flags);
1171 if (!vcpu->pv_time_enabled)
1175 * Time as measured by the TSC may go backwards when resetting the base
1176 * tsc_timestamp. The reason for this is that the TSC resolution is
1177 * higher than the resolution of the other clock scales. Thus, many
1178 * possible measurments of the TSC correspond to one measurement of any
1179 * other clock, and so a spread of values is possible. This is not a
1180 * problem for the computation of the nanosecond clock; with TSC rates
1181 * around 1GHZ, there can only be a few cycles which correspond to one
1182 * nanosecond value, and any path through this code will inevitably
1183 * take longer than that. However, with the kernel_ns value itself,
1184 * the precision may be much lower, down to HZ granularity. If the
1185 * first sampling of TSC against kernel_ns ends in the low part of the
1186 * range, and the second in the high end of the range, we can get:
1188 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1190 * As the sampling errors potentially range in the thousands of cycles,
1191 * it is possible such a time value has already been observed by the
1192 * guest. To protect against this, we must compute the system time as
1193 * observed by the guest and ensure the new system time is greater.
1196 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1197 max_kernel_ns = vcpu->last_guest_tsc -
1198 vcpu->hv_clock.tsc_timestamp;
1199 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1200 vcpu->hv_clock.tsc_to_system_mul,
1201 vcpu->hv_clock.tsc_shift);
1202 max_kernel_ns += vcpu->last_kernel_ns;
1205 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1206 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1207 &vcpu->hv_clock.tsc_shift,
1208 &vcpu->hv_clock.tsc_to_system_mul);
1209 vcpu->hw_tsc_khz = this_tsc_khz;
1212 if (max_kernel_ns > kernel_ns)
1213 kernel_ns = max_kernel_ns;
1215 /* With all the info we got, fill in the values */
1216 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1217 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1218 vcpu->last_kernel_ns = kernel_ns;
1219 vcpu->last_guest_tsc = tsc_timestamp;
1220 vcpu->hv_clock.flags = 0;
1223 * The interface expects us to write an even number signaling that the
1224 * update is finished. Since the guest won't see the intermediate
1225 * state, we just increase by 2 at the end.
1227 vcpu->hv_clock.version += 2;
1229 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1231 sizeof(vcpu->hv_clock));
1235 static bool msr_mtrr_valid(unsigned msr)
1238 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1239 case MSR_MTRRfix64K_00000:
1240 case MSR_MTRRfix16K_80000:
1241 case MSR_MTRRfix16K_A0000:
1242 case MSR_MTRRfix4K_C0000:
1243 case MSR_MTRRfix4K_C8000:
1244 case MSR_MTRRfix4K_D0000:
1245 case MSR_MTRRfix4K_D8000:
1246 case MSR_MTRRfix4K_E0000:
1247 case MSR_MTRRfix4K_E8000:
1248 case MSR_MTRRfix4K_F0000:
1249 case MSR_MTRRfix4K_F8000:
1250 case MSR_MTRRdefType:
1251 case MSR_IA32_CR_PAT:
1259 static bool valid_pat_type(unsigned t)
1261 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1264 static bool valid_mtrr_type(unsigned t)
1266 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1269 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1273 if (!msr_mtrr_valid(msr))
1276 if (msr == MSR_IA32_CR_PAT) {
1277 for (i = 0; i < 8; i++)
1278 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1281 } else if (msr == MSR_MTRRdefType) {
1284 return valid_mtrr_type(data & 0xff);
1285 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1286 for (i = 0; i < 8 ; i++)
1287 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1292 /* variable MTRRs */
1293 return valid_mtrr_type(data & 0xff);
1296 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1298 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1300 if (!mtrr_valid(vcpu, msr, data))
1303 if (msr == MSR_MTRRdefType) {
1304 vcpu->arch.mtrr_state.def_type = data;
1305 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1306 } else if (msr == MSR_MTRRfix64K_00000)
1308 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1309 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1310 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1311 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1312 else if (msr == MSR_IA32_CR_PAT)
1313 vcpu->arch.pat = data;
1314 else { /* Variable MTRRs */
1315 int idx, is_mtrr_mask;
1318 idx = (msr - 0x200) / 2;
1319 is_mtrr_mask = msr - 0x200 - 2 * idx;
1322 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1325 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1329 kvm_mmu_reset_context(vcpu);
1333 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1335 u64 mcg_cap = vcpu->arch.mcg_cap;
1336 unsigned bank_num = mcg_cap & 0xff;
1339 case MSR_IA32_MCG_STATUS:
1340 vcpu->arch.mcg_status = data;
1342 case MSR_IA32_MCG_CTL:
1343 if (!(mcg_cap & MCG_CTL_P))
1345 if (data != 0 && data != ~(u64)0)
1347 vcpu->arch.mcg_ctl = data;
1350 if (msr >= MSR_IA32_MC0_CTL &&
1351 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1352 u32 offset = msr - MSR_IA32_MC0_CTL;
1353 /* only 0 or all 1s can be written to IA32_MCi_CTL
1354 * some Linux kernels though clear bit 10 in bank 4 to
1355 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1356 * this to avoid an uncatched #GP in the guest
1358 if ((offset & 0x3) == 0 &&
1359 data != 0 && (data | (1 << 10)) != ~(u64)0)
1361 vcpu->arch.mce_banks[offset] = data;
1369 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1371 struct kvm *kvm = vcpu->kvm;
1372 int lm = is_long_mode(vcpu);
1373 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1374 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1375 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1376 : kvm->arch.xen_hvm_config.blob_size_32;
1377 u32 page_num = data & ~PAGE_MASK;
1378 u64 page_addr = data & PAGE_MASK;
1383 if (page_num >= blob_size)
1386 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1390 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1392 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1401 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1403 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1406 static bool kvm_hv_msr_partition_wide(u32 msr)
1410 case HV_X64_MSR_GUEST_OS_ID:
1411 case HV_X64_MSR_HYPERCALL:
1419 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1421 struct kvm *kvm = vcpu->kvm;
1424 case HV_X64_MSR_GUEST_OS_ID:
1425 kvm->arch.hv_guest_os_id = data;
1426 /* setting guest os id to zero disables hypercall page */
1427 if (!kvm->arch.hv_guest_os_id)
1428 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1430 case HV_X64_MSR_HYPERCALL: {
1435 /* if guest os id is not set hypercall should remain disabled */
1436 if (!kvm->arch.hv_guest_os_id)
1438 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1439 kvm->arch.hv_hypercall = data;
1442 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1443 addr = gfn_to_hva(kvm, gfn);
1444 if (kvm_is_error_hva(addr))
1446 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1447 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1448 if (__copy_to_user((void __user *)addr, instructions, 4))
1450 kvm->arch.hv_hypercall = data;
1454 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1455 "data 0x%llx\n", msr, data);
1461 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1464 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1467 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1468 vcpu->arch.hv_vapic = data;
1471 addr = gfn_to_hva(vcpu->kvm, data >>
1472 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1473 if (kvm_is_error_hva(addr))
1475 if (__clear_user((void __user *)addr, PAGE_SIZE))
1477 vcpu->arch.hv_vapic = data;
1480 case HV_X64_MSR_EOI:
1481 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1482 case HV_X64_MSR_ICR:
1483 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1484 case HV_X64_MSR_TPR:
1485 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1487 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1488 "data 0x%llx\n", msr, data);
1495 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1497 gpa_t gpa = data & ~0x3f;
1499 /* Bits 2:5 are resrved, Should be zero */
1503 vcpu->arch.apf.msr_val = data;
1505 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1506 kvm_clear_async_pf_completion_queue(vcpu);
1507 kvm_async_pf_hash_reset(vcpu);
1511 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1515 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1516 kvm_async_pf_wakeup_all(vcpu);
1520 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1522 vcpu->arch.pv_time_enabled = false;
1525 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1529 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1532 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1533 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1534 vcpu->arch.st.accum_steal = delta;
1537 static void record_steal_time(struct kvm_vcpu *vcpu)
1539 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1542 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1543 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1546 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1547 vcpu->arch.st.steal.version += 2;
1548 vcpu->arch.st.accum_steal = 0;
1550 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1551 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1554 int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1558 return set_efer(vcpu, data);
1560 data &= ~(u64)0x40; /* ignore flush filter disable */
1561 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1563 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1568 case MSR_FAM10H_MMIO_CONF_BASE:
1570 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1575 case MSR_AMD64_NB_CFG:
1577 case MSR_IA32_DEBUGCTLMSR:
1579 /* We support the non-activated case already */
1581 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1582 /* Values other than LBR and BTF are vendor-specific,
1583 thus reserved and should throw a #GP */
1586 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1589 case MSR_IA32_UCODE_REV:
1590 case MSR_IA32_UCODE_WRITE:
1591 case MSR_VM_HSAVE_PA:
1592 case MSR_AMD64_PATCH_LOADER:
1594 case 0x200 ... 0x2ff:
1595 return set_msr_mtrr(vcpu, msr, data);
1596 case MSR_IA32_APICBASE:
1597 kvm_set_apic_base(vcpu, data);
1599 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1600 return kvm_x2apic_msr_write(vcpu, msr, data);
1601 case MSR_IA32_TSCDEADLINE:
1602 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1604 case MSR_IA32_MISC_ENABLE:
1605 vcpu->arch.ia32_misc_enable_msr = data;
1607 case MSR_KVM_WALL_CLOCK_NEW:
1608 case MSR_KVM_WALL_CLOCK:
1609 vcpu->kvm->arch.wall_clock = data;
1610 kvm_write_wall_clock(vcpu->kvm, data);
1612 case MSR_KVM_SYSTEM_TIME_NEW:
1613 case MSR_KVM_SYSTEM_TIME: {
1615 kvmclock_reset(vcpu);
1617 vcpu->arch.time = data;
1618 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1620 /* we verify if the enable bit is set... */
1624 gpa_offset = data & ~(PAGE_MASK | 1);
1626 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1627 &vcpu->arch.pv_time, data & ~1ULL,
1628 sizeof(struct pvclock_vcpu_time_info)))
1629 vcpu->arch.pv_time_enabled = false;
1631 vcpu->arch.pv_time_enabled = true;
1634 case MSR_KVM_ASYNC_PF_EN:
1635 if (kvm_pv_enable_async_pf(vcpu, data))
1638 case MSR_KVM_STEAL_TIME:
1640 if (unlikely(!sched_info_on()))
1643 if (data & KVM_STEAL_RESERVED_MASK)
1646 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1647 data & KVM_STEAL_VALID_BITS,
1648 sizeof(struct kvm_steal_time)))
1651 vcpu->arch.st.msr_val = data;
1653 if (!(data & KVM_MSR_ENABLED))
1656 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1659 accumulate_steal_time(vcpu);
1662 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1666 case MSR_IA32_MCG_CTL:
1667 case MSR_IA32_MCG_STATUS:
1668 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1669 return set_msr_mce(vcpu, msr, data);
1671 /* Performance counters are not protected by a CPUID bit,
1672 * so we should check all of them in the generic path for the sake of
1673 * cross vendor migration.
1674 * Writing a zero into the event select MSRs disables them,
1675 * which we perfectly emulate ;-). Any other value should be at least
1676 * reported, some guests depend on them.
1678 case MSR_P6_EVNTSEL0:
1679 case MSR_P6_EVNTSEL1:
1680 case MSR_K7_EVNTSEL0:
1681 case MSR_K7_EVNTSEL1:
1682 case MSR_K7_EVNTSEL2:
1683 case MSR_K7_EVNTSEL3:
1685 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1686 "0x%x data 0x%llx\n", msr, data);
1688 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1689 * so we ignore writes to make it happy.
1691 case MSR_P6_PERFCTR0:
1692 case MSR_P6_PERFCTR1:
1693 case MSR_K7_PERFCTR0:
1694 case MSR_K7_PERFCTR1:
1695 case MSR_K7_PERFCTR2:
1696 case MSR_K7_PERFCTR3:
1697 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1698 "0x%x data 0x%llx\n", msr, data);
1700 case MSR_K7_CLK_CTL:
1702 * Ignore all writes to this no longer documented MSR.
1703 * Writes are only relevant for old K7 processors,
1704 * all pre-dating SVM, but a recommended workaround from
1705 * AMD for these chips. It is possible to speicify the
1706 * affected processor models on the command line, hence
1707 * the need to ignore the workaround.
1710 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1711 if (kvm_hv_msr_partition_wide(msr)) {
1713 mutex_lock(&vcpu->kvm->lock);
1714 r = set_msr_hyperv_pw(vcpu, msr, data);
1715 mutex_unlock(&vcpu->kvm->lock);
1718 return set_msr_hyperv(vcpu, msr, data);
1720 case MSR_IA32_BBL_CR_CTL3:
1721 /* Drop writes to this legacy MSR -- see rdmsr
1722 * counterpart for further detail.
1724 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1727 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1728 return xen_hvm_config(vcpu, data);
1730 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1734 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1741 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1745 * Reads an msr value (of 'msr_index') into 'pdata'.
1746 * Returns 0 on success, non-0 otherwise.
1747 * Assumes vcpu_load() was already called.
1749 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1751 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1754 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1756 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1758 if (!msr_mtrr_valid(msr))
1761 if (msr == MSR_MTRRdefType)
1762 *pdata = vcpu->arch.mtrr_state.def_type +
1763 (vcpu->arch.mtrr_state.enabled << 10);
1764 else if (msr == MSR_MTRRfix64K_00000)
1766 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1767 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1768 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1769 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1770 else if (msr == MSR_IA32_CR_PAT)
1771 *pdata = vcpu->arch.pat;
1772 else { /* Variable MTRRs */
1773 int idx, is_mtrr_mask;
1776 idx = (msr - 0x200) / 2;
1777 is_mtrr_mask = msr - 0x200 - 2 * idx;
1780 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1783 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1790 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1793 u64 mcg_cap = vcpu->arch.mcg_cap;
1794 unsigned bank_num = mcg_cap & 0xff;
1797 case MSR_IA32_P5_MC_ADDR:
1798 case MSR_IA32_P5_MC_TYPE:
1801 case MSR_IA32_MCG_CAP:
1802 data = vcpu->arch.mcg_cap;
1804 case MSR_IA32_MCG_CTL:
1805 if (!(mcg_cap & MCG_CTL_P))
1807 data = vcpu->arch.mcg_ctl;
1809 case MSR_IA32_MCG_STATUS:
1810 data = vcpu->arch.mcg_status;
1813 if (msr >= MSR_IA32_MC0_CTL &&
1814 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1815 u32 offset = msr - MSR_IA32_MC0_CTL;
1816 data = vcpu->arch.mce_banks[offset];
1825 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1828 struct kvm *kvm = vcpu->kvm;
1831 case HV_X64_MSR_GUEST_OS_ID:
1832 data = kvm->arch.hv_guest_os_id;
1834 case HV_X64_MSR_HYPERCALL:
1835 data = kvm->arch.hv_hypercall;
1838 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1846 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1851 case HV_X64_MSR_VP_INDEX: {
1854 kvm_for_each_vcpu(r, v, vcpu->kvm)
1859 case HV_X64_MSR_EOI:
1860 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1861 case HV_X64_MSR_ICR:
1862 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1863 case HV_X64_MSR_TPR:
1864 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
1865 case HV_X64_MSR_APIC_ASSIST_PAGE:
1866 data = vcpu->arch.hv_vapic;
1869 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1876 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1881 case MSR_IA32_PLATFORM_ID:
1882 case MSR_IA32_EBL_CR_POWERON:
1883 case MSR_IA32_DEBUGCTLMSR:
1884 case MSR_IA32_LASTBRANCHFROMIP:
1885 case MSR_IA32_LASTBRANCHTOIP:
1886 case MSR_IA32_LASTINTFROMIP:
1887 case MSR_IA32_LASTINTTOIP:
1889 case MSR_K8_TSEG_ADDR:
1890 case MSR_K8_TSEG_MASK:
1892 case MSR_VM_HSAVE_PA:
1893 case MSR_P6_PERFCTR0:
1894 case MSR_P6_PERFCTR1:
1895 case MSR_P6_EVNTSEL0:
1896 case MSR_P6_EVNTSEL1:
1897 case MSR_K7_EVNTSEL0:
1898 case MSR_K7_PERFCTR0:
1899 case MSR_K8_INT_PENDING_MSG:
1900 case MSR_AMD64_NB_CFG:
1901 case MSR_FAM10H_MMIO_CONF_BASE:
1904 case MSR_IA32_UCODE_REV:
1905 data = 0x100000000ULL;
1908 data = 0x500 | KVM_NR_VAR_MTRR;
1910 case 0x200 ... 0x2ff:
1911 return get_msr_mtrr(vcpu, msr, pdata);
1912 case 0xcd: /* fsb frequency */
1916 * MSR_EBC_FREQUENCY_ID
1917 * Conservative value valid for even the basic CPU models.
1918 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1919 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1920 * and 266MHz for model 3, or 4. Set Core Clock
1921 * Frequency to System Bus Frequency Ratio to 1 (bits
1922 * 31:24) even though these are only valid for CPU
1923 * models > 2, however guests may end up dividing or
1924 * multiplying by zero otherwise.
1926 case MSR_EBC_FREQUENCY_ID:
1929 case MSR_IA32_APICBASE:
1930 data = kvm_get_apic_base(vcpu);
1932 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1933 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1935 case MSR_IA32_TSCDEADLINE:
1936 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1938 case MSR_IA32_MISC_ENABLE:
1939 data = vcpu->arch.ia32_misc_enable_msr;
1941 case MSR_IA32_PERF_STATUS:
1942 /* TSC increment by tick */
1944 /* CPU multiplier */
1945 data |= (((uint64_t)4ULL) << 40);
1948 data = vcpu->arch.efer;
1950 case MSR_KVM_WALL_CLOCK:
1951 case MSR_KVM_WALL_CLOCK_NEW:
1952 data = vcpu->kvm->arch.wall_clock;
1954 case MSR_KVM_SYSTEM_TIME:
1955 case MSR_KVM_SYSTEM_TIME_NEW:
1956 data = vcpu->arch.time;
1958 case MSR_KVM_ASYNC_PF_EN:
1959 data = vcpu->arch.apf.msr_val;
1961 case MSR_KVM_STEAL_TIME:
1962 data = vcpu->arch.st.msr_val;
1964 case MSR_IA32_P5_MC_ADDR:
1965 case MSR_IA32_P5_MC_TYPE:
1966 case MSR_IA32_MCG_CAP:
1967 case MSR_IA32_MCG_CTL:
1968 case MSR_IA32_MCG_STATUS:
1969 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1970 return get_msr_mce(vcpu, msr, pdata);
1971 case MSR_K7_CLK_CTL:
1973 * Provide expected ramp-up count for K7. All other
1974 * are set to zero, indicating minimum divisors for
1977 * This prevents guest kernels on AMD host with CPU
1978 * type 6, model 8 and higher from exploding due to
1979 * the rdmsr failing.
1983 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1984 if (kvm_hv_msr_partition_wide(msr)) {
1986 mutex_lock(&vcpu->kvm->lock);
1987 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1988 mutex_unlock(&vcpu->kvm->lock);
1991 return get_msr_hyperv(vcpu, msr, pdata);
1993 case MSR_IA32_BBL_CR_CTL3:
1994 /* This legacy MSR exists but isn't fully documented in current
1995 * silicon. It is however accessed by winxp in very narrow
1996 * scenarios where it sets bit #19, itself documented as
1997 * a "reserved" bit. Best effort attempt to source coherent
1998 * read data here should the balance of the register be
1999 * interpreted by the guest:
2001 * L2 cache control register 3: 64GB range, 256KB size,
2002 * enabled, latency 0x1, configured
2008 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2011 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2019 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2022 * Read or write a bunch of msrs. All parameters are kernel addresses.
2024 * @return number of msrs set successfully.
2026 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2027 struct kvm_msr_entry *entries,
2028 int (*do_msr)(struct kvm_vcpu *vcpu,
2029 unsigned index, u64 *data))
2033 idx = srcu_read_lock(&vcpu->kvm->srcu);
2034 for (i = 0; i < msrs->nmsrs; ++i)
2035 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2037 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2043 * Read or write a bunch of msrs. Parameters are user addresses.
2045 * @return number of msrs set successfully.
2047 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2048 int (*do_msr)(struct kvm_vcpu *vcpu,
2049 unsigned index, u64 *data),
2052 struct kvm_msrs msrs;
2053 struct kvm_msr_entry *entries;
2058 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2062 if (msrs.nmsrs >= MAX_IO_MSRS)
2066 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2067 entries = kmalloc(size, GFP_KERNEL);
2072 if (copy_from_user(entries, user_msrs->entries, size))
2075 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2080 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2091 int kvm_dev_ioctl_check_extension(long ext)
2096 case KVM_CAP_IRQCHIP:
2098 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2099 case KVM_CAP_SET_TSS_ADDR:
2100 case KVM_CAP_EXT_CPUID:
2101 case KVM_CAP_CLOCKSOURCE:
2103 case KVM_CAP_NOP_IO_DELAY:
2104 case KVM_CAP_MP_STATE:
2105 case KVM_CAP_SYNC_MMU:
2106 case KVM_CAP_USER_NMI:
2107 case KVM_CAP_REINJECT_CONTROL:
2108 case KVM_CAP_IRQ_INJECT_STATUS:
2109 case KVM_CAP_ASSIGN_DEV_IRQ:
2111 case KVM_CAP_IOEVENTFD:
2113 case KVM_CAP_PIT_STATE2:
2114 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2115 case KVM_CAP_XEN_HVM:
2116 case KVM_CAP_ADJUST_CLOCK:
2117 case KVM_CAP_VCPU_EVENTS:
2118 case KVM_CAP_HYPERV:
2119 case KVM_CAP_HYPERV_VAPIC:
2120 case KVM_CAP_HYPERV_SPIN:
2121 case KVM_CAP_PCI_SEGMENT:
2122 case KVM_CAP_DEBUGREGS:
2123 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2125 case KVM_CAP_ASYNC_PF:
2126 case KVM_CAP_GET_TSC_KHZ:
2129 case KVM_CAP_COALESCED_MMIO:
2130 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2133 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2135 case KVM_CAP_NR_VCPUS:
2136 r = KVM_SOFT_MAX_VCPUS;
2138 case KVM_CAP_MAX_VCPUS:
2141 case KVM_CAP_NR_MEMSLOTS:
2142 r = KVM_MEMORY_SLOTS;
2144 case KVM_CAP_PV_MMU: /* obsolete */
2148 r = iommu_present(&pci_bus_type);
2151 r = KVM_MAX_MCE_BANKS;
2156 case KVM_CAP_TSC_CONTROL:
2157 r = kvm_has_tsc_control;
2159 case KVM_CAP_TSC_DEADLINE_TIMER:
2160 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2170 long kvm_arch_dev_ioctl(struct file *filp,
2171 unsigned int ioctl, unsigned long arg)
2173 void __user *argp = (void __user *)arg;
2177 case KVM_GET_MSR_INDEX_LIST: {
2178 struct kvm_msr_list __user *user_msr_list = argp;
2179 struct kvm_msr_list msr_list;
2183 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2186 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2187 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2190 if (n < msr_list.nmsrs)
2193 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2194 num_msrs_to_save * sizeof(u32)))
2196 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2198 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2203 case KVM_GET_SUPPORTED_CPUID: {
2204 struct kvm_cpuid2 __user *cpuid_arg = argp;
2205 struct kvm_cpuid2 cpuid;
2208 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2210 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
2211 cpuid_arg->entries);
2216 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2221 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2224 mce_cap = KVM_MCE_CAP_SUPPORTED;
2226 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2238 static void wbinvd_ipi(void *garbage)
2243 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2245 return vcpu->kvm->arch.iommu_domain &&
2246 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2249 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2251 /* Address WBINVD may be executed by guest */
2252 if (need_emulate_wbinvd(vcpu)) {
2253 if (kvm_x86_ops->has_wbinvd_exit())
2254 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2255 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2256 smp_call_function_single(vcpu->cpu,
2257 wbinvd_ipi, NULL, 1);
2260 kvm_x86_ops->vcpu_load(vcpu, cpu);
2261 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2262 /* Make sure TSC doesn't go backwards */
2266 tsc = kvm_x86_ops->read_l1_tsc(vcpu);
2267 tsc_delta = !vcpu->arch.last_guest_tsc ? 0 :
2268 tsc - vcpu->arch.last_guest_tsc;
2271 mark_tsc_unstable("KVM discovered backwards TSC");
2272 if (check_tsc_unstable()) {
2273 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
2274 vcpu->arch.tsc_catchup = 1;
2276 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2277 if (vcpu->cpu != cpu)
2278 kvm_migrate_timers(vcpu);
2282 accumulate_steal_time(vcpu);
2283 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2286 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2288 kvm_x86_ops->vcpu_put(vcpu);
2289 kvm_put_guest_fpu(vcpu);
2290 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
2293 static int is_efer_nx(void)
2295 unsigned long long efer = 0;
2297 rdmsrl_safe(MSR_EFER, &efer);
2298 return efer & EFER_NX;
2301 static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2304 struct kvm_cpuid_entry2 *e, *entry;
2307 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2308 e = &vcpu->arch.cpuid_entries[i];
2309 if (e->function == 0x80000001) {
2314 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
2315 entry->edx &= ~(1 << 20);
2316 printk(KERN_INFO "kvm: guest NX capability removed\n");
2320 /* when an old userspace process fills a new kernel module */
2321 static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2322 struct kvm_cpuid *cpuid,
2323 struct kvm_cpuid_entry __user *entries)
2326 struct kvm_cpuid_entry *cpuid_entries;
2329 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2332 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2336 if (copy_from_user(cpuid_entries, entries,
2337 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2339 for (i = 0; i < cpuid->nent; i++) {
2340 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2341 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2342 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2343 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2344 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2345 vcpu->arch.cpuid_entries[i].index = 0;
2346 vcpu->arch.cpuid_entries[i].flags = 0;
2347 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2348 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2349 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2351 vcpu->arch.cpuid_nent = cpuid->nent;
2352 cpuid_fix_nx_cap(vcpu);
2354 kvm_apic_set_version(vcpu);
2355 kvm_x86_ops->cpuid_update(vcpu);
2359 vfree(cpuid_entries);
2364 static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
2365 struct kvm_cpuid2 *cpuid,
2366 struct kvm_cpuid_entry2 __user *entries)
2371 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2374 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
2375 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
2377 vcpu->arch.cpuid_nent = cpuid->nent;
2378 kvm_apic_set_version(vcpu);
2379 kvm_x86_ops->cpuid_update(vcpu);
2387 static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
2388 struct kvm_cpuid2 *cpuid,
2389 struct kvm_cpuid_entry2 __user *entries)
2394 if (cpuid->nent < vcpu->arch.cpuid_nent)
2397 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
2398 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
2403 cpuid->nent = vcpu->arch.cpuid_nent;
2407 static void cpuid_mask(u32 *word, int wordnum)
2409 *word &= boot_cpu_data.x86_capability[wordnum];
2412 static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2415 entry->function = function;
2416 entry->index = index;
2417 cpuid_count(entry->function, entry->index,
2418 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
2422 static bool supported_xcr0_bit(unsigned bit)
2424 u64 mask = ((u64)1 << bit);
2426 return mask & (XSTATE_FP | XSTATE_SSE | XSTATE_YMM) & host_xcr0;
2429 #define F(x) bit(X86_FEATURE_##x)
2431 static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2432 u32 index, int *nent, int maxnent)
2434 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
2435 #ifdef CONFIG_X86_64
2436 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2438 unsigned f_lm = F(LM);
2440 unsigned f_gbpages = 0;
2443 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
2446 const u32 kvm_supported_word0_x86_features =
2447 F(FPU) | F(VME) | F(DE) | F(PSE) |
2448 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2449 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2450 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2451 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2452 0 /* Reserved, DS, ACPI */ | F(MMX) |
2453 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2454 0 /* HTT, TM, Reserved, PBE */;
2455 /* cpuid 0x80000001.edx */
2456 const u32 kvm_supported_word1_x86_features =
2457 F(FPU) | F(VME) | F(DE) | F(PSE) |
2458 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2459 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2460 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2461 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2462 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
2463 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
2464 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2466 const u32 kvm_supported_word4_x86_features =
2467 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
2468 0 /* DS-CPL, VMX, SMX, EST */ |
2469 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2470 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2471 0 /* Reserved, DCA */ | F(XMM4_1) |
2472 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
2473 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
2474 F(F16C) | F(RDRAND);
2475 /* cpuid 0x80000001.ecx */
2476 const u32 kvm_supported_word6_x86_features =
2477 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
2478 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
2479 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
2480 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
2482 /* cpuid 0xC0000001.edx */
2483 const u32 kvm_supported_word5_x86_features =
2484 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
2485 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
2489 const u32 kvm_supported_word9_x86_features =
2490 F(SMEP) | F(FSGSBASE) | F(ERMS);
2492 /* all calls to cpuid_count() should be made on the same cpu */
2494 do_cpuid_1_ent(entry, function, index);
2499 entry->eax = min(entry->eax, (u32)0xd);
2502 entry->edx &= kvm_supported_word0_x86_features;
2503 cpuid_mask(&entry->edx, 0);
2504 entry->ecx &= kvm_supported_word4_x86_features;
2505 cpuid_mask(&entry->ecx, 4);
2506 /* we support x2apic emulation even if host does not support
2507 * it since we emulate x2apic in software */
2508 entry->ecx |= F(X2APIC);
2510 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2511 * may return different values. This forces us to get_cpu() before
2512 * issuing the first command, and also to emulate this annoying behavior
2513 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2515 int t, times = entry->eax & 0xff;
2517 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2518 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2519 for (t = 1; t < times && *nent < maxnent; ++t) {
2520 do_cpuid_1_ent(&entry[t], function, 0);
2521 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2526 /* function 4 has additional index. */
2530 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2531 /* read more entries until cache_type is zero */
2532 for (i = 1; *nent < maxnent; ++i) {
2533 cache_type = entry[i - 1].eax & 0x1f;
2536 do_cpuid_1_ent(&entry[i], function, i);
2538 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2544 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2545 /* Mask ebx against host capbability word 9 */
2547 entry->ebx &= kvm_supported_word9_x86_features;
2548 cpuid_mask(&entry->ebx, 9);
2558 /* function 0xb has additional index. */
2562 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2563 /* read more entries until level_type is zero */
2564 for (i = 1; *nent < maxnent; ++i) {
2565 level_type = entry[i - 1].ecx & 0xff00;
2568 do_cpuid_1_ent(&entry[i], function, i);
2570 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2578 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2579 for (idx = 1, i = 1; *nent < maxnent && idx < 64; ++idx) {
2580 do_cpuid_1_ent(&entry[i], function, idx);
2581 if (entry[i].eax == 0 || !supported_xcr0_bit(idx))
2584 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2590 case KVM_CPUID_SIGNATURE: {
2591 char signature[12] = "KVMKVMKVM\0\0";
2592 u32 *sigptr = (u32 *)signature;
2594 entry->ebx = sigptr[0];
2595 entry->ecx = sigptr[1];
2596 entry->edx = sigptr[2];
2599 case KVM_CPUID_FEATURES:
2600 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2601 (1 << KVM_FEATURE_NOP_IO_DELAY) |
2602 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2603 (1 << KVM_FEATURE_ASYNC_PF) |
2604 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
2606 if (sched_info_on())
2607 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME);
2614 entry->eax = min(entry->eax, 0x8000001a);
2617 entry->edx &= kvm_supported_word1_x86_features;
2618 cpuid_mask(&entry->edx, 1);
2619 entry->ecx &= kvm_supported_word6_x86_features;
2620 cpuid_mask(&entry->ecx, 6);
2623 unsigned g_phys_as = (entry->eax >> 16) & 0xff;
2624 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U);
2625 unsigned phys_as = entry->eax & 0xff;
2628 g_phys_as = phys_as;
2629 entry->eax = g_phys_as | (virt_as << 8);
2630 entry->ebx = entry->edx = 0;
2634 entry->ecx = entry->edx = 0;
2640 /*Add support for Centaur's CPUID instruction*/
2642 /*Just support up to 0xC0000004 now*/
2643 entry->eax = min(entry->eax, 0xC0000004);
2646 entry->edx &= kvm_supported_word5_x86_features;
2647 cpuid_mask(&entry->edx, 5);
2649 case 3: /* Processor serial number */
2650 case 5: /* MONITOR/MWAIT */
2651 case 6: /* Thermal management */
2652 case 0xA: /* Architectural Performance Monitoring */
2653 case 0x80000007: /* Advanced power management */
2658 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
2662 kvm_x86_ops->set_supported_cpuid(function, entry);
2669 static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
2670 struct kvm_cpuid_entry2 __user *entries)
2672 struct kvm_cpuid_entry2 *cpuid_entries;
2673 int limit, nent = 0, r = -E2BIG;
2676 if (cpuid->nent < 1)
2678 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2679 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
2681 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2685 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2686 limit = cpuid_entries[0].eax;
2687 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2688 do_cpuid_ent(&cpuid_entries[nent], func, 0,
2689 &nent, cpuid->nent);
2691 if (nent >= cpuid->nent)
2694 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2695 limit = cpuid_entries[nent - 1].eax;
2696 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2697 do_cpuid_ent(&cpuid_entries[nent], func, 0,
2698 &nent, cpuid->nent);
2703 if (nent >= cpuid->nent)
2706 /* Add support for Centaur's CPUID instruction. */
2707 if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR) {
2708 do_cpuid_ent(&cpuid_entries[nent], 0xC0000000, 0,
2709 &nent, cpuid->nent);
2712 if (nent >= cpuid->nent)
2715 limit = cpuid_entries[nent - 1].eax;
2716 for (func = 0xC0000001;
2717 func <= limit && nent < cpuid->nent; ++func)
2718 do_cpuid_ent(&cpuid_entries[nent], func, 0,
2719 &nent, cpuid->nent);
2722 if (nent >= cpuid->nent)
2726 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2730 if (nent >= cpuid->nent)
2733 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2737 if (nent >= cpuid->nent)
2741 if (copy_to_user(entries, cpuid_entries,
2742 nent * sizeof(struct kvm_cpuid_entry2)))
2748 vfree(cpuid_entries);
2753 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2754 struct kvm_lapic_state *s)
2756 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2761 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2762 struct kvm_lapic_state *s)
2764 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
2765 kvm_apic_post_state_restore(vcpu);
2766 update_cr8_intercept(vcpu);
2771 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2772 struct kvm_interrupt *irq)
2774 if (irq->irq < 0 || irq->irq >= 256)
2776 if (irqchip_in_kernel(vcpu->kvm))
2779 kvm_queue_interrupt(vcpu, irq->irq, false);
2780 kvm_make_request(KVM_REQ_EVENT, vcpu);
2785 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2787 kvm_inject_nmi(vcpu);
2792 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2793 struct kvm_tpr_access_ctl *tac)
2797 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2801 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2805 unsigned bank_num = mcg_cap & 0xff, bank;
2808 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2810 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2813 vcpu->arch.mcg_cap = mcg_cap;
2814 /* Init IA32_MCG_CTL to all 1s */
2815 if (mcg_cap & MCG_CTL_P)
2816 vcpu->arch.mcg_ctl = ~(u64)0;
2817 /* Init IA32_MCi_CTL to all 1s */
2818 for (bank = 0; bank < bank_num; bank++)
2819 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2824 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2825 struct kvm_x86_mce *mce)
2827 u64 mcg_cap = vcpu->arch.mcg_cap;
2828 unsigned bank_num = mcg_cap & 0xff;
2829 u64 *banks = vcpu->arch.mce_banks;
2831 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2834 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2835 * reporting is disabled
2837 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2838 vcpu->arch.mcg_ctl != ~(u64)0)
2840 banks += 4 * mce->bank;
2842 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2843 * reporting is disabled for the bank
2845 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2847 if (mce->status & MCI_STATUS_UC) {
2848 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2849 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2850 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2853 if (banks[1] & MCI_STATUS_VAL)
2854 mce->status |= MCI_STATUS_OVER;
2855 banks[2] = mce->addr;
2856 banks[3] = mce->misc;
2857 vcpu->arch.mcg_status = mce->mcg_status;
2858 banks[1] = mce->status;
2859 kvm_queue_exception(vcpu, MC_VECTOR);
2860 } else if (!(banks[1] & MCI_STATUS_VAL)
2861 || !(banks[1] & MCI_STATUS_UC)) {
2862 if (banks[1] & MCI_STATUS_VAL)
2863 mce->status |= MCI_STATUS_OVER;
2864 banks[2] = mce->addr;
2865 banks[3] = mce->misc;
2866 banks[1] = mce->status;
2868 banks[1] |= MCI_STATUS_OVER;
2872 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2873 struct kvm_vcpu_events *events)
2876 events->exception.injected =
2877 vcpu->arch.exception.pending &&
2878 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2879 events->exception.nr = vcpu->arch.exception.nr;
2880 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2881 events->exception.pad = 0;
2882 events->exception.error_code = vcpu->arch.exception.error_code;
2884 events->interrupt.injected =
2885 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2886 events->interrupt.nr = vcpu->arch.interrupt.nr;
2887 events->interrupt.soft = 0;
2888 events->interrupt.shadow =
2889 kvm_x86_ops->get_interrupt_shadow(vcpu,
2890 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2892 events->nmi.injected = vcpu->arch.nmi_injected;
2893 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2894 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2895 events->nmi.pad = 0;
2897 events->sipi_vector = vcpu->arch.sipi_vector;
2899 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2900 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2901 | KVM_VCPUEVENT_VALID_SHADOW);
2902 memset(&events->reserved, 0, sizeof(events->reserved));
2905 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2906 struct kvm_vcpu_events *events)
2908 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2909 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2910 | KVM_VCPUEVENT_VALID_SHADOW))
2914 vcpu->arch.exception.pending = events->exception.injected;
2915 vcpu->arch.exception.nr = events->exception.nr;
2916 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2917 vcpu->arch.exception.error_code = events->exception.error_code;
2919 vcpu->arch.interrupt.pending = events->interrupt.injected;
2920 vcpu->arch.interrupt.nr = events->interrupt.nr;
2921 vcpu->arch.interrupt.soft = events->interrupt.soft;
2922 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2923 kvm_x86_ops->set_interrupt_shadow(vcpu,
2924 events->interrupt.shadow);
2926 vcpu->arch.nmi_injected = events->nmi.injected;
2927 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2928 vcpu->arch.nmi_pending = events->nmi.pending;
2929 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2931 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2932 vcpu->arch.sipi_vector = events->sipi_vector;
2934 kvm_make_request(KVM_REQ_EVENT, vcpu);
2939 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2940 struct kvm_debugregs *dbgregs)
2942 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2943 dbgregs->dr6 = vcpu->arch.dr6;
2944 dbgregs->dr7 = vcpu->arch.dr7;
2946 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2949 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2950 struct kvm_debugregs *dbgregs)
2955 if (dbgregs->dr6 & ~0xffffffffull)
2957 if (dbgregs->dr7 & ~0xffffffffull)
2960 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2961 vcpu->arch.dr6 = dbgregs->dr6;
2962 vcpu->arch.dr7 = dbgregs->dr7;
2967 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2968 struct kvm_xsave *guest_xsave)
2971 memcpy(guest_xsave->region,
2972 &vcpu->arch.guest_fpu.state->xsave,
2975 memcpy(guest_xsave->region,
2976 &vcpu->arch.guest_fpu.state->fxsave,
2977 sizeof(struct i387_fxsave_struct));
2978 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2983 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2984 struct kvm_xsave *guest_xsave)
2987 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2990 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2991 guest_xsave->region, xstate_size);
2993 if (xstate_bv & ~XSTATE_FPSSE)
2995 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2996 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3001 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3002 struct kvm_xcrs *guest_xcrs)
3004 if (!cpu_has_xsave) {
3005 guest_xcrs->nr_xcrs = 0;
3009 guest_xcrs->nr_xcrs = 1;
3010 guest_xcrs->flags = 0;
3011 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3012 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3015 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3016 struct kvm_xcrs *guest_xcrs)
3023 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3026 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3027 /* Only support XCR0 currently */
3028 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
3029 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3030 guest_xcrs->xcrs[0].value);
3038 long kvm_arch_vcpu_ioctl(struct file *filp,
3039 unsigned int ioctl, unsigned long arg)
3041 struct kvm_vcpu *vcpu = filp->private_data;
3042 void __user *argp = (void __user *)arg;
3045 struct kvm_lapic_state *lapic;
3046 struct kvm_xsave *xsave;
3047 struct kvm_xcrs *xcrs;
3053 case KVM_GET_LAPIC: {
3055 if (!vcpu->arch.apic)
3057 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3062 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3066 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3071 case KVM_SET_LAPIC: {
3073 if (!vcpu->arch.apic)
3075 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3080 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
3082 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3088 case KVM_INTERRUPT: {
3089 struct kvm_interrupt irq;
3092 if (copy_from_user(&irq, argp, sizeof irq))
3094 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3101 r = kvm_vcpu_ioctl_nmi(vcpu);
3107 case KVM_SET_CPUID: {
3108 struct kvm_cpuid __user *cpuid_arg = argp;
3109 struct kvm_cpuid cpuid;
3112 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3114 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3119 case KVM_SET_CPUID2: {
3120 struct kvm_cpuid2 __user *cpuid_arg = argp;
3121 struct kvm_cpuid2 cpuid;
3124 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3126 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3127 cpuid_arg->entries);
3132 case KVM_GET_CPUID2: {
3133 struct kvm_cpuid2 __user *cpuid_arg = argp;
3134 struct kvm_cpuid2 cpuid;
3137 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3139 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3140 cpuid_arg->entries);
3144 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3150 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3153 r = msr_io(vcpu, argp, do_set_msr, 0);
3155 case KVM_TPR_ACCESS_REPORTING: {
3156 struct kvm_tpr_access_ctl tac;
3159 if (copy_from_user(&tac, argp, sizeof tac))
3161 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3165 if (copy_to_user(argp, &tac, sizeof tac))
3170 case KVM_SET_VAPIC_ADDR: {
3171 struct kvm_vapic_addr va;
3174 if (!irqchip_in_kernel(vcpu->kvm))
3177 if (copy_from_user(&va, argp, sizeof va))
3179 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3182 case KVM_X86_SETUP_MCE: {
3186 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3188 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3191 case KVM_X86_SET_MCE: {
3192 struct kvm_x86_mce mce;
3195 if (copy_from_user(&mce, argp, sizeof mce))
3197 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3200 case KVM_GET_VCPU_EVENTS: {
3201 struct kvm_vcpu_events events;
3203 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3206 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3211 case KVM_SET_VCPU_EVENTS: {
3212 struct kvm_vcpu_events events;
3215 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3218 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3221 case KVM_GET_DEBUGREGS: {
3222 struct kvm_debugregs dbgregs;
3224 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3227 if (copy_to_user(argp, &dbgregs,
3228 sizeof(struct kvm_debugregs)))
3233 case KVM_SET_DEBUGREGS: {
3234 struct kvm_debugregs dbgregs;
3237 if (copy_from_user(&dbgregs, argp,
3238 sizeof(struct kvm_debugregs)))
3241 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3244 case KVM_GET_XSAVE: {
3245 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3250 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3253 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3258 case KVM_SET_XSAVE: {
3259 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3265 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
3268 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3271 case KVM_GET_XCRS: {
3272 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3277 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3280 if (copy_to_user(argp, u.xcrs,
3281 sizeof(struct kvm_xcrs)))
3286 case KVM_SET_XCRS: {
3287 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3293 if (copy_from_user(u.xcrs, argp,
3294 sizeof(struct kvm_xcrs)))
3297 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3300 case KVM_SET_TSC_KHZ: {
3304 if (!kvm_has_tsc_control)
3307 user_tsc_khz = (u32)arg;
3309 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3312 kvm_x86_ops->set_tsc_khz(vcpu, user_tsc_khz);
3317 case KVM_GET_TSC_KHZ: {
3319 if (check_tsc_unstable())
3322 r = vcpu_tsc_khz(vcpu);
3334 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3338 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3340 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3344 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3347 kvm->arch.ept_identity_map_addr = ident_addr;
3351 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3352 u32 kvm_nr_mmu_pages)
3354 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3357 mutex_lock(&kvm->slots_lock);
3358 spin_lock(&kvm->mmu_lock);
3360 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3361 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3363 spin_unlock(&kvm->mmu_lock);
3364 mutex_unlock(&kvm->slots_lock);
3368 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3370 return kvm->arch.n_max_mmu_pages;
3373 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3378 switch (chip->chip_id) {
3379 case KVM_IRQCHIP_PIC_MASTER:
3380 memcpy(&chip->chip.pic,
3381 &pic_irqchip(kvm)->pics[0],
3382 sizeof(struct kvm_pic_state));
3384 case KVM_IRQCHIP_PIC_SLAVE:
3385 memcpy(&chip->chip.pic,
3386 &pic_irqchip(kvm)->pics[1],
3387 sizeof(struct kvm_pic_state));
3389 case KVM_IRQCHIP_IOAPIC:
3390 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3399 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3404 switch (chip->chip_id) {
3405 case KVM_IRQCHIP_PIC_MASTER:
3406 spin_lock(&pic_irqchip(kvm)->lock);
3407 memcpy(&pic_irqchip(kvm)->pics[0],
3409 sizeof(struct kvm_pic_state));
3410 spin_unlock(&pic_irqchip(kvm)->lock);
3412 case KVM_IRQCHIP_PIC_SLAVE:
3413 spin_lock(&pic_irqchip(kvm)->lock);
3414 memcpy(&pic_irqchip(kvm)->pics[1],
3416 sizeof(struct kvm_pic_state));
3417 spin_unlock(&pic_irqchip(kvm)->lock);
3419 case KVM_IRQCHIP_IOAPIC:
3420 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3426 kvm_pic_update_irq(pic_irqchip(kvm));
3430 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3434 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3435 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3436 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3440 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3444 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3445 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3446 for (i = 0; i < 3; i++)
3447 kvm_pit_load_count(kvm, i, ps->channels[i].count, 0);
3448 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3452 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3456 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3457 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3458 sizeof(ps->channels));
3459 ps->flags = kvm->arch.vpit->pit_state.flags;
3460 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3461 memset(&ps->reserved, 0, sizeof(ps->reserved));
3465 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3467 int r = 0, start = 0;
3469 u32 prev_legacy, cur_legacy;
3470 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3471 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3472 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3473 if (!prev_legacy && cur_legacy)
3475 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3476 sizeof(kvm->arch.vpit->pit_state.channels));
3477 kvm->arch.vpit->pit_state.flags = ps->flags;
3478 for (i = 0; i < 3; i++)
3479 kvm_pit_load_count(kvm, i, kvm->arch.vpit->pit_state.channels[i].count,
3481 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3485 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3486 struct kvm_reinject_control *control)
3488 if (!kvm->arch.vpit)
3490 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3491 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
3492 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3497 * Get (and clear) the dirty memory log for a memory slot.
3499 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3500 struct kvm_dirty_log *log)
3503 struct kvm_memory_slot *memslot;
3505 unsigned long is_dirty = 0;
3507 mutex_lock(&kvm->slots_lock);
3510 if (log->slot >= KVM_MEMORY_SLOTS)
3513 memslot = &kvm->memslots->memslots[log->slot];
3515 if (!memslot->dirty_bitmap)
3518 n = kvm_dirty_bitmap_bytes(memslot);
3520 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3521 is_dirty = memslot->dirty_bitmap[i];
3523 /* If nothing is dirty, don't bother messing with page tables. */
3525 struct kvm_memslots *slots, *old_slots;
3526 unsigned long *dirty_bitmap;
3528 dirty_bitmap = memslot->dirty_bitmap_head;
3529 if (memslot->dirty_bitmap == dirty_bitmap)
3530 dirty_bitmap += n / sizeof(long);
3531 memset(dirty_bitmap, 0, n);
3534 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
3537 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3538 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
3539 slots->generation++;
3541 old_slots = kvm->memslots;
3542 rcu_assign_pointer(kvm->memslots, slots);
3543 synchronize_srcu_expedited(&kvm->srcu);
3544 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3547 spin_lock(&kvm->mmu_lock);
3548 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3549 spin_unlock(&kvm->mmu_lock);
3552 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
3556 if (clear_user(log->dirty_bitmap, n))
3562 mutex_unlock(&kvm->slots_lock);
3566 long kvm_arch_vm_ioctl(struct file *filp,
3567 unsigned int ioctl, unsigned long arg)
3569 struct kvm *kvm = filp->private_data;
3570 void __user *argp = (void __user *)arg;
3573 * This union makes it completely explicit to gcc-3.x
3574 * that these two variables' stack usage should be
3575 * combined, not added together.
3578 struct kvm_pit_state ps;
3579 struct kvm_pit_state2 ps2;
3580 struct kvm_pit_config pit_config;
3584 case KVM_SET_TSS_ADDR:
3585 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3589 case KVM_SET_IDENTITY_MAP_ADDR: {
3593 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3595 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3600 case KVM_SET_NR_MMU_PAGES:
3601 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3605 case KVM_GET_NR_MMU_PAGES:
3606 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3608 case KVM_CREATE_IRQCHIP: {
3609 struct kvm_pic *vpic;
3611 mutex_lock(&kvm->lock);
3614 goto create_irqchip_unlock;
3616 if (atomic_read(&kvm->online_vcpus))
3617 goto create_irqchip_unlock;
3619 vpic = kvm_create_pic(kvm);
3621 r = kvm_ioapic_init(kvm);
3623 mutex_lock(&kvm->slots_lock);
3624 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3626 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3628 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3630 mutex_unlock(&kvm->slots_lock);
3632 goto create_irqchip_unlock;
3635 goto create_irqchip_unlock;
3637 kvm->arch.vpic = vpic;
3639 r = kvm_setup_default_irq_routing(kvm);
3641 mutex_lock(&kvm->slots_lock);
3642 mutex_lock(&kvm->irq_lock);
3643 kvm_ioapic_destroy(kvm);
3644 kvm_destroy_pic(kvm);
3645 mutex_unlock(&kvm->irq_lock);
3646 mutex_unlock(&kvm->slots_lock);
3648 create_irqchip_unlock:
3649 mutex_unlock(&kvm->lock);
3652 case KVM_CREATE_PIT:
3653 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3655 case KVM_CREATE_PIT2:
3657 if (copy_from_user(&u.pit_config, argp,
3658 sizeof(struct kvm_pit_config)))
3661 mutex_lock(&kvm->slots_lock);
3664 goto create_pit_unlock;
3666 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3670 mutex_unlock(&kvm->slots_lock);
3672 case KVM_IRQ_LINE_STATUS:
3673 case KVM_IRQ_LINE: {
3674 struct kvm_irq_level irq_event;
3677 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3680 if (irqchip_in_kernel(kvm)) {
3682 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3683 irq_event.irq, irq_event.level);
3684 if (ioctl == KVM_IRQ_LINE_STATUS) {
3686 irq_event.status = status;
3687 if (copy_to_user(argp, &irq_event,
3695 case KVM_GET_IRQCHIP: {
3696 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3697 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
3703 if (copy_from_user(chip, argp, sizeof *chip))
3704 goto get_irqchip_out;
3706 if (!irqchip_in_kernel(kvm))
3707 goto get_irqchip_out;
3708 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3710 goto get_irqchip_out;
3712 if (copy_to_user(argp, chip, sizeof *chip))
3713 goto get_irqchip_out;
3721 case KVM_SET_IRQCHIP: {
3722 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3723 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
3729 if (copy_from_user(chip, argp, sizeof *chip))
3730 goto set_irqchip_out;
3732 if (!irqchip_in_kernel(kvm))
3733 goto set_irqchip_out;
3734 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3736 goto set_irqchip_out;
3746 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3749 if (!kvm->arch.vpit)
3751 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3755 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3762 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3765 if (!kvm->arch.vpit)
3767 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3773 case KVM_GET_PIT2: {
3775 if (!kvm->arch.vpit)
3777 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3781 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3786 case KVM_SET_PIT2: {
3788 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3791 if (!kvm->arch.vpit)
3793 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3799 case KVM_REINJECT_CONTROL: {
3800 struct kvm_reinject_control control;
3802 if (copy_from_user(&control, argp, sizeof(control)))
3804 r = kvm_vm_ioctl_reinject(kvm, &control);
3810 case KVM_XEN_HVM_CONFIG: {
3812 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3813 sizeof(struct kvm_xen_hvm_config)))
3816 if (kvm->arch.xen_hvm_config.flags)
3821 case KVM_SET_CLOCK: {
3822 struct kvm_clock_data user_ns;
3827 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3835 local_irq_disable();
3836 now_ns = get_kernel_ns();
3837 delta = user_ns.clock - now_ns;
3839 kvm->arch.kvmclock_offset = delta;
3842 case KVM_GET_CLOCK: {
3843 struct kvm_clock_data user_ns;
3846 local_irq_disable();
3847 now_ns = get_kernel_ns();
3848 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3851 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3854 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3867 static void kvm_init_msr_list(void)
3872 /* skip the first msrs in the list. KVM-specific */
3873 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3874 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3878 * Even MSRs that are valid in the host may not be exposed
3879 * to the guests in some cases.
3881 switch (msrs_to_save[i]) {
3883 if (!kvm_x86_ops->rdtscp_supported())
3891 msrs_to_save[j] = msrs_to_save[i];
3894 num_msrs_to_save = j;
3897 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3905 if (!(vcpu->arch.apic &&
3906 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3907 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3918 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3925 if (!(vcpu->arch.apic &&
3926 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3927 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3929 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3939 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3940 struct kvm_segment *var, int seg)
3942 kvm_x86_ops->set_segment(vcpu, var, seg);
3945 void kvm_get_segment(struct kvm_vcpu *vcpu,
3946 struct kvm_segment *var, int seg)
3948 kvm_x86_ops->get_segment(vcpu, var, seg);
3951 static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3956 static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3959 struct x86_exception exception;
3961 BUG_ON(!mmu_is_nested(vcpu));
3963 /* NPT walks are always user-walks */
3964 access |= PFERR_USER_MASK;
3965 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3970 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3971 struct x86_exception *exception)
3973 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3974 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3977 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3978 struct x86_exception *exception)
3980 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3981 access |= PFERR_FETCH_MASK;
3982 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3985 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3986 struct x86_exception *exception)
3988 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3989 access |= PFERR_WRITE_MASK;
3990 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3993 /* uses this to access any guest's mapped memory without checking CPL */
3994 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3995 struct x86_exception *exception)
3997 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
4000 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4001 struct kvm_vcpu *vcpu, u32 access,
4002 struct x86_exception *exception)
4005 int r = X86EMUL_CONTINUE;
4008 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
4010 unsigned offset = addr & (PAGE_SIZE-1);
4011 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
4014 if (gpa == UNMAPPED_GVA)
4015 return X86EMUL_PROPAGATE_FAULT;
4016 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
4018 r = X86EMUL_IO_NEEDED;
4030 /* used for instruction fetching */
4031 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4032 gva_t addr, void *val, unsigned int bytes,
4033 struct x86_exception *exception)
4035 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4036 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4038 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
4039 access | PFERR_FETCH_MASK,
4043 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4044 gva_t addr, void *val, unsigned int bytes,
4045 struct x86_exception *exception)
4047 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4048 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4050 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4053 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4055 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4056 gva_t addr, void *val, unsigned int bytes,
4057 struct x86_exception *exception)
4059 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4060 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4063 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4064 gva_t addr, void *val,
4066 struct x86_exception *exception)
4068 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4070 int r = X86EMUL_CONTINUE;
4073 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4076 unsigned offset = addr & (PAGE_SIZE-1);
4077 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4080 if (gpa == UNMAPPED_GVA)
4081 return X86EMUL_PROPAGATE_FAULT;
4082 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4084 r = X86EMUL_IO_NEEDED;
4095 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4097 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4098 gpa_t *gpa, struct x86_exception *exception,
4101 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4103 if (vcpu_match_mmio_gva(vcpu, gva) &&
4104 check_write_user_access(vcpu, write, access,
4105 vcpu->arch.access)) {
4106 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4107 (gva & (PAGE_SIZE - 1));
4108 trace_vcpu_match_mmio(gva, *gpa, write, false);
4113 access |= PFERR_WRITE_MASK;
4115 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4117 if (*gpa == UNMAPPED_GVA)
4120 /* For APIC access vmexit */
4121 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4124 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4125 trace_vcpu_match_mmio(gva, *gpa, write, true);
4132 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4133 const void *val, int bytes)
4137 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4140 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
4144 struct read_write_emulator_ops {
4145 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4147 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4148 void *val, int bytes);
4149 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4150 int bytes, void *val);
4151 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4152 void *val, int bytes);
4156 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4158 if (vcpu->mmio_read_completed) {
4159 memcpy(val, vcpu->mmio_data, bytes);
4160 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4161 vcpu->mmio_phys_addr, *(u64 *)val);
4162 vcpu->mmio_read_completed = 0;
4169 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4170 void *val, int bytes)
4172 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4175 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4176 void *val, int bytes)
4178 return emulator_write_phys(vcpu, gpa, val, bytes);
4181 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4183 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4184 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4187 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4188 void *val, int bytes)
4190 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4191 return X86EMUL_IO_NEEDED;
4194 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4195 void *val, int bytes)
4197 memcpy(vcpu->mmio_data, val, bytes);
4198 memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8);
4199 return X86EMUL_CONTINUE;
4202 static struct read_write_emulator_ops read_emultor = {
4203 .read_write_prepare = read_prepare,
4204 .read_write_emulate = read_emulate,
4205 .read_write_mmio = vcpu_mmio_read,
4206 .read_write_exit_mmio = read_exit_mmio,
4209 static struct read_write_emulator_ops write_emultor = {
4210 .read_write_emulate = write_emulate,
4211 .read_write_mmio = write_mmio,
4212 .read_write_exit_mmio = write_exit_mmio,
4216 static int emulator_read_write_onepage(unsigned long addr, void *val,
4218 struct x86_exception *exception,
4219 struct kvm_vcpu *vcpu,
4220 struct read_write_emulator_ops *ops)
4224 bool write = ops->write;
4226 if (ops->read_write_prepare &&
4227 ops->read_write_prepare(vcpu, val, bytes))
4228 return X86EMUL_CONTINUE;
4230 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4233 return X86EMUL_PROPAGATE_FAULT;
4235 /* For APIC access vmexit */
4239 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4240 return X86EMUL_CONTINUE;
4244 * Is this MMIO handled locally?
4246 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4247 if (handled == bytes)
4248 return X86EMUL_CONTINUE;
4254 vcpu->mmio_needed = 1;
4255 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4256 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
4257 vcpu->mmio_size = bytes;
4258 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
4259 vcpu->run->mmio.is_write = vcpu->mmio_is_write = write;
4260 vcpu->mmio_index = 0;
4262 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4265 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4266 void *val, unsigned int bytes,
4267 struct x86_exception *exception,
4268 struct read_write_emulator_ops *ops)
4270 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4272 /* Crossing a page boundary? */
4273 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4276 now = -addr & ~PAGE_MASK;
4277 rc = emulator_read_write_onepage(addr, val, now, exception,
4280 if (rc != X86EMUL_CONTINUE)
4287 return emulator_read_write_onepage(addr, val, bytes, exception,
4291 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4295 struct x86_exception *exception)
4297 return emulator_read_write(ctxt, addr, val, bytes,
4298 exception, &read_emultor);
4301 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4305 struct x86_exception *exception)
4307 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4308 exception, &write_emultor);
4311 #define CMPXCHG_TYPE(t, ptr, old, new) \
4312 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4314 #ifdef CONFIG_X86_64
4315 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4317 # define CMPXCHG64(ptr, old, new) \
4318 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4321 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4326 struct x86_exception *exception)
4328 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4334 /* guests cmpxchg8b have to be emulated atomically */
4335 if (bytes > 8 || (bytes & (bytes - 1)))
4338 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4340 if (gpa == UNMAPPED_GVA ||
4341 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4344 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4347 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4348 if (is_error_page(page)) {
4349 kvm_release_page_clean(page);
4353 kaddr = kmap_atomic(page, KM_USER0);
4354 kaddr += offset_in_page(gpa);
4357 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4360 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4363 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4366 exchanged = CMPXCHG64(kaddr, old, new);
4371 kunmap_atomic(kaddr, KM_USER0);
4372 kvm_release_page_dirty(page);
4375 return X86EMUL_CMPXCHG_FAILED;
4377 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
4379 return X86EMUL_CONTINUE;
4382 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4384 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4387 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4389 /* TODO: String I/O for in kernel device */
4392 if (vcpu->arch.pio.in)
4393 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4394 vcpu->arch.pio.size, pd);
4396 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4397 vcpu->arch.pio.port, vcpu->arch.pio.size,
4403 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4404 int size, unsigned short port, void *val,
4407 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4409 if (vcpu->arch.pio.count)
4412 trace_kvm_pio(0, port, size, count);
4414 vcpu->arch.pio.port = port;
4415 vcpu->arch.pio.in = 1;
4416 vcpu->arch.pio.count = count;
4417 vcpu->arch.pio.size = size;
4419 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4421 memcpy(val, vcpu->arch.pio_data, size * count);
4422 vcpu->arch.pio.count = 0;
4426 vcpu->run->exit_reason = KVM_EXIT_IO;
4427 vcpu->run->io.direction = KVM_EXIT_IO_IN;
4428 vcpu->run->io.size = size;
4429 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4430 vcpu->run->io.count = count;
4431 vcpu->run->io.port = port;
4436 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4437 int size, unsigned short port,
4438 const void *val, unsigned int count)
4440 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4442 trace_kvm_pio(1, port, size, count);
4444 vcpu->arch.pio.port = port;
4445 vcpu->arch.pio.in = 0;
4446 vcpu->arch.pio.count = count;
4447 vcpu->arch.pio.size = size;
4449 memcpy(vcpu->arch.pio_data, val, size * count);
4451 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4452 vcpu->arch.pio.count = 0;
4456 vcpu->run->exit_reason = KVM_EXIT_IO;
4457 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
4458 vcpu->run->io.size = size;
4459 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4460 vcpu->run->io.count = count;
4461 vcpu->run->io.port = port;
4466 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4468 return kvm_x86_ops->get_segment_base(vcpu, seg);
4471 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4473 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4476 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4478 if (!need_emulate_wbinvd(vcpu))
4479 return X86EMUL_CONTINUE;
4481 if (kvm_x86_ops->has_wbinvd_exit()) {
4482 int cpu = get_cpu();
4484 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4485 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4486 wbinvd_ipi, NULL, 1);
4488 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4491 return X86EMUL_CONTINUE;
4493 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4495 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4497 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4500 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4502 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4505 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4508 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4511 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4513 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4516 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4518 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4519 unsigned long value;
4523 value = kvm_read_cr0(vcpu);
4526 value = vcpu->arch.cr2;
4529 value = kvm_read_cr3(vcpu);
4532 value = kvm_read_cr4(vcpu);
4535 value = kvm_get_cr8(vcpu);
4538 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4545 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4547 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4552 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4555 vcpu->arch.cr2 = val;
4558 res = kvm_set_cr3(vcpu, val);
4561 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4564 res = kvm_set_cr8(vcpu, val);
4567 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4574 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4576 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4579 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4581 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4584 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4586 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4589 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4591 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4594 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4596 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4599 static unsigned long emulator_get_cached_segment_base(
4600 struct x86_emulate_ctxt *ctxt, int seg)
4602 return get_segment_base(emul_to_vcpu(ctxt), seg);
4605 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4606 struct desc_struct *desc, u32 *base3,
4609 struct kvm_segment var;
4611 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4612 *selector = var.selector;
4619 set_desc_limit(desc, var.limit);
4620 set_desc_base(desc, (unsigned long)var.base);
4621 #ifdef CONFIG_X86_64
4623 *base3 = var.base >> 32;
4625 desc->type = var.type;
4627 desc->dpl = var.dpl;
4628 desc->p = var.present;
4629 desc->avl = var.avl;
4637 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4638 struct desc_struct *desc, u32 base3,
4641 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4642 struct kvm_segment var;
4644 var.selector = selector;
4645 var.base = get_desc_base(desc);
4646 #ifdef CONFIG_X86_64
4647 var.base |= ((u64)base3) << 32;
4649 var.limit = get_desc_limit(desc);
4651 var.limit = (var.limit << 12) | 0xfff;
4652 var.type = desc->type;
4653 var.present = desc->p;
4654 var.dpl = desc->dpl;
4659 var.avl = desc->avl;
4660 var.present = desc->p;
4661 var.unusable = !var.present;
4664 kvm_set_segment(vcpu, &var, seg);
4668 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4669 u32 msr_index, u64 *pdata)
4671 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4674 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4675 u32 msr_index, u64 data)
4677 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4680 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4682 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4685 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4688 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4690 * CR0.TS may reference the host fpu state, not the guest fpu state,
4691 * so it may be clear at this point.
4696 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4701 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4702 struct x86_instruction_info *info,
4703 enum x86_intercept_stage stage)
4705 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4708 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4709 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4711 struct kvm_cpuid_entry2 *cpuid = NULL;
4714 cpuid = kvm_find_cpuid_entry(emul_to_vcpu(ctxt),
4730 static struct x86_emulate_ops emulate_ops = {
4731 .read_std = kvm_read_guest_virt_system,
4732 .write_std = kvm_write_guest_virt_system,
4733 .fetch = kvm_fetch_guest_virt,
4734 .read_emulated = emulator_read_emulated,
4735 .write_emulated = emulator_write_emulated,
4736 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4737 .invlpg = emulator_invlpg,
4738 .pio_in_emulated = emulator_pio_in_emulated,
4739 .pio_out_emulated = emulator_pio_out_emulated,
4740 .get_segment = emulator_get_segment,
4741 .set_segment = emulator_set_segment,
4742 .get_cached_segment_base = emulator_get_cached_segment_base,
4743 .get_gdt = emulator_get_gdt,
4744 .get_idt = emulator_get_idt,
4745 .set_gdt = emulator_set_gdt,
4746 .set_idt = emulator_set_idt,
4747 .get_cr = emulator_get_cr,
4748 .set_cr = emulator_set_cr,
4749 .cpl = emulator_get_cpl,
4750 .get_dr = emulator_get_dr,
4751 .set_dr = emulator_set_dr,
4752 .set_msr = emulator_set_msr,
4753 .get_msr = emulator_get_msr,
4754 .halt = emulator_halt,
4755 .wbinvd = emulator_wbinvd,
4756 .fix_hypercall = emulator_fix_hypercall,
4757 .get_fpu = emulator_get_fpu,
4758 .put_fpu = emulator_put_fpu,
4759 .intercept = emulator_intercept,
4760 .get_cpuid = emulator_get_cpuid,
4763 static void cache_all_regs(struct kvm_vcpu *vcpu)
4765 kvm_register_read(vcpu, VCPU_REGS_RAX);
4766 kvm_register_read(vcpu, VCPU_REGS_RSP);
4767 kvm_register_read(vcpu, VCPU_REGS_RIP);
4768 vcpu->arch.regs_dirty = ~0;
4771 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4773 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4775 * an sti; sti; sequence only disable interrupts for the first
4776 * instruction. So, if the last instruction, be it emulated or
4777 * not, left the system with the INT_STI flag enabled, it
4778 * means that the last instruction is an sti. We should not
4779 * leave the flag on in this case. The same goes for mov ss
4781 if (!(int_shadow & mask))
4782 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4785 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4787 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4788 if (ctxt->exception.vector == PF_VECTOR)
4789 kvm_propagate_fault(vcpu, &ctxt->exception);
4790 else if (ctxt->exception.error_code_valid)
4791 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4792 ctxt->exception.error_code);
4794 kvm_queue_exception(vcpu, ctxt->exception.vector);
4797 static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
4798 const unsigned long *regs)
4800 memset(&ctxt->twobyte, 0,
4801 (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4802 memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
4804 ctxt->fetch.start = 0;
4805 ctxt->fetch.end = 0;
4806 ctxt->io_read.pos = 0;
4807 ctxt->io_read.end = 0;
4808 ctxt->mem_read.pos = 0;
4809 ctxt->mem_read.end = 0;
4812 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4814 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4818 * TODO: fix emulate.c to use guest_read/write_register
4819 * instead of direct ->regs accesses, can save hundred cycles
4820 * on Intel for instructions that don't read/change RSP, for
4823 cache_all_regs(vcpu);
4825 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4827 ctxt->eflags = kvm_get_rflags(vcpu);
4828 ctxt->eip = kvm_rip_read(vcpu);
4829 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4830 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4831 cs_l ? X86EMUL_MODE_PROT64 :
4832 cs_db ? X86EMUL_MODE_PROT32 :
4833 X86EMUL_MODE_PROT16;
4834 ctxt->guest_mode = is_guest_mode(vcpu);
4836 init_decode_cache(ctxt, vcpu->arch.regs);
4837 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4840 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4842 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4845 init_emulate_ctxt(vcpu);
4849 ctxt->_eip = ctxt->eip + inc_eip;
4850 ret = emulate_int_real(ctxt, irq);
4852 if (ret != X86EMUL_CONTINUE)
4853 return EMULATE_FAIL;
4855 ctxt->eip = ctxt->_eip;
4856 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
4857 kvm_rip_write(vcpu, ctxt->eip);
4858 kvm_set_rflags(vcpu, ctxt->eflags);
4860 if (irq == NMI_VECTOR)
4861 vcpu->arch.nmi_pending = 0;
4863 vcpu->arch.interrupt.pending = false;
4865 return EMULATE_DONE;
4867 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4869 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4871 int r = EMULATE_DONE;
4873 ++vcpu->stat.insn_emulation_fail;
4874 trace_kvm_emulate_insn_failed(vcpu);
4875 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
4876 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4877 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4878 vcpu->run->internal.ndata = 0;
4881 kvm_queue_exception(vcpu, UD_VECTOR);
4886 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4894 * if emulation was due to access to shadowed page table
4895 * and it failed try to unshadow page and re-entetr the
4896 * guest to let CPU execute the instruction.
4898 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4901 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4903 if (gpa == UNMAPPED_GVA)
4904 return true; /* let cpu generate fault */
4906 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4912 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4919 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4920 bool writeback = true;
4922 kvm_clear_exception_queue(vcpu);
4924 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
4925 init_emulate_ctxt(vcpu);
4926 ctxt->interruptibility = 0;
4927 ctxt->have_exception = false;
4928 ctxt->perm_ok = false;
4930 ctxt->only_vendor_specific_insn
4931 = emulation_type & EMULTYPE_TRAP_UD;
4933 r = x86_decode_insn(ctxt, insn, insn_len);
4935 trace_kvm_emulate_insn_start(vcpu);
4936 ++vcpu->stat.insn_emulation;
4937 if (r != EMULATION_OK) {
4938 if (emulation_type & EMULTYPE_TRAP_UD)
4939 return EMULATE_FAIL;
4940 if (reexecute_instruction(vcpu, cr2))
4941 return EMULATE_DONE;
4942 if (emulation_type & EMULTYPE_SKIP)
4943 return EMULATE_FAIL;
4944 return handle_emulation_failure(vcpu);
4948 if (emulation_type & EMULTYPE_SKIP) {
4949 kvm_rip_write(vcpu, ctxt->_eip);
4950 return EMULATE_DONE;
4953 /* this is needed for vmware backdoor interface to work since it
4954 changes registers values during IO operation */
4955 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4956 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4957 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
4961 r = x86_emulate_insn(ctxt);
4963 if (r == EMULATION_INTERCEPTED)
4964 return EMULATE_DONE;
4966 if (r == EMULATION_FAILED) {
4967 if (reexecute_instruction(vcpu, cr2))
4968 return EMULATE_DONE;
4970 return handle_emulation_failure(vcpu);
4973 if (ctxt->have_exception) {
4974 inject_emulated_exception(vcpu);
4976 } else if (vcpu->arch.pio.count) {
4977 if (!vcpu->arch.pio.in)
4978 vcpu->arch.pio.count = 0;
4981 r = EMULATE_DO_MMIO;
4982 } else if (vcpu->mmio_needed) {
4983 if (!vcpu->mmio_is_write)
4985 r = EMULATE_DO_MMIO;
4986 } else if (r == EMULATION_RESTART)
4992 toggle_interruptibility(vcpu, ctxt->interruptibility);
4993 kvm_set_rflags(vcpu, ctxt->eflags);
4994 kvm_make_request(KVM_REQ_EVENT, vcpu);
4995 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
4996 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
4997 kvm_rip_write(vcpu, ctxt->eip);
4999 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5003 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5005 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5007 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5008 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5009 size, port, &val, 1);
5010 /* do not return to emulator after return from userspace */
5011 vcpu->arch.pio.count = 0;
5014 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5016 static void tsc_bad(void *info)
5018 __this_cpu_write(cpu_tsc_khz, 0);
5021 static void tsc_khz_changed(void *data)
5023 struct cpufreq_freqs *freq = data;
5024 unsigned long khz = 0;
5028 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5029 khz = cpufreq_quick_get(raw_smp_processor_id());
5032 __this_cpu_write(cpu_tsc_khz, khz);
5035 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5038 struct cpufreq_freqs *freq = data;
5040 struct kvm_vcpu *vcpu;
5041 int i, send_ipi = 0;
5044 * We allow guests to temporarily run on slowing clocks,
5045 * provided we notify them after, or to run on accelerating
5046 * clocks, provided we notify them before. Thus time never
5049 * However, we have a problem. We can't atomically update
5050 * the frequency of a given CPU from this function; it is
5051 * merely a notifier, which can be called from any CPU.
5052 * Changing the TSC frequency at arbitrary points in time
5053 * requires a recomputation of local variables related to
5054 * the TSC for each VCPU. We must flag these local variables
5055 * to be updated and be sure the update takes place with the
5056 * new frequency before any guests proceed.
5058 * Unfortunately, the combination of hotplug CPU and frequency
5059 * change creates an intractable locking scenario; the order
5060 * of when these callouts happen is undefined with respect to
5061 * CPU hotplug, and they can race with each other. As such,
5062 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5063 * undefined; you can actually have a CPU frequency change take
5064 * place in between the computation of X and the setting of the
5065 * variable. To protect against this problem, all updates of
5066 * the per_cpu tsc_khz variable are done in an interrupt
5067 * protected IPI, and all callers wishing to update the value
5068 * must wait for a synchronous IPI to complete (which is trivial
5069 * if the caller is on the CPU already). This establishes the
5070 * necessary total order on variable updates.
5072 * Note that because a guest time update may take place
5073 * anytime after the setting of the VCPU's request bit, the
5074 * correct TSC value must be set before the request. However,
5075 * to ensure the update actually makes it to any guest which
5076 * starts running in hardware virtualization between the set
5077 * and the acquisition of the spinlock, we must also ping the
5078 * CPU after setting the request bit.
5082 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5084 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5087 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5089 raw_spin_lock(&kvm_lock);
5090 list_for_each_entry(kvm, &vm_list, vm_list) {
5091 kvm_for_each_vcpu(i, vcpu, kvm) {
5092 if (vcpu->cpu != freq->cpu)
5094 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5095 if (vcpu->cpu != smp_processor_id())
5099 raw_spin_unlock(&kvm_lock);
5101 if (freq->old < freq->new && send_ipi) {
5103 * We upscale the frequency. Must make the guest
5104 * doesn't see old kvmclock values while running with
5105 * the new frequency, otherwise we risk the guest sees
5106 * time go backwards.
5108 * In case we update the frequency for another cpu
5109 * (which might be in guest context) send an interrupt
5110 * to kick the cpu out of guest context. Next time
5111 * guest context is entered kvmclock will be updated,
5112 * so the guest will not see stale values.
5114 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5119 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5120 .notifier_call = kvmclock_cpufreq_notifier
5123 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5124 unsigned long action, void *hcpu)
5126 unsigned int cpu = (unsigned long)hcpu;
5130 case CPU_DOWN_FAILED:
5131 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5133 case CPU_DOWN_PREPARE:
5134 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5140 static struct notifier_block kvmclock_cpu_notifier_block = {
5141 .notifier_call = kvmclock_cpu_notifier,
5142 .priority = -INT_MAX
5145 static void kvm_timer_init(void)
5149 max_tsc_khz = tsc_khz;
5150 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5151 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5152 #ifdef CONFIG_CPU_FREQ
5153 struct cpufreq_policy policy;
5154 memset(&policy, 0, sizeof(policy));
5156 cpufreq_get_policy(&policy, cpu);
5157 if (policy.cpuinfo.max_freq)
5158 max_tsc_khz = policy.cpuinfo.max_freq;
5161 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5162 CPUFREQ_TRANSITION_NOTIFIER);
5164 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5165 for_each_online_cpu(cpu)
5166 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5169 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5171 static int kvm_is_in_guest(void)
5173 return percpu_read(current_vcpu) != NULL;
5176 static int kvm_is_user_mode(void)
5180 if (percpu_read(current_vcpu))
5181 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
5183 return user_mode != 0;
5186 static unsigned long kvm_get_guest_ip(void)
5188 unsigned long ip = 0;
5190 if (percpu_read(current_vcpu))
5191 ip = kvm_rip_read(percpu_read(current_vcpu));
5196 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5197 .is_in_guest = kvm_is_in_guest,
5198 .is_user_mode = kvm_is_user_mode,
5199 .get_guest_ip = kvm_get_guest_ip,
5202 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5204 percpu_write(current_vcpu, vcpu);
5206 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5208 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5210 percpu_write(current_vcpu, NULL);
5212 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5214 static void kvm_set_mmio_spte_mask(void)
5217 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5220 * Set the reserved bits and the present bit of an paging-structure
5221 * entry to generate page fault with PFER.RSV = 1.
5223 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
5226 #ifdef CONFIG_X86_64
5228 * If reserved bit is not supported, clear the present bit to disable
5231 if (maxphyaddr == 52)
5235 kvm_mmu_set_mmio_spte_mask(mask);
5238 int kvm_arch_init(void *opaque)
5241 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
5244 printk(KERN_ERR "kvm: already loaded the other module\n");
5249 if (!ops->cpu_has_kvm_support()) {
5250 printk(KERN_ERR "kvm: no hardware support\n");
5254 if (ops->disabled_by_bios()) {
5255 printk(KERN_ERR "kvm: disabled by bios\n");
5260 r = kvm_mmu_module_init();
5264 kvm_set_mmio_spte_mask();
5267 kvm_init_msr_list();
5269 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5270 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5274 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5277 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5285 void kvm_arch_exit(void)
5287 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5289 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5290 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5291 CPUFREQ_TRANSITION_NOTIFIER);
5292 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5294 kvm_mmu_module_exit();
5297 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5299 ++vcpu->stat.halt_exits;
5300 if (irqchip_in_kernel(vcpu->kvm)) {
5301 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5304 vcpu->run->exit_reason = KVM_EXIT_HLT;
5308 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5310 static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
5313 if (is_long_mode(vcpu))
5316 return a0 | ((gpa_t)a1 << 32);
5319 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5321 u64 param, ingpa, outgpa, ret;
5322 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5323 bool fast, longmode;
5327 * hypercall generates UD from non zero cpl and real mode
5330 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5331 kvm_queue_exception(vcpu, UD_VECTOR);
5335 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5336 longmode = is_long_mode(vcpu) && cs_l == 1;
5339 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5340 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5341 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5342 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5343 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5344 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5346 #ifdef CONFIG_X86_64
5348 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5349 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5350 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5354 code = param & 0xffff;
5355 fast = (param >> 16) & 0x1;
5356 rep_cnt = (param >> 32) & 0xfff;
5357 rep_idx = (param >> 48) & 0xfff;
5359 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5362 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5363 kvm_vcpu_on_spin(vcpu);
5366 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5370 ret = res | (((u64)rep_done & 0xfff) << 32);
5372 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5374 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5375 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5381 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5383 unsigned long nr, a0, a1, a2, a3, ret;
5386 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5387 return kvm_hv_hypercall(vcpu);
5389 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5390 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5391 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5392 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5393 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5395 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5397 if (!is_long_mode(vcpu)) {
5405 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5411 case KVM_HC_VAPIC_POLL_IRQ:
5415 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
5422 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5423 ++vcpu->stat.hypercalls;
5426 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5428 int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5430 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5431 char instruction[3];
5432 unsigned long rip = kvm_rip_read(vcpu);
5435 * Blow out the MMU to ensure that no other VCPU has an active mapping
5436 * to ensure that the updated hypercall appears atomically across all
5439 kvm_mmu_zap_all(vcpu->kvm);
5441 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5443 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5446 static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
5448 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
5449 int j, nent = vcpu->arch.cpuid_nent;
5451 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
5452 /* when no next entry is found, the current entry[i] is reselected */
5453 for (j = i + 1; ; j = (j + 1) % nent) {
5454 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
5455 if (ej->function == e->function) {
5456 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
5460 return 0; /* silence gcc, even though control never reaches here */
5463 /* find an entry with matching function, matching index (if needed), and that
5464 * should be read next (if it's stateful) */
5465 static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
5466 u32 function, u32 index)
5468 if (e->function != function)
5470 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
5472 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
5473 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
5478 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
5479 u32 function, u32 index)
5482 struct kvm_cpuid_entry2 *best = NULL;
5484 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
5485 struct kvm_cpuid_entry2 *e;
5487 e = &vcpu->arch.cpuid_entries[i];
5488 if (is_matching_cpuid_entry(e, function, index)) {
5489 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
5490 move_to_next_stateful_cpuid_entry(vcpu, i);
5497 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
5499 int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
5501 struct kvm_cpuid_entry2 *best;
5503 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
5504 if (!best || best->eax < 0x80000008)
5506 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
5508 return best->eax & 0xff;
5514 * If no match is found, check whether we exceed the vCPU's limit
5515 * and return the content of the highest valid _standard_ leaf instead.
5516 * This is to satisfy the CPUID specification.
5518 static struct kvm_cpuid_entry2* check_cpuid_limit(struct kvm_vcpu *vcpu,
5519 u32 function, u32 index)
5521 struct kvm_cpuid_entry2 *maxlevel;
5523 maxlevel = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0);
5524 if (!maxlevel || maxlevel->eax >= function)
5526 if (function & 0x80000000) {
5527 maxlevel = kvm_find_cpuid_entry(vcpu, 0, 0);
5531 return kvm_find_cpuid_entry(vcpu, maxlevel->eax, index);
5534 void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
5536 u32 function, index;
5537 struct kvm_cpuid_entry2 *best;
5539 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
5540 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5541 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
5542 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
5543 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
5544 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
5545 best = kvm_find_cpuid_entry(vcpu, function, index);
5548 best = check_cpuid_limit(vcpu, function, index);
5551 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
5552 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
5553 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
5554 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
5556 kvm_x86_ops->skip_emulated_instruction(vcpu);
5557 trace_kvm_cpuid(function,
5558 kvm_register_read(vcpu, VCPU_REGS_RAX),
5559 kvm_register_read(vcpu, VCPU_REGS_RBX),
5560 kvm_register_read(vcpu, VCPU_REGS_RCX),
5561 kvm_register_read(vcpu, VCPU_REGS_RDX));
5563 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
5566 * Check if userspace requested an interrupt window, and that the
5567 * interrupt window is open.
5569 * No need to exit to userspace if we already have an interrupt queued.
5571 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5573 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5574 vcpu->run->request_interrupt_window &&
5575 kvm_arch_interrupt_allowed(vcpu));
5578 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5580 struct kvm_run *kvm_run = vcpu->run;
5582 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5583 kvm_run->cr8 = kvm_get_cr8(vcpu);
5584 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5585 if (irqchip_in_kernel(vcpu->kvm))
5586 kvm_run->ready_for_interrupt_injection = 1;
5588 kvm_run->ready_for_interrupt_injection =
5589 kvm_arch_interrupt_allowed(vcpu) &&
5590 !kvm_cpu_has_interrupt(vcpu) &&
5591 !kvm_event_needs_reinjection(vcpu);
5594 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5598 if (!kvm_x86_ops->update_cr8_intercept)
5601 if (!vcpu->arch.apic)
5604 if (!vcpu->arch.apic->vapic_addr)
5605 max_irr = kvm_lapic_find_highest_irr(vcpu);
5612 tpr = kvm_lapic_get_cr8(vcpu);
5614 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5617 static void inject_pending_event(struct kvm_vcpu *vcpu)
5619 /* try to reinject previous events if any */
5620 if (vcpu->arch.exception.pending) {
5621 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5622 vcpu->arch.exception.has_error_code,
5623 vcpu->arch.exception.error_code);
5624 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5625 vcpu->arch.exception.has_error_code,
5626 vcpu->arch.exception.error_code,
5627 vcpu->arch.exception.reinject);
5631 if (vcpu->arch.nmi_injected) {
5632 kvm_x86_ops->set_nmi(vcpu);
5636 if (vcpu->arch.interrupt.pending) {
5637 kvm_x86_ops->set_irq(vcpu);
5641 /* try to inject new event if pending */
5642 if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
5643 --vcpu->arch.nmi_pending;
5644 vcpu->arch.nmi_injected = true;
5645 kvm_x86_ops->set_nmi(vcpu);
5646 } else if (kvm_cpu_has_interrupt(vcpu)) {
5647 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5648 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5650 kvm_x86_ops->set_irq(vcpu);
5655 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5657 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5658 !vcpu->guest_xcr0_loaded) {
5659 /* kvm_set_xcr() also depends on this */
5660 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5661 vcpu->guest_xcr0_loaded = 1;
5665 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5667 if (vcpu->guest_xcr0_loaded) {
5668 if (vcpu->arch.xcr0 != host_xcr0)
5669 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5670 vcpu->guest_xcr0_loaded = 0;
5674 static void process_nmi(struct kvm_vcpu *vcpu)
5679 * x86 is limited to one NMI running, and one NMI pending after it.
5680 * If an NMI is already in progress, limit further NMIs to just one.
5681 * Otherwise, allow two (and we'll inject the first one immediately).
5683 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5686 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5687 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5688 kvm_make_request(KVM_REQ_EVENT, vcpu);
5691 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5694 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5695 vcpu->run->request_interrupt_window;
5697 if (vcpu->requests) {
5698 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5699 kvm_mmu_unload(vcpu);
5700 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5701 __kvm_migrate_timers(vcpu);
5702 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5703 r = kvm_guest_time_update(vcpu);
5707 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5708 kvm_mmu_sync_roots(vcpu);
5709 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5710 kvm_x86_ops->tlb_flush(vcpu);
5711 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5712 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5716 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5717 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5721 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5722 vcpu->fpu_active = 0;
5723 kvm_x86_ops->fpu_deactivate(vcpu);
5725 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5726 /* Page is swapped out. Do synthetic halt */
5727 vcpu->arch.apf.halted = true;
5731 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5732 record_steal_time(vcpu);
5733 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5738 r = kvm_mmu_reload(vcpu);
5742 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5743 inject_pending_event(vcpu);
5745 /* enable NMI/IRQ window open exits if needed */
5746 if (vcpu->arch.nmi_pending)
5747 kvm_x86_ops->enable_nmi_window(vcpu);
5748 if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5749 kvm_x86_ops->enable_irq_window(vcpu);
5751 if (kvm_lapic_enabled(vcpu)) {
5752 update_cr8_intercept(vcpu);
5753 kvm_lapic_sync_to_vapic(vcpu);
5759 kvm_x86_ops->prepare_guest_switch(vcpu);
5760 if (vcpu->fpu_active)
5761 kvm_load_guest_fpu(vcpu);
5762 vcpu->mode = IN_GUEST_MODE;
5764 /* We should set ->mode before check ->requests,
5765 * see the comment in make_all_cpus_request.
5769 local_irq_disable();
5771 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5772 || need_resched() || signal_pending(current)) {
5773 vcpu->mode = OUTSIDE_GUEST_MODE;
5777 kvm_x86_ops->cancel_injection(vcpu);
5782 kvm_load_guest_xcr0(vcpu);
5784 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5788 if (unlikely(vcpu->arch.switch_db_regs)) {
5790 set_debugreg(vcpu->arch.eff_db[0], 0);
5791 set_debugreg(vcpu->arch.eff_db[1], 1);
5792 set_debugreg(vcpu->arch.eff_db[2], 2);
5793 set_debugreg(vcpu->arch.eff_db[3], 3);
5796 trace_kvm_entry(vcpu->vcpu_id);
5797 kvm_x86_ops->run(vcpu);
5800 * If the guest has used debug registers, at least dr7
5801 * will be disabled while returning to the host.
5802 * If we don't have active breakpoints in the host, we don't
5803 * care about the messed up debug address registers. But if
5804 * we have some of them active, restore the old state.
5806 if (hw_breakpoint_active())
5807 hw_breakpoint_restore();
5809 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
5811 vcpu->mode = OUTSIDE_GUEST_MODE;
5814 kvm_put_guest_xcr0(vcpu);
5821 * We must have an instruction between local_irq_enable() and
5822 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5823 * the interrupt shadow. The stat.exits increment will do nicely.
5824 * But we need to prevent reordering, hence this barrier():
5832 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5835 * Profile KVM exit RIPs:
5837 if (unlikely(prof_on == KVM_PROFILING)) {
5838 unsigned long rip = kvm_rip_read(vcpu);
5839 profile_hit(KVM_PROFILING, (void *)rip);
5843 kvm_lapic_sync_from_vapic(vcpu);
5845 r = kvm_x86_ops->handle_exit(vcpu);
5851 static int __vcpu_run(struct kvm_vcpu *vcpu)
5854 struct kvm *kvm = vcpu->kvm;
5856 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
5857 pr_debug("vcpu %d received sipi with vector # %x\n",
5858 vcpu->vcpu_id, vcpu->arch.sipi_vector);
5859 kvm_lapic_reset(vcpu);
5860 r = kvm_arch_vcpu_reset(vcpu);
5863 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5866 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5870 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5871 !vcpu->arch.apf.halted)
5872 r = vcpu_enter_guest(vcpu);
5874 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5875 kvm_vcpu_block(vcpu);
5876 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5877 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
5879 switch(vcpu->arch.mp_state) {
5880 case KVM_MP_STATE_HALTED:
5881 vcpu->arch.mp_state =
5882 KVM_MP_STATE_RUNNABLE;
5883 case KVM_MP_STATE_RUNNABLE:
5884 vcpu->arch.apf.halted = false;
5886 case KVM_MP_STATE_SIPI_RECEIVED:
5897 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5898 if (kvm_cpu_has_pending_timer(vcpu))
5899 kvm_inject_pending_timer_irqs(vcpu);
5901 if (dm_request_for_irq_injection(vcpu)) {
5903 vcpu->run->exit_reason = KVM_EXIT_INTR;
5904 ++vcpu->stat.request_irq_exits;
5907 kvm_check_async_pf_completion(vcpu);
5909 if (signal_pending(current)) {
5911 vcpu->run->exit_reason = KVM_EXIT_INTR;
5912 ++vcpu->stat.signal_exits;
5914 if (need_resched()) {
5915 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5917 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5921 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5926 static int complete_mmio(struct kvm_vcpu *vcpu)
5928 struct kvm_run *run = vcpu->run;
5931 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5934 if (vcpu->mmio_needed) {
5935 vcpu->mmio_needed = 0;
5936 if (!vcpu->mmio_is_write)
5937 memcpy(vcpu->mmio_data + vcpu->mmio_index,
5939 vcpu->mmio_index += 8;
5940 if (vcpu->mmio_index < vcpu->mmio_size) {
5941 run->exit_reason = KVM_EXIT_MMIO;
5942 run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index;
5943 memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8);
5944 run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8);
5945 run->mmio.is_write = vcpu->mmio_is_write;
5946 vcpu->mmio_needed = 1;
5949 if (vcpu->mmio_is_write)
5951 vcpu->mmio_read_completed = 1;
5953 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5954 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5955 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5956 if (r != EMULATE_DONE)
5961 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5966 if (!tsk_used_math(current) && init_fpu(current))
5969 if (vcpu->sigset_active)
5970 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5972 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
5973 kvm_vcpu_block(vcpu);
5974 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
5979 /* re-sync apic's tpr */
5980 if (!irqchip_in_kernel(vcpu->kvm)) {
5981 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5987 r = complete_mmio(vcpu);
5991 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5992 kvm_register_write(vcpu, VCPU_REGS_RAX,
5993 kvm_run->hypercall.ret);
5995 r = __vcpu_run(vcpu);
5998 post_kvm_run_save(vcpu);
5999 if (vcpu->sigset_active)
6000 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6005 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6007 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6009 * We are here if userspace calls get_regs() in the middle of
6010 * instruction emulation. Registers state needs to be copied
6011 * back from emulation context to vcpu. Usrapace shouldn't do
6012 * that usually, but some bad designed PV devices (vmware
6013 * backdoor interface) need this to work
6015 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6016 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
6017 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6019 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6020 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6021 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6022 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6023 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6024 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6025 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6026 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6027 #ifdef CONFIG_X86_64
6028 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6029 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6030 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6031 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6032 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6033 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6034 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6035 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6038 regs->rip = kvm_rip_read(vcpu);
6039 regs->rflags = kvm_get_rflags(vcpu);
6044 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6046 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6047 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6049 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6050 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6051 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6052 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6053 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6054 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6055 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6056 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6057 #ifdef CONFIG_X86_64
6058 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6059 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6060 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6061 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6062 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6063 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6064 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6065 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6068 kvm_rip_write(vcpu, regs->rip);
6069 kvm_set_rflags(vcpu, regs->rflags);
6071 vcpu->arch.exception.pending = false;
6073 kvm_make_request(KVM_REQ_EVENT, vcpu);
6078 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6080 struct kvm_segment cs;
6082 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6086 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6088 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6089 struct kvm_sregs *sregs)
6093 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6094 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6095 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6096 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6097 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6098 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6100 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6101 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6103 kvm_x86_ops->get_idt(vcpu, &dt);
6104 sregs->idt.limit = dt.size;
6105 sregs->idt.base = dt.address;
6106 kvm_x86_ops->get_gdt(vcpu, &dt);
6107 sregs->gdt.limit = dt.size;
6108 sregs->gdt.base = dt.address;
6110 sregs->cr0 = kvm_read_cr0(vcpu);
6111 sregs->cr2 = vcpu->arch.cr2;
6112 sregs->cr3 = kvm_read_cr3(vcpu);
6113 sregs->cr4 = kvm_read_cr4(vcpu);
6114 sregs->cr8 = kvm_get_cr8(vcpu);
6115 sregs->efer = vcpu->arch.efer;
6116 sregs->apic_base = kvm_get_apic_base(vcpu);
6118 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6120 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6121 set_bit(vcpu->arch.interrupt.nr,
6122 (unsigned long *)sregs->interrupt_bitmap);
6127 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6128 struct kvm_mp_state *mp_state)
6130 mp_state->mp_state = vcpu->arch.mp_state;
6134 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6135 struct kvm_mp_state *mp_state)
6137 vcpu->arch.mp_state = mp_state->mp_state;
6138 kvm_make_request(KVM_REQ_EVENT, vcpu);
6142 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
6143 bool has_error_code, u32 error_code)
6145 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6148 init_emulate_ctxt(vcpu);
6150 ret = emulator_task_switch(ctxt, tss_selector, reason,
6151 has_error_code, error_code);
6154 return EMULATE_FAIL;
6156 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
6157 kvm_rip_write(vcpu, ctxt->eip);
6158 kvm_set_rflags(vcpu, ctxt->eflags);
6159 kvm_make_request(KVM_REQ_EVENT, vcpu);
6160 return EMULATE_DONE;
6162 EXPORT_SYMBOL_GPL(kvm_task_switch);
6164 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6165 struct kvm_sregs *sregs)
6167 int mmu_reset_needed = 0;
6168 int pending_vec, max_bits, idx;
6171 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6174 dt.size = sregs->idt.limit;
6175 dt.address = sregs->idt.base;
6176 kvm_x86_ops->set_idt(vcpu, &dt);
6177 dt.size = sregs->gdt.limit;
6178 dt.address = sregs->gdt.base;
6179 kvm_x86_ops->set_gdt(vcpu, &dt);
6181 vcpu->arch.cr2 = sregs->cr2;
6182 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6183 vcpu->arch.cr3 = sregs->cr3;
6184 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6186 kvm_set_cr8(vcpu, sregs->cr8);
6188 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6189 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6190 kvm_set_apic_base(vcpu, sregs->apic_base);
6192 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6193 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6194 vcpu->arch.cr0 = sregs->cr0;
6196 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6197 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6198 if (sregs->cr4 & X86_CR4_OSXSAVE)
6201 idx = srcu_read_lock(&vcpu->kvm->srcu);
6202 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6203 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6204 mmu_reset_needed = 1;
6206 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6208 if (mmu_reset_needed)
6209 kvm_mmu_reset_context(vcpu);
6211 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
6212 pending_vec = find_first_bit(
6213 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6214 if (pending_vec < max_bits) {
6215 kvm_queue_interrupt(vcpu, pending_vec, false);
6216 pr_debug("Set back pending irq %d\n", pending_vec);
6219 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6220 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6221 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6222 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6223 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6224 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6226 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6227 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6229 update_cr8_intercept(vcpu);
6231 /* Older userspace won't unhalt the vcpu on reset. */
6232 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6233 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6235 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6237 kvm_make_request(KVM_REQ_EVENT, vcpu);
6242 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6243 struct kvm_guest_debug *dbg)
6245 unsigned long rflags;
6248 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6250 if (vcpu->arch.exception.pending)
6252 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6253 kvm_queue_exception(vcpu, DB_VECTOR);
6255 kvm_queue_exception(vcpu, BP_VECTOR);
6259 * Read rflags as long as potentially injected trace flags are still
6262 rflags = kvm_get_rflags(vcpu);
6264 vcpu->guest_debug = dbg->control;
6265 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6266 vcpu->guest_debug = 0;
6268 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6269 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6270 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6271 vcpu->arch.switch_db_regs =
6272 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
6274 for (i = 0; i < KVM_NR_DB_REGS; i++)
6275 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6276 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
6279 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6280 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6281 get_segment_base(vcpu, VCPU_SREG_CS);
6284 * Trigger an rflags update that will inject or remove the trace
6287 kvm_set_rflags(vcpu, rflags);
6289 kvm_x86_ops->set_guest_debug(vcpu, dbg);
6299 * Translate a guest virtual address to a guest physical address.
6301 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6302 struct kvm_translation *tr)
6304 unsigned long vaddr = tr->linear_address;
6308 idx = srcu_read_lock(&vcpu->kvm->srcu);
6309 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6310 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6311 tr->physical_address = gpa;
6312 tr->valid = gpa != UNMAPPED_GVA;
6319 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6321 struct i387_fxsave_struct *fxsave =
6322 &vcpu->arch.guest_fpu.state->fxsave;
6324 memcpy(fpu->fpr, fxsave->st_space, 128);
6325 fpu->fcw = fxsave->cwd;
6326 fpu->fsw = fxsave->swd;
6327 fpu->ftwx = fxsave->twd;
6328 fpu->last_opcode = fxsave->fop;
6329 fpu->last_ip = fxsave->rip;
6330 fpu->last_dp = fxsave->rdp;
6331 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6336 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6338 struct i387_fxsave_struct *fxsave =
6339 &vcpu->arch.guest_fpu.state->fxsave;
6341 memcpy(fxsave->st_space, fpu->fpr, 128);
6342 fxsave->cwd = fpu->fcw;
6343 fxsave->swd = fpu->fsw;
6344 fxsave->twd = fpu->ftwx;
6345 fxsave->fop = fpu->last_opcode;
6346 fxsave->rip = fpu->last_ip;
6347 fxsave->rdp = fpu->last_dp;
6348 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6353 int fx_init(struct kvm_vcpu *vcpu)
6357 err = fpu_alloc(&vcpu->arch.guest_fpu);
6361 fpu_finit(&vcpu->arch.guest_fpu);
6364 * Ensure guest xcr0 is valid for loading
6366 vcpu->arch.xcr0 = XSTATE_FP;
6368 vcpu->arch.cr0 |= X86_CR0_ET;
6372 EXPORT_SYMBOL_GPL(fx_init);
6374 static void fx_free(struct kvm_vcpu *vcpu)
6376 fpu_free(&vcpu->arch.guest_fpu);
6379 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6381 if (vcpu->guest_fpu_loaded)
6385 * Restore all possible states in the guest,
6386 * and assume host would use all available bits.
6387 * Guest xcr0 would be loaded later.
6389 vcpu->guest_fpu_loaded = 1;
6390 unlazy_fpu(current);
6391 fpu_restore_checking(&vcpu->arch.guest_fpu);
6395 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6397 if (!vcpu->guest_fpu_loaded)
6400 vcpu->guest_fpu_loaded = 0;
6401 fpu_save_init(&vcpu->arch.guest_fpu);
6402 ++vcpu->stat.fpu_reload;
6403 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
6407 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6409 kvmclock_reset(vcpu);
6411 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6413 kvm_x86_ops->vcpu_free(vcpu);
6416 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6419 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6420 printk_once(KERN_WARNING
6421 "kvm: SMP vm created on host with unstable TSC; "
6422 "guest TSC will not be reliable\n");
6423 return kvm_x86_ops->vcpu_create(kvm, id);
6426 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6430 vcpu->arch.mtrr_state.have_fixed = 1;
6432 r = kvm_arch_vcpu_reset(vcpu);
6434 r = kvm_mmu_setup(vcpu);
6440 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6442 vcpu->arch.apf.msr_val = 0;
6445 kvm_mmu_unload(vcpu);
6449 kvm_x86_ops->vcpu_free(vcpu);
6452 int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6454 atomic_set(&vcpu->arch.nmi_queued, 0);
6455 vcpu->arch.nmi_pending = 0;
6456 vcpu->arch.nmi_injected = false;
6458 vcpu->arch.switch_db_regs = 0;
6459 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6460 vcpu->arch.dr6 = DR6_FIXED_1;
6461 vcpu->arch.dr7 = DR7_FIXED_1;
6463 kvm_make_request(KVM_REQ_EVENT, vcpu);
6464 vcpu->arch.apf.msr_val = 0;
6465 vcpu->arch.st.msr_val = 0;
6467 kvmclock_reset(vcpu);
6469 kvm_clear_async_pf_completion_queue(vcpu);
6470 kvm_async_pf_hash_reset(vcpu);
6471 vcpu->arch.apf.halted = false;
6473 return kvm_x86_ops->vcpu_reset(vcpu);
6476 int kvm_arch_hardware_enable(void *garbage)
6479 struct kvm_vcpu *vcpu;
6482 kvm_shared_msr_cpu_online();
6483 list_for_each_entry(kvm, &vm_list, vm_list)
6484 kvm_for_each_vcpu(i, vcpu, kvm)
6485 if (vcpu->cpu == smp_processor_id())
6486 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6487 return kvm_x86_ops->hardware_enable(garbage);
6490 void kvm_arch_hardware_disable(void *garbage)
6492 kvm_x86_ops->hardware_disable(garbage);
6493 drop_user_return_notifiers(garbage);
6496 int kvm_arch_hardware_setup(void)
6498 return kvm_x86_ops->hardware_setup();
6501 void kvm_arch_hardware_unsetup(void)
6503 kvm_x86_ops->hardware_unsetup();
6506 void kvm_arch_check_processor_compat(void *rtn)
6508 kvm_x86_ops->check_processor_compatibility(rtn);
6511 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6513 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6516 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6522 BUG_ON(vcpu->kvm == NULL);
6525 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6526 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
6527 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
6528 vcpu->arch.mmu.translate_gpa = translate_gpa;
6529 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
6530 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6531 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6533 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6535 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6540 vcpu->arch.pio_data = page_address(page);
6542 kvm_init_tsc_catchup(vcpu, max_tsc_khz);
6544 r = kvm_mmu_create(vcpu);
6546 goto fail_free_pio_data;
6548 if (irqchip_in_kernel(kvm)) {
6549 r = kvm_create_lapic(vcpu);
6551 goto fail_mmu_destroy;
6554 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6556 if (!vcpu->arch.mce_banks) {
6558 goto fail_free_lapic;
6560 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6562 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6563 goto fail_free_mce_banks;
6565 vcpu->arch.pv_time_enabled = false;
6566 kvm_async_pf_hash_reset(vcpu);
6569 fail_free_mce_banks:
6570 kfree(vcpu->arch.mce_banks);
6572 kvm_free_lapic(vcpu);
6574 kvm_mmu_destroy(vcpu);
6576 free_page((unsigned long)vcpu->arch.pio_data);
6581 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6585 kfree(vcpu->arch.mce_banks);
6586 kvm_free_lapic(vcpu);
6587 idx = srcu_read_lock(&vcpu->kvm->srcu);
6588 kvm_mmu_destroy(vcpu);
6589 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6590 free_page((unsigned long)vcpu->arch.pio_data);
6593 int kvm_arch_init_vm(struct kvm *kvm)
6595 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6596 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
6598 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6599 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6601 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
6606 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6609 kvm_mmu_unload(vcpu);
6613 static void kvm_free_vcpus(struct kvm *kvm)
6616 struct kvm_vcpu *vcpu;
6619 * Unpin any mmu pages first.
6621 kvm_for_each_vcpu(i, vcpu, kvm) {
6622 kvm_clear_async_pf_completion_queue(vcpu);
6623 kvm_unload_vcpu_mmu(vcpu);
6625 kvm_for_each_vcpu(i, vcpu, kvm)
6626 kvm_arch_vcpu_free(vcpu);
6628 mutex_lock(&kvm->lock);
6629 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6630 kvm->vcpus[i] = NULL;
6632 atomic_set(&kvm->online_vcpus, 0);
6633 mutex_unlock(&kvm->lock);
6636 void kvm_arch_sync_events(struct kvm *kvm)
6638 kvm_free_all_assigned_devices(kvm);
6642 void kvm_arch_destroy_vm(struct kvm *kvm)
6644 kvm_iommu_unmap_guest(kvm);
6645 kfree(kvm->arch.vpic);
6646 kfree(kvm->arch.vioapic);
6647 kvm_free_vcpus(kvm);
6648 if (kvm->arch.apic_access_page)
6649 put_page(kvm->arch.apic_access_page);
6650 if (kvm->arch.ept_identity_pagetable)
6651 put_page(kvm->arch.ept_identity_pagetable);
6654 int kvm_arch_prepare_memory_region(struct kvm *kvm,
6655 struct kvm_memory_slot *memslot,
6656 struct kvm_memory_slot old,
6657 struct kvm_userspace_memory_region *mem,
6660 int npages = memslot->npages;
6661 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6663 /* Prevent internal slot pages from being moved by fork()/COW. */
6664 if (memslot->id >= KVM_MEMORY_SLOTS)
6665 map_flags = MAP_SHARED | MAP_ANONYMOUS;
6667 /*To keep backward compatibility with older userspace,
6668 *x86 needs to hanlde !user_alloc case.
6671 if (npages && !old.rmap) {
6672 unsigned long userspace_addr;
6674 down_write(¤t->mm->mmap_sem);
6675 userspace_addr = do_mmap(NULL, 0,
6677 PROT_READ | PROT_WRITE,
6680 up_write(¤t->mm->mmap_sem);
6682 if (IS_ERR((void *)userspace_addr))
6683 return PTR_ERR((void *)userspace_addr);
6685 memslot->userspace_addr = userspace_addr;
6693 void kvm_arch_commit_memory_region(struct kvm *kvm,
6694 struct kvm_userspace_memory_region *mem,
6695 struct kvm_memory_slot old,
6699 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
6701 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6704 down_write(¤t->mm->mmap_sem);
6705 ret = do_munmap(current->mm, old.userspace_addr,
6706 old.npages * PAGE_SIZE);
6707 up_write(¤t->mm->mmap_sem);
6710 "kvm_vm_ioctl_set_memory_region: "
6711 "failed to munmap memory\n");
6714 if (!kvm->arch.n_requested_mmu_pages)
6715 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6717 spin_lock(&kvm->mmu_lock);
6719 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
6720 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
6721 spin_unlock(&kvm->mmu_lock);
6724 void kvm_arch_flush_shadow(struct kvm *kvm)
6726 kvm_mmu_zap_all(kvm);
6727 kvm_reload_remote_mmus(kvm);
6730 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6732 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6733 !vcpu->arch.apf.halted)
6734 || !list_empty_careful(&vcpu->async_pf.done)
6735 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6736 || atomic_read(&vcpu->arch.nmi_queued) ||
6737 (kvm_arch_interrupt_allowed(vcpu) &&
6738 kvm_cpu_has_interrupt(vcpu));
6741 void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6744 int cpu = vcpu->cpu;
6746 if (waitqueue_active(&vcpu->wq)) {
6747 wake_up_interruptible(&vcpu->wq);
6748 ++vcpu->stat.halt_wakeup;
6752 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6753 if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE)
6754 smp_send_reschedule(cpu);
6758 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6760 return kvm_x86_ops->interrupt_allowed(vcpu);
6763 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6765 unsigned long current_rip = kvm_rip_read(vcpu) +
6766 get_segment_base(vcpu, VCPU_SREG_CS);
6768 return current_rip == linear_rip;
6770 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6772 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6774 unsigned long rflags;
6776 rflags = kvm_x86_ops->get_rflags(vcpu);
6777 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6778 rflags &= ~X86_EFLAGS_TF;
6781 EXPORT_SYMBOL_GPL(kvm_get_rflags);
6783 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6785 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
6786 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
6787 rflags |= X86_EFLAGS_TF;
6788 kvm_x86_ops->set_rflags(vcpu, rflags);
6789 kvm_make_request(KVM_REQ_EVENT, vcpu);
6791 EXPORT_SYMBOL_GPL(kvm_set_rflags);
6793 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6797 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
6798 is_error_page(work->page))
6801 r = kvm_mmu_reload(vcpu);
6805 if (!vcpu->arch.mmu.direct_map &&
6806 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6809 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6812 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6814 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6817 static inline u32 kvm_async_pf_next_probe(u32 key)
6819 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6822 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6824 u32 key = kvm_async_pf_hash_fn(gfn);
6826 while (vcpu->arch.apf.gfns[key] != ~0)
6827 key = kvm_async_pf_next_probe(key);
6829 vcpu->arch.apf.gfns[key] = gfn;
6832 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6835 u32 key = kvm_async_pf_hash_fn(gfn);
6837 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
6838 (vcpu->arch.apf.gfns[key] != gfn &&
6839 vcpu->arch.apf.gfns[key] != ~0); i++)
6840 key = kvm_async_pf_next_probe(key);
6845 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6847 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6850 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6854 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6856 vcpu->arch.apf.gfns[i] = ~0;
6858 j = kvm_async_pf_next_probe(j);
6859 if (vcpu->arch.apf.gfns[j] == ~0)
6861 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6863 * k lies cyclically in ]i,j]
6865 * |....j i.k.| or |.k..j i...|
6867 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6868 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6873 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6876 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6880 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6881 struct kvm_async_pf *work)
6883 struct x86_exception fault;
6885 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
6886 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
6888 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
6889 (vcpu->arch.apf.send_user_only &&
6890 kvm_x86_ops->get_cpl(vcpu) == 0))
6891 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6892 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6893 fault.vector = PF_VECTOR;
6894 fault.error_code_valid = true;
6895 fault.error_code = 0;
6896 fault.nested_page_fault = false;
6897 fault.address = work->arch.token;
6898 kvm_inject_page_fault(vcpu, &fault);
6902 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6903 struct kvm_async_pf *work)
6905 struct x86_exception fault;
6907 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6908 if (is_error_page(work->page))
6909 work->arch.token = ~0; /* broadcast wakeup */
6911 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6913 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6914 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6915 fault.vector = PF_VECTOR;
6916 fault.error_code_valid = true;
6917 fault.error_code = 0;
6918 fault.nested_page_fault = false;
6919 fault.address = work->arch.token;
6920 kvm_inject_page_fault(vcpu, &fault);
6922 vcpu->arch.apf.halted = false;
6925 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6927 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6930 return !kvm_event_needs_reinjection(vcpu) &&
6931 kvm_x86_ops->interrupt_allowed(vcpu);
6934 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6935 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6936 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6937 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6938 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
6939 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
6940 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
6941 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
6942 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
6943 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
6944 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
6945 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);