arch/x86/kvm/x86.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * derived from drivers/kvm/kvm_main.c
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright (C) 2008 Qumranet, Inc.
   8  * Copyright IBM Corporation, 2008
   9  * Copyright 2010 Red Hat, Inc. and/or its affilates.
  10  *
  11  * Authors:
  12  *   Avi Kivity   <avi@qumranet.com>
  13  *   Yaniv Kamay  <yaniv@qumranet.com>
  14  *   Amit Shah    <amit.shah@qumranet.com>
  15  *   Ben-Ami Yassour <benami@il.ibm.com>
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  *
  20  */
  21
  22 #include <linux/kvm_host.h>
  23 #include "irq.h"
  24 #include "mmu.h"
  25 #include "i8254.h"
  26 #include "tss.h"
  27 #include "kvm_cache_regs.h"
  28 #include "x86.h"
  29
  30 #include <linux/clocksource.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/kvm.h>
  33 #include <linux/fs.h>
  34 #include <linux/vmalloc.h>
  35 #include <linux/module.h>
  36 #include <linux/mman.h>
  37 #include <linux/highmem.h>
  38 #include <linux/iommu.h>
  39 #include <linux/intel-iommu.h>
  40 #include <linux/cpufreq.h>
  41 #include <linux/user-return-notifier.h>
  42 #include <linux/srcu.h>
  43 #include <linux/slab.h>
  44 #include <linux/perf_event.h>
  45 #include <linux/uaccess.h>
  46 #include <trace/events/kvm.h>
  47
  48 #define CREATE_TRACE_POINTS
  49 #include "trace.h"
  50
  51 #include <asm/debugreg.h>
  52 #include <asm/msr.h>
  53 #include <asm/desc.h>
  54 #include <asm/mtrr.h>
  55 #include <asm/mce.h>
  56 #include <asm/i387.h>
  57 #include <asm/xcr.h>
  58 #include <asm/pvclock.h>
  59 #include <asm/div64.h>
  60
  61 #define MAX_IO_MSRS 256
  62 #define CR0_RESERVED_BITS                                               \
  63         (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
  64                           | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
  65                           | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
  66 #define CR4_RESERVED_BITS                                               \
  67         (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
  68                           | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE     \
  69                           | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR  \
  70                           | X86_CR4_OSXSAVE \
  71                           | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
  72
  73 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
  74
  75 #define KVM_MAX_MCE_BANKS 32
  76 #define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
  77
  78 /* EFER defaults:
  79  * - enable syscall per default because its emulated by KVM
  80  * - enable LME and LMA per default on 64 bit KVM
  81  */
  82 #ifdef CONFIG_X86_64
  83 static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
  84 #else
  85 static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
  86 #endif
  87
  88 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
  89 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
  90
  91 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
  92 static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
  93                                     struct kvm_cpuid_entry2 __user *entries);
  94
  95 struct kvm_x86_ops *kvm_x86_ops;
  96 EXPORT_SYMBOL_GPL(kvm_x86_ops);
  97
  98 int ignore_msrs = 0;
  99 module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
 100
 101 #define KVM_NR_SHARED_MSRS 16
 102
 103 struct kvm_shared_msrs_global {
 104         int nr;
 105         u32 msrs[KVM_NR_SHARED_MSRS];
 106 };
 107
 108 struct kvm_shared_msrs {
 109         struct user_return_notifier urn;
 110         bool registered;
 111         struct kvm_shared_msr_values {
 112                 u64 host;
 113                 u64 curr;
 114         } values[KVM_NR_SHARED_MSRS];
 115 };
 116
 117 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
 118 static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
 119
 120 struct kvm_stats_debugfs_item debugfs_entries[] = {
 121         { "pf_fixed", VCPU_STAT(pf_fixed) },
 122         { "pf_guest", VCPU_STAT(pf_guest) },
 123         { "tlb_flush", VCPU_STAT(tlb_flush) },
 124         { "invlpg", VCPU_STAT(invlpg) },
 125         { "exits", VCPU_STAT(exits) },
 126         { "io_exits", VCPU_STAT(io_exits) },
 127         { "mmio_exits", VCPU_STAT(mmio_exits) },
 128         { "signal_exits", VCPU_STAT(signal_exits) },
 129         { "irq_window", VCPU_STAT(irq_window_exits) },
 130         { "nmi_window", VCPU_STAT(nmi_window_exits) },
 131         { "halt_exits", VCPU_STAT(halt_exits) },
 132         { "halt_wakeup", VCPU_STAT(halt_wakeup) },
 133         { "hypercalls", VCPU_STAT(hypercalls) },
 134         { "request_irq", VCPU_STAT(request_irq_exits) },
 135         { "irq_exits", VCPU_STAT(irq_exits) },
 136         { "host_state_reload", VCPU_STAT(host_state_reload) },
 137         { "efer_reload", VCPU_STAT(efer_reload) },
 138         { "fpu_reload", VCPU_STAT(fpu_reload) },
 139         { "insn_emulation", VCPU_STAT(insn_emulation) },
 140         { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
 141         { "irq_injections", VCPU_STAT(irq_injections) },
 142         { "nmi_injections", VCPU_STAT(nmi_injections) },
 143         { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
 144         { "mmu_pte_write", VM_STAT(mmu_pte_write) },
 145         { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
 146         { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
 147         { "mmu_flooded", VM_STAT(mmu_flooded) },
 148         { "mmu_recycled", VM_STAT(mmu_recycled) },
 149         { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
 150         { "mmu_unsync", VM_STAT(mmu_unsync) },
 151         { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
 152         { "largepages", VM_STAT(lpages) },
 153         { NULL }
 154 };
 155
 156 u64 __read_mostly host_xcr0;
 157
 158 static inline u32 bit(int bitno)
 159 {
 160         return 1 << (bitno & 31);
 161 }
 162
 163 static void kvm_on_user_return(struct user_return_notifier *urn)
 164 {
 165         unsigned slot;
 166         struct kvm_shared_msrs *locals
 167                 = container_of(urn, struct kvm_shared_msrs, urn);
 168         struct kvm_shared_msr_values *values;
 169
 170         for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
 171                 values = &locals->values[slot];
 172                 if (values->host != values->curr) {
 173                         wrmsrl(shared_msrs_global.msrs[slot], values->host);
 174                         values->curr = values->host;
 175                 }
 176         }
 177         locals->registered = false;
 178         user_return_notifier_unregister(urn);
 179 }
 180
 181 static void shared_msr_update(unsigned slot, u32 msr)
 182 {
 183         struct kvm_shared_msrs *smsr;
 184         u64 value;
 185
 186         smsr = &__get_cpu_var(shared_msrs);
 187         /* only read, and nobody should modify it at this time,
 188          * so don't need lock */
 189         if (slot >= shared_msrs_global.nr) {
 190                 printk(KERN_ERR "kvm: invalid MSR slot!");
 191                 return;
 192         }
 193         rdmsrl_safe(msr, &value);
 194         smsr->values[slot].host = value;
 195         smsr->values[slot].curr = value;
 196 }
 197
 198 void kvm_define_shared_msr(unsigned slot, u32 msr)
 199 {
 200         if (slot >= shared_msrs_global.nr)
 201                 shared_msrs_global.nr = slot + 1;
 202         shared_msrs_global.msrs[slot] = msr;
 203         /* we need ensured the shared_msr_global have been updated */
 204         smp_wmb();
 205 }
 206 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
 207
 208 static void kvm_shared_msr_cpu_online(void)
 209 {
 210         unsigned i;
 211
 212         for (i = 0; i < shared_msrs_global.nr; ++i)
 213                 shared_msr_update(i, shared_msrs_global.msrs[i]);
 214 }
 215
 216 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
 217 {
 218         struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
 219
 220         if (((value ^ smsr->values[slot].curr) & mask) == 0)
 221                 return;
 222         smsr->values[slot].curr = value;
 223         wrmsrl(shared_msrs_global.msrs[slot], value);
 224         if (!smsr->registered) {
 225                 smsr->urn.on_user_return = kvm_on_user_return;
 226                 user_return_notifier_register(&smsr->urn);
 227                 smsr->registered = true;
 228         }
 229 }
 230 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
 231
 232 static void drop_user_return_notifiers(void *ignore)
 233 {
 234         struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
 235
 236         if (smsr->registered)
 237                 kvm_on_user_return(&smsr->urn);
 238 }
 239
 240 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
 241 {
 242         if (irqchip_in_kernel(vcpu->kvm))
 243                 return vcpu->arch.apic_base;
 244         else
 245                 return vcpu->arch.apic_base;
 246 }
 247 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
 248
 249 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
 250 {
 251         /* TODO: reserve bits check */
 252         if (irqchip_in_kernel(vcpu->kvm))
 253                 kvm_lapic_set_base(vcpu, data);
 254         else
 255                 vcpu->arch.apic_base = data;
 256 }
 257 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
 258
 259 #define EXCPT_BENIGN            0
 260 #define EXCPT_CONTRIBUTORY      1
 261 #define EXCPT_PF                2
 262
 263 static int exception_class(int vector)
 264 {
 265         switch (vector) {
 266         case PF_VECTOR:
 267                 return EXCPT_PF;
 268         case DE_VECTOR:
 269         case TS_VECTOR:
 270         case NP_VECTOR:
 271         case SS_VECTOR:
 272         case GP_VECTOR:
 273                 return EXCPT_CONTRIBUTORY;
 274         default:
 275                 break;
 276         }
 277         return EXCPT_BENIGN;
 278 }
 279
 280 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
 281                 unsigned nr, bool has_error, u32 error_code,
 282                 bool reinject)
 283 {
 284         u32 prev_nr;
 285         int class1, class2;
 286
 287         kvm_make_request(KVM_REQ_EVENT, vcpu);
 288
 289         if (!vcpu->arch.exception.pending) {
 290         queue:
 291                 vcpu->arch.exception.pending = true;
 292                 vcpu->arch.exception.has_error_code = has_error;
 293                 vcpu->arch.exception.nr = nr;
 294                 vcpu->arch.exception.error_code = error_code;
 295                 vcpu->arch.exception.reinject = reinject;
 296                 return;
 297         }
 298
 299         /* to check exception */
 300         prev_nr = vcpu->arch.exception.nr;
 301         if (prev_nr == DF_VECTOR) {
 302                 /* triple fault -> shutdown */
 303                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
 304                 return;
 305         }
 306         class1 = exception_class(prev_nr);
 307         class2 = exception_class(nr);
 308         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
 309                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
 310                 /* generate double fault per SDM Table 5-5 */
 311                 vcpu->arch.exception.pending = true;
 312                 vcpu->arch.exception.has_error_code = true;
 313                 vcpu->arch.exception.nr = DF_VECTOR;
 314                 vcpu->arch.exception.error_code = 0;
 315         } else
 316                 /* replace previous exception with a new one in a hope
 317                    that instruction re-execution will regenerate lost
 318                    exception */
 319                 goto queue;
 320 }
 321
 322 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 323 {
 324         kvm_multiple_exception(vcpu, nr, false, 0, false);
 325 }
 326 EXPORT_SYMBOL_GPL(kvm_queue_exception);
 327
 328 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 329 {
 330         kvm_multiple_exception(vcpu, nr, false, 0, true);
 331 }
 332 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
 333
 334 void kvm_inject_page_fault(struct kvm_vcpu *vcpu)
 335 {
 336         unsigned error_code = vcpu->arch.fault.error_code;
 337
 338         ++vcpu->stat.pf_guest;
 339         vcpu->arch.cr2 = vcpu->arch.fault.address;
 340         kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
 341 }
 342
 343 void kvm_propagate_fault(struct kvm_vcpu *vcpu)
 344 {
 345         if (mmu_is_nested(vcpu) && !vcpu->arch.fault.nested)
 346                 vcpu->arch.nested_mmu.inject_page_fault(vcpu);
 347         else
 348                 vcpu->arch.mmu.inject_page_fault(vcpu);
 349
 350         vcpu->arch.fault.nested = false;
 351 }
 352
 353 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
 354 {
 355         kvm_make_request(KVM_REQ_EVENT, vcpu);
 356         vcpu->arch.nmi_pending = 1;
 357 }
 358 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
 359
 360 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 361 {
 362         kvm_multiple_exception(vcpu, nr, true, error_code, false);
 363 }
 364 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
 365
 366 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 367 {
 368         kvm_multiple_exception(vcpu, nr, true, error_code, true);
 369 }
 370 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
 371
 372 /*
 373  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
 374  * a #GP and return false.
 375  */
 376 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
 377 {
 378         if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
 379                 return true;
 380         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
 381         return false;
 382 }
 383 EXPORT_SYMBOL_GPL(kvm_require_cpl);
 384
 385 /*
 386  * This function will be used to read from the physical memory of the currently
 387  * running guest. The difference to kvm_read_guest_page is that this function
 388  * can read from guest physical or from the guest's guest physical memory.
 389  */
 390 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
 391                             gfn_t ngfn, void *data, int offset, int len,
 392                             u32 access)
 393 {
 394         gfn_t real_gfn;
 395         gpa_t ngpa;
 396
 397         ngpa     = gfn_to_gpa(ngfn);
 398         real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
 399         if (real_gfn == UNMAPPED_GVA)
 400                 return -EFAULT;
 401
 402         real_gfn = gpa_to_gfn(real_gfn);
 403
 404         return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
 405 }
 406 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
 407
 408 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
 409                                void *data, int offset, int len, u32 access)
 410 {
 411         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
 412                                        data, offset, len, access);
 413 }
 414
 415 /*
 416  * Load the pae pdptrs.  Return true is they are all valid.
 417  */
 418 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
 419 {
 420         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
 421         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
 422         int i;
 423         int ret;
 424         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
 425
 426         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
 427                                       offset * sizeof(u64), sizeof(pdpte),
 428                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
 429         if (ret < 0) {
 430                 ret = 0;
 431                 goto out;
 432         }
 433         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
 434                 if (is_present_gpte(pdpte[i]) &&
 435                     (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
 436                         ret = 0;
 437                         goto out;
 438                 }
 439         }
 440         ret = 1;
 441
 442         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
 443         __set_bit(VCPU_EXREG_PDPTR,
 444                   (unsigned long *)&vcpu->arch.regs_avail);
 445         __set_bit(VCPU_EXREG_PDPTR,
 446                   (unsigned long *)&vcpu->arch.regs_dirty);
 447 out:
 448
 449         return ret;
 450 }
 451 EXPORT_SYMBOL_GPL(load_pdptrs);
 452
 453 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
 454 {
 455         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
 456         bool changed = true;
 457         int offset;
 458         gfn_t gfn;
 459         int r;
 460
 461         if (is_long_mode(vcpu) || !is_pae(vcpu))
 462                 return false;
 463
 464         if (!test_bit(VCPU_EXREG_PDPTR,
 465                       (unsigned long *)&vcpu->arch.regs_avail))
 466                 return true;
 467
 468         gfn = (vcpu->arch.cr3 & ~31u) >> PAGE_SHIFT;
 469         offset = (vcpu->arch.cr3 & ~31u) & (PAGE_SIZE - 1);
 470         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
 471                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
 472         if (r < 0)
 473                 goto out;
 474         changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
 475 out:
 476
 477         return changed;
 478 }
 479
 480 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 481 {
 482         unsigned long old_cr0 = kvm_read_cr0(vcpu);
 483         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
 484                                     X86_CR0_CD | X86_CR0_NW;
 485
 486         cr0 |= X86_CR0_ET;
 487
 488 #ifdef CONFIG_X86_64
 489         if (cr0 & 0xffffffff00000000UL)
 490                 return 1;
 491 #endif
 492
 493         cr0 &= ~CR0_RESERVED_BITS;
 494
 495         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
 496                 return 1;
 497
 498         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
 499                 return 1;
 500
 501         if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 502 #ifdef CONFIG_X86_64
 503                 if ((vcpu->arch.efer & EFER_LME)) {
 504                         int cs_db, cs_l;
 505
 506                         if (!is_pae(vcpu))
 507                                 return 1;
 508                         kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
 509                         if (cs_l)
 510                                 return 1;
 511                 } else
 512 #endif
 513                 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 514                                                  vcpu->arch.cr3))
 515                         return 1;
 516         }
 517
 518         kvm_x86_ops->set_cr0(vcpu, cr0);
 519
 520         if ((cr0 ^ old_cr0) & update_bits)
 521                 kvm_mmu_reset_context(vcpu);
 522         return 0;
 523 }
 524 EXPORT_SYMBOL_GPL(kvm_set_cr0);
 525
 526 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
 527 {
 528         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
 529 }
 530 EXPORT_SYMBOL_GPL(kvm_lmsw);
 531
 532 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 533 {
 534         u64 xcr0;
 535
 536         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
 537         if (index != XCR_XFEATURE_ENABLED_MASK)
 538                 return 1;
 539         xcr0 = xcr;
 540         if (kvm_x86_ops->get_cpl(vcpu) != 0)
 541                 return 1;
 542         if (!(xcr0 & XSTATE_FP))
 543                 return 1;
 544         if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
 545                 return 1;
 546         if (xcr0 & ~host_xcr0)
 547                 return 1;
 548         vcpu->arch.xcr0 = xcr0;
 549         vcpu->guest_xcr0_loaded = 0;
 550         return 0;
 551 }
 552
 553 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 554 {
 555         if (__kvm_set_xcr(vcpu, index, xcr)) {
 556                 kvm_inject_gp(vcpu, 0);
 557                 return 1;
 558         }
 559         return 0;
 560 }
 561 EXPORT_SYMBOL_GPL(kvm_set_xcr);
 562
 563 static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
 564 {
 565         struct kvm_cpuid_entry2 *best;
 566
 567         best = kvm_find_cpuid_entry(vcpu, 1, 0);
 568         return best && (best->ecx & bit(X86_FEATURE_XSAVE));
 569 }
 570
 571 static void update_cpuid(struct kvm_vcpu *vcpu)
 572 {
 573         struct kvm_cpuid_entry2 *best;
 574
 575         best = kvm_find_cpuid_entry(vcpu, 1, 0);
 576         if (!best)
 577                 return;
 578
 579         /* Update OSXSAVE bit */
 580         if (cpu_has_xsave && best->function == 0x1) {
 581                 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
 582                 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
 583                         best->ecx |= bit(X86_FEATURE_OSXSAVE);
 584         }
 585 }
 586
 587 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 588 {
 589         unsigned long old_cr4 = kvm_read_cr4(vcpu);
 590         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
 591
 592         if (cr4 & CR4_RESERVED_BITS)
 593                 return 1;
 594
 595         if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
 596                 return 1;
 597
 598         if (is_long_mode(vcpu)) {
 599                 if (!(cr4 & X86_CR4_PAE))
 600                         return 1;
 601         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
 602                    && ((cr4 ^ old_cr4) & pdptr_bits)
 603                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3))
 604                 return 1;
 605
 606         if (cr4 & X86_CR4_VMXE)
 607                 return 1;
 608
 609         kvm_x86_ops->set_cr4(vcpu, cr4);
 610
 611         if ((cr4 ^ old_cr4) & pdptr_bits)
 612                 kvm_mmu_reset_context(vcpu);
 613
 614         if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
 615                 update_cpuid(vcpu);
 616
 617         return 0;
 618 }
 619 EXPORT_SYMBOL_GPL(kvm_set_cr4);
 620
 621 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
 622 {
 623         if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
 624                 kvm_mmu_sync_roots(vcpu);
 625                 kvm_mmu_flush_tlb(vcpu);
 626                 return 0;
 627         }
 628
 629         if (is_long_mode(vcpu)) {
 630                 if (cr3 & CR3_L_MODE_RESERVED_BITS)
 631                         return 1;
 632         } else {
 633                 if (is_pae(vcpu)) {
 634                         if (cr3 & CR3_PAE_RESERVED_BITS)
 635                                 return 1;
 636                         if (is_paging(vcpu) &&
 637                             !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
 638                                 return 1;
 639                 }
 640                 /*
 641                  * We don't check reserved bits in nonpae mode, because
 642                  * this isn't enforced, and VMware depends on this.
 643                  */
 644         }
 645
 646         /*
 647          * Does the new cr3 value map to physical memory? (Note, we
 648          * catch an invalid cr3 even in real-mode, because it would
 649          * cause trouble later on when we turn on paging anyway.)
 650          *
 651          * A real CPU would silently accept an invalid cr3 and would
 652          * attempt to use it - with largely undefined (and often hard
 653          * to debug) behavior on the guest side.
 654          */
 655         if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
 656                 return 1;
 657         vcpu->arch.cr3 = cr3;
 658         vcpu->arch.mmu.new_cr3(vcpu);
 659         return 0;
 660 }
 661 EXPORT_SYMBOL_GPL(kvm_set_cr3);
 662
 663 int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
 664 {
 665         if (cr8 & CR8_RESERVED_BITS)
 666                 return 1;
 667         if (irqchip_in_kernel(vcpu->kvm))
 668                 kvm_lapic_set_tpr(vcpu, cr8);
 669         else
 670                 vcpu->arch.cr8 = cr8;
 671         return 0;
 672 }
 673
 674 void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
 675 {
 676         if (__kvm_set_cr8(vcpu, cr8))
 677                 kvm_inject_gp(vcpu, 0);
 678 }
 679 EXPORT_SYMBOL_GPL(kvm_set_cr8);
 680
 681 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
 682 {
 683         if (irqchip_in_kernel(vcpu->kvm))
 684                 return kvm_lapic_get_cr8(vcpu);
 685         else
 686                 return vcpu->arch.cr8;
 687 }
 688 EXPORT_SYMBOL_GPL(kvm_get_cr8);
 689
 690 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
 691 {
 692         switch (dr) {
 693         case 0 ... 3:
 694                 vcpu->arch.db[dr] = val;
 695                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
 696                         vcpu->arch.eff_db[dr] = val;
 697                 break;
 698         case 4:
 699                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 700                         return 1; /* #UD */
 701                 /* fall through */
 702         case 6:
 703                 if (val & 0xffffffff00000000ULL)
 704                         return -1; /* #GP */
 705                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
 706                 break;
 707         case 5:
 708                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 709                         return 1; /* #UD */
 710                 /* fall through */
 711         default: /* 7 */
 712                 if (val & 0xffffffff00000000ULL)
 713                         return -1; /* #GP */
 714                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
 715                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
 716                         kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
 717                         vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
 718                 }
 719                 break;
 720         }
 721
 722         return 0;
 723 }
 724
 725 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
 726 {
 727         int res;
 728
 729         res = __kvm_set_dr(vcpu, dr, val);
 730         if (res > 0)
 731                 kvm_queue_exception(vcpu, UD_VECTOR);
 732         else if (res < 0)
 733                 kvm_inject_gp(vcpu, 0);
 734
 735         return res;
 736 }
 737 EXPORT_SYMBOL_GPL(kvm_set_dr);
 738
 739 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
 740 {
 741         switch (dr) {
 742         case 0 ... 3:
 743                 *val = vcpu->arch.db[dr];
 744                 break;
 745         case 4:
 746                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 747                         return 1;
 748                 /* fall through */
 749         case 6:
 750                 *val = vcpu->arch.dr6;
 751                 break;
 752         case 5:
 753                 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 754                         return 1;
 755                 /* fall through */
 756         default: /* 7 */
 757                 *val = vcpu->arch.dr7;
 758                 break;
 759         }
 760
 761         return 0;
 762 }
 763
 764 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
 765 {
 766         if (_kvm_get_dr(vcpu, dr, val)) {
 767                 kvm_queue_exception(vcpu, UD_VECTOR);
 768                 return 1;
 769         }
 770         return 0;
 771 }
 772 EXPORT_SYMBOL_GPL(kvm_get_dr);
 773
 774 /*
 775  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
 776  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
 777  *
 778  * This list is modified at module load time to reflect the
 779  * capabilities of the host cpu. This capabilities test skips MSRs that are
 780  * kvm-specific. Those are put in the beginning of the list.
 781  */
 782
 783 #define KVM_SAVE_MSRS_BEGIN     7
 784 static u32 msrs_to_save[] = {
 785         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
 786         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
 787         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
 788         HV_X64_MSR_APIC_ASSIST_PAGE,
 789         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
 790         MSR_STAR,
 791 #ifdef CONFIG_X86_64
 792         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
 793 #endif
 794         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
 795 };
 796
 797 static unsigned num_msrs_to_save;
 798
 799 static u32 emulated_msrs[] = {
 800         MSR_IA32_MISC_ENABLE,
 801         MSR_IA32_MCG_STATUS,
 802         MSR_IA32_MCG_CTL,
 803 };
 804
 805 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
 806 {
 807         u64 old_efer = vcpu->arch.efer;
 808
 809         if (efer & efer_reserved_bits)
 810                 return 1;
 811
 812         if (is_paging(vcpu)
 813             && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
 814                 return 1;
 815
 816         if (efer & EFER_FFXSR) {
 817                 struct kvm_cpuid_entry2 *feat;
 818
 819                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
 820                 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
 821                         return 1;
 822         }
 823
 824         if (efer & EFER_SVME) {
 825                 struct kvm_cpuid_entry2 *feat;
 826
 827                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
 828                 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
 829                         return 1;
 830         }
 831
 832         efer &= ~EFER_LMA;
 833         efer |= vcpu->arch.efer & EFER_LMA;
 834
 835         kvm_x86_ops->set_efer(vcpu, efer);
 836
 837         vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
 838         kvm_mmu_reset_context(vcpu);
 839
 840         /* Update reserved bits */
 841         if ((efer ^ old_efer) & EFER_NX)
 842                 kvm_mmu_reset_context(vcpu);
 843
 844         return 0;
 845 }
 846
 847 void kvm_enable_efer_bits(u64 mask)
 848 {
 849        efer_reserved_bits &= ~mask;
 850 }
 851 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
 852
 853
 854 /*
 855  * Writes msr value into into the appropriate "register".
 856  * Returns 0 on success, non-0 otherwise.
 857  * Assumes vcpu_load() was already called.
 858  */
 859 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
 860 {
 861         return kvm_x86_ops->set_msr(vcpu, msr_index, data);
 862 }
 863
 864 /*
 865  * Adapt set_msr() to msr_io()'s calling convention
 866  */
 867 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
 868 {
 869         return kvm_set_msr(vcpu, index, *data);
 870 }
 871
 872 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
 873 {
 874         int version;
 875         int r;
 876         struct pvclock_wall_clock wc;
 877         struct timespec boot;
 878
 879         if (!wall_clock)
 880                 return;
 881
 882         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
 883         if (r)
 884                 return;
 885
 886         if (version & 1)
 887                 ++version;  /* first time write, random junk */
 888
 889         ++version;
 890
 891         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
 892
 893         /*
 894          * The guest calculates current wall clock time by adding
 895          * system time (updated by kvm_guest_time_update below) to the
 896          * wall clock specified here.  guest system time equals host
 897          * system time for us, thus we must fill in host boot time here.
 898          */
 899         getboottime(&boot);
 900
 901         wc.sec = boot.tv_sec;
 902         wc.nsec = boot.tv_nsec;
 903         wc.version = version;
 904
 905         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
 906
 907         version++;
 908         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
 909 }
 910
 911 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
 912 {
 913         uint32_t quotient, remainder;
 914
 915         /* Don't try to replace with do_div(), this one calculates
 916          * "(dividend << 32) / divisor" */
 917         __asm__ ( "divl %4"
 918                   : "=a" (quotient), "=d" (remainder)
 919                   : "0" (0), "1" (dividend), "r" (divisor) );
 920         return quotient;
 921 }
 922
 923 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
 924                                s8 *pshift, u32 *pmultiplier)
 925 {
 926         uint64_t scaled64;
 927         int32_t  shift = 0;
 928         uint64_t tps64;
 929         uint32_t tps32;
 930
 931         tps64 = base_khz * 1000LL;
 932         scaled64 = scaled_khz * 1000LL;
 933         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000UL) {
 934                 tps64 >>= 1;
 935                 shift--;
 936         }
 937
 938         tps32 = (uint32_t)tps64;
 939         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000UL) {
 940                 if (scaled64 & 0xffffffff00000000UL || tps32 & 0x80000000)
 941                         scaled64 >>= 1;
 942                 else
 943                         tps32 <<= 1;
 944                 shift++;
 945         }
 946
 947         *pshift = shift;
 948         *pmultiplier = div_frac(scaled64, tps32);
 949
 950         pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
 951                  __func__, base_khz, scaled_khz, shift, *pmultiplier);
 952 }
 953
 954 static inline u64 get_kernel_ns(void)
 955 {
 956         struct timespec ts;
 957
 958         WARN_ON(preemptible());
 959         ktime_get_ts(&ts);
 960         monotonic_to_bootbased(&ts);
 961         return timespec_to_ns(&ts);
 962 }
 963
 964 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
 965
 966 static inline int kvm_tsc_changes_freq(void)
 967 {
 968         int cpu = get_cpu();
 969         int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
 970                   cpufreq_quick_get(cpu) != 0;
 971         put_cpu();
 972         return ret;
 973 }
 974
 975 static inline u64 nsec_to_cycles(u64 nsec)
 976 {
 977         u64 ret;
 978
 979         WARN_ON(preemptible());
 980         if (kvm_tsc_changes_freq())
 981                 printk_once(KERN_WARNING
 982                  "kvm: unreliable cycle conversion on adjustable rate TSC\n");
 983         ret = nsec * __get_cpu_var(cpu_tsc_khz);
 984         do_div(ret, USEC_PER_SEC);
 985         return ret;
 986 }
 987
 988 void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
 989 {
 990         struct kvm *kvm = vcpu->kvm;
 991         u64 offset, ns, elapsed;
 992         unsigned long flags;
 993         s64 sdiff;
 994
 995         spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
 996         offset = data - native_read_tsc();
 997         ns = get_kernel_ns();
 998         elapsed = ns - kvm->arch.last_tsc_nsec;
 999         sdiff = data - kvm->arch.last_tsc_write;
1000         if (sdiff < 0)
1001                 sdiff = -sdiff;
1002
1003         /*
1004          * Special case: close write to TSC within 5 seconds of
1005          * another CPU is interpreted as an attempt to synchronize
1006          * The 5 seconds is to accomodate host load / swapping as
1007          * well as any reset of TSC during the boot process.
1008          *
1009          * In that case, for a reliable TSC, we can match TSC offsets,
1010          * or make a best guest using elapsed value.
1011          */
1012         if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
1013             elapsed < 5ULL * NSEC_PER_SEC) {
1014                 if (!check_tsc_unstable()) {
1015                         offset = kvm->arch.last_tsc_offset;
1016                         pr_debug("kvm: matched tsc offset for %llu\n", data);
1017                 } else {
1018                         u64 delta = nsec_to_cycles(elapsed);
1019                         offset += delta;
1020                         pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1021                 }
1022                 ns = kvm->arch.last_tsc_nsec;
1023         }
1024         kvm->arch.last_tsc_nsec = ns;
1025         kvm->arch.last_tsc_write = data;
1026         kvm->arch.last_tsc_offset = offset;
1027         kvm_x86_ops->write_tsc_offset(vcpu, offset);
1028         spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1029
1030         /* Reset of TSC must disable overshoot protection below */
1031         vcpu->arch.hv_clock.tsc_timestamp = 0;
1032 }
1033 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1034
1035 static int kvm_guest_time_update(struct kvm_vcpu *v)
1036 {
1037         unsigned long flags;
1038         struct kvm_vcpu_arch *vcpu = &v->arch;
1039         void *shared_kaddr;
1040         unsigned long this_tsc_khz;
1041         s64 kernel_ns, max_kernel_ns;
1042         u64 tsc_timestamp;
1043
1044         if ((!vcpu->time_page))
1045                 return 0;
1046
1047         /* Keep irq disabled to prevent changes to the clock */
1048         local_irq_save(flags);
1049         kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
1050         kernel_ns = get_kernel_ns();
1051         this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1052         local_irq_restore(flags);
1053
1054         if (unlikely(this_tsc_khz == 0)) {
1055                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1056                 return 1;
1057         }
1058
1059         /*
1060          * Time as measured by the TSC may go backwards when resetting the base
1061          * tsc_timestamp.  The reason for this is that the TSC resolution is
1062          * higher than the resolution of the other clock scales.  Thus, many
1063          * possible measurments of the TSC correspond to one measurement of any
1064          * other clock, and so a spread of values is possible.  This is not a
1065          * problem for the computation of the nanosecond clock; with TSC rates
1066          * around 1GHZ, there can only be a few cycles which correspond to one
1067          * nanosecond value, and any path through this code will inevitably
1068          * take longer than that.  However, with the kernel_ns value itself,
1069          * the precision may be much lower, down to HZ granularity.  If the
1070          * first sampling of TSC against kernel_ns ends in the low part of the
1071          * range, and the second in the high end of the range, we can get:
1072          *
1073          * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1074          *
1075          * As the sampling errors potentially range in the thousands of cycles,
1076          * it is possible such a time value has already been observed by the
1077          * guest.  To protect against this, we must compute the system time as
1078          * observed by the guest and ensure the new system time is greater.
1079          */
1080         max_kernel_ns = 0;
1081         if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1082                 max_kernel_ns = vcpu->last_guest_tsc -
1083                                 vcpu->hv_clock.tsc_timestamp;
1084                 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1085                                     vcpu->hv_clock.tsc_to_system_mul,
1086                                     vcpu->hv_clock.tsc_shift);
1087                 max_kernel_ns += vcpu->last_kernel_ns;
1088         }
1089
1090         if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1091                 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1092                                    &vcpu->hv_clock.tsc_shift,
1093                                    &vcpu->hv_clock.tsc_to_system_mul);
1094                 vcpu->hw_tsc_khz = this_tsc_khz;
1095         }
1096
1097         if (max_kernel_ns > kernel_ns)
1098                 kernel_ns = max_kernel_ns;
1099
1100         /* With all the info we got, fill in the values */
1101         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1102         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1103         vcpu->last_kernel_ns = kernel_ns;
1104         vcpu->last_guest_tsc = tsc_timestamp;
1105         vcpu->hv_clock.flags = 0;
1106
1107         /*
1108          * The interface expects us to write an even number signaling that the
1109          * update is finished. Since the guest won't see the intermediate
1110          * state, we just increase by 2 at the end.
1111          */
1112         vcpu->hv_clock.version += 2;
1113
1114         shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1115
1116         memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
1117                sizeof(vcpu->hv_clock));
1118
1119         kunmap_atomic(shared_kaddr, KM_USER0);
1120
1121         mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
1122         return 0;
1123 }
1124
1125 static int kvm_request_guest_time_update(struct kvm_vcpu *v)
1126 {
1127         struct kvm_vcpu_arch *vcpu = &v->arch;
1128
1129         if (!vcpu->time_page)
1130                 return 0;
1131         kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1132         return 1;
1133 }
1134
1135 static bool msr_mtrr_valid(unsigned msr)
1136 {
1137         switch (msr) {
1138         case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1139         case MSR_MTRRfix64K_00000:
1140         case MSR_MTRRfix16K_80000:
1141         case MSR_MTRRfix16K_A0000:
1142         case MSR_MTRRfix4K_C0000:
1143         case MSR_MTRRfix4K_C8000:
1144         case MSR_MTRRfix4K_D0000:
1145         case MSR_MTRRfix4K_D8000:
1146         case MSR_MTRRfix4K_E0000:
1147         case MSR_MTRRfix4K_E8000:
1148         case MSR_MTRRfix4K_F0000:
1149         case MSR_MTRRfix4K_F8000:
1150         case MSR_MTRRdefType:
1151         case MSR_IA32_CR_PAT:
1152                 return true;
1153         case 0x2f8:
1154                 return true;
1155         }
1156         return false;
1157 }
1158
1159 static bool valid_pat_type(unsigned t)
1160 {
1161         return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1162 }
1163
1164 static bool valid_mtrr_type(unsigned t)
1165 {
1166         return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1167 }
1168
1169 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1170 {
1171         int i;
1172
1173         if (!msr_mtrr_valid(msr))
1174                 return false;
1175
1176         if (msr == MSR_IA32_CR_PAT) {
1177                 for (i = 0; i < 8; i++)
1178                         if (!valid_pat_type((data >> (i * 8)) & 0xff))
1179                                 return false;
1180                 return true;
1181         } else if (msr == MSR_MTRRdefType) {
1182                 if (data & ~0xcff)
1183                         return false;
1184                 return valid_mtrr_type(data & 0xff);
1185         } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1186                 for (i = 0; i < 8 ; i++)
1187                         if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1188                                 return false;
1189                 return true;
1190         }
1191
1192         /* variable MTRRs */
1193         return valid_mtrr_type(data & 0xff);
1194 }
1195
1196 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1197 {
1198         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1199
1200         if (!mtrr_valid(vcpu, msr, data))
1201                 return 1;
1202
1203         if (msr == MSR_MTRRdefType) {
1204                 vcpu->arch.mtrr_state.def_type = data;
1205                 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1206         } else if (msr == MSR_MTRRfix64K_00000)
1207                 p[0] = data;
1208         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1209                 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1210         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1211                 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1212         else if (msr == MSR_IA32_CR_PAT)
1213                 vcpu->arch.pat = data;
1214         else {  /* Variable MTRRs */
1215                 int idx, is_mtrr_mask;
1216                 u64 *pt;
1217
1218                 idx = (msr - 0x200) / 2;
1219                 is_mtrr_mask = msr - 0x200 - 2 * idx;
1220                 if (!is_mtrr_mask)
1221                         pt =
1222                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1223                 else
1224                         pt =
1225                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1226                 *pt = data;
1227         }
1228
1229         kvm_mmu_reset_context(vcpu);
1230         return 0;
1231 }
1232
1233 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1234 {
1235         u64 mcg_cap = vcpu->arch.mcg_cap;
1236         unsigned bank_num = mcg_cap & 0xff;
1237
1238         switch (msr) {
1239         case MSR_IA32_MCG_STATUS:
1240                 vcpu->arch.mcg_status = data;
1241                 break;
1242         case MSR_IA32_MCG_CTL:
1243                 if (!(mcg_cap & MCG_CTL_P))
1244                         return 1;
1245                 if (data != 0 && data != ~(u64)0)
1246                         return -1;
1247                 vcpu->arch.mcg_ctl = data;
1248                 break;
1249         default:
1250                 if (msr >= MSR_IA32_MC0_CTL &&
1251                     msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1252                         u32 offset = msr - MSR_IA32_MC0_CTL;
1253                         /* only 0 or all 1s can be written to IA32_MCi_CTL
1254                          * some Linux kernels though clear bit 10 in bank 4 to
1255                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1256                          * this to avoid an uncatched #GP in the guest
1257                          */
1258                         if ((offset & 0x3) == 0 &&
1259                             data != 0 && (data | (1 << 10)) != ~(u64)0)
1260                                 return -1;
1261                         vcpu->arch.mce_banks[offset] = data;
1262                         break;
1263                 }
1264                 return 1;
1265         }
1266         return 0;
1267 }
1268
1269 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1270 {
1271         struct kvm *kvm = vcpu->kvm;
1272         int lm = is_long_mode(vcpu);
1273         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1274                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1275         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1276                 : kvm->arch.xen_hvm_config.blob_size_32;
1277         u32 page_num = data & ~PAGE_MASK;
1278         u64 page_addr = data & PAGE_MASK;
1279         u8 *page;
1280         int r;
1281
1282         r = -E2BIG;
1283         if (page_num >= blob_size)
1284                 goto out;
1285         r = -ENOMEM;
1286         page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1287         if (!page)
1288                 goto out;
1289         r = -EFAULT;
1290         if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1291                 goto out_free;
1292         if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1293                 goto out_free;
1294         r = 0;
1295 out_free:
1296         kfree(page);
1297 out:
1298         return r;
1299 }
1300
1301 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1302 {
1303         return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1304 }
1305
1306 static bool kvm_hv_msr_partition_wide(u32 msr)
1307 {
1308         bool r = false;
1309         switch (msr) {
1310         case HV_X64_MSR_GUEST_OS_ID:
1311         case HV_X64_MSR_HYPERCALL:
1312                 r = true;
1313                 break;
1314         }
1315
1316         return r;
1317 }
1318
1319 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1320 {
1321         struct kvm *kvm = vcpu->kvm;
1322
1323         switch (msr) {
1324         case HV_X64_MSR_GUEST_OS_ID:
1325                 kvm->arch.hv_guest_os_id = data;
1326                 /* setting guest os id to zero disables hypercall page */
1327                 if (!kvm->arch.hv_guest_os_id)
1328                         kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1329                 break;
1330         case HV_X64_MSR_HYPERCALL: {
1331                 u64 gfn;
1332                 unsigned long addr;
1333                 u8 instructions[4];
1334
1335                 /* if guest os id is not set hypercall should remain disabled */
1336                 if (!kvm->arch.hv_guest_os_id)
1337                         break;
1338                 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1339                         kvm->arch.hv_hypercall = data;
1340                         break;
1341                 }
1342                 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1343                 addr = gfn_to_hva(kvm, gfn);
1344                 if (kvm_is_error_hva(addr))
1345                         return 1;
1346                 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1347                 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1348                 if (copy_to_user((void __user *)addr, instructions, 4))
1349                         return 1;
1350                 kvm->arch.hv_hypercall = data;
1351                 break;
1352         }
1353         default:
1354                 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1355                           "data 0x%llx\n", msr, data);
1356                 return 1;
1357         }
1358         return 0;
1359 }
1360
1361 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1362 {
1363         switch (msr) {
1364         case HV_X64_MSR_APIC_ASSIST_PAGE: {
1365                 unsigned long addr;
1366
1367                 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1368                         vcpu->arch.hv_vapic = data;
1369                         break;
1370                 }
1371                 addr = gfn_to_hva(vcpu->kvm, data >>
1372                                   HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1373                 if (kvm_is_error_hva(addr))
1374                         return 1;
1375                 if (clear_user((void __user *)addr, PAGE_SIZE))
1376                         return 1;
1377                 vcpu->arch.hv_vapic = data;
1378                 break;
1379         }
1380         case HV_X64_MSR_EOI:
1381                 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1382         case HV_X64_MSR_ICR:
1383                 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1384         case HV_X64_MSR_TPR:
1385                 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1386         default:
1387                 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1388                           "data 0x%llx\n", msr, data);
1389                 return 1;
1390         }
1391
1392         return 0;
1393 }
1394
1395 int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1396 {
1397         switch (msr) {
1398         case MSR_EFER:
1399                 return set_efer(vcpu, data);
1400         case MSR_K7_HWCR:
1401                 data &= ~(u64)0x40;     /* ignore flush filter disable */
1402                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
1403                 if (data != 0) {
1404                         pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1405                                 data);
1406                         return 1;
1407                 }
1408                 break;
1409         case MSR_FAM10H_MMIO_CONF_BASE:
1410                 if (data != 0) {
1411                         pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1412                                 "0x%llx\n", data);
1413                         return 1;
1414                 }
1415                 break;
1416         case MSR_AMD64_NB_CFG:
1417                 break;
1418         case MSR_IA32_DEBUGCTLMSR:
1419                 if (!data) {
1420                         /* We support the non-activated case already */
1421                         break;
1422                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1423                         /* Values other than LBR and BTF are vendor-specific,
1424                            thus reserved and should throw a #GP */
1425                         return 1;
1426                 }
1427                 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1428                         __func__, data);
1429                 break;
1430         case MSR_IA32_UCODE_REV:
1431         case MSR_IA32_UCODE_WRITE:
1432         case MSR_VM_HSAVE_PA:
1433         case MSR_AMD64_PATCH_LOADER:
1434                 break;
1435         case 0x200 ... 0x2ff:
1436                 return set_msr_mtrr(vcpu, msr, data);
1437         case MSR_IA32_APICBASE:
1438                 kvm_set_apic_base(vcpu, data);
1439                 break;
1440         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1441                 return kvm_x2apic_msr_write(vcpu, msr, data);
1442         case MSR_IA32_MISC_ENABLE:
1443                 vcpu->arch.ia32_misc_enable_msr = data;
1444                 break;
1445         case MSR_KVM_WALL_CLOCK_NEW:
1446         case MSR_KVM_WALL_CLOCK:
1447                 vcpu->kvm->arch.wall_clock = data;
1448                 kvm_write_wall_clock(vcpu->kvm, data);
1449                 break;
1450         case MSR_KVM_SYSTEM_TIME_NEW:
1451         case MSR_KVM_SYSTEM_TIME: {
1452                 if (vcpu->arch.time_page) {
1453                         kvm_release_page_dirty(vcpu->arch.time_page);
1454                         vcpu->arch.time_page = NULL;
1455                 }
1456
1457                 vcpu->arch.time = data;
1458
1459                 /* we verify if the enable bit is set... */
1460                 if (!(data & 1))
1461                         break;
1462
1463                 /* ...but clean it before doing the actual write */
1464                 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1465
1466                 vcpu->arch.time_page =
1467                                 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
1468
1469                 if (is_error_page(vcpu->arch.time_page)) {
1470                         kvm_release_page_clean(vcpu->arch.time_page);
1471                         vcpu->arch.time_page = NULL;
1472                 }
1473
1474                 kvm_request_guest_time_update(vcpu);
1475                 break;
1476         }
1477         case MSR_IA32_MCG_CTL:
1478         case MSR_IA32_MCG_STATUS:
1479         case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1480                 return set_msr_mce(vcpu, msr, data);
1481
1482         /* Performance counters are not protected by a CPUID bit,
1483          * so we should check all of them in the generic path for the sake of
1484          * cross vendor migration.
1485          * Writing a zero into the event select MSRs disables them,
1486          * which we perfectly emulate ;-). Any other value should be at least
1487          * reported, some guests depend on them.
1488          */
1489         case MSR_P6_EVNTSEL0:
1490         case MSR_P6_EVNTSEL1:
1491         case MSR_K7_EVNTSEL0:
1492         case MSR_K7_EVNTSEL1:
1493         case MSR_K7_EVNTSEL2:
1494         case MSR_K7_EVNTSEL3:
1495                 if (data != 0)
1496                         pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1497                                 "0x%x data 0x%llx\n", msr, data);
1498                 break;
1499         /* at least RHEL 4 unconditionally writes to the perfctr registers,
1500          * so we ignore writes to make it happy.
1501          */
1502         case MSR_P6_PERFCTR0:
1503         case MSR_P6_PERFCTR1:
1504         case MSR_K7_PERFCTR0:
1505         case MSR_K7_PERFCTR1:
1506         case MSR_K7_PERFCTR2:
1507         case MSR_K7_PERFCTR3:
1508                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1509                         "0x%x data 0x%llx\n", msr, data);
1510                 break;
1511         case MSR_K7_CLK_CTL:
1512                 /*
1513                  * Ignore all writes to this no longer documented MSR.
1514                  * Writes are only relevant for old K7 processors,
1515                  * all pre-dating SVM, but a recommended workaround from
1516                  * AMD for these chips. It is possible to speicify the
1517                  * affected processor models on the command line, hence
1518                  * the need to ignore the workaround.
1519                  */
1520                 break;
1521         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1522                 if (kvm_hv_msr_partition_wide(msr)) {
1523                         int r;
1524                         mutex_lock(&vcpu->kvm->lock);
1525                         r = set_msr_hyperv_pw(vcpu, msr, data);
1526                         mutex_unlock(&vcpu->kvm->lock);
1527                         return r;
1528                 } else
1529                         return set_msr_hyperv(vcpu, msr, data);
1530                 break;
1531         default:
1532                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1533                         return xen_hvm_config(vcpu, data);
1534                 if (!ignore_msrs) {
1535                         pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1536                                 msr, data);
1537                         return 1;
1538                 } else {
1539                         pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1540                                 msr, data);
1541                         break;
1542                 }
1543         }
1544         return 0;
1545 }
1546 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1547
1548
1549 /*
1550  * Reads an msr value (of 'msr_index') into 'pdata'.
1551  * Returns 0 on success, non-0 otherwise.
1552  * Assumes vcpu_load() was already called.
1553  */
1554 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1555 {
1556         return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1557 }
1558
1559 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1560 {
1561         u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1562
1563         if (!msr_mtrr_valid(msr))
1564                 return 1;
1565
1566         if (msr == MSR_MTRRdefType)
1567                 *pdata = vcpu->arch.mtrr_state.def_type +
1568                          (vcpu->arch.mtrr_state.enabled << 10);
1569         else if (msr == MSR_MTRRfix64K_00000)
1570                 *pdata = p[0];
1571         else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1572                 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1573         else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1574                 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1575         else if (msr == MSR_IA32_CR_PAT)
1576                 *pdata = vcpu->arch.pat;
1577         else {  /* Variable MTRRs */
1578                 int idx, is_mtrr_mask;
1579                 u64 *pt;
1580
1581                 idx = (msr - 0x200) / 2;
1582                 is_mtrr_mask = msr - 0x200 - 2 * idx;
1583                 if (!is_mtrr_mask)
1584                         pt =
1585                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1586                 else
1587                         pt =
1588                           (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1589                 *pdata = *pt;
1590         }
1591
1592         return 0;
1593 }
1594
1595 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1596 {
1597         u64 data;
1598         u64 mcg_cap = vcpu->arch.mcg_cap;
1599         unsigned bank_num = mcg_cap & 0xff;
1600
1601         switch (msr) {
1602         case MSR_IA32_P5_MC_ADDR:
1603         case MSR_IA32_P5_MC_TYPE:
1604                 data = 0;
1605                 break;
1606         case MSR_IA32_MCG_CAP:
1607                 data = vcpu->arch.mcg_cap;
1608                 break;
1609         case MSR_IA32_MCG_CTL:
1610                 if (!(mcg_cap & MCG_CTL_P))
1611                         return 1;
1612                 data = vcpu->arch.mcg_ctl;
1613                 break;
1614         case MSR_IA32_MCG_STATUS:
1615                 data = vcpu->arch.mcg_status;
1616                 break;
1617         default:
1618                 if (msr >= MSR_IA32_MC0_CTL &&
1619                     msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1620                         u32 offset = msr - MSR_IA32_MC0_CTL;
1621                         data = vcpu->arch.mce_banks[offset];
1622                         break;
1623                 }
1624                 return 1;
1625         }
1626         *pdata = data;
1627         return 0;
1628 }
1629
1630 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1631 {
1632         u64 data = 0;
1633         struct kvm *kvm = vcpu->kvm;
1634
1635         switch (msr) {
1636         case HV_X64_MSR_GUEST_OS_ID:
1637                 data = kvm->arch.hv_guest_os_id;
1638                 break;
1639         case HV_X64_MSR_HYPERCALL:
1640                 data = kvm->arch.hv_hypercall;
1641                 break;
1642         default:
1643                 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1644                 return 1;
1645         }
1646
1647         *pdata = data;
1648         return 0;
1649 }
1650
1651 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1652 {
1653         u64 data = 0;
1654
1655         switch (msr) {
1656         case HV_X64_MSR_VP_INDEX: {
1657                 int r;
1658                 struct kvm_vcpu *v;
1659                 kvm_for_each_vcpu(r, v, vcpu->kvm)
1660                         if (v == vcpu)
1661                                 data = r;
1662                 break;
1663         }
1664         case HV_X64_MSR_EOI:
1665                 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1666         case HV_X64_MSR_ICR:
1667                 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1668         case HV_X64_MSR_TPR:
1669                 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
1670         default:
1671                 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1672                 return 1;
1673         }
1674         *pdata = data;
1675         return 0;
1676 }
1677
1678 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1679 {
1680         u64 data;
1681
1682         switch (msr) {
1683         case MSR_IA32_PLATFORM_ID:
1684         case MSR_IA32_UCODE_REV:
1685         case MSR_IA32_EBL_CR_POWERON:
1686         case MSR_IA32_DEBUGCTLMSR:
1687         case MSR_IA32_LASTBRANCHFROMIP:
1688         case MSR_IA32_LASTBRANCHTOIP:
1689         case MSR_IA32_LASTINTFROMIP:
1690         case MSR_IA32_LASTINTTOIP:
1691         case MSR_K8_SYSCFG:
1692         case MSR_K7_HWCR:
1693         case MSR_VM_HSAVE_PA:
1694         case MSR_P6_PERFCTR0:
1695         case MSR_P6_PERFCTR1:
1696         case MSR_P6_EVNTSEL0:
1697         case MSR_P6_EVNTSEL1:
1698         case MSR_K7_EVNTSEL0:
1699         case MSR_K7_PERFCTR0:
1700         case MSR_K8_INT_PENDING_MSG:
1701         case MSR_AMD64_NB_CFG:
1702         case MSR_FAM10H_MMIO_CONF_BASE:
1703                 data = 0;
1704                 break;
1705         case MSR_MTRRcap:
1706                 data = 0x500 | KVM_NR_VAR_MTRR;
1707                 break;
1708         case 0x200 ... 0x2ff:
1709                 return get_msr_mtrr(vcpu, msr, pdata);
1710         case 0xcd: /* fsb frequency */
1711                 data = 3;
1712                 break;
1713                 /*
1714                  * MSR_EBC_FREQUENCY_ID
1715                  * Conservative value valid for even the basic CPU models.
1716                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1717                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1718                  * and 266MHz for model 3, or 4. Set Core Clock
1719                  * Frequency to System Bus Frequency Ratio to 1 (bits
1720                  * 31:24) even though these are only valid for CPU
1721                  * models > 2, however guests may end up dividing or
1722                  * multiplying by zero otherwise.
1723                  */
1724         case MSR_EBC_FREQUENCY_ID:
1725                 data = 1 << 24;
1726                 break;
1727         case MSR_IA32_APICBASE:
1728                 data = kvm_get_apic_base(vcpu);
1729                 break;
1730         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1731                 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1732                 break;
1733         case MSR_IA32_MISC_ENABLE:
1734                 data = vcpu->arch.ia32_misc_enable_msr;
1735                 break;
1736         case MSR_IA32_PERF_STATUS:
1737                 /* TSC increment by tick */
1738                 data = 1000ULL;
1739                 /* CPU multiplier */
1740                 data |= (((uint64_t)4ULL) << 40);
1741                 break;
1742         case MSR_EFER:
1743                 data = vcpu->arch.efer;
1744                 break;
1745         case MSR_KVM_WALL_CLOCK:
1746         case MSR_KVM_WALL_CLOCK_NEW:
1747                 data = vcpu->kvm->arch.wall_clock;
1748                 break;
1749         case MSR_KVM_SYSTEM_TIME:
1750         case MSR_KVM_SYSTEM_TIME_NEW:
1751                 data = vcpu->arch.time;
1752                 break;
1753         case MSR_IA32_P5_MC_ADDR:
1754         case MSR_IA32_P5_MC_TYPE:
1755         case MSR_IA32_MCG_CAP:
1756         case MSR_IA32_MCG_CTL:
1757         case MSR_IA32_MCG_STATUS:
1758         case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1759                 return get_msr_mce(vcpu, msr, pdata);
1760         case MSR_K7_CLK_CTL:
1761                 /*
1762                  * Provide expected ramp-up count for K7. All other
1763                  * are set to zero, indicating minimum divisors for
1764                  * every field.
1765                  *
1766                  * This prevents guest kernels on AMD host with CPU
1767                  * type 6, model 8 and higher from exploding due to
1768                  * the rdmsr failing.
1769                  */
1770                 data = 0x20000000;
1771                 break;
1772         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1773                 if (kvm_hv_msr_partition_wide(msr)) {
1774                         int r;
1775                         mutex_lock(&vcpu->kvm->lock);
1776                         r = get_msr_hyperv_pw(vcpu, msr, pdata);
1777                         mutex_unlock(&vcpu->kvm->lock);
1778                         return r;
1779                 } else
1780                         return get_msr_hyperv(vcpu, msr, pdata);
1781                 break;
1782         default:
1783                 if (!ignore_msrs) {
1784                         pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1785                         return 1;
1786                 } else {
1787                         pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1788                         data = 0;
1789                 }
1790                 break;
1791         }
1792         *pdata = data;
1793         return 0;
1794 }
1795 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1796
1797 /*
1798  * Read or write a bunch of msrs. All parameters are kernel addresses.
1799  *
1800  * @return number of msrs set successfully.
1801  */
1802 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1803                     struct kvm_msr_entry *entries,
1804                     int (*do_msr)(struct kvm_vcpu *vcpu,
1805                                   unsigned index, u64 *data))
1806 {
1807         int i, idx;
1808
1809         idx = srcu_read_lock(&vcpu->kvm->srcu);
1810         for (i = 0; i < msrs->nmsrs; ++i)
1811                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1812                         break;
1813         srcu_read_unlock(&vcpu->kvm->srcu, idx);
1814
1815         return i;
1816 }
1817
1818 /*
1819  * Read or write a bunch of msrs. Parameters are user addresses.
1820  *
1821  * @return number of msrs set successfully.
1822  */
1823 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1824                   int (*do_msr)(struct kvm_vcpu *vcpu,
1825                                 unsigned index, u64 *data),
1826                   int writeback)
1827 {
1828         struct kvm_msrs msrs;
1829         struct kvm_msr_entry *entries;
1830         int r, n;
1831         unsigned size;
1832
1833         r = -EFAULT;
1834         if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1835                 goto out;
1836
1837         r = -E2BIG;
1838         if (msrs.nmsrs >= MAX_IO_MSRS)
1839                 goto out;
1840
1841         r = -ENOMEM;
1842         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1843         entries = kmalloc(size, GFP_KERNEL);
1844         if (!entries)
1845                 goto out;
1846
1847         r = -EFAULT;
1848         if (copy_from_user(entries, user_msrs->entries, size))
1849                 goto out_free;
1850
1851         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1852         if (r < 0)
1853                 goto out_free;
1854
1855         r = -EFAULT;
1856         if (writeback && copy_to_user(user_msrs->entries, entries, size))
1857                 goto out_free;
1858
1859         r = n;
1860
1861 out_free:
1862         kfree(entries);
1863 out:
1864         return r;
1865 }
1866
1867 int kvm_dev_ioctl_check_extension(long ext)
1868 {
1869         int r;
1870
1871         switch (ext) {
1872         case KVM_CAP_IRQCHIP:
1873         case KVM_CAP_HLT:
1874         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
1875         case KVM_CAP_SET_TSS_ADDR:
1876         case KVM_CAP_EXT_CPUID:
1877         case KVM_CAP_CLOCKSOURCE:
1878         case KVM_CAP_PIT:
1879         case KVM_CAP_NOP_IO_DELAY:
1880         case KVM_CAP_MP_STATE:
1881         case KVM_CAP_SYNC_MMU:
1882         case KVM_CAP_REINJECT_CONTROL:
1883         case KVM_CAP_IRQ_INJECT_STATUS:
1884         case KVM_CAP_ASSIGN_DEV_IRQ:
1885         case KVM_CAP_IRQFD:
1886         case KVM_CAP_IOEVENTFD:
1887         case KVM_CAP_PIT2:
1888         case KVM_CAP_PIT_STATE2:
1889         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
1890         case KVM_CAP_XEN_HVM:
1891         case KVM_CAP_ADJUST_CLOCK:
1892         case KVM_CAP_VCPU_EVENTS:
1893         case KVM_CAP_HYPERV:
1894         case KVM_CAP_HYPERV_VAPIC:
1895         case KVM_CAP_HYPERV_SPIN:
1896         case KVM_CAP_PCI_SEGMENT:
1897         case KVM_CAP_DEBUGREGS:
1898         case KVM_CAP_X86_ROBUST_SINGLESTEP:
1899         case KVM_CAP_XSAVE:
1900                 r = 1;
1901                 break;
1902         case KVM_CAP_COALESCED_MMIO:
1903                 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1904                 break;
1905         case KVM_CAP_VAPIC:
1906                 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1907                 break;
1908         case KVM_CAP_NR_VCPUS:
1909                 r = KVM_MAX_VCPUS;
1910                 break;
1911         case KVM_CAP_NR_MEMSLOTS:
1912                 r = KVM_MEMORY_SLOTS;
1913                 break;
1914         case KVM_CAP_PV_MMU:    /* obsolete */
1915                 r = 0;
1916                 break;
1917         case KVM_CAP_IOMMU:
1918                 r = iommu_found();
1919                 break;
1920         case KVM_CAP_MCE:
1921                 r = KVM_MAX_MCE_BANKS;
1922                 break;
1923         case KVM_CAP_XCRS:
1924                 r = cpu_has_xsave;
1925                 break;
1926         default:
1927                 r = 0;
1928                 break;
1929         }
1930         return r;
1931
1932 }
1933
1934 long kvm_arch_dev_ioctl(struct file *filp,
1935                         unsigned int ioctl, unsigned long arg)
1936 {
1937         void __user *argp = (void __user *)arg;
1938         long r;
1939
1940         switch (ioctl) {
1941         case KVM_GET_MSR_INDEX_LIST: {
1942                 struct kvm_msr_list __user *user_msr_list = argp;
1943                 struct kvm_msr_list msr_list;
1944                 unsigned n;
1945
1946                 r = -EFAULT;
1947                 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1948                         goto out;
1949                 n = msr_list.nmsrs;
1950                 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1951                 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1952                         goto out;
1953                 r = -E2BIG;
1954                 if (n < msr_list.nmsrs)
1955                         goto out;
1956                 r = -EFAULT;
1957                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1958                                  num_msrs_to_save * sizeof(u32)))
1959                         goto out;
1960                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
1961                                  &emulated_msrs,
1962                                  ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1963                         goto out;
1964                 r = 0;
1965                 break;
1966         }
1967         case KVM_GET_SUPPORTED_CPUID: {
1968                 struct kvm_cpuid2 __user *cpuid_arg = argp;
1969                 struct kvm_cpuid2 cpuid;
1970
1971                 r = -EFAULT;
1972                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1973                         goto out;
1974                 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
1975                                                       cpuid_arg->entries);
1976                 if (r)
1977                         goto out;
1978
1979                 r = -EFAULT;
1980                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1981                         goto out;
1982                 r = 0;
1983                 break;
1984         }
1985         case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1986                 u64 mce_cap;
1987
1988                 mce_cap = KVM_MCE_CAP_SUPPORTED;
1989                 r = -EFAULT;
1990                 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1991                         goto out;
1992                 r = 0;
1993                 break;
1994         }
1995         default:
1996                 r = -EINVAL;
1997         }
1998 out:
1999         return r;
2000 }
2001
2002 static void wbinvd_ipi(void *garbage)
2003 {
2004         wbinvd();
2005 }
2006
2007 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2008 {
2009         return vcpu->kvm->arch.iommu_domain &&
2010                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2011 }
2012
2013 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2014 {
2015         /* Address WBINVD may be executed by guest */
2016         if (need_emulate_wbinvd(vcpu)) {
2017                 if (kvm_x86_ops->has_wbinvd_exit())
2018                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2019                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2020                         smp_call_function_single(vcpu->cpu,
2021                                         wbinvd_ipi, NULL, 1);
2022         }
2023
2024         kvm_x86_ops->vcpu_load(vcpu, cpu);
2025         if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2026                 /* Make sure TSC doesn't go backwards */
2027                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2028                                 native_read_tsc() - vcpu->arch.last_host_tsc;
2029                 if (tsc_delta < 0)
2030                         mark_tsc_unstable("KVM discovered backwards TSC");
2031                 if (check_tsc_unstable())
2032                         kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
2033                 kvm_migrate_timers(vcpu);
2034                 vcpu->cpu = cpu;
2035         }
2036 }
2037
2038 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2039 {
2040         kvm_x86_ops->vcpu_put(vcpu);
2041         kvm_put_guest_fpu(vcpu);
2042         vcpu->arch.last_host_tsc = native_read_tsc();
2043 }
2044
2045 static int is_efer_nx(void)
2046 {
2047         unsigned long long efer = 0;
2048
2049         rdmsrl_safe(MSR_EFER, &efer);
2050         return efer & EFER_NX;
2051 }
2052
2053 static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2054 {
2055         int i;
2056         struct kvm_cpuid_entry2 *e, *entry;
2057
2058         entry = NULL;
2059         for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2060                 e = &vcpu->arch.cpuid_entries[i];
2061                 if (e->function == 0x80000001) {
2062                         entry = e;
2063                         break;
2064                 }
2065         }
2066         if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
2067                 entry->edx &= ~(1 << 20);
2068                 printk(KERN_INFO "kvm: guest NX capability removed\n");
2069         }
2070 }
2071
2072 /* when an old userspace process fills a new kernel module */
2073 static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2074                                     struct kvm_cpuid *cpuid,
2075                                     struct kvm_cpuid_entry __user *entries)
2076 {
2077         int r, i;
2078         struct kvm_cpuid_entry *cpuid_entries;
2079
2080         r = -E2BIG;
2081         if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2082                 goto out;
2083         r = -ENOMEM;
2084         cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2085         if (!cpuid_entries)
2086                 goto out;
2087         r = -EFAULT;
2088         if (copy_from_user(cpuid_entries, entries,
2089                            cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2090                 goto out_free;
2091         for (i = 0; i < cpuid->nent; i++) {
2092                 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2093                 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2094                 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2095                 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2096                 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2097                 vcpu->arch.cpuid_entries[i].index = 0;
2098                 vcpu->arch.cpuid_entries[i].flags = 0;
2099                 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2100                 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2101                 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2102         }
2103         vcpu->arch.cpuid_nent = cpuid->nent;
2104         cpuid_fix_nx_cap(vcpu);
2105         r = 0;
2106         kvm_apic_set_version(vcpu);
2107         kvm_x86_ops->cpuid_update(vcpu);
2108         update_cpuid(vcpu);
2109
2110 out_free:
2111         vfree(cpuid_entries);
2112 out:
2113         return r;
2114 }
2115
2116 static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
2117                                      struct kvm_cpuid2 *cpuid,
2118                                      struct kvm_cpuid_entry2 __user *entries)
2119 {
2120         int r;
2121
2122         r = -E2BIG;
2123         if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2124                 goto out;
2125         r = -EFAULT;
2126         if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
2127                            cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
2128                 goto out;
2129         vcpu->arch.cpuid_nent = cpuid->nent;
2130         kvm_apic_set_version(vcpu);
2131         kvm_x86_ops->cpuid_update(vcpu);
2132         update_cpuid(vcpu);
2133         return 0;
2134
2135 out:
2136         return r;
2137 }
2138
2139 static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
2140                                      struct kvm_cpuid2 *cpuid,
2141                                      struct kvm_cpuid_entry2 __user *entries)
2142 {
2143         int r;
2144
2145         r = -E2BIG;
2146         if (cpuid->nent < vcpu->arch.cpuid_nent)
2147                 goto out;
2148         r = -EFAULT;
2149         if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
2150                          vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
2151                 goto out;
2152         return 0;
2153
2154 out:
2155         cpuid->nent = vcpu->arch.cpuid_nent;
2156         return r;
2157 }
2158
2159 static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2160                            u32 index)
2161 {
2162         entry->function = function;
2163         entry->index = index;
2164         cpuid_count(entry->function, entry->index,
2165                     &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
2166         entry->flags = 0;
2167 }
2168
2169 #define F(x) bit(X86_FEATURE_##x)
2170
2171 static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2172                          u32 index, int *nent, int maxnent)
2173 {
2174         unsigned f_nx = is_efer_nx() ? F(NX) : 0;
2175 #ifdef CONFIG_X86_64
2176         unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2177                                 ? F(GBPAGES) : 0;
2178         unsigned f_lm = F(LM);
2179 #else
2180         unsigned f_gbpages = 0;
2181         unsigned f_lm = 0;
2182 #endif
2183         unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
2184
2185         /* cpuid 1.edx */
2186         const u32 kvm_supported_word0_x86_features =
2187                 F(FPU) | F(VME) | F(DE) | F(PSE) |
2188                 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2189                 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2190                 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2191                 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2192                 0 /* Reserved, DS, ACPI */ | F(MMX) |
2193                 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2194                 0 /* HTT, TM, Reserved, PBE */;
2195         /* cpuid 0x80000001.edx */
2196         const u32 kvm_supported_word1_x86_features =
2197                 F(FPU) | F(VME) | F(DE) | F(PSE) |
2198                 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2199                 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2200                 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2201                 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2202                 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
2203                 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
2204                 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2205         /* cpuid 1.ecx */
2206         const u32 kvm_supported_word4_x86_features =
2207                 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
2208                 0 /* DS-CPL, VMX, SMX, EST */ |
2209                 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2210                 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2211                 0 /* Reserved, DCA */ | F(XMM4_1) |
2212                 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
2213                 0 /* Reserved, AES */ | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX);
2214         /* cpuid 0x80000001.ecx */
2215         const u32 kvm_supported_word6_x86_features =
2216                 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
2217                 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
2218                 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
2219                 0 /* SKINIT */ | 0 /* WDT */;
2220
2221         /* all calls to cpuid_count() should be made on the same cpu */
2222         get_cpu();
2223         do_cpuid_1_ent(entry, function, index);
2224         ++*nent;
2225
2226         switch (function) {
2227         case 0:
2228                 entry->eax = min(entry->eax, (u32)0xd);
2229                 break;
2230         case 1:
2231                 entry->edx &= kvm_supported_word0_x86_features;
2232                 entry->ecx &= kvm_supported_word4_x86_features;
2233                 /* we support x2apic emulation even if host does not support
2234                  * it since we emulate x2apic in software */
2235                 entry->ecx |= F(X2APIC);
2236                 break;
2237         /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2238          * may return different values. This forces us to get_cpu() before
2239          * issuing the first command, and also to emulate this annoying behavior
2240          * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2241         case 2: {
2242                 int t, times = entry->eax & 0xff;
2243
2244                 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2245                 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2246                 for (t = 1; t < times && *nent < maxnent; ++t) {
2247                         do_cpuid_1_ent(&entry[t], function, 0);
2248                         entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2249                         ++*nent;
2250                 }
2251                 break;
2252         }
2253         /* function 4 and 0xb have additional index. */
2254         case 4: {
2255                 int i, cache_type;
2256
2257                 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2258                 /* read more entries until cache_type is zero */
2259                 for (i = 1; *nent < maxnent; ++i) {
2260                         cache_type = entry[i - 1].eax & 0x1f;
2261                         if (!cache_type)
2262                                 break;
2263                         do_cpuid_1_ent(&entry[i], function, i);
2264                         entry[i].flags |=
2265                                KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2266                         ++*nent;
2267                 }
2268                 break;
2269         }
2270         case 0xb: {
2271                 int i, level_type;
2272
2273                 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2274                 /* read more entries until level_type is zero */
2275                 for (i = 1; *nent < maxnent; ++i) {
2276                         level_type = entry[i - 1].ecx & 0xff00;
2277                         if (!level_type)
2278                                 break;
2279                         do_cpuid_1_ent(&entry[i], function, i);
2280                         entry[i].flags |=
2281                                KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2282                         ++*nent;
2283                 }
2284                 break;
2285         }
2286         case 0xd: {
2287                 int i;
2288
2289                 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2290                 for (i = 1; *nent < maxnent; ++i) {
2291                         if (entry[i - 1].eax == 0 && i != 2)
2292                                 break;
2293                         do_cpuid_1_ent(&entry[i], function, i);
2294                         entry[i].flags |=
2295                                KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2296                         ++*nent;
2297                 }
2298                 break;
2299         }
2300         case KVM_CPUID_SIGNATURE: {
2301                 char signature[12] = "KVMKVMKVM\0\0";
2302                 u32 *sigptr = (u32 *)signature;
2303                 entry->eax = 0;
2304                 entry->ebx = sigptr[0];
2305                 entry->ecx = sigptr[1];
2306                 entry->edx = sigptr[2];
2307                 break;
2308         }
2309         case KVM_CPUID_FEATURES:
2310                 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2311                              (1 << KVM_FEATURE_NOP_IO_DELAY) |
2312                              (1 << KVM_FEATURE_CLOCKSOURCE2) |
2313                              (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
2314                 entry->ebx = 0;
2315                 entry->ecx = 0;
2316                 entry->edx = 0;
2317                 break;
2318         case 0x80000000:
2319                 entry->eax = min(entry->eax, 0x8000001a);
2320                 break;
2321         case 0x80000001:
2322                 entry->edx &= kvm_supported_word1_x86_features;
2323                 entry->ecx &= kvm_supported_word6_x86_features;
2324                 break;
2325         }
2326
2327         kvm_x86_ops->set_supported_cpuid(function, entry);
2328
2329         put_cpu();
2330 }
2331
2332 #undef F
2333
2334 static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
2335                                      struct kvm_cpuid_entry2 __user *entries)
2336 {
2337         struct kvm_cpuid_entry2 *cpuid_entries;
2338         int limit, nent = 0, r = -E2BIG;
2339         u32 func;
2340
2341         if (cpuid->nent < 1)
2342                 goto out;
2343         if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2344                 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
2345         r = -ENOMEM;
2346         cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2347         if (!cpuid_entries)
2348                 goto out;
2349
2350         do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2351         limit = cpuid_entries[0].eax;
2352         for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2353                 do_cpuid_ent(&cpuid_entries[nent], func, 0,
2354                              &nent, cpuid->nent);
2355         r = -E2BIG;
2356         if (nent >= cpuid->nent)
2357                 goto out_free;
2358
2359         do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2360         limit = cpuid_entries[nent - 1].eax;
2361         for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2362                 do_cpuid_ent(&cpuid_entries[nent], func, 0,
2363                              &nent, cpuid->nent);
2364
2365
2366
2367         r = -E2BIG;
2368         if (nent >= cpuid->nent)
2369                 goto out_free;
2370
2371         do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2372                      cpuid->nent);
2373
2374         r = -E2BIG;
2375         if (nent >= cpuid->nent)
2376                 goto out_free;
2377
2378         do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2379                      cpuid->nent);
2380
2381         r = -E2BIG;
2382         if (nent >= cpuid->nent)
2383                 goto out_free;
2384
2385         r = -EFAULT;
2386         if (copy_to_user(entries, cpuid_entries,
2387                          nent * sizeof(struct kvm_cpuid_entry2)))
2388                 goto out_free;
2389         cpuid->nent = nent;
2390         r = 0;
2391
2392 out_free:
2393         vfree(cpuid_entries);
2394 out:
2395         return r;
2396 }
2397
2398 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2399                                     struct kvm_lapic_state *s)
2400 {
2401         memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2402
2403         return 0;
2404 }
2405
2406 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2407                                     struct kvm_lapic_state *s)
2408 {
2409         memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
2410         kvm_apic_post_state_restore(vcpu);
2411         update_cr8_intercept(vcpu);
2412
2413         return 0;
2414 }
2415
2416 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2417                                     struct kvm_interrupt *irq)
2418 {
2419         if (irq->irq < 0 || irq->irq >= 256)
2420                 return -EINVAL;
2421         if (irqchip_in_kernel(vcpu->kvm))
2422                 return -ENXIO;
2423
2424         kvm_queue_interrupt(vcpu, irq->irq, false);
2425         kvm_make_request(KVM_REQ_EVENT, vcpu);
2426
2427         return 0;
2428 }
2429
2430 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2431 {
2432         kvm_inject_nmi(vcpu);
2433
2434         return 0;
2435 }
2436
2437 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2438                                            struct kvm_tpr_access_ctl *tac)
2439 {
2440         if (tac->flags)
2441                 return -EINVAL;
2442         vcpu->arch.tpr_access_reporting = !!tac->enabled;
2443         return 0;
2444 }
2445
2446 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2447                                         u64 mcg_cap)
2448 {
2449         int r;
2450         unsigned bank_num = mcg_cap & 0xff, bank;
2451
2452         r = -EINVAL;
2453         if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2454                 goto out;
2455         if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2456                 goto out;
2457         r = 0;
2458         vcpu->arch.mcg_cap = mcg_cap;
2459         /* Init IA32_MCG_CTL to all 1s */
2460         if (mcg_cap & MCG_CTL_P)
2461                 vcpu->arch.mcg_ctl = ~(u64)0;
2462         /* Init IA32_MCi_CTL to all 1s */
2463         for (bank = 0; bank < bank_num; bank++)
2464                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2465 out:
2466         return r;
2467 }
2468
2469 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2470                                       struct kvm_x86_mce *mce)
2471 {
2472         u64 mcg_cap = vcpu->arch.mcg_cap;
2473         unsigned bank_num = mcg_cap & 0xff;
2474         u64 *banks = vcpu->arch.mce_banks;
2475
2476         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2477                 return -EINVAL;
2478         /*
2479          * if IA32_MCG_CTL is not all 1s, the uncorrected error
2480          * reporting is disabled
2481          */
2482         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2483             vcpu->arch.mcg_ctl != ~(u64)0)
2484                 return 0;
2485         banks += 4 * mce->bank;
2486         /*
2487          * if IA32_MCi_CTL is not all 1s, the uncorrected error
2488          * reporting is disabled for the bank
2489          */
2490         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2491                 return 0;
2492         if (mce->status & MCI_STATUS_UC) {
2493                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2494                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2495                         printk(KERN_DEBUG "kvm: set_mce: "
2496                                "injects mce exception while "
2497                                "previous one is in progress!\n");
2498                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2499                         return 0;
2500                 }
2501                 if (banks[1] & MCI_STATUS_VAL)
2502                         mce->status |= MCI_STATUS_OVER;
2503                 banks[2] = mce->addr;
2504                 banks[3] = mce->misc;
2505                 vcpu->arch.mcg_status = mce->mcg_status;
2506                 banks[1] = mce->status;
2507                 kvm_queue_exception(vcpu, MC_VECTOR);
2508         } else if (!(banks[1] & MCI_STATUS_VAL)
2509                    || !(banks[1] & MCI_STATUS_UC)) {
2510                 if (banks[1] & MCI_STATUS_VAL)
2511                         mce->status |= MCI_STATUS_OVER;
2512                 banks[2] = mce->addr;
2513                 banks[3] = mce->misc;
2514                 banks[1] = mce->status;
2515         } else
2516                 banks[1] |= MCI_STATUS_OVER;
2517         return 0;
2518 }
2519
2520 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2521                                                struct kvm_vcpu_events *events)
2522 {
2523         events->exception.injected =
2524                 vcpu->arch.exception.pending &&
2525                 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2526         events->exception.nr = vcpu->arch.exception.nr;
2527         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2528         events->exception.error_code = vcpu->arch.exception.error_code;
2529
2530         events->interrupt.injected =
2531                 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2532         events->interrupt.nr = vcpu->arch.interrupt.nr;
2533         events->interrupt.soft = 0;
2534         events->interrupt.shadow =
2535                 kvm_x86_ops->get_interrupt_shadow(vcpu,
2536                         KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2537
2538         events->nmi.injected = vcpu->arch.nmi_injected;
2539         events->nmi.pending = vcpu->arch.nmi_pending;
2540         events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2541
2542         events->sipi_vector = vcpu->arch.sipi_vector;
2543
2544         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2545                          | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2546                          | KVM_VCPUEVENT_VALID_SHADOW);
2547 }
2548
2549 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2550                                               struct kvm_vcpu_events *events)
2551 {
2552         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2553                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2554                               | KVM_VCPUEVENT_VALID_SHADOW))
2555                 return -EINVAL;
2556
2557         vcpu->arch.exception.pending = events->exception.injected;
2558         vcpu->arch.exception.nr = events->exception.nr;
2559         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2560         vcpu->arch.exception.error_code = events->exception.error_code;
2561
2562         vcpu->arch.interrupt.pending = events->interrupt.injected;
2563         vcpu->arch.interrupt.nr = events->interrupt.nr;
2564         vcpu->arch.interrupt.soft = events->interrupt.soft;
2565         if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2566                 kvm_pic_clear_isr_ack(vcpu->kvm);
2567         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2568                 kvm_x86_ops->set_interrupt_shadow(vcpu,
2569                                                   events->interrupt.shadow);
2570
2571         vcpu->arch.nmi_injected = events->nmi.injected;
2572         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2573                 vcpu->arch.nmi_pending = events->nmi.pending;
2574         kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2575
2576         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2577                 vcpu->arch.sipi_vector = events->sipi_vector;
2578
2579         kvm_make_request(KVM_REQ_EVENT, vcpu);
2580
2581         return 0;
2582 }
2583
2584 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2585                                              struct kvm_debugregs *dbgregs)
2586 {
2587         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2588         dbgregs->dr6 = vcpu->arch.dr6;
2589         dbgregs->dr7 = vcpu->arch.dr7;
2590         dbgregs->flags = 0;
2591 }
2592
2593 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2594                                             struct kvm_debugregs *dbgregs)
2595 {
2596         if (dbgregs->flags)
2597                 return -EINVAL;
2598
2599         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2600         vcpu->arch.dr6 = dbgregs->dr6;
2601         vcpu->arch.dr7 = dbgregs->dr7;
2602
2603         return 0;
2604 }
2605
2606 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2607                                          struct kvm_xsave *guest_xsave)
2608 {
2609         if (cpu_has_xsave)
2610                 memcpy(guest_xsave->region,
2611                         &vcpu->arch.guest_fpu.state->xsave,
2612                         xstate_size);
2613         else {
2614                 memcpy(guest_xsave->region,
2615                         &vcpu->arch.guest_fpu.state->fxsave,
2616                         sizeof(struct i387_fxsave_struct));
2617                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2618                         XSTATE_FPSSE;
2619         }
2620 }
2621
2622 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2623                                         struct kvm_xsave *guest_xsave)
2624 {
2625         u64 xstate_bv =
2626                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2627
2628         if (cpu_has_xsave)
2629                 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2630                         guest_xsave->region, xstate_size);
2631         else {
2632                 if (xstate_bv & ~XSTATE_FPSSE)
2633                         return -EINVAL;
2634                 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2635                         guest_xsave->region, sizeof(struct i387_fxsave_struct));
2636         }
2637         return 0;
2638 }
2639
2640 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2641                                         struct kvm_xcrs *guest_xcrs)
2642 {
2643         if (!cpu_has_xsave) {
2644                 guest_xcrs->nr_xcrs = 0;
2645                 return;
2646         }
2647
2648         guest_xcrs->nr_xcrs = 1;
2649         guest_xcrs->flags = 0;
2650         guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2651         guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2652 }
2653
2654 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2655                                        struct kvm_xcrs *guest_xcrs)
2656 {
2657         int i, r = 0;
2658
2659         if (!cpu_has_xsave)
2660                 return -EINVAL;
2661
2662         if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2663                 return -EINVAL;
2664
2665         for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2666                 /* Only support XCR0 currently */
2667                 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2668                         r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2669                                 guest_xcrs->xcrs[0].value);
2670                         break;
2671                 }
2672         if (r)
2673                 r = -EINVAL;
2674         return r;
2675 }
2676
2677 long kvm_arch_vcpu_ioctl(struct file *filp,
2678                          unsigned int ioctl, unsigned long arg)
2679 {
2680         struct kvm_vcpu *vcpu = filp->private_data;
2681         void __user *argp = (void __user *)arg;
2682         int r;
2683         union {
2684                 struct kvm_lapic_state *lapic;
2685                 struct kvm_xsave *xsave;
2686                 struct kvm_xcrs *xcrs;
2687                 void *buffer;
2688         } u;
2689
2690         u.buffer = NULL;
2691         switch (ioctl) {
2692         case KVM_GET_LAPIC: {
2693                 r = -EINVAL;
2694                 if (!vcpu->arch.apic)
2695                         goto out;
2696                 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2697
2698                 r = -ENOMEM;
2699                 if (!u.lapic)
2700                         goto out;
2701                 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
2702                 if (r)
2703                         goto out;
2704                 r = -EFAULT;
2705                 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
2706                         goto out;
2707                 r = 0;
2708                 break;
2709         }
2710         case KVM_SET_LAPIC: {
2711                 r = -EINVAL;
2712                 if (!vcpu->arch.apic)
2713                         goto out;
2714                 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2715                 r = -ENOMEM;
2716                 if (!u.lapic)
2717                         goto out;
2718                 r = -EFAULT;
2719                 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
2720                         goto out;
2721                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
2722                 if (r)
2723                         goto out;
2724                 r = 0;
2725                 break;
2726         }
2727         case KVM_INTERRUPT: {
2728                 struct kvm_interrupt irq;
2729
2730                 r = -EFAULT;
2731                 if (copy_from_user(&irq, argp, sizeof irq))
2732                         goto out;
2733                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2734                 if (r)
2735                         goto out;
2736                 r = 0;
2737                 break;
2738         }
2739         case KVM_NMI: {
2740                 r = kvm_vcpu_ioctl_nmi(vcpu);
2741                 if (r)
2742                         goto out;
2743                 r = 0;
2744                 break;
2745         }
2746         case KVM_SET_CPUID: {
2747                 struct kvm_cpuid __user *cpuid_arg = argp;
2748                 struct kvm_cpuid cpuid;
2749
2750                 r = -EFAULT;
2751                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2752                         goto out;
2753                 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2754                 if (r)
2755                         goto out;
2756                 break;
2757         }
2758         case KVM_SET_CPUID2: {
2759                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2760                 struct kvm_cpuid2 cpuid;
2761
2762                 r = -EFAULT;
2763                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2764                         goto out;
2765                 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
2766                                               cpuid_arg->entries);
2767                 if (r)
2768                         goto out;
2769                 break;
2770         }
2771         case KVM_GET_CPUID2: {
2772                 struct kvm_cpuid2 __user *cpuid_arg = argp;
2773                 struct kvm_cpuid2 cpuid;
2774
2775                 r = -EFAULT;
2776                 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2777                         goto out;
2778                 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
2779                                               cpuid_arg->entries);
2780                 if (r)
2781                         goto out;
2782                 r = -EFAULT;
2783                 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2784                         goto out;
2785                 r = 0;
2786                 break;
2787         }
2788         case KVM_GET_MSRS:
2789                 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2790                 break;
2791         case KVM_SET_MSRS:
2792                 r = msr_io(vcpu, argp, do_set_msr, 0);
2793                 break;
2794         case KVM_TPR_ACCESS_REPORTING: {
2795                 struct kvm_tpr_access_ctl tac;
2796
2797                 r = -EFAULT;
2798                 if (copy_from_user(&tac, argp, sizeof tac))
2799                         goto out;
2800                 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2801                 if (r)
2802                         goto out;
2803                 r = -EFAULT;
2804                 if (copy_to_user(argp, &tac, sizeof tac))
2805                         goto out;
2806                 r = 0;
2807                 break;
2808         };
2809         case KVM_SET_VAPIC_ADDR: {
2810                 struct kvm_vapic_addr va;
2811
2812                 r = -EINVAL;
2813                 if (!irqchip_in_kernel(vcpu->kvm))
2814                         goto out;
2815                 r = -EFAULT;
2816                 if (copy_from_user(&va, argp, sizeof va))
2817                         goto out;
2818                 r = 0;
2819                 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2820                 break;
2821         }
2822         case KVM_X86_SETUP_MCE: {
2823                 u64 mcg_cap;
2824
2825                 r = -EFAULT;
2826                 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2827                         goto out;
2828                 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2829                 break;
2830         }
2831         case KVM_X86_SET_MCE: {
2832                 struct kvm_x86_mce mce;
2833
2834                 r = -EFAULT;
2835                 if (copy_from_user(&mce, argp, sizeof mce))
2836                         goto out;
2837                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2838                 break;
2839         }
2840         case KVM_GET_VCPU_EVENTS: {
2841                 struct kvm_vcpu_events events;
2842
2843                 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2844
2845                 r = -EFAULT;
2846                 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2847                         break;
2848                 r = 0;
2849                 break;
2850         }
2851         case KVM_SET_VCPU_EVENTS: {
2852                 struct kvm_vcpu_events events;
2853
2854                 r = -EFAULT;
2855                 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2856                         break;
2857
2858                 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2859                 break;
2860         }
2861         case KVM_GET_DEBUGREGS: {
2862                 struct kvm_debugregs dbgregs;
2863
2864                 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2865
2866                 r = -EFAULT;
2867                 if (copy_to_user(argp, &dbgregs,
2868                                  sizeof(struct kvm_debugregs)))
2869                         break;
2870                 r = 0;
2871                 break;
2872         }
2873         case KVM_SET_DEBUGREGS: {
2874                 struct kvm_debugregs dbgregs;
2875
2876                 r = -EFAULT;
2877                 if (copy_from_user(&dbgregs, argp,
2878                                    sizeof(struct kvm_debugregs)))
2879                         break;
2880
2881                 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2882                 break;
2883         }
2884         case KVM_GET_XSAVE: {
2885                 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2886                 r = -ENOMEM;
2887                 if (!u.xsave)
2888                         break;
2889
2890                 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2891
2892                 r = -EFAULT;
2893                 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2894                         break;
2895                 r = 0;
2896                 break;
2897         }
2898         case KVM_SET_XSAVE: {
2899                 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2900                 r = -ENOMEM;
2901                 if (!u.xsave)
2902                         break;
2903
2904                 r = -EFAULT;
2905                 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2906                         break;
2907
2908                 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2909                 break;
2910         }
2911         case KVM_GET_XCRS: {
2912                 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2913                 r = -ENOMEM;
2914                 if (!u.xcrs)
2915                         break;
2916
2917                 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2918
2919                 r = -EFAULT;
2920                 if (copy_to_user(argp, u.xcrs,
2921                                  sizeof(struct kvm_xcrs)))
2922                         break;
2923                 r = 0;
2924                 break;
2925         }
2926         case KVM_SET_XCRS: {
2927                 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2928                 r = -ENOMEM;
2929                 if (!u.xcrs)
2930                         break;
2931
2932                 r = -EFAULT;
2933                 if (copy_from_user(u.xcrs, argp,
2934                                    sizeof(struct kvm_xcrs)))
2935                         break;
2936
2937                 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2938                 break;
2939         }
2940         default:
2941                 r = -EINVAL;
2942         }
2943 out:
2944         kfree(u.buffer);
2945         return r;
2946 }
2947
2948 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2949 {
2950         int ret;
2951
2952         if (addr > (unsigned int)(-3 * PAGE_SIZE))
2953                 return -1;
2954         ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2955         return ret;
2956 }
2957
2958 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2959                                               u64 ident_addr)
2960 {
2961         kvm->arch.ept_identity_map_addr = ident_addr;
2962         return 0;
2963 }
2964
2965 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2966                                           u32 kvm_nr_mmu_pages)
2967 {
2968         if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2969                 return -EINVAL;
2970
2971         mutex_lock(&kvm->slots_lock);
2972         spin_lock(&kvm->mmu_lock);
2973
2974         kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
2975         kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
2976
2977         spin_unlock(&kvm->mmu_lock);
2978         mutex_unlock(&kvm->slots_lock);
2979         return 0;
2980 }
2981
2982 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2983 {
2984         return kvm->arch.n_max_mmu_pages;
2985 }
2986
2987 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2988 {
2989         int r;
2990
2991         r = 0;
2992         switch (chip->chip_id) {
2993         case KVM_IRQCHIP_PIC_MASTER:
2994                 memcpy(&chip->chip.pic,
2995                         &pic_irqchip(kvm)->pics[0],
2996                         sizeof(struct kvm_pic_state));
2997                 break;
2998         case KVM_IRQCHIP_PIC_SLAVE:
2999                 memcpy(&chip->chip.pic,
3000                         &pic_irqchip(kvm)->pics[1],
3001                         sizeof(struct kvm_pic_state));
3002                 break;
3003         case KVM_IRQCHIP_IOAPIC:
3004                 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3005                 break;
3006         default:
3007                 r = -EINVAL;
3008                 break;
3009         }
3010         return r;
3011 }
3012
3013 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3014 {
3015         int r;
3016
3017         r = 0;
3018         switch (chip->chip_id) {
3019         case KVM_IRQCHIP_PIC_MASTER:
3020                 spin_lock(&pic_irqchip(kvm)->lock);
3021                 memcpy(&pic_irqchip(kvm)->pics[0],
3022                         &chip->chip.pic,
3023                         sizeof(struct kvm_pic_state));
3024                 spin_unlock(&pic_irqchip(kvm)->lock);
3025                 break;
3026         case KVM_IRQCHIP_PIC_SLAVE:
3027                 spin_lock(&pic_irqchip(kvm)->lock);
3028                 memcpy(&pic_irqchip(kvm)->pics[1],
3029                         &chip->chip.pic,
3030                         sizeof(struct kvm_pic_state));
3031                 spin_unlock(&pic_irqchip(kvm)->lock);
3032                 break;
3033         case KVM_IRQCHIP_IOAPIC:
3034                 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3035                 break;
3036         default:
3037                 r = -EINVAL;
3038                 break;
3039         }
3040         kvm_pic_update_irq(pic_irqchip(kvm));
3041         return r;
3042 }
3043
3044 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3045 {
3046         int r = 0;
3047
3048         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3049         memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3050         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3051         return r;
3052 }
3053
3054 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3055 {
3056         int r = 0;
3057
3058         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3059         memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3060         kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3061         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3062         return r;
3063 }
3064
3065 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3066 {
3067         int r = 0;
3068
3069         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3070         memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3071                 sizeof(ps->channels));
3072         ps->flags = kvm->arch.vpit->pit_state.flags;
3073         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3074         return r;
3075 }
3076
3077 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3078 {
3079         int r = 0, start = 0;
3080         u32 prev_legacy, cur_legacy;
3081         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3082         prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3083         cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3084         if (!prev_legacy && cur_legacy)
3085                 start = 1;
3086         memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3087                sizeof(kvm->arch.vpit->pit_state.channels));
3088         kvm->arch.vpit->pit_state.flags = ps->flags;
3089         kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3090         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3091         return r;
3092 }
3093
3094 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3095                                  struct kvm_reinject_control *control)
3096 {
3097         if (!kvm->arch.vpit)
3098                 return -ENXIO;
3099         mutex_lock(&kvm->arch.vpit->pit_state.lock);
3100         kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
3101         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3102         return 0;
3103 }
3104
3105 /*
3106  * Get (and clear) the dirty memory log for a memory slot.
3107  */
3108 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3109                                       struct kvm_dirty_log *log)
3110 {
3111         int r, i;
3112         struct kvm_memory_slot *memslot;
3113         unsigned long n;
3114         unsigned long is_dirty = 0;
3115
3116         mutex_lock(&kvm->slots_lock);
3117
3118         r = -EINVAL;
3119         if (log->slot >= KVM_MEMORY_SLOTS)
3120                 goto out;
3121
3122         memslot = &kvm->memslots->memslots[log->slot];
3123         r = -ENOENT;
3124         if (!memslot->dirty_bitmap)
3125                 goto out;
3126
3127         n = kvm_dirty_bitmap_bytes(memslot);
3128
3129         for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3130                 is_dirty = memslot->dirty_bitmap[i];
3131
3132         /* If nothing is dirty, don't bother messing with page tables. */
3133         if (is_dirty) {
3134                 struct kvm_memslots *slots, *old_slots;
3135                 unsigned long *dirty_bitmap;
3136
3137                 spin_lock(&kvm->mmu_lock);
3138                 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3139                 spin_unlock(&kvm->mmu_lock);
3140
3141                 r = -ENOMEM;
3142                 dirty_bitmap = vmalloc(n);
3143                 if (!dirty_bitmap)
3144                         goto out;
3145                 memset(dirty_bitmap, 0, n);
3146
3147                 r = -ENOMEM;
3148                 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
3149                 if (!slots) {
3150                         vfree(dirty_bitmap);
3151                         goto out;
3152                 }
3153                 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3154                 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
3155
3156                 old_slots = kvm->memslots;
3157                 rcu_assign_pointer(kvm->memslots, slots);
3158                 synchronize_srcu_expedited(&kvm->srcu);
3159                 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3160                 kfree(old_slots);
3161
3162                 r = -EFAULT;
3163                 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
3164                         vfree(dirty_bitmap);
3165                         goto out;
3166                 }
3167                 vfree(dirty_bitmap);
3168         } else {
3169                 r = -EFAULT;
3170                 if (clear_user(log->dirty_bitmap, n))
3171                         goto out;
3172         }
3173
3174         r = 0;
3175 out:
3176         mutex_unlock(&kvm->slots_lock);
3177         return r;
3178 }
3179
3180 long kvm_arch_vm_ioctl(struct file *filp,
3181                        unsigned int ioctl, unsigned long arg)
3182 {
3183         struct kvm *kvm = filp->private_data;
3184         void __user *argp = (void __user *)arg;
3185         int r = -ENOTTY;
3186         /*
3187          * This union makes it completely explicit to gcc-3.x
3188          * that these two variables' stack usage should be
3189          * combined, not added together.
3190          */
3191         union {
3192                 struct kvm_pit_state ps;
3193                 struct kvm_pit_state2 ps2;
3194                 struct kvm_pit_config pit_config;
3195         } u;
3196
3197         switch (ioctl) {
3198         case KVM_SET_TSS_ADDR:
3199                 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3200                 if (r < 0)
3201                         goto out;
3202                 break;
3203         case KVM_SET_IDENTITY_MAP_ADDR: {
3204                 u64 ident_addr;
3205
3206                 r = -EFAULT;
3207                 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3208                         goto out;
3209                 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3210                 if (r < 0)
3211                         goto out;
3212                 break;
3213         }
3214         case KVM_SET_NR_MMU_PAGES:
3215                 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3216                 if (r)
3217                         goto out;
3218                 break;
3219         case KVM_GET_NR_MMU_PAGES:
3220                 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3221                 break;
3222         case KVM_CREATE_IRQCHIP: {
3223                 struct kvm_pic *vpic;
3224
3225                 mutex_lock(&kvm->lock);