2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
38 #include <asm/virtext.h>
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
47 MODULE_AUTHOR("Qumranet");
48 MODULE_LICENSE("GPL");
50 static int __read_mostly bypass_guest_pf = 1;
51 module_param(bypass_guest_pf, bool, S_IRUGO);
53 static int __read_mostly enable_vpid = 1;
54 module_param_named(vpid, enable_vpid, bool, 0444);
56 static int __read_mostly flexpriority_enabled = 1;
57 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
59 static int __read_mostly enable_ept = 1;
60 module_param_named(ept, enable_ept, bool, S_IRUGO);
62 static int __read_mostly enable_unrestricted_guest = 1;
63 module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
66 static int __read_mostly emulate_invalid_guest_state = 0;
67 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
69 static int __read_mostly vmm_exclusive = 1;
70 module_param(vmm_exclusive, bool, S_IRUGO);
72 static int __read_mostly yield_on_hlt = 1;
73 module_param(yield_on_hlt, bool, S_IRUGO);
75 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
76 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
77 #define KVM_GUEST_CR0_MASK \
78 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
79 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
80 (X86_CR0_WP | X86_CR0_NE)
81 #define KVM_VM_CR0_ALWAYS_ON \
82 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
83 #define KVM_CR4_GUEST_OWNED_BITS \
84 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
87 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
88 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
90 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
93 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
94 * ple_gap: upper bound on the amount of time between two successive
95 * executions of PAUSE in a loop. Also indicate if ple enabled.
96 * According to test, this time is usually small than 41 cycles.
97 * ple_window: upper bound on the amount of time a guest is allowed to execute
98 * in a PAUSE loop. Tests indicate that most spinlocks are held for
99 * less than 2^12 cycles
100 * Time is measured based on a counter that runs at the same rate as the TSC,
101 * refer SDM volume 3b section 21.6.13 & 22.1.3.
103 #define KVM_VMX_DEFAULT_PLE_GAP 41
104 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
105 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
106 module_param(ple_gap, int, S_IRUGO);
108 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
109 module_param(ple_window, int, S_IRUGO);
111 #define NR_AUTOLOAD_MSRS 1
119 struct shared_msr_entry {
126 struct kvm_vcpu vcpu;
127 struct list_head local_vcpus_link;
128 unsigned long host_rsp;
132 u32 idt_vectoring_info;
133 struct shared_msr_entry *guest_msrs;
137 u64 msr_host_kernel_gs_base;
138 u64 msr_guest_kernel_gs_base;
141 struct msr_autoload {
143 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
144 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
148 u16 fs_sel, gs_sel, ldt_sel;
149 int gs_ldt_reload_needed;
150 int fs_reload_needed;
155 struct kvm_save_segment {
160 } tr, es, ds, fs, gs;
163 bool emulation_required;
165 /* Support for vnmi-less CPUs */
166 int soft_vnmi_blocked;
168 s64 vnmi_blocked_time;
174 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
176 return container_of(vcpu, struct vcpu_vmx, vcpu);
179 static int init_rmode(struct kvm *kvm);
180 static u64 construct_eptp(unsigned long root_hpa);
181 static void kvm_cpu_vmxon(u64 addr);
182 static void kvm_cpu_vmxoff(void);
183 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
185 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
186 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
187 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
188 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
190 static unsigned long *vmx_io_bitmap_a;
191 static unsigned long *vmx_io_bitmap_b;
192 static unsigned long *vmx_msr_bitmap_legacy;
193 static unsigned long *vmx_msr_bitmap_longmode;
195 static bool cpu_has_load_ia32_efer;
197 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
198 static DEFINE_SPINLOCK(vmx_vpid_lock);
200 static struct vmcs_config {
204 u32 pin_based_exec_ctrl;
205 u32 cpu_based_exec_ctrl;
206 u32 cpu_based_2nd_exec_ctrl;
211 static struct vmx_capability {
216 #define VMX_SEGMENT_FIELD(seg) \
217 [VCPU_SREG_##seg] = { \
218 .selector = GUEST_##seg##_SELECTOR, \
219 .base = GUEST_##seg##_BASE, \
220 .limit = GUEST_##seg##_LIMIT, \
221 .ar_bytes = GUEST_##seg##_AR_BYTES, \
224 static struct kvm_vmx_segment_field {
229 } kvm_vmx_segment_fields[] = {
230 VMX_SEGMENT_FIELD(CS),
231 VMX_SEGMENT_FIELD(DS),
232 VMX_SEGMENT_FIELD(ES),
233 VMX_SEGMENT_FIELD(FS),
234 VMX_SEGMENT_FIELD(GS),
235 VMX_SEGMENT_FIELD(SS),
236 VMX_SEGMENT_FIELD(TR),
237 VMX_SEGMENT_FIELD(LDTR),
240 static u64 host_efer;
242 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
245 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
246 * away by decrementing the array size.
248 static const u32 vmx_msr_index[] = {
250 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
252 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
254 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
256 static inline bool is_page_fault(u32 intr_info)
258 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
259 INTR_INFO_VALID_MASK)) ==
260 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
263 static inline bool is_no_device(u32 intr_info)
265 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
266 INTR_INFO_VALID_MASK)) ==
267 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
270 static inline bool is_invalid_opcode(u32 intr_info)
272 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
273 INTR_INFO_VALID_MASK)) ==
274 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
277 static inline bool is_external_interrupt(u32 intr_info)
279 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
280 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
283 static inline bool is_machine_check(u32 intr_info)
285 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
286 INTR_INFO_VALID_MASK)) ==
287 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
290 static inline bool cpu_has_vmx_msr_bitmap(void)
292 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
295 static inline bool cpu_has_vmx_tpr_shadow(void)
297 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
300 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
302 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
305 static inline bool cpu_has_secondary_exec_ctrls(void)
307 return vmcs_config.cpu_based_exec_ctrl &
308 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
311 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
313 return vmcs_config.cpu_based_2nd_exec_ctrl &
314 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
317 static inline bool cpu_has_vmx_flexpriority(void)
319 return cpu_has_vmx_tpr_shadow() &&
320 cpu_has_vmx_virtualize_apic_accesses();
323 static inline bool cpu_has_vmx_ept_execute_only(void)
325 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
328 static inline bool cpu_has_vmx_eptp_uncacheable(void)
330 return vmx_capability.ept & VMX_EPTP_UC_BIT;
333 static inline bool cpu_has_vmx_eptp_writeback(void)
335 return vmx_capability.ept & VMX_EPTP_WB_BIT;
338 static inline bool cpu_has_vmx_ept_2m_page(void)
340 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
343 static inline bool cpu_has_vmx_ept_1g_page(void)
345 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
348 static inline bool cpu_has_vmx_ept_4levels(void)
350 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
353 static inline bool cpu_has_vmx_invept_individual_addr(void)
355 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
358 static inline bool cpu_has_vmx_invept_context(void)
360 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
363 static inline bool cpu_has_vmx_invept_global(void)
365 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
368 static inline bool cpu_has_vmx_invvpid_single(void)
370 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
373 static inline bool cpu_has_vmx_invvpid_global(void)
375 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
378 static inline bool cpu_has_vmx_ept(void)
380 return vmcs_config.cpu_based_2nd_exec_ctrl &
381 SECONDARY_EXEC_ENABLE_EPT;
384 static inline bool cpu_has_vmx_unrestricted_guest(void)
386 return vmcs_config.cpu_based_2nd_exec_ctrl &
387 SECONDARY_EXEC_UNRESTRICTED_GUEST;
390 static inline bool cpu_has_vmx_ple(void)
392 return vmcs_config.cpu_based_2nd_exec_ctrl &
393 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
396 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
398 return flexpriority_enabled && irqchip_in_kernel(kvm);
401 static inline bool cpu_has_vmx_vpid(void)
403 return vmcs_config.cpu_based_2nd_exec_ctrl &
404 SECONDARY_EXEC_ENABLE_VPID;
407 static inline bool cpu_has_vmx_rdtscp(void)
409 return vmcs_config.cpu_based_2nd_exec_ctrl &
410 SECONDARY_EXEC_RDTSCP;
413 static inline bool cpu_has_virtual_nmis(void)
415 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
418 static inline bool cpu_has_vmx_wbinvd_exit(void)
420 return vmcs_config.cpu_based_2nd_exec_ctrl &
421 SECONDARY_EXEC_WBINVD_EXITING;
424 static inline bool report_flexpriority(void)
426 return flexpriority_enabled;
429 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
433 for (i = 0; i < vmx->nmsrs; ++i)
434 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
439 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
445 } operand = { vpid, 0, gva };
447 asm volatile (__ex(ASM_VMX_INVVPID)
448 /* CF==1 or ZF==1 --> rc = -1 */
450 : : "a"(&operand), "c"(ext) : "cc", "memory");
453 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
457 } operand = {eptp, gpa};
459 asm volatile (__ex(ASM_VMX_INVEPT)
460 /* CF==1 or ZF==1 --> rc = -1 */
461 "; ja 1f ; ud2 ; 1:\n"
462 : : "a" (&operand), "c" (ext) : "cc", "memory");
465 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
469 i = __find_msr_index(vmx, msr);
471 return &vmx->guest_msrs[i];
475 static void vmcs_clear(struct vmcs *vmcs)
477 u64 phys_addr = __pa(vmcs);
480 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
481 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
484 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
488 static void vmcs_load(struct vmcs *vmcs)
490 u64 phys_addr = __pa(vmcs);
493 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
494 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
497 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
501 static void __vcpu_clear(void *arg)
503 struct vcpu_vmx *vmx = arg;
504 int cpu = raw_smp_processor_id();
506 if (vmx->vcpu.cpu == cpu)
507 vmcs_clear(vmx->vmcs);
508 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
509 per_cpu(current_vmcs, cpu) = NULL;
510 list_del(&vmx->local_vcpus_link);
515 static void vcpu_clear(struct vcpu_vmx *vmx)
517 if (vmx->vcpu.cpu == -1)
519 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
522 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
527 if (cpu_has_vmx_invvpid_single())
528 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
531 static inline void vpid_sync_vcpu_global(void)
533 if (cpu_has_vmx_invvpid_global())
534 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
537 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
539 if (cpu_has_vmx_invvpid_single())
540 vpid_sync_vcpu_single(vmx);
542 vpid_sync_vcpu_global();
545 static inline void ept_sync_global(void)
547 if (cpu_has_vmx_invept_global())
548 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
551 static inline void ept_sync_context(u64 eptp)
554 if (cpu_has_vmx_invept_context())
555 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
561 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
564 if (cpu_has_vmx_invept_individual_addr())
565 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
568 ept_sync_context(eptp);
572 static unsigned long vmcs_readl(unsigned long field)
574 unsigned long value = 0;
576 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
577 : "+a"(value) : "d"(field) : "cc");
581 static u16 vmcs_read16(unsigned long field)
583 return vmcs_readl(field);
586 static u32 vmcs_read32(unsigned long field)
588 return vmcs_readl(field);
591 static u64 vmcs_read64(unsigned long field)
594 return vmcs_readl(field);
596 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
600 static noinline void vmwrite_error(unsigned long field, unsigned long value)
602 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
603 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
607 static void vmcs_writel(unsigned long field, unsigned long value)
611 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
612 : "=q"(error) : "a"(value), "d"(field) : "cc");
614 vmwrite_error(field, value);
617 static void vmcs_write16(unsigned long field, u16 value)
619 vmcs_writel(field, value);
622 static void vmcs_write32(unsigned long field, u32 value)
624 vmcs_writel(field, value);
627 static void vmcs_write64(unsigned long field, u64 value)
629 vmcs_writel(field, value);
630 #ifndef CONFIG_X86_64
632 vmcs_writel(field+1, value >> 32);
636 static void vmcs_clear_bits(unsigned long field, u32 mask)
638 vmcs_writel(field, vmcs_readl(field) & ~mask);
641 static void vmcs_set_bits(unsigned long field, u32 mask)
643 vmcs_writel(field, vmcs_readl(field) | mask);
646 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
650 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
651 (1u << NM_VECTOR) | (1u << DB_VECTOR);
652 if ((vcpu->guest_debug &
653 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
654 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
655 eb |= 1u << BP_VECTOR;
656 if (to_vmx(vcpu)->rmode.vm86_active)
659 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
660 if (vcpu->fpu_active)
661 eb &= ~(1u << NM_VECTOR);
662 vmcs_write32(EXCEPTION_BITMAP, eb);
665 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
668 struct msr_autoload *m = &vmx->msr_autoload;
670 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
671 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
672 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
676 for (i = 0; i < m->nr; ++i)
677 if (m->guest[i].index == msr)
683 m->guest[i] = m->guest[m->nr];
684 m->host[i] = m->host[m->nr];
685 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
686 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
689 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
690 u64 guest_val, u64 host_val)
693 struct msr_autoload *m = &vmx->msr_autoload;
695 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
696 vmcs_write64(GUEST_IA32_EFER, guest_val);
697 vmcs_write64(HOST_IA32_EFER, host_val);
698 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
699 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
703 for (i = 0; i < m->nr; ++i)
704 if (m->guest[i].index == msr)
709 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
710 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
713 m->guest[i].index = msr;
714 m->guest[i].value = guest_val;
715 m->host[i].index = msr;
716 m->host[i].value = host_val;
719 static void reload_tss(void)
722 * VT restores TR but not its size. Useless.
724 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
725 struct desc_struct *descs;
727 descs = (void *)gdt->address;
728 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
732 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
737 guest_efer = vmx->vcpu.arch.efer;
740 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
743 ignore_bits = EFER_NX | EFER_SCE;
745 ignore_bits |= EFER_LMA | EFER_LME;
746 /* SCE is meaningful only in long mode on Intel */
747 if (guest_efer & EFER_LMA)
748 ignore_bits &= ~(u64)EFER_SCE;
750 guest_efer &= ~ignore_bits;
751 guest_efer |= host_efer & ignore_bits;
752 vmx->guest_msrs[efer_offset].data = guest_efer;
753 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
755 clear_atomic_switch_msr(vmx, MSR_EFER);
756 /* On ept, can't emulate nx, and must switch nx atomically */
757 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
758 guest_efer = vmx->vcpu.arch.efer;
759 if (!(guest_efer & EFER_LMA))
760 guest_efer &= ~EFER_LME;
761 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
768 static unsigned long segment_base(u16 selector)
770 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
771 struct desc_struct *d;
772 unsigned long table_base;
775 if (!(selector & ~3))
778 table_base = gdt->address;
780 if (selector & 4) { /* from ldt */
781 u16 ldt_selector = kvm_read_ldt();
783 if (!(ldt_selector & ~3))
786 table_base = segment_base(ldt_selector);
788 d = (struct desc_struct *)(table_base + (selector & ~7));
789 v = get_desc_base(d);
791 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
792 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
797 static inline unsigned long kvm_read_tr_base(void)
800 asm("str %0" : "=g"(tr));
801 return segment_base(tr);
804 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
806 struct vcpu_vmx *vmx = to_vmx(vcpu);
809 if (vmx->host_state.loaded)
812 vmx->host_state.loaded = 1;
814 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
815 * allow segment selectors with cpl > 0 or ti == 1.
817 vmx->host_state.ldt_sel = kvm_read_ldt();
818 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
819 savesegment(fs, vmx->host_state.fs_sel);
820 if (!(vmx->host_state.fs_sel & 7)) {
821 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
822 vmx->host_state.fs_reload_needed = 0;
824 vmcs_write16(HOST_FS_SELECTOR, 0);
825 vmx->host_state.fs_reload_needed = 1;
827 savesegment(gs, vmx->host_state.gs_sel);
828 if (!(vmx->host_state.gs_sel & 7))
829 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
831 vmcs_write16(HOST_GS_SELECTOR, 0);
832 vmx->host_state.gs_ldt_reload_needed = 1;
836 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
837 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
839 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
840 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
844 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
845 if (is_long_mode(&vmx->vcpu))
846 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
848 for (i = 0; i < vmx->save_nmsrs; ++i)
849 kvm_set_shared_msr(vmx->guest_msrs[i].index,
850 vmx->guest_msrs[i].data,
851 vmx->guest_msrs[i].mask);
854 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
856 if (!vmx->host_state.loaded)
859 ++vmx->vcpu.stat.host_state_reload;
860 vmx->host_state.loaded = 0;
862 if (is_long_mode(&vmx->vcpu))
863 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
865 if (vmx->host_state.gs_ldt_reload_needed) {
866 kvm_load_ldt(vmx->host_state.ldt_sel);
868 load_gs_index(vmx->host_state.gs_sel);
870 loadsegment(gs, vmx->host_state.gs_sel);
873 if (vmx->host_state.fs_reload_needed)
874 loadsegment(fs, vmx->host_state.fs_sel);
877 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
879 if (current_thread_info()->status & TS_USEDFPU)
881 load_gdt(&__get_cpu_var(host_gdt));
884 static void vmx_load_host_state(struct vcpu_vmx *vmx)
887 __vmx_load_host_state(vmx);
892 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
893 * vcpu mutex is already taken.
895 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
897 struct vcpu_vmx *vmx = to_vmx(vcpu);
898 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
901 kvm_cpu_vmxon(phys_addr);
902 else if (vcpu->cpu != cpu)
905 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
906 per_cpu(current_vmcs, cpu) = vmx->vmcs;
907 vmcs_load(vmx->vmcs);
910 if (vcpu->cpu != cpu) {
911 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
912 unsigned long sysenter_esp;
914 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
916 list_add(&vmx->local_vcpus_link,
917 &per_cpu(vcpus_on_cpu, cpu));
921 * Linux uses per-cpu TSS and GDT, so set these when switching
924 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
925 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
927 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
928 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
932 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
934 __vmx_load_host_state(to_vmx(vcpu));
935 if (!vmm_exclusive) {
936 __vcpu_clear(to_vmx(vcpu));
941 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
945 if (vcpu->fpu_active)
947 vcpu->fpu_active = 1;
948 cr0 = vmcs_readl(GUEST_CR0);
949 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
950 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
951 vmcs_writel(GUEST_CR0, cr0);
952 update_exception_bitmap(vcpu);
953 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
954 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
957 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
959 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
961 vmx_decache_cr0_guest_bits(vcpu);
962 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
963 update_exception_bitmap(vcpu);
964 vcpu->arch.cr0_guest_owned_bits = 0;
965 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
966 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
969 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
971 unsigned long rflags, save_rflags;
973 rflags = vmcs_readl(GUEST_RFLAGS);
974 if (to_vmx(vcpu)->rmode.vm86_active) {
975 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
976 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
977 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
982 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
984 if (to_vmx(vcpu)->rmode.vm86_active) {
985 to_vmx(vcpu)->rmode.save_rflags = rflags;
986 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
988 vmcs_writel(GUEST_RFLAGS, rflags);
991 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
993 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
996 if (interruptibility & GUEST_INTR_STATE_STI)
997 ret |= KVM_X86_SHADOW_INT_STI;
998 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
999 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1004 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1006 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1007 u32 interruptibility = interruptibility_old;
1009 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1011 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1012 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1013 else if (mask & KVM_X86_SHADOW_INT_STI)
1014 interruptibility |= GUEST_INTR_STATE_STI;
1016 if ((interruptibility != interruptibility_old))
1017 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1020 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1024 rip = kvm_rip_read(vcpu);
1025 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1026 kvm_rip_write(vcpu, rip);
1028 /* skipping an emulated instruction also counts */
1029 vmx_set_interrupt_shadow(vcpu, 0);
1032 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1034 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1035 * explicitly skip the instruction because if the HLT state is set, then
1036 * the instruction is already executing and RIP has already been
1038 if (!yield_on_hlt &&
1039 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1040 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1043 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1044 bool has_error_code, u32 error_code,
1047 struct vcpu_vmx *vmx = to_vmx(vcpu);
1048 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1050 if (has_error_code) {
1051 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1052 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1055 if (vmx->rmode.vm86_active) {
1056 if (kvm_inject_realmode_interrupt(vcpu, nr) != EMULATE_DONE)
1057 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1061 if (kvm_exception_is_soft(nr)) {
1062 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1063 vmx->vcpu.arch.event_exit_inst_len);
1064 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1066 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1068 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1069 vmx_clear_hlt(vcpu);
1072 static bool vmx_rdtscp_supported(void)
1074 return cpu_has_vmx_rdtscp();
1078 * Swap MSR entry in host/guest MSR entry array.
1080 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1082 struct shared_msr_entry tmp;
1084 tmp = vmx->guest_msrs[to];
1085 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1086 vmx->guest_msrs[from] = tmp;
1090 * Set up the vmcs to automatically save and restore system
1091 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1092 * mode, as fiddling with msrs is very expensive.
1094 static void setup_msrs(struct vcpu_vmx *vmx)
1096 int save_nmsrs, index;
1097 unsigned long *msr_bitmap;
1099 vmx_load_host_state(vmx);
1101 #ifdef CONFIG_X86_64
1102 if (is_long_mode(&vmx->vcpu)) {
1103 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1105 move_msr_up(vmx, index, save_nmsrs++);
1106 index = __find_msr_index(vmx, MSR_LSTAR);
1108 move_msr_up(vmx, index, save_nmsrs++);
1109 index = __find_msr_index(vmx, MSR_CSTAR);
1111 move_msr_up(vmx, index, save_nmsrs++);
1112 index = __find_msr_index(vmx, MSR_TSC_AUX);
1113 if (index >= 0 && vmx->rdtscp_enabled)
1114 move_msr_up(vmx, index, save_nmsrs++);
1116 * MSR_STAR is only needed on long mode guests, and only
1117 * if efer.sce is enabled.
1119 index = __find_msr_index(vmx, MSR_STAR);
1120 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1121 move_msr_up(vmx, index, save_nmsrs++);
1124 index = __find_msr_index(vmx, MSR_EFER);
1125 if (index >= 0 && update_transition_efer(vmx, index))
1126 move_msr_up(vmx, index, save_nmsrs++);
1128 vmx->save_nmsrs = save_nmsrs;
1130 if (cpu_has_vmx_msr_bitmap()) {
1131 if (is_long_mode(&vmx->vcpu))
1132 msr_bitmap = vmx_msr_bitmap_longmode;
1134 msr_bitmap = vmx_msr_bitmap_legacy;
1136 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1141 * reads and returns guest's timestamp counter "register"
1142 * guest_tsc = host_tsc + tsc_offset -- 21.3
1144 static u64 guest_read_tsc(void)
1146 u64 host_tsc, tsc_offset;
1149 tsc_offset = vmcs_read64(TSC_OFFSET);
1150 return host_tsc + tsc_offset;
1154 * writes 'offset' into guest's timestamp counter offset register
1156 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1158 vmcs_write64(TSC_OFFSET, offset);
1161 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1163 u64 offset = vmcs_read64(TSC_OFFSET);
1164 vmcs_write64(TSC_OFFSET, offset + adjustment);
1168 * Reads an msr value (of 'msr_index') into 'pdata'.
1169 * Returns 0 on success, non-0 otherwise.
1170 * Assumes vcpu_load() was already called.
1172 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1175 struct shared_msr_entry *msr;
1178 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1182 switch (msr_index) {
1183 #ifdef CONFIG_X86_64
1185 data = vmcs_readl(GUEST_FS_BASE);
1188 data = vmcs_readl(GUEST_GS_BASE);
1190 case MSR_KERNEL_GS_BASE:
1191 vmx_load_host_state(to_vmx(vcpu));
1192 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1196 return kvm_get_msr_common(vcpu, msr_index, pdata);
1198 data = guest_read_tsc();
1200 case MSR_IA32_SYSENTER_CS:
1201 data = vmcs_read32(GUEST_SYSENTER_CS);
1203 case MSR_IA32_SYSENTER_EIP:
1204 data = vmcs_readl(GUEST_SYSENTER_EIP);
1206 case MSR_IA32_SYSENTER_ESP:
1207 data = vmcs_readl(GUEST_SYSENTER_ESP);
1210 if (!to_vmx(vcpu)->rdtscp_enabled)
1212 /* Otherwise falls through */
1214 vmx_load_host_state(to_vmx(vcpu));
1215 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1217 vmx_load_host_state(to_vmx(vcpu));
1221 return kvm_get_msr_common(vcpu, msr_index, pdata);
1229 * Writes msr value into into the appropriate "register".
1230 * Returns 0 on success, non-0 otherwise.
1231 * Assumes vcpu_load() was already called.
1233 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1235 struct vcpu_vmx *vmx = to_vmx(vcpu);
1236 struct shared_msr_entry *msr;
1239 switch (msr_index) {
1241 vmx_load_host_state(vmx);
1242 ret = kvm_set_msr_common(vcpu, msr_index, data);
1244 #ifdef CONFIG_X86_64
1246 vmcs_writel(GUEST_FS_BASE, data);
1249 vmcs_writel(GUEST_GS_BASE, data);
1251 case MSR_KERNEL_GS_BASE:
1252 vmx_load_host_state(vmx);
1253 vmx->msr_guest_kernel_gs_base = data;
1256 case MSR_IA32_SYSENTER_CS:
1257 vmcs_write32(GUEST_SYSENTER_CS, data);
1259 case MSR_IA32_SYSENTER_EIP:
1260 vmcs_writel(GUEST_SYSENTER_EIP, data);
1262 case MSR_IA32_SYSENTER_ESP:
1263 vmcs_writel(GUEST_SYSENTER_ESP, data);
1266 kvm_write_tsc(vcpu, data);
1268 case MSR_IA32_CR_PAT:
1269 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1270 vmcs_write64(GUEST_IA32_PAT, data);
1271 vcpu->arch.pat = data;
1274 ret = kvm_set_msr_common(vcpu, msr_index, data);
1277 if (!vmx->rdtscp_enabled)
1279 /* Check reserved bit, higher 32 bits should be zero */
1280 if ((data >> 32) != 0)
1282 /* Otherwise falls through */
1284 msr = find_msr_entry(vmx, msr_index);
1286 vmx_load_host_state(vmx);
1290 ret = kvm_set_msr_common(vcpu, msr_index, data);
1296 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1298 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1301 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1304 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1306 case VCPU_EXREG_PDPTR:
1308 ept_save_pdptrs(vcpu);
1315 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1317 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1318 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1320 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1322 update_exception_bitmap(vcpu);
1325 static __init int cpu_has_kvm_support(void)
1327 return cpu_has_vmx();
1330 static __init int vmx_disabled_by_bios(void)
1334 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1335 if (msr & FEATURE_CONTROL_LOCKED) {
1336 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1339 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1340 && !tboot_enabled()) {
1341 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
1342 " activate TXT before enabling KVM\n");
1348 /* locked but not enabled */
1351 static void kvm_cpu_vmxon(u64 addr)
1353 asm volatile (ASM_VMX_VMXON_RAX
1354 : : "a"(&addr), "m"(addr)
1358 static int hardware_enable(void *garbage)
1360 int cpu = raw_smp_processor_id();
1361 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1364 if (read_cr4() & X86_CR4_VMXE)
1367 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1368 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1370 test_bits = FEATURE_CONTROL_LOCKED;
1371 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1372 if (tboot_enabled())
1373 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1375 if ((old & test_bits) != test_bits) {
1376 /* enable and lock */
1377 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1379 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1381 if (vmm_exclusive) {
1382 kvm_cpu_vmxon(phys_addr);
1386 store_gdt(&__get_cpu_var(host_gdt));
1391 static void vmclear_local_vcpus(void)
1393 int cpu = raw_smp_processor_id();
1394 struct vcpu_vmx *vmx, *n;
1396 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1402 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1405 static void kvm_cpu_vmxoff(void)
1407 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1410 static void hardware_disable(void *garbage)
1412 if (vmm_exclusive) {
1413 vmclear_local_vcpus();
1416 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1419 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1420 u32 msr, u32 *result)
1422 u32 vmx_msr_low, vmx_msr_high;
1423 u32 ctl = ctl_min | ctl_opt;
1425 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1427 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1428 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1430 /* Ensure minimum (required) set of control bits are supported. */
1438 static __init bool allow_1_setting(u32 msr, u32 ctl)
1440 u32 vmx_msr_low, vmx_msr_high;
1442 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1443 return vmx_msr_high & ctl;
1446 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1448 u32 vmx_msr_low, vmx_msr_high;
1449 u32 min, opt, min2, opt2;
1450 u32 _pin_based_exec_control = 0;
1451 u32 _cpu_based_exec_control = 0;
1452 u32 _cpu_based_2nd_exec_control = 0;
1453 u32 _vmexit_control = 0;
1454 u32 _vmentry_control = 0;
1456 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1457 opt = PIN_BASED_VIRTUAL_NMIS;
1458 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1459 &_pin_based_exec_control) < 0)
1463 #ifdef CONFIG_X86_64
1464 CPU_BASED_CR8_LOAD_EXITING |
1465 CPU_BASED_CR8_STORE_EXITING |
1467 CPU_BASED_CR3_LOAD_EXITING |
1468 CPU_BASED_CR3_STORE_EXITING |
1469 CPU_BASED_USE_IO_BITMAPS |
1470 CPU_BASED_MOV_DR_EXITING |
1471 CPU_BASED_USE_TSC_OFFSETING |
1472 CPU_BASED_MWAIT_EXITING |
1473 CPU_BASED_MONITOR_EXITING |
1474 CPU_BASED_INVLPG_EXITING;
1477 min |= CPU_BASED_HLT_EXITING;
1479 opt = CPU_BASED_TPR_SHADOW |
1480 CPU_BASED_USE_MSR_BITMAPS |
1481 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1482 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1483 &_cpu_based_exec_control) < 0)
1485 #ifdef CONFIG_X86_64
1486 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1487 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1488 ~CPU_BASED_CR8_STORE_EXITING;
1490 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1492 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1493 SECONDARY_EXEC_WBINVD_EXITING |
1494 SECONDARY_EXEC_ENABLE_VPID |
1495 SECONDARY_EXEC_ENABLE_EPT |
1496 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1497 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1498 SECONDARY_EXEC_RDTSCP;
1499 if (adjust_vmx_controls(min2, opt2,
1500 MSR_IA32_VMX_PROCBASED_CTLS2,
1501 &_cpu_based_2nd_exec_control) < 0)
1504 #ifndef CONFIG_X86_64
1505 if (!(_cpu_based_2nd_exec_control &
1506 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1507 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1509 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1510 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1512 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1513 CPU_BASED_CR3_STORE_EXITING |
1514 CPU_BASED_INVLPG_EXITING);
1515 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1516 vmx_capability.ept, vmx_capability.vpid);
1520 #ifdef CONFIG_X86_64
1521 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1523 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1524 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1525 &_vmexit_control) < 0)
1529 opt = VM_ENTRY_LOAD_IA32_PAT;
1530 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1531 &_vmentry_control) < 0)
1534 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1536 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1537 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1540 #ifdef CONFIG_X86_64
1541 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1542 if (vmx_msr_high & (1u<<16))
1546 /* Require Write-Back (WB) memory type for VMCS accesses. */
1547 if (((vmx_msr_high >> 18) & 15) != 6)
1550 vmcs_conf->size = vmx_msr_high & 0x1fff;
1551 vmcs_conf->order = get_order(vmcs_config.size);
1552 vmcs_conf->revision_id = vmx_msr_low;
1554 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1555 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1556 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1557 vmcs_conf->vmexit_ctrl = _vmexit_control;
1558 vmcs_conf->vmentry_ctrl = _vmentry_control;
1560 cpu_has_load_ia32_efer =
1561 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
1562 VM_ENTRY_LOAD_IA32_EFER)
1563 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
1564 VM_EXIT_LOAD_IA32_EFER);
1569 static struct vmcs *alloc_vmcs_cpu(int cpu)
1571 int node = cpu_to_node(cpu);
1575 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1578 vmcs = page_address(pages);
1579 memset(vmcs, 0, vmcs_config.size);
1580 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1584 static struct vmcs *alloc_vmcs(void)
1586 return alloc_vmcs_cpu(raw_smp_processor_id());
1589 static void free_vmcs(struct vmcs *vmcs)
1591 free_pages((unsigned long)vmcs, vmcs_config.order);
1594 static void free_kvm_area(void)
1598 for_each_possible_cpu(cpu) {
1599 free_vmcs(per_cpu(vmxarea, cpu));
1600 per_cpu(vmxarea, cpu) = NULL;
1604 static __init int alloc_kvm_area(void)
1608 for_each_possible_cpu(cpu) {
1611 vmcs = alloc_vmcs_cpu(cpu);
1617 per_cpu(vmxarea, cpu) = vmcs;
1622 static __init int hardware_setup(void)
1624 if (setup_vmcs_config(&vmcs_config) < 0)
1627 if (boot_cpu_has(X86_FEATURE_NX))
1628 kvm_enable_efer_bits(EFER_NX);
1630 if (!cpu_has_vmx_vpid())
1633 if (!cpu_has_vmx_ept() ||
1634 !cpu_has_vmx_ept_4levels()) {
1636 enable_unrestricted_guest = 0;
1639 if (!cpu_has_vmx_unrestricted_guest())
1640 enable_unrestricted_guest = 0;
1642 if (!cpu_has_vmx_flexpriority())
1643 flexpriority_enabled = 0;
1645 if (!cpu_has_vmx_tpr_shadow())
1646 kvm_x86_ops->update_cr8_intercept = NULL;
1648 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1649 kvm_disable_largepages();
1651 if (!cpu_has_vmx_ple())
1654 return alloc_kvm_area();
1657 static __exit void hardware_unsetup(void)
1662 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1664 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1666 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1667 vmcs_write16(sf->selector, save->selector);
1668 vmcs_writel(sf->base, save->base);
1669 vmcs_write32(sf->limit, save->limit);
1670 vmcs_write32(sf->ar_bytes, save->ar);
1672 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1674 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1678 static void enter_pmode(struct kvm_vcpu *vcpu)
1680 unsigned long flags;
1681 struct vcpu_vmx *vmx = to_vmx(vcpu);
1683 vmx->emulation_required = 1;
1684 vmx->rmode.vm86_active = 0;
1686 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
1687 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1688 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1689 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1691 flags = vmcs_readl(GUEST_RFLAGS);
1692 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1693 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1694 vmcs_writel(GUEST_RFLAGS, flags);
1696 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1697 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1699 update_exception_bitmap(vcpu);
1701 if (emulate_invalid_guest_state)
1704 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1705 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1706 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1707 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1709 vmcs_write16(GUEST_SS_SELECTOR, 0);
1710 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1712 vmcs_write16(GUEST_CS_SELECTOR,
1713 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1714 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1717 static gva_t rmode_tss_base(struct kvm *kvm)
1719 if (!kvm->arch.tss_addr) {
1720 struct kvm_memslots *slots;
1723 slots = kvm_memslots(kvm);
1724 base_gfn = slots->memslots[0].base_gfn +
1725 kvm->memslots->memslots[0].npages - 3;
1726 return base_gfn << PAGE_SHIFT;
1728 return kvm->arch.tss_addr;
1731 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1733 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1735 save->selector = vmcs_read16(sf->selector);
1736 save->base = vmcs_readl(sf->base);
1737 save->limit = vmcs_read32(sf->limit);
1738 save->ar = vmcs_read32(sf->ar_bytes);
1739 vmcs_write16(sf->selector, save->base >> 4);
1740 vmcs_write32(sf->base, save->base & 0xffff0);
1741 vmcs_write32(sf->limit, 0xffff);
1742 vmcs_write32(sf->ar_bytes, 0xf3);
1743 if (save->base & 0xf)
1744 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
1745 " aligned when entering protected mode (seg=%d)",
1749 static void enter_rmode(struct kvm_vcpu *vcpu)
1751 unsigned long flags;
1752 struct vcpu_vmx *vmx = to_vmx(vcpu);
1754 if (enable_unrestricted_guest)
1757 vmx->emulation_required = 1;
1758 vmx->rmode.vm86_active = 1;
1760 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
1761 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1762 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1764 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1765 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1767 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1768 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1770 flags = vmcs_readl(GUEST_RFLAGS);
1771 vmx->rmode.save_rflags = flags;
1773 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1775 vmcs_writel(GUEST_RFLAGS, flags);
1776 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1777 update_exception_bitmap(vcpu);
1779 if (emulate_invalid_guest_state)
1780 goto continue_rmode;
1782 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1783 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1784 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1786 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1787 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1788 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1789 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1790 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1792 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1793 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1794 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1795 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1798 kvm_mmu_reset_context(vcpu);
1799 init_rmode(vcpu->kvm);
1802 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1804 struct vcpu_vmx *vmx = to_vmx(vcpu);
1805 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1811 * Force kernel_gs_base reloading before EFER changes, as control
1812 * of this msr depends on is_long_mode().
1814 vmx_load_host_state(to_vmx(vcpu));
1815 vcpu->arch.efer = efer;
1816 if (efer & EFER_LMA) {
1817 vmcs_write32(VM_ENTRY_CONTROLS,
1818 vmcs_read32(VM_ENTRY_CONTROLS) |
1819 VM_ENTRY_IA32E_MODE);
1822 vmcs_write32(VM_ENTRY_CONTROLS,
1823 vmcs_read32(VM_ENTRY_CONTROLS) &
1824 ~VM_ENTRY_IA32E_MODE);
1826 msr->data = efer & ~EFER_LME;
1831 #ifdef CONFIG_X86_64
1833 static void enter_lmode(struct kvm_vcpu *vcpu)
1837 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1838 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1839 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1841 vmcs_write32(GUEST_TR_AR_BYTES,
1842 (guest_tr_ar & ~AR_TYPE_MASK)
1843 | AR_TYPE_BUSY_64_TSS);
1845 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
1848 static void exit_lmode(struct kvm_vcpu *vcpu)
1850 vmcs_write32(VM_ENTRY_CONTROLS,
1851 vmcs_read32(VM_ENTRY_CONTROLS)
1852 & ~VM_ENTRY_IA32E_MODE);
1853 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
1858 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1860 vpid_sync_context(to_vmx(vcpu));
1862 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1864 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1868 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1870 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1872 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1873 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1876 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
1878 if (enable_ept && is_paging(vcpu))
1879 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1880 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
1883 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1885 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1887 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1888 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1891 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1893 if (!test_bit(VCPU_EXREG_PDPTR,
1894 (unsigned long *)&vcpu->arch.regs_dirty))
1897 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1898 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
1899 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
1900 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
1901 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1905 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1907 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1908 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1909 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1910 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1911 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1914 __set_bit(VCPU_EXREG_PDPTR,
1915 (unsigned long *)&vcpu->arch.regs_avail);
1916 __set_bit(VCPU_EXREG_PDPTR,
1917 (unsigned long *)&vcpu->arch.regs_dirty);
1920 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1922 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1924 struct kvm_vcpu *vcpu)
1926 vmx_decache_cr3(vcpu);
1927 if (!(cr0 & X86_CR0_PG)) {
1928 /* From paging/starting to nonpaging */
1929 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1930 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1931 (CPU_BASED_CR3_LOAD_EXITING |
1932 CPU_BASED_CR3_STORE_EXITING));
1933 vcpu->arch.cr0 = cr0;
1934 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1935 } else if (!is_paging(vcpu)) {
1936 /* From nonpaging to paging */
1937 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1938 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1939 ~(CPU_BASED_CR3_LOAD_EXITING |
1940 CPU_BASED_CR3_STORE_EXITING));
1941 vcpu->arch.cr0 = cr0;
1942 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1945 if (!(cr0 & X86_CR0_WP))
1946 *hw_cr0 &= ~X86_CR0_WP;
1949 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1951 struct vcpu_vmx *vmx = to_vmx(vcpu);
1952 unsigned long hw_cr0;
1954 if (enable_unrestricted_guest)
1955 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1956 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1958 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1960 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1963 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1966 #ifdef CONFIG_X86_64
1967 if (vcpu->arch.efer & EFER_LME) {
1968 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1970 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1976 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1978 if (!vcpu->fpu_active)
1979 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1981 vmcs_writel(CR0_READ_SHADOW, cr0);
1982 vmcs_writel(GUEST_CR0, hw_cr0);
1983 vcpu->arch.cr0 = cr0;
1986 static u64 construct_eptp(unsigned long root_hpa)
1990 /* TODO write the value reading from MSR */
1991 eptp = VMX_EPT_DEFAULT_MT |
1992 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1993 eptp |= (root_hpa & PAGE_MASK);
1998 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2000 unsigned long guest_cr3;
2005 eptp = construct_eptp(cr3);
2006 vmcs_write64(EPT_POINTER, eptp);
2007 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
2008 vcpu->kvm->arch.ept_identity_map_addr;
2009 ept_load_pdptrs(vcpu);
2012 vmx_flush_tlb(vcpu);
2013 vmcs_writel(GUEST_CR3, guest_cr3);
2016 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2018 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
2019 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2021 vcpu->arch.cr4 = cr4;
2023 if (!is_paging(vcpu)) {
2024 hw_cr4 &= ~X86_CR4_PAE;
2025 hw_cr4 |= X86_CR4_PSE;
2026 } else if (!(cr4 & X86_CR4_PAE)) {
2027 hw_cr4 &= ~X86_CR4_PAE;
2031 vmcs_writel(CR4_READ_SHADOW, cr4);
2032 vmcs_writel(GUEST_CR4, hw_cr4);
2035 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2037 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2039 return vmcs_readl(sf->base);
2042 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2043 struct kvm_segment *var, int seg)
2045 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2048 var->base = vmcs_readl(sf->base);
2049 var->limit = vmcs_read32(sf->limit);
2050 var->selector = vmcs_read16(sf->selector);
2051 ar = vmcs_read32(sf->ar_bytes);
2052 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2054 var->type = ar & 15;
2055 var->s = (ar >> 4) & 1;
2056 var->dpl = (ar >> 5) & 3;
2057 var->present = (ar >> 7) & 1;
2058 var->avl = (ar >> 12) & 1;
2059 var->l = (ar >> 13) & 1;
2060 var->db = (ar >> 14) & 1;
2061 var->g = (ar >> 15) & 1;
2062 var->unusable = (ar >> 16) & 1;
2065 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2067 if (!is_protmode(vcpu))
2070 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2073 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2076 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2083 ar = var->type & 15;
2084 ar |= (var->s & 1) << 4;
2085 ar |= (var->dpl & 3) << 5;
2086 ar |= (var->present & 1) << 7;
2087 ar |= (var->avl & 1) << 12;
2088 ar |= (var->l & 1) << 13;
2089 ar |= (var->db & 1) << 14;
2090 ar |= (var->g & 1) << 15;
2092 if (ar == 0) /* a 0 value means unusable */
2093 ar = AR_UNUSABLE_MASK;
2098 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2099 struct kvm_segment *var, int seg)
2101 struct vcpu_vmx *vmx = to_vmx(vcpu);
2102 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2105 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2106 vmx->rmode.tr.selector = var->selector;
2107 vmx->rmode.tr.base = var->base;
2108 vmx->rmode.tr.limit = var->limit;
2109 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2112 vmcs_writel(sf->base, var->base);
2113 vmcs_write32(sf->limit, var->limit);
2114 vmcs_write16(sf->selector, var->selector);
2115 if (vmx->rmode.vm86_active && var->s) {
2117 * Hack real-mode segments into vm86 compatibility.
2119 if (var->base == 0xffff0000 && var->selector == 0xf000)
2120 vmcs_writel(sf->base, 0xf0000);
2123 ar = vmx_segment_access_rights(var);
2126 * Fix the "Accessed" bit in AR field of segment registers for older
2128 * IA32 arch specifies that at the time of processor reset the
2129 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2130 * is setting it to 0 in the usedland code. This causes invalid guest
2131 * state vmexit when "unrestricted guest" mode is turned on.
2132 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2133 * tree. Newer qemu binaries with that qemu fix would not need this
2136 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2137 ar |= 0x1; /* Accessed */
2139 vmcs_write32(sf->ar_bytes, ar);
2142 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2144 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2146 *db = (ar >> 14) & 1;
2147 *l = (ar >> 13) & 1;
2150 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2152 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2153 dt->address = vmcs_readl(GUEST_IDTR_BASE);
2156 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2158 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2159 vmcs_writel(GUEST_IDTR_BASE, dt->address);
2162 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2164 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2165 dt->address = vmcs_readl(GUEST_GDTR_BASE);
2168 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2170 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2171 vmcs_writel(GUEST_GDTR_BASE, dt->address);
2174 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2176 struct kvm_segment var;
2179 vmx_get_segment(vcpu, &var, seg);
2180 ar = vmx_segment_access_rights(&var);
2182 if (var.base != (var.selector << 4))
2184 if (var.limit != 0xffff)
2192 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2194 struct kvm_segment cs;
2195 unsigned int cs_rpl;
2197 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2198 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2202 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2206 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2207 if (cs.dpl > cs_rpl)
2210 if (cs.dpl != cs_rpl)
2216 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2220 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2222 struct kvm_segment ss;
2223 unsigned int ss_rpl;
2225 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2226 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2230 if (ss.type != 3 && ss.type != 7)
2234 if (ss.dpl != ss_rpl) /* DPL != RPL */
2242 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2244 struct kvm_segment var;
2247 vmx_get_segment(vcpu, &var, seg);
2248 rpl = var.selector & SELECTOR_RPL_MASK;
2256 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2257 if (var.dpl < rpl) /* DPL < RPL */
2261 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2267 static bool tr_valid(struct kvm_vcpu *vcpu)
2269 struct kvm_segment tr;
2271 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2275 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2277 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2285 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2287 struct kvm_segment ldtr;
2289 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2293 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2303 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2305 struct kvm_segment cs, ss;
2307 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2308 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2310 return ((cs.selector & SELECTOR_RPL_MASK) ==
2311 (ss.selector & SELECTOR_RPL_MASK));
2315 * Check if guest state is valid. Returns true if valid, false if
2317 * We assume that registers are always usable
2319 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2321 /* real mode guest state checks */
2322 if (!is_protmode(vcpu)) {
2323 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2325 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2327 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2329 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2331 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2333 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2336 /* protected mode guest state checks */
2337 if (!cs_ss_rpl_check(vcpu))
2339 if (!code_segment_valid(vcpu))
2341 if (!stack_segment_valid(vcpu))
2343 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2345 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2347 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2349 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2351 if (!tr_valid(vcpu))
2353 if (!ldtr_valid(vcpu))
2357 * - Add checks on RIP
2358 * - Add checks on RFLAGS
2364 static int init_rmode_tss(struct kvm *kvm)
2366 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2371 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2374 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2375 r = kvm_write_guest_page(kvm, fn++, &data,
2376 TSS_IOPB_BASE_OFFSET, sizeof(u16));
2379 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2382 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2386 r = kvm_write_guest_page(kvm, fn, &data,
2387 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2397 static int init_rmode_identity_map(struct kvm *kvm)
2400 pfn_t identity_map_pfn;
2405 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2406 printk(KERN_ERR "EPT: identity-mapping pagetable "
2407 "haven't been allocated!\n");
2410 if (likely(kvm->arch.ept_identity_pagetable_done))
2413 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2414 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2417 /* Set up identity-mapping pagetable for EPT in real mode */
2418 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2419 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2420 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2421 r = kvm_write_guest_page(kvm, identity_map_pfn,
2422 &tmp, i * sizeof(tmp), sizeof(tmp));
2426 kvm->arch.ept_identity_pagetable_done = true;
2432 static void seg_setup(int seg)
2434 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2437 vmcs_write16(sf->selector, 0);
2438 vmcs_writel(sf->base, 0);
2439 vmcs_write32(sf->limit, 0xffff);
2440 if (enable_unrestricted_guest) {
2442 if (seg == VCPU_SREG_CS)
2443 ar |= 0x08; /* code segment */
2447 vmcs_write32(sf->ar_bytes, ar);
2450 static int alloc_apic_access_page(struct kvm *kvm)
2452 struct kvm_userspace_memory_region kvm_userspace_mem;
2455 mutex_lock(&kvm->slots_lock);
2456 if (kvm->arch.apic_access_page)
2458 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2459 kvm_userspace_mem.flags = 0;
2460 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2461 kvm_userspace_mem.memory_size = PAGE_SIZE;
2462 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2466 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2468 mutex_unlock(&kvm->slots_lock);
2472 static int alloc_identity_pagetable(struct kvm *kvm)
2474 struct kvm_userspace_memory_region kvm_userspace_mem;
2477 mutex_lock(&kvm->slots_lock);
2478 if (kvm->arch.ept_identity_pagetable)
2480 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2481 kvm_userspace_mem.flags = 0;
2482 kvm_userspace_mem.guest_phys_addr =
2483 kvm->arch.ept_identity_map_addr;
2484 kvm_userspace_mem.memory_size = PAGE_SIZE;
2485 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2489 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2490 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2492 mutex_unlock(&kvm->slots_lock);
2496 static void allocate_vpid(struct vcpu_vmx *vmx)
2503 spin_lock(&vmx_vpid_lock);
2504 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2505 if (vpid < VMX_NR_VPIDS) {
2507 __set_bit(vpid, vmx_vpid_bitmap);
2509 spin_unlock(&vmx_vpid_lock);
2512 static void free_vpid(struct vcpu_vmx *vmx)
2516 spin_lock(&vmx_vpid_lock);
2518 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2519 spin_unlock(&vmx_vpid_lock);
2522 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2524 int f = sizeof(unsigned long);
2526 if (!cpu_has_vmx_msr_bitmap())
2530 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2531 * have the write-low and read-high bitmap offsets the wrong way round.
2532 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2534 if (msr <= 0x1fff) {
2535 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2536 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2537 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2539 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2540 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2544 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2547 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2548 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2552 * Sets up the vmcs for emulated real mode.
2554 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2556 u32 host_sysenter_cs, msr_low, msr_high;
2562 unsigned long kvm_vmx_return;
2566 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2567 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2569 if (cpu_has_vmx_msr_bitmap())
2570 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2572 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2575 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2576 vmcs_config.pin_based_exec_ctrl);
2578 exec_control = vmcs_config.cpu_based_exec_ctrl;
2579 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2580 exec_control &= ~CPU_BASED_TPR_SHADOW;
2581 #ifdef CONFIG_X86_64
2582 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2583 CPU_BASED_CR8_LOAD_EXITING;
2587 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2588 CPU_BASED_CR3_LOAD_EXITING |
2589 CPU_BASED_INVLPG_EXITING;
2590 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2592 if (cpu_has_secondary_exec_ctrls()) {
2593 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2594 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2596 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2598 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2600 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2601 enable_unrestricted_guest = 0;
2603 if (!enable_unrestricted_guest)
2604 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2606 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2607 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2611 vmcs_write32(PLE_GAP, ple_gap);
2612 vmcs_write32(PLE_WINDOW, ple_window);
2615 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2616 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2617 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2619 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
2620 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2621 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2623 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2624 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2625 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2626 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
2627 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
2628 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2629 #ifdef CONFIG_X86_64
2630 rdmsrl(MSR_FS_BASE, a);
2631 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2632 rdmsrl(MSR_GS_BASE, a);
2633 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2635 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2636 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2639 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2641 native_store_idt(&dt);
2642 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
2644 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2645 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2646 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2647 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2648 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2649 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2650 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2652 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2653 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2654 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2655 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2656 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2657 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2659 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2660 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2661 host_pat = msr_low | ((u64) msr_high << 32);
2662 vmcs_write64(HOST_IA32_PAT, host_pat);
2664 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2665 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2666 host_pat = msr_low | ((u64) msr_high << 32);
2667 /* Write the default value follow host pat */
2668 vmcs_write64(GUEST_IA32_PAT, host_pat);
2669 /* Keep arch.pat sync with GUEST_IA32_PAT */
2670 vmx->vcpu.arch.pat = host_pat;
2673 for (i = 0; i < NR_VMX_MSR; ++i) {
2674 u32 index = vmx_msr_index[i];
2675 u32 data_low, data_high;
2678 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2680 if (wrmsr_safe(index, data_low, data_high) < 0)
2682 vmx->guest_msrs[j].index = i;
2683 vmx->guest_msrs[j].data = 0;
2684 vmx->guest_msrs[j].mask = -1ull;
2688 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2690 /* 22.2.1, 20.8.1 */
2691 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2693 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2694 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2696 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2697 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2699 kvm_write_tsc(&vmx->vcpu, 0);
2704 static int init_rmode(struct kvm *kvm)
2708 idx = srcu_read_lock(&kvm->srcu);
2709 if (!init_rmode_tss(kvm))
2711 if (!init_rmode_identity_map(kvm))
2716 srcu_read_unlock(&kvm->srcu, idx);
2720 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2722 struct vcpu_vmx *vmx = to_vmx(vcpu);
2726 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2727 if (!init_rmode(vmx->vcpu.kvm)) {
2732 vmx->rmode.vm86_active = 0;
2734 vmx->soft_vnmi_blocked = 0;
2736 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2737 kvm_set_cr8(&vmx->vcpu, 0);
2738 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2739 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2740 msr |= MSR_IA32_APICBASE_BSP;
2741 kvm_set_apic_base(&vmx->vcpu, msr);
2743 ret = fx_init(&vmx->vcpu);
2747 seg_setup(VCPU_SREG_CS);
2749 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2750 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2752 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2753 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2754 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2756 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2757 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2760 seg_setup(VCPU_SREG_DS);
2761 seg_setup(VCPU_SREG_ES);
2762 seg_setup(VCPU_SREG_FS);
2763 seg_setup(VCPU_SREG_GS);
2764 seg_setup(VCPU_SREG_SS);
2766 vmcs_write16(GUEST_TR_SELECTOR, 0);
2767 vmcs_writel(GUEST_TR_BASE, 0);
2768 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2769 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2771 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2772 vmcs_writel(GUEST_LDTR_BASE, 0);
2773 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2774 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2776 vmcs_write32(GUEST_SYSENTER_CS, 0);
2777 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2778 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2780 vmcs_writel(GUEST_RFLAGS, 0x02);
2781 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2782 kvm_rip_write(vcpu, 0xfff0);
2784 kvm_rip_write(vcpu, 0);
2785 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2787 vmcs_writel(GUEST_DR7, 0x400);
2789 vmcs_writel(GUEST_GDTR_BASE, 0);
2790 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2792 vmcs_writel(GUEST_IDTR_BASE, 0);
2793 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2795 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
2796 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2797 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2799 /* Special registers */
2800 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2804 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2806 if (cpu_has_vmx_tpr_shadow()) {
2807 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2808 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2809 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2810 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2811 vmcs_write32(TPR_THRESHOLD, 0);
2814 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2815 vmcs_write64(APIC_ACCESS_ADDR,
2816 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2819 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2821 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2822 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2823 vmx_set_cr4(&vmx->vcpu, 0);
2824 vmx_set_efer(&vmx->vcpu, 0);
2825 vmx_fpu_activate(&vmx->vcpu);
2826 update_exception_bitmap(&vmx->vcpu);
2828 vpid_sync_context(vmx);
2832 /* HACK: Don't enable emulation on guest boot/reset */
2833 vmx->emulation_required = 0;
2839 static void enable_irq_window(struct kvm_vcpu *vcpu)
2841 u32 cpu_based_vm_exec_control;
2843 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2844 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2845 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2848 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2850 u32 cpu_based_vm_exec_control;
2852 if (!cpu_has_virtual_nmis()) {
2853 enable_irq_window(vcpu);
2857 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
2858 enable_irq_window(vcpu);
2861 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2862 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2863 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2866 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2868 struct vcpu_vmx *vmx = to_vmx(vcpu);
2870 int irq = vcpu->arch.interrupt.nr;
2872 trace_kvm_inj_virq(irq);
2874 ++vcpu->stat.irq_injections;
2875 if (vmx->rmode.vm86_active) {
2876 if (kvm_inject_realmode_interrupt(vcpu, irq) != EMULATE_DONE)
2877 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2880 intr = irq | INTR_INFO_VALID_MASK;
2881 if (vcpu->arch.interrupt.soft) {
2882 intr |= INTR_TYPE_SOFT_INTR;
2883 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2884 vmx->vcpu.arch.event_exit_inst_len);
2886 intr |= INTR_TYPE_EXT_INTR;
2887 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2888 vmx_clear_hlt(vcpu);
2891 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2893 struct vcpu_vmx *vmx = to_vmx(vcpu);
2895 if (!cpu_has_virtual_nmis()) {
2897 * Tracking the NMI-blocked state in software is built upon
2898 * finding the next open IRQ window. This, in turn, depends on
2899 * well-behaving guests: They have to keep IRQs disabled at
2900 * least as long as the NMI handler runs. Otherwise we may
2901 * cause NMI nesting, maybe breaking the guest. But as this is
2902 * highly unlikely, we can live with the residual risk.
2904 vmx->soft_vnmi_blocked = 1;
2905 vmx->vnmi_blocked_time = 0;
2908 ++vcpu->stat.nmi_injections;
2909 if (vmx->rmode.vm86_active) {
2910 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR) != EMULATE_DONE)
2911 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2914 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2915 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2916 vmx_clear_hlt(vcpu);
2919 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2921 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2924 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2925 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
2926 | GUEST_INTR_STATE_NMI));
2929 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2931 if (!cpu_has_virtual_nmis())
2932 return to_vmx(vcpu)->soft_vnmi_blocked;
2933 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
2936 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2938 struct vcpu_vmx *vmx = to_vmx(vcpu);
2940 if (!cpu_has_virtual_nmis()) {
2941 if (vmx->soft_vnmi_blocked != masked) {
2942 vmx->soft_vnmi_blocked = masked;
2943 vmx->vnmi_blocked_time = 0;
2947 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2948 GUEST_INTR_STATE_NMI);
2950 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2951 GUEST_INTR_STATE_NMI);
2955 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2957 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2958 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2959 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2962 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2965 struct kvm_userspace_memory_region tss_mem = {
2966 .slot = TSS_PRIVATE_MEMSLOT,
2967 .guest_phys_addr = addr,
2968 .memory_size = PAGE_SIZE * 3,
2972 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2975 kvm->arch.tss_addr = addr;
2979 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2980 int vec, u32 err_code)
2983 * Instruction with address size override prefix opcode 0x67
2984 * Cause the #SS fault with 0 error code in VM86 mode.
2986 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2987 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
2990 * Forward all other exceptions that are valid in real mode.
2991 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2992 * the required debugging infrastructure rework.
2996 if (vcpu->guest_debug &
2997 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2999 kvm_queue_exception(vcpu, vec);
3003 * Update instruction length as we may reinject the exception
3004 * from user space while in guest debugging mode.
3006 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3007 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3008 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3019 kvm_queue_exception(vcpu, vec);
3026 * Trigger machine check on the host. We assume all the MSRs are already set up
3027 * by the CPU and that we still run on the same CPU as the MCE occurred on.
3028 * We pass a fake environment to the machine check handler because we want
3029 * the guest to be always treated like user space, no matter what context
3030 * it used internally.
3032 static void kvm_machine_check(void)
3034 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3035 struct pt_regs regs = {
3036 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3037 .flags = X86_EFLAGS_IF,
3040 do_machine_check(®s, 0);
3044 static int handle_machine_check(struct kvm_vcpu *vcpu)
3046 /* already handled by vcpu_run */
3050 static int handle_exception(struct kvm_vcpu *vcpu)
3052 struct vcpu_vmx *vmx = to_vmx(vcpu);
3053 struct kvm_run *kvm_run = vcpu->run;
3054 u32 intr_info, ex_no, error_code;
3055 unsigned long cr2, rip, dr6;
3057 enum emulation_result er;
3059 vect_info = vmx->idt_vectoring_info;
3060 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3062 if (is_machine_check(intr_info))
3063 return handle_machine_check(vcpu);
3065 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3066 !is_page_fault(intr_info)) {
3067 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3068 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3069 vcpu->run->internal.ndata = 2;
3070 vcpu->run->internal.data[0] = vect_info;
3071 vcpu->run->internal.data[1] = intr_info;
3075 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3076 return 1; /* already handled by vmx_vcpu_run() */
3078 if (is_no_device(intr_info)) {
3079 vmx_fpu_activate(vcpu);
3083 if (is_invalid_opcode(intr_info)) {
3084 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
3085 if (er != EMULATE_DONE)
3086 kvm_queue_exception(vcpu, UD_VECTOR);
3091 rip = kvm_rip_read(vcpu);
3092 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3093 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3094 if (is_page_fault(intr_info)) {
3095 /* EPT won't cause page fault directly */
3098 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3099 trace_kvm_page_fault(cr2, error_code);
3101 if (kvm_event_needs_reinjection(vcpu))
3102 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3103 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
3106 if (vmx->rmode.vm86_active &&
3107 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3109 if (vcpu->arch.halt_request) {
3110 vcpu->arch.halt_request = 0;
3111 return kvm_emulate_halt(vcpu);
3116 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3119 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3120 if (!(vcpu->guest_debug &
3121 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3122 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3123 kvm_queue_exception(vcpu, DB_VECTOR);
3126 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3127 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3131 * Update instruction length as we may reinject #BP from
3132 * user space while in guest debugging mode. Reading it for
3133 * #DB as well causes no harm, it is not used in that case.
3135 vmx->vcpu.arch.event_exit_inst_len =
3136 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3137 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3138 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3139 kvm_run->debug.arch.exception = ex_no;
3142 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3143 kvm_run->ex.exception = ex_no;
3144 kvm_run->ex.error_code = error_code;
3150 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3152 ++vcpu->stat.irq_exits;
3156 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3158 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3162 static int handle_io(struct kvm_vcpu *vcpu)
3164 unsigned long exit_qualification;
3165 int size, in, string;
3168 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3169 string = (exit_qualification & 16) != 0;
3170 in = (exit_qualification & 8) != 0;
3172 ++vcpu->stat.io_exits;
3175 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3177 port = exit_qualification >> 16;
3178 size = (exit_qualification & 7) + 1;
3179 skip_emulated_instruction(vcpu);
3181 return kvm_fast_pio_out(vcpu, size, port);
3185 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3188 * Patch in the VMCALL instruction:
3190 hypercall[0] = 0x0f;
3191 hypercall[1] = 0x01;
3192 hypercall[2] = 0xc1;
3195 static int handle_cr(struct kvm_vcpu *vcpu)
3197 unsigned long exit_qualification, val;
3202 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3203 cr = exit_qualification & 15;
3204 reg = (exit_qualification >> 8) & 15;
3205 switch ((exit_qualification >> 4) & 3) {
3206 case 0: /* mov to cr */
3207 val = kvm_register_read(vcpu, reg);
3208 trace_kvm_cr_write(cr, val);
3211 err = kvm_set_cr0(vcpu, val);
3212 kvm_complete_insn_gp(vcpu, err);
3215 err = kvm_set_cr3(vcpu, val);
3216 kvm_complete_insn_gp(vcpu, err);
3219 err = kvm_set_cr4(vcpu, val);
3220 kvm_complete_insn_gp(vcpu, err);
3223 u8 cr8_prev = kvm_get_cr8(vcpu);
3224 u8 cr8 = kvm_register_read(vcpu, reg);
3225 err = kvm_set_cr8(vcpu, cr8);
3226 kvm_complete_insn_gp(vcpu, err);
3227 if (irqchip_in_kernel(vcpu->kvm))
3229 if (cr8_prev <= cr8)
3231 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3237 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3238 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3239 skip_emulated_instruction(vcpu);
3240 vmx_fpu_activate(vcpu);
3242 case 1: /*mov from cr*/
3245 val = kvm_read_cr3(vcpu);
3246 kvm_register_write(vcpu, reg, val);
3247 trace_kvm_cr_read(cr, val);
3248 skip_emulated_instruction(vcpu);
3251 val = kvm_get_cr8(vcpu);
3252 kvm_register_write(vcpu, reg, val);
3253 trace_kvm_cr_read(cr, val);
3254 skip_emulated_instruction(vcpu);
3259 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3260 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3261 kvm_lmsw(vcpu, val);
3263 skip_emulated_instruction(vcpu);
3268 vcpu->run->exit_reason = 0;
3269 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3270 (int)(exit_qualification >> 4) & 3, cr);
3274 static int handle_dr(struct kvm_vcpu *vcpu)
3276 unsigned long exit_qualification;
3279 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3280 if (!kvm_require_cpl(vcpu, 0))
3282 dr = vmcs_readl(GUEST_DR7);
3285 * As the vm-exit takes precedence over the debug trap, we
3286 * need to emulate the latter, either for the host or the
3287 * guest debugging itself.
3289 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3290 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3291 vcpu->run->debug.arch.dr7 = dr;
3292 vcpu->run->debug.arch.pc =
3293 vmcs_readl(GUEST_CS_BASE) +
3294 vmcs_readl(GUEST_RIP);
3295 vcpu->run->debug.arch.exception = DB_VECTOR;
3296 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3299 vcpu->arch.dr7 &= ~DR7_GD;
3300 vcpu->arch.dr6 |= DR6_BD;
3301 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3302 kvm_queue_exception(vcpu, DB_VECTOR);
3307 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3308 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3309 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3310 if (exit_qualification & TYPE_MOV_FROM_DR) {
3312 if (!kvm_get_dr(vcpu, dr, &val))
3313 kvm_register_write(vcpu, reg, val);
3315 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3316 skip_emulated_instruction(vcpu);
3320 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3322 vmcs_writel(GUEST_DR7, val);
3325 static int handle_cpuid(struct kvm_vcpu *vcpu)
3327 kvm_emulate_cpuid(vcpu);
3331 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3333 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3336 if (vmx_get_msr(vcpu, ecx, &data)) {
3337 trace_kvm_msr_read_ex(ecx);
3338 kvm_inject_gp(vcpu, 0);
3342 trace_kvm_msr_read(ecx, data);
3344 /* FIXME: handling of bits 32:63 of rax, rdx */
3345 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3346 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3347 skip_emulated_instruction(vcpu);
3351 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3353 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3354 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3355 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3357 if (vmx_set_msr(vcpu, ecx, data) != 0) {
3358 trace_kvm_msr_write_ex(ecx, data);
3359 kvm_inject_gp(vcpu, 0);
3363 trace_kvm_msr_write(ecx, data);
3364 skip_emulated_instruction(vcpu);
3368 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3370 kvm_make_request(KVM_REQ_EVENT, vcpu);
3374 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3376 u32 cpu_based_vm_exec_control;
3378 /* clear pending irq */
3379 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3380 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3381 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3383 kvm_make_request(KVM_REQ_EVENT, vcpu);
3385 ++vcpu->stat.irq_window_exits;
3388 * If the user space waits to inject interrupts, exit as soon as
3391 if (!irqchip_in_kernel(vcpu->kvm) &&
3392 vcpu->run->request_interrupt_window &&
3393 !kvm_cpu_has_interrupt(vcpu)) {
3394 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3400 static int handle_halt(struct kvm_vcpu *vcpu)
3402 skip_emulated_instruction(vcpu);
3403 return kvm_emulate_halt(vcpu);
3406 static int handle_vmcall(struct kvm_vcpu *vcpu)
3408 skip_emulated_instruction(vcpu);
3409 kvm_emulate_hypercall(vcpu);
3413 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3415 kvm_queue_exception(vcpu, UD_VECTOR);
3419 static int handle_invd(struct kvm_vcpu *vcpu)
3421 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3424 static int handle_invlpg(struct kvm_vcpu *vcpu)
3426 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3428 kvm_mmu_invlpg(vcpu, exit_qualification);
3429 skip_emulated_instruction(vcpu);
3433 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3435 skip_emulated_instruction(vcpu);
3436 kvm_emulate_wbinvd(vcpu);
3440 static int handle_xsetbv(struct kvm_vcpu *vcpu)
3442 u64 new_bv = kvm_read_edx_eax(vcpu);
3443 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3445 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3446 skip_emulated_instruction(vcpu);
3450 static int handle_apic_access(struct kvm_vcpu *vcpu)
3452 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3455 static int handle_task_switch(struct kvm_vcpu *vcpu)
3457 struct vcpu_vmx *vmx = to_vmx(vcpu);
3458 unsigned long exit_qualification;
3459 bool has_error_code = false;
3462 int reason, type, idt_v;
3464 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3465 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3467 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3469 reason = (u32)exit_qualification >> 30;
3470 if (reason == TASK_SWITCH_GATE && idt_v) {
3472 case INTR_TYPE_NMI_INTR:
3473 vcpu->arch.nmi_injected = false;
3474 if (cpu_has_virtual_nmis())
3475 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3476 GUEST_INTR_STATE_NMI);
3478 case INTR_TYPE_EXT_INTR:
3479 case INTR_TYPE_SOFT_INTR:
3480 kvm_clear_interrupt_queue(vcpu);
3482 case INTR_TYPE_HARD_EXCEPTION:
3483 if (vmx->idt_vectoring_info &
3484 VECTORING_INFO_DELIVER_CODE_MASK) {
3485 has_error_code = true;
3487 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3490 case INTR_TYPE_SOFT_EXCEPTION:
3491 kvm_clear_exception_queue(vcpu);
3497 tss_selector = exit_qualification;
3499 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3500 type != INTR_TYPE_EXT_INTR &&
3501 type != INTR_TYPE_NMI_INTR))
3502 skip_emulated_instruction(vcpu);
3504 if (kvm_task_switch(vcpu, tss_selector, reason,
3505 has_error_code, error_code) == EMULATE_FAIL) {
3506 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3507 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3508 vcpu->run->internal.ndata = 0;
3512 /* clear all local breakpoint enable flags */
3513 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3516 * TODO: What about debug traps on tss switch?
3517 * Are we supposed to inject them and update dr6?
3523 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3525 unsigned long exit_qualification;
3529 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3531 if (exit_qualification & (1 << 6)) {
3532 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3536 gla_validity = (exit_qualification >> 7) & 0x3;
3537 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3538 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3539 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3540 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3541 vmcs_readl(GUEST_LINEAR_ADDRESS));
3542 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3543 (long unsigned int)exit_qualification);
3544 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3545 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3549 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3550 trace_kvm_page_fault(gpa, exit_qualification);
3551 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
3554 static u64 ept_rsvd_mask(u64 spte, int level)
3559 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3560 mask |= (1ULL << i);
3563 /* bits 7:3 reserved */
3565 else if (level == 2) {
3566 if (spte & (1ULL << 7))
3567 /* 2MB ref, bits 20:12 reserved */
3570 /* bits 6:3 reserved */
3577 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3580 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3582 /* 010b (write-only) */
3583 WARN_ON((spte & 0x7) == 0x2);
3585 /* 110b (write/execute) */
3586 WARN_ON((spte & 0x7) == 0x6);
3588 /* 100b (execute-only) and value not supported by logical processor */
3589 if (!cpu_has_vmx_ept_execute_only())
3590 WARN_ON((spte & 0x7) == 0x4);
3594 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3596 if (rsvd_bits != 0) {
3597 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3598 __func__, rsvd_bits);
3602 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3603 u64 ept_mem_type = (spte & 0x38) >> 3;
3605 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3606 ept_mem_type == 7) {
3607 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3608 __func__, ept_mem_type);
3615 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3621 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3623 printk(KERN_ERR "EPT: Misconfiguration.\n");
3624 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3626 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3628 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3629 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3631 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3632 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3637 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3639 u32 cpu_based_vm_exec_control;
3641 /* clear pending NMI */
3642 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3643 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3644 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3645 ++vcpu->stat.nmi_window_exits;
3646 kvm_make_request(KVM_REQ_EVENT, vcpu);
3651 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3653 struct vcpu_vmx *vmx = to_vmx(vcpu);
3654 enum emulation_result err = EMULATE_DONE;
3657 bool intr_window_requested;
3659 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3660 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
3662 while (!guest_state_valid(vcpu)) {
3663 if (intr_window_requested
3664 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
3665 return handle_interrupt_window(&vmx->vcpu);
3667 err = emulate_instruction(vcpu, 0);
3669 if (err == EMULATE_DO_MMIO) {
3674 if (err != EMULATE_DONE)
3677 if (signal_pending(current))
3683 vmx->emulation_required = 0;
3689 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3690 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3692 static int handle_pause(struct kvm_vcpu *vcpu)
3694 skip_emulated_instruction(vcpu);
3695 kvm_vcpu_on_spin(vcpu);
3700 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3702 kvm_queue_exception(vcpu, UD_VECTOR);
3707 * The exit handlers return 1 if the exit was handled fully and guest execution
3708 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3709 * to be done to userspace and return 0.
3711 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3712 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3713 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3714 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3715 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3716 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3717 [EXIT_REASON_CR_ACCESS] = handle_cr,
3718 [EXIT_REASON_DR_ACCESS] = handle_dr,
3719 [EXIT_REASON_CPUID] = handle_cpuid,
3720 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3721 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3722 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3723 [EXIT_REASON_HLT] = handle_halt,
3724 [EXIT_REASON_INVD] = handle_invd,
3725 [EXIT_REASON_INVLPG] = handle_invlpg,
3726 [EXIT_REASON_VMCALL] = handle_vmcall,
3727 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3728 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3729 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3730 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3731 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3732 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3733 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3734 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3735 [EXIT_REASON_VMON] = handle_vmx_insn,
3736 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3737 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3738 [EXIT_REASON_WBINVD] = handle_wbinvd,
3739 [EXIT_REASON_XSETBV] = handle_xsetbv,
3740 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3741 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3742 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3743 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
3744 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
3745 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3746 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
3749 static const int kvm_vmx_max_exit_handlers =
3750 ARRAY_SIZE(kvm_vmx_exit_handlers);
3752 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3754 *info1 = vmcs_readl(EXIT_QUALIFICATION);
3755 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
3759 * The guest has exited. See if we can fix it or if we need userspace
3762 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3764 struct vcpu_vmx *vmx = to_vmx(vcpu);
3765 u32 exit_reason = vmx->exit_reason;
3766 u32 vectoring_info = vmx->idt_vectoring_info;
3768 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
3770 /* If guest state is invalid, start emulating */
3771 if (vmx->emulation_required && emulate_invalid_guest_state)
3772 return handle_invalid_guest_state(vcpu);
3774 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3775 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3776 vcpu->run->fail_entry.hardware_entry_failure_reason
3781 if (unlikely(vmx->fail)) {
3782 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3783 vcpu->run->fail_entry.hardware_entry_failure_reason
3784 = vmcs_read32(VM_INSTRUCTION_ERROR);
3788 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3789 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3790 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3791 exit_reason != EXIT_REASON_TASK_SWITCH))
3792 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3793 "(0x%x) and exit reason is 0x%x\n",
3794 __func__, vectoring_info, exit_reason);
3796 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3797 if (vmx_interrupt_allowed(vcpu)) {
3798 vmx->soft_vnmi_blocked = 0;
3799 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3800 vcpu->arch.nmi_pending) {
3802 * This CPU don't support us in finding the end of an
3803 * NMI-blocked window if the guest runs with IRQs
3804 * disabled. So we pull the trigger after 1 s of
3805 * futile waiting, but inform the user about this.
3807 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3808 "state on VCPU %d after 1 s timeout\n",
3809 __func__, vcpu->vcpu_id);
3810 vmx->soft_vnmi_blocked = 0;
3814 if (exit_reason < kvm_vmx_max_exit_handlers
3815 && kvm_vmx_exit_handlers[exit_reason])
3816 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3818 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3819 vcpu->run->hw.hardware_exit_reason = exit_reason;
3824 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3826 if (irr == -1 || tpr < irr) {
3827 vmcs_write32(TPR_THRESHOLD, 0);
3831 vmcs_write32(TPR_THRESHOLD, irr);
3834 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
3836 u32 exit_intr_info = vmx->exit_intr_info;
3838 /* Handle machine checks before interrupts are enabled */
3839 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3840 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3841 && is_machine_check(exit_intr_info)))
3842 kvm_machine_check();
3844 /* We need to handle NMIs before interrupts are enabled */
3845 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3846 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3847 kvm_before_handle_nmi(&vmx->vcpu);
3849 kvm_after_handle_nmi(&vmx->vcpu);
3853 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
3855 u32 exit_intr_info = vmx->exit_intr_info;
3858 bool idtv_info_valid;
3860 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3862 if (cpu_has_virtual_nmis()) {
3863 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3864 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3866 * SDM 3: 27.7.1.2 (September 2008)
3867 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3868 * a guest IRET fault.
3869 * SDM 3: 23.2.2 (September 2008)
3870 * Bit 12 is undefined in any of the following cases:
3871 * If the VM exit sets the valid bit in the IDT-vectoring
3872 * information field.
3873 * If the VM exit is due to a double fault.
3875 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3876 vector != DF_VECTOR && !idtv_info_valid)
3877 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3878 GUEST_INTR_STATE_NMI);
3879 } else if (unlikely(vmx->soft_vnmi_blocked))
3880 vmx->vnmi_blocked_time +=
3881 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3884 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
3885 u32 idt_vectoring_info,
3886 int instr_len_field,
3887 int error_code_field)
3891 bool idtv_info_valid;
3893 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3895 vmx->vcpu.arch.nmi_injected = false;
3896 kvm_clear_exception_queue(&vmx->vcpu);
3897 kvm_clear_interrupt_queue(&vmx->vcpu);
3899 if (!idtv_info_valid)
3902 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
3904 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3905 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3908 case INTR_TYPE_NMI_INTR:
3909 vmx->vcpu.arch.nmi_injected = true;
3911 * SDM 3: 27.7.1.2 (September 2008)
3912 * Clear bit "block by NMI" before VM entry if a NMI
3915 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3916 GUEST_INTR_STATE_NMI);
3918 case INTR_TYPE_SOFT_EXCEPTION:
3919 vmx->vcpu.arch.event_exit_inst_len =
3920 vmcs_read32(instr_len_field);
3922 case INTR_TYPE_HARD_EXCEPTION:
3923 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3924 u32 err = vmcs_read32(error_code_field);
3925 kvm_queue_exception_e(&vmx->vcpu, vector, err);
3927 kvm_queue_exception(&vmx->vcpu, vector);
3929 case INTR_TYPE_SOFT_INTR:
3930 vmx->vcpu.arch.event_exit_inst_len =
3931 vmcs_read32(instr_len_field);
3933 case INTR_TYPE_EXT_INTR:
3934 kvm_queue_interrupt(&vmx->vcpu, vector,
3935 type == INTR_TYPE_SOFT_INTR);
3942 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3944 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
3945 VM_EXIT_INSTRUCTION_LEN,
3946 IDT_VECTORING_ERROR_CODE);
3949 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
3951 __vmx_complete_interrupts(to_vmx(vcpu),
3952 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
3953 VM_ENTRY_INSTRUCTION_LEN,
3954 VM_ENTRY_EXCEPTION_ERROR_CODE);
3956 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
3959 #ifdef CONFIG_X86_64
3967 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3969 struct vcpu_vmx *vmx = to_vmx(vcpu);
3971 /* Record the guest's net vcpu time for enforced NMI injections. */
3972 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3973 vmx->entry_time = ktime_get();
3975 /* Don't enter VMX if guest state is invalid, let the exit handler
3976 start emulation until we arrive back to a valid state */
3977 if (vmx->emulation_required && emulate_invalid_guest_state)
3980 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3981 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3982 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3983 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3985 /* When single-stepping over STI and MOV SS, we must clear the
3986 * corresponding interruptibility bits in the guest state. Otherwise
3987 * vmentry fails as it then expects bit 14 (BS) in pending debug
3988 * exceptions being set, but that's not correct for the guest debugging
3990 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3991 vmx_set_interrupt_shadow(vcpu, 0);
3994 /* Store host registers */
3995 "push %%"R"dx; push %%"R"bp;"
3997 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3999 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4000 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
4002 /* Reload cr2 if changed */
4003 "mov %c[cr2](%0), %%"R"ax \n\t"
4004 "mov %%cr2, %%"R"dx \n\t"
4005 "cmp %%"R"ax, %%"R"dx \n\t"
4007 "mov %%"R"ax, %%cr2 \n\t"
4009 /* Check if vmlaunch of vmresume is needed */
4010 "cmpl $0, %c[launched](%0) \n\t"
4011 /* Load guest registers. Don't clobber flags. */
4012 "mov %c[rax](%0), %%"R"ax \n\t"
4013 "mov %c[rbx](%0), %%"R"bx \n\t"
4014 "mov %c[rdx](%0), %%"R"dx \n\t"
4015 "mov %c[rsi](%0), %%"R"si \n\t"
4016 "mov %c[rdi](%0), %%"R"di \n\t"
4017 "mov %c[rbp](%0), %%"R"bp \n\t"
4018 #ifdef CONFIG_X86_64
4019 "mov %c[r8](%0), %%r8 \n\t"
4020 "mov %c[r9](%0), %%r9 \n\t"
4021 "mov %c[r10](%0), %%r10 \n\t"
4022 "mov %c[r11](%0), %%r11 \n\t"
4023 "mov %c[r12](%0), %%r12 \n\t"
4024 "mov %c[r13](%0), %%r13 \n\t"
4025 "mov %c[r14](%0), %%r14 \n\t"
4026 "mov %c[r15](%0), %%r15 \n\t"
4028 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
4030 /* Enter guest mode */
4031 "jne .Llaunched \n\t"
4032 __ex(ASM_VMX_VMLAUNCH) "\n\t"
4033 "jmp .Lkvm_vmx_return \n\t"
4034 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
4035 ".Lkvm_vmx_return: "
4036 /* Save guest registers, load host registers, keep flags */
4037 "xchg %0, (%%"R"sp) \n\t"
4038 "mov %%"R"ax, %c[rax](%0) \n\t"
4039 "mov %%"R"bx, %c[rbx](%0) \n\t"
4040 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
4041 "mov %%"R"dx, %c[rdx](%0) \n\t"
4042 "mov %%"R"si, %c[rsi](%0) \n\t"
4043 "mov %%"R"di, %c[rdi](%0) \n\t"
4044 "mov %%"R"bp, %c[rbp](%0) \n\t"
4045 #ifdef CONFIG_X86_64
4046 "mov %%r8, %c[r8](%0) \n\t"
4047 "mov %%r9, %c[r9](%0) \n\t"
4048 "mov %%r10, %c[r10](%0) \n\t"
4049 "mov %%r11, %c[r11](%0) \n\t"
4050 "mov %%r12, %c[r12](%0) \n\t"
4051 "mov %%r13, %c[r13](%0) \n\t"
4052 "mov %%r14, %c[r14](%0) \n\t"
4053 "mov %%r15, %c[r15](%0) \n\t"
4055 "mov %%cr2, %%"R"ax \n\t"
4056 "mov %%"R"ax, %c[cr2](%0) \n\t"
4058 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
4059 "setbe %c[fail](%0) \n\t"
4060 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4061 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4062 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
4063 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
4064 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4065 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4066 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4067 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4068 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4069 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4070 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
4071 #ifdef CONFIG_X86_64
4072 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4073 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4074 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4075 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4076 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4077 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4078 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4079 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
4081 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
4083 , R"ax", R"bx", R"di", R"si"
4084 #ifdef CONFIG_X86_64
4085 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4089 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4090 | (1 << VCPU_EXREG_PDPTR)
4091 | (1 << VCPU_EXREG_CR3));
4092 vcpu->arch.regs_dirty = 0;
4094 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4096 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
4099 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
4100 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4102 vmx_complete_atomic_exit(vmx);
4103 vmx_recover_nmi_blocking(vmx);
4104 vmx_complete_interrupts(vmx);
4110 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4112 struct vcpu_vmx *vmx = to_vmx(vcpu);
4116 free_vmcs(vmx->vmcs);
4121 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4123 struct vcpu_vmx *vmx = to_vmx(vcpu);
4126 vmx_free_vmcs(vcpu);
4127 kfree(vmx->guest_msrs);
4128 kvm_vcpu_uninit(vcpu);
4129 kmem_cache_free(kvm_vcpu_cache, vmx);
4132 static inline void vmcs_init(struct vmcs *vmcs)
4134 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4137 kvm_cpu_vmxon(phys_addr);
4145 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4148 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4152 return ERR_PTR(-ENOMEM);
4156 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4160 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4161 if (!vmx->guest_msrs) {
4166 vmx->vmcs = alloc_vmcs();
4170 vmcs_init(vmx->vmcs);
4173 vmx_vcpu_load(&vmx->vcpu, cpu);
4174 vmx->vcpu.cpu = cpu;
4175 err = vmx_vcpu_setup(vmx);
4176 vmx_vcpu_put(&vmx->vcpu);
4180 if (vm_need_virtualize_apic_accesses(kvm))
4181 if (alloc_apic_access_page(kvm) != 0)
4185 if (!kvm->arch.ept_identity_map_addr)
4186 kvm->arch.ept_identity_map_addr =
4187 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4188 if (alloc_identity_pagetable(kvm) != 0)
4195 free_vmcs(vmx->vmcs);
4197 kfree(vmx->guest_msrs);
4199 kvm_vcpu_uninit(&vmx->vcpu);
4202 kmem_cache_free(kvm_vcpu_cache, vmx);
4203 return ERR_PTR(err);
4206 static void __init vmx_check_processor_compat(void *rtn)
4208 struct vmcs_config vmcs_conf;
4211 if (setup_vmcs_config(&vmcs_conf) < 0)
4213 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4214 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4215 smp_processor_id());
4220 static int get_ept_level(void)
4222 return VMX_EPT_DEFAULT_GAW + 1;
4225 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4229 /* For VT-d and EPT combination
4230 * 1. MMIO: always map as UC
4232 * a. VT-d without snooping control feature: can't guarantee the
4233 * result, try to trust guest.
4234 * b. VT-d with snooping control feature: snooping control feature of
4235 * VT-d engine can guarantee the cache correctness. Just set it
4236 * to WB to keep consistent with host. So the same as item 3.
4237 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4238 * consistent with host MTRR
4241 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4242 else if (vcpu->kvm->arch.iommu_domain &&
4243 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4244 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4245 VMX_EPT_MT_EPTE_SHIFT;
4247 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4253 #define _ER(x) { EXIT_REASON_##x, #x }
4255 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4257 _ER(EXTERNAL_INTERRUPT),
4259 _ER(PENDING_INTERRUPT),
4279 _ER(IO_INSTRUCTION),
4282 _ER(MWAIT_INSTRUCTION),
4283 _ER(MONITOR_INSTRUCTION),
4284 _ER(PAUSE_INSTRUCTION),
4285 _ER(MCE_DURING_VMENTRY),
4286 _ER(TPR_BELOW_THRESHOLD),
4296 static int vmx_get_lpage_level(void)
4298 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4299 return PT_DIRECTORY_LEVEL;
4301 /* For shadow and EPT supported 1GB page */
4302 return PT_PDPE_LEVEL;
4305 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4307 struct kvm_cpuid_entry2 *best;
4308 struct vcpu_vmx *vmx = to_vmx(vcpu);
4311 vmx->rdtscp_enabled = false;
4312 if (vmx_rdtscp_supported()) {
4313 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4314 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4315 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4316 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4317 vmx->rdtscp_enabled = true;
4319 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4320 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4327 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4331 static struct kvm_x86_ops vmx_x86_ops = {
4332 .cpu_has_kvm_support = cpu_has_kvm_support,
4333 .disabled_by_bios = vmx_disabled_by_bios,
4334 .hardware_setup = hardware_setup,
4335 .hardware_unsetup = hardware_unsetup,
4336 .check_processor_compatibility = vmx_check_processor_compat,
4337 .hardware_enable = hardware_enable,
4338 .hardware_disable = hardware_disable,
4339 .cpu_has_accelerated_tpr = report_flexpriority,
4341 .vcpu_create = vmx_create_vcpu,
4342 .vcpu_free = vmx_free_vcpu,
4343 .vcpu_reset = vmx_vcpu_reset,
4345 .prepare_guest_switch = vmx_save_host_state,
4346 .vcpu_load = vmx_vcpu_load,
4347 .vcpu_put = vmx_vcpu_put,
4349 .set_guest_debug = set_guest_debug,
4350 .get_msr = vmx_get_msr,
4351 .set_msr = vmx_set_msr,
4352 .get_segment_base = vmx_get_segment_base,
4353 .get_segment = vmx_get_segment,
4354 .set_segment = vmx_set_segment,
4355 .get_cpl = vmx_get_cpl,
4356 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4357 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4358 .decache_cr3 = vmx_decache_cr3,
4359 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4360 .set_cr0 = vmx_set_cr0,
4361 .set_cr3 = vmx_set_cr3,
4362 .set_cr4 = vmx_set_cr4,
4363 .set_efer = vmx_set_efer,
4364 .get_idt = vmx_get_idt,
4365 .set_idt = vmx_set_idt,
4366 .get_gdt = vmx_get_gdt,
4367 .set_gdt = vmx_set_gdt,
4368 .set_dr7 = vmx_set_dr7,
4369 .cache_reg = vmx_cache_reg,
4370 .get_rflags = vmx_get_rflags,
4371 .set_rflags = vmx_set_rflags,
4372 .fpu_activate = vmx_fpu_activate,
4373 .fpu_deactivate = vmx_fpu_deactivate,
4375 .tlb_flush = vmx_flush_tlb,
4377 .run = vmx_vcpu_run,
4378 .handle_exit = vmx_handle_exit,
4379 .skip_emulated_instruction = skip_emulated_instruction,
4380 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4381 .get_interrupt_shadow = vmx_get_interrupt_shadow,
4382 .patch_hypercall = vmx_patch_hypercall,
4383 .set_irq = vmx_inject_irq,
4384 .set_nmi = vmx_inject_nmi,
4385 .queue_exception = vmx_queue_exception,
4386 .cancel_injection = vmx_cancel_injection,
4387 .interrupt_allowed = vmx_interrupt_allowed,
4388 .nmi_allowed = vmx_nmi_allowed,
4389 .get_nmi_mask = vmx_get_nmi_mask,
4390 .set_nmi_mask = vmx_set_nmi_mask,
4391 .enable_nmi_window = enable_nmi_window,
4392 .enable_irq_window = enable_irq_window,
4393 .update_cr8_intercept = update_cr8_intercept,
4395 .set_tss_addr = vmx_set_tss_addr,
4396 .get_tdp_level = get_ept_level,
4397 .get_mt_mask = vmx_get_mt_mask,
4399 .get_exit_info = vmx_get_exit_info,
4400 .exit_reasons_str = vmx_exit_reasons_str,
4402 .get_lpage_level = vmx_get_lpage_level,
4404 .cpuid_update = vmx_cpuid_update,
4406 .rdtscp_supported = vmx_rdtscp_supported,
4408 .set_supported_cpuid = vmx_set_supported_cpuid,
4410 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
4412 .write_tsc_offset = vmx_write_tsc_offset,
4413 .adjust_tsc_offset = vmx_adjust_tsc_offset,
4415 .set_tdp_cr3 = vmx_set_cr3,
4418 static int __init vmx_init(void)
4422 rdmsrl_safe(MSR_EFER, &host_efer);
4424 for (i = 0; i < NR_VMX_MSR; ++i)
4425 kvm_define_shared_msr(i, vmx_msr_index[i]);
4427 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4428 if (!vmx_io_bitmap_a)
4431 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4432 if (!vmx_io_bitmap_b) {
4437 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4438 if (!vmx_msr_bitmap_legacy) {
4443 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4444 if (!vmx_msr_bitmap_longmode) {
4450 * Allow direct access to the PC debug port (it is often used for I/O
4451 * delays, but the vmexits simply slow things down).
4453 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4454 clear_bit(0x80, vmx_io_bitmap_a);
4456 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4458 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4459 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4461 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4463 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4464 __alignof__(struct vcpu_vmx), THIS_MODULE);
4468 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4469 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4470 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4471 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4472 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4473 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4476 bypass_guest_pf = 0;
4477 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4478 VMX_EPT_EXECUTABLE_MASK);
4483 if (bypass_guest_pf)
4484 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4489 free_page((unsigned long)vmx_msr_bitmap_longmode);
4491 free_page((unsigned long)vmx_msr_bitmap_legacy);
4493 free_page((unsigned long)vmx_io_bitmap_b);
4495 free_page((unsigned long)vmx_io_bitmap_a);
4499 static void __exit vmx_exit(void)
4501 free_page((unsigned long)vmx_msr_bitmap_legacy);
4502 free_page((unsigned long)vmx_msr_bitmap_longmode);
4503 free_page((unsigned long)vmx_io_bitmap_b);
4504 free_page((unsigned long)vmx_io_bitmap_a);
4509 module_init(vmx_init)
4510 module_exit(vmx_exit)