arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/kvm_host.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31 #include <linux/tboot.h>
  32 #include "kvm_cache_regs.h"
  33 #include "x86.h"
  34
  35 #include <asm/io.h>
  36 #include <asm/desc.h>
  37 #include <asm/vmx.h>
  38 #include <asm/virtext.h>
  39 #include <asm/mce.h>
  40 #include <asm/i387.h>
  41 #include <asm/xcr.h>
  42
  43 #include "trace.h"
  44
  45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  46 #define __ex_clear(x, reg) \
  47         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  48
  49 MODULE_AUTHOR("Qumranet");
  50 MODULE_LICENSE("GPL");
  51
  52 static int __read_mostly bypass_guest_pf = 1;
  53 module_param(bypass_guest_pf, bool, S_IRUGO);
  54
  55 static int __read_mostly enable_vpid = 1;
  56 module_param_named(vpid, enable_vpid, bool, 0444);
  57
  58 static int __read_mostly flexpriority_enabled = 1;
  59 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  60
  61 static int __read_mostly enable_ept = 1;
  62 module_param_named(ept, enable_ept, bool, S_IRUGO);
  63
  64 static int __read_mostly enable_unrestricted_guest = 1;
  65 module_param_named(unrestricted_guest,
  66                         enable_unrestricted_guest, bool, S_IRUGO);
  67
  68 static int __read_mostly emulate_invalid_guest_state = 0;
  69 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  70
  71 static int __read_mostly vmm_exclusive = 1;
  72 module_param(vmm_exclusive, bool, S_IRUGO);
  73
  74 static int __read_mostly yield_on_hlt = 1;
  75 module_param(yield_on_hlt, bool, S_IRUGO);
  76
  77 /*
  78  * If nested=1, nested virtualization is supported, i.e., guests may use
  79  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  80  * use VMX instructions.
  81  */
  82 static int __read_mostly nested = 0;
  83 module_param(nested, bool, S_IRUGO);
  84
  85 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  86         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  87 #define KVM_GUEST_CR0_MASK                                              \
  88         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  89 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  90         (X86_CR0_WP | X86_CR0_NE)
  91 #define KVM_VM_CR0_ALWAYS_ON                                            \
  92         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  93 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  94         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  95          | X86_CR4_OSXMMEXCPT)
  96
  97 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  98 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  99
 100 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 101
 102 /*
 103  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 104  * ple_gap:    upper bound on the amount of time between two successive
 105  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 106  *             According to test, this time is usually smaller than 128 cycles.
 107  * ple_window: upper bound on the amount of time a guest is allowed to execute
 108  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 109  *             less than 2^12 cycles
 110  * Time is measured based on a counter that runs at the same rate as the TSC,
 111  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 112  */
 113 #define KVM_VMX_DEFAULT_PLE_GAP    128
 114 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 115 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 116 module_param(ple_gap, int, S_IRUGO);
 117
 118 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 119 module_param(ple_window, int, S_IRUGO);
 120
 121 #define NR_AUTOLOAD_MSRS 1
 122 #define VMCS02_POOL_SIZE 1
 123
 124 struct vmcs {
 125         u32 revision_id;
 126         u32 abort;
 127         char data[0];
 128 };
 129
 130 /*
 131  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 132  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 133  * loaded on this CPU (so we can clear them if the CPU goes down).
 134  */
 135 struct loaded_vmcs {
 136         struct vmcs *vmcs;
 137         int cpu;
 138         int launched;
 139         struct list_head loaded_vmcss_on_cpu_link;
 140 };
 141
 142 struct shared_msr_entry {
 143         unsigned index;
 144         u64 data;
 145         u64 mask;
 146 };
 147
 148 /*
 149  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 150  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 151  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 152  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 153  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 154  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 155  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 156  * underlying hardware which will be used to run L2.
 157  * This structure is packed to ensure that its layout is identical across
 158  * machines (necessary for live migration).
 159  * If there are changes in this struct, VMCS12_REVISION must be changed.
 160  */
 161 typedef u64 natural_width;
 162 struct __packed vmcs12 {
 163         /* According to the Intel spec, a VMCS region must start with the
 164          * following two fields. Then follow implementation-specific data.
 165          */
 166         u32 revision_id;
 167         u32 abort;
 168
 169         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 170         u32 padding[7]; /* room for future expansion */
 171
 172         u64 io_bitmap_a;
 173         u64 io_bitmap_b;
 174         u64 msr_bitmap;
 175         u64 vm_exit_msr_store_addr;
 176         u64 vm_exit_msr_load_addr;
 177         u64 vm_entry_msr_load_addr;
 178         u64 tsc_offset;
 179         u64 virtual_apic_page_addr;
 180         u64 apic_access_addr;
 181         u64 ept_pointer;
 182         u64 guest_physical_address;
 183         u64 vmcs_link_pointer;
 184         u64 guest_ia32_debugctl;
 185         u64 guest_ia32_pat;
 186         u64 guest_ia32_efer;
 187         u64 guest_ia32_perf_global_ctrl;
 188         u64 guest_pdptr0;
 189         u64 guest_pdptr1;
 190         u64 guest_pdptr2;
 191         u64 guest_pdptr3;
 192         u64 host_ia32_pat;
 193         u64 host_ia32_efer;
 194         u64 host_ia32_perf_global_ctrl;
 195         u64 padding64[8]; /* room for future expansion */
 196         /*
 197          * To allow migration of L1 (complete with its L2 guests) between
 198          * machines of different natural widths (32 or 64 bit), we cannot have
 199          * unsigned long fields with no explict size. We use u64 (aliased
 200          * natural_width) instead. Luckily, x86 is little-endian.
 201          */
 202         natural_width cr0_guest_host_mask;
 203         natural_width cr4_guest_host_mask;
 204         natural_width cr0_read_shadow;
 205         natural_width cr4_read_shadow;
 206         natural_width cr3_target_value0;
 207         natural_width cr3_target_value1;
 208         natural_width cr3_target_value2;
 209         natural_width cr3_target_value3;
 210         natural_width exit_qualification;
 211         natural_width guest_linear_address;
 212         natural_width guest_cr0;
 213         natural_width guest_cr3;
 214         natural_width guest_cr4;
 215         natural_width guest_es_base;
 216         natural_width guest_cs_base;
 217         natural_width guest_ss_base;
 218         natural_width guest_ds_base;
 219         natural_width guest_fs_base;
 220         natural_width guest_gs_base;
 221         natural_width guest_ldtr_base;
 222         natural_width guest_tr_base;
 223         natural_width guest_gdtr_base;
 224         natural_width guest_idtr_base;
 225         natural_width guest_dr7;
 226         natural_width guest_rsp;
 227         natural_width guest_rip;
 228         natural_width guest_rflags;
 229         natural_width guest_pending_dbg_exceptions;
 230         natural_width guest_sysenter_esp;
 231         natural_width guest_sysenter_eip;
 232         natural_width host_cr0;
 233         natural_width host_cr3;
 234         natural_width host_cr4;
 235         natural_width host_fs_base;
 236         natural_width host_gs_base;
 237         natural_width host_tr_base;
 238         natural_width host_gdtr_base;
 239         natural_width host_idtr_base;
 240         natural_width host_ia32_sysenter_esp;
 241         natural_width host_ia32_sysenter_eip;
 242         natural_width host_rsp;
 243         natural_width host_rip;
 244         natural_width paddingl[8]; /* room for future expansion */
 245         u32 pin_based_vm_exec_control;
 246         u32 cpu_based_vm_exec_control;
 247         u32 exception_bitmap;
 248         u32 page_fault_error_code_mask;
 249         u32 page_fault_error_code_match;
 250         u32 cr3_target_count;
 251         u32 vm_exit_controls;
 252         u32 vm_exit_msr_store_count;
 253         u32 vm_exit_msr_load_count;
 254         u32 vm_entry_controls;
 255         u32 vm_entry_msr_load_count;
 256         u32 vm_entry_intr_info_field;
 257         u32 vm_entry_exception_error_code;
 258         u32 vm_entry_instruction_len;
 259         u32 tpr_threshold;
 260         u32 secondary_vm_exec_control;
 261         u32 vm_instruction_error;
 262         u32 vm_exit_reason;
 263         u32 vm_exit_intr_info;
 264         u32 vm_exit_intr_error_code;
 265         u32 idt_vectoring_info_field;
 266         u32 idt_vectoring_error_code;
 267         u32 vm_exit_instruction_len;
 268         u32 vmx_instruction_info;
 269         u32 guest_es_limit;
 270         u32 guest_cs_limit;
 271         u32 guest_ss_limit;
 272         u32 guest_ds_limit;
 273         u32 guest_fs_limit;
 274         u32 guest_gs_limit;
 275         u32 guest_ldtr_limit;
 276         u32 guest_tr_limit;
 277         u32 guest_gdtr_limit;
 278         u32 guest_idtr_limit;
 279         u32 guest_es_ar_bytes;
 280         u32 guest_cs_ar_bytes;
 281         u32 guest_ss_ar_bytes;
 282         u32 guest_ds_ar_bytes;
 283         u32 guest_fs_ar_bytes;
 284         u32 guest_gs_ar_bytes;
 285         u32 guest_ldtr_ar_bytes;
 286         u32 guest_tr_ar_bytes;
 287         u32 guest_interruptibility_info;
 288         u32 guest_activity_state;
 289         u32 guest_sysenter_cs;
 290         u32 host_ia32_sysenter_cs;
 291         u32 padding32[8]; /* room for future expansion */
 292         u16 virtual_processor_id;
 293         u16 guest_es_selector;
 294         u16 guest_cs_selector;
 295         u16 guest_ss_selector;
 296         u16 guest_ds_selector;
 297         u16 guest_fs_selector;
 298         u16 guest_gs_selector;
 299         u16 guest_ldtr_selector;
 300         u16 guest_tr_selector;
 301         u16 host_es_selector;
 302         u16 host_cs_selector;
 303         u16 host_ss_selector;
 304         u16 host_ds_selector;
 305         u16 host_fs_selector;
 306         u16 host_gs_selector;
 307         u16 host_tr_selector;
 308 };
 309
 310 /*
 311  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 312  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 313  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 314  */
 315 #define VMCS12_REVISION 0x11e57ed0
 316
 317 /*
 318  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 319  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 320  * current implementation, 4K are reserved to avoid future complications.
 321  */
 322 #define VMCS12_SIZE 0x1000
 323
 324 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 325 struct vmcs02_list {
 326         struct list_head list;
 327         gpa_t vmptr;
 328         struct loaded_vmcs vmcs02;
 329 };
 330
 331 /*
 332  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 333  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 334  */
 335 struct nested_vmx {
 336         /* Has the level1 guest done vmxon? */
 337         bool vmxon;
 338
 339         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 340         gpa_t current_vmptr;
 341         /* The host-usable pointer to the above */
 342         struct page *current_vmcs12_page;
 343         struct vmcs12 *current_vmcs12;
 344
 345         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 346         struct list_head vmcs02_pool;
 347         int vmcs02_num;
 348         u64 vmcs01_tsc_offset;
 349         /* L2 must run next, and mustn't decide to exit to L1. */
 350         bool nested_run_pending;
 351         /*
 352          * Guest pages referred to in vmcs02 with host-physical pointers, so
 353          * we must keep them pinned while L2 runs.
 354          */
 355         struct page *apic_access_page;
 356 };
 357
 358 struct vcpu_vmx {
 359         struct kvm_vcpu       vcpu;
 360         unsigned long         host_rsp;
 361         u8                    fail;
 362         u8                    cpl;
 363         bool                  nmi_known_unmasked;
 364         u32                   exit_intr_info;
 365         u32                   idt_vectoring_info;
 366         ulong                 rflags;
 367         struct shared_msr_entry *guest_msrs;
 368         int                   nmsrs;
 369         int                   save_nmsrs;
 370 #ifdef CONFIG_X86_64
 371         u64                   msr_host_kernel_gs_base;
 372         u64                   msr_guest_kernel_gs_base;
 373 #endif
 374         /*
 375          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 376          * non-nested (L1) guest, it always points to vmcs01. For a nested
 377          * guest (L2), it points to a different VMCS.
 378          */
 379         struct loaded_vmcs    vmcs01;
 380         struct loaded_vmcs   *loaded_vmcs;
 381         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 382         struct msr_autoload {
 383                 unsigned nr;
 384                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 385                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 386         } msr_autoload;
 387         struct {
 388                 int           loaded;
 389                 u16           fs_sel, gs_sel, ldt_sel;
 390                 int           gs_ldt_reload_needed;
 391                 int           fs_reload_needed;
 392         } host_state;
 393         struct {
 394                 int vm86_active;
 395                 ulong save_rflags;
 396                 struct kvm_save_segment {
 397                         u16 selector;
 398                         unsigned long base;
 399                         u32 limit;
 400                         u32 ar;
 401                 } tr, es, ds, fs, gs;
 402         } rmode;
 403         struct {
 404                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 405                 struct kvm_save_segment seg[8];
 406         } segment_cache;
 407         int vpid;
 408         bool emulation_required;
 409
 410         /* Support for vnmi-less CPUs */
 411         int soft_vnmi_blocked;
 412         ktime_t entry_time;
 413         s64 vnmi_blocked_time;
 414         u32 exit_reason;
 415
 416         bool rdtscp_enabled;
 417
 418         /* Support for a guest hypervisor (nested VMX) */
 419         struct nested_vmx nested;
 420 };
 421
 422 enum segment_cache_field {
 423         SEG_FIELD_SEL = 0,
 424         SEG_FIELD_BASE = 1,
 425         SEG_FIELD_LIMIT = 2,
 426         SEG_FIELD_AR = 3,
 427
 428         SEG_FIELD_NR = 4
 429 };
 430
 431 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 432 {
 433         return container_of(vcpu, struct vcpu_vmx, vcpu);
 434 }
 435
 436 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 437 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 438 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 439                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 440
 441 static unsigned short vmcs_field_to_offset_table[] = {
 442         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 443         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 444         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 445         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 446         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 447         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 448         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 449         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 450         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 451         FIELD(HOST_ES_SELECTOR, host_es_selector),
 452         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 453         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 454         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 455         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 456         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 457         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 458         FIELD64(IO_BITMAP_A, io_bitmap_a),
 459         FIELD64(IO_BITMAP_B, io_bitmap_b),
 460         FIELD64(MSR_BITMAP, msr_bitmap),
 461         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 462         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 463         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 464         FIELD64(TSC_OFFSET, tsc_offset),
 465         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 466         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 467         FIELD64(EPT_POINTER, ept_pointer),
 468         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 469         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 470         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 471         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 472         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 473         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 474         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 475         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 476         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 477         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 478         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 479         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 480         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 481         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 482         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 483         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 484         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 485         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 486         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 487         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 488         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 489         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 490         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 491         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 492         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 493         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 494         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 495         FIELD(TPR_THRESHOLD, tpr_threshold),
 496         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 497         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 498         FIELD(VM_EXIT_REASON, vm_exit_reason),
 499         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 500         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 501         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 502         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 503         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 504         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 505         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 506         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 507         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 508         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 509         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 510         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 511         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 512         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 513         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 514         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 515         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 516         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 517         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 518         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 519         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 520         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 521         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 522         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 523         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 524         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 525         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 526         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 527         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 528         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 529         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 530         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 531         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 532         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 533         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 534         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 535         FIELD(EXIT_QUALIFICATION, exit_qualification),
 536         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 537         FIELD(GUEST_CR0, guest_cr0),
 538         FIELD(GUEST_CR3, guest_cr3),
 539         FIELD(GUEST_CR4, guest_cr4),
 540         FIELD(GUEST_ES_BASE, guest_es_base),
 541         FIELD(GUEST_CS_BASE, guest_cs_base),
 542         FIELD(GUEST_SS_BASE, guest_ss_base),
 543         FIELD(GUEST_DS_BASE, guest_ds_base),
 544         FIELD(GUEST_FS_BASE, guest_fs_base),
 545         FIELD(GUEST_GS_BASE, guest_gs_base),
 546         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 547         FIELD(GUEST_TR_BASE, guest_tr_base),
 548         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 549         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 550         FIELD(GUEST_DR7, guest_dr7),
 551         FIELD(GUEST_RSP, guest_rsp),
 552         FIELD(GUEST_RIP, guest_rip),
 553         FIELD(GUEST_RFLAGS, guest_rflags),
 554         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 555         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 556         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 557         FIELD(HOST_CR0, host_cr0),
 558         FIELD(HOST_CR3, host_cr3),
 559         FIELD(HOST_CR4, host_cr4),
 560         FIELD(HOST_FS_BASE, host_fs_base),
 561         FIELD(HOST_GS_BASE, host_gs_base),
 562         FIELD(HOST_TR_BASE, host_tr_base),
 563         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 564         FIELD(HOST_IDTR_BASE, host_idtr_base),
 565         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 566         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 567         FIELD(HOST_RSP, host_rsp),
 568         FIELD(HOST_RIP, host_rip),
 569 };
 570 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 571
 572 static inline short vmcs_field_to_offset(unsigned long field)
 573 {
 574         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 575                 return -1;
 576         return vmcs_field_to_offset_table[field];
 577 }
 578
 579 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 580 {
 581         return to_vmx(vcpu)->nested.current_vmcs12;
 582 }
 583
 584 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 585 {
 586         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 587         if (is_error_page(page)) {
 588                 kvm_release_page_clean(page);
 589                 return NULL;
 590         }
 591         return page;
 592 }
 593
 594 static void nested_release_page(struct page *page)
 595 {
 596         kvm_release_page_dirty(page);
 597 }
 598
 599 static void nested_release_page_clean(struct page *page)
 600 {
 601         kvm_release_page_clean(page);
 602 }
 603
 604 static u64 construct_eptp(unsigned long root_hpa);
 605 static void kvm_cpu_vmxon(u64 addr);
 606 static void kvm_cpu_vmxoff(void);
 607 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 608 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 609
 610 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 611 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 612 /*
 613  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 614  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 615  */
 616 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 617 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 618
 619 static unsigned long *vmx_io_bitmap_a;
 620 static unsigned long *vmx_io_bitmap_b;
 621 static unsigned long *vmx_msr_bitmap_legacy;
 622 static unsigned long *vmx_msr_bitmap_longmode;
 623
 624 static bool cpu_has_load_ia32_efer;
 625
 626 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 627 static DEFINE_SPINLOCK(vmx_vpid_lock);
 628
 629 static struct vmcs_config {
 630         int size;
 631         int order;
 632         u32 revision_id;
 633         u32 pin_based_exec_ctrl;
 634         u32 cpu_based_exec_ctrl;
 635         u32 cpu_based_2nd_exec_ctrl;
 636         u32 vmexit_ctrl;
 637         u32 vmentry_ctrl;
 638 } vmcs_config;
 639
 640 static struct vmx_capability {
 641         u32 ept;
 642         u32 vpid;
 643 } vmx_capability;
 644
 645 #define VMX_SEGMENT_FIELD(seg)                                  \
 646         [VCPU_SREG_##seg] = {                                   \
 647                 .selector = GUEST_##seg##_SELECTOR,             \
 648                 .base = GUEST_##seg##_BASE,                     \
 649                 .limit = GUEST_##seg##_LIMIT,                   \
 650                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 651         }
 652
 653 static struct kvm_vmx_segment_field {
 654         unsigned selector;
 655         unsigned base;
 656         unsigned limit;
 657         unsigned ar_bytes;
 658 } kvm_vmx_segment_fields[] = {
 659         VMX_SEGMENT_FIELD(CS),
 660         VMX_SEGMENT_FIELD(DS),
 661         VMX_SEGMENT_FIELD(ES),
 662         VMX_SEGMENT_FIELD(FS),
 663         VMX_SEGMENT_FIELD(GS),
 664         VMX_SEGMENT_FIELD(SS),
 665         VMX_SEGMENT_FIELD(TR),
 666         VMX_SEGMENT_FIELD(LDTR),
 667 };
 668
 669 static u64 host_efer;
 670
 671 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 672
 673 /*
 674  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 675  * away by decrementing the array size.
 676  */
 677 static const u32 vmx_msr_index[] = {
 678 #ifdef CONFIG_X86_64
 679         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 680 #endif
 681         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 682 };
 683 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 684
 685 static inline bool is_page_fault(u32 intr_info)
 686 {
 687         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 688                              INTR_INFO_VALID_MASK)) ==
 689                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 690 }
 691
 692 static inline bool is_no_device(u32 intr_info)
 693 {
 694         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 695                              INTR_INFO_VALID_MASK)) ==
 696                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 697 }
 698
 699 static inline bool is_invalid_opcode(u32 intr_info)
 700 {
 701         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 702                              INTR_INFO_VALID_MASK)) ==
 703                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 704 }
 705
 706 static inline bool is_external_interrupt(u32 intr_info)
 707 {
 708         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 709                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 710 }
 711
 712 static inline bool is_machine_check(u32 intr_info)
 713 {
 714         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 715                              INTR_INFO_VALID_MASK)) ==
 716                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 717 }
 718
 719 static inline bool cpu_has_vmx_msr_bitmap(void)
 720 {
 721         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 722 }
 723
 724 static inline bool cpu_has_vmx_tpr_shadow(void)
 725 {
 726         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 727 }
 728
 729 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 730 {
 731         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 732 }
 733
 734 static inline bool cpu_has_secondary_exec_ctrls(void)
 735 {
 736         return vmcs_config.cpu_based_exec_ctrl &
 737                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 738 }
 739
 740 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 741 {
 742         return vmcs_config.cpu_based_2nd_exec_ctrl &
 743                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 744 }
 745
 746 static inline bool cpu_has_vmx_flexpriority(void)
 747 {
 748         return cpu_has_vmx_tpr_shadow() &&
 749                 cpu_has_vmx_virtualize_apic_accesses();
 750 }
 751
 752 static inline bool cpu_has_vmx_ept_execute_only(void)
 753 {
 754         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 755 }
 756
 757 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 758 {
 759         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 760 }
 761
 762 static inline bool cpu_has_vmx_eptp_writeback(void)
 763 {
 764         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 765 }
 766
 767 static inline bool cpu_has_vmx_ept_2m_page(void)
 768 {
 769         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 770 }
 771
 772 static inline bool cpu_has_vmx_ept_1g_page(void)
 773 {
 774         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 775 }
 776
 777 static inline bool cpu_has_vmx_ept_4levels(void)
 778 {
 779         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 780 }
 781
 782 static inline bool cpu_has_vmx_invept_individual_addr(void)
 783 {
 784         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 785 }
 786
 787 static inline bool cpu_has_vmx_invept_context(void)
 788 {
 789         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 790 }
 791
 792 static inline bool cpu_has_vmx_invept_global(void)
 793 {
 794         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 795 }
 796
 797 static inline bool cpu_has_vmx_invvpid_single(void)
 798 {
 799         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 800 }
 801
 802 static inline bool cpu_has_vmx_invvpid_global(void)
 803 {
 804         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 805 }
 806
 807 static inline bool cpu_has_vmx_ept(void)
 808 {
 809         return vmcs_config.cpu_based_2nd_exec_ctrl &
 810                 SECONDARY_EXEC_ENABLE_EPT;
 811 }
 812
 813 static inline bool cpu_has_vmx_unrestricted_guest(void)
 814 {
 815         return vmcs_config.cpu_based_2nd_exec_ctrl &
 816                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 817 }
 818
 819 static inline bool cpu_has_vmx_ple(void)
 820 {
 821         return vmcs_config.cpu_based_2nd_exec_ctrl &
 822                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 823 }
 824
 825 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 826 {
 827         return flexpriority_enabled && irqchip_in_kernel(kvm);
 828 }
 829
 830 static inline bool cpu_has_vmx_vpid(void)
 831 {
 832         return vmcs_config.cpu_based_2nd_exec_ctrl &
 833                 SECONDARY_EXEC_ENABLE_VPID;
 834 }
 835
 836 static inline bool cpu_has_vmx_rdtscp(void)
 837 {
 838         return vmcs_config.cpu_based_2nd_exec_ctrl &
 839                 SECONDARY_EXEC_RDTSCP;
 840 }
 841
 842 static inline bool cpu_has_virtual_nmis(void)
 843 {
 844         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 845 }
 846
 847 static inline bool cpu_has_vmx_wbinvd_exit(void)
 848 {
 849         return vmcs_config.cpu_based_2nd_exec_ctrl &
 850                 SECONDARY_EXEC_WBINVD_EXITING;
 851 }
 852
 853 static inline bool report_flexpriority(void)
 854 {
 855         return flexpriority_enabled;
 856 }
 857
 858 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
 859 {
 860         return vmcs12->cpu_based_vm_exec_control & bit;
 861 }
 862
 863 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
 864 {
 865         return (vmcs12->cpu_based_vm_exec_control &
 866                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
 867                 (vmcs12->secondary_vm_exec_control & bit);
 868 }
 869
 870 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
 871         struct kvm_vcpu *vcpu)
 872 {
 873         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
 874 }
 875
 876 static inline bool is_exception(u32 intr_info)
 877 {
 878         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 879                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
 880 }
 881
 882 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
 883 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
 884                         struct vmcs12 *vmcs12,
 885                         u32 reason, unsigned long qualification);
 886
 887 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 888 {
 889         int i;
 890
 891         for (i = 0; i < vmx->nmsrs; ++i)
 892                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 893                         return i;
 894         return -1;
 895 }
 896
 897 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 898 {
 899     struct {
 900         u64 vpid : 16;
 901         u64 rsvd : 48;
 902         u64 gva;
 903     } operand = { vpid, 0, gva };
 904
 905     asm volatile (__ex(ASM_VMX_INVVPID)
 906                   /* CF==1 or ZF==1 --> rc = -1 */
 907                   "; ja 1f ; ud2 ; 1:"
 908                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 909 }
 910
 911 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 912 {
 913         struct {
 914                 u64 eptp, gpa;
 915         } operand = {eptp, gpa};
 916
 917         asm volatile (__ex(ASM_VMX_INVEPT)
 918                         /* CF==1 or ZF==1 --> rc = -1 */
 919                         "; ja 1f ; ud2 ; 1:\n"
 920                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 921 }
 922
 923 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 924 {
 925         int i;
 926
 927         i = __find_msr_index(vmx, msr);
 928         if (i >= 0)
 929                 return &vmx->guest_msrs[i];
 930         return NULL;
 931 }
 932
 933 static void vmcs_clear(struct vmcs *vmcs)
 934 {
 935         u64 phys_addr = __pa(vmcs);
 936         u8 error;
 937
 938         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 939                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 940                       : "cc", "memory");
 941         if (error)
 942                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 943                        vmcs, phys_addr);
 944 }
 945
 946 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 947 {
 948         vmcs_clear(loaded_vmcs->vmcs);
 949         loaded_vmcs->cpu = -1;
 950         loaded_vmcs->launched = 0;
 951 }
 952
 953 static void vmcs_load(struct vmcs *vmcs)
 954 {
 955         u64 phys_addr = __pa(vmcs);
 956         u8 error;
 957
 958         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 959                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 960                         : "cc", "memory");
 961         if (error)
 962                 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 963                        vmcs, phys_addr);
 964 }
 965
 966 static void __loaded_vmcs_clear(void *arg)
 967 {
 968         struct loaded_vmcs *loaded_vmcs = arg;
 969         int cpu = raw_smp_processor_id();
 970
 971         if (loaded_vmcs->cpu != cpu)
 972                 return; /* vcpu migration can race with cpu offline */
 973         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 974                 per_cpu(current_vmcs, cpu) = NULL;
 975         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 976         loaded_vmcs_init(loaded_vmcs);
 977 }
 978
 979 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 980 {
 981         if (loaded_vmcs->cpu != -1)
 982                 smp_call_function_single(
 983                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
 984 }
 985
 986 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
 987 {
 988         if (vmx->vpid == 0)
 989                 return;
 990
 991         if (cpu_has_vmx_invvpid_single())
 992                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 993 }
 994
 995 static inline void vpid_sync_vcpu_global(void)
 996 {
 997         if (cpu_has_vmx_invvpid_global())
 998                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
 999 }
1000
1001 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1002 {
1003         if (cpu_has_vmx_invvpid_single())
1004                 vpid_sync_vcpu_single(vmx);
1005         else
1006                 vpid_sync_vcpu_global();
1007 }
1008
1009 static inline void ept_sync_global(void)
1010 {
1011         if (cpu_has_vmx_invept_global())
1012                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1013 }
1014
1015 static inline void ept_sync_context(u64 eptp)
1016 {
1017         if (enable_ept) {
1018                 if (cpu_has_vmx_invept_context())
1019                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1020                 else
1021                         ept_sync_global();
1022         }
1023 }
1024
1025 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1026 {
1027         if (enable_ept) {
1028                 if (cpu_has_vmx_invept_individual_addr())
1029                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1030                                         eptp, gpa);
1031                 else
1032                         ept_sync_context(eptp);
1033         }
1034 }
1035
1036 static __always_inline unsigned long vmcs_readl(unsigned long field)
1037 {
1038         unsigned long value;
1039
1040         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1041                       : "=a"(value) : "d"(field) : "cc");
1042         return value;
1043 }
1044
1045 static __always_inline u16 vmcs_read16(unsigned long field)
1046 {
1047         return vmcs_readl(field);
1048 }
1049
1050 static __always_inline u32 vmcs_read32(unsigned long field)
1051 {
1052         return vmcs_readl(field);
1053 }
1054
1055 static __always_inline u64 vmcs_read64(unsigned long field)
1056 {
1057 #ifdef CONFIG_X86_64
1058         return vmcs_readl(field);
1059 #else
1060         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1061 #endif
1062 }
1063
1064 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1065 {
1066         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1067                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1068         dump_stack();
1069 }
1070
1071 static void vmcs_writel(unsigned long field, unsigned long value)
1072 {
1073         u8 error;
1074
1075         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1076                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1077         if (unlikely(error))
1078                 vmwrite_error(field, value);
1079 }
1080
1081 static void vmcs_write16(unsigned long field, u16 value)
1082 {
1083         vmcs_writel(field, value);
1084 }
1085
1086 static void vmcs_write32(unsigned long field, u32 value)
1087 {
1088         vmcs_writel(field, value);
1089 }
1090
1091 static void vmcs_write64(unsigned long field, u64 value)
1092 {
1093         vmcs_writel(field, value);
1094 #ifndef CONFIG_X86_64
1095         asm volatile ("");
1096         vmcs_writel(field+1, value >> 32);
1097 #endif
1098 }
1099
1100 static void vmcs_clear_bits(unsigned long field, u32 mask)
1101 {
1102         vmcs_writel(field, vmcs_readl(field) & ~mask);
1103 }
1104
1105 static void vmcs_set_bits(unsigned long field, u32 mask)
1106 {
1107         vmcs_writel(field, vmcs_readl(field) | mask);
1108 }
1109
1110 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1111 {
1112         vmx->segment_cache.bitmask = 0;
1113 }
1114
1115 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1116                                        unsigned field)
1117 {
1118         bool ret;
1119         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1120
1121         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1122                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1123                 vmx->segment_cache.bitmask = 0;
1124         }
1125         ret = vmx->segment_cache.bitmask & mask;
1126         vmx->segment_cache.bitmask |= mask;
1127         return ret;
1128 }
1129
1130 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1131 {
1132         u16 *p = &vmx->segment_cache.seg[seg].selector;
1133
1134         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1135                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1136         return *p;
1137 }
1138
1139 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1140 {
1141         ulong *p = &vmx->segment_cache.seg[seg].base;
1142
1143         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1144                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1145         return *p;
1146 }
1147
1148 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1149 {
1150         u32 *p = &vmx->segment_cache.seg[seg].limit;
1151
1152         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1153                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1154         return *p;
1155 }
1156
1157 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1158 {
1159         u32 *p = &vmx->segment_cache.seg[seg].ar;
1160
1161         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1162                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1163         return *p;
1164 }
1165
1166 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1167 {
1168         u32 eb;
1169
1170         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1171              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1172         if ((vcpu->guest_debug &
1173              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1174             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1175                 eb |= 1u << BP_VECTOR;
1176         if (to_vmx(vcpu)->rmode.vm86_active)
1177                 eb = ~0;
1178         if (enable_ept)
1179                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1180         if (vcpu->fpu_active)
1181                 eb &= ~(1u << NM_VECTOR);
1182         vmcs_write32(EXCEPTION_BITMAP, eb);
1183 }
1184
1185 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1186 {
1187         unsigned i;
1188         struct msr_autoload *m = &vmx->msr_autoload;
1189
1190         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1191                 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1192                 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1193                 return;
1194         }
1195
1196         for (i = 0; i < m->nr; ++i)
1197                 if (m->guest[i].index == msr)
1198                         break;
1199
1200         if (i == m->nr)
1201                 return;
1202         --m->nr;
1203         m->guest[i] = m->guest[m->nr];
1204         m->host[i] = m->host[m->nr];
1205         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1206         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1207 }
1208
1209 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1210                                   u64 guest_val, u64 host_val)
1211 {
1212         unsigned i;
1213         struct msr_autoload *m = &vmx->msr_autoload;
1214
1215         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1216                 vmcs_write64(GUEST_IA32_EFER, guest_val);
1217                 vmcs_write64(HOST_IA32_EFER, host_val);
1218                 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1219                 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1220                 return;
1221         }
1222
1223         for (i = 0; i < m->nr; ++i)
1224                 if (m->guest[i].index == msr)
1225                         break;
1226
1227         if (i == m->nr) {
1228                 ++m->nr;
1229                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1230                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1231         }
1232
1233         m->guest[i].index = msr;
1234         m->guest[i].value = guest_val;
1235         m->host[i].index = msr;
1236         m->host[i].value = host_val;
1237 }
1238
1239 static void reload_tss(void)
1240 {
1241         /*
1242          * VT restores TR but not its size.  Useless.
1243          */
1244         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1245         struct desc_struct *descs;
1246
1247         descs = (void *)gdt->address;
1248         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1249         load_TR_desc();
1250 }
1251
1252 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1253 {
1254         u64 guest_efer;
1255         u64 ignore_bits;
1256
1257         guest_efer = vmx->vcpu.arch.efer;
1258
1259         /*
1260          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1261          * outside long mode
1262          */
1263         ignore_bits = EFER_NX | EFER_SCE;
1264 #ifdef CONFIG_X86_64
1265         ignore_bits |= EFER_LMA | EFER_LME;
1266         /* SCE is meaningful only in long mode on Intel */
1267         if (guest_efer & EFER_LMA)
1268                 ignore_bits &= ~(u64)EFER_SCE;
1269 #endif
1270         guest_efer &= ~ignore_bits;
1271         guest_efer |= host_efer & ignore_bits;
1272         vmx->guest_msrs[efer_offset].data = guest_efer;
1273         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1274
1275         clear_atomic_switch_msr(vmx, MSR_EFER);
1276         /* On ept, can't emulate nx, and must switch nx atomically */
1277         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1278                 guest_efer = vmx->vcpu.arch.efer;
1279                 if (!(guest_efer & EFER_LMA))
1280                         guest_efer &= ~EFER_LME;
1281                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1282                 return false;
1283         }
1284
1285         return true;
1286 }
1287
1288 static unsigned long segment_base(u16 selector)
1289 {
1290         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1291         struct desc_struct *d;
1292         unsigned long table_base;
1293         unsigned long v;
1294
1295         if (!(selector & ~3))
1296                 return 0;
1297
1298         table_base = gdt->address;
1299
1300         if (selector & 4) {           /* from ldt */
1301                 u16 ldt_selector = kvm_read_ldt();
1302
1303                 if (!(ldt_selector & ~3))
1304                         return 0;
1305
1306                 table_base = segment_base(ldt_selector);
1307         }
1308         d = (struct desc_struct *)(table_base + (selector & ~7));
1309         v = get_desc_base(d);
1310 #ifdef CONFIG_X86_64
1311        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1312                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1313 #endif
1314         return v;
1315 }
1316
1317 static inline unsigned long kvm_read_tr_base(void)
1318 {
1319         u16 tr;
1320         asm("str %0" : "=g"(tr));
1321         return segment_base(tr);
1322 }
1323
1324 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1325 {
1326         struct vcpu_vmx *vmx = to_vmx(vcpu);
1327         int i;
1328
1329         if (vmx->host_state.loaded)
1330                 return;
1331
1332         vmx->host_state.loaded = 1;
1333         /*
1334          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1335          * allow segment selectors with cpl > 0 or ti == 1.
1336          */
1337         vmx->host_state.ldt_sel = kvm_read_ldt();
1338         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1339         savesegment(fs, vmx->host_state.fs_sel);
1340         if (!(vmx->host_state.fs_sel & 7)) {
1341                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1342                 vmx->host_state.fs_reload_needed = 0;
1343         } else {
1344                 vmcs_write16(HOST_FS_SELECTOR, 0);
1345                 vmx->host_state.fs_reload_needed = 1;
1346         }
1347         savesegment(gs, vmx->host_state.gs_sel);
1348         if (!(vmx->host_state.gs_sel & 7))
1349                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1350         else {
1351                 vmcs_write16(HOST_GS_SELECTOR, 0);
1352                 vmx->host_state.gs_ldt_reload_needed = 1;
1353         }
1354
1355 #ifdef CONFIG_X86_64
1356         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1357         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1358 #else
1359         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1360         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1361 #endif
1362
1363 #ifdef CONFIG_X86_64
1364         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1365         if (is_long_mode(&vmx->vcpu))
1366                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1367 #endif
1368         for (i = 0; i < vmx->save_nmsrs; ++i)
1369                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1370                                    vmx->guest_msrs[i].data,
1371                                    vmx->guest_msrs[i].mask);
1372 }
1373
1374 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1375 {
1376         if (!vmx->host_state.loaded)
1377                 return;
1378
1379         ++vmx->vcpu.stat.host_state_reload;
1380         vmx->host_state.loaded = 0;
1381 #ifdef CONFIG_X86_64
1382         if (is_long_mode(&vmx->vcpu))
1383                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1384 #endif
1385         if (vmx->host_state.gs_ldt_reload_needed) {
1386                 kvm_load_ldt(vmx->host_state.ldt_sel);
1387 #ifdef CONFIG_X86_64
1388                 load_gs_index(vmx->host_state.gs_sel);
1389 #else
1390                 loadsegment(gs, vmx->host_state.gs_sel);
1391 #endif
1392         }
1393         if (vmx->host_state.fs_reload_needed)
1394                 loadsegment(fs, vmx->host_state.fs_sel);
1395         reload_tss();
1396 #ifdef CONFIG_X86_64
1397         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1398 #endif
1399         if (current_thread_info()->status & TS_USEDFPU)
1400                 clts();
1401         load_gdt(&__get_cpu_var(host_gdt));
1402 }
1403
1404 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1405 {
1406         preempt_disable();
1407         __vmx_load_host_state(vmx);
1408         preempt_enable();
1409 }
1410
1411 /*
1412  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1413  * vcpu mutex is already taken.
1414  */
1415 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1416 {
1417         struct vcpu_vmx *vmx = to_vmx(vcpu);
1418         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1419
1420         if (!vmm_exclusive)
1421                 kvm_cpu_vmxon(phys_addr);
1422         else if (vmx->loaded_vmcs->cpu != cpu)
1423                 loaded_vmcs_clear(vmx->loaded_vmcs);
1424
1425         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1426                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1427                 vmcs_load(vmx->loaded_vmcs->vmcs);
1428         }
1429
1430         if (vmx->loaded_vmcs->cpu != cpu) {
1431                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1432                 unsigned long sysenter_esp;
1433
1434                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1435                 local_irq_disable();
1436                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1437                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1438                 local_irq_enable();
1439
1440                 /*
1441                  * Linux uses per-cpu TSS and GDT, so set these when switching
1442                  * processors.
1443                  */
1444                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1445                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1446
1447                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1448                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1449                 vmx->loaded_vmcs->cpu = cpu;
1450         }
1451 }
1452
1453 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1454 {
1455         __vmx_load_host_state(to_vmx(vcpu));
1456         if (!vmm_exclusive) {
1457                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1458                 vcpu->cpu = -1;
1459                 kvm_cpu_vmxoff();
1460         }
1461 }
1462
1463 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1464 {
1465         ulong cr0;
1466
1467         if (vcpu->fpu_active)
1468                 return;
1469         vcpu->fpu_active = 1;
1470         cr0 = vmcs_readl(GUEST_CR0);
1471         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1472         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1473         vmcs_writel(GUEST_CR0, cr0);
1474         update_exception_bitmap(vcpu);
1475         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1476         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1477 }
1478
1479 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1480
1481 /*
1482  * Return the cr0 value that a nested guest would read. This is a combination
1483  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1484  * its hypervisor (cr0_read_shadow).
1485  */
1486 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1487 {
1488         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1489                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1490 }
1491 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1492 {
1493         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1494                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1495 }
1496
1497 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1498 {
1499         vmx_decache_cr0_guest_bits(vcpu);
1500         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1501         update_exception_bitmap(vcpu);
1502         vcpu->arch.cr0_guest_owned_bits = 0;
1503         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1504         vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1505 }
1506
1507 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1508 {
1509         unsigned long rflags, save_rflags;
1510
1511         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1512                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1513                 rflags = vmcs_readl(GUEST_RFLAGS);
1514                 if (to_vmx(vcpu)->rmode.vm86_active) {
1515                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1516                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1517                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1518                 }
1519                 to_vmx(vcpu)->rflags = rflags;
1520         }
1521         return to_vmx(vcpu)->rflags;
1522 }
1523
1524 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1525 {
1526         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1527         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1528         to_vmx(vcpu)->rflags = rflags;
1529         if (to_vmx(vcpu)->rmode.vm86_active) {
1530                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1531                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1532         }
1533         vmcs_writel(GUEST_RFLAGS, rflags);
1534 }
1535
1536 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1537 {
1538         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1539         int ret = 0;
1540
1541         if (interruptibility & GUEST_INTR_STATE_STI)
1542                 ret |= KVM_X86_SHADOW_INT_STI;
1543         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1544                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1545
1546         return ret & mask;
1547 }
1548
1549 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1550 {
1551         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1552         u32 interruptibility = interruptibility_old;
1553
1554         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1555
1556         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1557                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1558         else if (mask & KVM_X86_SHADOW_INT_STI)
1559                 interruptibility |= GUEST_INTR_STATE_STI;
1560
1561         if ((interruptibility != interruptibility_old))
1562                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1563 }
1564
1565 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1566 {
1567         unsigned long rip;
1568
1569         rip = kvm_rip_read(vcpu);
1570         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1571         kvm_rip_write(vcpu, rip);
1572
1573         /* skipping an emulated instruction also counts */
1574         vmx_set_interrupt_shadow(vcpu, 0);
1575 }
1576
1577 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1578 {
1579         /* Ensure that we clear the HLT state in the VMCS.  We don't need to
1580          * explicitly skip the instruction because if the HLT state is set, then
1581          * the instruction is already executing and RIP has already been
1582          * advanced. */
1583         if (!yield_on_hlt &&
1584             vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1585                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1586 }
1587
1588 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1589                                 bool has_error_code, u32 error_code,
1590                                 bool reinject)
1591 {
1592         struct vcpu_vmx *vmx = to_vmx(vcpu);
1593         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1594
1595         if (has_error_code) {
1596                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1597                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1598         }
1599
1600         if (vmx->rmode.vm86_active) {
1601                 int inc_eip = 0;
1602                 if (kvm_exception_is_soft(nr))
1603                         inc_eip = vcpu->arch.event_exit_inst_len;
1604                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1605                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1606                 return;
1607         }
1608
1609         if (kvm_exception_is_soft(nr)) {
1610                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1611                              vmx->vcpu.arch.event_exit_inst_len);
1612                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1613         } else
1614                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1615
1616         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1617         vmx_clear_hlt(vcpu);
1618 }
1619
1620 static bool vmx_rdtscp_supported(void)
1621 {
1622         return cpu_has_vmx_rdtscp();
1623 }
1624
1625 /*
1626  * Swap MSR entry in host/guest MSR entry array.
1627  */
1628 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1629 {
1630         struct shared_msr_entry tmp;
1631
1632         tmp = vmx->guest_msrs[to];
1633         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1634         vmx->guest_msrs[from] = tmp;
1635 }
1636
1637 /*
1638  * Set up the vmcs to automatically save and restore system
1639  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1640  * mode, as fiddling with msrs is very expensive.
1641  */
1642 static void setup_msrs(struct vcpu_vmx *vmx)
1643 {
1644         int save_nmsrs, index;
1645         unsigned long *msr_bitmap;
1646
1647         vmx_load_host_state(vmx);
1648         save_nmsrs = 0;
1649 #ifdef CONFIG_X86_64
1650         if (is_long_mode(&vmx->vcpu)) {
1651                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1652                 if (index >= 0)
1653                         move_msr_up(vmx, index, save_nmsrs++);
1654                 index = __find_msr_index(vmx, MSR_LSTAR);
1655                 if (index >= 0)
1656                         move_msr_up(vmx, index, save_nmsrs++);
1657                 index = __find_msr_index(vmx, MSR_CSTAR);
1658                 if (index >= 0)
1659                         move_msr_up(vmx, index, save_nmsrs++);
1660                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1661                 if (index >= 0 && vmx->rdtscp_enabled)
1662                         move_msr_up(vmx, index, save_nmsrs++);
1663                 /*
1664                  * MSR_STAR is only needed on long mode guests, and only
1665                  * if efer.sce is enabled.
1666                  */
1667                 index = __find_msr_index(vmx, MSR_STAR);
1668                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1669                         move_msr_up(vmx, index, save_nmsrs++);
1670         }
1671 #endif
1672         index = __find_msr_index(vmx, MSR_EFER);
1673         if (index >= 0 && update_transition_efer(vmx, index))
1674                 move_msr_up(vmx, index, save_nmsrs++);
1675
1676         vmx->save_nmsrs = save_nmsrs;
1677
1678         if (cpu_has_vmx_msr_bitmap()) {
1679                 if (is_long_mode(&vmx->vcpu))
1680                         msr_bitmap = vmx_msr_bitmap_longmode;
1681                 else
1682                         msr_bitmap = vmx_msr_bitmap_legacy;
1683
1684                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1685         }
1686 }
1687
1688 /*
1689  * reads and returns guest's timestamp counter "register"
1690  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1691  */
1692 static u64 guest_read_tsc(void)
1693 {
1694         u64 host_tsc, tsc_offset;
1695
1696         rdtscll(host_tsc);
1697         tsc_offset = vmcs_read64(TSC_OFFSET);
1698         return host_tsc + tsc_offset;
1699 }
1700
1701 /*
1702  * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1703  * ioctl. In this case the call-back should update internal vmx state to make
1704  * the changes effective.
1705  */
1706 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1707 {
1708         /* Nothing to do here */
1709 }
1710
1711 /*
1712  * writes 'offset' into guest's timestamp counter offset register
1713  */
1714 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1715 {
1716         vmcs_write64(TSC_OFFSET, offset);
1717 }
1718
1719 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1720 {
1721         u64 offset = vmcs_read64(TSC_OFFSET);
1722         vmcs_write64(TSC_OFFSET, offset + adjustment);
1723 }
1724
1725 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1726 {
1727         return target_tsc - native_read_tsc();
1728 }
1729
1730 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1731 {
1732         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1733         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1734 }
1735
1736 /*
1737  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1738  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1739  * all guests if the "nested" module option is off, and can also be disabled
1740  * for a single guest by disabling its VMX cpuid bit.
1741  */
1742 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1743 {
1744         return nested && guest_cpuid_has_vmx(vcpu);
1745 }
1746
1747 /*
1748  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1749  * returned for the various VMX controls MSRs when nested VMX is enabled.
1750  * The same values should also be used to verify that vmcs12 control fields are
1751  * valid during nested entry from L1 to L2.
1752  * Each of these control msrs has a low and high 32-bit half: A low bit is on
1753  * if the corresponding bit in the (32-bit) control field *must* be on, and a
1754  * bit in the high half is on if the corresponding bit in the control field
1755  * may be on. See also vmx_control_verify().
1756  * TODO: allow these variables to be modified (downgraded) by module options
1757  * or other means.
1758  */
1759 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1760 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1761 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1762 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1763 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1764 static __init void nested_vmx_setup_ctls_msrs(void)
1765 {
1766         /*
1767          * Note that as a general rule, the high half of the MSRs (bits in
1768          * the control fields which may be 1) should be initialized by the
1769          * intersection of the underlying hardware's MSR (i.e., features which
1770          * can be supported) and the list of features we want to expose -
1771          * because they are known to be properly supported in our code.
1772          * Also, usually, the low half of the MSRs (bits which must be 1) can
1773          * be set to 0, meaning that L1 may turn off any of these bits. The
1774          * reason is that if one of these bits is necessary, it will appear
1775          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1776          * fields of vmcs01 and vmcs02, will turn these bits off - and
1777          * nested_vmx_exit_handled() will not pass related exits to L1.
1778          * These rules have exceptions below.
1779          */
1780
1781         /* pin-based controls */
1782         /*
1783          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1784          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1785          */
1786         nested_vmx_pinbased_ctls_low = 0x16 ;
1787         nested_vmx_pinbased_ctls_high = 0x16 |
1788                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1789                 PIN_BASED_VIRTUAL_NMIS;
1790
1791         /* exit controls */
1792         nested_vmx_exit_ctls_low = 0;
1793         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1794 #ifdef CONFIG_X86_64
1795         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1796 #else
1797         nested_vmx_exit_ctls_high = 0;
1798 #endif
1799
1800         /* entry controls */
1801         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1802                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1803         nested_vmx_entry_ctls_low = 0;
1804         nested_vmx_entry_ctls_high &=
1805                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1806
1807         /* cpu-based controls */
1808         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1809                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1810         nested_vmx_procbased_ctls_low = 0;
1811         nested_vmx_procbased_ctls_high &=
1812                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1813                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1814                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1815                 CPU_BASED_CR3_STORE_EXITING |
1816 #ifdef CONFIG_X86_64
1817                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1818 #endif
1819                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1820                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1821                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1822         /*
1823          * We can allow some features even when not supported by the
1824          * hardware. For example, L1 can specify an MSR bitmap - and we
1825          * can use it to avoid exits to L1 - even when L0 runs L2
1826          * without MSR bitmaps.
1827          */
1828         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1829
1830         /* secondary cpu-based controls */
1831         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1832                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1833         nested_vmx_secondary_ctls_low = 0;
1834         nested_vmx_secondary_ctls_high &=
1835                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1836 }
1837
1838 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1839 {
1840         /*
1841          * Bits 0 in high must be 0, and bits 1 in low must be 1.
1842          */
1843         return ((control & high) | low) == control;
1844 }
1845
1846 static inline u64 vmx_control_msr(u32 low, u32 high)
1847 {
1848         return low | ((u64)high << 32);
1849 }
1850
1851 /*
1852  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1853  * also let it use VMX-specific MSRs.
1854  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1855  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1856  * like all other MSRs).
1857  */
1858 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1859 {
1860         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1861                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
1862                 /*
1863                  * According to the spec, processors which do not support VMX
1864                  * should throw a #GP(0) when VMX capability MSRs are read.
1865                  */
1866                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
1867                 return 1;
1868         }
1869
1870         switch (msr_index) {
1871         case MSR_IA32_FEATURE_CONTROL:
1872                 *pdata = 0;
1873                 break;
1874         case MSR_IA32_VMX_BASIC:
1875                 /*
1876                  * This MSR reports some information about VMX support. We
1877                  * should return information about the VMX we emulate for the
1878                  * guest, and the VMCS structure we give it - not about the
1879                  * VMX support of the underlying hardware.
1880                  */
1881                 *pdata = VMCS12_REVISION |
1882                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
1883                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
1884                 break;
1885         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1886         case MSR_IA32_VMX_PINBASED_CTLS:
1887                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
1888                                         nested_vmx_pinbased_ctls_high);
1889                 break;
1890         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1891         case MSR_IA32_VMX_PROCBASED_CTLS:
1892                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
1893                                         nested_vmx_procbased_ctls_high);
1894                 break;
1895         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1896         case MSR_IA32_VMX_EXIT_CTLS:
1897                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
1898                                         nested_vmx_exit_ctls_high);
1899                 break;
1900         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1901         case MSR_IA32_VMX_ENTRY_CTLS:
1902                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
1903                                         nested_vmx_entry_ctls_high);
1904                 break;
1905         case MSR_IA32_VMX_MISC:
1906                 *pdata = 0;
1907                 break;
1908         /*
1909          * These MSRs specify bits which the guest must keep fixed (on or off)
1910          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
1911          * We picked the standard core2 setting.
1912          */
1913 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
1914 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
1915         case MSR_IA32_VMX_CR0_FIXED0:
1916                 *pdata = VMXON_CR0_ALWAYSON;
1917                 break;
1918         case MSR_IA32_VMX_CR0_FIXED1:
1919                 *pdata = -1ULL;
1920                 break;
1921         case MSR_IA32_VMX_CR4_FIXED0:
1922                 *pdata = VMXON_CR4_ALWAYSON;
1923                 break;
1924         case MSR_IA32_VMX_CR4_FIXED1:
1925                 *pdata = -1ULL;
1926                 break;
1927         case MSR_IA32_VMX_VMCS_ENUM:
1928                 *pdata = 0x1f;
1929                 break;
1930         case MSR_IA32_VMX_PROCBASED_CTLS2:
1931                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
1932                                         nested_vmx_secondary_ctls_high);
1933                 break;
1934         case MSR_IA32_VMX_EPT_VPID_CAP:
1935                 /* Currently, no nested ept or nested vpid */
1936                 *pdata = 0;
1937                 break;
1938         default:
1939                 return 0;
1940         }
1941
1942         return 1;
1943 }
1944
1945 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1946 {
1947         if (!nested_vmx_allowed(vcpu))
1948                 return 0;
1949
1950         if (msr_index == MSR_IA32_FEATURE_CONTROL)
1951                 /* TODO: the right thing. */
1952                 return 1;
1953         /*
1954          * No need to treat VMX capability MSRs specially: If we don't handle
1955          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
1956          */
1957         return 0;
1958 }
1959
1960 /*
1961  * Reads an msr value (of 'msr_index') into 'pdata'.
1962  * Returns 0 on success, non-0 otherwise.
1963  * Assumes vcpu_load() was already called.
1964  */
1965 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1966 {
1967         u64 data;
1968         struct shared_msr_entry *msr;
1969
1970         if (!pdata) {
1971                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1972                 return -EINVAL;
1973         }
1974
1975         switch (msr_index) {
1976 #ifdef CONFIG_X86_64
1977         case MSR_FS_BASE:
1978                 data = vmcs_readl(GUEST_FS_BASE);
1979                 break;
1980         case MSR_GS_BASE:
1981                 data = vmcs_readl(GUEST_GS_BASE);
1982                 break;
1983         case MSR_KERNEL_GS_BASE:
1984                 vmx_load_host_state(to_vmx(vcpu));
1985                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1986                 break;
1987 #endif
1988         case MSR_EFER:
1989                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1990         case MSR_IA32_TSC:
1991                 data = guest_read_tsc();
1992                 break;
1993         case MSR_IA32_SYSENTER_CS:
1994                 data = vmcs_read32(GUEST_SYSENTER_CS);
1995                 break;
1996         case MSR_IA32_SYSENTER_EIP:
1997                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1998                 break;
1999         case MSR_IA32_SYSENTER_ESP:
2000                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2001                 break;
2002         case MSR_TSC_AUX:
2003                 if (!to_vmx(vcpu)->rdtscp_enabled)
2004                         return 1;
2005                 /* Otherwise falls through */
2006         default:
2007                 vmx_load_host_state(to_vmx(vcpu));
2008                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2009                         return 0;
2010                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2011                 if (msr) {
2012                         vmx_load_host_state(to_vmx(vcpu));
2013                         data = msr->data;
2014                         break;
2015                 }
2016                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2017         }
2018
2019         *pdata = data;
2020         return 0;
2021 }
2022
2023 /*
2024  * Writes msr value into into the appropriate "register".
2025  * Returns 0 on success, non-0 otherwise.
2026  * Assumes vcpu_load() was already called.
2027  */
2028 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2029 {
2030         struct vcpu_vmx *vmx = to_vmx(vcpu);
2031         struct shared_msr_entry *msr;
2032         int ret = 0;
2033
2034         switch (msr_index) {
2035         case MSR_EFER:
2036                 vmx_load_host_state(vmx);
2037                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2038                 break;
2039 #ifdef CONFIG_X86_64
2040         case MSR_FS_BASE:
2041                 vmx_segment_cache_clear(vmx);
2042                 vmcs_writel(GUEST_FS_BASE, data);
2043                 break;
2044         case MSR_GS_BASE:
2045                 vmx_segment_cache_clear(vmx);
2046                 vmcs_writel(GUEST_GS_BASE, data);
2047                 break;
2048         case MSR_KERNEL_GS_BASE:
2049                 vmx_load_host_state(vmx);
2050                 vmx->msr_guest_kernel_gs_base = data;
2051                 break;
2052 #endif
2053         case MSR_IA32_SYSENTER_CS:
2054                 vmcs_write32(GUEST_SYSENTER_CS, data);
2055                 break;
2056         case MSR_IA32_SYSENTER_EIP:
2057                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2058                 break;
2059         case MSR_IA32_SYSENTER_ESP:
2060                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2061                 break;
2062         case MSR_IA32_TSC:
2063                 kvm_write_tsc(vcpu, data);
2064                 break;
2065         case MSR_IA32_CR_PAT:
2066                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2067                         vmcs_write64(GUEST_IA32_PAT, data);
2068                         vcpu->arch.pat = data;
2069                         break;
2070                 }
2071                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2072                 break;
2073         case MSR_TSC_AUX:
2074                 if (!vmx->rdtscp_enabled)
2075                         return 1;
2076                 /* Check reserved bit, higher 32 bits should be zero */
2077                 if ((data >> 32) != 0)
2078                         return 1;
2079                 /* Otherwise falls through */
2080         default:
2081                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2082                         break;
2083                 msr = find_msr_entry(vmx, msr_index);
2084                 if (msr) {
2085                         vmx_load_host_state(vmx);
2086                         msr->data = data;
2087                         break;
2088                 }
2089                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2090         }
2091
2092         return ret;
2093 }
2094
2095 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2096 {
2097         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2098         switch (reg) {
2099         case VCPU_REGS_RSP:
2100                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2101                 break;
2102         case VCPU_REGS_RIP:
2103                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2104                 break;
2105         case VCPU_EXREG_PDPTR:
2106                 if (enable_ept)
2107                         ept_save_pdptrs(vcpu);
2108                 break;
2109         default:
2110                 break;
2111         }
2112 }
2113
2114 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2115 {
2116         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2117                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2118         else
2119                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2120
2121         update_exception_bitmap(vcpu);
2122 }
2123
2124 static __init int cpu_has_kvm_support(void)
2125 {
2126         return cpu_has_vmx();
2127 }
2128
2129 static __init int vmx_disabled_by_bios(void)
2130 {
2131         u64 msr;
2132
2133         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2134         if (msr & FEATURE_CONTROL_LOCKED) {
2135                 /* launched w/ TXT and VMX disabled */
2136                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2137                         && tboot_enabled())
2138                         return 1;
2139                 /* launched w/o TXT and VMX only enabled w/ TXT */
2140                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2141                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2142                         && !tboot_enabled()) {
2143                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2144                                 "activate TXT before enabling KVM\n");
2145                         return 1;
2146                 }
2147                 /* launched w/o TXT and VMX disabled */
2148                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2149                         && !tboot_enabled())
2150                         return 1;
2151         }
2152
2153         return 0;
2154 }
2155
2156 static void kvm_cpu_vmxon(u64 addr)
2157 {
2158         asm volatile (ASM_VMX_VMXON_RAX
2159                         : : "a"(&addr), "m"(addr)
2160                         : "memory", "cc");
2161 }
2162
2163 static int hardware_enable(void *garbage)
2164 {
2165         int cpu = raw_smp_processor_id();
2166         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2167         u64 old, test_bits;
2168
2169         if (read_cr4() & X86_CR4_VMXE)
2170                 return -EBUSY;
2171
2172         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2173         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2174
2175         test_bits = FEATURE_CONTROL_LOCKED;
2176         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2177         if (tboot_enabled())
2178                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2179
2180         if ((old & test_bits) != test_bits) {
2181                 /* enable and lock */
2182                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2183         }
2184         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2185
2186         if (vmm_exclusive) {
2187                 kvm_cpu_vmxon(phys_addr);
2188                 ept_sync_global();
2189         }
2190
2191         store_gdt(&__get_cpu_var(host_gdt));
2192
2193         return 0;
2194 }
2195
2196 static void vmclear_local_loaded_vmcss(void)
2197 {
2198         int cpu = raw_smp_processor_id();
2199         struct loaded_vmcs *v, *n;
2200
2201         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2202                                  loaded_vmcss_on_cpu_link)
2203                 __loaded_vmcs_clear(v);
2204 }
2205
2206
2207 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2208  * tricks.
2209  */
2210 static void kvm_cpu_vmxoff(void)
2211 {
2212         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2213 }
2214
2215 static void hardware_disable(void *garbage)
2216 {
2217         if (vmm_exclusive) {
2218                 vmclear_local_loaded_vmcss();
2219                 kvm_cpu_vmxoff();
2220         }
2221         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2222 }
2223
2224 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2225                                       u32 msr, u32 *result)
2226 {
2227         u32 vmx_msr_low, vmx_msr_high;
2228         u32 ctl = ctl_min | ctl_opt;
2229
2230         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2231
2232         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2233         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2234
2235         /* Ensure minimum (required) set of control bits are supported. */
2236         if (ctl_min & ~ctl)
2237                 return -EIO;
2238
2239         *result = ctl;
2240         return 0;
2241 }
2242
2243 static __init bool allow_1_setting(u32 msr, u32 ctl)
2244 {
2245         u32 vmx_msr_low, vmx_msr_high;
2246
2247         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2248         return vmx_msr_high & ctl;
2249 }
2250
2251 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2252 {
2253         u32 vmx_msr_low, vmx_msr_high;
2254         u32 min, opt, min2, opt2;
2255         u32 _pin_based_exec_control = 0;
2256         u32 _cpu_based_exec_control = 0;
2257         u32 _cpu_based_2nd_exec_control = 0;
2258         u32 _vmexit_control = 0;
2259         u32 _vmentry_control = 0;
2260
2261         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2262         opt = PIN_BASED_VIRTUAL_NMIS;
2263         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2264                                 &_pin_based_exec_control) < 0)
2265                 return -EIO;
2266
2267         min =
2268 #ifdef CONFIG_X86_64
2269               CPU_BASED_CR8_LOAD_EXITING |
2270               CPU_BASED_CR8_STORE_EXITING |
2271 #endif
2272               CPU_BASED_CR3_LOAD_EXITING |
2273               CPU_BASED_CR3_STORE_EXITING |
2274               CPU_BASED_USE_IO_BITMAPS |
2275               CPU_BASED_MOV_DR_EXITING |
2276               CPU_BASED_USE_TSC_OFFSETING |
2277               CPU_BASED_MWAIT_EXITING |
2278               CPU_BASED_MONITOR_EXITING |
2279               CPU_BASED_INVLPG_EXITING;
2280
2281         if (yield_on_hlt)
2282                 min |= CPU_BASED_HLT_EXITING;
2283
2284         opt = CPU_BASED_TPR_SHADOW |
2285               CPU_BASED_USE_MSR_BITMAPS |
2286               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2287         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2288                                 &_cpu_based_exec_control) < 0)
2289                 return -EIO;
2290 #ifdef CONFIG_X86_64
2291         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2292                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2293                                            ~CPU_BASED_CR8_STORE_EXITING;
2294 #endif
2295         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2296                 min2 = 0;
2297                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2298                         SECONDARY_EXEC_WBINVD_EXITING |
2299                         SECONDARY_EXEC_ENABLE_VPID |
2300                         SECONDARY_EXEC_ENABLE_EPT |
2301                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2302                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2303                         SECONDARY_EXEC_RDTSCP;
2304                 if (adjust_vmx_controls(min2, opt2,
2305                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2306                                         &_cpu_based_2nd_exec_control) < 0)
2307                         return -EIO;
2308         }
2309 #ifndef CONFIG_X86_64
2310         if (!(_cpu_based_2nd_exec_control &
2311                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2312                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2313 #endif
2314         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2315                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2316                    enabled */
2317                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2318                                              CPU_BASED_CR3_STORE_EXITING |
2319                                              CPU_BASED_INVLPG_EXITING);
2320                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2321                       vmx_capability.ept, vmx_capability.vpid);
2322         }
2323
2324         min = 0;
2325 #ifdef CONFIG_X86_64
2326         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2327 #endif
2328         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2329         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2330                                 &_vmexit_control) < 0)
2331                 return -EIO;
2332
2333         min = 0;
2334         opt = VM_ENTRY_LOAD_IA32_PAT;
2335         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2336                                 &_vmentry_control) < 0)
2337                 return -EIO;
2338
2339         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2340
2341         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2342         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2343                 return -EIO;
2344
2345 #ifdef CONFIG_X86_64
2346         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2347         if (vmx_msr_high & (1u<<16))
2348                 return -EIO;
2349 #endif
2350
2351         /* Require Write-Back (WB) memory type for VMCS accesses. */
2352         if (((vmx_msr_high >> 18) & 15) != 6)
2353                 return -EIO;
2354
2355         vmcs_conf->size = vmx_msr_high & 0x1fff;
2356         vmcs_conf->order = get_order(vmcs_config.size);
2357         vmcs_conf->revision_id = vmx_msr_low;
2358
2359         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2360         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2361         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2362         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2363         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2364
2365         cpu_has_load_ia32_efer =
2366                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2367                                 VM_ENTRY_LOAD_IA32_EFER)
2368                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2369                                    VM_EXIT_LOAD_IA32_EFER);
2370
2371         return 0;
2372 }
2373
2374 static struct vmcs *alloc_vmcs_cpu(int cpu)
2375 {
2376         int node = cpu_to_node(cpu);
2377         struct page *pages;
2378         struct vmcs *vmcs;
2379
2380         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2381         if (!pages)
2382                 return NULL;
2383         vmcs = page_address(pages);
2384         memset(vmcs, 0, vmcs_config.size);
2385         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2386         return vmcs;
2387 }
2388
2389 static struct vmcs *alloc_vmcs(void)
2390 {
2391         return alloc_vmcs_cpu(raw_smp_processor_id());
2392 }
2393
2394 static void free_vmcs(struct vmcs *vmcs)
2395 {
2396         free_pages((unsigned long)vmcs, vmcs_config.order);
2397 }
2398
2399 /*
2400  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2401  */
2402 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2403 {
2404         if (!loaded_vmcs->vmcs)
2405                 return;
2406         loaded_vmcs_clear(loaded_vmcs);
2407         free_vmcs(loaded_vmcs->vmcs);
2408         loaded_vmcs->vmcs = NULL;
2409 }
2410
2411 static void free_kvm_area(void)
2412 {
2413         int cpu;
2414
2415         for_each_possible_cpu(cpu) {
2416                 free_vmcs(per_cpu(vmxarea, cpu));
2417                 per_cpu(vmxarea, cpu) = NULL;
2418         }
2419 }
2420
2421 static __init int alloc_kvm_area(void)
2422 {
2423         int cpu;
2424
2425         for_each_possible_cpu(cpu) {
2426                 struct vmcs *vmcs;
2427
2428                 vmcs = alloc_vmcs_cpu(cpu);
2429                 if (!vmcs) {
2430                         free_kvm_area();
2431                         return -ENOMEM;
2432                 }
2433
2434                 per_cpu(vmxarea, cpu) = vmcs;
2435         }
2436         return 0;
2437 }
2438
2439 static __init int hardware_setup(void)
2440 {
2441         if (setup_vmcs_config(&vmcs_config) < 0)
2442                 return -EIO;
2443
2444         if (boot_cpu_has(X86_FEATURE_NX))
2445                 kvm_enable_efer_bits(EFER_NX);
2446
2447         if (!cpu_has_vmx_vpid())
2448                 enable_vpid = 0;
2449
2450         if (!cpu_has_vmx_ept() ||
2451             !cpu_has_vmx_ept_4levels()) {
2452                 enable_ept = 0;
2453                 enable_unrestricted_guest = 0;
2454         }
2455
2456         if (!cpu_has_vmx_unrestricted_guest())
2457                 enable_unrestricted_guest = 0;
2458
2459         if (!cpu_has_vmx_flexpriority())
2460                 flexpriority_enabled = 0;
2461
2462         if (!cpu_has_vmx_tpr_shadow())
2463                 kvm_x86_ops->update_cr8_intercept = NULL;
2464
2465         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2466                 kvm_disable_largepages();
2467
2468         if (!cpu_has_vmx_ple())
2469                 ple_gap = 0;
2470
2471         if (nested)
2472                 nested_vmx_setup_ctls_msrs();
2473
2474         return alloc_kvm_area();
2475 }
2476
2477 static __exit void hardware_unsetup(void)
2478 {
2479         free_kvm_area();
2480 }
2481
2482 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2483 {
2484         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2485
2486         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2487                 vmcs_write16(sf->selector, save->selector);
2488                 vmcs_writel(sf->base, save->base);
2489                 vmcs_write32(sf->limit, save->limit);
2490                 vmcs_write32(sf->ar_bytes, save->ar);
2491         } else {
2492                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2493                         << AR_DPL_SHIFT;
2494                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2495         }
2496 }
2497
2498 static void enter_pmode(struct kvm_vcpu *vcpu)
2499 {
2500         unsigned long flags;
2501         struct vcpu_vmx *vmx = to_vmx(vcpu);
2502
2503         vmx->emulation_required = 1;
2504         vmx->rmode.vm86_active = 0;
2505
2506         vmx_segment_cache_clear(vmx);
2507
2508         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2509         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2510         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2511         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2512
2513         flags = vmcs_readl(GUEST_RFLAGS);
2514         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2515         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2516         vmcs_writel(GUEST_RFLAGS, flags);
2517
2518         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2519                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2520
2521         update_exception_bitmap(vcpu);
2522
2523         if (emulate_invalid_guest_state)
2524                 return;
2525
2526         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2527         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2528         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2529         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2530
2531         vmx_segment_cache_clear(vmx);
2532
2533         vmcs_write16(GUEST_SS_SELECTOR, 0);
2534         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2535
2536         vmcs_write16(GUEST_CS_SELECTOR,
2537                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2538         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2539 }
2540
2541 static gva_t rmode_tss_base(struct kvm *kvm)
2542 {
2543         if (!kvm->arch.tss_addr) {
2544                 struct kvm_memslots *slots;
2545                 gfn_t base_gfn;
2546
2547                 slots = kvm_memslots(kvm);
2548                 base_gfn = slots->memslots[0].base_gfn +
2549                                  kvm->memslots->memslots[0].npages - 3;
2550                 return base_gfn << PAGE_SHIFT;
2551         }
2552         return kvm->arch.tss_addr;
2553 }
2554
2555 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2556 {
2557         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2558
2559         save->selector = vmcs_read16(sf->selector);
2560         save->base = vmcs_readl(sf->base);
2561         save->limit = vmcs_read32(sf->limit);
2562         save->ar = vmcs_read32(sf->ar_bytes);
2563         vmcs_write16(sf->selector, save->base >> 4);
2564         vmcs_write32(sf->base, save->base & 0xffff0);
2565         vmcs_write32(sf->limit, 0xffff);
2566         vmcs_write32(sf->ar_bytes, 0xf3);
2567         if (save->base & 0xf)
2568                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2569                             " aligned when entering protected mode (seg=%d)",
2570                             seg);
2571 }
2572
2573 static void enter_rmode(struct kvm_vcpu *vcpu)
2574 {
2575         unsigned long flags;
2576         struct vcpu_vmx *vmx = to_vmx(vcpu);
2577
2578         if (enable_unrestricted_guest)
2579                 return;
2580
2581         vmx->emulation_required = 1;
2582         vmx->rmode.vm86_active = 1;
2583
2584         /*
2585          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2586          * vcpu. Call it here with phys address pointing 16M below 4G.
2587          */
2588         if (!vcpu->kvm->arch.tss_addr) {
2589                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2590                              "called before entering vcpu\n");
2591                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2592                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2593                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2594         }
2595
2596         vmx_segment_cache_clear(vmx);
2597
2598         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2599         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2600         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2601
2602         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2603         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2604
2605         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2606         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2607
2608         flags = vmcs_readl(GUEST_RFLAGS);
2609         vmx->rmode.save_rflags = flags;
2610
2611         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2612
2613         vmcs_writel(GUEST_RFLAGS, flags);
2614         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2615         update_exception_bitmap(vcpu);
2616
2617         if (emulate_invalid_guest_state)
2618                 goto continue_rmode;
2619
2620         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2621         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2622         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2623
2624         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
2625         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2626         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2627                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
2628         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2629
2630         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2631         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2632         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2633         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
2634
2635 continue_rmode:
2636         kvm_mmu_reset_context(vcpu);
2637 }
2638
2639 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2640 {
2641         struct vcpu_vmx *vmx = to_vmx(vcpu);
2642         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2643
2644         if (!msr)
2645                 return;
2646
2647         /*
2648          * Force kernel_gs_base reloading before EFER changes, as control
2649          * of this msr depends on is_long_mode().
2650          */
2651         vmx_load_host_state(to_vmx(vcpu));
2652         vcpu->arch.efer = efer;
2653         if (efer & EFER_LMA) {
2654                 vmcs_write32(VM_ENTRY_CONTROLS,
2655                              vmcs_read32(VM_ENTRY_CONTROLS) |
2656                              VM_ENTRY_IA32E_MODE);
2657                 msr->data = efer;
2658         } else {
2659                 vmcs_write32(VM_ENTRY_CONTROLS,
2660                              vmcs_read32(VM_ENTRY_CONTROLS) &
2661                              ~VM_ENTRY_IA32E_MODE);
2662
2663                 msr->data = efer & ~EFER_LME;
2664         }
2665         setup_msrs(vmx);
2666 }
2667
2668 #ifdef CONFIG_X86_64
2669
2670 static void enter_lmode(struct kvm_vcpu *vcpu)
2671 {
2672         u32 guest_tr_ar;
2673
2674         vmx_segment_cache_clear(to_vmx(vcpu));
2675
2676         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2677         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2678                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
2679                        __func__);
2680                 vmcs_write32(GUEST_TR_AR_BYTES,
2681                              (guest_tr_ar & ~AR_TYPE_MASK)
2682                              | AR_TYPE_BUSY_64_TSS);
2683         }
2684         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2685 }
2686
2687 static void exit_lmode(struct kvm_vcpu *vcpu)
2688 {
2689         vmcs_write32(VM_ENTRY_CONTROLS,
2690                      vmcs_read32(VM_ENTRY_CONTROLS)
2691                      & ~VM_ENTRY_IA32E_MODE);
2692         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2693 }
2694
2695 #endif
2696
2697 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2698 {
2699         vpid_sync_context(to_vmx(vcpu));
2700         if (enable_ept) {
2701                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2702                         return;
2703                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2704         }
2705 }
2706
2707 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2708 {
2709         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2710
2711         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2712         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2713 }
2714
2715 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2716 {
2717         if (enable_ept && is_paging(vcpu))
2718                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2719         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2720 }
2721
2722 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2723 {
2724         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2725
2726         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2727         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2728 }
2729
2730 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2731 {
2732         if (!test_bit(VCPU_EXREG_PDPTR,
2733                       (unsigned long *)&vcpu->arch.regs_dirty))
2734                 return;
2735
2736         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2737                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2738                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2739                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2740                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2741         }
2742 }
2743
2744 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2745 {
2746         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2747                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2748                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2749                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2750                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2751         }
2752
2753         __set_bit(VCPU_EXREG_PDPTR,
2754                   (unsigned long *)&vcpu->arch.regs_avail);
2755         __set_bit(VCPU_EXREG_PDPTR,
2756                   (unsigned long *)&vcpu->arch.regs_dirty);
2757 }
2758
2759 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2760
2761 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2762                                         unsigned long cr0,
2763                                         struct kvm_vcpu *vcpu)
2764 {
2765         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2766                 vmx_decache_cr3(vcpu);
2767         if (!(cr0 & X86_CR0_PG)) {
2768                 /* From paging/starting to nonpaging */
2769                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2770                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2771                              (CPU_BASED_CR3_LOAD_EXITING |
2772                               CPU_BASED_CR3_STORE_EXITING));
2773                 vcpu->arch.cr0 = cr0;
2774                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2775         } else if (!is_paging(vcpu)) {
2776                 /* From nonpaging to paging */
2777                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2778                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2779                              ~(CPU_BASED_CR3_LOAD_EXITING |
2780                                CPU_BASED_CR3_STORE_EXITING));
2781                 vcpu->arch.cr0 = cr0;
2782                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2783         }
2784
2785         if (!(cr0 & X86_CR0_WP))
2786                 *hw_cr0 &= ~X86_CR0_WP;
2787 }
2788
2789 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2790 {
2791         struct vcpu_vmx *vmx = to_vmx(vcpu);
2792         unsigned long hw_cr0;
2793
2794         if (enable_unrestricted_guest)
2795                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2796                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2797         else
2798                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2799
2800         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2801                 enter_pmode(vcpu);
2802
2803         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2804                 enter_rmode(vcpu);
2805
2806 #ifdef CONFIG_X86_64
2807         if (vcpu->arch.efer & EFER_LME) {
2808                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2809                         enter_lmode(vcpu);
2810                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2811                         exit_lmode(vcpu);
2812         }
2813 #endif
2814
2815         if (enable_ept)
2816                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2817
2818         if (!vcpu->fpu_active)
2819                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2820
2821         vmcs_writel(CR0_READ_SHADOW, cr0);
2822         vmcs_writel(GUEST_CR0, hw_cr0);
2823         vcpu->arch.cr0 = cr0;
2824         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2825 }
2826
2827 static u64 construct_eptp(unsigned long root_hpa)
2828 {
2829         u64 eptp;
2830
2831         /* TODO write the value reading from MSR */
2832         eptp = VMX_EPT_DEFAULT_MT |
2833                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2834         eptp |= (root_hpa & PAGE_MASK);
2835
2836         return eptp;
2837 }
2838
2839 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2840 {
2841         unsigned long guest_cr3;
2842         u64 eptp;
2843
2844         guest_cr3 = cr3;
2845         if (enable_ept) {
2846                 eptp = construct_eptp(cr3);
2847                 vmcs_write64(EPT_POINTER, eptp);
2848                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
2849                         vcpu->kvm->arch.ept_identity_map_addr;
2850                 ept_load_pdptrs(vcpu);
2851         }
2852
2853         vmx_flush_tlb(vcpu);
2854         vmcs_writel(GUEST_CR3, guest_cr3);
2855 }
2856
2857 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2858 {
2859         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
2860                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2861
2862         if (cr4 & X86_CR4_VMXE) {
2863                 /*
2864                  * To use VMXON (and later other VMX instructions), a guest
2865                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
2866                  * So basically the check on whether to allow nested VMX
2867                  * is here.
2868                  */
2869                 if (!nested_vmx_allowed(vcpu))
2870                         return 1;
2871         } else if (to_vmx(vcpu)->nested.vmxon)
2872                 return 1;
2873
2874         vcpu->arch.cr4 = cr4;
2875         if (enable_ept) {
2876                 if (!is_paging(vcpu)) {
2877                         hw_cr4 &= ~X86_CR4_PAE;
2878                         hw_cr4 |= X86_CR4_PSE;
2879                 } else if (!(cr4 & X86_CR4_PAE)) {
2880                         hw_cr4 &= ~X86_CR4_PAE;
2881                 }
2882         }
2883
2884         vmcs_writel(CR4_READ_SHADOW, cr4);
2885         vmcs_writel(GUEST_CR4, hw_cr4);
2886         return 0;
2887 }
2888
2889 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2890                             struct kvm_segment *var, int seg)
2891 {
2892         struct vcpu_vmx *vmx = to_vmx(vcpu);
2893         struct kvm_save_segment *save;
2894         u32 ar;
2895
2896         if (vmx->rmode.vm86_active
2897             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2898                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2899                 || seg == VCPU_SREG_GS)
2900             && !emulate_invalid_guest_state) {
2901                 switch (seg) {
2902                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2903                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2904                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2905                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2906                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2907                 default: BUG();
2908                 }
2909                 var->selector = save->selector;
2910                 var->base = save->base;
2911                 var->limit = save->limit;
2912                 ar = save->ar;
2913                 if (seg == VCPU_SREG_TR
2914                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
2915                         goto use_saved_rmode_seg;
2916         }
2917         var->base = vmx_read_guest_seg_base(vmx, seg);
2918         var->limit = vmx_read_guest_seg_limit(vmx, seg);
2919         var->selector = vmx_read_guest_seg_selector(vmx, seg);
2920         ar = vmx_read_guest_seg_ar(vmx, seg);
2921 use_saved_rmode_seg:
2922         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2923                 ar = 0;
2924         var->type = ar & 15;
2925         var->s = (ar >> 4) & 1;
2926         var->dpl = (ar >> 5) & 3;
2927         var->present = (ar >> 7) & 1;
2928         var->avl = (ar >> 12) & 1;
2929         var->l = (ar >> 13) & 1;
2930         var->db = (ar >> 14) & 1;
2931         var->g = (ar >> 15) & 1;
2932         var->unusable = (ar >> 16) & 1;
2933 }
2934
2935 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2936 {
2937         struct kvm_segment s;
2938
2939         if (to_vmx(vcpu)->rmode.vm86_active) {
2940                 vmx_get_segment(vcpu, &s, seg);
2941                 return s.base;
2942         }
2943         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
2944 }
2945
2946 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2947 {
2948         if (!is_protmode(vcpu))
2949                 return 0;
2950
2951         if (!is_long_mode(vcpu)
2952             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2953                 return 3;
2954
2955         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2956 }
2957
2958 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2959 {
2960         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
2961                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2962                 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
2963         }
2964         return to_vmx(vcpu)->cpl;
2965 }
2966
2967
2968 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2969 {
2970         u32 ar;
2971
2972         if (var->unusable)
2973                 ar = 1 << 16;
2974         else {
2975                 ar = var->type & 15;
2976                 ar |= (var->s & 1) << 4;
2977                 ar |= (var->dpl & 3) << 5;
2978                 ar |= (var->present & 1) << 7;
2979                 ar |= (var->avl & 1) << 12;
2980                 ar |= (var->l & 1) << 13;
2981                 ar |= (var->db & 1) << 14;
2982                 ar |= (var->g & 1) << 15;
2983         }
2984         if (ar == 0) /* a 0 value means unusable */
2985                 ar = AR_UNUSABLE_MASK;
2986
2987         return ar;
2988 }
2989
2990 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2991                             struct kvm_segment *var, int seg)
2992 {
2993         struct vcpu_vmx *vmx = to_vmx(vcpu);
2994         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2995         u32 ar;
2996
2997         vmx_segment_cache_clear(vmx);
2998
2999         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3000                 vmcs_write16(sf->selector, var->selector);
3001                 vmx->rmode.tr.selector = var->selector;
3002                 vmx->rmode.tr.base = var->base;
3003                 vmx->rmode.tr.limit = var->limit;
3004                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3005                 return;
3006         }
3007         vmcs_writel(sf->base, var->base);
3008         vmcs_write32(sf->limit, var->limit);
3009         vmcs_write16(sf->selector, var->selector);
3010         if (vmx->rmode.vm86_active && var->s) {
3011                 /*
3012                  * Hack real-mode segments into vm86 compatibility.
3013                  */
3014                 if (var->base == 0xffff0000 && var->selector == 0xf000)
3015                         vmcs_writel(sf->base, 0xf0000);
3016                 ar = 0xf3;
3017         } else
3018                 ar = vmx_segment_access_rights(var);
3019
3020         /*
3021          *   Fix the "Accessed" bit in AR field of segment registers for older
3022          * qemu binaries.
3023          *   IA32 arch specifies that at the time of processor reset the
3024          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3025          * is setting it to 0 in the usedland code. This causes invalid guest
3026          * state vmexit when "unrestricted guest" mode is turned on.
3027          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3028          * tree. Newer qemu binaries with that qemu fix would not need this
3029          * kvm hack.
3030          */
3031         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3032                 ar |= 0x1; /* Accessed */
3033
3034         vmcs_write32(sf->ar_bytes, ar);
3035         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3036 }
3037
3038 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3039 {
3040         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3041
3042         *db = (ar >> 14) & 1;
3043         *l = (ar >> 13) & 1;
3044 }
3045
3046 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3047 {
3048         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3049         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3050 }
3051
3052 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3053 {
3054         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3055         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3056 }
3057
3058 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3059 {
3060         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3061         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3062 }
3063
3064 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3065 {
3066         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3067         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3068 }
3069
3070 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3071 {
3072         struct kvm_segment var;
3073         u32 ar;
3074
3075         vmx_get_segment(vcpu, &var, seg);
3076         ar = vmx_segment_access_rights(&var);
3077
3078         if (var.base != (var.selector << 4))
3079                 return false;
3080         if (var.limit != 0xffff)
3081                 return false;
3082         if (ar != 0xf3)
3083                 return false;
3084
3085         return true;
3086 }
3087
3088 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3089 {
3090         struct kvm_segment cs;
3091         unsigned int cs_rpl;
3092
3093         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3094         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3095
3096         if (cs.unusable)
3097                 return false;
3098         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3099                 return false;
3100         if (!cs.s)
3101                 return false;
3102         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3103                 if (cs.dpl > cs_rpl)
3104                         return false;
3105         } else {
3106                 if (cs.dpl != cs_rpl)
3107                         return false;
3108         }
3109         if (!cs.present)
3110                 return false;
3111
3112         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3113         return true;
3114 }
3115
3116 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3117 {
3118         struct kvm_segment ss;
3119         unsigned int ss_rpl;
3120
3121         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3122         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3123
3124         if (ss.unusable)
3125                 return true;
3126         if (ss.type != 3 && ss.type != 7)
3127                 return false;
3128         if (!ss.s)
3129                 return false;
3130         if (ss.dpl != ss_rpl) /* DPL != RPL */
3131                 return false;
3132         if (!ss.present)
3133                 return false;
3134
3135         return true;
3136 }
3137
3138 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3139 {
3140         struct kvm_segment var;
3141         unsigned int rpl;
3142
3143         vmx_get_segment(vcpu, &var, seg);
3144         rpl = var.selector & SELECTOR_RPL_MASK;
3145
3146         if (var.unusable)
3147                 return true;
3148         if (!var.s)
3149                 return false;
3150         if (!var.present)
3151                 return false;
3152         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3153                 if (var.dpl < rpl) /* DPL < RPL */
3154                         return false;
3155         }
3156
3157         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3158          * rights flags
3159          */
3160         return true;
3161 }
3162
3163 static bool tr_valid(struct kvm_vcpu *vcpu)
3164 {
3165         struct kvm_segment tr;
3166
3167         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3168
3169         if (tr.unusable)
3170                 return false;
3171         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3172                 return false;
3173         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3174                 return false;
3175         if (!tr.present)
3176                 return false;
3177
3178         return true;
3179 }
3180
3181 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3182 {
3183         struct kvm_segment ldtr;
3184
3185         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3186
3187         if (ldtr.unusable)
3188                 return true;
3189         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3190                 return false;
3191         if (ldtr.type != 2)
3192                 return false;
3193         if (!ldtr.present)
3194                 return false;
3195
3196         return true;
3197 }
3198
3199 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3200 {
3201         struct kvm_segment cs, ss;
3202
3203         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3204         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3205
3206         return ((cs.selector & SELECTOR_RPL_MASK) ==
3207                  (ss.selector & SELECTOR_RPL_MASK));
3208 }
3209
3210 /*
3211  * Check if guest state is valid. Returns true if valid, false if
3212  * not.
3213  * We assume that registers are always usable
3214  */
3215 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3216 {
3217         /* real mode guest state checks */
3218         if (!is_protmode(vcpu)) {
3219                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3220                         return false;
3221                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3222                         return false;
3223                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3224                         return false;
3225                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3226                         return false;
3227                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3228                         return false;
3229                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3230                         return false;
3231         } else {
3232         /* protected mode guest state checks */
3233                 if (!cs_ss_rpl_check(vcpu))
3234                         return false;
3235                 if (!code_segment_valid(vcpu))
3236                         return false;
3237                 if (!stack_segment_valid(vcpu))
3238                         return false;
3239                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3240                         return false;
3241                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3242                         return false;
3243                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3244                         return false;
3245                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3246                         return false;
3247                 if (!tr_valid(vcpu))
3248                         return false;
3249                 if (!ldtr_valid(vcpu))
3250                         return false;
3251         }
3252         /* TODO:
3253          * - Add checks on RIP
3254          * - Add checks on RFLAGS
3255          */
3256
3257         return true;
3258 }
3259
3260 static int init_rmode_tss(struct kvm *kvm)
3261 {
3262         gfn_t fn;
3263         u16 data = 0;
3264         int r, idx, ret = 0;
3265
3266         idx = srcu_read_lock(&kvm->srcu);
3267         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3268         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3269         if (r < 0)
3270                 goto out;
3271         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3272         r = kvm_write_guest_page(kvm, fn++, &data,
3273                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3274         if (r < 0)
3275                 goto out;
3276         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3277         if (r < 0)
3278                 goto out;
3279         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3280         if (r < 0)
3281                 goto out;
3282         data = ~0;
3283         r = kvm_write_guest_page(kvm, fn, &data,
3284                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3285                                  sizeof(u8));
3286         if (r < 0)
3287                 goto out;
3288
3289         ret = 1;
3290 out:
3291         srcu_read_unlock(&kvm->srcu, idx);
3292         return ret;
3293 }
3294
3295 static int init_rmode_identity_map(struct kvm *kvm)
3296 {
3297         int i, idx, r, ret;
3298         pfn_t identity_map_pfn;
3299         u32 tmp;
3300
3301         if (!enable_ept)
3302                 return 1;
3303         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3304                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3305                         "haven't been allocated!\n");
3306                 return 0;
3307         }
3308         if (likely(kvm->arch.ept_identity_pagetable_done))
3309                 return 1;
3310         ret = 0;
3311         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3312         idx = srcu_read_lock(&kvm->srcu);
3313         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3314         if (r < 0)
3315                 goto out;
3316         /* Set up identity-mapping pagetable for EPT in real mode */
3317         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3318                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3319                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3320                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3321                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3322                 if (r < 0)
3323                         goto out;
3324         }
3325         kvm->arch.ept_identity_pagetable_done = true;
3326         ret = 1;
3327 out:
3328         srcu_read_unlock(&kvm->srcu, idx);
3329         return ret;
3330 }
3331
3332 static void seg_setup(int seg)
3333 {
3334         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3335         unsigned int ar;
3336
3337         vmcs_write16(sf->selector, 0);
3338         vmcs_writel(sf->base, 0);
3339         vmcs_write32(sf->limit, 0xffff);
3340         if (enable_unrestricted_guest) {
3341                 ar = 0x93;
3342                 if (seg == VCPU_SREG_CS)
3343                         ar |= 0x08; /* code segment */
3344         } else
3345                 ar = 0xf3;
3346
3347         vmcs_write32(sf->ar_bytes, ar);
3348 }
3349
3350 static int alloc_apic_access_page(struct kvm *kvm)
3351 {
3352         struct kvm_userspace_memory_region kvm_userspace_mem;
3353         int r = 0;
3354
3355         mutex_lock(&kvm->slots_lock);
3356         if (kvm->arch.apic_access_page)
3357                 goto out;
3358         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3359         kvm_userspace_mem.flags = 0;
3360         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3361         kvm_userspace_mem.memory_size = PAGE_SIZE;
3362         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3363         if (r)
3364                 goto out;
3365
3366         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3367 out:
3368         mutex_unlock(&kvm->slots_lock);
3369         return r;
3370 }
3371
3372 static int alloc_identity_pagetable(struct kvm *kvm)
3373 {
3374         struct kvm_userspace_memory_region kvm_userspace_mem;
3375         int r = 0;
3376
3377         mutex_lock(&kvm->slots_lock);
3378         if (kvm->arch.ept_identity_pagetable)
3379                 goto out;
3380         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3381         kvm_userspace_mem.flags = 0;
3382         kvm_userspace_mem.guest_phys_addr =
3383                 kvm->arch.ept_identity_map_addr;
3384         kvm_userspace_mem.memory_size = PAGE_SIZE;
3385         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3386         if (r)
3387                 goto out;
3388
3389         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3390                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3391 out:
3392         mutex_unlock(&kvm->slots_lock);
3393         return r;
3394 }
3395
3396 static void allocate_vpid(struct vcpu_vmx *vmx)
3397 {
3398         int vpid;
3399
3400         vmx->vpid = 0;
3401         if (!enable_vpid)
3402                 return;
3403         spin_lock(&vmx_vpid_lock);
3404         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3405         if (vpid < VMX_NR_VPIDS) {
3406                 vmx->vpid = vpid;
3407                 __set_bit(vpid, vmx_vpid_bitmap);
3408         }
3409         spin_unlock(&vmx_vpid_lock);
3410 }
3411
3412 static void free_vpid(struct vcpu_vmx *vmx)
3413 {
3414         if (!enable_vpid)
3415                 return;
3416         spin_lock(&vmx_vpid_lock);
3417         if (vmx->vpid != 0)
3418                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3419         spin_unlock(&vmx_vpid_lock);
3420 }
3421
3422 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3423 {
3424         int f = sizeof(unsigned long);
3425
3426         if (!cpu_has_vmx_msr_bitmap())
3427                 return;
3428
3429         /*
3430          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3431          * have the write-low and read-high bitmap offsets the wrong way round.
3432          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3433          */
3434         if (msr <= 0x1fff) {
3435                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3436                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3437         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3438                 msr &= 0x1fff;
3439                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3440                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3441         }
3442 }
3443
3444 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3445 {
3446         if (!longmode_only)
3447                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3448         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3449 }
3450
3451 /*
3452  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3453  * will not change in the lifetime of the guest.
3454  * Note that host-state that does change is set elsewhere. E.g., host-state
3455  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3456  */
3457 static void vmx_set_constant_host_state(void)
3458 {
3459         u32 low32, high32;
3460         unsigned long tmpl;
3461         struct desc_ptr dt;
3462
3463         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
3464         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
3465         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
3466
3467         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3468         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3469         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3470         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3471         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3472
3473         native_store_idt(&dt);
3474         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3475
3476         asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3477         vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3478
3479         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3480         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3481         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3482         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3483
3484         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3485                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3486                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3487         }
3488 }
3489
3490 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3491 {
3492         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3493         if (enable_ept)
3494                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3495         if (is_guest_mode(&vmx->vcpu))
3496                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3497                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3498         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3499 }
3500
3501 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3502 {
3503         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3504         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3505                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3506 #ifdef CONFIG_X86_64
3507                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3508                                 CPU_BASED_CR8_LOAD_EXITING;
3509 #endif
3510         }
3511         if (!enable_ept)
3512                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3513                                 CPU_BASED_CR3_LOAD_EXITING  |
3514                                 CPU_BASED_INVLPG_EXITING;
3515         return exec_control;
3516 }
3517
3518 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3519 {
3520         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3521         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3522                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3523         if (vmx->vpid == 0)
3524                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3525         if (!enable_ept) {
3526                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3527                 enable_unrestricted_guest = 0;
3528         }
3529         if (!enable_unrestricted_guest)
3530                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3531         if (!ple_gap)
3532                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3533         return exec_control;
3534 }
3535
3536 /*
3537  * Sets up the vmcs for emulated real mode.
3538  */
3539 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3540 {
3541         unsigned long a;
3542         int i;
3543
3544         /* I/O */
3545         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3546         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3547
3548         if (cpu_has_vmx_msr_bitmap())
3549                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3550
3551         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3552
3553         /* Control */
3554         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3555                 vmcs_config.pin_based_exec_ctrl);
3556
3557         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3558
3559         if (cpu_has_secondary_exec_ctrls()) {
3560                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3561                                 vmx_secondary_exec_control(vmx));
3562         }
3563
3564         if (ple_gap) {
3565                 vmcs_write32(PLE_GAP, ple_gap);
3566                 vmcs_write32(PLE_WINDOW, ple_window);
3567         }
3568
3569         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
3570         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
3571         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
3572
3573         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
3574         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
3575         vmx_set_constant_host_state();
3576 #ifdef CONFIG_X86_64
3577         rdmsrl(MSR_FS_BASE, a);
3578         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3579         rdmsrl(MSR_GS_BASE, a);
3580         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3581 #else
3582         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3583         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3584 #endif
3585
3586         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3587         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3588         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3589         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3590         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3591
3592         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3593                 u32 msr_low, msr_high;
3594                 u64 host_pat;
3595                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3596                 host_pat = msr_low | ((u64) msr_high << 32);
3597                 /* Write the default value follow host pat */
3598                 vmcs_write64(GUEST_IA32_PAT, host_pat);
3599                 /* Keep arch.pat sync with GUEST_IA32_PAT */
3600                 vmx->vcpu.arch.pat = host_pat;
3601         }
3602
3603         for (i = 0; i < NR_VMX_MSR; ++i) {
3604                 u32 index = vmx_msr_index[i];
3605                 u32 data_low, data_high;
3606                 int j = vmx->nmsrs;
3607
3608                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3609                         continue;
3610                 if (wrmsr_safe(index, data_low, data_high) < 0)
3611                         continue;
3612                 vmx->guest_msrs[j].index = i;
3613                 vmx->guest_msrs[j].data = 0;
3614                 vmx->guest_msrs[j].mask = -1ull;
3615                 ++vmx->nmsrs;
3616         }
3617
3618         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3619
3620         /* 22.2.1, 20.8.1 */
3621         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3622
3623         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3624         set_cr4_guest_host_mask(vmx);
3625
3626         kvm_write_tsc(&vmx->vcpu, 0);
3627
3628         return 0;
3629 }
3630
3631 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3632 {
3633         struct vcpu_vmx *vmx = to_vmx(vcpu);
3634         u64 msr;
3635         int ret;
3636
3637         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3638
3639         vmx->rmode.vm86_active = 0;
3640
3641         vmx->soft_vnmi_blocked = 0;
3642
3643         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3644         kvm_set_cr8(&vmx->vcpu, 0);
3645         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3646         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3647                 msr |= MSR_IA32_APICBASE_BSP;
3648         kvm_set_apic_base(&vmx->vcpu, msr);
3649
3650         ret = fx_init(&vmx->vcpu);
3651         if (ret != 0)
3652                 goto out;
3653
3654         vmx_segment_cache_clear(vmx);
3655
3656         seg_setup(VCPU_SREG_CS);
3657         /*
3658          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3659          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
3660          */
3661         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3662                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3663                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3664         } else {
3665                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3666                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3667         }
3668
3669         seg_setup(VCPU_SREG_DS);
3670         seg_setup(VCPU_SREG_ES);
3671         seg_setup(VCPU_SREG_FS);
3672         seg_setup(VCPU_SREG_GS);
3673         seg_setup(VCPU_SREG_SS);
3674
3675         vmcs_write16(GUEST_TR_SELECTOR, 0);
3676         vmcs_writel(GUEST_TR_BASE, 0);
3677         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3678         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3679
3680         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3681         vmcs_writel(GUEST_LDTR_BASE, 0);
3682         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3683         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3684
3685         vmcs_write32(GUEST_SYSENTER_CS, 0);
3686         vmcs_writel(GUEST_SYSENTER_ESP, 0);
3687         vmcs_writel(GUEST_SYSENTER_EIP, 0);
3688
3689         vmcs_writel(GUEST_RFLAGS, 0x02);
3690         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3691                 kvm_rip_write(vcpu, 0xfff0);
3692         else
3693                 kvm_rip_write(vcpu, 0);
3694         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3695
3696         vmcs_writel(GUEST_DR7, 0x400);
3697
3698         vmcs_writel(GUEST_GDTR_BASE, 0);
3699         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3700
3701         vmcs_writel(GUEST_IDTR_BASE, 0);
3702         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3703
3704         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3705         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3706         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3707
3708         /* Special registers */
3709         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3710
3711         setup_msrs(vmx);
3712
3713         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
3714
3715         if (cpu_has_vmx_tpr_shadow()) {
3716                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3717                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3718                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3719                                      __pa(vmx->vcpu.arch.apic->regs));
3720                 vmcs_write32(TPR_THRESHOLD, 0);
3721         }
3722
3723         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3724                 vmcs_write64(APIC_ACCESS_ADDR,
3725                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3726
3727         if (vmx->vpid != 0)
3728                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3729
3730         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3731         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3732         vmx_set_cr4(&vmx->vcpu, 0);
3733         vmx_set_efer(&vmx->vcpu, 0);
3734         vmx_fpu_activate(&vmx->vcpu);
3735         update_exception_bitmap(&vmx->vcpu);
3736
3737         vpid_sync_context(vmx);
3738
3739         ret = 0;
3740
3741         /* HACK: Don't enable emulation on guest boot/reset */
3742         vmx->emulation_required = 0;
3743
3744 out:
3745         return ret;
3746 }
3747
3748 /*
3749  * In nested virtualization, check if L1 asked to exit on external interrupts.
3750  * For most existing hypervisors, this will always return true.
3751  */
3752 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3753 {
3754         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3755                 PIN_BASED_EXT_INTR_MASK;
3756 }
3757
3758 static void enable_irq_window(struct kvm_vcpu *vcpu)
3759 {
3760         u32 cpu_based_vm_exec_control;
3761         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
3762                 /* We can get here when nested_run_pending caused
3763                  * vmx_interrupt_allowed() to return false. In this case, do
3764                  * nothing - the interrupt will be injected later.
3765                  */
3766                 return;
3767
3768         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3769         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3770         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3771 }
3772
3773 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3774 {
3775         u32 cpu_based_vm_exec_control;
3776
3777         if (!cpu_has_virtual_nmis()) {
3778                 enable_irq_window(vcpu);
3779                 return;
3780         }
3781
3782         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3783                 enable_irq_window(vcpu);
3784                 return;
3785         }
3786         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3787         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3788         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3789 }
3790
3791 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
3792 {
3793         struct vcpu_vmx *vmx = to_vmx(vcpu);
3794         uint32_t intr;
3795         int irq = vcpu->arch.interrupt.nr;
3796
3797         trace_kvm_inj_virq(irq);
3798
3799         ++vcpu->stat.irq_injections;
3800         if (vmx->rmode.vm86_active) {
3801                 int inc_eip = 0;
3802                 if (vcpu->arch.interrupt.soft)
3803                         inc_eip = vcpu->arch.event_exit_inst_len;
3804                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
3805                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3806                 return;
3807         }
3808         intr = irq | INTR_INFO_VALID_MASK;
3809         if (vcpu->arch.interrupt.soft) {
3810                 intr |= INTR_TYPE_SOFT_INTR;
3811                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3812                              vmx->vcpu.arch.event_exit_inst_len);
3813         } else
3814                 intr |= INTR_TYPE_EXT_INTR;
3815         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
3816         vmx_clear_hlt(vcpu);
3817 }
3818
3819 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
3820 {
3821         struct vcpu_vmx *vmx = to_vmx(vcpu);
3822
3823         if (!cpu_has_virtual_nmis()) {
3824                 /*
3825                  * Tracking the NMI-blocked state in software is built upon
3826                  * finding the next open IRQ window. This, in turn, depends on
3827                  * well-behaving guests: They have to keep IRQs disabled at
3828                  * least as long as the NMI handler runs. Otherwise we may
3829                  * cause NMI nesting, maybe breaking the guest. But as this is
3830                  * highly unlikely, we can live with the residual risk.
3831                  */
3832                 vmx->soft_vnmi_blocked = 1;
3833                 vmx->vnmi_blocked_time = 0;
3834         }
3835
3836         ++vcpu->stat.nmi_injections;
3837         vmx->nmi_known_unmasked = false;
3838         if (vmx->rmode.vm86_active) {
3839                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
3840                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3841                 return;
3842         }
3843         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
3844                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
3845         vmx_clear_hlt(vcpu);
3846 }
3847
3848 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
3849 {
3850         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
3851                 return 0;
3852
3853         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3854                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
3855                    | GUEST_INTR_STATE_NMI));
3856 }
3857
3858 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3859 {
3860         if (!cpu_has_virtual_nmis())
3861                 return to_vmx(vcpu)->soft_vnmi_blocked;
3862         if (to_vmx(vcpu)->nmi_known_unmasked)
3863                 return false;
3864         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3865 }
3866
3867 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3868 {
3869         struct vcpu_vmx *vmx = to_vmx(vcpu);
3870
3871         if (!cpu_has_virtual_nmis()) {
3872                 if (vmx->soft_vnmi_blocked != masked) {
3873                         vmx->soft_vnmi_blocked = masked;
3874                         vmx->vnmi_blocked_time = 0;
3875                 }
3876         } else {
3877                 vmx->nmi_known_unmasked = !masked;
3878                 if (masked)
3879                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3880                                       GUEST_INTR_STATE_NMI);
3881                 else
3882                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3883                                         GUEST_INTR_STATE_NMI);
3884         }
3885 }
3886
3887 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
3888 {
3889         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
3890                 struct vmcs12 *vmcs12;
3891                 if (to_vmx(vcpu)->nested.nested_run_pending)
3892                         return 0;
3893                 nested_vmx_vmexit(vcpu);
3894                 vmcs12 = get_vmcs12(vcpu);
3895                 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
3896                 vmcs12->vm_exit_intr_info = 0;
3897                 /* fall through to normal code, but now in L1, not L2 */
3898         }
3899
3900         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
3901                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3902                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
3903 }
3904
3905 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
3906 {
3907         int ret;
3908         struct kvm_userspace_memory_region tss_mem = {
3909                 .slot = TSS_PRIVATE_MEMSLOT,
3910                 .guest_phys_addr = addr,
3911                 .memory_size = PAGE_SIZE * 3,
3912                 .flags = 0,
3913         };
3914
3915         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3916         if (ret)
3917                 return ret;
3918         kvm->arch.tss_addr = addr;
3919         if (!init_rmode_tss(kvm))
3920                 return  -ENOMEM;
3921
3922         return 0;
3923 }
3924
3925 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3926                                   int vec, u32 err_code)
3927 {
3928         /*
3929          * Instruction with address size override prefix opcode 0x67
3930          * Cause the #SS fault with 0 error code in VM86 mode.
3931          */
3932         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3933                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
3934                         return 1;
3935         /*
3936          * Forward all other exceptions that are valid in real mode.
3937          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3938          *        the required debugging infrastructure rework.
3939          */
3940         switch (vec) {
3941         case DB_VECTOR:
3942                 if (vcpu->guest_debug &
3943                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
3944                         return 0;
3945                 kvm_queue_exception(vcpu, vec);
3946                 return 1;
3947         case BP_VECTOR:
3948                 /*
3949                  * Update instruction length as we may reinject the exception
3950                  * from user space while in guest debugging mode.
3951                  */
3952                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3953                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3954                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3955                         return 0;
3956                 /* fall through */
3957         case DE_VECTOR:
3958         case OF_VECTOR:
3959         case BR_VECTOR:
3960         case UD_VECTOR:
3961         case DF_VECTOR:
3962         case SS_VECTOR:
3963         case GP_VECTOR:
3964         case MF_VECTOR:
3965                 kvm_queue_exception(vcpu, vec);
3966                 return 1;
3967         }
3968         return 0;
3969 }
3970
3971 /*
3972  * Trigger machine check on the host. We assume all the MSRs are already set up
3973  * by the CPU and that we still run on the same CPU as the MCE occurred on.
3974  * We pass a fake environment to the machine check handler because we want
3975  * the guest to be always treated like user space, no matter what context
3976  * it used internally.
3977  */
3978 static void kvm_machine_check(void)
3979 {
3980 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3981         struct pt_regs regs = {
3982                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3983                 .flags = X86_EFLAGS_IF,
3984         };
3985
3986         do_machine_check(&regs, 0);
3987 #endif
3988 }
3989
3990 static int handle_machine_check(struct kvm_vcpu *vcpu)
3991 {
3992         /* already handled by vcpu_run */
3993         return 1;
3994 }
3995
3996 static int handle_exception(struct kvm_vcpu *vcpu)
3997 {
3998         struct vcpu_vmx *vmx = to_vmx(vcpu);
3999         struct kvm_run *kvm_run = vcpu->run;
4000         u32 intr_info, ex_no, error_code;
4001         unsigned long cr2, rip, dr6;
4002         u32 vect_info;
4003         enum emulation_result er;
4004
4005         vect_info = vmx->idt_vectoring_info;
4006         intr_info = vmx->exit_intr_info;
4007
4008         if (is_machine_check(intr_info))
4009                 return handle_machine_check(vcpu);
4010
4011         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4012             !is_page_fault(intr_info)) {
4013                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4014                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4015                 vcpu->run->internal.ndata = 2;
4016                 vcpu->run->internal.data[0] = vect_info;
4017                 vcpu->run->internal.data[1] = intr_info;
4018                 return 0;
4019         }
4020
4021         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4022                 return 1;  /* already handled by vmx_vcpu_run() */
4023
4024         if (is_no_device(intr_info)) {
4025                 vmx_fpu_activate(vcpu);
4026                 return 1;
4027         }
4028
4029         if (is_invalid_opcode(intr_info)) {
4030                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4031                 if (er != EMULATE_DONE)
4032                         kvm_queue_exception(vcpu, UD_VECTOR);
4033                 return 1;
4034         }
4035
4036         error_code = 0;
4037         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4038                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4039         if (is_page_fault(intr_info)) {
4040                 /* EPT won't cause page fault directly */
4041                 if (enable_ept)
4042                         BUG();
4043                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4044                 trace_kvm_page_fault(cr2, error_code);
4045
4046                 if (kvm_event_needs_reinjection(vcpu))
4047                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4048                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4049         }
4050
4051         if (vmx->rmode.vm86_active &&
4052             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4053                                                                 error_code)) {
4054                 if (vcpu->arch.halt_request) {
4055                         vcpu->arch.halt_request = 0;
4056                         return kvm_emulate_halt(vcpu);
4057                 }
4058                 return 1;
4059         }
4060
4061         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4062         switch (ex_no) {
4063         case DB_VECTOR:
4064                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4065                 if (!(vcpu->guest_debug &
4066                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4067                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4068                         kvm_queue_exception(vcpu, DB_VECTOR);
4069                         return 1;
4070                 }
4071                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4072                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4073                 /* fall through */
4074         case BP_VECTOR:
4075                 /*
4076                  * Update instruction length as we may reinject #BP from
4077                  * user space while in guest debugging mode. Reading it for
4078                  * #DB as well causes no harm, it is not used in that case.
4079                  */
4080                 vmx->vcpu.arch.event_exit_inst_len =
4081                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4082                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4083                 rip = kvm_rip_read(vcpu);
4084                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4085                 kvm_run->debug.arch.exception = ex_no;
4086                 break;
4087         default:
4088                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4089                 kvm_run->ex.exception = ex_no;
4090                 kvm_run->ex.error_code = error_code;
4091                 break;
4092         }
4093         return 0;
4094 }
4095
4096 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4097 {
4098         ++vcpu->stat.irq_exits;
4099         return 1;
4100 }
4101
4102 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4103 {
4104         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4105         return 0;
4106 }
4107
4108 static int handle_io(struct kvm_vcpu *vcpu)
4109 {
4110         unsigned long exit_qualification;
4111         int size, in, string;
4112         unsigned port;
4113
4114         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4115         string = (exit_qualification & 16) != 0;
4116         in = (exit_qualification & 8) != 0;
4117
4118         ++vcpu->stat.io_exits;
4119
4120         if (string || in)
4121                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4122
4123         port = exit_qualification >> 16;
4124         size = (exit_qualification & 7) + 1;
4125         skip_emulated_instruction(vcpu);
4126
4127         return kvm_fast_pio_out(vcpu, size, port);
4128 }
4129
4130 static void
4131 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4132 {
4133         /*
4134          * Patch in the VMCALL instruction:
4135          */
4136         hypercall[0] = 0x0f;
4137         hypercall[1] = 0x01;
4138         hypercall[2] = 0xc1;
4139 }
4140
4141 static int handle_cr(struct kvm_vcpu *vcpu)
4142 {
4143         unsigned long exit_qualification, val;
4144         int cr;
4145         int reg;
4146         int err;
4147
4148         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4149         cr = exit_qualification & 15;
4150         reg = (exit_qualification >> 8) & 15;
4151         switch ((exit_qualification >> 4) & 3) {
4152         case 0: /* mov to cr */
4153                 val = kvm_register_read(vcpu, reg);
4154                 trace_kvm_cr_write(cr, val);
4155                 switch (cr) {
4156                 case 0:
4157                         err = kvm_set_cr0(vcpu, val);
4158                         kvm_complete_insn_gp(vcpu, err);
4159                         return 1;
4160                 case 3:
4161                         err = kvm_set_cr3(vcpu, val);
4162                         kvm_complete_insn_gp(vcpu, err);
4163                         return 1;
4164                 case 4:
4165                         err = kvm_set_cr4(vcpu, val);
4166                         kvm_complete_insn_gp(vcpu, err);
4167                         return 1;
4168                 case 8: {
4169                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4170                                 u8 cr8 = kvm_register_read(vcpu, reg);
4171                                 err = kvm_set_cr8(vcpu, cr8);
4172                                 kvm_complete_insn_gp(vcpu, err);
4173                                 if (irqchip_in_kernel(vcpu->kvm))
4174                                         return 1;
4175                                 if (cr8_prev <= cr8)
4176                                         return 1;
4177                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4178                                 return 0;
4179                         }
4180                 };
4181                 break;
4182         case 2: /* clts */
4183                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4184                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4185                 skip_emulated_instruction(vcpu);
4186                 vmx_fpu_activate(vcpu);
4187                 return 1;
4188         case 1: /*mov from cr*/
4189                 switch (cr) {
4190                 case 3:
4191                         val = kvm_read_cr3(vcpu);
4192                         kvm_register_write(vcpu, reg, val);
4193                         trace_kvm_cr_read(cr, val);
4194                         skip_emulated_instruction(vcpu);
4195                         return 1;
4196                 case 8:
4197                         val = kvm_get_cr8(vcpu);
4198                         kvm_register_write(vcpu, reg, val);
4199                         trace_kvm_cr_read(cr, val);
4200                         skip_emulated_instruction(vcpu);
4201                         return 1;
4202                 }
4203                 break;
4204         case 3: /* lmsw */
4205                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4206                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4207                 kvm_lmsw(vcpu, val);
4208
4209                 skip_emulated_instruction(vcpu);
4210                 return 1;
4211         default:
4212                 break;
4213         }
4214         vcpu->run->exit_reason = 0;
4215         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4216                (int)(exit_qualification >> 4) & 3, cr);
4217         return 0;
4218 }
4219
4220 static int handle_dr(struct kvm_vcpu *vcpu)
4221 {
4222         unsigned long exit_qualification;
4223         int dr, reg;
4224
4225         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4226         if (!kvm_require_cpl(vcpu, 0))
4227                 return 1;
4228         dr = vmcs_readl(GUEST_DR7);
4229         if (dr & DR7_GD) {
4230                 /*
4231                  * As the vm-exit takes precedence over the debug trap, we
4232                  * need to emulate the latter, either for the host or the
4233                  * guest debugging itself.
4234                  */
4235                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4236                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4237                         vcpu->run->debug.arch.dr7 = dr;
4238                         vcpu->run->debug.arch.pc =
4239                                 vmcs_readl(GUEST_CS_BASE) +
4240                                 vmcs_readl(GUEST_RIP);
4241                         vcpu->run->debug.arch.exception = DB_VECTOR;
4242                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4243                         return 0;
4244                 } else {
4245                         vcpu->arch.dr7 &= ~DR7_GD;
4246                         vcpu->arch.dr6 |= DR6_BD;
4247                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4248                         kvm_queue_exception(vcpu, DB_VECTOR);
4249                         return 1;
4250                 }
4251         }
4252
4253         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4254         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4255         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4256         if (exit_qualification & TYPE_MOV_FROM_DR) {
4257                 unsigned long val;
4258                 if (!kvm_get_dr(vcpu, dr, &val))
4259                         kvm_register_write(vcpu, reg, val);
4260         } else
4261                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4262         skip_emulated_instruction(vcpu);
4263         return 1;
4264 }
4265
4266 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4267 {
4268         vmcs_writel(GUEST_DR7, val);
4269 }
4270
4271 static int handle_cpuid(struct kvm_vcpu *vcpu)
4272 {
4273         kvm_emulate_cpuid(vcpu);
4274         return 1;
4275 }
4276
4277 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4278 {
4279         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4280         u64 data;
4281
4282         if (vmx_get_msr(vcpu, ecx, &data)) {
4283                 trace_kvm_msr_read_ex(ecx);
4284                 kvm_inject_gp(vcpu, 0);
4285                 return 1;
4286         }
4287
4288         trace_kvm_msr_read(ecx, data);
4289
4290         /* FIXME: handling of bits 32:63 of rax, rdx */
4291         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4292         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4293         skip_emulated_instruction(vcpu);
4294         return 1;
4295 }
4296
4297 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4298 {
4299         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4300         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4301                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4302
4303         if (vmx_set_msr(vcpu, ecx, data) != 0) {
4304                 trace_kvm_msr_write_ex(ecx, data);
4305                 kvm_inject_gp(vcpu, 0);
4306                 return 1;
4307         }
4308
4309         trace_kvm_msr_write(ecx, data);
4310         skip_emulated_instruction(vcpu);
4311         return 1;
4312 }
4313
4314 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4315 {
4316         kvm_make_request(KVM_REQ_EVENT, vcpu);
4317         return 1;
4318 }
4319
4320 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4321 {
4322         u32 cpu_based_vm_exec_control;
4323
4324         /* clear pending irq */
4325         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4326         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4327         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4328
4329         kvm_make_request(KVM_REQ_EVENT, vcpu);
4330
4331         ++vcpu->stat.irq_window_exits;
4332
4333         /*
4334          * If the user space waits to inject interrupts, exit as soon as
4335          * possible
4336          */
4337         if (!irqchip_in_kernel(vcpu->kvm) &&
4338             vcpu->run->request_interrupt_window &&
4339             !kvm_cpu_has_interrupt(vcpu)) {
4340                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4341                 return 0;
4342         }
4343         return 1;
4344 }
4345
4346 static int handle_halt(struct kvm_vcpu *vcpu)
4347 {
4348         skip_emulated_instruction(vcpu);
4349         return kvm_emulate_halt(vcpu);
4350 }
4351
4352 static int handle_vmcall(struct kvm_vcpu *vcpu)
4353 {
4354         skip_emulated_instruction(vcpu);
4355         kvm_emulate_hypercall(vcpu);
4356         return 1;
4357 }
4358
4359 static int handle_invd(struct kvm_vcpu *vcpu)
4360 {
4361         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4362 }
4363
4364 static int handle_invlpg(struct kvm_vcpu *vcpu)
4365 {
4366         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4367
4368         kvm_mmu_invlpg(vcpu, exit_qualification);
4369         skip_emulated_instruction(vcpu);
4370         return 1;
4371 }
4372
4373 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4374 {
4375         skip_emulated_instruction(vcpu);
4376         kvm_emulate_wbinvd(vcpu);
4377         return 1;
4378 }
4379
4380 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4381 {
4382         u64 new_bv = kvm_read_edx_eax(vcpu);
4383         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4384
4385         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4386                 skip_emulated_instruction(vcpu);
4387         return 1;
4388 }
4389
4390 static int handle_apic_access(struct kvm_vcpu *vcpu)
4391 {
4392         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4393 }
4394
4395 static int handle_task_switch(struct kvm_vcpu *vcpu)
4396 {
4397         struct vcpu_vmx *vmx = to_vmx(vcpu);
4398         unsigned long exit_qualification;
4399         bool has_error_code = false;
4400         u32 error_code = 0;
4401         u16 tss_selector;
4402         int reason, type, idt_v;
4403
4404         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4405         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4406
4407         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4408
4409         reason = (u32)exit_qualification >> 30;
4410         if (reason == TASK_SWITCH_GATE && idt_v) {
4411                 switch (type) {
4412                 case INTR_TYPE_NMI_INTR:
4413                         vcpu->arch.nmi_injected = false;
4414                         vmx_set_nmi_mask(vcpu, true);
4415                         break;
4416                 case INTR_TYPE_EXT_INTR:
4417                 case INTR_TYPE_SOFT_INTR:
4418                         kvm_clear_interrupt_queue(vcpu);
4419                         break;
4420                 case INTR_TYPE_HARD_EXCEPTION:
4421                         if (vmx->idt_vectoring_info &
4422                             VECTORING_INFO_DELIVER_CODE_MASK) {
4423                                 has_error_code = true;
4424                                 error_code =
4425                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
4426                         }
4427                         /* fall through */
4428                 case INTR_TYPE_SOFT_EXCEPTION:
4429                         kvm_clear_exception_queue(vcpu);
4430                         break;
4431                 default:
4432                         break;
4433                 }
4434         }
4435         tss_selector = exit_qualification;
4436
4437         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4438                        type != INTR_TYPE_EXT_INTR &&
4439                        type != INTR_TYPE_NMI_INTR))
4440                 skip_emulated_instruction(vcpu);
4441
4442         if (kvm_task_switch(vcpu, tss_selector, reason,
4443                                 has_error_code, error_code) == EMULATE_FAIL) {
4444                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4445                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4446                 vcpu->run->internal.ndata = 0;
4447                 return 0;
4448         }
4449
4450         /* clear all local breakpoint enable flags */
4451         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4452
4453         /*
4454          * TODO: What about debug traps on tss switch?
4455          *       Are we supposed to inject them and update dr6?
4456          */
4457
4458         return 1;
4459 }
4460
4461 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4462 {
4463         unsigned long exit_qualification;
4464         gpa_t gpa;
4465         int gla_validity;
4466
4467         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4468
4469         if (exit_qualification & (1 << 6)) {
4470                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4471                 return -EINVAL;
4472         }
4473
4474         gla_validity = (exit_qualification >> 7) & 0x3;
4475         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4476                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4477                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4478                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4479                         vmcs_readl(GUEST_LINEAR_ADDRESS));
4480                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4481                         (long unsigned int)exit_qualification);
4482                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4483                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4484                 return 0;
4485         }
4486
4487         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4488         trace_kvm_page_fault(gpa, exit_qualification);
4489         return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
4490 }
4491
4492 static u64 ept_rsvd_mask(u64 spte, int level)
4493 {
4494         int i;
4495         u64 mask = 0;
4496
4497         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4498                 mask |= (1ULL << i);
4499
4500         if (level > 2)
4501                 /* bits 7:3 reserved */
4502                 mask |= 0xf8;
4503         else if (level == 2) {
4504                 if (spte & (1ULL << 7))
4505                         /* 2MB ref, bits 20:12 reserved */
4506                         mask |= 0x1ff000;
4507                 else
4508                         /* bits 6:3 reserved */
4509                         mask |= 0x78;
4510         }
4511
4512         return mask;
4513 }
4514
4515 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4516                                        int level)
4517 {
4518         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4519
4520         /* 010b (write-only) */
4521         WARN_ON((spte & 0x7) == 0x2);
4522
4523         /* 110b (write/execute) */
4524         WARN_ON((spte & 0x7) == 0x6);
4525
4526         /* 100b (execute-only) and value not supported by logical processor */
4527         if (!cpu_has_vmx_ept_execute_only())
4528                 WARN_ON((spte & 0x7) == 0x4);
4529
4530         /* not 000b */
4531         if ((spte & 0x7)) {
4532                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4533
4534                 if (rsvd_bits != 0) {
4535                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4536                                          __func__, rsvd_bits);
4537                         WARN_ON(1);
4538                 }
4539
4540                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4541                         u64 ept_mem_type = (spte & 0x38) >> 3;
4542
4543                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
4544                             ept_mem_type == 7) {
4545                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4546                                                 __func__, ept_mem_type);
4547                                 WARN_ON(1);
4548                         }
4549                 }
4550         }
4551 }
4552
4553 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4554 {
4555         u64 sptes[4];
4556         int nr_sptes, i;
4557         gpa_t gpa;
4558
4559         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4560
4561         printk(KERN_ERR "EPT: Misconfiguration.\n");
4562         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4563
4564         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4565
4566         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4567                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4568
4569         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4570         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4571
4572         return 0;
4573 }
4574
4575 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4576 {
4577         u32 cpu_based_vm_exec_control;
4578
4579         /* clear pending NMI */
4580         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4581         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4582         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4583         ++vcpu->stat.nmi_window_exits;
4584         kvm_make_request(KVM_REQ_EVENT, vcpu);
4585
4586         return 1;
4587 }
4588
4589 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4590 {
4591         struct vcpu_vmx *vmx = to_vmx(vcpu);
4592         enum emulation_result err = EMULATE_DONE;
4593         int ret = 1;
4594         u32 cpu_exec_ctrl;
4595         bool intr_window_requested;
4596
4597         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4598         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4599
4600         while (!guest_state_valid(vcpu)) {
4601                 if (intr_window_requested
4602                     && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4603                         return handle_interrupt_window(&vmx->vcpu);
4604
4605                 err = emulate_instruction(vcpu, 0);
4606
4607                 if (err == EMULATE_DO_MMIO) {
4608                         ret = 0;
4609                         goto out;
4610                 }
4611
4612                 if (err != EMULATE_DONE)
4613                         return 0;
4614
4615                 if (signal_pending(current))
4616                         goto out;
4617                 if (need_resched())
4618                         schedule();
4619         }
4620
4621         vmx->emulation_required = 0;
4622 out:
4623         return ret;
4624 }
4625
4626 /*
4627  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4628  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4629  */
4630 static int handle_pause(struct kvm_vcpu *vcpu)
4631 {
4632         skip_emulated_instruction(vcpu);
4633         kvm_vcpu_on_spin(vcpu);
4634
4635         return 1;
4636 }
4637
4638 static int handle_invalid_op(struct kvm_vcpu *vcpu)
4639 {
4640         kvm_queue_exception(vcpu, UD_VECTOR);
4641         return 1;
4642 }
4643
4644 /*
4645  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4646  * We could reuse a single VMCS for all the L2 guests, but we also want the
4647  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4648  * allows keeping them loaded on the processor, and in the future will allow
4649  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4650  * every entry if they never change.
4651  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4652  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4653  *
4654  * The following functions allocate and free a vmcs02 in this pool.
4655  */
4656
4657 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4658 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4659 {
4660         struct vmcs02_list *item;
4661         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4662                 if (item->vmptr == vmx->nested.current_vmptr) {
4663                         list_move(&item->list, &vmx->nested.vmcs02_pool);
4664                         return &item->vmcs02;
4665                 }
4666
4667         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4668                 /* Recycle the least recently used VMCS. */
4669                 item = list_entry(vmx->nested.vmcs02_pool.prev,
4670                         struct vmcs02_list, list);
4671                 item->vmptr = vmx->nested.current_vmptr;
4672                 list_move(&item->list, &vmx->nested.vmcs02_pool);
4673                 return &item->vmcs02;
4674         }
4675
4676         /* Create a new VMCS */
4677         item = (struct vmcs02_list *)
4678                 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4679         if (!item)
4680                 return NULL;
4681         item->vmcs02.vmcs = alloc_vmcs();
4682         if (!item->vmcs02.vmcs) {
4683                 kfree(item);
4684                 return NULL;
4685         }
4686         loaded_vmcs_init(&item->vmcs02);
4687         item->vmptr = vmx->nested.current_vmptr;
4688         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4689         vmx->nested.vmcs02_num++;
4690         return &item->vmcs02;
4691 }
4692
4693 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4694 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4695 {
4696         struct vmcs02_list *item;
4697         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4698                 if (item->vmptr == vmptr) {
4699                         free_loaded_vmcs(&item->vmcs02);
4700                         list_del(&item->list);
4701                         kfree(item);
4702                         vmx->nested.vmcs02_num--;
4703                         return;
4704                 }
4705 }
4706
4707 /*
4708  * Free all VMCSs saved for this vcpu, except the one pointed by
4709  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4710  * currently used, if running L2), and vmcs01 when running L2.
4711  */
4712 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4713 {
4714         struct vmcs02_list *item, *n;
4715         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4716                 if (vmx->loaded_vmcs != &item->vmcs02)
4717                         free_loaded_vmcs(&item->vmcs02);
4718                 list_del(&item->list);
4719                 kfree(item);
4720         }
4721         vmx->nested.vmcs02_num = 0;
4722
4723         if (vmx->loaded_vmcs != &vmx->vmcs01)
4724                 free_loaded_vmcs(&vmx->vmcs01);
4725 }
4726
4727 /*
4728  * Emulate the VMXON instruction.
4729  * Currently, we just remember that VMX is active, and do not save or even
4730  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4731  * do not currently need to store anything in that guest-allocated memory
4732  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
4733  * argument is different from the VMXON pointer (which the spec says they do).
4734  */
4735 static int handle_vmon(struct kvm_vcpu *vcpu)
4736 {
4737         struct kvm_segment cs;
4738         struct vcpu_vmx *vmx = to_vmx(vcpu);
4739
4740         /* The Intel VMX Instruction Reference lists a bunch of bits that
4741          * are prerequisite to running VMXON, most notably cr4.VMXE must be
4742          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
4743          * Otherwise, we should fail with #UD. We test these now:
4744          */
4745         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
4746             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
4747             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4748                 kvm_queue_exception(vcpu, UD_VECTOR);
4749                 return 1;
4750         }
4751
4752         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4753         if (is_long_mode(vcpu) && !cs.l) {
4754                 kvm_queue_exception(vcpu, UD_VECTOR);
4755                 return 1;
4756         }
4757
4758         if (vmx_get_cpl(vcpu)) {
4759                 kvm_inject_gp(vcpu, 0);
4760                 return 1;
4761         }
4762
4763         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
4764         vmx->nested.vmcs02_num = 0;
4765
4766         vmx->nested.vmxon = true;
4767
4768         skip_emulated_instruction(vcpu);
4769         return 1;
4770 }
4771
4772 /*
4773  * Intel's VMX Instruction Reference specifies a common set of prerequisites
4774  * for running VMX instructions (except VMXON, whose prerequisites are
4775  * slightly different). It also specifies what exception to inject otherwise.
4776  */
4777 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
4778 {
4779         struct kvm_segment cs;
4780         struct vcpu_vmx *vmx = to_vmx(vcpu);
4781
4782         if (!vmx->nested.vmxon) {
4783                 kvm_queue_exception(vcpu, UD_VECTOR);
4784                 return 0;
4785         }
4786
4787         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4788         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
4789             (is_long_mode(vcpu) && !cs.l)) {
4790                 kvm_queue_exception(vcpu, UD_VECTOR);
4791                 return 0;
4792         }
4793
4794         if (vmx_get_cpl(vcpu)) {
4795                 kvm_inject_gp(vcpu, 0);
4796                 return 0;
4797         }
4798
4799         return 1;
4800 }
4801
4802 /*
4803  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
4804  * just stops using VMX.
4805  */
4806 static void free_nested(struct vcpu_vmx *vmx)
4807 {
4808         if (!vmx->nested.vmxon)
4809                 return;
4810         vmx->nested.vmxon = false;
4811         if (vmx->nested.current_vmptr != -1ull) {
4812                 kunmap(vmx->nested.current_vmcs12_page);
4813                 nested_release_page(vmx->nested.current_vmcs12_page);
4814                 vmx->nested.current_vmptr = -1ull;
4815                 vmx->nested.current_vmcs12 = NULL;
4816         }
4817         /* Unpin physical memory we referred to in current vmcs02 */
4818         if (vmx->nested.apic_access_page) {
4819                 nested_release_page(vmx->nested.apic_access_page);
4820                 vmx->nested.apic_access_page = 0;
4821         }
4822
4823         nested_free_all_saved_vmcss(vmx);
4824 }
4825
4826 /* Emulate the VMXOFF instruction */
4827 static int handle_vmoff(struct kvm_vcpu *vcpu)
4828 {
4829         if (!nested_vmx_check_permission(vcpu))
4830                 return 1;
4831         free_nested(to_vmx(vcpu));
4832         skip_emulated_instruction(vcpu);
4833         return 1;
4834 }
4835
4836 /*
4837  * Decode the memory-address operand of a vmx instruction, as recorded on an
4838  * exit caused by such an instruction (run by a guest hypervisor).
4839  * On success, returns 0. When the operand is invalid, returns 1 and throws
4840  * #UD or #GP.
4841  */
4842 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
4843                                  unsigned long exit_qualification,
4844                                  u32 vmx_instruction_info, gva_t *ret)
4845 {
4846         /*
4847          * According to Vol. 3B, "Information for VM Exits Due to Instruction
4848          * Execution", on an exit, vmx_instruction_info holds most of the
4849          * addressing components of the operand. Only the displacement part
4850          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
4851          * For how an actual address is calculated from all these components,
4852          * refer to Vol. 1, "Operand Addressing".
4853          */
4854         int  scaling = vmx_instruction_info & 3;
4855         int  addr_size = (vmx_instruction_info >> 7) & 7;
4856         bool is_reg = vmx_instruction_info & (1u << 10);
4857         int  seg_reg = (vmx_instruction_info >> 15) & 7;
4858         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
4859         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
4860         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
4861         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
4862
4863         if (is_reg) {
4864                 kvm_queue_exception(vcpu, UD_VECTOR);
4865                 return 1;
4866         }
4867
4868         /* Addr = segment_base + offset */
4869         /* offset = base + [index * scale] + displacement */
4870         *ret = vmx_get_segment_base(vcpu, seg_reg);
4871         if (base_is_valid)
4872                 *ret += kvm_register_read(vcpu, base_reg);
4873         if (index_is_valid)
4874                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
4875         *ret += exit_qualification; /* holds the displacement */
4876
4877         if (addr_size == 1) /* 32 bit */
4878                 *ret &= 0xffffffff;
4879
4880         /*
4881          * TODO: throw #GP (and return 1) in various cases that the VM*
4882          * instructions require it - e.g., offset beyond segment limit,
4883          * unusable or unreadable/unwritable segment, non-canonical 64-bit
4884          * address, and so on. Currently these are not checked.
4885          */
4886         return 0;
4887 }
4888
4889 /*
4890  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
4891  * set the success or error code of an emulated VMX instruction, as specified
4892  * by Vol 2B, VMX Instruction Reference, "Conventions".
4893  */
4894 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
4895 {
4896         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
4897                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
4898                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
4899 }
4900
4901 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
4902 {
4903         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
4904                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
4905                             X86_EFLAGS_SF | X86_EFLAGS_OF))
4906                         | X86_EFLAGS_CF);
4907 }
4908
4909 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
4910                                         u32 vm_instruction_error)
4911 {
4912         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
4913                 /*
4914                  * failValid writes the error number to the current VMCS, which
4915                  * can't be done there isn't a current VMCS.
4916                  */
4917                 nested_vmx_failInvalid(vcpu);
4918                 return;
4919         }
4920         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
4921                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
4922                             X86_EFLAGS_SF | X86_EFLAGS_OF))
4923                         | X86_EFLAGS_ZF);
4924         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
4925 }
4926
4927 /* Emulate the VMCLEAR instruction */
4928 static int handle_vmclear(struct kvm_vcpu *vcpu)
4929 {
4930         struct vcpu_vmx *vmx = to_vmx(vcpu);
4931         gva_t gva;
4932         gpa_t vmptr;
4933         struct vmcs12 *vmcs12;
4934         struct page *page;
4935         struct x86_exception e;
4936
4937         if (!nested_vmx_check_permission(vcpu))
4938                 return 1;
4939
4940         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
4941                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
4942                 return 1;
4943
4944         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
4945                                 sizeof(vmptr), &e)) {
4946                 kvm_inject_page_fault(vcpu, &e);
4947                 return 1;
4948         }
4949
4950         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
4951                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
4952                 skip_emulated_instruction(vcpu);
4953                 return 1;
4954         }
4955
4956         if (vmptr == vmx->nested.current_vmptr) {
4957                 kunmap(vmx->nested.current_vmcs12_page);
4958                 nested_release_page(vmx->nested.current_vmcs12_page);
4959                 vmx->nested.current_vmptr = -1ull;
4960                 vmx->nested.current_vmcs12 = NULL;
4961         }
4962
4963         page = nested_get_page(vcpu, vmptr);
4964         if (page == NULL) {
4965                 /*
4966                  * For accurate processor emulation, VMCLEAR beyond available
4967                  * physical memory should do nothing at all. However, it is
4968                  * possible that a nested vmx bug, not a guest hypervisor bug,
4969                  * resulted in this case, so let's shut down before doing any
4970                  * more damage:
4971                  */
4972                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4973                 return 1;
4974         }
4975         vmcs12 = kmap(page);
4976         vmcs12->launch_state = 0;
4977         kunmap(page);
4978         nested_release_page(page);
4979
4980         nested_free_vmcs02(vmx, vmptr);
4981
4982         skip_emulated_instruction(vcpu);
4983         nested_vmx_succeed(vcpu);
4984         return 1;
4985 }
4986
4987 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
4988
4989 /* Emulate the VMLAUNCH instruction */
4990 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
4991 {
4992         return nested_vmx_run(vcpu, true);
4993 }
4994
4995 /* Emulate the VMRESUME instruction */
4996 static int handle_vmresume(struct kvm_vcpu *vcpu)
4997 {
4998
4999         return nested_vmx_run(vcpu, false);
5000 }
5001
5002 enum vmcs_field_type {
5003         VMCS_FIELD_TYPE_U16 = 0,
5004         VMCS_FIELD_TYPE_U64 = 1,
5005         VMCS_FIELD_TYPE_U32 = 2,
5006         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5007 };
5008
5009 static inline int vmcs_field_type(unsigned long field)
5010 {
5011         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5012                 return VMCS_FIELD_TYPE_U32;
5013         return (field >> 13) & 0x3 ;
5014 }
5015
5016 static inline int vmcs_field_readonly(unsigned long field)
5017 {
5018         return (((field >> 10) & 0x3) == 1);
5019 }
5020
5021 /*
5022  * Read a vmcs12 field. Since these can have varying lengths and we return
5023  * one type, we chose the biggest type (u64) and zero-extend the return value
5024  * to that size. Note that the caller, handle_vmread, might need to use only
5025  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5026  * 64-bit fields are to be returned).
5027  */
5028 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5029                                         unsigned long field, u64 *ret)
5030 {
5031         short offset = vmcs_field_to_offset(field);
5032         char *p;
5033
5034         if (offset < 0)
5035                 return 0;
5036
5037         p = ((char *)(get_vmcs12(vcpu))) + offset;
5038
5039         switch (vmcs_field_type(field)) {
5040         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5041                 *ret = *((natural_width *)p);
5042                 return 1;
5043         case VMCS_FIELD_TYPE_U16:
5044                 *ret = *((u16 *)p);
5045                 return 1;
5046         case VMCS_FIELD_TYPE_U32:
5047                 *ret = *((u32 *)p);
5048                 return 1;
5049         case VMCS_FIELD_TYPE_U64:
5050                 *ret = *((u64 *)p);
5051                 return 1;
5052         default:
5053                 return 0; /* can never happen. */
5054         }
5055 }
5056
5057 /*
5058  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5059  * used before) all generate the same failure when it is missing.
5060  */
5061 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5062 {
5063         struct vcpu_vmx *vmx = to_vmx(vcpu);
5064         if (vmx->nested.current_vmptr == -1ull) {
5065                 nested_vmx_failInvalid(vcpu);
5066                 skip_emulated_instruction(vcpu);
5067                 return 0;
5068         }
5069         return 1;
5070 }
5071
5072 static int handle_vmread(struct kvm_vcpu *vcpu)
5073 {
5074         unsigned long field;
5075         u64 field_value;
5076         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5077         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5078         gva_t gva = 0;
5079
5080         if (!nested_vmx_check_permission(vcpu) ||
5081             !nested_vmx_check_vmcs12(vcpu))
5082                 return 1;
5083
5084         /* Decode instruction info and find the field to read */
5085         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5086         /* Read the field, zero-extended to a u64 field_value */
5087         if (!vmcs12_read_any(vcpu, field, &field_value)) {
5088                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5089                 skip_emulated_instruction(vcpu);
5090                 return 1;
5091         }
5092         /*
5093          * Now copy part of this value to register or memory, as requested.
5094          * Note that the number of bits actually copied is 32 or 64 depending
5095          * on the guest's mode (32 or 64 bit), not on the given field's length.
5096          */
5097         if (vmx_instruction_info & (1u << 10)) {
5098                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5099                         field_value);
5100         } else {
5101                 if (get_vmx_mem_address(vcpu, exit_qualification,
5102                                 vmx_instruction_info, &gva))
5103                         return 1;
5104                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5105                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5106                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5107         }
5108
5109         nested_vmx_succeed(vcpu);
5110         skip_emulated_instruction(vcpu);
5111         return 1;
5112 }
5113
5114
5115 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5116 {
5117         unsigned long field;
5118         gva_t gva;
5119         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5120         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5121         char *p;
5122         short offset;
5123         /* The value to write might be 32 or 64 bits, depending on L1's long
5124          * mode, and eventually we need to write that into a field of several
5125          * possible lengths. The code below first zero-extends the value to 64
5126          * bit (field_value), and then copies only the approriate number of
5127          * bits into the vmcs12 field.
5128          */
5129         u64 field_value = 0;
5130         struct x86_exception e;
5131
5132         if (!nested_vmx_check_permission(vcpu) ||
5133             !nested_vmx_check_vmcs12(vcpu))
5134                 return 1;
5135
5136         if (vmx_instruction_info & (1u << 10))
5137                 field_value = kvm_register_read(vcpu,
5138                         (((vmx_instruction_info) >> 3) & 0xf));
5139         else {
5140                 if (get_vmx_mem_address(vcpu, exit_qualification,
5141                                 vmx_instruction_info, &gva))
5142                         return 1;
5143                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5144                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5145                         kvm_inject_page_fault(vcpu, &e);
5146                         return 1;
5147                 }
5148         }
5149
5150
5151         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5152         if (vmcs_field_readonly(field)) {
5153                 nested_vmx_failValid(vcpu,
5154                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5155                 skip_emulated_instruction(vcpu);
5156                 return 1;
5157         }
5158
5159         offset = vmcs_field_to_offset(field);
5160         if (offset < 0) {
5161                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5162                 skip_emulated_instruction(vcpu);
5163                 return 1;
5164         }
5165         p = ((char *) get_vmcs12(vcpu)) + offset;
5166
5167         switch (vmcs_field_type(field)) {
5168         case VMCS_FIELD_TYPE_U16:
5169                 *(u16 *)p = field_value;
5170                 break;
5171         case VMCS_FIELD_TYPE_U32:
5172                 *(u32 *)p = field_value;
5173                 break;
5174         case VMCS_FIELD_TYPE_U64:
5175                 *(u64 *)p = field_value;
5176                 break;
5177         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5178                 *(natural_width *)p = field_value;
5179                 break;
5180         default:
5181                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5182                 skip_emulated_instruction(vcpu);
5183                 return 1;
5184         }
5185
5186         nested_vmx_succeed(vcpu);
5187         skip_emulated_instruction(vcpu);
5188         return 1;
5189 }
5190
5191 /* Emulate the VMPTRLD instruction */
5192 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5193 {
5194         struct vcpu_vmx *vmx = to_vmx(vcpu);
5195         gva_t gva;
5196         gpa_t vmptr;
5197         struct x86_exception e;
5198
5199         if (!nested_vmx_check_permission(vcpu))
5200                 return 1;
5201
5202         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5203                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5204                 return 1;
5205
5206         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5207                                 sizeof(vmptr), &e)) {
5208                 kvm_inject_page_fault(vcpu, &e);
5209                 return 1;
5210         }
5211
5212         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5213                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5214                 skip_emulated_instruction(vcpu);
5215                 return 1;
5216         }
5217
5218         if (vmx->nested.current_vmptr != vmptr) {
5219                 struct vmcs12 *new_vmcs12;
5220                 struct page *page;
5221                 page = nested_get_page(vcpu, vmptr);
5222                 if (page == NULL) {
5223                         nested_vmx_failInvalid(vcpu);
5224                         skip_emulated_instruction(vcpu);
5225                         return 1;
5226                 }
5227                 new_vmcs12 = kmap(page);
5228                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5229                         kunmap(page);
5230                         nested_release_page_clean(page);
5231                         nested_vmx_failValid(vcpu,
5232                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5233                         skip_emulated_instruction(vcpu);
5234                         return 1;
5235                 }
5236                 if (vmx->nested.current_vmptr != -1ull) {
5237                         kunmap(vmx->nested.current_vmcs12_page);
5238                         nested_release_page(vmx->nested.current_vmcs12_page);
5239                 }
5240
5241                 vmx->nested.current_vmptr = vmptr;
5242                 vmx->nested.current_vmcs12 = new_vmcs12;
5243                 vmx->nested.current_vmcs12_page = page;
5244         }
5245
5246         nested_vmx_succeed(vcpu);
5247         skip_emulated_instruction(vcpu);
5248         return 1;
5249 }
5250
5251 /* Emulate the VMPTRST instruction */
5252 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5253 {
5254         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5255         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5256         gva_t vmcs_gva;
5257         struct x86_exception e;
5258
5259         if (!nested_vmx_check_permission(vcpu))
5260                 return 1;
5261
5262         if (get_vmx_mem_address(vcpu, exit_qualification,
5263                         vmx_instruction_info, &vmcs_gva))
5264                 return 1;
5265         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5266         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5267                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
5268                                  sizeof(u64), &e)) {
5269                 kvm_inject_page_fault(vcpu, &e);
5270                 return 1;
5271         }
5272         nested_vmx_succeed(vcpu);
5273         skip_emulated_instruction(vcpu);
5274         return 1;
5275 }
5276
5277 /*
5278  * The exit handlers return 1 if the exit was handled fully and guest execution
5279  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5280  * to be done to userspace and return 0.
5281  */
5282 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5283         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
5284         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5285         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5286         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5287         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5288         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5289         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5290         [EXIT_REASON_CPUID]                   = handle_cpuid,
5291         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5292         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5293         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5294         [EXIT_REASON_HLT]                     = handle_halt,
5295         [EXIT_REASON_INVD]                    = handle_invd,
5296         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5297         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5298         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
5299         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
5300         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
5301         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
5302         [EXIT_REASON_VMREAD]                  = handle_vmread,
5303         [EXIT_REASON_VMRESUME]                = handle_vmresume,
5304         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
5305         [EXIT_REASON_VMOFF]                   = handle_vmoff,
5306         [EXIT_REASON_VMON]                    = handle_vmon,
5307         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5308         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5309         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5310         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5311         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5312         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5313         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5314         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5315         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5316         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
5317         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
5318 };
5319
5320 static const int kvm_vmx_max_exit_handlers =
5321         ARRAY_SIZE(kvm_vmx_exit_handlers);
5322
5323 /*
5324  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5325  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5326  * disinterest in the current event (read or write a specific MSR) by using an
5327  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5328  */
5329 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5330         struct vmcs12 *vmcs12, u32 exit_reason)
5331 {
5332         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5333         gpa_t bitmap;
5334
5335         if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5336                 return 1;
5337
5338         /*
5339          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5340          * for the four combinations of read/write and low/high MSR numbers.
5341          * First we need to figure out which of the four to use:
5342          */
5343         bitmap = vmcs12->msr_bitmap;
5344         if (exit_reason == EXIT_REASON_MSR_WRITE)
5345                 bitmap += 2048;
5346         if (msr_index >= 0xc0000000) {
5347                 msr_index -= 0xc0000000;
5348                 bitmap += 1024;
5349         }
5350
5351         /* Then read the msr_index'th bit from this bitmap: */
5352         if (msr_index < 1024*8) {
5353                 unsigned char b;
5354                 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5355                 return 1 & (b >> (msr_index & 7));
5356         } else
5357                 return 1; /* let L1 handle the wrong parameter */
5358 }
5359
5360 /*
5361  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5362  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5363  * intercept (via guest_host_mask etc.) the current event.
5364  */
5365 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5366         struct vmcs12 *vmcs12)
5367 {
5368         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5369         int cr = exit_qualification & 15;
5370         int reg = (exit_qualification >> 8) & 15;
5371         unsigned long val = kvm_register_read(vcpu, reg);
5372
5373         switch ((exit_qualification >> 4) & 3) {
5374         case 0: /* mov to cr */
5375                 switch (cr) {
5376                 case 0:
5377                         if (vmcs12->cr0_guest_host_mask &
5378                             (val ^ vmcs12->cr0_read_shadow))
5379                                 return 1;
5380                         break;
5381                 case 3:
5382                         if ((vmcs12->cr3_target_count >= 1 &&
5383                                         vmcs12->cr3_target_value0 == val) ||
5384                                 (vmcs12->cr3_target_count >= 2 &&
5385                                         vmcs12->cr3_target_value1 == val) ||
5386                                 (vmcs12->cr3_target_count >= 3 &&
5387                                         vmcs12->cr3_target_value2 == val) ||
5388                                 (vmcs12->cr3_target_count >= 4 &&
5389                                         vmcs12->cr3_target_value3 == val))
5390                                 return 0;
5391                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5392                                 return 1;
5393                         break;
5394                 case 4:
5395                         if (vmcs12->cr4_guest_host_mask &
5396                             (vmcs12->cr4_read_shadow ^ val))
5397                                 return 1;
5398                         break;
5399                 case 8:
5400                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5401                                 return 1;
5402                         break;
5403                 }
5404                 break;
5405         case 2: /* clts */
5406                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5407                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
5408                         return 1;
5409                 break;
5410         case 1: /* mov from cr */
5411                 switch (cr) {
5412                 case 3:
5413                         if (vmcs12->cpu_based_vm_exec_control &
5414                             CPU_BASED_CR3_STORE_EXITING)
5415                                 return 1;
5416                         break;
5417                 case 8:
5418                         if (vmcs12->cpu_based_vm_exec_control &
5419                             CPU_BASED_CR8_STORE_EXITING)
5420                                 return 1;
5421                         break;
5422                 }
5423                 break;
5424         case 3: /* lmsw */
5425                 /*
5426                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5427                  * cr0. Other attempted changes are ignored, with no exit.
5428                  */
5429                 if (vmcs12->cr0_guest_host_mask & 0xe &
5430                     (val ^ vmcs12->cr0_read_shadow))
5431                         return 1;
5432                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5433                     !(vmcs12->cr0_read_shadow & 0x1) &&
5434                     (val & 0x1))
5435                         return 1;
5436                 break;
5437         }
5438         return 0;
5439 }
5440
5441 /*
5442  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5443  * should handle it ourselves in L0 (and then continue L2). Only call this
5444  * when in is_guest_mode (L2).
5445  */
5446 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5447 {
5448         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5449         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5450         struct vcpu_vmx *vmx = to_vmx(vcpu);
5451         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5452
5453         if (vmx->nested.nested_run_pending)
5454                 return 0;
5455
5456         if (unlikely(vmx->fail)) {
5457                 printk(KERN_INFO "%s failed vm entry %x\n",
5458                        __func__, vmcs_read32(VM_INSTRUCTION_ERROR));
5459                 return 1;
5460         }
5461
5462         switch (exit_reason) {
5463         case EXIT_REASON_EXCEPTION_NMI:
5464                 if (!is_exception(intr_info))
5465                         return 0;
5466                 else if (is_page_fault(intr_info))
5467                         return enable_ept;
5468                 return vmcs12->exception_bitmap &
5469                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5470         case EXIT_REASON_EXTERNAL_INTERRUPT:
5471                 return 0;
5472         case EXIT_REASON_TRIPLE_FAULT:
5473                 return 1;
5474         case EXIT_REASON_PENDING_INTERRUPT:
5475         case EXIT_REASON_NMI_WINDOW:
5476                 /*
5477                  * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5478                  * (aka Interrupt Window Exiting) only when L1 turned it on,
5479                  * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5480                  * Same for NMI Window Exiting.
5481                  */
5482                 return 1;
5483         case EXIT_REASON_TASK_SWITCH:
5484                 return 1;
5485         case EXIT_REASON_CPUID:
5486                 return 1;
5487         case EXIT_REASON_HLT:
5488                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5489         case EXIT_REASON_INVD:
5490                 return 1;
5491         case EXIT_REASON_INVLPG:
5492                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5493         case EXIT_REASON_RDPMC:
5494                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5495         case EXIT_REASON_RDTSC:
5496                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5497         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5498         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5499         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5500         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5501         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5502                 /*
5503                  * VMX instructions trap unconditionally. This allows L1 to
5504                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
5505                  */
5506                 return 1;
5507         case EXIT_REASON_CR_ACCESS:
5508                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5509         case EXIT_REASON_DR_ACCESS:
5510                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5511         case EXIT_REASON_IO_INSTRUCTION:
5512                 /* TODO: support IO bitmaps */
5513                 return 1;
5514         case EXIT_REASON_MSR_READ:
5515         case EXIT_REASON_MSR_WRITE:
5516                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5517         case EXIT_REASON_INVALID_STATE:
5518                 return 1;
5519         case EXIT_REASON_MWAIT_INSTRUCTION:
5520                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5521         case EXIT_REASON_MONITOR_INSTRUCTION:
5522                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5523         case EXIT_REASON_PAUSE_INSTRUCTION:
5524                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5525                         nested_cpu_has2(vmcs12,
5526                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5527         case EXIT_REASON_MCE_DURING_VMENTRY:
5528                 return 0;
5529         case EXIT_REASON_TPR_BELOW_THRESHOLD:
5530                 return 1;
5531         case EXIT_REASON_APIC_ACCESS:
5532                 return nested_cpu_has2(vmcs12,
5533                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5534         case EXIT_REASON_EPT_VIOLATION:
5535         case EXIT_REASON_EPT_MISCONFIG:
5536                 return 0;
5537         case EXIT_REASON_WBINVD:
5538                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5539         case EXIT_REASON_XSETBV:
5540                 return 1;
5541         default:
5542                 return 1;
5543         }
5544 }
5545
5546 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5547 {
5548         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5549         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5550 }
5551
5552 /*
5553  * The guest has exited.  See if we can fix it or if we need userspace
5554  * assistance.
5555  */
5556 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5557 {
5558         struct vcpu_vmx *vmx = to_vmx(vcpu);
5559         u32 exit_reason = vmx->exit_reason;
5560         u32 vectoring_info = vmx->idt_vectoring_info;
5561
5562         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5563
5564         /* If guest state is invalid, start emulating */
5565         if (vmx->emulation_required && emulate_invalid_guest_state)
5566                 return handle_invalid_guest_state(vcpu);
5567
5568         /*
5569          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5570          * we did not inject a still-pending event to L1 now because of
5571          * nested_run_pending, we need to re-enable this bit.
5572          */
5573         if (vmx->nested.nested_run_pending)
5574                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5575
5576         if (exit_reason == EXIT_REASON_VMLAUNCH ||
5577             exit_reason == EXIT_REASON_VMRESUME)
5578                 vmx->nested.nested_run_pending = 1;
5579         else
5580                 vmx->nested.nested_run_pending = 0;
5581
5582         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5583                 nested_vmx_vmexit(vcpu);
5584                 return 1;
5585         }
5586
5587         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5588                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5589                 vcpu->run->fail_entry.hardware_entry_failure_reason
5590                         = exit_reason;
5591                 return 0;
5592         }
5593
5594         if (unlikely(vmx->fail)) {
5595                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5596                 vcpu->run->fail_entry.hardware_entry_failure_reason
5597                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5598                 return 0;
5599         }
5600
5601         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5602                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5603                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5604                         exit_reason != EXIT_REASON_TASK_SWITCH))
5605                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5606                        "(0x%x) and exit reason is 0x%x\n",
5607                        __func__, vectoring_info, exit_reason);
5608
5609         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5610             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5611                                         get_vmcs12(vcpu), vcpu)))) {
5612                 if (vmx_interrupt_allowed(vcpu)) {
5613                         vmx->soft_vnmi_blocked = 0;
5614                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
5615                            vcpu->arch.nmi_pending) {
5616                         /*
5617                          * This CPU don't support us in finding the end of an
5618                          * NMI-blocked window if the guest runs with IRQs
5619                          * disabled. So we pull the trigger after 1 s of
5620                          * futile waiting, but inform the user about this.
5621                          */
5622                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5623                                "state on VCPU %d after 1 s timeout\n",
5624                                __func__, vcpu->vcpu_id);
5625                         vmx->soft_vnmi_blocked = 0;
5626                 }
5627         }
5628
5629         if (exit_reason < kvm_vmx_max_exit_handlers
5630             && kvm_vmx_exit_handlers[exit_reason])
5631                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5632         else {
5633                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5634                 vcpu->run->hw.hardware_exit_reason = exit_reason;
5635         }
5636         return 0;
5637 }
5638
5639 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5640 {
5641         if (irr == -1 || tpr < irr) {
5642                 vmcs_write32(TPR_THRESHOLD, 0);
5643                 return;
5644         }
5645
5646         vmcs_write32(TPR_THRESHOLD, irr);
5647 }
5648
5649 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
5650 {
5651         u32 exit_intr_info;
5652
5653         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5654               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5655                 return;
5656
5657         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5658         exit_intr_info = vmx->exit_intr_info;
5659
5660         /* Handle machine checks before interrupts are enabled */
5661         if (is_machine_check(exit_intr_info))
5662                 kvm_machine_check();
5663
5664         /* We need to handle NMIs before interrupts are enabled */
5665         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
5666             (exit_intr_info & INTR_INFO_VALID_MASK)) {
5667                 kvm_before_handle_nmi(&vmx->vcpu);
5668                 asm("int $2");
5669                 kvm_after_handle_nmi(&vmx->vcpu);
5670         }
5671 }
5672
5673 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5674 {
5675         u32 exit_intr_info;
5676         bool unblock_nmi;
5677         u8 vector;
5678         bool idtv_info_valid;
5679
5680         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5681
5682         if (cpu_has_virtual_nmis()) {
5683                 if (vmx->nmi_known_unmasked)
5684                         return;
5685                 /*
5686                  * Can't use vmx->exit_intr_info since we're not sure what
5687                  * the exit reason is.
5688                  */
5689                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5690                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5691                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5692                 /*
5693                  * SDM 3: 27.7.1.2 (September 2008)
5694                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
5695                  * a guest IRET fault.
5696                  * SDM 3: 23.2.2 (September 2008)
5697                  * Bit 12 is undefined in any of the following cases:
5698                  *  If the VM exit sets the valid bit in the IDT-vectoring
5699                  *   information field.
5700                  *  If the VM exit is due to a double fault.
5701                  */
5702                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5703                     vector != DF_VECTOR && !idtv_info_valid)
5704                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5705                                       GUEST_INTR_STATE_NMI);
5706                 else
5707                         vmx->nmi_known_unmasked =
5708                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5709                                   & GUEST_INTR_STATE_NMI);
5710         } else if (unlikely(vmx->soft_vnmi_blocked))
5711                 vmx->vnmi_blocked_time +=
5712                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
5713 }
5714
5715 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5716                                       u32 idt_vectoring_info,
5717                                       int instr_len_field,
5718                                       int error_code_field)
5719 {
5720         u8 vector;
5721         int type;
5722         bool idtv_info_valid;
5723
5724         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5725
5726         vmx->vcpu.arch.nmi_injected = false;
5727         kvm_clear_exception_queue(&vmx->vcpu);
5728         kvm_clear_interrupt_queue(&vmx->vcpu);
5729
5730         if (!idtv_info_valid)
5731                 return;
5732
5733         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5734
5735         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
5736         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
5737
5738         switch (type) {
5739         case INTR_TYPE_NMI_INTR:
5740                 vmx->vcpu.arch.nmi_injected = true;
5741                 /*
5742                  * SDM 3: 27.7.1.2 (September 2008)
5743                  * Clear bit "block by NMI" before VM entry if a NMI
5744                  * delivery faulted.
5745                  */
5746                 vmx_set_nmi_mask(&vmx->vcpu, false);
5747                 break;
5748         case INTR_TYPE_SOFT_EXCEPTION:
5749                 vmx->vcpu.arch.event_exit_inst_len =
5750                         vmcs_read32(instr_len_field);
5751                 /* fall through */
5752         case INTR_TYPE_HARD_EXCEPTION:
5753                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
5754                         u32 err = vmcs_read32(error_code_field);
5755                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
5756                 } else
5757                         kvm_queue_exception(&vmx->vcpu, vector);
5758                 break;
5759         case INTR_TYPE_SOFT_INTR:
5760                 vmx->vcpu.arch.event_exit_inst_len =
5761                         vmcs_read32(instr_len_field);
5762                 /* fall through */
5763         case INTR_TYPE_EXT_INTR:
5764                 kvm_queue_interrupt(&vmx->vcpu, vector,
5765                         type == INTR_TYPE_SOFT_INTR);
5766                 break;
5767         default:
5768                 break;
5769         }
5770 }
5771
5772 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
5773 {
5774         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
5775                                   VM_EXIT_INSTRUCTION_LEN,
5776                                   IDT_VECTORING_ERROR_CODE);
5777 }
5778
5779 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
5780 {
5781         __vmx_complete_interrupts(to_vmx(vcpu),
5782                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5783                                   VM_ENTRY_INSTRUCTION_LEN,
5784                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
5785
5786         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
5787 }
5788
5789 #ifdef CONFIG_X86_64
5790 #define R "r"
5791 #define Q "q"
5792 #else
5793 #define R "e"
5794 #define Q "l"
5795 #endif
5796
5797 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
5798 {
5799         struct vcpu_vmx *vmx = to_vmx(vcpu);
5800
5801         /* Record the guest's net vcpu time for enforced NMI injections. */
5802         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
5803                 vmx->entry_time = ktime_get();
5804
5805         /* Don't enter VMX if guest state is invalid, let the exit handler
5806            start emulation until we arrive back to a valid state */
5807         if (vmx->emulation_required && emulate_invalid_guest_state)
5808                 return;
5809
5810         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
5811                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
5812         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
5813                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
5814
5815         /* When single-stepping over STI and MOV SS, we must clear the
5816          * corresponding interruptibility bits in the guest state. Otherwise
5817          * vmentry fails as it then expects bit 14 (BS) in pending debug
5818          * exceptions being set, but that's not correct for the guest debugging
5819          * case. */
5820         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5821                 vmx_set_interrupt_shadow(vcpu, 0);
5822
5823         vmx->__launched = vmx->loaded_vmcs->launched;
5824         asm(
5825                 /* Store host registers */
5826                 "push %%"R"dx; push %%"R"bp;"
5827                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
5828                 "push %%"R"cx \n\t"
5829                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
5830                 "je 1f \n\t"
5831                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
5832                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
5833                 "1: \n\t"
5834                 /* Reload cr2 if changed */
5835                 "mov %c[cr2](%0), %%"R"ax \n\t"
5836                 "mov %%cr2, %%"R"dx \n\t"
5837                 "cmp %%"R"ax, %%"R"dx \n\t"
5838                 "je 2f \n\t"
5839                 "mov %%"R"ax, %%cr2 \n\t"
5840                 "2: \n\t"
5841                 /* Check if vmlaunch of vmresume is needed */
5842                 "cmpl $0, %c[launched](%0) \n\t"
5843                 /* Load guest registers.  Don't clobber flags. */
5844                 "mov %c[rax](%0), %%"R"ax \n\t"
5845                 "mov %c[rbx](%0), %%"R"bx \n\t"
5846                 "mov %c[rdx](%0), %%"R"dx \n\t"
5847                 "mov %c[rsi](%0), %%"R"si \n\t"
5848                 "mov %c[rdi](%0), %%"R"di \n\t"
5849                 "mov %c[rbp](%0), %%"R"bp \n\t"
5850 #ifdef CONFIG_X86_64
5851                 "mov %c[r8](%0),  %%r8  \n\t"
5852                 "mov %c[r9](%0),  %%r9  \n\t"
5853                 "mov %c[r10](%0), %%r10 \n\t"
5854                 "mov %c[r11](%0), %%r11 \n\t"
5855                 "mov %c[r12](%0), %%r12 \n\t"
5856                 "mov %c[r13](%0), %%r13 \n\t"
5857                 "mov %c[r14](%0), %%r14 \n\t"
5858                 "mov %c[r15](%0), %%r15 \n\t"
5859 #endif
5860                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
5861
5862                 /* Enter guest mode */
5863                 "jne .Llaunched \n\t"
5864                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
5865                 "jmp .Lkvm_vmx_return \n\t"
5866                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
5867                 ".Lkvm_vmx_return: "
5868                 /* Save guest registers, load host registers, keep flags */
5869                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
5870                 "pop %0 \n\t"
5871                 "mov %%"R"ax, %c[rax](%0) \n\t"
5872                 "mov %%"R"bx, %c[rbx](%0) \n\t"
5873                 "pop"Q" %c[rcx](%0) \n\t"
5874                 "mov %%"R"dx, %c[rdx](%0) \n\t"
5875                 "mov %%"R"si, %c[rsi](%0) \n\t"
5876                 "mov %%"R"di, %c[rdi](%0) \n\t"
5877                 "mov %%"R"bp, %c[rbp](%0) \n\t"
5878 #ifdef CONFIG_X86_64
5879                 "mov %%r8,  %c[r8](%0) \n\t"
5880                 "mov %%r9,  %c[r9](%0) \n\t"
5881                 "mov %%r10, %c[r10](%0) \n\t"
5882                 "mov %%r11, %c[r11](%0) \n\t"
5883                 "mov %%r12, %c[r12](%0) \n\t"
5884                 "mov %%r13, %c[r13](%0) \n\t"
5885                 "mov %%r14, %c[r14](%0) \n\t"
5886                 "mov %%r15, %c[r15](%0) \n\t"
5887 #endif
5888                 "mov %%cr2, %%"R"ax   \n\t"
5889                 "mov %%"R"ax, %c[cr2](%0) \n\t"
5890
5891                 "pop  %%"R"bp; pop  %%"R"dx \n\t"
5892                 "setbe %c[fail](%0) \n\t"
5893               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
5894                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
5895                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
5896                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
5897                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
5898                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
5899                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
5900                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
5901                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
5902                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
5903                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
5904 #ifdef CONFIG_X86_64
5905                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
5906                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
5907                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
5908                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
5909                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
5910                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
5911                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
5912                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
5913 #endif
5914                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
5915                 [wordsize]"i"(sizeof(ulong))
5916               : "cc", "memory"
5917                 , R"ax", R"bx", R"di", R"si"
5918 #ifdef CONFIG_X86_64
5919                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5920 #endif
5921               );
5922
5923         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
5924                                   | (1 << VCPU_EXREG_RFLAGS)
5925                                   | (1 << VCPU_EXREG_CPL)
5926                                   | (1 << VCPU_EXREG_PDPTR)
5927                                   | (1 << VCPU_EXREG_SEGMENTS)
5928                                   | (1 << VCPU_EXREG_CR3));
5929         vcpu->arch.regs_dirty = 0;
5930
5931         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
5932
5933         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
5934         vmx->loaded_vmcs->launched = 1;
5935
5936         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
5937
5938         vmx_complete_atomic_exit(vmx);
5939         vmx_recover_nmi_blocking(vmx);
5940         vmx_complete_interrupts(vmx);
5941 }
5942
5943 #undef R
5944 #undef Q
5945
5946 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
5947 {
5948         struct vcpu_vmx *vmx = to_vmx(vcpu);
5949
5950         free_vpid(vmx);
5951         free_nested(vmx);
5952         free_loaded_vmcs(vmx->loaded_vmcs);
5953         kfree(vmx->guest_msrs);
5954         kvm_vcpu_uninit(vcpu);
5955         kmem_cache_free(kvm_vcpu_cache, vmx);
5956 }
5957
5958 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
5959 {
5960         int err;
5961         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
5962         int cpu;
5963
5964         if (!vmx)
5965                 return ERR_PTR(-ENOMEM);
5966
5967         allocate_vpid(vmx);
5968
5969         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
5970         if (err)
5971                 goto free_vcpu;
5972
5973         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
5974         err = -ENOMEM;
5975         if (!vmx->guest_msrs) {
5976                 goto uninit_vcpu;
5977         }
5978
5979         vmx->loaded_vmcs = &vmx->vmcs01;
5980         vmx->loaded_vmcs->vmcs = alloc_vmcs();
5981         if (!vmx->loaded_vmcs->vmcs)
5982                 goto free_msrs;
5983         if (!vmm_exclusive)
5984                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
5985         loaded_vmcs_init(vmx->loaded_vmcs);
5986         if (!vmm_exclusive)
5987                 kvm_cpu_vmxoff();
5988
5989         cpu = get_cpu();
5990         vmx_vcpu_load(&vmx->vcpu, cpu);
5991         vmx->vcpu.cpu = cpu;
5992         err = vmx_vcpu_setup(vmx);
5993         vmx_vcpu_put(&vmx->vcpu);
5994         put_cpu();
5995         if (err)
5996                 goto free_vmcs;
5997         if (vm_need_virtualize_apic_accesses(kvm))
5998                 err = alloc_apic_access_page(kvm);
5999                 if (err)
6000                         goto free_vmcs;
6001
6002         if (enable_ept) {
6003                 if (!kvm->arch.ept_identity_map_addr)
6004                         kvm->arch.ept_identity_map_addr =
6005                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6006                 err = -ENOMEM;
6007                 if (alloc_identity_pagetable(kvm) != 0)
6008                         goto free_vmcs;
6009                 if (!init_rmode_identity_map(kvm))
6010                         goto free_vmcs;
6011         }
6012
6013         vmx->nested.current_vmptr = -1ull;
6014         vmx->nested.current_vmcs12 = NULL;
6015
6016         return &vmx->vcpu;
6017
6018 free_vmcs:
6019         free_vmcs(vmx->loaded_vmcs->vmcs);
6020 free_msrs:
6021         kfree(vmx->guest_msrs);
6022 uninit_vcpu:
6023         kvm_vcpu_uninit(&vmx->vcpu);
6024 free_vcpu:
6025         free_vpid(vmx);
6026         kmem_cache_free(kvm_vcpu_cache, vmx);
6027         return ERR_PTR(err);
6028 }
6029
6030 static void __init vmx_check_processor_compat(void *rtn)
6031 {
6032         struct vmcs_config vmcs_conf;
6033
6034         *(int *)rtn = 0;
6035         if (setup_vmcs_config(&vmcs_conf) < 0)
6036                 *(int *)rtn = -EIO;
6037         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6038                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6039                                 smp_processor_id());
6040                 *(int *)rtn = -EIO;
6041         }
6042 }
6043
6044 static int get_ept_level(void)
6045 {
6046         return VMX_EPT_DEFAULT_GAW + 1;
6047 }
6048
6049 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6050 {
6051         u64 ret;
6052
6053         /* For VT-d and EPT combination
6054          * 1. MMIO: always map as UC
6055          * 2. EPT with VT-d:
6056          *   a. VT-d without snooping control feature: can't guarantee the
6057          *      result, try to trust guest.
6058          *   b. VT-d with snooping control feature: snooping control feature of
6059          *      VT-d engine can guarantee the cache correctness. Just set it
6060          *      to WB to keep consistent with host. So the same as item 3.
6061          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6062          *    consistent with host MTRR
6063          */
6064         if (is_mmio)
6065                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6066         else if (vcpu->kvm->arch.iommu_domain &&
6067                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6068                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6069                       VMX_EPT_MT_EPTE_SHIFT;
6070         else
6071                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6072                         | VMX_EPT_IPAT_BIT;
6073
6074         return ret;
6075 }
6076
6077 #define _ER(x) { EXIT_REASON_##x, #x }
6078
6079 static const struct trace_print_flags vmx_exit_reasons_str[] = {
6080         _ER(EXCEPTION_NMI),
6081         _ER(EXTERNAL_INTERRUPT),
6082         _ER(TRIPLE_FAULT),
6083         _ER(PENDING_INTERRUPT),
6084         _ER(NMI_WINDOW),
6085         _ER(TASK_SWITCH),
6086         _ER(CPUID),
6087         _ER(HLT),
6088         _ER(INVLPG),
6089         _ER(RDPMC),
6090         _ER(RDTSC),
6091         _ER(VMCALL),
6092         _ER(VMCLEAR),
6093         _ER(VMLAUNCH),
6094         _ER(VMPTRLD),
6095         _ER(VMPTRST),
6096         _ER(VMREAD),
6097         _ER(VMRESUME),
6098         _ER(VMWRITE),
6099         _ER(VMOFF),
6100         _ER(VMON),
6101         _ER(CR_ACCESS),
6102         _ER(DR_ACCESS),
6103         _ER(IO_INSTRUCTION),
6104         _ER(MSR_READ),
6105         _ER(MSR_WRITE),
6106         _ER(MWAIT_INSTRUCTION),
6107         _ER(MONITOR_INSTRUCTION),
6108         _ER(PAUSE_INSTRUCTION),
6109         _ER(MCE_DURING_VMENTRY),
6110         _ER(TPR_BELOW_THRESHOLD),
6111         _ER(APIC_ACCESS),
6112         _ER(EPT_VIOLATION),
6113         _ER(EPT_MISCONFIG),
6114         _ER(WBINVD),
6115         { -1, NULL }
6116 };
6117
6118 #undef _ER
6119
6120 static int vmx_get_lpage_level(void)
6121 {
6122         if (enable_ept && !cpu_has_vmx_ept_1g_page())
6123                 return PT_DIRECTORY_LEVEL;
6124         else
6125                 /* For shadow and EPT supported 1GB page */
6126                 return PT_PDPE_LEVEL;
6127 }
6128
6129 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6130 {
6131         struct kvm_cpuid_entry2 *best;
6132         struct vcpu_vmx *vmx = to_vmx(vcpu);
6133         u32 exec_control;
6134
6135         vmx->rdtscp_enabled = false;
6136         if (vmx_rdtscp_supported()) {
6137                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6138                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6139                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6140                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6141                                 vmx->rdtscp_enabled = true;
6142                         else {
6143                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6144                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6145                                                 exec_control);
6146                         }
6147                 }
6148         }
6149 }
6150
6151 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6152 {
6153 }
6154
6155 /*
6156  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6157  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6158  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6159  * guest in a way that will both be appropriate to L1's requests, and our
6160  * needs. In addition to modifying the active vmcs (which is vmcs02), this
6161  * function also has additional necessary side-effects, like setting various
6162  * vcpu->arch fields.
6163  */
6164 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6165 {
6166         struct vcpu_vmx *vmx = to_vmx(vcpu);
6167         u32 exec_control;
6168
6169         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6170         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6171         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6172         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6173         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6174         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6175         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6176         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6177         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6178         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6179         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6180         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6181         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6182         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6183         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6184         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6185         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6186         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6187         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6188         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6189         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6190         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6191         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6192         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6193         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6194         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6195         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6196         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6197         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6198         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6199         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6200         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6201         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6202         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6203         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6204         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6205
6206         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6207         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6208                 vmcs12->vm_entry_intr_info_field);
6209         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6210                 vmcs12->vm_entry_exception_error_code);
6211         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6212                 vmcs12->vm_entry_instruction_len);
6213         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6214                 vmcs12->guest_interruptibility_info);
6215         vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6216         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6217         vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6218         vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6219         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6220                 vmcs12->guest_pending_dbg_exceptions);
6221         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6222         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6223
6224         vmcs_write64(VMCS_LINK_POINTER, -1ull);
6225
6226         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6227                 (vmcs_config.pin_based_exec_ctrl |
6228                  vmcs12->pin_based_vm_exec_control));
6229
6230         /*
6231          * Whether page-faults are trapped is determined by a combination of
6232          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6233          * If enable_ept, L0 doesn't care about page faults and we should
6234          * set all of these to L1's desires. However, if !enable_ept, L0 does
6235          * care about (at least some) page faults, and because it is not easy
6236          * (if at all possible?) to merge L0 and L1's desires, we simply ask
6237          * to exit on each and every L2 page fault. This is done by setting
6238          * MASK=MATCH=0 and (see below) EB.PF=1.
6239          * Note that below we don't need special code to set EB.PF beyond the
6240          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6241          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6242          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6243          *
6244          * A problem with this approach (when !enable_ept) is that L1 may be
6245          * injected with more page faults than it asked for. This could have
6246          * caused problems, but in practice existing hypervisors don't care.
6247          * To fix this, we will need to emulate the PFEC checking (on the L1
6248          * page tables), using walk_addr(), when injecting PFs to L1.
6249          */
6250         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6251                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6252         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6253                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6254
6255         if (cpu_has_secondary_exec_ctrls()) {
6256                 u32 exec_control = vmx_secondary_exec_control(vmx);
6257                 if (!vmx->rdtscp_enabled)
6258                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
6259                 /* Take the following fields only from vmcs12 */
6260                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6261                 if (nested_cpu_has(vmcs12,
6262                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6263                         exec_control |= vmcs12->secondary_vm_exec_control;
6264
6265                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6266                         /*
6267                          * Translate L1 physical address to host physical
6268                          * address for vmcs02. Keep the page pinned, so this
6269                          * physical address remains valid. We keep a reference
6270                          * to it so we can release it later.
6271                          */
6272                         if (vmx->nested.apic_access_page) /* shouldn't happen */
6273                                 nested_release_page(vmx->nested.apic_access_page);
6274                         vmx->nested.apic_access_page =
6275                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
6276                         /*
6277                          * If translation failed, no matter: This feature asks
6278                          * to exit when accessing the given address, and if it
6279                          * can never be accessed, this feature won't do
6280                          * anything anyway.
6281                          */
6282                         if (!vmx->nested.apic_access_page)
6283                                 exec_control &=
6284                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6285                         else
6286                                 vmcs_write64(APIC_ACCESS_ADDR,
6287                                   page_to_phys(vmx->nested.apic_access_page));
6288                 }
6289
6290                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6291         }
6292
6293
6294         /*
6295          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6296          * Some constant fields are set here by vmx_set_constant_host_state().
6297          * Other fields are different per CPU, and will be set later when
6298          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6299          */
6300         vmx_set_constant_host_state();
6301
6302         /*
6303          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6304          * entry, but only if the current (host) sp changed from the value
6305          * we wrote last (vmx->host_rsp). This cache is no longer relevant
6306          * if we switch vmcs, and rather than hold a separate cache per vmcs,
6307          * here we just force the write to happen on entry.
6308          */
6309         vmx->host_rsp = 0;
6310
6311         exec_control = vmx_exec_control(vmx); /* L0's desires */
6312         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6313         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6314         exec_control &= ~CPU_BASED_TPR_SHADOW;
6315         exec_control |= vmcs12->cpu_based_vm_exec_control;
6316         /*
6317          * Merging of IO and MSR bitmaps not currently supported.
6318          * Rather, exit every time.
6319          */
6320         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6321         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6322         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6323
6324         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6325
6326         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6327          * bitwise-or of what L1 wants to trap for L2, and what we want to
6328          * trap. Note that CR0.TS also needs updating - we do this later.
6329          */
6330         update_exception_bitmap(vcpu);
6331         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6332         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6333
6334         /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6335         vmcs_write32(VM_EXIT_CONTROLS,
6336                 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6337         vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6338                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6339
6340         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6341                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6342         else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6343                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6344
6345
6346         set_cr4_guest_host_mask(vmx);
6347
6348         vmcs_write64(TSC_OFFSET,
6349                 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6350
6351         if (enable_vpid) {
6352                 /*
6353                  * Trivially support vpid by letting L2s share their parent
6354                  * L1's vpid. TODO: move to a more elaborate solution, giving
6355                  * each L2 its own vpid and exposing the vpid feature to L1.
6356                  */
6357                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6358                 vmx_flush_tlb(vcpu);
6359         }
6360
6361         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6362                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6363         if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6364                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6365         else
6366                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6367         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6368         vmx_set_efer(vcpu, vcpu->arch.efer);
6369
6370         /*
6371          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6372          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6373          * The CR0_READ_SHADOW is what L2 should have expected to read given
6374          * the specifications by L1; It's not enough to take
6375          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6376          * have more bits than L1 expected.
6377          */
6378         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6379         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6380
6381         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6382         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6383
6384         /* shadow page tables on either EPT or shadow page tables */
6385         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6386         kvm_mmu_reset_context(vcpu);
6387
6388         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6389         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6390 }
6391
6392 /*
6393  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6394  * for running an L2 nested guest.
6395  */
6396 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6397 {
6398         struct vmcs12 *vmcs12;
6399         struct vcpu_vmx *vmx = to_vmx(vcpu);
6400         int cpu;
6401         struct loaded_vmcs *vmcs02;
6402
6403         if (!nested_vmx_check_permission(vcpu) ||
6404             !nested_vmx_check_vmcs12(vcpu))
6405                 return 1;
6406
6407         skip_emulated_instruction(vcpu);
6408         vmcs12 = get_vmcs12(vcpu);
6409
6410         /*
6411          * The nested entry process starts with enforcing various prerequisites
6412          * on vmcs12 as required by the Intel SDM, and act appropriately when
6413          * they fail: As the SDM explains, some conditions should cause the
6414          * instruction to fail, while others will cause the instruction to seem
6415          * to succeed, but return an EXIT_REASON_INVALID_STATE.
6416          * To speed up the normal (success) code path, we should avoid checking
6417          * for misconfigurations which will anyway be caught by the processor
6418          * when using the merged vmcs02.
6419          */
6420         if (vmcs12->launch_state == launch) {
6421                 nested_vmx_failValid(vcpu,
6422                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6423                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6424                 return 1;
6425         }
6426
6427         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6428                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6429                 /*TODO: Also verify bits beyond physical address width are 0*/
6430                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6431                 return 1;
6432         }
6433
6434         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6435                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6436                 /*TODO: Also verify bits beyond physical address width are 0*/
6437                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6438                 return 1;
6439         }
6440
6441         if (vmcs12->vm_entry_msr_load_count > 0 ||
6442             vmcs12->vm_exit_msr_load_count > 0 ||
6443             vmcs12->vm_exit_msr_store_count > 0) {
6444                 if (printk_ratelimit())
6445                         printk(KERN_WARNING
6446                           "%s: VMCS MSR_{LOAD,STORE} unsupported\n", __func__);
6447                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6448                 return 1;
6449         }
6450
6451         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6452               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6453             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6454               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6455             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6456               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6457             !vmx_control_verify(vmcs12->vm_exit_controls,
6458               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6459             !vmx_control_verify(vmcs12->vm_entry_controls,
6460               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6461         {
6462                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6463                 return 1;
6464         }
6465
6466         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6467             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6468                 nested_vmx_failValid(vcpu,
6469                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6470                 return 1;
6471         }
6472
6473         if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6474             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6475                 nested_vmx_entry_failure(vcpu, vmcs12,
6476                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6477                 return 1;
6478         }
6479         if (vmcs12->vmcs_link_pointer != -1ull) {
6480                 nested_vmx_entry_failure(vcpu, vmcs12,
6481                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6482                 return 1;
6483         }
6484
6485         /*
6486          * We're finally done with prerequisite checking, and can start with
6487          * the nested entry.
6488          */
6489
6490         vmcs02 = nested_get_current_vmcs02(vmx);
6491         if (!vmcs02)
6492                 return -ENOMEM;
6493
6494         enter_guest_mode(vcpu);
6495
6496         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6497
6498         cpu = get_cpu();
6499         vmx->loaded_vmcs = vmcs02;
6500         vmx_vcpu_put(vcpu);
6501         vmx_vcpu_load(vcpu, cpu);
6502         vcpu->cpu = cpu;
6503         put_cpu();
6504
6505         vmcs12->launch_state = 1;
6506
6507         prepare_vmcs02(vcpu, vmcs12);
6508
6509         /*
6510          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6511          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6512          * returned as far as L1 is concerned. It will only return (and set
6513          * the success flag) when L2 exits (see nested_vmx_vmexit()).
6514          */
6515         return 1;
6516 }
6517
6518 /*
6519  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6520  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6521  * This function returns the new value we should put in vmcs12.guest_cr0.
6522  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6523  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6524  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6525  *     didn't trap the bit, because if L1 did, so would L0).
6526  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6527  *     been modified by L2, and L1 knows it. So just leave the old value of
6528  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6529  *     isn't relevant, because if L0 traps this bit it can set it to anything.
6530  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6531  *     changed these bits, and therefore they need to be updated, but L0
6532  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6533  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6534  */
6535 static inline unsigned long
6536 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6537 {
6538         return
6539         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6540         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6541         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6542                         vcpu->arch.cr0_guest_owned_bits));
6543 }
6544
6545 static inline unsigned long
6546 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6547 {
6548         return
6549         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6550         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6551         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6552                         vcpu->arch.cr4_guest_owned_bits));
6553 }
6554
6555 /*
6556  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6557  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6558  * and this function updates it to reflect the changes to the guest state while
6559  * L2 was running (and perhaps made some exits which were handled directly by L0
6560  * without going back to L1), and to reflect the exit reason.
6561  * Note that we do not have to copy here all VMCS fields, just those that
6562  * could have changed by the L2 guest or the exit - i.e., the guest-state and
6563  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6564  * which already writes to vmcs12 directly.
6565  */
6566 void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6567 {
6568         /* update guest state fields: */
6569         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6570         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6571
6572         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6573         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6574         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6575         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6576
6577         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6578         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6579         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6580         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6581         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6582         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6583         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6584         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6585         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6586         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6587         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6588         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6589         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6590         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6591         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6592         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6593         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6594         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6595         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6596         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6597         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6598         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6599         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6600         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6601         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6602         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6603         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6604         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6605         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6606         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6607         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6608         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6609         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6610         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6611         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6612         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6613
6614         vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
6615         vmcs12->guest_interruptibility_info =
6616                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
6617         vmcs12->guest_pending_dbg_exceptions =
6618                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
6619
6620         /* TODO: These cannot have changed unless we have MSR bitmaps and
6621          * the relevant bit asks not to trap the change */
6622         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
6623         if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
6624                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
6625         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
6626         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
6627         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
6628
6629         /* update exit information fields: */
6630
6631         vmcs12->vm_exit_reason  = vmcs_read32(VM_EXIT_REASON);
6632         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6633
6634         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6635         vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6636         vmcs12->idt_vectoring_info_field =
6637                 vmcs_read32(IDT_VECTORING_INFO_FIELD);
6638         vmcs12->idt_vectoring_error_code =
6639                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6640         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6641         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6642
6643         /* clear vm-entry fields which are to be cleared on exit */
6644         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6645                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
6646 }
6647
6648 /*
6649  * A part of what we need to when the nested L2 guest exits and we want to
6650  * run its L1 parent, is to reset L1's guest state to the host state specified
6651  * in vmcs12.
6652  * This function is to be called not only on normal nested exit, but also on
6653  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6654  * Failures During or After Loading Guest State").
6655  * This function should be called when the active VMCS is L1's (vmcs01).
6656  */
6657 void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6658 {
6659         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
6660                 vcpu->arch.efer = vmcs12->host_ia32_efer;
6661         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
6662                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6663         else
6664                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6665         vmx_set_efer(vcpu, vcpu->arch.efer);
6666
6667         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
6668         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
6669         /*
6670          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
6671          * actually changed, because it depends on the current state of
6672          * fpu_active (which may have changed).
6673          * Note that vmx_set_cr0 refers to efer set above.
6674          */
6675         kvm_set_cr0(vcpu, vmcs12->host_cr0);
6676         /*
6677          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
6678          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
6679          * but we also need to update cr0_guest_host_mask and exception_bitmap.
6680          */
6681         update_exception_bitmap(vcpu);
6682         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
6683         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6684
6685         /*
6686          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
6687          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
6688          */
6689         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
6690         kvm_set_cr4(vcpu, vmcs12->host_cr4);
6691
6692         /* shadow page tables on either EPT or shadow page tables */
6693         kvm_set_cr3(vcpu, vmcs12->host_cr3);
6694         kvm_mmu_reset_context(vcpu);
6695
6696         if (enable_vpid) {
6697                 /*
6698                  * Trivially support vpid by letting L2s share their parent
6699                  * L1's vpid. TODO: move to a more elaborate solution, giving
6700                  * each L2 its own vpid and exposing the vpid feature to L1.
6701                  */
6702                 vmx_flush_tlb(vcpu);
6703         }
6704
6705
6706         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
6707         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
6708         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
6709         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
6710         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
6711         vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
6712         vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
6713         vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
6714         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
6715         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
6716         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
6717         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
6718         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
6719         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
6720         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
6721
6722         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
6723                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
6724         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
6725                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
6726                         vmcs12->host_ia32_perf_global_ctrl);
6727 }
6728
6729 /*
6730  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
6731  * and modify vmcs12 to make it see what it would expect to see there if
6732  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
6733  */
6734 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
6735 {
6736         struct vcpu_vmx *vmx = to_vmx(vcpu);
6737         int cpu;
6738         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6739
6740         leave_guest_mode(vcpu);
6741         prepare_vmcs12(vcpu, vmcs12);
6742
6743         cpu = get_cpu();
6744         vmx->loaded_vmcs = &vmx->vmcs01;
6745         vmx_vcpu_put(vcpu);
6746         vmx_vcpu_load(vcpu, cpu);
6747         vcpu->cpu = cpu;
6748         put_cpu();
6749
6750         /* if no vmcs02 cache requested, remove the one we used */
6751         if (VMCS02_POOL_SIZE == 0)
6752                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
6753
6754         load_vmcs12_host_state(vcpu, vmcs12);
6755
6756         /* Update TSC_OFFSET if vmx_adjust_tsc_offset() was used while L2 ran */
6757         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6758
6759         /* This is needed for same reason as it was needed in prepare_vmcs02 */
6760         vmx->host_rsp = 0;
6761
6762         /* Unpin physical memory we referred to in vmcs02 */
6763         if (vmx->nested.apic_access_page) {
6764                 nested_release_page(vmx->nested.apic_access_page);
6765                 vmx->nested.apic_access_page = 0;
6766         }
6767
6768         /*
6769          * Exiting from L2 to L1, we're now back to L1 which thinks it just
6770          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
6771          * success or failure flag accordingly.
6772          */
6773         if (unlikely(vmx->fail)) {
6774                 vmx->fail = 0;
6775                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
6776         } else
6777                 nested_vmx_succeed(vcpu);
6778 }
6779
6780 /*
6781  * L1's failure to enter L2 is a subset of a normal exit, as explained in
6782  * 23.7 "VM-entry failures during or after loading guest state" (this also
6783  * lists the acceptable exit-reason and exit-qualification parameters).
6784  * It should only be called before L2 actually succeeded to run, and when
6785  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
6786  */
6787 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
6788                         struct vmcs12 *vmcs12,
6789                         u32 reason, unsigned long qualification)
6790 {
6791         load_vmcs12_host_state(vcpu, vmcs12);
6792         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
6793         vmcs12->exit_qualification = qualification;
6794         nested_vmx_succeed(vcpu);
6795 }
6796
6797 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
6798                                struct x86_instruction_info *info,
6799                                enum x86_intercept_stage stage)
6800 {
6801         return X86EMUL_CONTINUE;
6802 }
6803
6804 static struct kvm_x86_ops vmx_x86_ops = {
6805         .cpu_has_kvm_support = cpu_has_kvm_support,
6806         .disabled_by_bios = vmx_disabled_by_bios,
6807         .hardware_setup = hardware_setup,
6808         .hardware_unsetup = hardware_unsetup,
6809         .check_processor_compatibility = vmx_check_processor_compat,
6810         .hardware_enable = hardware_enable,
6811         .hardware_disable = hardware_disable,
6812         .cpu_has_accelerated_tpr = report_flexpriority,
6813
6814         .vcpu_create = vmx_create_vcpu,
6815         .vcpu_free = vmx_free_vcpu,
6816         .vcpu_reset = vmx_vcpu_reset,
6817
6818         .prepare_guest_switch = vmx_save_host_state,
6819         .vcpu_load = vmx_vcpu_load,
6820         .vcpu_put = vmx_vcpu_put,
6821
6822         .set_guest_debug = set_guest_debug,
6823         .get_msr = vmx_get_msr,
6824         .set_msr = vmx_set_msr,
6825         .get_segment_base = vmx_get_segment_base,
6826         .get_segment = vmx_get_segment,
6827         .set_segment = vmx_set_segment,
6828         .get_cpl = vmx_get_cpl,
6829         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
6830         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
6831         .decache_cr3 = vmx_decache_cr3,
6832         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6833         .set_cr0 = vmx_set_cr0,
6834         .set_cr3 = vmx_set_cr3,
6835         .set_cr4 = vmx_set_cr4,
6836         .set_efer = vmx_set_efer,
6837         .get_idt = vmx_get_idt,
6838         .set_idt = vmx_set_idt,
6839         .get_gdt = vmx_get_gdt,
6840         .set_gdt = vmx_set_gdt,
6841         .set_dr7 = vmx_set_dr7,
6842         .cache_reg = vmx_cache_reg,
6843         .get_rflags = vmx_get_rflags,
6844         .set_rflags = vmx_set_rflags,
6845         .fpu_activate = vmx_fpu_activate,
6846         .fpu_deactivate = vmx_fpu_deactivate,
6847
6848         .tlb_flush = vmx_flush_tlb,
6849
6850         .run = vmx_vcpu_run,
6851         .handle_exit = vmx_handle_exit,
6852         .skip_emulated_instruction = skip_emulated_instruction,
6853         .set_interrupt_shadow = vmx_set_interrupt_shadow,
6854         .get_interrupt_shadow = vmx_get_interrupt_shadow,
6855         .patch_hypercall = vmx_patch_hypercall,
6856         .set_irq = vmx_inject_irq,
6857         .set_nmi = vmx_inject_nmi,
6858         .queue_exception = vmx_queue_exception,
6859         .cancel_injection = vmx_cancel_injection,
6860         .interrupt_allowed = vmx_interrupt_allowed,
6861         .nmi_allowed = vmx_nmi_allowed,
6862         .get_nmi_mask = vmx_get_nmi_mask,
6863         .set_nmi_mask = vmx_set_nmi_mask,
6864         .enable_nmi_window = enable_nmi_window,
6865         .enable_irq_window = enable_irq_window,
6866         .update_cr8_intercept = update_cr8_intercept,
6867
6868         .set_tss_addr = vmx_set_tss_addr,
6869         .get_tdp_level = get_ept_level,
6870         .get_mt_mask = vmx_get_mt_mask,
6871
6872         .get_exit_info = vmx_get_exit_info,
6873         .exit_reasons_str = vmx_exit_reasons_str,
6874
6875         .get_lpage_level = vmx_get_lpage_level,
6876
6877         .cpuid_update = vmx_cpuid_update,
6878
6879         .rdtscp_supported = vmx_rdtscp_supported,
6880
6881         .set_supported_cpuid = vmx_set_supported_cpuid,
6882
6883         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
6884
6885         .set_tsc_khz = vmx_set_tsc_khz,
6886         .write_tsc_offset = vmx_write_tsc_offset,
6887         .adjust_tsc_offset = vmx_adjust_tsc_offset,
6888         .compute_tsc_offset = vmx_compute_tsc_offset,
6889
6890         .set_tdp_cr3 = vmx_set_cr3,
6891
6892         .check_intercept = vmx_check_intercept,
6893 };
6894
6895 static int __init vmx_init(void)
6896 {
6897         int r, i;
6898
6899         rdmsrl_safe(MSR_EFER, &host_efer);
6900
6901         for (i = 0; i < NR_VMX_MSR; ++i)
6902                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6903
6904         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6905         if (!vmx_io_bitmap_a)
6906                 return -ENOMEM;
6907
6908         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6909         if (!vmx_io_bitmap_b) {
6910                 r = -ENOMEM;
6911                 goto out;
6912         }
6913
6914         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6915         if (!vmx_msr_bitmap_legacy) {
6916                 r = -ENOMEM;
6917                 goto out1;
6918         }
6919
6920         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6921         if (!vmx_msr_bitmap_longmode) {
6922                 r = -ENOMEM;
6923                 goto out2;
6924         }
6925
6926         /*
6927          * Allow direct access to the PC debug port (it is often used for I/O
6928          * delays, but the vmexits simply slow things down).
6929          */
6930         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6931         clear_bit(0x80, vmx_io_bitmap_a);
6932
6933         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6934
6935         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6936         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6937
6938         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6939
6940         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
6941                      __alignof__(struct vcpu_vmx), THIS_MODULE);
6942         if (r)
6943                 goto out3;
6944
6945         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6946         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6947         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6948         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6949         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6950         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6951
6952         if (enable_ept) {
6953                 bypass_guest_pf = 0;
6954                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
6955                                 VMX_EPT_EXECUTABLE_MASK);
6956                 kvm_enable_tdp();
6957         } else
6958                 kvm_disable_tdp();
6959
6960         if (bypass_guest_pf)
6961                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
6962
6963         return 0;
6964
6965 out3:
6966         free_page((unsigned long)vmx_msr_bitmap_longmode);
6967 out2:
6968         free_page((unsigned long)vmx_msr_bitmap_legacy);
6969 out1:
6970         free_page((unsigned long)vmx_io_bitmap_b);
6971 out:
6972         free_page((unsigned long)vmx_io_bitmap_a);
6973         return r;
6974 }
6975
6976 static void __exit vmx_exit(void)
6977 {
6978         free_page((unsigned long)vmx_msr_bitmap_legacy);
6979         free_page((unsigned long)vmx_msr_bitmap_longmode);
6980         free_page((unsigned long)vmx_io_bitmap_b);
6981         free_page((unsigned long)vmx_io_bitmap_a);
6982
6983         kvm_exit();
6984 }
6985
6986 module_init(vmx_init)
6987 module_exit(vmx_exit)