arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/kvm_host.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31 #include <linux/tboot.h>
  32 #include "kvm_cache_regs.h"
  33 #include "x86.h"
  34
  35 #include <asm/io.h>
  36 #include <asm/desc.h>
  37 #include <asm/vmx.h>
  38 #include <asm/virtext.h>
  39 #include <asm/mce.h>
  40 #include <asm/i387.h>
  41 #include <asm/xcr.h>
  42
  43 #include "trace.h"
  44
  45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  46 #define __ex_clear(x, reg) \
  47         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  48
  49 MODULE_AUTHOR("Qumranet");
  50 MODULE_LICENSE("GPL");
  51
  52 static int __read_mostly bypass_guest_pf = 1;
  53 module_param(bypass_guest_pf, bool, S_IRUGO);
  54
  55 static int __read_mostly enable_vpid = 1;
  56 module_param_named(vpid, enable_vpid, bool, 0444);
  57
  58 static int __read_mostly flexpriority_enabled = 1;
  59 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  60
  61 static int __read_mostly enable_ept = 1;
  62 module_param_named(ept, enable_ept, bool, S_IRUGO);
  63
  64 static int __read_mostly enable_unrestricted_guest = 1;
  65 module_param_named(unrestricted_guest,
  66                         enable_unrestricted_guest, bool, S_IRUGO);
  67
  68 static int __read_mostly emulate_invalid_guest_state = 0;
  69 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  70
  71 static int __read_mostly vmm_exclusive = 1;
  72 module_param(vmm_exclusive, bool, S_IRUGO);
  73
  74 static int __read_mostly yield_on_hlt = 1;
  75 module_param(yield_on_hlt, bool, S_IRUGO);
  76
  77 /*
  78  * If nested=1, nested virtualization is supported, i.e., guests may use
  79  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  80  * use VMX instructions.
  81  */
  82 static int __read_mostly nested = 0;
  83 module_param(nested, bool, S_IRUGO);
  84
  85 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  86         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  87 #define KVM_GUEST_CR0_MASK                                              \
  88         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  89 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  90         (X86_CR0_WP | X86_CR0_NE)
  91 #define KVM_VM_CR0_ALWAYS_ON                                            \
  92         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  93 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  94         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  95          | X86_CR4_OSXMMEXCPT)
  96
  97 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  98 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  99
 100 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 101
 102 /*
 103  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 104  * ple_gap:    upper bound on the amount of time between two successive
 105  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 106  *             According to test, this time is usually smaller than 128 cycles.
 107  * ple_window: upper bound on the amount of time a guest is allowed to execute
 108  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 109  *             less than 2^12 cycles
 110  * Time is measured based on a counter that runs at the same rate as the TSC,
 111  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 112  */
 113 #define KVM_VMX_DEFAULT_PLE_GAP    128
 114 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 115 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 116 module_param(ple_gap, int, S_IRUGO);
 117
 118 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 119 module_param(ple_window, int, S_IRUGO);
 120
 121 #define NR_AUTOLOAD_MSRS 1
 122
 123 struct vmcs {
 124         u32 revision_id;
 125         u32 abort;
 126         char data[0];
 127 };
 128
 129 /*
 130  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 131  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 132  * loaded on this CPU (so we can clear them if the CPU goes down).
 133  */
 134 struct loaded_vmcs {
 135         struct vmcs *vmcs;
 136         int cpu;
 137         int launched;
 138         struct list_head loaded_vmcss_on_cpu_link;
 139 };
 140
 141 struct shared_msr_entry {
 142         unsigned index;
 143         u64 data;
 144         u64 mask;
 145 };
 146
 147 /*
 148  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 149  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 150  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 151  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 152  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 153  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 154  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 155  * underlying hardware which will be used to run L2.
 156  * This structure is packed to ensure that its layout is identical across
 157  * machines (necessary for live migration).
 158  * If there are changes in this struct, VMCS12_REVISION must be changed.
 159  */
 160 struct __packed vmcs12 {
 161         /* According to the Intel spec, a VMCS region must start with the
 162          * following two fields. Then follow implementation-specific data.
 163          */
 164         u32 revision_id;
 165         u32 abort;
 166 };
 167
 168 /*
 169  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 170  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 171  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 172  */
 173 #define VMCS12_REVISION 0x11e57ed0
 174
 175 /*
 176  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 177  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 178  * current implementation, 4K are reserved to avoid future complications.
 179  */
 180 #define VMCS12_SIZE 0x1000
 181
 182 /*
 183  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 184  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 185  */
 186 struct nested_vmx {
 187         /* Has the level1 guest done vmxon? */
 188         bool vmxon;
 189
 190         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 191         gpa_t current_vmptr;
 192         /* The host-usable pointer to the above */
 193         struct page *current_vmcs12_page;
 194         struct vmcs12 *current_vmcs12;
 195 };
 196
 197 struct vcpu_vmx {
 198         struct kvm_vcpu       vcpu;
 199         unsigned long         host_rsp;
 200         u8                    fail;
 201         u8                    cpl;
 202         bool                  nmi_known_unmasked;
 203         u32                   exit_intr_info;
 204         u32                   idt_vectoring_info;
 205         ulong                 rflags;
 206         struct shared_msr_entry *guest_msrs;
 207         int                   nmsrs;
 208         int                   save_nmsrs;
 209 #ifdef CONFIG_X86_64
 210         u64                   msr_host_kernel_gs_base;
 211         u64                   msr_guest_kernel_gs_base;
 212 #endif
 213         /*
 214          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 215          * non-nested (L1) guest, it always points to vmcs01. For a nested
 216          * guest (L2), it points to a different VMCS.
 217          */
 218         struct loaded_vmcs    vmcs01;
 219         struct loaded_vmcs   *loaded_vmcs;
 220         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 221         struct msr_autoload {
 222                 unsigned nr;
 223                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 224                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 225         } msr_autoload;
 226         struct {
 227                 int           loaded;
 228                 u16           fs_sel, gs_sel, ldt_sel;
 229                 int           gs_ldt_reload_needed;
 230                 int           fs_reload_needed;
 231         } host_state;
 232         struct {
 233                 int vm86_active;
 234                 ulong save_rflags;
 235                 struct kvm_save_segment {
 236                         u16 selector;
 237                         unsigned long base;
 238                         u32 limit;
 239                         u32 ar;
 240                 } tr, es, ds, fs, gs;
 241         } rmode;
 242         struct {
 243                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 244                 struct kvm_save_segment seg[8];
 245         } segment_cache;
 246         int vpid;
 247         bool emulation_required;
 248
 249         /* Support for vnmi-less CPUs */
 250         int soft_vnmi_blocked;
 251         ktime_t entry_time;
 252         s64 vnmi_blocked_time;
 253         u32 exit_reason;
 254
 255         bool rdtscp_enabled;
 256
 257         /* Support for a guest hypervisor (nested VMX) */
 258         struct nested_vmx nested;
 259 };
 260
 261 enum segment_cache_field {
 262         SEG_FIELD_SEL = 0,
 263         SEG_FIELD_BASE = 1,
 264         SEG_FIELD_LIMIT = 2,
 265         SEG_FIELD_AR = 3,
 266
 267         SEG_FIELD_NR = 4
 268 };
 269
 270 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 271 {
 272         return container_of(vcpu, struct vcpu_vmx, vcpu);
 273 }
 274
 275 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 276 {
 277         return to_vmx(vcpu)->nested.current_vmcs12;
 278 }
 279
 280 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 281 {
 282         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 283         if (is_error_page(page)) {
 284                 kvm_release_page_clean(page);
 285                 return NULL;
 286         }
 287         return page;
 288 }
 289
 290 static void nested_release_page(struct page *page)
 291 {
 292         kvm_release_page_dirty(page);
 293 }
 294
 295 static void nested_release_page_clean(struct page *page)
 296 {
 297         kvm_release_page_clean(page);
 298 }
 299
 300 static u64 construct_eptp(unsigned long root_hpa);
 301 static void kvm_cpu_vmxon(u64 addr);
 302 static void kvm_cpu_vmxoff(void);
 303 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 304 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 305
 306 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 307 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 308 /*
 309  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 310  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 311  */
 312 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 313 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 314
 315 static unsigned long *vmx_io_bitmap_a;
 316 static unsigned long *vmx_io_bitmap_b;
 317 static unsigned long *vmx_msr_bitmap_legacy;
 318 static unsigned long *vmx_msr_bitmap_longmode;
 319
 320 static bool cpu_has_load_ia32_efer;
 321
 322 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 323 static DEFINE_SPINLOCK(vmx_vpid_lock);
 324
 325 static struct vmcs_config {
 326         int size;
 327         int order;
 328         u32 revision_id;
 329         u32 pin_based_exec_ctrl;
 330         u32 cpu_based_exec_ctrl;
 331         u32 cpu_based_2nd_exec_ctrl;
 332         u32 vmexit_ctrl;
 333         u32 vmentry_ctrl;
 334 } vmcs_config;
 335
 336 static struct vmx_capability {
 337         u32 ept;
 338         u32 vpid;
 339 } vmx_capability;
 340
 341 #define VMX_SEGMENT_FIELD(seg)                                  \
 342         [VCPU_SREG_##seg] = {                                   \
 343                 .selector = GUEST_##seg##_SELECTOR,             \
 344                 .base = GUEST_##seg##_BASE,                     \
 345                 .limit = GUEST_##seg##_LIMIT,                   \
 346                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 347         }
 348
 349 static struct kvm_vmx_segment_field {
 350         unsigned selector;
 351         unsigned base;
 352         unsigned limit;
 353         unsigned ar_bytes;
 354 } kvm_vmx_segment_fields[] = {
 355         VMX_SEGMENT_FIELD(CS),
 356         VMX_SEGMENT_FIELD(DS),
 357         VMX_SEGMENT_FIELD(ES),
 358         VMX_SEGMENT_FIELD(FS),
 359         VMX_SEGMENT_FIELD(GS),
 360         VMX_SEGMENT_FIELD(SS),
 361         VMX_SEGMENT_FIELD(TR),
 362         VMX_SEGMENT_FIELD(LDTR),
 363 };
 364
 365 static u64 host_efer;
 366
 367 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 368
 369 /*
 370  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 371  * away by decrementing the array size.
 372  */
 373 static const u32 vmx_msr_index[] = {
 374 #ifdef CONFIG_X86_64
 375         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 376 #endif
 377         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 378 };
 379 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 380
 381 static inline bool is_page_fault(u32 intr_info)
 382 {
 383         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 384                              INTR_INFO_VALID_MASK)) ==
 385                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 386 }
 387
 388 static inline bool is_no_device(u32 intr_info)
 389 {
 390         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 391                              INTR_INFO_VALID_MASK)) ==
 392                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 393 }
 394
 395 static inline bool is_invalid_opcode(u32 intr_info)
 396 {
 397         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 398                              INTR_INFO_VALID_MASK)) ==
 399                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 400 }
 401
 402 static inline bool is_external_interrupt(u32 intr_info)
 403 {
 404         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 405                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 406 }
 407
 408 static inline bool is_machine_check(u32 intr_info)
 409 {
 410         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 411                              INTR_INFO_VALID_MASK)) ==
 412                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 413 }
 414
 415 static inline bool cpu_has_vmx_msr_bitmap(void)
 416 {
 417         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 418 }
 419
 420 static inline bool cpu_has_vmx_tpr_shadow(void)
 421 {
 422         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 423 }
 424
 425 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 426 {
 427         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 428 }
 429
 430 static inline bool cpu_has_secondary_exec_ctrls(void)
 431 {
 432         return vmcs_config.cpu_based_exec_ctrl &
 433                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 434 }
 435
 436 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 437 {
 438         return vmcs_config.cpu_based_2nd_exec_ctrl &
 439                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 440 }
 441
 442 static inline bool cpu_has_vmx_flexpriority(void)
 443 {
 444         return cpu_has_vmx_tpr_shadow() &&
 445                 cpu_has_vmx_virtualize_apic_accesses();
 446 }
 447
 448 static inline bool cpu_has_vmx_ept_execute_only(void)
 449 {
 450         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 451 }
 452
 453 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 454 {
 455         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 456 }
 457
 458 static inline bool cpu_has_vmx_eptp_writeback(void)
 459 {
 460         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 461 }
 462
 463 static inline bool cpu_has_vmx_ept_2m_page(void)
 464 {
 465         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 466 }
 467
 468 static inline bool cpu_has_vmx_ept_1g_page(void)
 469 {
 470         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 471 }
 472
 473 static inline bool cpu_has_vmx_ept_4levels(void)
 474 {
 475         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 476 }
 477
 478 static inline bool cpu_has_vmx_invept_individual_addr(void)
 479 {
 480         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 481 }
 482
 483 static inline bool cpu_has_vmx_invept_context(void)
 484 {
 485         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 486 }
 487
 488 static inline bool cpu_has_vmx_invept_global(void)
 489 {
 490         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 491 }
 492
 493 static inline bool cpu_has_vmx_invvpid_single(void)
 494 {
 495         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 496 }
 497
 498 static inline bool cpu_has_vmx_invvpid_global(void)
 499 {
 500         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 501 }
 502
 503 static inline bool cpu_has_vmx_ept(void)
 504 {
 505         return vmcs_config.cpu_based_2nd_exec_ctrl &
 506                 SECONDARY_EXEC_ENABLE_EPT;
 507 }
 508
 509 static inline bool cpu_has_vmx_unrestricted_guest(void)
 510 {
 511         return vmcs_config.cpu_based_2nd_exec_ctrl &
 512                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 513 }
 514
 515 static inline bool cpu_has_vmx_ple(void)
 516 {
 517         return vmcs_config.cpu_based_2nd_exec_ctrl &
 518                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 519 }
 520
 521 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 522 {
 523         return flexpriority_enabled && irqchip_in_kernel(kvm);
 524 }
 525
 526 static inline bool cpu_has_vmx_vpid(void)
 527 {
 528         return vmcs_config.cpu_based_2nd_exec_ctrl &
 529                 SECONDARY_EXEC_ENABLE_VPID;
 530 }
 531
 532 static inline bool cpu_has_vmx_rdtscp(void)
 533 {
 534         return vmcs_config.cpu_based_2nd_exec_ctrl &
 535                 SECONDARY_EXEC_RDTSCP;
 536 }
 537
 538 static inline bool cpu_has_virtual_nmis(void)
 539 {
 540         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 541 }
 542
 543 static inline bool cpu_has_vmx_wbinvd_exit(void)
 544 {
 545         return vmcs_config.cpu_based_2nd_exec_ctrl &
 546                 SECONDARY_EXEC_WBINVD_EXITING;
 547 }
 548
 549 static inline bool report_flexpriority(void)
 550 {
 551         return flexpriority_enabled;
 552 }
 553
 554 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 555 {
 556         int i;
 557
 558         for (i = 0; i < vmx->nmsrs; ++i)
 559                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 560                         return i;
 561         return -1;
 562 }
 563
 564 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 565 {
 566     struct {
 567         u64 vpid : 16;
 568         u64 rsvd : 48;
 569         u64 gva;
 570     } operand = { vpid, 0, gva };
 571
 572     asm volatile (__ex(ASM_VMX_INVVPID)
 573                   /* CF==1 or ZF==1 --> rc = -1 */
 574                   "; ja 1f ; ud2 ; 1:"
 575                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 576 }
 577
 578 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 579 {
 580         struct {
 581                 u64 eptp, gpa;
 582         } operand = {eptp, gpa};
 583
 584         asm volatile (__ex(ASM_VMX_INVEPT)
 585                         /* CF==1 or ZF==1 --> rc = -1 */
 586                         "; ja 1f ; ud2 ; 1:\n"
 587                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 588 }
 589
 590 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 591 {
 592         int i;
 593
 594         i = __find_msr_index(vmx, msr);
 595         if (i >= 0)
 596                 return &vmx->guest_msrs[i];
 597         return NULL;
 598 }
 599
 600 static void vmcs_clear(struct vmcs *vmcs)
 601 {
 602         u64 phys_addr = __pa(vmcs);
 603         u8 error;
 604
 605         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 606                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 607                       : "cc", "memory");
 608         if (error)
 609                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 610                        vmcs, phys_addr);
 611 }
 612
 613 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 614 {
 615         vmcs_clear(loaded_vmcs->vmcs);
 616         loaded_vmcs->cpu = -1;
 617         loaded_vmcs->launched = 0;
 618 }
 619
 620 static void vmcs_load(struct vmcs *vmcs)
 621 {
 622         u64 phys_addr = __pa(vmcs);
 623         u8 error;
 624
 625         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 626                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 627                         : "cc", "memory");
 628         if (error)
 629                 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 630                        vmcs, phys_addr);
 631 }
 632
 633 static void __loaded_vmcs_clear(void *arg)
 634 {
 635         struct loaded_vmcs *loaded_vmcs = arg;
 636         int cpu = raw_smp_processor_id();
 637
 638         if (loaded_vmcs->cpu != cpu)
 639                 return; /* vcpu migration can race with cpu offline */
 640         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 641                 per_cpu(current_vmcs, cpu) = NULL;
 642         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 643         loaded_vmcs_init(loaded_vmcs);
 644 }
 645
 646 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 647 {
 648         if (loaded_vmcs->cpu != -1)
 649                 smp_call_function_single(
 650                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
 651 }
 652
 653 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
 654 {
 655         if (vmx->vpid == 0)
 656                 return;
 657
 658         if (cpu_has_vmx_invvpid_single())
 659                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 660 }
 661
 662 static inline void vpid_sync_vcpu_global(void)
 663 {
 664         if (cpu_has_vmx_invvpid_global())
 665                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
 666 }
 667
 668 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
 669 {
 670         if (cpu_has_vmx_invvpid_single())
 671                 vpid_sync_vcpu_single(vmx);
 672         else
 673                 vpid_sync_vcpu_global();
 674 }
 675
 676 static inline void ept_sync_global(void)
 677 {
 678         if (cpu_has_vmx_invept_global())
 679                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 680 }
 681
 682 static inline void ept_sync_context(u64 eptp)
 683 {
 684         if (enable_ept) {
 685                 if (cpu_has_vmx_invept_context())
 686                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 687                 else
 688                         ept_sync_global();
 689         }
 690 }
 691
 692 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 693 {
 694         if (enable_ept) {
 695                 if (cpu_has_vmx_invept_individual_addr())
 696                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 697                                         eptp, gpa);
 698                 else
 699                         ept_sync_context(eptp);
 700         }
 701 }
 702
 703 static __always_inline unsigned long vmcs_readl(unsigned long field)
 704 {
 705         unsigned long value;
 706
 707         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
 708                       : "=a"(value) : "d"(field) : "cc");
 709         return value;
 710 }
 711
 712 static __always_inline u16 vmcs_read16(unsigned long field)
 713 {
 714         return vmcs_readl(field);
 715 }
 716
 717 static __always_inline u32 vmcs_read32(unsigned long field)
 718 {
 719         return vmcs_readl(field);
 720 }
 721
 722 static __always_inline u64 vmcs_read64(unsigned long field)
 723 {
 724 #ifdef CONFIG_X86_64
 725         return vmcs_readl(field);
 726 #else
 727         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 728 #endif
 729 }
 730
 731 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 732 {
 733         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 734                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 735         dump_stack();
 736 }
 737
 738 static void vmcs_writel(unsigned long field, unsigned long value)
 739 {
 740         u8 error;
 741
 742         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 743                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 744         if (unlikely(error))
 745                 vmwrite_error(field, value);
 746 }
 747
 748 static void vmcs_write16(unsigned long field, u16 value)
 749 {
 750         vmcs_writel(field, value);
 751 }
 752
 753 static void vmcs_write32(unsigned long field, u32 value)
 754 {
 755         vmcs_writel(field, value);
 756 }
 757
 758 static void vmcs_write64(unsigned long field, u64 value)
 759 {
 760         vmcs_writel(field, value);
 761 #ifndef CONFIG_X86_64
 762         asm volatile ("");
 763         vmcs_writel(field+1, value >> 32);
 764 #endif
 765 }
 766
 767 static void vmcs_clear_bits(unsigned long field, u32 mask)
 768 {
 769         vmcs_writel(field, vmcs_readl(field) & ~mask);
 770 }
 771
 772 static void vmcs_set_bits(unsigned long field, u32 mask)
 773 {
 774         vmcs_writel(field, vmcs_readl(field) | mask);
 775 }
 776
 777 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
 778 {
 779         vmx->segment_cache.bitmask = 0;
 780 }
 781
 782 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
 783                                        unsigned field)
 784 {
 785         bool ret;
 786         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
 787
 788         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
 789                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
 790                 vmx->segment_cache.bitmask = 0;
 791         }
 792         ret = vmx->segment_cache.bitmask & mask;
 793         vmx->segment_cache.bitmask |= mask;
 794         return ret;
 795 }
 796
 797 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
 798 {
 799         u16 *p = &vmx->segment_cache.seg[seg].selector;
 800
 801         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
 802                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
 803         return *p;
 804 }
 805
 806 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
 807 {
 808         ulong *p = &vmx->segment_cache.seg[seg].base;
 809
 810         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
 811                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
 812         return *p;
 813 }
 814
 815 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
 816 {
 817         u32 *p = &vmx->segment_cache.seg[seg].limit;
 818
 819         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
 820                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
 821         return *p;
 822 }
 823
 824 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
 825 {
 826         u32 *p = &vmx->segment_cache.seg[seg].ar;
 827
 828         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
 829                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
 830         return *p;
 831 }
 832
 833 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 834 {
 835         u32 eb;
 836
 837         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 838              (1u << NM_VECTOR) | (1u << DB_VECTOR);
 839         if ((vcpu->guest_debug &
 840              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 841             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 842                 eb |= 1u << BP_VECTOR;
 843         if (to_vmx(vcpu)->rmode.vm86_active)
 844                 eb = ~0;
 845         if (enable_ept)
 846                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 847         if (vcpu->fpu_active)
 848                 eb &= ~(1u << NM_VECTOR);
 849         vmcs_write32(EXCEPTION_BITMAP, eb);
 850 }
 851
 852 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 853 {
 854         unsigned i;
 855         struct msr_autoload *m = &vmx->msr_autoload;
 856
 857         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
 858                 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
 859                 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
 860                 return;
 861         }
 862
 863         for (i = 0; i < m->nr; ++i)
 864                 if (m->guest[i].index == msr)
 865                         break;
 866
 867         if (i == m->nr)
 868                 return;
 869         --m->nr;
 870         m->guest[i] = m->guest[m->nr];
 871         m->host[i] = m->host[m->nr];
 872         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
 873         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
 874 }
 875
 876 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 877                                   u64 guest_val, u64 host_val)
 878 {
 879         unsigned i;
 880         struct msr_autoload *m = &vmx->msr_autoload;
 881
 882         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
 883                 vmcs_write64(GUEST_IA32_EFER, guest_val);
 884                 vmcs_write64(HOST_IA32_EFER, host_val);
 885                 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
 886                 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
 887                 return;
 888         }
 889
 890         for (i = 0; i < m->nr; ++i)
 891                 if (m->guest[i].index == msr)
 892                         break;
 893
 894         if (i == m->nr) {
 895                 ++m->nr;
 896                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
 897                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
 898         }
 899
 900         m->guest[i].index = msr;
 901         m->guest[i].value = guest_val;
 902         m->host[i].index = msr;
 903         m->host[i].value = host_val;
 904 }
 905
 906 static void reload_tss(void)
 907 {
 908         /*
 909          * VT restores TR but not its size.  Useless.
 910          */
 911         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
 912         struct desc_struct *descs;
 913
 914         descs = (void *)gdt->address;
 915         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 916         load_TR_desc();
 917 }
 918
 919 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 920 {
 921         u64 guest_efer;
 922         u64 ignore_bits;
 923
 924         guest_efer = vmx->vcpu.arch.efer;
 925
 926         /*
 927          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 928          * outside long mode
 929          */
 930         ignore_bits = EFER_NX | EFER_SCE;
 931 #ifdef CONFIG_X86_64
 932         ignore_bits |= EFER_LMA | EFER_LME;
 933         /* SCE is meaningful only in long mode on Intel */
 934         if (guest_efer & EFER_LMA)
 935                 ignore_bits &= ~(u64)EFER_SCE;
 936 #endif
 937         guest_efer &= ~ignore_bits;
 938         guest_efer |= host_efer & ignore_bits;
 939         vmx->guest_msrs[efer_offset].data = guest_efer;
 940         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
 941
 942         clear_atomic_switch_msr(vmx, MSR_EFER);
 943         /* On ept, can't emulate nx, and must switch nx atomically */
 944         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
 945                 guest_efer = vmx->vcpu.arch.efer;
 946                 if (!(guest_efer & EFER_LMA))
 947                         guest_efer &= ~EFER_LME;
 948                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
 949                 return false;
 950         }
 951
 952         return true;
 953 }
 954
 955 static unsigned long segment_base(u16 selector)
 956 {
 957         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
 958         struct desc_struct *d;
 959         unsigned long table_base;
 960         unsigned long v;
 961
 962         if (!(selector & ~3))
 963                 return 0;
 964
 965         table_base = gdt->address;
 966
 967         if (selector & 4) {           /* from ldt */
 968                 u16 ldt_selector = kvm_read_ldt();
 969
 970                 if (!(ldt_selector & ~3))
 971                         return 0;
 972
 973                 table_base = segment_base(ldt_selector);
 974         }
 975         d = (struct desc_struct *)(table_base + (selector & ~7));
 976         v = get_desc_base(d);
 977 #ifdef CONFIG_X86_64
 978        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
 979                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
 980 #endif
 981         return v;
 982 }
 983
 984 static inline unsigned long kvm_read_tr_base(void)
 985 {
 986         u16 tr;
 987         asm("str %0" : "=g"(tr));
 988         return segment_base(tr);
 989 }
 990
 991 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 992 {
 993         struct vcpu_vmx *vmx = to_vmx(vcpu);
 994         int i;
 995
 996         if (vmx->host_state.loaded)
 997                 return;
 998
 999         vmx->host_state.loaded = 1;
1000         /*
1001          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1002          * allow segment selectors with cpl > 0 or ti == 1.
1003          */
1004         vmx->host_state.ldt_sel = kvm_read_ldt();
1005         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1006         savesegment(fs, vmx->host_state.fs_sel);
1007         if (!(vmx->host_state.fs_sel & 7)) {
1008                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1009                 vmx->host_state.fs_reload_needed = 0;
1010         } else {
1011                 vmcs_write16(HOST_FS_SELECTOR, 0);
1012                 vmx->host_state.fs_reload_needed = 1;
1013         }
1014         savesegment(gs, vmx->host_state.gs_sel);
1015         if (!(vmx->host_state.gs_sel & 7))
1016                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1017         else {
1018                 vmcs_write16(HOST_GS_SELECTOR, 0);
1019                 vmx->host_state.gs_ldt_reload_needed = 1;
1020         }
1021
1022 #ifdef CONFIG_X86_64
1023         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1024         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1025 #else
1026         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1027         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1028 #endif
1029
1030 #ifdef CONFIG_X86_64
1031         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1032         if (is_long_mode(&vmx->vcpu))
1033                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1034 #endif
1035         for (i = 0; i < vmx->save_nmsrs; ++i)
1036                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1037                                    vmx->guest_msrs[i].data,
1038                                    vmx->guest_msrs[i].mask);
1039 }
1040
1041 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1042 {
1043         if (!vmx->host_state.loaded)
1044                 return;
1045
1046         ++vmx->vcpu.stat.host_state_reload;
1047         vmx->host_state.loaded = 0;
1048 #ifdef CONFIG_X86_64
1049         if (is_long_mode(&vmx->vcpu))
1050                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1051 #endif
1052         if (vmx->host_state.gs_ldt_reload_needed) {
1053                 kvm_load_ldt(vmx->host_state.ldt_sel);
1054 #ifdef CONFIG_X86_64
1055                 load_gs_index(vmx->host_state.gs_sel);
1056 #else
1057                 loadsegment(gs, vmx->host_state.gs_sel);
1058 #endif
1059         }
1060         if (vmx->host_state.fs_reload_needed)
1061                 loadsegment(fs, vmx->host_state.fs_sel);
1062         reload_tss();
1063 #ifdef CONFIG_X86_64
1064         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1065 #endif
1066         if (current_thread_info()->status & TS_USEDFPU)
1067                 clts();
1068         load_gdt(&__get_cpu_var(host_gdt));
1069 }
1070
1071 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1072 {
1073         preempt_disable();
1074         __vmx_load_host_state(vmx);
1075         preempt_enable();
1076 }
1077
1078 /*
1079  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1080  * vcpu mutex is already taken.
1081  */
1082 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1083 {
1084         struct vcpu_vmx *vmx = to_vmx(vcpu);
1085         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1086
1087         if (!vmm_exclusive)
1088                 kvm_cpu_vmxon(phys_addr);
1089         else if (vmx->loaded_vmcs->cpu != cpu)
1090                 loaded_vmcs_clear(vmx->loaded_vmcs);
1091
1092         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1093                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1094                 vmcs_load(vmx->loaded_vmcs->vmcs);
1095         }
1096
1097         if (vmx->loaded_vmcs->cpu != cpu) {
1098                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1099                 unsigned long sysenter_esp;
1100
1101                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1102                 local_irq_disable();
1103                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1104                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1105                 local_irq_enable();
1106
1107                 /*
1108                  * Linux uses per-cpu TSS and GDT, so set these when switching
1109                  * processors.
1110                  */
1111                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1112                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1113
1114                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1115                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1116                 vmx->loaded_vmcs->cpu = cpu;
1117         }
1118 }
1119
1120 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1121 {
1122         __vmx_load_host_state(to_vmx(vcpu));
1123         if (!vmm_exclusive) {
1124                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1125                 vcpu->cpu = -1;
1126                 kvm_cpu_vmxoff();
1127         }
1128 }
1129
1130 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1131 {
1132         ulong cr0;
1133
1134         if (vcpu->fpu_active)
1135                 return;
1136         vcpu->fpu_active = 1;
1137         cr0 = vmcs_readl(GUEST_CR0);
1138         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1139         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1140         vmcs_writel(GUEST_CR0, cr0);
1141         update_exception_bitmap(vcpu);
1142         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1143         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1144 }
1145
1146 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1147
1148 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1149 {
1150         vmx_decache_cr0_guest_bits(vcpu);
1151         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1152         update_exception_bitmap(vcpu);
1153         vcpu->arch.cr0_guest_owned_bits = 0;
1154         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1155         vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1156 }
1157
1158 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1159 {
1160         unsigned long rflags, save_rflags;
1161
1162         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1163                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1164                 rflags = vmcs_readl(GUEST_RFLAGS);
1165                 if (to_vmx(vcpu)->rmode.vm86_active) {
1166                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1167                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1168                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1169                 }
1170                 to_vmx(vcpu)->rflags = rflags;
1171         }
1172         return to_vmx(vcpu)->rflags;
1173 }
1174
1175 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1176 {
1177         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1178         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1179         to_vmx(vcpu)->rflags = rflags;
1180         if (to_vmx(vcpu)->rmode.vm86_active) {
1181                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1182                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1183         }
1184         vmcs_writel(GUEST_RFLAGS, rflags);
1185 }
1186
1187 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1188 {
1189         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1190         int ret = 0;
1191
1192         if (interruptibility & GUEST_INTR_STATE_STI)
1193                 ret |= KVM_X86_SHADOW_INT_STI;
1194         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1195                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1196
1197         return ret & mask;
1198 }
1199
1200 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1201 {
1202         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1203         u32 interruptibility = interruptibility_old;
1204
1205         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1206
1207         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1208                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1209         else if (mask & KVM_X86_SHADOW_INT_STI)
1210                 interruptibility |= GUEST_INTR_STATE_STI;
1211
1212         if ((interruptibility != interruptibility_old))
1213                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1214 }
1215
1216 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1217 {
1218         unsigned long rip;
1219
1220         rip = kvm_rip_read(vcpu);
1221         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1222         kvm_rip_write(vcpu, rip);
1223
1224         /* skipping an emulated instruction also counts */
1225         vmx_set_interrupt_shadow(vcpu, 0);
1226 }
1227
1228 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1229 {
1230         /* Ensure that we clear the HLT state in the VMCS.  We don't need to
1231          * explicitly skip the instruction because if the HLT state is set, then
1232          * the instruction is already executing and RIP has already been
1233          * advanced. */
1234         if (!yield_on_hlt &&
1235             vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1236                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1237 }
1238
1239 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1240                                 bool has_error_code, u32 error_code,
1241                                 bool reinject)
1242 {
1243         struct vcpu_vmx *vmx = to_vmx(vcpu);
1244         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1245
1246         if (has_error_code) {
1247                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1248                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1249         }
1250
1251         if (vmx->rmode.vm86_active) {
1252                 int inc_eip = 0;
1253                 if (kvm_exception_is_soft(nr))
1254                         inc_eip = vcpu->arch.event_exit_inst_len;
1255                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1256                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1257                 return;
1258         }
1259
1260         if (kvm_exception_is_soft(nr)) {
1261                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1262                              vmx->vcpu.arch.event_exit_inst_len);
1263                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1264         } else
1265                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1266
1267         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1268         vmx_clear_hlt(vcpu);
1269 }
1270
1271 static bool vmx_rdtscp_supported(void)
1272 {
1273         return cpu_has_vmx_rdtscp();
1274 }
1275
1276 /*
1277  * Swap MSR entry in host/guest MSR entry array.
1278  */
1279 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1280 {
1281         struct shared_msr_entry tmp;
1282
1283         tmp = vmx->guest_msrs[to];
1284         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1285         vmx->guest_msrs[from] = tmp;
1286 }
1287
1288 /*
1289  * Set up the vmcs to automatically save and restore system
1290  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1291  * mode, as fiddling with msrs is very expensive.
1292  */
1293 static void setup_msrs(struct vcpu_vmx *vmx)
1294 {
1295         int save_nmsrs, index;
1296         unsigned long *msr_bitmap;
1297
1298         vmx_load_host_state(vmx);
1299         save_nmsrs = 0;
1300 #ifdef CONFIG_X86_64
1301         if (is_long_mode(&vmx->vcpu)) {
1302                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1303                 if (index >= 0)
1304                         move_msr_up(vmx, index, save_nmsrs++);
1305                 index = __find_msr_index(vmx, MSR_LSTAR);
1306                 if (index >= 0)
1307                         move_msr_up(vmx, index, save_nmsrs++);
1308                 index = __find_msr_index(vmx, MSR_CSTAR);
1309                 if (index >= 0)
1310                         move_msr_up(vmx, index, save_nmsrs++);
1311                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1312                 if (index >= 0 && vmx->rdtscp_enabled)
1313                         move_msr_up(vmx, index, save_nmsrs++);
1314                 /*
1315                  * MSR_STAR is only needed on long mode guests, and only
1316                  * if efer.sce is enabled.
1317                  */
1318                 index = __find_msr_index(vmx, MSR_STAR);
1319                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1320                         move_msr_up(vmx, index, save_nmsrs++);
1321         }
1322 #endif
1323         index = __find_msr_index(vmx, MSR_EFER);
1324         if (index >= 0 && update_transition_efer(vmx, index))
1325                 move_msr_up(vmx, index, save_nmsrs++);
1326
1327         vmx->save_nmsrs = save_nmsrs;
1328
1329         if (cpu_has_vmx_msr_bitmap()) {
1330                 if (is_long_mode(&vmx->vcpu))
1331                         msr_bitmap = vmx_msr_bitmap_longmode;
1332                 else
1333                         msr_bitmap = vmx_msr_bitmap_legacy;
1334
1335                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1336         }
1337 }
1338
1339 /*
1340  * reads and returns guest's timestamp counter "register"
1341  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1342  */
1343 static u64 guest_read_tsc(void)
1344 {
1345         u64 host_tsc, tsc_offset;
1346
1347         rdtscll(host_tsc);
1348         tsc_offset = vmcs_read64(TSC_OFFSET);
1349         return host_tsc + tsc_offset;
1350 }
1351
1352 /*
1353  * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1354  * ioctl. In this case the call-back should update internal vmx state to make
1355  * the changes effective.
1356  */
1357 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1358 {
1359         /* Nothing to do here */
1360 }
1361
1362 /*
1363  * writes 'offset' into guest's timestamp counter offset register
1364  */
1365 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1366 {
1367         vmcs_write64(TSC_OFFSET, offset);
1368 }
1369
1370 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1371 {
1372         u64 offset = vmcs_read64(TSC_OFFSET);
1373         vmcs_write64(TSC_OFFSET, offset + adjustment);
1374 }
1375
1376 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1377 {
1378         return target_tsc - native_read_tsc();
1379 }
1380
1381 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1382 {
1383         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1384         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1385 }
1386
1387 /*
1388  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1389  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1390  * all guests if the "nested" module option is off, and can also be disabled
1391  * for a single guest by disabling its VMX cpuid bit.
1392  */
1393 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1394 {
1395         return nested && guest_cpuid_has_vmx(vcpu);
1396 }
1397
1398 /*
1399  * Reads an msr value (of 'msr_index') into 'pdata'.
1400  * Returns 0 on success, non-0 otherwise.
1401  * Assumes vcpu_load() was already called.
1402  */
1403 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1404 {
1405         u64 data;
1406         struct shared_msr_entry *msr;
1407
1408         if (!pdata) {
1409                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1410                 return -EINVAL;
1411         }
1412
1413         switch (msr_index) {
1414 #ifdef CONFIG_X86_64
1415         case MSR_FS_BASE:
1416                 data = vmcs_readl(GUEST_FS_BASE);
1417                 break;
1418         case MSR_GS_BASE:
1419                 data = vmcs_readl(GUEST_GS_BASE);
1420                 break;
1421         case MSR_KERNEL_GS_BASE:
1422                 vmx_load_host_state(to_vmx(vcpu));
1423                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1424                 break;
1425 #endif
1426         case MSR_EFER:
1427                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1428         case MSR_IA32_TSC:
1429                 data = guest_read_tsc();
1430                 break;
1431         case MSR_IA32_SYSENTER_CS:
1432                 data = vmcs_read32(GUEST_SYSENTER_CS);
1433                 break;
1434         case MSR_IA32_SYSENTER_EIP:
1435                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1436                 break;
1437         case MSR_IA32_SYSENTER_ESP:
1438                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1439                 break;
1440         case MSR_TSC_AUX:
1441                 if (!to_vmx(vcpu)->rdtscp_enabled)
1442                         return 1;
1443                 /* Otherwise falls through */
1444         default:
1445                 vmx_load_host_state(to_vmx(vcpu));
1446                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1447                 if (msr) {
1448                         vmx_load_host_state(to_vmx(vcpu));
1449                         data = msr->data;
1450                         break;
1451                 }
1452                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1453         }
1454
1455         *pdata = data;
1456         return 0;
1457 }
1458
1459 /*
1460  * Writes msr value into into the appropriate "register".
1461  * Returns 0 on success, non-0 otherwise.
1462  * Assumes vcpu_load() was already called.
1463  */
1464 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1465 {
1466         struct vcpu_vmx *vmx = to_vmx(vcpu);
1467         struct shared_msr_entry *msr;
1468         int ret = 0;
1469
1470         switch (msr_index) {
1471         case MSR_EFER:
1472                 vmx_load_host_state(vmx);
1473                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1474                 break;
1475 #ifdef CONFIG_X86_64
1476         case MSR_FS_BASE:
1477                 vmx_segment_cache_clear(vmx);
1478                 vmcs_writel(GUEST_FS_BASE, data);
1479                 break;
1480         case MSR_GS_BASE:
1481                 vmx_segment_cache_clear(vmx);
1482                 vmcs_writel(GUEST_GS_BASE, data);
1483                 break;
1484         case MSR_KERNEL_GS_BASE:
1485                 vmx_load_host_state(vmx);
1486                 vmx->msr_guest_kernel_gs_base = data;
1487                 break;
1488 #endif
1489         case MSR_IA32_SYSENTER_CS:
1490                 vmcs_write32(GUEST_SYSENTER_CS, data);
1491                 break;
1492         case MSR_IA32_SYSENTER_EIP:
1493                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1494                 break;
1495         case MSR_IA32_SYSENTER_ESP:
1496                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1497                 break;
1498         case MSR_IA32_TSC:
1499                 kvm_write_tsc(vcpu, data);
1500                 break;
1501         case MSR_IA32_CR_PAT:
1502                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1503                         vmcs_write64(GUEST_IA32_PAT, data);
1504                         vcpu->arch.pat = data;
1505                         break;
1506                 }
1507                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1508                 break;
1509         case MSR_TSC_AUX:
1510                 if (!vmx->rdtscp_enabled)
1511                         return 1;
1512                 /* Check reserved bit, higher 32 bits should be zero */
1513                 if ((data >> 32) != 0)
1514                         return 1;
1515                 /* Otherwise falls through */
1516         default:
1517                 msr = find_msr_entry(vmx, msr_index);
1518                 if (msr) {
1519                         vmx_load_host_state(vmx);
1520                         msr->data = data;
1521                         break;
1522                 }
1523                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1524         }
1525
1526         return ret;
1527 }
1528
1529 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1530 {
1531         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1532         switch (reg) {
1533         case VCPU_REGS_RSP:
1534                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1535                 break;
1536         case VCPU_REGS_RIP:
1537                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1538                 break;
1539         case VCPU_EXREG_PDPTR:
1540                 if (enable_ept)
1541                         ept_save_pdptrs(vcpu);
1542                 break;
1543         default:
1544                 break;
1545         }
1546 }
1547
1548 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1549 {
1550         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1551                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1552         else
1553                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1554
1555         update_exception_bitmap(vcpu);
1556 }
1557
1558 static __init int cpu_has_kvm_support(void)
1559 {
1560         return cpu_has_vmx();
1561 }
1562
1563 static __init int vmx_disabled_by_bios(void)
1564 {
1565         u64 msr;
1566
1567         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1568         if (msr & FEATURE_CONTROL_LOCKED) {
1569                 /* launched w/ TXT and VMX disabled */
1570                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1571                         && tboot_enabled())
1572                         return 1;
1573                 /* launched w/o TXT and VMX only enabled w/ TXT */
1574                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1575                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1576                         && !tboot_enabled()) {
1577                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
1578                                 "activate TXT before enabling KVM\n");
1579                         return 1;
1580                 }
1581                 /* launched w/o TXT and VMX disabled */
1582                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1583                         && !tboot_enabled())
1584                         return 1;
1585         }
1586
1587         return 0;
1588 }
1589
1590 static void kvm_cpu_vmxon(u64 addr)
1591 {
1592         asm volatile (ASM_VMX_VMXON_RAX
1593                         : : "a"(&addr), "m"(addr)
1594                         : "memory", "cc");
1595 }
1596
1597 static int hardware_enable(void *garbage)
1598 {
1599         int cpu = raw_smp_processor_id();
1600         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1601         u64 old, test_bits;
1602
1603         if (read_cr4() & X86_CR4_VMXE)
1604                 return -EBUSY;
1605
1606         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
1607         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1608
1609         test_bits = FEATURE_CONTROL_LOCKED;
1610         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1611         if (tboot_enabled())
1612                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1613
1614         if ((old & test_bits) != test_bits) {
1615                 /* enable and lock */
1616                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1617         }
1618         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1619
1620         if (vmm_exclusive) {
1621                 kvm_cpu_vmxon(phys_addr);
1622                 ept_sync_global();
1623         }
1624
1625         store_gdt(&__get_cpu_var(host_gdt));
1626
1627         return 0;
1628 }
1629
1630 static void vmclear_local_loaded_vmcss(void)
1631 {
1632         int cpu = raw_smp_processor_id();
1633         struct loaded_vmcs *v, *n;
1634
1635         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
1636                                  loaded_vmcss_on_cpu_link)
1637                 __loaded_vmcs_clear(v);
1638 }
1639
1640
1641 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1642  * tricks.
1643  */
1644 static void kvm_cpu_vmxoff(void)
1645 {
1646         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1647 }
1648
1649 static void hardware_disable(void *garbage)
1650 {
1651         if (vmm_exclusive) {
1652                 vmclear_local_loaded_vmcss();
1653                 kvm_cpu_vmxoff();
1654         }
1655         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1656 }
1657
1658 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1659                                       u32 msr, u32 *result)
1660 {
1661         u32 vmx_msr_low, vmx_msr_high;
1662         u32 ctl = ctl_min | ctl_opt;
1663
1664         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1665
1666         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1667         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1668
1669         /* Ensure minimum (required) set of control bits are supported. */
1670         if (ctl_min & ~ctl)
1671                 return -EIO;
1672
1673         *result = ctl;
1674         return 0;
1675 }
1676
1677 static __init bool allow_1_setting(u32 msr, u32 ctl)
1678 {
1679         u32 vmx_msr_low, vmx_msr_high;
1680
1681         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1682         return vmx_msr_high & ctl;
1683 }
1684
1685 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1686 {
1687         u32 vmx_msr_low, vmx_msr_high;
1688         u32 min, opt, min2, opt2;
1689         u32 _pin_based_exec_control = 0;
1690         u32 _cpu_based_exec_control = 0;
1691         u32 _cpu_based_2nd_exec_control = 0;
1692         u32 _vmexit_control = 0;
1693         u32 _vmentry_control = 0;
1694
1695         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1696         opt = PIN_BASED_VIRTUAL_NMIS;
1697         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1698                                 &_pin_based_exec_control) < 0)
1699                 return -EIO;
1700
1701         min =
1702 #ifdef CONFIG_X86_64
1703               CPU_BASED_CR8_LOAD_EXITING |
1704               CPU_BASED_CR8_STORE_EXITING |
1705 #endif
1706               CPU_BASED_CR3_LOAD_EXITING |
1707               CPU_BASED_CR3_STORE_EXITING |
1708               CPU_BASED_USE_IO_BITMAPS |
1709               CPU_BASED_MOV_DR_EXITING |
1710               CPU_BASED_USE_TSC_OFFSETING |
1711               CPU_BASED_MWAIT_EXITING |
1712               CPU_BASED_MONITOR_EXITING |
1713               CPU_BASED_INVLPG_EXITING;
1714
1715         if (yield_on_hlt)
1716                 min |= CPU_BASED_HLT_EXITING;
1717
1718         opt = CPU_BASED_TPR_SHADOW |
1719               CPU_BASED_USE_MSR_BITMAPS |
1720               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1721         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1722                                 &_cpu_based_exec_control) < 0)
1723                 return -EIO;
1724 #ifdef CONFIG_X86_64
1725         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1726                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1727                                            ~CPU_BASED_CR8_STORE_EXITING;
1728 #endif
1729         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1730                 min2 = 0;
1731                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1732                         SECONDARY_EXEC_WBINVD_EXITING |
1733                         SECONDARY_EXEC_ENABLE_VPID |
1734                         SECONDARY_EXEC_ENABLE_EPT |
1735                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
1736                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1737                         SECONDARY_EXEC_RDTSCP;
1738                 if (adjust_vmx_controls(min2, opt2,
1739                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1740                                         &_cpu_based_2nd_exec_control) < 0)
1741                         return -EIO;
1742         }
1743 #ifndef CONFIG_X86_64
1744         if (!(_cpu_based_2nd_exec_control &
1745                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1746                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1747 #endif
1748         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1749                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1750                    enabled */
1751                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1752                                              CPU_BASED_CR3_STORE_EXITING |
1753                                              CPU_BASED_INVLPG_EXITING);
1754                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1755                       vmx_capability.ept, vmx_capability.vpid);
1756         }
1757
1758         min = 0;
1759 #ifdef CONFIG_X86_64
1760         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1761 #endif
1762         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1763         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1764                                 &_vmexit_control) < 0)
1765                 return -EIO;
1766
1767         min = 0;
1768         opt = VM_ENTRY_LOAD_IA32_PAT;
1769         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1770                                 &_vmentry_control) < 0)
1771                 return -EIO;
1772
1773         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1774
1775         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1776         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1777                 return -EIO;
1778
1779 #ifdef CONFIG_X86_64
1780         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1781         if (vmx_msr_high & (1u<<16))
1782                 return -EIO;
1783 #endif
1784
1785         /* Require Write-Back (WB) memory type for VMCS accesses. */
1786         if (((vmx_msr_high >> 18) & 15) != 6)
1787                 return -EIO;
1788
1789         vmcs_conf->size = vmx_msr_high & 0x1fff;
1790         vmcs_conf->order = get_order(vmcs_config.size);
1791         vmcs_conf->revision_id = vmx_msr_low;
1792
1793         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1794         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1795         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1796         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1797         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1798
1799         cpu_has_load_ia32_efer =
1800                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
1801                                 VM_ENTRY_LOAD_IA32_EFER)
1802                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
1803                                    VM_EXIT_LOAD_IA32_EFER);
1804
1805         return 0;
1806 }
1807
1808 static struct vmcs *alloc_vmcs_cpu(int cpu)
1809 {
1810         int node = cpu_to_node(cpu);
1811         struct page *pages;
1812         struct vmcs *vmcs;
1813
1814         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1815         if (!pages)
1816                 return NULL;
1817         vmcs = page_address(pages);
1818         memset(vmcs, 0, vmcs_config.size);
1819         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1820         return vmcs;
1821 }
1822
1823 static struct vmcs *alloc_vmcs(void)
1824 {
1825         return alloc_vmcs_cpu(raw_smp_processor_id());
1826 }
1827
1828 static void free_vmcs(struct vmcs *vmcs)
1829 {
1830         free_pages((unsigned long)vmcs, vmcs_config.order);
1831 }
1832
1833 /*
1834  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
1835  */
1836 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
1837 {
1838         if (!loaded_vmcs->vmcs)
1839                 return;
1840         loaded_vmcs_clear(loaded_vmcs);
1841         free_vmcs(loaded_vmcs->vmcs);
1842         loaded_vmcs->vmcs = NULL;
1843 }
1844
1845 static void free_kvm_area(void)
1846 {
1847         int cpu;
1848
1849         for_each_possible_cpu(cpu) {
1850                 free_vmcs(per_cpu(vmxarea, cpu));
1851                 per_cpu(vmxarea, cpu) = NULL;
1852         }
1853 }
1854
1855 static __init int alloc_kvm_area(void)
1856 {
1857         int cpu;
1858
1859         for_each_possible_cpu(cpu) {
1860                 struct vmcs *vmcs;
1861
1862                 vmcs = alloc_vmcs_cpu(cpu);
1863                 if (!vmcs) {
1864                         free_kvm_area();
1865                         return -ENOMEM;
1866                 }
1867
1868                 per_cpu(vmxarea, cpu) = vmcs;
1869         }
1870         return 0;
1871 }
1872
1873 static __init int hardware_setup(void)
1874 {
1875         if (setup_vmcs_config(&vmcs_config) < 0)
1876                 return -EIO;
1877
1878         if (boot_cpu_has(X86_FEATURE_NX))
1879                 kvm_enable_efer_bits(EFER_NX);
1880
1881         if (!cpu_has_vmx_vpid())
1882                 enable_vpid = 0;
1883
1884         if (!cpu_has_vmx_ept() ||
1885             !cpu_has_vmx_ept_4levels()) {
1886                 enable_ept = 0;
1887                 enable_unrestricted_guest = 0;
1888         }
1889
1890         if (!cpu_has_vmx_unrestricted_guest())
1891                 enable_unrestricted_guest = 0;
1892
1893         if (!cpu_has_vmx_flexpriority())
1894                 flexpriority_enabled = 0;
1895
1896         if (!cpu_has_vmx_tpr_shadow())
1897                 kvm_x86_ops->update_cr8_intercept = NULL;
1898
1899         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1900                 kvm_disable_largepages();
1901
1902         if (!cpu_has_vmx_ple())
1903                 ple_gap = 0;
1904
1905         return alloc_kvm_area();
1906 }
1907
1908 static __exit void hardware_unsetup(void)
1909 {
1910         free_kvm_area();
1911 }
1912
1913 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1914 {
1915         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1916
1917         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1918                 vmcs_write16(sf->selector, save->selector);
1919                 vmcs_writel(sf->base, save->base);
1920                 vmcs_write32(sf->limit, save->limit);
1921                 vmcs_write32(sf->ar_bytes, save->ar);
1922         } else {
1923                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1924                         << AR_DPL_SHIFT;
1925                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1926         }
1927 }
1928
1929 static void enter_pmode(struct kvm_vcpu *vcpu)
1930 {
1931         unsigned long flags;
1932         struct vcpu_vmx *vmx = to_vmx(vcpu);
1933
1934         vmx->emulation_required = 1;
1935         vmx->rmode.vm86_active = 0;
1936
1937         vmx_segment_cache_clear(vmx);
1938
1939         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
1940         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1941         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1942         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1943
1944         flags = vmcs_readl(GUEST_RFLAGS);
1945         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1946         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1947         vmcs_writel(GUEST_RFLAGS, flags);
1948
1949         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1950                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1951
1952         update_exception_bitmap(vcpu);
1953
1954         if (emulate_invalid_guest_state)
1955                 return;
1956
1957         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1958         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1959         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1960         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1961
1962         vmx_segment_cache_clear(vmx);
1963
1964         vmcs_write16(GUEST_SS_SELECTOR, 0);
1965         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1966
1967         vmcs_write16(GUEST_CS_SELECTOR,
1968                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1969         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1970 }
1971
1972 static gva_t rmode_tss_base(struct kvm *kvm)
1973 {
1974         if (!kvm->arch.tss_addr) {
1975                 struct kvm_memslots *slots;
1976                 gfn_t base_gfn;
1977
1978                 slots = kvm_memslots(kvm);
1979                 base_gfn = slots->memslots[0].base_gfn +
1980                                  kvm->memslots->memslots[0].npages - 3;
1981                 return base_gfn << PAGE_SHIFT;
1982         }
1983         return kvm->arch.tss_addr;
1984 }
1985
1986 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1987 {
1988         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1989
1990         save->selector = vmcs_read16(sf->selector);
1991         save->base = vmcs_readl(sf->base);
1992         save->limit = vmcs_read32(sf->limit);
1993         save->ar = vmcs_read32(sf->ar_bytes);
1994         vmcs_write16(sf->selector, save->base >> 4);
1995         vmcs_write32(sf->base, save->base & 0xffff0);
1996         vmcs_write32(sf->limit, 0xffff);
1997         vmcs_write32(sf->ar_bytes, 0xf3);
1998         if (save->base & 0xf)
1999                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2000                             " aligned when entering protected mode (seg=%d)",
2001                             seg);
2002 }
2003
2004 static void enter_rmode(struct kvm_vcpu *vcpu)
2005 {
2006         unsigned long flags;
2007         struct vcpu_vmx *vmx = to_vmx(vcpu);
2008
2009         if (enable_unrestricted_guest)
2010                 return;
2011
2012         vmx->emulation_required = 1;
2013         vmx->rmode.vm86_active = 1;
2014
2015         /*
2016          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2017          * vcpu. Call it here with phys address pointing 16M below 4G.
2018          */
2019         if (!vcpu->kvm->arch.tss_addr) {
2020                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2021                              "called before entering vcpu\n");
2022                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2023                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2024                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2025         }
2026
2027         vmx_segment_cache_clear(vmx);
2028
2029         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2030         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2031         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2032
2033         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2034         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2035
2036         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2037         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2038
2039         flags = vmcs_readl(GUEST_RFLAGS);
2040         vmx->rmode.save_rflags = flags;
2041
2042         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2043
2044         vmcs_writel(GUEST_RFLAGS, flags);
2045         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2046         update_exception_bitmap(vcpu);
2047
2048         if (emulate_invalid_guest_state)
2049                 goto continue_rmode;
2050
2051         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2052         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2053         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2054
2055         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
2056         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2057         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2058                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
2059         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2060
2061         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2062         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2063         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2064         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
2065
2066 continue_rmode:
2067         kvm_mmu_reset_context(vcpu);
2068 }
2069
2070 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2071 {
2072         struct vcpu_vmx *vmx = to_vmx(vcpu);
2073         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2074
2075         if (!msr)
2076                 return;
2077
2078         /*
2079          * Force kernel_gs_base reloading before EFER changes, as control
2080          * of this msr depends on is_long_mode().
2081          */
2082         vmx_load_host_state(to_vmx(vcpu));
2083         vcpu->arch.efer = efer;
2084         if (efer & EFER_LMA) {
2085                 vmcs_write32(VM_ENTRY_CONTROLS,
2086                              vmcs_read32(VM_ENTRY_CONTROLS) |
2087                              VM_ENTRY_IA32E_MODE);
2088                 msr->data = efer;
2089         } else {
2090                 vmcs_write32(VM_ENTRY_CONTROLS,
2091                              vmcs_read32(VM_ENTRY_CONTROLS) &
2092                              ~VM_ENTRY_IA32E_MODE);
2093
2094                 msr->data = efer & ~EFER_LME;
2095         }
2096         setup_msrs(vmx);
2097 }
2098
2099 #ifdef CONFIG_X86_64
2100
2101 static void enter_lmode(struct kvm_vcpu *vcpu)
2102 {
2103         u32 guest_tr_ar;
2104
2105         vmx_segment_cache_clear(to_vmx(vcpu));
2106
2107         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2108         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2109                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
2110                        __func__);
2111                 vmcs_write32(GUEST_TR_AR_BYTES,
2112                              (guest_tr_ar & ~AR_TYPE_MASK)
2113                              | AR_TYPE_BUSY_64_TSS);
2114         }
2115         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2116 }
2117
2118 static void exit_lmode(struct kvm_vcpu *vcpu)
2119 {
2120         vmcs_write32(VM_ENTRY_CONTROLS,
2121                      vmcs_read32(VM_ENTRY_CONTROLS)
2122                      & ~VM_ENTRY_IA32E_MODE);
2123         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2124 }
2125
2126 #endif
2127
2128 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2129 {
2130         vpid_sync_context(to_vmx(vcpu));
2131         if (enable_ept) {
2132                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2133                         return;
2134                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2135         }
2136 }
2137
2138 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2139 {
2140         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2141
2142         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2143         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2144 }
2145
2146 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2147 {
2148         if (enable_ept && is_paging(vcpu))
2149                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2150         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2151 }
2152
2153 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2154 {
2155         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2156
2157         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2158         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2159 }
2160
2161 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2162 {
2163         if (!test_bit(VCPU_EXREG_PDPTR,
2164                       (unsigned long *)&vcpu->arch.regs_dirty))
2165                 return;
2166
2167         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2168                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2169                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2170                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2171                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2172         }
2173 }
2174
2175 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2176 {
2177         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2178                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2179                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2180                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2181                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2182         }
2183
2184         __set_bit(VCPU_EXREG_PDPTR,
2185                   (unsigned long *)&vcpu->arch.regs_avail);
2186         __set_bit(VCPU_EXREG_PDPTR,
2187                   (unsigned long *)&vcpu->arch.regs_dirty);
2188 }
2189
2190 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2191
2192 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2193                                         unsigned long cr0,
2194                                         struct kvm_vcpu *vcpu)
2195 {
2196         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2197                 vmx_decache_cr3(vcpu);
2198         if (!(cr0 & X86_CR0_PG)) {
2199                 /* From paging/starting to nonpaging */
2200                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2201                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2202                              (CPU_BASED_CR3_LOAD_EXITING |
2203                               CPU_BASED_CR3_STORE_EXITING));
2204                 vcpu->arch.cr0 = cr0;
2205                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2206         } else if (!is_paging(vcpu)) {
2207                 /* From nonpaging to paging */
2208                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2209                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2210                              ~(CPU_BASED_CR3_LOAD_EXITING |
2211                                CPU_BASED_CR3_STORE_EXITING));
2212                 vcpu->arch.cr0 = cr0;
2213                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2214         }
2215
2216         if (!(cr0 & X86_CR0_WP))
2217                 *hw_cr0 &= ~X86_CR0_WP;
2218 }
2219
2220 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2221 {
2222         struct vcpu_vmx *vmx = to_vmx(vcpu);
2223         unsigned long hw_cr0;
2224
2225         if (enable_unrestricted_guest)
2226                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2227                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2228         else
2229                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2230
2231         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2232                 enter_pmode(vcpu);
2233
2234         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2235                 enter_rmode(vcpu);
2236
2237 #ifdef CONFIG_X86_64
2238         if (vcpu->arch.efer & EFER_LME) {
2239                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2240                         enter_lmode(vcpu);
2241                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2242                         exit_lmode(vcpu);
2243         }
2244 #endif
2245
2246         if (enable_ept)
2247                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2248
2249         if (!vcpu->fpu_active)
2250                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2251
2252         vmcs_writel(CR0_READ_SHADOW, cr0);
2253         vmcs_writel(GUEST_CR0, hw_cr0);
2254         vcpu->arch.cr0 = cr0;
2255         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2256 }
2257
2258 static u64 construct_eptp(unsigned long root_hpa)
2259 {
2260         u64 eptp;
2261
2262         /* TODO write the value reading from MSR */
2263         eptp = VMX_EPT_DEFAULT_MT |
2264                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2265         eptp |= (root_hpa & PAGE_MASK);
2266
2267         return eptp;
2268 }
2269
2270 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2271 {
2272         unsigned long guest_cr3;
2273         u64 eptp;
2274
2275         guest_cr3 = cr3;
2276         if (enable_ept) {
2277                 eptp = construct_eptp(cr3);
2278                 vmcs_write64(EPT_POINTER, eptp);
2279                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
2280                         vcpu->kvm->arch.ept_identity_map_addr;
2281                 ept_load_pdptrs(vcpu);
2282         }
2283
2284         vmx_flush_tlb(vcpu);
2285         vmcs_writel(GUEST_CR3, guest_cr3);
2286 }
2287
2288 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2289 {
2290         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
2291                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2292
2293         if (cr4 & X86_CR4_VMXE) {
2294                 /*
2295                  * To use VMXON (and later other VMX instructions), a guest
2296                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
2297                  * So basically the check on whether to allow nested VMX
2298                  * is here.
2299                  */
2300                 if (!nested_vmx_allowed(vcpu))
2301                         return 1;
2302         } else if (to_vmx(vcpu)->nested.vmxon)
2303                 return 1;
2304
2305         vcpu->arch.cr4 = cr4;
2306         if (enable_ept) {
2307                 if (!is_paging(vcpu)) {
2308                         hw_cr4 &= ~X86_CR4_PAE;
2309                         hw_cr4 |= X86_CR4_PSE;
2310                 } else if (!(cr4 & X86_CR4_PAE)) {
2311                         hw_cr4 &= ~X86_CR4_PAE;
2312                 }
2313         }
2314
2315         vmcs_writel(CR4_READ_SHADOW, cr4);
2316         vmcs_writel(GUEST_CR4, hw_cr4);
2317         return 0;
2318 }
2319
2320 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2321                             struct kvm_segment *var, int seg)
2322 {
2323         struct vcpu_vmx *vmx = to_vmx(vcpu);
2324         struct kvm_save_segment *save;
2325         u32 ar;
2326
2327         if (vmx->rmode.vm86_active
2328             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2329                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2330                 || seg == VCPU_SREG_GS)
2331             && !emulate_invalid_guest_state) {
2332                 switch (seg) {
2333                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2334                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2335                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2336                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2337                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2338                 default: BUG();
2339                 }
2340                 var->selector = save->selector;
2341                 var->base = save->base;
2342                 var->limit = save->limit;
2343                 ar = save->ar;
2344                 if (seg == VCPU_SREG_TR
2345                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
2346                         goto use_saved_rmode_seg;
2347         }
2348         var->base = vmx_read_guest_seg_base(vmx, seg);
2349         var->limit = vmx_read_guest_seg_limit(vmx, seg);
2350         var->selector = vmx_read_guest_seg_selector(vmx, seg);
2351         ar = vmx_read_guest_seg_ar(vmx, seg);
2352 use_saved_rmode_seg:
2353         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2354                 ar = 0;
2355         var->type = ar & 15;
2356         var->s = (ar >> 4) & 1;
2357         var->dpl = (ar >> 5) & 3;
2358         var->present = (ar >> 7) & 1;
2359         var->avl = (ar >> 12) & 1;
2360         var->l = (ar >> 13) & 1;
2361         var->db = (ar >> 14) & 1;
2362         var->g = (ar >> 15) & 1;
2363         var->unusable = (ar >> 16) & 1;
2364 }
2365
2366 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2367 {
2368         struct kvm_segment s;
2369
2370         if (to_vmx(vcpu)->rmode.vm86_active) {
2371                 vmx_get_segment(vcpu, &s, seg);
2372                 return s.base;
2373         }
2374         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
2375 }
2376
2377 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2378 {
2379         if (!is_protmode(vcpu))
2380                 return 0;
2381
2382         if (!is_long_mode(vcpu)
2383             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2384                 return 3;
2385
2386         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2387 }
2388
2389 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2390 {
2391         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
2392                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2393                 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
2394         }
2395         return to_vmx(vcpu)->cpl;
2396 }
2397
2398
2399 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2400 {
2401         u32 ar;
2402
2403         if (var->unusable)
2404                 ar = 1 << 16;
2405         else {
2406                 ar = var->type & 15;
2407                 ar |= (var->s & 1) << 4;
2408                 ar |= (var->dpl & 3) << 5;
2409                 ar |= (var->present & 1) << 7;
2410                 ar |= (var->avl & 1) << 12;
2411                 ar |= (var->l & 1) << 13;
2412                 ar |= (var->db & 1) << 14;
2413                 ar |= (var->g & 1) << 15;
2414         }
2415         if (ar == 0) /* a 0 value means unusable */
2416                 ar = AR_UNUSABLE_MASK;
2417
2418         return ar;
2419 }
2420
2421 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2422                             struct kvm_segment *var, int seg)
2423 {
2424         struct vcpu_vmx *vmx = to_vmx(vcpu);
2425         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2426         u32 ar;
2427
2428         vmx_segment_cache_clear(vmx);
2429
2430         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2431                 vmcs_write16(sf->selector, var->selector);
2432                 vmx->rmode.tr.selector = var->selector;
2433                 vmx->rmode.tr.base = var->base;
2434                 vmx->rmode.tr.limit = var->limit;
2435                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2436                 return;
2437         }
2438         vmcs_writel(sf->base, var->base);
2439         vmcs_write32(sf->limit, var->limit);
2440         vmcs_write16(sf->selector, var->selector);
2441         if (vmx->rmode.vm86_active && var->s) {
2442                 /*
2443                  * Hack real-mode segments into vm86 compatibility.
2444                  */
2445                 if (var->base == 0xffff0000 && var->selector == 0xf000)
2446                         vmcs_writel(sf->base, 0xf0000);
2447                 ar = 0xf3;
2448         } else
2449                 ar = vmx_segment_access_rights(var);
2450
2451         /*
2452          *   Fix the "Accessed" bit in AR field of segment registers for older
2453          * qemu binaries.
2454          *   IA32 arch specifies that at the time of processor reset the
2455          * "Accessed" bit in the AR field of segment registers is 1. And qemu
2456          * is setting it to 0 in the usedland code. This causes invalid guest
2457          * state vmexit when "unrestricted guest" mode is turned on.
2458          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
2459          * tree. Newer qemu binaries with that qemu fix would not need this
2460          * kvm hack.
2461          */
2462         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2463                 ar |= 0x1; /* Accessed */
2464
2465         vmcs_write32(sf->ar_bytes, ar);
2466         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2467 }
2468
2469 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2470 {
2471         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
2472
2473         *db = (ar >> 14) & 1;
2474         *l = (ar >> 13) & 1;
2475 }
2476
2477 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2478 {
2479         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2480         dt->address = vmcs_readl(GUEST_IDTR_BASE);
2481 }
2482
2483 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2484 {
2485         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2486         vmcs_writel(GUEST_IDTR_BASE, dt->address);
2487 }
2488
2489 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2490 {
2491         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2492         dt->address = vmcs_readl(GUEST_GDTR_BASE);
2493 }
2494
2495 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2496 {
2497         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2498         vmcs_writel(GUEST_GDTR_BASE, dt->address);
2499 }
2500
2501 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2502 {
2503         struct kvm_segment var;
2504         u32 ar;
2505
2506         vmx_get_segment(vcpu, &var, seg);
2507         ar = vmx_segment_access_rights(&var);
2508
2509         if (var.base != (var.selector << 4))
2510                 return false;
2511         if (var.limit != 0xffff)
2512                 return false;
2513         if (ar != 0xf3)
2514                 return false;
2515
2516         return true;
2517 }
2518
2519 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2520 {
2521         struct kvm_segment cs;
2522         unsigned int cs_rpl;
2523
2524         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2525         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2526
2527         if (cs.unusable)
2528                 return false;
2529         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2530                 return false;
2531         if (!cs.s)
2532                 return false;
2533         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2534                 if (cs.dpl > cs_rpl)
2535                         return false;
2536         } else {
2537                 if (cs.dpl != cs_rpl)
2538                         return false;
2539         }
2540         if (!cs.present)
2541                 return false;
2542
2543         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2544         return true;
2545 }
2546
2547 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2548 {
2549         struct kvm_segment ss;
2550         unsigned int ss_rpl;
2551
2552         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2553         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2554
2555         if (ss.unusable)
2556                 return true;
2557         if (ss.type != 3 && ss.type != 7)
2558                 return false;
2559         if (!ss.s)
2560                 return false;
2561         if (ss.dpl != ss_rpl) /* DPL != RPL */
2562                 return false;
2563         if (!ss.present)
2564                 return false;
2565
2566         return true;
2567 }
2568
2569 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2570 {
2571         struct kvm_segment var;
2572         unsigned int rpl;
2573
2574         vmx_get_segment(vcpu, &var, seg);
2575         rpl = var.selector & SELECTOR_RPL_MASK;
2576
2577         if (var.unusable)
2578                 return true;
2579         if (!var.s)
2580                 return false;
2581         if (!var.present)
2582                 return false;
2583         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2584                 if (var.dpl < rpl) /* DPL < RPL */
2585                         return false;
2586         }
2587
2588         /* TODO: Add other members to kvm_segment_field to allow checking for other access
2589          * rights flags
2590          */
2591         return true;
2592 }
2593
2594 static bool tr_valid(struct kvm_vcpu *vcpu)
2595 {
2596         struct kvm_segment tr;
2597
2598         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2599
2600         if (tr.unusable)
2601                 return false;
2602         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
2603                 return false;
2604         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2605                 return false;
2606         if (!tr.present)
2607                 return false;
2608
2609         return true;
2610 }
2611
2612 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2613 {
2614         struct kvm_segment ldtr;
2615
2616         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2617
2618         if (ldtr.unusable)
2619                 return true;
2620         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2621                 return false;
2622         if (ldtr.type != 2)
2623                 return false;
2624         if (!ldtr.present)
2625                 return false;
2626
2627         return true;
2628 }
2629
2630 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2631 {
2632         struct kvm_segment cs, ss;
2633
2634         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2635         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2636
2637         return ((cs.selector & SELECTOR_RPL_MASK) ==
2638                  (ss.selector & SELECTOR_RPL_MASK));
2639 }
2640
2641 /*
2642  * Check if guest state is valid. Returns true if valid, false if
2643  * not.
2644  * We assume that registers are always usable
2645  */
2646 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2647 {
2648         /* real mode guest state checks */
2649         if (!is_protmode(vcpu)) {
2650                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2651                         return false;
2652                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2653                         return false;
2654                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2655                         return false;
2656                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2657                         return false;
2658                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2659                         return false;
2660                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2661                         return false;
2662         } else {
2663         /* protected mode guest state checks */
2664                 if (!cs_ss_rpl_check(vcpu))
2665                         return false;
2666                 if (!code_segment_valid(vcpu))
2667                         return false;
2668                 if (!stack_segment_valid(vcpu))
2669                         return false;
2670                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2671                         return false;
2672                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2673                         return false;
2674                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2675                         return false;
2676                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2677                         return false;
2678                 if (!tr_valid(vcpu))
2679                         return false;
2680                 if (!ldtr_valid(vcpu))
2681                         return false;
2682         }
2683         /* TODO:
2684          * - Add checks on RIP
2685          * - Add checks on RFLAGS
2686          */
2687
2688         return true;
2689 }
2690
2691 static int init_rmode_tss(struct kvm *kvm)
2692 {
2693         gfn_t fn;
2694         u16 data = 0;
2695         int r, idx, ret = 0;
2696
2697         idx = srcu_read_lock(&kvm->srcu);
2698         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2699         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2700         if (r < 0)
2701                 goto out;
2702         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2703         r = kvm_write_guest_page(kvm, fn++, &data,
2704                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2705         if (r < 0)
2706                 goto out;
2707         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2708         if (r < 0)
2709                 goto out;
2710         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2711         if (r < 0)
2712                 goto out;
2713         data = ~0;
2714         r = kvm_write_guest_page(kvm, fn, &data,
2715                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2716                                  sizeof(u8));
2717         if (r < 0)
2718                 goto out;
2719
2720         ret = 1;
2721 out:
2722         srcu_read_unlock(&kvm->srcu, idx);
2723         return ret;
2724 }
2725
2726 static int init_rmode_identity_map(struct kvm *kvm)
2727 {
2728         int i, idx, r, ret;
2729         pfn_t identity_map_pfn;
2730         u32 tmp;
2731
2732         if (!enable_ept)
2733                 return 1;
2734         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2735                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2736                         "haven't been allocated!\n");
2737                 return 0;
2738         }
2739         if (likely(kvm->arch.ept_identity_pagetable_done))
2740                 return 1;
2741         ret = 0;
2742         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2743         idx = srcu_read_lock(&kvm->srcu);
2744         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2745         if (r < 0)
2746                 goto out;
2747         /* Set up identity-mapping pagetable for EPT in real mode */
2748         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2749                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2750                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2751                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2752                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2753                 if (r < 0)
2754                         goto out;
2755         }
2756         kvm->arch.ept_identity_pagetable_done = true;
2757         ret = 1;
2758 out:
2759         srcu_read_unlock(&kvm->srcu, idx);
2760         return ret;
2761 }
2762
2763 static void seg_setup(int seg)
2764 {
2765         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2766         unsigned int ar;
2767
2768         vmcs_write16(sf->selector, 0);
2769         vmcs_writel(sf->base, 0);
2770         vmcs_write32(sf->limit, 0xffff);
2771         if (enable_unrestricted_guest) {
2772                 ar = 0x93;
2773                 if (seg == VCPU_SREG_CS)
2774                         ar |= 0x08; /* code segment */
2775         } else
2776                 ar = 0xf3;
2777
2778         vmcs_write32(sf->ar_bytes, ar);
2779 }
2780
2781 static int alloc_apic_access_page(struct kvm *kvm)
2782 {
2783         struct kvm_userspace_memory_region kvm_userspace_mem;
2784         int r = 0;
2785
2786         mutex_lock(&kvm->slots_lock);
2787         if (kvm->arch.apic_access_page)
2788                 goto out;
2789         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2790         kvm_userspace_mem.flags = 0;
2791         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2792         kvm_userspace_mem.memory_size = PAGE_SIZE;
2793         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2794         if (r)
2795                 goto out;
2796
2797         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2798 out:
2799         mutex_unlock(&kvm->slots_lock);
2800         return r;
2801 }
2802
2803 static int alloc_identity_pagetable(struct kvm *kvm)
2804 {
2805         struct kvm_userspace_memory_region kvm_userspace_mem;
2806         int r = 0;
2807
2808         mutex_lock(&kvm->slots_lock);
2809         if (kvm->arch.ept_identity_pagetable)
2810                 goto out;
2811         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2812         kvm_userspace_mem.flags = 0;
2813         kvm_userspace_mem.guest_phys_addr =
2814                 kvm->arch.ept_identity_map_addr;
2815         kvm_userspace_mem.memory_size = PAGE_SIZE;
2816         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2817         if (r)
2818                 goto out;
2819
2820         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2821                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2822 out:
2823         mutex_unlock(&kvm->slots_lock);
2824         return r;
2825 }
2826
2827 static void allocate_vpid(struct vcpu_vmx *vmx)
2828 {
2829         int vpid;
2830
2831         vmx->vpid = 0;
2832         if (!enable_vpid)
2833                 return;
2834         spin_lock(&vmx_vpid_lock);
2835         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2836         if (vpid < VMX_NR_VPIDS) {
2837                 vmx->vpid = vpid;
2838                 __set_bit(vpid, vmx_vpid_bitmap);
2839         }
2840         spin_unlock(&vmx_vpid_lock);
2841 }
2842
2843 static void free_vpid(struct vcpu_vmx *vmx)
2844 {
2845         if (!enable_vpid)
2846                 return;
2847         spin_lock(&vmx_vpid_lock);
2848         if (vmx->vpid != 0)
2849                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2850         spin_unlock(&vmx_vpid_lock);
2851 }
2852
2853 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2854 {
2855         int f = sizeof(unsigned long);
2856
2857         if (!cpu_has_vmx_msr_bitmap())
2858                 return;
2859
2860         /*
2861          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2862          * have the write-low and read-high bitmap offsets the wrong way round.
2863          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2864          */
2865         if (msr <= 0x1fff) {
2866                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2867                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2868         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2869                 msr &= 0x1fff;
2870                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2871                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2872         }
2873 }
2874
2875 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2876 {
2877         if (!longmode_only)
2878                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2879         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2880 }
2881
2882 /*
2883  * Sets up the vmcs for emulated real mode.
2884  */
2885 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2886 {
2887         u32 host_sysenter_cs, msr_low, msr_high;
2888         u32 junk;
2889         u64 host_pat;
2890         unsigned long a;
2891         struct desc_ptr dt;
2892         int i;
2893         unsigned long kvm_vmx_return;
2894         u32 exec_control;
2895
2896         /* I/O */
2897         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2898         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2899
2900         if (cpu_has_vmx_msr_bitmap())
2901                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2902
2903         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2904
2905         /* Control */
2906         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2907                 vmcs_config.pin_based_exec_ctrl);
2908
2909         exec_control = vmcs_config.cpu_based_exec_ctrl;
2910         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2911                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2912 #ifdef CONFIG_X86_64
2913                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2914                                 CPU_BASED_CR8_LOAD_EXITING;
2915 #endif
2916         }
2917         if (!enable_ept)
2918                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2919                                 CPU_BASED_CR3_LOAD_EXITING  |
2920                                 CPU_BASED_INVLPG_EXITING;
2921         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2922
2923         if (cpu_has_secondary_exec_ctrls()) {
2924                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2925                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2926                         exec_control &=
2927                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2928                 if (vmx->vpid == 0)
2929                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2930                 if (!enable_ept) {
2931                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2932                         enable_unrestricted_guest = 0;
2933                 }
2934                 if (!enable_unrestricted_guest)
2935                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2936                 if (!ple_gap)
2937                         exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2938                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2939         }
2940
2941         if (ple_gap) {
2942                 vmcs_write32(PLE_GAP, ple_gap);
2943                 vmcs_write32(PLE_WINDOW, ple_window);
2944         }
2945
2946         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2947         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2948         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2949
2950         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
2951         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2952         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2953
2954         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2955         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2956         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2957         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
2958         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
2959         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2960 #ifdef CONFIG_X86_64
2961         rdmsrl(MSR_FS_BASE, a);
2962         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2963         rdmsrl(MSR_GS_BASE, a);
2964         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2965 #else
2966         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2967         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2968 #endif
2969
2970         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2971
2972         native_store_idt(&dt);
2973         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
2974
2975         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2976         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2977         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2978         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2979         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2980         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2981         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2982
2983         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2984         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2985         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2986         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2987         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2988         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2989
2990         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2991                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2992                 host_pat = msr_low | ((u64) msr_high << 32);
2993                 vmcs_write64(HOST_IA32_PAT, host_pat);
2994         }
2995         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2996                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2997                 host_pat = msr_low | ((u64) msr_high << 32);
2998                 /* Write the default value follow host pat */
2999                 vmcs_write64(GUEST_IA32_PAT, host_pat);
3000                 /* Keep arch.pat sync with GUEST_IA32_PAT */
3001                 vmx->vcpu.arch.pat = host_pat;
3002         }
3003
3004         for (i = 0; i < NR_VMX_MSR; ++i) {
3005                 u32 index = vmx_msr_index[i];
3006                 u32 data_low, data_high;
3007                 int j = vmx->nmsrs;
3008
3009                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3010                         continue;
3011                 if (wrmsr_safe(index, data_low, data_high) < 0)
3012                         continue;
3013                 vmx->guest_msrs[j].index = i;
3014                 vmx->guest_msrs[j].data = 0;
3015                 vmx->guest_msrs[j].mask = -1ull;
3016                 ++vmx->nmsrs;
3017         }
3018
3019         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3020
3021         /* 22.2.1, 20.8.1 */
3022         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3023
3024         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3025         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3026         if (enable_ept)
3027                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3028         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3029
3030         kvm_write_tsc(&vmx->vcpu, 0);
3031
3032         return 0;
3033 }
3034
3035 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3036 {
3037         struct vcpu_vmx *vmx = to_vmx(vcpu);
3038         u64 msr;
3039         int ret;
3040
3041         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3042
3043         vmx->rmode.vm86_active = 0;
3044
3045         vmx->soft_vnmi_blocked = 0;
3046
3047         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3048         kvm_set_cr8(&vmx->vcpu, 0);
3049         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3050         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3051                 msr |= MSR_IA32_APICBASE_BSP;
3052         kvm_set_apic_base(&vmx->vcpu, msr);
3053
3054         ret = fx_init(&vmx->vcpu);
3055         if (ret != 0)
3056                 goto out;
3057
3058         vmx_segment_cache_clear(vmx);
3059
3060         seg_setup(VCPU_SREG_CS);
3061         /*
3062          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3063          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
3064          */
3065         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3066                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3067                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3068         } else {
3069                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3070                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3071         }
3072
3073         seg_setup(VCPU_SREG_DS);
3074         seg_setup(VCPU_SREG_ES);
3075         seg_setup(VCPU_SREG_FS);
3076         seg_setup(VCPU_SREG_GS);
3077         seg_setup(VCPU_SREG_SS);
3078
3079         vmcs_write16(GUEST_TR_SELECTOR, 0);
3080         vmcs_writel(GUEST_TR_BASE, 0);
3081         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3082         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3083
3084         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3085         vmcs_writel(GUEST_LDTR_BASE, 0);
3086         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3087         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3088
3089         vmcs_write32(GUEST_SYSENTER_CS, 0);
3090         vmcs_writel(GUEST_SYSENTER_ESP, 0);
3091         vmcs_writel(GUEST_SYSENTER_EIP, 0);
3092
3093         vmcs_writel(GUEST_RFLAGS, 0x02);
3094         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3095                 kvm_rip_write(vcpu, 0xfff0);
3096         else
3097                 kvm_rip_write(vcpu, 0);
3098         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3099
3100         vmcs_writel(GUEST_DR7, 0x400);
3101
3102         vmcs_writel(GUEST_GDTR_BASE, 0);
3103         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3104
3105         vmcs_writel(GUEST_IDTR_BASE, 0);
3106         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3107
3108         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3109         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3110         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3111
3112         /* Special registers */
3113         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3114
3115         setup_msrs(vmx);
3116
3117         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
3118
3119         if (cpu_has_vmx_tpr_shadow()) {
3120                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3121                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3122                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3123                                      __pa(vmx->vcpu.arch.apic->regs));
3124                 vmcs_write32(TPR_THRESHOLD, 0);
3125         }
3126
3127         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3128                 vmcs_write64(APIC_ACCESS_ADDR,
3129                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3130
3131         if (vmx->vpid != 0)
3132                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3133
3134         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3135         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3136         vmx_set_cr4(&vmx->vcpu, 0);
3137         vmx_set_efer(&vmx->vcpu, 0);
3138         vmx_fpu_activate(&vmx->vcpu);
3139         update_exception_bitmap(&vmx->vcpu);
3140
3141         vpid_sync_context(vmx);
3142
3143         ret = 0;
3144
3145         /* HACK: Don't enable emulation on guest boot/reset */
3146         vmx->emulation_required = 0;
3147
3148 out:
3149         return ret;
3150 }
3151
3152 static void enable_irq_window(struct kvm_vcpu *vcpu)
3153 {
3154         u32 cpu_based_vm_exec_control;
3155
3156         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3157         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3158         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3159 }
3160
3161 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3162 {
3163         u32 cpu_based_vm_exec_control;
3164
3165         if (!cpu_has_virtual_nmis()) {
3166                 enable_irq_window(vcpu);
3167                 return;
3168         }
3169
3170         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3171                 enable_irq_window(vcpu);
3172                 return;
3173         }
3174         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3175         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3176         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3177 }
3178
3179 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
3180 {
3181         struct vcpu_vmx *vmx = to_vmx(vcpu);
3182         uint32_t intr;
3183         int irq = vcpu->arch.interrupt.nr;
3184
3185         trace_kvm_inj_virq(irq);
3186
3187         ++vcpu->stat.irq_injections;
3188         if (vmx->rmode.vm86_active) {
3189                 int inc_eip = 0;
3190                 if (vcpu->arch.interrupt.soft)
3191                         inc_eip = vcpu->arch.event_exit_inst_len;
3192                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
3193                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3194                 return;
3195         }
3196         intr = irq | INTR_INFO_VALID_MASK;
3197         if (vcpu->arch.interrupt.soft) {
3198                 intr |= INTR_TYPE_SOFT_INTR;
3199                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3200                              vmx->vcpu.arch.event_exit_inst_len);
3201         } else
3202                 intr |= INTR_TYPE_EXT_INTR;
3203         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
3204         vmx_clear_hlt(vcpu);
3205 }
3206
3207 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
3208 {
3209         struct vcpu_vmx *vmx = to_vmx(vcpu);
3210
3211         if (!cpu_has_virtual_nmis()) {
3212                 /*
3213                  * Tracking the NMI-blocked state in software is built upon
3214                  * finding the next open IRQ window. This, in turn, depends on
3215                  * well-behaving guests: They have to keep IRQs disabled at
3216                  * least as long as the NMI handler runs. Otherwise we may
3217                  * cause NMI nesting, maybe breaking the guest. But as this is
3218                  * highly unlikely, we can live with the residual risk.
3219                  */
3220                 vmx->soft_vnmi_blocked = 1;
3221                 vmx->vnmi_blocked_time = 0;
3222         }
3223
3224         ++vcpu->stat.nmi_injections;
3225         vmx->nmi_known_unmasked = false;
3226         if (vmx->rmode.vm86_active) {
3227                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
3228                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3229                 return;
3230         }
3231         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
3232                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
3233         vmx_clear_hlt(vcpu);
3234 }
3235
3236 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
3237 {
3238         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
3239                 return 0;
3240
3241         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3242                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
3243                    | GUEST_INTR_STATE_NMI));
3244 }
3245
3246 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3247 {
3248         if (!cpu_has_virtual_nmis())
3249                 return to_vmx(vcpu)->soft_vnmi_blocked;
3250         if (to_vmx(vcpu)->nmi_known_unmasked)
3251                 return false;
3252         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3253 }
3254
3255 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3256 {
3257         struct vcpu_vmx *vmx = to_vmx(vcpu);
3258
3259         if (!cpu_has_virtual_nmis()) {
3260                 if (vmx->soft_vnmi_blocked != masked) {
3261                         vmx->soft_vnmi_blocked = masked;
3262                         vmx->vnmi_blocked_time = 0;
3263                 }
3264         } else {
3265                 vmx->nmi_known_unmasked = !masked;
3266                 if (masked)
3267                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3268                                       GUEST_INTR_STATE_NMI);
3269                 else
3270                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3271                                         GUEST_INTR_STATE_NMI);
3272         }
3273 }
3274
3275 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
3276 {
3277         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
3278                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3279                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
3280 }
3281
3282 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
3283 {
3284         int ret;
3285         struct kvm_userspace_memory_region tss_mem = {
3286                 .slot = TSS_PRIVATE_MEMSLOT,
3287                 .guest_phys_addr = addr,
3288                 .memory_size = PAGE_SIZE * 3,
3289                 .flags = 0,
3290         };
3291
3292         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3293         if (ret)
3294                 return ret;
3295         kvm->arch.tss_addr = addr;
3296         if (!init_rmode_tss(kvm))
3297                 return  -ENOMEM;
3298
3299         return 0;
3300 }
3301
3302 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3303                                   int vec, u32 err_code)
3304 {
3305         /*
3306          * Instruction with address size override prefix opcode 0x67
3307          * Cause the #SS fault with 0 error code in VM86 mode.
3308          */
3309         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3310                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
3311                         return 1;
3312         /*
3313          * Forward all other exceptions that are valid in real mode.
3314          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3315          *        the required debugging infrastructure rework.
3316          */
3317         switch (vec) {
3318         case DB_VECTOR:
3319                 if (vcpu->guest_debug &
3320                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
3321                         return 0;
3322                 kvm_queue_exception(vcpu, vec);
3323                 return 1;
3324         case BP_VECTOR:
3325                 /*
3326                  * Update instruction length as we may reinject the exception
3327                  * from user space while in guest debugging mode.
3328                  */
3329                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3330                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3331                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3332                         return 0;
3333                 /* fall through */
3334         case DE_VECTOR:
3335         case OF_VECTOR:
3336         case BR_VECTOR:
3337         case UD_VECTOR:
3338         case DF_VECTOR:
3339         case SS_VECTOR:
3340         case GP_VECTOR:
3341         case MF_VECTOR:
3342                 kvm_queue_exception(vcpu, vec);
3343                 return 1;
3344         }
3345         return 0;
3346 }
3347
3348 /*
3349  * Trigger machine check on the host. We assume all the MSRs are already set up
3350  * by the CPU and that we still run on the same CPU as the MCE occurred on.
3351  * We pass a fake environment to the machine check handler because we want
3352  * the guest to be always treated like user space, no matter what context
3353  * it used internally.
3354  */
3355 static void kvm_machine_check(void)
3356 {
3357 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3358         struct pt_regs regs = {
3359                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3360                 .flags = X86_EFLAGS_IF,
3361         };
3362
3363         do_machine_check(&regs, 0);
3364 #endif
3365 }
3366
3367 static int handle_machine_check(struct kvm_vcpu *vcpu)
3368 {
3369         /* already handled by vcpu_run */
3370         return 1;
3371 }
3372
3373 static int handle_exception(struct kvm_vcpu *vcpu)
3374 {
3375         struct vcpu_vmx *vmx = to_vmx(vcpu);
3376         struct kvm_run *kvm_run = vcpu->run;
3377         u32 intr_info, ex_no, error_code;
3378         unsigned long cr2, rip, dr6;
3379         u32 vect_info;
3380         enum emulation_result er;
3381
3382         vect_info = vmx->idt_vectoring_info;
3383         intr_info = vmx->exit_intr_info;
3384
3385         if (is_machine_check(intr_info))
3386                 return handle_machine_check(vcpu);
3387
3388         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3389             !is_page_fault(intr_info)) {
3390                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3391                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3392                 vcpu->run->internal.ndata = 2;
3393                 vcpu->run->internal.data[0] = vect_info;
3394                 vcpu->run->internal.data[1] = intr_info;
3395                 return 0;
3396         }
3397
3398         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3399                 return 1;  /* already handled by vmx_vcpu_run() */
3400
3401         if (is_no_device(intr_info)) {
3402                 vmx_fpu_activate(vcpu);
3403                 return 1;
3404         }
3405
3406         if (is_invalid_opcode(intr_info)) {
3407                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
3408                 if (er != EMULATE_DONE)
3409                         kvm_queue_exception(vcpu, UD_VECTOR);
3410                 return 1;
3411         }
3412
3413         error_code = 0;
3414         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3415                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3416         if (is_page_fault(intr_info)) {
3417                 /* EPT won't cause page fault directly */
3418                 if (enable_ept)
3419                         BUG();
3420                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3421                 trace_kvm_page_fault(cr2, error_code);
3422
3423                 if (kvm_event_needs_reinjection(vcpu))
3424                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
3425                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
3426         }
3427
3428         if (vmx->rmode.vm86_active &&
3429             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3430                                                                 error_code)) {
3431                 if (vcpu->arch.halt_request) {
3432                         vcpu->arch.halt_request = 0;
3433                         return kvm_emulate_halt(vcpu);
3434                 }
3435                 return 1;
3436         }
3437
3438         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3439         switch (ex_no) {
3440         case DB_VECTOR:
3441                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3442                 if (!(vcpu->guest_debug &
3443                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3444                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3445                         kvm_queue_exception(vcpu, DB_VECTOR);
3446                         return 1;
3447                 }
3448                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3449                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3450                 /* fall through */
3451         case BP_VECTOR:
3452                 /*
3453                  * Update instruction length as we may reinject #BP from
3454                  * user space while in guest debugging mode. Reading it for
3455                  * #DB as well causes no harm, it is not used in that case.
3456                  */
3457                 vmx->vcpu.arch.event_exit_inst_len =
3458                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3459                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3460                 rip = kvm_rip_read(vcpu);
3461                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3462                 kvm_run->debug.arch.exception = ex_no;
3463                 break;
3464         default:
3465                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3466                 kvm_run->ex.exception = ex_no;
3467                 kvm_run->ex.error_code = error_code;
3468                 break;
3469         }
3470         return 0;
3471 }
3472
3473 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3474 {
3475         ++vcpu->stat.irq_exits;
3476         return 1;
3477 }
3478
3479 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3480 {
3481         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3482         return 0;
3483 }
3484
3485 static int handle_io(struct kvm_vcpu *vcpu)
3486 {
3487         unsigned long exit_qualification;
3488         int size, in, string;
3489         unsigned port;
3490
3491         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3492         string = (exit_qualification & 16) != 0;
3493         in = (exit_qualification & 8) != 0;
3494
3495         ++vcpu->stat.io_exits;
3496
3497         if (string || in)
3498                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3499
3500         port = exit_qualification >> 16;
3501         size = (exit_qualification & 7) + 1;
3502         skip_emulated_instruction(vcpu);
3503
3504         return kvm_fast_pio_out(vcpu, size, port);
3505 }
3506
3507 static void
3508 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3509 {
3510         /*
3511          * Patch in the VMCALL instruction:
3512          */
3513         hypercall[0] = 0x0f;
3514         hypercall[1] = 0x01;
3515         hypercall[2] = 0xc1;
3516 }
3517
3518 static int handle_cr(struct kvm_vcpu *vcpu)
3519 {
3520         unsigned long exit_qualification, val;
3521         int cr;
3522         int reg;
3523         int err;
3524
3525         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3526         cr = exit_qualification & 15;
3527         reg = (exit_qualification >> 8) & 15;
3528         switch ((exit_qualification >> 4) & 3) {
3529         case 0: /* mov to cr */
3530                 val = kvm_register_read(vcpu, reg);
3531                 trace_kvm_cr_write(cr, val);
3532                 switch (cr) {
3533                 case 0:
3534                         err = kvm_set_cr0(vcpu, val);
3535                         kvm_complete_insn_gp(vcpu, err);
3536                         return 1;
3537                 case 3:
3538                         err = kvm_set_cr3(vcpu, val);
3539                         kvm_complete_insn_gp(vcpu, err);
3540                         return 1;
3541                 case 4:
3542                         err = kvm_set_cr4(vcpu, val);
3543                         kvm_complete_insn_gp(vcpu, err);
3544                         return 1;
3545                 case 8: {
3546                                 u8 cr8_prev = kvm_get_cr8(vcpu);
3547                                 u8 cr8 = kvm_register_read(vcpu, reg);
3548                                 err = kvm_set_cr8(vcpu, cr8);
3549                                 kvm_complete_insn_gp(vcpu, err);
3550                                 if (irqchip_in_kernel(vcpu->kvm))
3551                                         return 1;
3552                                 if (cr8_prev <= cr8)
3553                                         return 1;
3554                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3555                                 return 0;
3556                         }
3557                 };
3558                 break;
3559         case 2: /* clts */
3560                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3561                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3562                 skip_emulated_instruction(vcpu);
3563                 vmx_fpu_activate(vcpu);
3564                 return 1;
3565         case 1: /*mov from cr*/
3566                 switch (cr) {
3567                 case 3:
3568                         val = kvm_read_cr3(vcpu);
3569                         kvm_register_write(vcpu, reg, val);
3570                         trace_kvm_cr_read(cr, val);
3571                         skip_emulated_instruction(vcpu);
3572                         return 1;
3573                 case 8:
3574                         val = kvm_get_cr8(vcpu);
3575                         kvm_register_write(vcpu, reg, val);
3576                         trace_kvm_cr_read(cr, val);
3577                         skip_emulated_instruction(vcpu);
3578                         return 1;
3579                 }
3580                 break;
3581         case 3: /* lmsw */
3582                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3583                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3584                 kvm_lmsw(vcpu, val);
3585
3586                 skip_emulated_instruction(vcpu);
3587                 return 1;
3588         default:
3589                 break;
3590         }
3591         vcpu->run->exit_reason = 0;
3592         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3593                (int)(exit_qualification >> 4) & 3, cr);
3594         return 0;
3595 }
3596
3597 static int handle_dr(struct kvm_vcpu *vcpu)
3598 {
3599         unsigned long exit_qualification;
3600         int dr, reg;
3601
3602         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3603         if (!kvm_require_cpl(vcpu, 0))
3604                 return 1;
3605         dr = vmcs_readl(GUEST_DR7);
3606         if (dr & DR7_GD) {
3607                 /*
3608                  * As the vm-exit takes precedence over the debug trap, we
3609                  * need to emulate the latter, either for the host or the
3610                  * guest debugging itself.
3611                  */
3612                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3613                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3614                         vcpu->run->debug.arch.dr7 = dr;
3615                         vcpu->run->debug.arch.pc =
3616                                 vmcs_readl(GUEST_CS_BASE) +
3617                                 vmcs_readl(GUEST_RIP);
3618                         vcpu->run->debug.arch.exception = DB_VECTOR;
3619                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3620                         return 0;
3621                 } else {
3622                         vcpu->arch.dr7 &= ~DR7_GD;
3623                         vcpu->arch.dr6 |= DR6_BD;
3624                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3625                         kvm_queue_exception(vcpu, DB_VECTOR);
3626                         return 1;
3627                 }
3628         }
3629
3630         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3631         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3632         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3633         if (exit_qualification & TYPE_MOV_FROM_DR) {
3634                 unsigned long val;
3635                 if (!kvm_get_dr(vcpu, dr, &val))
3636                         kvm_register_write(vcpu, reg, val);
3637         } else
3638                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3639         skip_emulated_instruction(vcpu);
3640         return 1;
3641 }
3642
3643 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3644 {
3645         vmcs_writel(GUEST_DR7, val);
3646 }
3647
3648 static int handle_cpuid(struct kvm_vcpu *vcpu)
3649 {
3650         kvm_emulate_cpuid(vcpu);
3651         return 1;
3652 }
3653
3654 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3655 {
3656         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3657         u64 data;
3658
3659         if (vmx_get_msr(vcpu, ecx, &data)) {
3660                 trace_kvm_msr_read_ex(ecx);
3661                 kvm_inject_gp(vcpu, 0);
3662                 return 1;
3663         }
3664
3665         trace_kvm_msr_read(ecx, data);
3666
3667         /* FIXME: handling of bits 32:63 of rax, rdx */
3668         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3669         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3670         skip_emulated_instruction(vcpu);
3671         return 1;
3672 }
3673
3674 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3675 {
3676         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3677         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3678                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3679
3680         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3681                 trace_kvm_msr_write_ex(ecx, data);
3682                 kvm_inject_gp(vcpu, 0);
3683                 return 1;
3684         }
3685
3686         trace_kvm_msr_write(ecx, data);
3687         skip_emulated_instruction(vcpu);
3688         return 1;
3689 }
3690
3691 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3692 {
3693         kvm_make_request(KVM_REQ_EVENT, vcpu);
3694         return 1;
3695 }
3696
3697 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3698 {
3699         u32 cpu_based_vm_exec_control;
3700
3701         /* clear pending irq */
3702         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3703         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3704         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3705
3706         kvm_make_request(KVM_REQ_EVENT, vcpu);
3707
3708         ++vcpu->stat.irq_window_exits;
3709
3710         /*
3711          * If the user space waits to inject interrupts, exit as soon as
3712          * possible
3713          */
3714         if (!irqchip_in_kernel(vcpu->kvm) &&
3715             vcpu->run->request_interrupt_window &&
3716             !kvm_cpu_has_interrupt(vcpu)) {
3717                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3718                 return 0;
3719         }
3720         return 1;
3721 }
3722
3723 static int handle_halt(struct kvm_vcpu *vcpu)
3724 {
3725         skip_emulated_instruction(vcpu);
3726         return kvm_emulate_halt(vcpu);
3727 }
3728
3729 static int handle_vmcall(struct kvm_vcpu *vcpu)
3730 {
3731         skip_emulated_instruction(vcpu);
3732         kvm_emulate_hypercall(vcpu);
3733         return 1;
3734 }
3735
3736 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3737 {
3738         kvm_queue_exception(vcpu, UD_VECTOR);
3739         return 1;
3740 }
3741
3742 static int handle_invd(struct kvm_vcpu *vcpu)
3743 {
3744         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3745 }
3746
3747 static int handle_invlpg(struct kvm_vcpu *vcpu)
3748 {
3749         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3750
3751         kvm_mmu_invlpg(vcpu, exit_qualification);
3752         skip_emulated_instruction(vcpu);
3753         return 1;
3754 }
3755
3756 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3757 {
3758         skip_emulated_instruction(vcpu);
3759         kvm_emulate_wbinvd(vcpu);
3760         return 1;
3761 }
3762
3763 static int handle_xsetbv(struct kvm_vcpu *vcpu)
3764 {
3765         u64 new_bv = kvm_read_edx_eax(vcpu);
3766         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3767
3768         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3769                 skip_emulated_instruction(vcpu);
3770         return 1;
3771 }
3772
3773 static int handle_apic_access(struct kvm_vcpu *vcpu)
3774 {
3775         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3776 }
3777
3778 static int handle_task_switch(struct kvm_vcpu *vcpu)
3779 {
3780         struct vcpu_vmx *vmx = to_vmx(vcpu);
3781         unsigned long exit_qualification;
3782         bool has_error_code = false;
3783         u32 error_code = 0;
3784         u16 tss_selector;
3785         int reason, type, idt_v;
3786
3787         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3788         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3789
3790         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3791
3792         reason = (u32)exit_qualification >> 30;
3793         if (reason == TASK_SWITCH_GATE && idt_v) {
3794                 switch (type) {
3795                 case INTR_TYPE_NMI_INTR:
3796                         vcpu->arch.nmi_injected = false;
3797                         vmx_set_nmi_mask(vcpu, true);
3798                         break;
3799                 case INTR_TYPE_EXT_INTR:
3800                 case INTR_TYPE_SOFT_INTR:
3801                         kvm_clear_interrupt_queue(vcpu);
3802                         break;
3803                 case INTR_TYPE_HARD_EXCEPTION:
3804                         if (vmx->idt_vectoring_info &
3805                             VECTORING_INFO_DELIVER_CODE_MASK) {
3806                                 has_error_code = true;
3807                                 error_code =
3808                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
3809                         }
3810                         /* fall through */
3811                 case INTR_TYPE_SOFT_EXCEPTION:
3812                         kvm_clear_exception_queue(vcpu);
3813                         break;
3814                 default:
3815                         break;
3816                 }
3817         }
3818         tss_selector = exit_qualification;
3819
3820         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3821                        type != INTR_TYPE_EXT_INTR &&
3822                        type != INTR_TYPE_NMI_INTR))
3823                 skip_emulated_instruction(vcpu);
3824
3825         if (kvm_task_switch(vcpu, tss_selector, reason,
3826                                 has_error_code, error_code) == EMULATE_FAIL) {
3827                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3828                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3829                 vcpu->run->internal.ndata = 0;
3830                 return 0;
3831         }
3832
3833         /* clear all local breakpoint enable flags */
3834         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3835
3836         /*
3837          * TODO: What about debug traps on tss switch?
3838          *       Are we supposed to inject them and update dr6?
3839          */
3840
3841         return 1;
3842 }
3843
3844 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3845 {
3846         unsigned long exit_qualification;
3847         gpa_t gpa;
3848         int gla_validity;
3849
3850         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3851
3852         if (exit_qualification & (1 << 6)) {
3853                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3854                 return -EINVAL;
3855         }
3856
3857         gla_validity = (exit_qualification >> 7) & 0x3;
3858         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3859                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3860                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3861                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3862                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3863                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3864                         (long unsigned int)exit_qualification);
3865                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3866                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3867                 return 0;
3868         }
3869
3870         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3871         trace_kvm_page_fault(gpa, exit_qualification);
3872         return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
3873 }
3874
3875 static u64 ept_rsvd_mask(u64 spte, int level)
3876 {
3877         int i;
3878         u64 mask = 0;
3879
3880         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3881                 mask |= (1ULL << i);
3882
3883         if (level > 2)
3884                 /* bits 7:3 reserved */
3885                 mask |= 0xf8;
3886         else if (level == 2) {
3887                 if (spte & (1ULL << 7))
3888                         /* 2MB ref, bits 20:12 reserved */
3889                         mask |= 0x1ff000;
3890                 else
3891                         /* bits 6:3 reserved */
3892                         mask |= 0x78;
3893         }
3894
3895         return mask;
3896 }
3897
3898 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3899                                        int level)
3900 {
3901         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3902
3903         /* 010b (write-only) */
3904         WARN_ON((spte & 0x7) == 0x2);
3905
3906         /* 110b (write/execute) */
3907         WARN_ON((spte & 0x7) == 0x6);
3908
3909         /* 100b (execute-only) and value not supported by logical processor */
3910         if (!cpu_has_vmx_ept_execute_only())
3911                 WARN_ON((spte & 0x7) == 0x4);
3912
3913         /* not 000b */
3914         if ((spte & 0x7)) {
3915                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3916
3917                 if (rsvd_bits != 0) {
3918                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3919                                          __func__, rsvd_bits);
3920                         WARN_ON(1);
3921                 }
3922
3923                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3924                         u64 ept_mem_type = (spte & 0x38) >> 3;
3925
3926                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3927                             ept_mem_type == 7) {
3928                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3929                                                 __func__, ept_mem_type);
3930                                 WARN_ON(1);
3931                         }
3932                 }
3933         }
3934 }
3935
3936 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3937 {
3938         u64 sptes[4];
3939         int nr_sptes, i;
3940         gpa_t gpa;
3941
3942         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3943
3944         printk(KERN_ERR "EPT: Misconfiguration.\n");
3945         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3946
3947         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3948
3949         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3950                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3951
3952         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3953         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3954
3955         return 0;
3956 }
3957
3958 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3959 {
3960         u32 cpu_based_vm_exec_control;
3961
3962         /* clear pending NMI */
3963         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3964         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3965         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3966         ++vcpu->stat.nmi_window_exits;
3967         kvm_make_request(KVM_REQ_EVENT, vcpu);
3968
3969         return 1;
3970 }
3971
3972 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3973 {
3974         struct vcpu_vmx *vmx = to_vmx(vcpu);
3975         enum emulation_result err = EMULATE_DONE;
3976         int ret = 1;
3977         u32 cpu_exec_ctrl;
3978         bool intr_window_requested;
3979
3980         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3981         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
3982
3983         while (!guest_state_valid(vcpu)) {
3984                 if (intr_window_requested
3985                     && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
3986                         return handle_interrupt_window(&vmx->vcpu);
3987
3988                 err = emulate_instruction(vcpu, 0);
3989
3990                 if (err == EMULATE_DO_MMIO) {
3991                         ret = 0;
3992                         goto out;
3993                 }
3994
3995                 if (err != EMULATE_DONE)
3996                         return 0;
3997
3998                 if (signal_pending(current))
3999                         goto out;
4000                 if (need_resched())
4001                         schedule();
4002         }
4003
4004         vmx->emulation_required = 0;
4005 out:
4006         return ret;
4007 }
4008
4009 /*
4010  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4011  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4012  */
4013 static int handle_pause(struct kvm_vcpu *vcpu)
4014 {
4015         skip_emulated_instruction(vcpu);
4016         kvm_vcpu_on_spin(vcpu);
4017
4018         return 1;
4019 }
4020
4021 static int handle_invalid_op(struct kvm_vcpu *vcpu)
4022 {
4023         kvm_queue_exception(vcpu, UD_VECTOR);
4024         return 1;
4025 }
4026
4027 /*
4028  * Emulate the VMXON instruction.
4029  * Currently, we just remember that VMX is active, and do not save or even
4030  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4031  * do not currently need to store anything in that guest-allocated memory
4032  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
4033  * argument is different from the VMXON pointer (which the spec says they do).
4034  */
4035 static int handle_vmon(struct kvm_vcpu *vcpu)
4036 {
4037         struct kvm_segment cs;
4038         struct vcpu_vmx *vmx = to_vmx(vcpu);
4039
4040         /* The Intel VMX Instruction Reference lists a bunch of bits that
4041          * are prerequisite to running VMXON, most notably cr4.VMXE must be
4042          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
4043          * Otherwise, we should fail with #UD. We test these now:
4044          */
4045         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
4046             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
4047             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4048                 kvm_queue_exception(vcpu, UD_VECTOR);
4049                 return 1;
4050         }
4051
4052         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4053         if (is_long_mode(vcpu) && !cs.l) {
4054                 kvm_queue_exception(vcpu, UD_VECTOR);
4055                 return 1;
4056         }
4057
4058         if (vmx_get_cpl(vcpu)) {
4059                 kvm_inject_gp(vcpu, 0);
4060                 return 1;
4061         }
4062
4063         vmx->nested.vmxon = true;
4064
4065         skip_emulated_instruction(vcpu);
4066         return 1;
4067 }
4068
4069 /*
4070  * Intel's VMX Instruction Reference specifies a common set of prerequisites
4071  * for running VMX instructions (except VMXON, whose prerequisites are
4072  * slightly different). It also specifies what exception to inject otherwise.
4073  */
4074 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
4075 {
4076         struct kvm_segment cs;
4077         struct vcpu_vmx *vmx = to_vmx(vcpu);
4078
4079         if (!vmx->nested.vmxon) {
4080                 kvm_queue_exception(vcpu, UD_VECTOR);
4081                 return 0;
4082         }
4083
4084         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4085         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
4086             (is_long_mode(vcpu) && !cs.l)) {
4087                 kvm_queue_exception(vcpu, UD_VECTOR);
4088                 return 0;
4089         }
4090
4091         if (vmx_get_cpl(vcpu)) {
4092                 kvm_inject_gp(vcpu, 0);
4093                 return 0;
4094         }
4095
4096         return 1;
4097 }
4098
4099 /*
4100  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
4101  * just stops using VMX.
4102  */
4103 static void free_nested(struct vcpu_vmx *vmx)
4104 {
4105         if (!vmx->nested.vmxon)
4106                 return;
4107         vmx->nested.vmxon = false;
4108         if (vmx->nested.current_vmptr != -1ull) {
4109                 kunmap(vmx->nested.current_vmcs12_page);
4110                 nested_release_page(vmx->nested.current_vmcs12_page);
4111                 vmx->nested.current_vmptr = -1ull;
4112                 vmx->nested.current_vmcs12 = NULL;
4113         }
4114 }
4115
4116 /* Emulate the VMXOFF instruction */
4117 static int handle_vmoff(struct kvm_vcpu *vcpu)
4118 {
4119         if (!nested_vmx_check_permission(vcpu))
4120                 return 1;
4121         free_nested(to_vmx(vcpu));
4122         skip_emulated_instruction(vcpu);
4123         return 1;
4124 }
4125
4126 /*
4127  * The exit handlers return 1 if the exit was handled fully and guest execution
4128  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
4129  * to be done to userspace and return 0.
4130  */
4131 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
4132         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
4133         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
4134         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
4135         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
4136         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
4137         [EXIT_REASON_CR_ACCESS]               = handle_cr,
4138         [EXIT_REASON_DR_ACCESS]               = handle_dr,
4139         [EXIT_REASON_CPUID]                   = handle_cpuid,
4140         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
4141         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
4142         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
4143         [EXIT_REASON_HLT]                     = handle_halt,
4144         [EXIT_REASON_INVD]                    = handle_invd,
4145         [EXIT_REASON_INVLPG]                  = handle_invlpg,
4146         [EXIT_REASON_VMCALL]                  = handle_vmcall,
4147         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
4148         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
4149         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
4150         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
4151         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
4152         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
4153         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
4154         [EXIT_REASON_VMOFF]                   = handle_vmoff,
4155         [EXIT_REASON_VMON]                    = handle_vmon,
4156         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
4157         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
4158         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
4159         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
4160         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
4161         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
4162         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
4163         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
4164         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
4165         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
4166         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
4167 };
4168
4169 static const int kvm_vmx_max_exit_handlers =
4170         ARRAY_SIZE(kvm_vmx_exit_handlers);
4171
4172 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4173 {
4174         *info1 = vmcs_readl(EXIT_QUALIFICATION);
4175         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
4176 }
4177
4178 /*
4179  * The guest has exited.  See if we can fix it or if we need userspace
4180  * assistance.
4181  */
4182 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
4183 {
4184         struct vcpu_vmx *vmx = to_vmx(vcpu);
4185         u32 exit_reason = vmx->exit_reason;
4186         u32 vectoring_info = vmx->idt_vectoring_info;
4187
4188         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
4189
4190         /* If guest state is invalid, start emulating */
4191         if (vmx->emulation_required && emulate_invalid_guest_state)
4192                 return handle_invalid_guest_state(vcpu);
4193
4194         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
4195                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4196                 vcpu->run->fail_entry.hardware_entry_failure_reason
4197                         = exit_reason;
4198                 return 0;
4199         }
4200
4201         if (unlikely(vmx->fail)) {
4202                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4203                 vcpu->run->fail_entry.hardware_entry_failure_reason
4204                         = vmcs_read32(VM_INSTRUCTION_ERROR);
4205                 return 0;
4206         }
4207
4208         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
4209                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
4210                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
4211                         exit_reason != EXIT_REASON_TASK_SWITCH))
4212                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
4213                        "(0x%x) and exit reason is 0x%x\n",
4214                        __func__, vectoring_info, exit_reason);
4215
4216         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
4217                 if (vmx_interrupt_allowed(vcpu)) {
4218                         vmx->soft_vnmi_blocked = 0;
4219                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4220                            vcpu->arch.nmi_pending) {
4221                         /*
4222                          * This CPU don't support us in finding the end of an
4223                          * NMI-blocked window if the guest runs with IRQs
4224                          * disabled. So we pull the trigger after 1 s of
4225                          * futile waiting, but inform the user about this.
4226                          */
4227                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
4228                                "state on VCPU %d after 1 s timeout\n",
4229                                __func__, vcpu->vcpu_id);
4230                         vmx->soft_vnmi_blocked = 0;
4231                 }
4232         }
4233
4234         if (exit_reason < kvm_vmx_max_exit_handlers
4235             && kvm_vmx_exit_handlers[exit_reason])
4236                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
4237         else {
4238                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4239                 vcpu->run->hw.hardware_exit_reason = exit_reason;
4240         }
4241         return 0;
4242 }
4243
4244 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
4245 {
4246         if (irr == -1 || tpr < irr) {
4247                 vmcs_write32(TPR_THRESHOLD, 0);
4248                 return;
4249         }
4250
4251         vmcs_write32(TPR_THRESHOLD, irr);
4252 }
4253
4254 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
4255 {
4256         u32 exit_intr_info;
4257
4258         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
4259               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
4260                 return;
4261
4262         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4263         exit_intr_info = vmx->exit_intr_info;
4264
4265         /* Handle machine checks before interrupts are enabled */
4266         if (is_machine_check(exit_intr_info))
4267                 kvm_machine_check();
4268
4269         /* We need to handle NMIs before interrupts are enabled */
4270         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
4271             (exit_intr_info & INTR_INFO_VALID_MASK)) {
4272                 kvm_before_handle_nmi(&vmx->vcpu);
4273                 asm("int $2");
4274                 kvm_after_handle_nmi(&vmx->vcpu);
4275         }
4276 }
4277
4278 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
4279 {
4280         u32 exit_intr_info;
4281         bool unblock_nmi;
4282         u8 vector;
4283         bool idtv_info_valid;
4284
4285         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
4286
4287         if (cpu_has_virtual_nmis()) {
4288                 if (vmx->nmi_known_unmasked)
4289                         return;
4290                 /*
4291                  * Can't use vmx->exit_intr_info since we're not sure what
4292                  * the exit reason is.
4293                  */
4294                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4295                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
4296                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
4297                 /*
4298                  * SDM 3: 27.7.1.2 (September 2008)
4299                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
4300                  * a guest IRET fault.
4301                  * SDM 3: 23.2.2 (September 2008)
4302                  * Bit 12 is undefined in any of the following cases:
4303                  *  If the VM exit sets the valid bit in the IDT-vectoring
4304                  *   information field.
4305                  *  If the VM exit is due to a double fault.
4306                  */
4307                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
4308                     vector != DF_VECTOR && !idtv_info_valid)
4309                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4310                                       GUEST_INTR_STATE_NMI);
4311                 else
4312                         vmx->nmi_known_unmasked =
4313                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
4314                                   & GUEST_INTR_STATE_NMI);
4315         } else if (unlikely(vmx->soft_vnmi_blocked))
4316                 vmx->vnmi_blocked_time +=
4317                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
4318 }
4319
4320 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
4321                                       u32 idt_vectoring_info,
4322                                       int instr_len_field,
4323                                       int error_code_field)
4324 {
4325         u8 vector;
4326         int type;
4327         bool idtv_info_valid;
4328
4329         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
4330
4331         vmx->vcpu.arch.nmi_injected = false;
4332         kvm_clear_exception_queue(&vmx->vcpu);
4333         kvm_clear_interrupt_queue(&vmx->vcpu);
4334
4335         if (!idtv_info_valid)
4336                 return;
4337
4338         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
4339
4340         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
4341         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
4342
4343         switch (type) {
4344         case INTR_TYPE_NMI_INTR:
4345                 vmx->vcpu.arch.nmi_injected = true;
4346                 /*
4347                  * SDM 3: 27.7.1.2 (September 2008)
4348                  * Clear bit "block by NMI" before VM entry if a NMI
4349                  * delivery faulted.
4350                  */
4351                 vmx_set_nmi_mask(&vmx->vcpu, false);
4352                 break;
4353         case INTR_TYPE_SOFT_EXCEPTION:
4354                 vmx->vcpu.arch.event_exit_inst_len =
4355                         vmcs_read32(instr_len_field);
4356                 /* fall through */
4357         case INTR_TYPE_HARD_EXCEPTION:
4358                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
4359                         u32 err = vmcs_read32(error_code_field);
4360                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
4361                 } else
4362                         kvm_queue_exception(&vmx->vcpu, vector);
4363                 break;
4364         case INTR_TYPE_SOFT_INTR:
4365                 vmx->vcpu.arch.event_exit_inst_len =
4366                         vmcs_read32(instr_len_field);
4367                 /* fall through */
4368         case INTR_TYPE_EXT_INTR:
4369                 kvm_queue_interrupt(&vmx->vcpu, vector,
4370                         type == INTR_TYPE_SOFT_INTR);
4371                 break;
4372         default:
4373                 break;
4374         }
4375 }
4376
4377 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
4378 {
4379         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
4380                                   VM_EXIT_INSTRUCTION_LEN,
4381                                   IDT_VECTORING_ERROR_CODE);
4382 }
4383
4384 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
4385 {
4386         __vmx_complete_interrupts(to_vmx(vcpu),
4387                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
4388                                   VM_ENTRY_INSTRUCTION_LEN,
4389                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
4390
4391         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
4392 }
4393
4394 #ifdef CONFIG_X86_64
4395 #define R "r"
4396 #define Q "q"
4397 #else
4398 #define R "e"
4399 #define Q "l"
4400 #endif
4401
4402 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
4403 {
4404         struct vcpu_vmx *vmx = to_vmx(vcpu);
4405
4406         /* Record the guest's net vcpu time for enforced NMI injections. */
4407         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
4408                 vmx->entry_time = ktime_get();
4409
4410         /* Don't enter VMX if guest state is invalid, let the exit handler
4411            start emulation until we arrive back to a valid state */
4412         if (vmx->emulation_required && emulate_invalid_guest_state)
4413                 return;
4414
4415         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
4416                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
4417         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
4418                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
4419
4420         /* When single-stepping over STI and MOV SS, we must clear the
4421          * corresponding interruptibility bits in the guest state. Otherwise
4422          * vmentry fails as it then expects bit 14 (BS) in pending debug
4423          * exceptions being set, but that's not correct for the guest debugging
4424          * case. */
4425         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
4426                 vmx_set_interrupt_shadow(vcpu, 0);
4427
4428         vmx->__launched = vmx->loaded_vmcs->launched;
4429         asm(
4430                 /* Store host registers */
4431                 "push %%"R"dx; push %%"R"bp;"
4432                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
4433                 "push %%"R"cx \n\t"
4434                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
4435                 "je 1f \n\t"
4436                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4437                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
4438                 "1: \n\t"
4439                 /* Reload cr2 if changed */
4440                 "mov %c[cr2](%0), %%"R"ax \n\t"
4441                 "mov %%cr2, %%"R"dx \n\t"
4442                 "cmp %%"R"ax, %%"R"dx \n\t"
4443                 "je 2f \n\t"
4444                 "mov %%"R"ax, %%cr2 \n\t"
4445                 "2: \n\t"
4446                 /* Check if vmlaunch of vmresume is needed */
4447                 "cmpl $0, %c[launched](%0) \n\t"
4448                 /* Load guest registers.  Don't clobber flags. */
4449                 "mov %c[rax](%0), %%"R"ax \n\t"
4450                 "mov %c[rbx](%0), %%"R"bx \n\t"
4451                 "mov %c[rdx](%0), %%"R"dx \n\t"
4452                 "mov %c[rsi](%0), %%"R"si \n\t"
4453                 "mov %c[rdi](%0), %%"R"di \n\t"
4454                 "mov %c[rbp](%0), %%"R"bp \n\t"
4455 #ifdef CONFIG_X86_64
4456                 "mov %c[r8](%0),  %%r8  \n\t"
4457                 "mov %c[r9](%0),  %%r9  \n\t"
4458                 "mov %c[r10](%0), %%r10 \n\t"
4459                 "mov %c[r11](%0), %%r11 \n\t"
4460                 "mov %c[r12](%0), %%r12 \n\t"
4461                 "mov %c[r13](%0), %%r13 \n\t"
4462                 "mov %c[r14](%0), %%r14 \n\t"
4463                 "mov %c[r15](%0), %%r15 \n\t"
4464 #endif
4465                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
4466
4467                 /* Enter guest mode */
4468                 "jne .Llaunched \n\t"
4469                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
4470                 "jmp .Lkvm_vmx_return \n\t"
4471                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
4472                 ".Lkvm_vmx_return: "
4473                 /* Save guest registers, load host registers, keep flags */
4474                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
4475                 "pop %0 \n\t"
4476                 "mov %%"R"ax, %c[rax](%0) \n\t"
4477                 "mov %%"R"bx, %c[rbx](%0) \n\t"
4478                 "pop"Q" %c[rcx](%0) \n\t"
4479                 "mov %%"R"dx, %c[rdx](%0) \n\t"
4480                 "mov %%"R"si, %c[rsi](%0) \n\t"
4481                 "mov %%"R"di, %c[rdi](%0) \n\t"
4482                 "mov %%"R"bp, %c[rbp](%0) \n\t"
4483 #ifdef CONFIG_X86_64
4484                 "mov %%r8,  %c[r8](%0) \n\t"
4485                 "mov %%r9,  %c[r9](%0) \n\t"
4486                 "mov %%r10, %c[r10](%0) \n\t"
4487                 "mov %%r11, %c[r11](%0) \n\t"
4488                 "mov %%r12, %c[r12](%0) \n\t"
4489                 "mov %%r13, %c[r13](%0) \n\t"
4490                 "mov %%r14, %c[r14](%0) \n\t"
4491                 "mov %%r15, %c[r15](%0) \n\t"
4492 #endif
4493                 "mov %%cr2, %%"R"ax   \n\t"
4494                 "mov %%"R"ax, %c[cr2](%0) \n\t"
4495
4496                 "pop  %%"R"bp; pop  %%"R"dx \n\t"
4497                 "setbe %c[fail](%0) \n\t"
4498               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4499                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
4500                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
4501                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
4502                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4503                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4504                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4505                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4506                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4507                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4508                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
4509 #ifdef CONFIG_X86_64
4510                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4511                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4512                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4513                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4514                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4515                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4516                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4517                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
4518 #endif
4519                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
4520                 [wordsize]"i"(sizeof(ulong))
4521               : "cc", "memory"
4522                 , R"ax", R"bx", R"di", R"si"
4523 #ifdef CONFIG_X86_64
4524                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4525 #endif
4526               );
4527
4528         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4529                                   | (1 << VCPU_EXREG_RFLAGS)
4530                                   | (1 << VCPU_EXREG_CPL)
4531                                   | (1 << VCPU_EXREG_PDPTR)
4532                                   | (1 << VCPU_EXREG_SEGMENTS)
4533                                   | (1 << VCPU_EXREG_CR3));
4534         vcpu->arch.regs_dirty = 0;
4535
4536         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4537
4538         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
4539         vmx->loaded_vmcs->launched = 1;
4540
4541         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
4542
4543         vmx_complete_atomic_exit(vmx);
4544         vmx_recover_nmi_blocking(vmx);
4545         vmx_complete_interrupts(vmx);
4546 }
4547
4548 #undef R
4549 #undef Q
4550
4551 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4552 {
4553         struct vcpu_vmx *vmx = to_vmx(vcpu);
4554
4555         free_vpid(vmx);
4556         free_nested(vmx);
4557         free_loaded_vmcs(vmx->loaded_vmcs);
4558         kfree(vmx->guest_msrs);
4559         kvm_vcpu_uninit(vcpu);
4560         kmem_cache_free(kvm_vcpu_cache, vmx);
4561 }
4562
4563 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4564 {
4565         int err;
4566         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4567         int cpu;
4568
4569         if (!vmx)
4570                 return ERR_PTR(-ENOMEM);
4571
4572         allocate_vpid(vmx);
4573
4574         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4575         if (err)
4576                 goto free_vcpu;
4577
4578         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4579         err = -ENOMEM;
4580         if (!vmx->guest_msrs) {
4581                 goto uninit_vcpu;
4582         }
4583
4584         vmx->loaded_vmcs = &vmx->vmcs01;
4585         vmx->loaded_vmcs->vmcs = alloc_vmcs();
4586         if (!vmx->loaded_vmcs->vmcs)
4587                 goto free_msrs;
4588         if (!vmm_exclusive)
4589                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
4590         loaded_vmcs_init(vmx->loaded_vmcs);
4591         if (!vmm_exclusive)
4592                 kvm_cpu_vmxoff();
4593
4594         cpu = get_cpu();
4595         vmx_vcpu_load(&vmx->vcpu, cpu);
4596         vmx->vcpu.cpu = cpu;
4597         err = vmx_vcpu_setup(vmx);
4598         vmx_vcpu_put(&vmx->vcpu);
4599         put_cpu();
4600         if (err)
4601                 goto free_vmcs;
4602         if (vm_need_virtualize_apic_accesses(kvm))
4603                 err = alloc_apic_access_page(kvm);
4604                 if (err)
4605                         goto free_vmcs;
4606
4607         if (enable_ept) {
4608                 if (!kvm->arch.ept_identity_map_addr)
4609                         kvm->arch.ept_identity_map_addr =
4610                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4611                 err = -ENOMEM;
4612                 if (alloc_identity_pagetable(kvm) != 0)
4613                         goto free_vmcs;
4614                 if (!init_rmode_identity_map(kvm))
4615                         goto free_vmcs;
4616         }
4617
4618         vmx->nested.current_vmptr = -1ull;
4619         vmx->nested.current_vmcs12 = NULL;
4620
4621         return &vmx->vcpu;
4622
4623 free_vmcs:
4624         free_vmcs(vmx->loaded_vmcs->vmcs);
4625 free_msrs:
4626         kfree(vmx->guest_msrs);
4627 uninit_vcpu:
4628         kvm_vcpu_uninit(&vmx->vcpu);
4629 free_vcpu:
4630         free_vpid(vmx);
4631         kmem_cache_free(kvm_vcpu_cache, vmx);
4632         return ERR_PTR(err);
4633 }
4634
4635 static void __init vmx_check_processor_compat(void *rtn)
4636 {
4637         struct vmcs_config vmcs_conf;
4638
4639         *(int *)rtn = 0;
4640         if (setup_vmcs_config(&vmcs_conf) < 0)
4641                 *(int *)rtn = -EIO;
4642         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4643                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4644                                 smp_processor_id());
4645                 *(int *)rtn = -EIO;
4646         }
4647 }
4648
4649 static int get_ept_level(void)
4650 {
4651         return VMX_EPT_DEFAULT_GAW + 1;
4652 }
4653
4654 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4655 {
4656         u64 ret;
4657
4658         /* For VT-d and EPT combination
4659          * 1. MMIO: always map as UC
4660          * 2. EPT with VT-d:
4661          *   a. VT-d without snooping control feature: can't guarantee the
4662          *      result, try to trust guest.
4663          *   b. VT-d with snooping control feature: snooping control feature of
4664          *      VT-d engine can guarantee the cache correctness. Just set it
4665          *      to WB to keep consistent with host. So the same as item 3.
4666          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4667          *    consistent with host MTRR
4668          */
4669         if (is_mmio)
4670                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4671         else if (vcpu->kvm->arch.iommu_domain &&
4672                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4673                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4674                       VMX_EPT_MT_EPTE_SHIFT;
4675         else
4676                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4677                         | VMX_EPT_IPAT_BIT;
4678
4679         return ret;
4680 }
4681
4682 #define _ER(x) { EXIT_REASON_##x, #x }
4683
4684 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4685         _ER(EXCEPTION_NMI),
4686         _ER(EXTERNAL_INTERRUPT),
4687         _ER(TRIPLE_FAULT),
4688         _ER(PENDING_INTERRUPT),
4689         _ER(NMI_WINDOW),
4690         _ER(TASK_SWITCH),
4691         _ER(CPUID),
4692         _ER(HLT),
4693         _ER(INVLPG),
4694         _ER(RDPMC),
4695         _ER(RDTSC),
4696         _ER(VMCALL),
4697         _ER(VMCLEAR),
4698         _ER(VMLAUNCH),
4699         _ER(VMPTRLD),
4700         _ER(VMPTRST),
4701         _ER(VMREAD),
4702         _ER(VMRESUME),
4703         _ER(VMWRITE),
4704         _ER(VMOFF),
4705         _ER(VMON),
4706         _ER(CR_ACCESS),
4707         _ER(DR_ACCESS),
4708         _ER(IO_INSTRUCTION),
4709         _ER(MSR_READ),
4710         _ER(MSR_WRITE),
4711         _ER(MWAIT_INSTRUCTION),
4712         _ER(MONITOR_INSTRUCTION),
4713         _ER(PAUSE_INSTRUCTION),
4714         _ER(MCE_DURING_VMENTRY),
4715         _ER(TPR_BELOW_THRESHOLD),
4716         _ER(APIC_ACCESS),
4717         _ER(EPT_VIOLATION),
4718         _ER(EPT_MISCONFIG),
4719         _ER(WBINVD),
4720         { -1, NULL }
4721 };
4722
4723 #undef _ER
4724
4725 static int vmx_get_lpage_level(void)
4726 {
4727         if (enable_ept && !cpu_has_vmx_ept_1g_page())
4728                 return PT_DIRECTORY_LEVEL;
4729         else
4730                 /* For shadow and EPT supported 1GB page */
4731                 return PT_PDPE_LEVEL;
4732 }
4733
4734 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4735 {
4736         struct kvm_cpuid_entry2 *best;
4737         struct vcpu_vmx *vmx = to_vmx(vcpu);
4738         u32 exec_control;
4739
4740         vmx->rdtscp_enabled = false;
4741         if (vmx_rdtscp_supported()) {
4742                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4743                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4744                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4745                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4746                                 vmx->rdtscp_enabled = true;
4747                         else {
4748                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4749                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4750                                                 exec_control);
4751                         }
4752                 }
4753         }
4754 }
4755
4756 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4757 {
4758 }
4759
4760 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
4761                                struct x86_instruction_info *info,
4762                                enum x86_intercept_stage stage)
4763 {
4764         return X86EMUL_CONTINUE;
4765 }
4766
4767 static struct kvm_x86_ops vmx_x86_ops = {
4768         .cpu_has_kvm_support = cpu_has_kvm_support,
4769         .disabled_by_bios = vmx_disabled_by_bios,
4770         .hardware_setup = hardware_setup,
4771         .hardware_unsetup = hardware_unsetup,
4772         .check_processor_compatibility = vmx_check_processor_compat,
4773         .hardware_enable = hardware_enable,
4774         .hardware_disable = hardware_disable,
4775         .cpu_has_accelerated_tpr = report_flexpriority,
4776
4777         .vcpu_create = vmx_create_vcpu,
4778         .vcpu_free = vmx_free_vcpu,
4779         .vcpu_reset = vmx_vcpu_reset,
4780
4781         .prepare_guest_switch = vmx_save_host_state,
4782         .vcpu_load = vmx_vcpu_load,
4783         .vcpu_put = vmx_vcpu_put,
4784
4785         .set_guest_debug = set_guest_debug,
4786         .get_msr = vmx_get_msr,
4787         .set_msr = vmx_set_msr,
4788         .get_segment_base = vmx_get_segment_base,
4789         .get_segment = vmx_get_segment,
4790         .set_segment = vmx_set_segment,
4791         .get_cpl = vmx_get_cpl,
4792         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4793         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4794         .decache_cr3 = vmx_decache_cr3,
4795         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4796         .set_cr0 = vmx_set_cr0,
4797         .set_cr3 = vmx_set_cr3,
4798         .set_cr4 = vmx_set_cr4,
4799         .set_efer = vmx_set_efer,
4800         .get_idt = vmx_get_idt,
4801         .set_idt = vmx_set_idt,
4802         .get_gdt = vmx_get_gdt,
4803         .set_gdt = vmx_set_gdt,
4804         .set_dr7 = vmx_set_dr7,
4805         .cache_reg = vmx_cache_reg,
4806         .get_rflags = vmx_get_rflags,
4807         .set_rflags = vmx_set_rflags,
4808         .fpu_activate = vmx_fpu_activate,
4809         .fpu_deactivate = vmx_fpu_deactivate,
4810
4811         .tlb_flush = vmx_flush_tlb,
4812
4813         .run = vmx_vcpu_run,
4814         .handle_exit = vmx_handle_exit,
4815         .skip_emulated_instruction = skip_emulated_instruction,
4816         .set_interrupt_shadow = vmx_set_interrupt_shadow,
4817         .get_interrupt_shadow = vmx_get_interrupt_shadow,
4818         .patch_hypercall = vmx_patch_hypercall,
4819         .set_irq = vmx_inject_irq,
4820         .set_nmi = vmx_inject_nmi,
4821         .queue_exception = vmx_queue_exception,
4822         .cancel_injection = vmx_cancel_injection,
4823         .interrupt_allowed = vmx_interrupt_allowed,
4824         .nmi_allowed = vmx_nmi_allowed,
4825         .get_nmi_mask = vmx_get_nmi_mask,
4826         .set_nmi_mask = vmx_set_nmi_mask,
4827         .enable_nmi_window = enable_nmi_window,
4828         .enable_irq_window = enable_irq_window,
4829         .update_cr8_intercept = update_cr8_intercept,
4830
4831         .set_tss_addr = vmx_set_tss_addr,
4832         .get_tdp_level = get_ept_level,
4833         .get_mt_mask = vmx_get_mt_mask,
4834
4835         .get_exit_info = vmx_get_exit_info,
4836         .exit_reasons_str = vmx_exit_reasons_str,
4837
4838         .get_lpage_level = vmx_get_lpage_level,
4839
4840         .cpuid_update = vmx_cpuid_update,
4841
4842         .rdtscp_supported = vmx_rdtscp_supported,
4843
4844         .set_supported_cpuid = vmx_set_supported_cpuid,
4845
4846         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
4847
4848         .set_tsc_khz = vmx_set_tsc_khz,
4849         .write_tsc_offset = vmx_write_tsc_offset,
4850         .adjust_tsc_offset = vmx_adjust_tsc_offset,
4851         .compute_tsc_offset = vmx_compute_tsc_offset,
4852
4853         .set_tdp_cr3 = vmx_set_cr3,
4854
4855         .check_intercept = vmx_check_intercept,
4856 };
4857
4858 static int __init vmx_init(void)
4859 {
4860         int r, i;
4861
4862         rdmsrl_safe(MSR_EFER, &host_efer);
4863
4864         for (i = 0; i < NR_VMX_MSR; ++i)
4865                 kvm_define_shared_msr(i, vmx_msr_index[i]);
4866
4867         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4868         if (!vmx_io_bitmap_a)
4869                 return -ENOMEM;
4870
4871         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4872         if (!vmx_io_bitmap_b) {
4873                 r = -ENOMEM;
4874                 goto out;
4875         }
4876
4877         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4878         if (!vmx_msr_bitmap_legacy) {
4879                 r = -ENOMEM;
4880                 goto out1;
4881         }
4882
4883         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4884         if (!vmx_msr_bitmap_longmode) {
4885                 r = -ENOMEM;
4886                 goto out2;
4887         }
4888
4889         /*
4890          * Allow direct access to the PC debug port (it is often used for I/O
4891          * delays, but the vmexits simply slow things down).
4892          */
4893         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4894         clear_bit(0x80, vmx_io_bitmap_a);
4895
4896         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4897
4898         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4899         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4900
4901         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4902
4903         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4904                      __alignof__(struct vcpu_vmx), THIS_MODULE);
4905         if (r)
4906                 goto out3;
4907
4908         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4909         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4910         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4911         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4912         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4913         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4914
4915         if (enable_ept) {
4916                 bypass_guest_pf = 0;
4917                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4918                                 VMX_EPT_EXECUTABLE_MASK);
4919                 kvm_enable_tdp();
4920         } else
4921                 kvm_disable_tdp();
4922
4923         if (bypass_guest_pf)
4924                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4925
4926         return 0;
4927
4928 out3:
4929         free_page((unsigned long)vmx_msr_bitmap_longmode);
4930 out2:
4931         free_page((unsigned long)vmx_msr_bitmap_legacy);
4932 out1:
4933         free_page((unsigned long)vmx_io_bitmap_b);
4934 out:
4935         free_page((unsigned long)vmx_io_bitmap_a);
4936         return r;
4937 }
4938
4939 static void __exit vmx_exit(void)
4940 {
4941         free_page((unsigned long)vmx_msr_bitmap_legacy);
4942         free_page((unsigned long)vmx_msr_bitmap_longmode);
4943         free_page((unsigned long)vmx_io_bitmap_b);
4944         free_page((unsigned long)vmx_io_bitmap_a);
4945
4946         kvm_exit();
4947 }
4948
4949 module_init(vmx_init)
4950 module_exit(vmx_exit)