arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/kvm_host.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31 #include <linux/tboot.h>
  32 #include "kvm_cache_regs.h"
  33 #include "x86.h"
  34
  35 #include <asm/io.h>
  36 #include <asm/desc.h>
  37 #include <asm/vmx.h>
  38 #include <asm/virtext.h>
  39 #include <asm/mce.h>
  40 #include <asm/i387.h>
  41 #include <asm/xcr.h>
  42
  43 #include "trace.h"
  44
  45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  46 #define __ex_clear(x, reg) \
  47         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  48
  49 MODULE_AUTHOR("Qumranet");
  50 MODULE_LICENSE("GPL");
  51
  52 static int __read_mostly bypass_guest_pf = 1;
  53 module_param(bypass_guest_pf, bool, S_IRUGO);
  54
  55 static int __read_mostly enable_vpid = 1;
  56 module_param_named(vpid, enable_vpid, bool, 0444);
  57
  58 static int __read_mostly flexpriority_enabled = 1;
  59 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  60
  61 static int __read_mostly enable_ept = 1;
  62 module_param_named(ept, enable_ept, bool, S_IRUGO);
  63
  64 static int __read_mostly enable_unrestricted_guest = 1;
  65 module_param_named(unrestricted_guest,
  66                         enable_unrestricted_guest, bool, S_IRUGO);
  67
  68 static int __read_mostly emulate_invalid_guest_state = 0;
  69 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  70
  71 static int __read_mostly vmm_exclusive = 1;
  72 module_param(vmm_exclusive, bool, S_IRUGO);
  73
  74 static int __read_mostly yield_on_hlt = 1;
  75 module_param(yield_on_hlt, bool, S_IRUGO);
  76
  77 /*
  78  * If nested=1, nested virtualization is supported, i.e., guests may use
  79  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  80  * use VMX instructions.
  81  */
  82 static int __read_mostly nested = 0;
  83 module_param(nested, bool, S_IRUGO);
  84
  85 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  86         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  87 #define KVM_GUEST_CR0_MASK                                              \
  88         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  89 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  90         (X86_CR0_WP | X86_CR0_NE)
  91 #define KVM_VM_CR0_ALWAYS_ON                                            \
  92         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  93 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  94         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  95          | X86_CR4_OSXMMEXCPT)
  96
  97 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  98 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  99
 100 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 101
 102 /*
 103  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 104  * ple_gap:    upper bound on the amount of time between two successive
 105  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 106  *             According to test, this time is usually smaller than 128 cycles.
 107  * ple_window: upper bound on the amount of time a guest is allowed to execute
 108  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 109  *             less than 2^12 cycles
 110  * Time is measured based on a counter that runs at the same rate as the TSC,
 111  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 112  */
 113 #define KVM_VMX_DEFAULT_PLE_GAP    128
 114 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 115 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 116 module_param(ple_gap, int, S_IRUGO);
 117
 118 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 119 module_param(ple_window, int, S_IRUGO);
 120
 121 #define NR_AUTOLOAD_MSRS 1
 122 #define VMCS02_POOL_SIZE 1
 123
 124 struct vmcs {
 125         u32 revision_id;
 126         u32 abort;
 127         char data[0];
 128 };
 129
 130 /*
 131  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 132  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 133  * loaded on this CPU (so we can clear them if the CPU goes down).
 134  */
 135 struct loaded_vmcs {
 136         struct vmcs *vmcs;
 137         int cpu;
 138         int launched;
 139         struct list_head loaded_vmcss_on_cpu_link;
 140 };
 141
 142 struct shared_msr_entry {
 143         unsigned index;
 144         u64 data;
 145         u64 mask;
 146 };
 147
 148 /*
 149  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 150  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 151  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 152  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 153  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 154  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 155  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 156  * underlying hardware which will be used to run L2.
 157  * This structure is packed to ensure that its layout is identical across
 158  * machines (necessary for live migration).
 159  * If there are changes in this struct, VMCS12_REVISION must be changed.
 160  */
 161 typedef u64 natural_width;
 162 struct __packed vmcs12 {
 163         /* According to the Intel spec, a VMCS region must start with the
 164          * following two fields. Then follow implementation-specific data.
 165          */
 166         u32 revision_id;
 167         u32 abort;
 168
 169         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 170         u32 padding[7]; /* room for future expansion */
 171
 172         u64 io_bitmap_a;
 173         u64 io_bitmap_b;
 174         u64 msr_bitmap;
 175         u64 vm_exit_msr_store_addr;
 176         u64 vm_exit_msr_load_addr;
 177         u64 vm_entry_msr_load_addr;
 178         u64 tsc_offset;
 179         u64 virtual_apic_page_addr;
 180         u64 apic_access_addr;
 181         u64 ept_pointer;
 182         u64 guest_physical_address;
 183         u64 vmcs_link_pointer;
 184         u64 guest_ia32_debugctl;
 185         u64 guest_ia32_pat;
 186         u64 guest_ia32_efer;
 187         u64 guest_ia32_perf_global_ctrl;
 188         u64 guest_pdptr0;
 189         u64 guest_pdptr1;
 190         u64 guest_pdptr2;
 191         u64 guest_pdptr3;
 192         u64 host_ia32_pat;
 193         u64 host_ia32_efer;
 194         u64 host_ia32_perf_global_ctrl;
 195         u64 padding64[8]; /* room for future expansion */
 196         /*
 197          * To allow migration of L1 (complete with its L2 guests) between
 198          * machines of different natural widths (32 or 64 bit), we cannot have
 199          * unsigned long fields with no explict size. We use u64 (aliased
 200          * natural_width) instead. Luckily, x86 is little-endian.
 201          */
 202         natural_width cr0_guest_host_mask;
 203         natural_width cr4_guest_host_mask;
 204         natural_width cr0_read_shadow;
 205         natural_width cr4_read_shadow;
 206         natural_width cr3_target_value0;
 207         natural_width cr3_target_value1;
 208         natural_width cr3_target_value2;
 209         natural_width cr3_target_value3;
 210         natural_width exit_qualification;
 211         natural_width guest_linear_address;
 212         natural_width guest_cr0;
 213         natural_width guest_cr3;
 214         natural_width guest_cr4;
 215         natural_width guest_es_base;
 216         natural_width guest_cs_base;
 217         natural_width guest_ss_base;
 218         natural_width guest_ds_base;
 219         natural_width guest_fs_base;
 220         natural_width guest_gs_base;
 221         natural_width guest_ldtr_base;
 222         natural_width guest_tr_base;
 223         natural_width guest_gdtr_base;
 224         natural_width guest_idtr_base;
 225         natural_width guest_dr7;
 226         natural_width guest_rsp;
 227         natural_width guest_rip;
 228         natural_width guest_rflags;
 229         natural_width guest_pending_dbg_exceptions;
 230         natural_width guest_sysenter_esp;
 231         natural_width guest_sysenter_eip;
 232         natural_width host_cr0;
 233         natural_width host_cr3;
 234         natural_width host_cr4;
 235         natural_width host_fs_base;
 236         natural_width host_gs_base;
 237         natural_width host_tr_base;
 238         natural_width host_gdtr_base;
 239         natural_width host_idtr_base;
 240         natural_width host_ia32_sysenter_esp;
 241         natural_width host_ia32_sysenter_eip;
 242         natural_width host_rsp;
 243         natural_width host_rip;
 244         natural_width paddingl[8]; /* room for future expansion */
 245         u32 pin_based_vm_exec_control;
 246         u32 cpu_based_vm_exec_control;
 247         u32 exception_bitmap;
 248         u32 page_fault_error_code_mask;
 249         u32 page_fault_error_code_match;
 250         u32 cr3_target_count;
 251         u32 vm_exit_controls;
 252         u32 vm_exit_msr_store_count;
 253         u32 vm_exit_msr_load_count;
 254         u32 vm_entry_controls;
 255         u32 vm_entry_msr_load_count;
 256         u32 vm_entry_intr_info_field;
 257         u32 vm_entry_exception_error_code;
 258         u32 vm_entry_instruction_len;
 259         u32 tpr_threshold;
 260         u32 secondary_vm_exec_control;
 261         u32 vm_instruction_error;
 262         u32 vm_exit_reason;
 263         u32 vm_exit_intr_info;
 264         u32 vm_exit_intr_error_code;
 265         u32 idt_vectoring_info_field;
 266         u32 idt_vectoring_error_code;
 267         u32 vm_exit_instruction_len;
 268         u32 vmx_instruction_info;
 269         u32 guest_es_limit;
 270         u32 guest_cs_limit;
 271         u32 guest_ss_limit;
 272         u32 guest_ds_limit;
 273         u32 guest_fs_limit;
 274         u32 guest_gs_limit;
 275         u32 guest_ldtr_limit;
 276         u32 guest_tr_limit;
 277         u32 guest_gdtr_limit;
 278         u32 guest_idtr_limit;
 279         u32 guest_es_ar_bytes;
 280         u32 guest_cs_ar_bytes;
 281         u32 guest_ss_ar_bytes;
 282         u32 guest_ds_ar_bytes;
 283         u32 guest_fs_ar_bytes;
 284         u32 guest_gs_ar_bytes;
 285         u32 guest_ldtr_ar_bytes;
 286         u32 guest_tr_ar_bytes;
 287         u32 guest_interruptibility_info;
 288         u32 guest_activity_state;
 289         u32 guest_sysenter_cs;
 290         u32 host_ia32_sysenter_cs;
 291         u32 padding32[8]; /* room for future expansion */
 292         u16 virtual_processor_id;
 293         u16 guest_es_selector;
 294         u16 guest_cs_selector;
 295         u16 guest_ss_selector;
 296         u16 guest_ds_selector;
 297         u16 guest_fs_selector;
 298         u16 guest_gs_selector;
 299         u16 guest_ldtr_selector;
 300         u16 guest_tr_selector;
 301         u16 host_es_selector;
 302         u16 host_cs_selector;
 303         u16 host_ss_selector;
 304         u16 host_ds_selector;
 305         u16 host_fs_selector;
 306         u16 host_gs_selector;
 307         u16 host_tr_selector;
 308 };
 309
 310 /*
 311  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 312  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 313  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 314  */
 315 #define VMCS12_REVISION 0x11e57ed0
 316
 317 /*
 318  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 319  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 320  * current implementation, 4K are reserved to avoid future complications.
 321  */
 322 #define VMCS12_SIZE 0x1000
 323
 324 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 325 struct vmcs02_list {
 326         struct list_head list;
 327         gpa_t vmptr;
 328         struct loaded_vmcs vmcs02;
 329 };
 330
 331 /*
 332  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 333  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 334  */
 335 struct nested_vmx {
 336         /* Has the level1 guest done vmxon? */
 337         bool vmxon;
 338
 339         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 340         gpa_t current_vmptr;
 341         /* The host-usable pointer to the above */
 342         struct page *current_vmcs12_page;
 343         struct vmcs12 *current_vmcs12;
 344
 345         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 346         struct list_head vmcs02_pool;
 347         int vmcs02_num;
 348         u64 vmcs01_tsc_offset;
 349         /*
 350          * Guest pages referred to in vmcs02 with host-physical pointers, so
 351          * we must keep them pinned while L2 runs.
 352          */
 353         struct page *apic_access_page;
 354 };
 355
 356 struct vcpu_vmx {
 357         struct kvm_vcpu       vcpu;
 358         unsigned long         host_rsp;
 359         u8                    fail;
 360         u8                    cpl;
 361         bool                  nmi_known_unmasked;
 362         u32                   exit_intr_info;
 363         u32                   idt_vectoring_info;
 364         ulong                 rflags;
 365         struct shared_msr_entry *guest_msrs;
 366         int                   nmsrs;
 367         int                   save_nmsrs;
 368 #ifdef CONFIG_X86_64
 369         u64                   msr_host_kernel_gs_base;
 370         u64                   msr_guest_kernel_gs_base;
 371 #endif
 372         /*
 373          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 374          * non-nested (L1) guest, it always points to vmcs01. For a nested
 375          * guest (L2), it points to a different VMCS.
 376          */
 377         struct loaded_vmcs    vmcs01;
 378         struct loaded_vmcs   *loaded_vmcs;
 379         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 380         struct msr_autoload {
 381                 unsigned nr;
 382                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 383                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 384         } msr_autoload;
 385         struct {
 386                 int           loaded;
 387                 u16           fs_sel, gs_sel, ldt_sel;
 388                 int           gs_ldt_reload_needed;
 389                 int           fs_reload_needed;
 390         } host_state;
 391         struct {
 392                 int vm86_active;
 393                 ulong save_rflags;
 394                 struct kvm_save_segment {
 395                         u16 selector;
 396                         unsigned long base;
 397                         u32 limit;
 398                         u32 ar;
 399                 } tr, es, ds, fs, gs;
 400         } rmode;
 401         struct {
 402                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 403                 struct kvm_save_segment seg[8];
 404         } segment_cache;
 405         int vpid;
 406         bool emulation_required;
 407
 408         /* Support for vnmi-less CPUs */
 409         int soft_vnmi_blocked;
 410         ktime_t entry_time;
 411         s64 vnmi_blocked_time;
 412         u32 exit_reason;
 413
 414         bool rdtscp_enabled;
 415
 416         /* Support for a guest hypervisor (nested VMX) */
 417         struct nested_vmx nested;
 418 };
 419
 420 enum segment_cache_field {
 421         SEG_FIELD_SEL = 0,
 422         SEG_FIELD_BASE = 1,
 423         SEG_FIELD_LIMIT = 2,
 424         SEG_FIELD_AR = 3,
 425
 426         SEG_FIELD_NR = 4
 427 };
 428
 429 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 430 {
 431         return container_of(vcpu, struct vcpu_vmx, vcpu);
 432 }
 433
 434 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 435 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 436 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 437                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 438
 439 static unsigned short vmcs_field_to_offset_table[] = {
 440         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 441         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 442         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 443         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 444         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 445         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 446         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 447         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 448         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 449         FIELD(HOST_ES_SELECTOR, host_es_selector),
 450         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 451         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 452         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 453         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 454         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 455         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 456         FIELD64(IO_BITMAP_A, io_bitmap_a),
 457         FIELD64(IO_BITMAP_B, io_bitmap_b),
 458         FIELD64(MSR_BITMAP, msr_bitmap),
 459         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 460         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 461         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 462         FIELD64(TSC_OFFSET, tsc_offset),
 463         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 464         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 465         FIELD64(EPT_POINTER, ept_pointer),
 466         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 467         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 468         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 469         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 470         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 471         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 472         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 473         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 474         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 475         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 476         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 477         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 478         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 479         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 480         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 481         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 482         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 483         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 484         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 485         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 486         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 487         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 488         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 489         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 490         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 491         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 492         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 493         FIELD(TPR_THRESHOLD, tpr_threshold),
 494         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 495         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 496         FIELD(VM_EXIT_REASON, vm_exit_reason),
 497         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 498         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 499         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 500         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 501         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 502         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 503         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 504         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 505         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 506         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 507         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 508         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 509         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 510         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 511         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 512         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 513         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 514         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 515         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 516         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 517         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 518         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 519         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 520         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 521         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 522         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 523         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 524         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 525         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 526         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 527         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 528         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 529         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 530         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 531         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 532         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 533         FIELD(EXIT_QUALIFICATION, exit_qualification),
 534         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 535         FIELD(GUEST_CR0, guest_cr0),
 536         FIELD(GUEST_CR3, guest_cr3),
 537         FIELD(GUEST_CR4, guest_cr4),
 538         FIELD(GUEST_ES_BASE, guest_es_base),
 539         FIELD(GUEST_CS_BASE, guest_cs_base),
 540         FIELD(GUEST_SS_BASE, guest_ss_base),
 541         FIELD(GUEST_DS_BASE, guest_ds_base),
 542         FIELD(GUEST_FS_BASE, guest_fs_base),
 543         FIELD(GUEST_GS_BASE, guest_gs_base),
 544         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 545         FIELD(GUEST_TR_BASE, guest_tr_base),
 546         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 547         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 548         FIELD(GUEST_DR7, guest_dr7),
 549         FIELD(GUEST_RSP, guest_rsp),
 550         FIELD(GUEST_RIP, guest_rip),
 551         FIELD(GUEST_RFLAGS, guest_rflags),
 552         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 553         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 554         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 555         FIELD(HOST_CR0, host_cr0),
 556         FIELD(HOST_CR3, host_cr3),
 557         FIELD(HOST_CR4, host_cr4),
 558         FIELD(HOST_FS_BASE, host_fs_base),
 559         FIELD(HOST_GS_BASE, host_gs_base),
 560         FIELD(HOST_TR_BASE, host_tr_base),
 561         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 562         FIELD(HOST_IDTR_BASE, host_idtr_base),
 563         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 564         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 565         FIELD(HOST_RSP, host_rsp),
 566         FIELD(HOST_RIP, host_rip),
 567 };
 568 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 569
 570 static inline short vmcs_field_to_offset(unsigned long field)
 571 {
 572         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 573                 return -1;
 574         return vmcs_field_to_offset_table[field];
 575 }
 576
 577 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 578 {
 579         return to_vmx(vcpu)->nested.current_vmcs12;
 580 }
 581
 582 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 583 {
 584         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 585         if (is_error_page(page)) {
 586                 kvm_release_page_clean(page);
 587                 return NULL;
 588         }
 589         return page;
 590 }
 591
 592 static void nested_release_page(struct page *page)
 593 {
 594         kvm_release_page_dirty(page);
 595 }
 596
 597 static void nested_release_page_clean(struct page *page)
 598 {
 599         kvm_release_page_clean(page);
 600 }
 601
 602 static u64 construct_eptp(unsigned long root_hpa);
 603 static void kvm_cpu_vmxon(u64 addr);
 604 static void kvm_cpu_vmxoff(void);
 605 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 606 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 607
 608 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 609 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 610 /*
 611  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 612  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 613  */
 614 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 615 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 616
 617 static unsigned long *vmx_io_bitmap_a;
 618 static unsigned long *vmx_io_bitmap_b;
 619 static unsigned long *vmx_msr_bitmap_legacy;
 620 static unsigned long *vmx_msr_bitmap_longmode;
 621
 622 static bool cpu_has_load_ia32_efer;
 623
 624 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 625 static DEFINE_SPINLOCK(vmx_vpid_lock);
 626
 627 static struct vmcs_config {
 628         int size;
 629         int order;
 630         u32 revision_id;
 631         u32 pin_based_exec_ctrl;
 632         u32 cpu_based_exec_ctrl;
 633         u32 cpu_based_2nd_exec_ctrl;
 634         u32 vmexit_ctrl;
 635         u32 vmentry_ctrl;
 636 } vmcs_config;
 637
 638 static struct vmx_capability {
 639         u32 ept;
 640         u32 vpid;
 641 } vmx_capability;
 642
 643 #define VMX_SEGMENT_FIELD(seg)                                  \
 644         [VCPU_SREG_##seg] = {                                   \
 645                 .selector = GUEST_##seg##_SELECTOR,             \
 646                 .base = GUEST_##seg##_BASE,                     \
 647                 .limit = GUEST_##seg##_LIMIT,                   \
 648                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 649         }
 650
 651 static struct kvm_vmx_segment_field {
 652         unsigned selector;
 653         unsigned base;
 654         unsigned limit;
 655         unsigned ar_bytes;
 656 } kvm_vmx_segment_fields[] = {
 657         VMX_SEGMENT_FIELD(CS),
 658         VMX_SEGMENT_FIELD(DS),
 659         VMX_SEGMENT_FIELD(ES),
 660         VMX_SEGMENT_FIELD(FS),
 661         VMX_SEGMENT_FIELD(GS),
 662         VMX_SEGMENT_FIELD(SS),
 663         VMX_SEGMENT_FIELD(TR),
 664         VMX_SEGMENT_FIELD(LDTR),
 665 };
 666
 667 static u64 host_efer;
 668
 669 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 670
 671 /*
 672  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 673  * away by decrementing the array size.
 674  */
 675 static const u32 vmx_msr_index[] = {
 676 #ifdef CONFIG_X86_64
 677         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 678 #endif
 679         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 680 };
 681 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 682
 683 static inline bool is_page_fault(u32 intr_info)
 684 {
 685         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 686                              INTR_INFO_VALID_MASK)) ==
 687                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 688 }
 689
 690 static inline bool is_no_device(u32 intr_info)
 691 {
 692         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 693                              INTR_INFO_VALID_MASK)) ==
 694                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 695 }
 696
 697 static inline bool is_invalid_opcode(u32 intr_info)
 698 {
 699         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 700                              INTR_INFO_VALID_MASK)) ==
 701                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 702 }
 703
 704 static inline bool is_external_interrupt(u32 intr_info)
 705 {
 706         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 707                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 708 }
 709
 710 static inline bool is_machine_check(u32 intr_info)
 711 {
 712         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 713                              INTR_INFO_VALID_MASK)) ==
 714                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 715 }
 716
 717 static inline bool cpu_has_vmx_msr_bitmap(void)
 718 {
 719         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 720 }
 721
 722 static inline bool cpu_has_vmx_tpr_shadow(void)
 723 {
 724         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 725 }
 726
 727 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 728 {
 729         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 730 }
 731
 732 static inline bool cpu_has_secondary_exec_ctrls(void)
 733 {
 734         return vmcs_config.cpu_based_exec_ctrl &
 735                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 736 }
 737
 738 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 739 {
 740         return vmcs_config.cpu_based_2nd_exec_ctrl &
 741                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 742 }
 743
 744 static inline bool cpu_has_vmx_flexpriority(void)
 745 {
 746         return cpu_has_vmx_tpr_shadow() &&
 747                 cpu_has_vmx_virtualize_apic_accesses();
 748 }
 749
 750 static inline bool cpu_has_vmx_ept_execute_only(void)
 751 {
 752         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 753 }
 754
 755 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 756 {
 757         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 758 }
 759
 760 static inline bool cpu_has_vmx_eptp_writeback(void)
 761 {
 762         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 763 }
 764
 765 static inline bool cpu_has_vmx_ept_2m_page(void)
 766 {
 767         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 768 }
 769
 770 static inline bool cpu_has_vmx_ept_1g_page(void)
 771 {
 772         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 773 }
 774
 775 static inline bool cpu_has_vmx_ept_4levels(void)
 776 {
 777         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 778 }
 779
 780 static inline bool cpu_has_vmx_invept_individual_addr(void)
 781 {
 782         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 783 }
 784
 785 static inline bool cpu_has_vmx_invept_context(void)
 786 {
 787         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 788 }
 789
 790 static inline bool cpu_has_vmx_invept_global(void)
 791 {
 792         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 793 }
 794
 795 static inline bool cpu_has_vmx_invvpid_single(void)
 796 {
 797         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 798 }
 799
 800 static inline bool cpu_has_vmx_invvpid_global(void)
 801 {
 802         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 803 }
 804
 805 static inline bool cpu_has_vmx_ept(void)
 806 {
 807         return vmcs_config.cpu_based_2nd_exec_ctrl &
 808                 SECONDARY_EXEC_ENABLE_EPT;
 809 }
 810
 811 static inline bool cpu_has_vmx_unrestricted_guest(void)
 812 {
 813         return vmcs_config.cpu_based_2nd_exec_ctrl &
 814                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 815 }
 816
 817 static inline bool cpu_has_vmx_ple(void)
 818 {
 819         return vmcs_config.cpu_based_2nd_exec_ctrl &
 820                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 821 }
 822
 823 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 824 {
 825         return flexpriority_enabled && irqchip_in_kernel(kvm);
 826 }
 827
 828 static inline bool cpu_has_vmx_vpid(void)
 829 {
 830         return vmcs_config.cpu_based_2nd_exec_ctrl &
 831                 SECONDARY_EXEC_ENABLE_VPID;
 832 }
 833
 834 static inline bool cpu_has_vmx_rdtscp(void)
 835 {
 836         return vmcs_config.cpu_based_2nd_exec_ctrl &
 837                 SECONDARY_EXEC_RDTSCP;
 838 }
 839
 840 static inline bool cpu_has_virtual_nmis(void)
 841 {
 842         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 843 }
 844
 845 static inline bool cpu_has_vmx_wbinvd_exit(void)
 846 {
 847         return vmcs_config.cpu_based_2nd_exec_ctrl &
 848                 SECONDARY_EXEC_WBINVD_EXITING;
 849 }
 850
 851 static inline bool report_flexpriority(void)
 852 {
 853         return flexpriority_enabled;
 854 }
 855
 856 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
 857 {
 858         return vmcs12->cpu_based_vm_exec_control & bit;
 859 }
 860
 861 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
 862 {
 863         return (vmcs12->cpu_based_vm_exec_control &
 864                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
 865                 (vmcs12->secondary_vm_exec_control & bit);
 866 }
 867
 868 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 869 {
 870         int i;
 871
 872         for (i = 0; i < vmx->nmsrs; ++i)
 873                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 874                         return i;
 875         return -1;
 876 }
 877
 878 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 879 {
 880     struct {
 881         u64 vpid : 16;
 882         u64 rsvd : 48;
 883         u64 gva;
 884     } operand = { vpid, 0, gva };
 885
 886     asm volatile (__ex(ASM_VMX_INVVPID)
 887                   /* CF==1 or ZF==1 --> rc = -1 */
 888                   "; ja 1f ; ud2 ; 1:"
 889                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 890 }
 891
 892 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 893 {
 894         struct {
 895                 u64 eptp, gpa;
 896         } operand = {eptp, gpa};
 897
 898         asm volatile (__ex(ASM_VMX_INVEPT)
 899                         /* CF==1 or ZF==1 --> rc = -1 */
 900                         "; ja 1f ; ud2 ; 1:\n"
 901                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 902 }
 903
 904 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 905 {
 906         int i;
 907
 908         i = __find_msr_index(vmx, msr);
 909         if (i >= 0)
 910                 return &vmx->guest_msrs[i];
 911         return NULL;
 912 }
 913
 914 static void vmcs_clear(struct vmcs *vmcs)
 915 {
 916         u64 phys_addr = __pa(vmcs);
 917         u8 error;
 918
 919         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 920                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 921                       : "cc", "memory");
 922         if (error)
 923                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 924                        vmcs, phys_addr);
 925 }
 926
 927 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 928 {
 929         vmcs_clear(loaded_vmcs->vmcs);
 930         loaded_vmcs->cpu = -1;
 931         loaded_vmcs->launched = 0;
 932 }
 933
 934 static void vmcs_load(struct vmcs *vmcs)
 935 {
 936         u64 phys_addr = __pa(vmcs);
 937         u8 error;
 938
 939         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 940                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 941                         : "cc", "memory");
 942         if (error)
 943                 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 944                        vmcs, phys_addr);
 945 }
 946
 947 static void __loaded_vmcs_clear(void *arg)
 948 {
 949         struct loaded_vmcs *loaded_vmcs = arg;
 950         int cpu = raw_smp_processor_id();
 951
 952         if (loaded_vmcs->cpu != cpu)
 953                 return; /* vcpu migration can race with cpu offline */
 954         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 955                 per_cpu(current_vmcs, cpu) = NULL;
 956         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 957         loaded_vmcs_init(loaded_vmcs);
 958 }
 959
 960 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 961 {
 962         if (loaded_vmcs->cpu != -1)
 963                 smp_call_function_single(
 964                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
 965 }
 966
 967 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
 968 {
 969         if (vmx->vpid == 0)
 970                 return;
 971
 972         if (cpu_has_vmx_invvpid_single())
 973                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 974 }
 975
 976 static inline void vpid_sync_vcpu_global(void)
 977 {
 978         if (cpu_has_vmx_invvpid_global())
 979                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
 980 }
 981
 982 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
 983 {
 984         if (cpu_has_vmx_invvpid_single())
 985                 vpid_sync_vcpu_single(vmx);
 986         else
 987                 vpid_sync_vcpu_global();
 988 }
 989
 990 static inline void ept_sync_global(void)
 991 {
 992         if (cpu_has_vmx_invept_global())
 993                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 994 }
 995
 996 static inline void ept_sync_context(u64 eptp)
 997 {
 998         if (enable_ept) {
 999                 if (cpu_has_vmx_invept_context())
1000                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1001                 else
1002                         ept_sync_global();
1003         }
1004 }
1005
1006 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1007 {
1008         if (enable_ept) {
1009                 if (cpu_has_vmx_invept_individual_addr())
1010                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1011                                         eptp, gpa);
1012                 else
1013                         ept_sync_context(eptp);
1014         }
1015 }
1016
1017 static __always_inline unsigned long vmcs_readl(unsigned long field)
1018 {
1019         unsigned long value;
1020
1021         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1022                       : "=a"(value) : "d"(field) : "cc");
1023         return value;
1024 }
1025
1026 static __always_inline u16 vmcs_read16(unsigned long field)
1027 {
1028         return vmcs_readl(field);
1029 }
1030
1031 static __always_inline u32 vmcs_read32(unsigned long field)
1032 {
1033         return vmcs_readl(field);
1034 }
1035
1036 static __always_inline u64 vmcs_read64(unsigned long field)
1037 {
1038 #ifdef CONFIG_X86_64
1039         return vmcs_readl(field);
1040 #else
1041         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1042 #endif
1043 }
1044
1045 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1046 {
1047         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1048                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1049         dump_stack();
1050 }
1051
1052 static void vmcs_writel(unsigned long field, unsigned long value)
1053 {
1054         u8 error;
1055
1056         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1057                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1058         if (unlikely(error))
1059                 vmwrite_error(field, value);
1060 }
1061
1062 static void vmcs_write16(unsigned long field, u16 value)
1063 {
1064         vmcs_writel(field, value);
1065 }
1066
1067 static void vmcs_write32(unsigned long field, u32 value)
1068 {
1069         vmcs_writel(field, value);
1070 }
1071
1072 static void vmcs_write64(unsigned long field, u64 value)
1073 {
1074         vmcs_writel(field, value);
1075 #ifndef CONFIG_X86_64
1076         asm volatile ("");
1077         vmcs_writel(field+1, value >> 32);
1078 #endif
1079 }
1080
1081 static void vmcs_clear_bits(unsigned long field, u32 mask)
1082 {
1083         vmcs_writel(field, vmcs_readl(field) & ~mask);
1084 }
1085
1086 static void vmcs_set_bits(unsigned long field, u32 mask)
1087 {
1088         vmcs_writel(field, vmcs_readl(field) | mask);
1089 }
1090
1091 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1092 {
1093         vmx->segment_cache.bitmask = 0;
1094 }
1095
1096 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1097                                        unsigned field)
1098 {
1099         bool ret;
1100         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1101
1102         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1103                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1104                 vmx->segment_cache.bitmask = 0;
1105         }
1106         ret = vmx->segment_cache.bitmask & mask;
1107         vmx->segment_cache.bitmask |= mask;
1108         return ret;
1109 }
1110
1111 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1112 {
1113         u16 *p = &vmx->segment_cache.seg[seg].selector;
1114
1115         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1116                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1117         return *p;
1118 }
1119
1120 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1121 {
1122         ulong *p = &vmx->segment_cache.seg[seg].base;
1123
1124         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1125                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1126         return *p;
1127 }
1128
1129 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1130 {
1131         u32 *p = &vmx->segment_cache.seg[seg].limit;
1132
1133         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1134                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1135         return *p;
1136 }
1137
1138 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1139 {
1140         u32 *p = &vmx->segment_cache.seg[seg].ar;
1141
1142         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1143                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1144         return *p;
1145 }
1146
1147 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1148 {
1149         u32 eb;
1150
1151         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1152              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1153         if ((vcpu->guest_debug &
1154              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1155             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1156                 eb |= 1u << BP_VECTOR;
1157         if (to_vmx(vcpu)->rmode.vm86_active)
1158                 eb = ~0;
1159         if (enable_ept)
1160                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1161         if (vcpu->fpu_active)
1162                 eb &= ~(1u << NM_VECTOR);
1163         vmcs_write32(EXCEPTION_BITMAP, eb);
1164 }
1165
1166 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1167 {
1168         unsigned i;
1169         struct msr_autoload *m = &vmx->msr_autoload;
1170
1171         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1172                 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1173                 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1174                 return;
1175         }
1176
1177         for (i = 0; i < m->nr; ++i)
1178                 if (m->guest[i].index == msr)
1179                         break;
1180
1181         if (i == m->nr)
1182                 return;
1183         --m->nr;
1184         m->guest[i] = m->guest[m->nr];
1185         m->host[i] = m->host[m->nr];
1186         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1187         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1188 }
1189
1190 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1191                                   u64 guest_val, u64 host_val)
1192 {
1193         unsigned i;
1194         struct msr_autoload *m = &vmx->msr_autoload;
1195
1196         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1197                 vmcs_write64(GUEST_IA32_EFER, guest_val);
1198                 vmcs_write64(HOST_IA32_EFER, host_val);
1199                 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1200                 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1201                 return;
1202         }
1203
1204         for (i = 0; i < m->nr; ++i)
1205                 if (m->guest[i].index == msr)
1206                         break;
1207
1208         if (i == m->nr) {
1209                 ++m->nr;
1210                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1211                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1212         }
1213
1214         m->guest[i].index = msr;
1215         m->guest[i].value = guest_val;
1216         m->host[i].index = msr;
1217         m->host[i].value = host_val;
1218 }
1219
1220 static void reload_tss(void)
1221 {
1222         /*
1223          * VT restores TR but not its size.  Useless.
1224          */
1225         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1226         struct desc_struct *descs;
1227
1228         descs = (void *)gdt->address;
1229         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1230         load_TR_desc();
1231 }
1232
1233 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1234 {
1235         u64 guest_efer;
1236         u64 ignore_bits;
1237
1238         guest_efer = vmx->vcpu.arch.efer;
1239
1240         /*
1241          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1242          * outside long mode
1243          */
1244         ignore_bits = EFER_NX | EFER_SCE;
1245 #ifdef CONFIG_X86_64
1246         ignore_bits |= EFER_LMA | EFER_LME;
1247         /* SCE is meaningful only in long mode on Intel */
1248         if (guest_efer & EFER_LMA)
1249                 ignore_bits &= ~(u64)EFER_SCE;
1250 #endif
1251         guest_efer &= ~ignore_bits;
1252         guest_efer |= host_efer & ignore_bits;
1253         vmx->guest_msrs[efer_offset].data = guest_efer;
1254         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1255
1256         clear_atomic_switch_msr(vmx, MSR_EFER);
1257         /* On ept, can't emulate nx, and must switch nx atomically */
1258         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1259                 guest_efer = vmx->vcpu.arch.efer;
1260                 if (!(guest_efer & EFER_LMA))
1261                         guest_efer &= ~EFER_LME;
1262                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1263                 return false;
1264         }
1265
1266         return true;
1267 }
1268
1269 static unsigned long segment_base(u16 selector)
1270 {
1271         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1272         struct desc_struct *d;
1273         unsigned long table_base;
1274         unsigned long v;
1275
1276         if (!(selector & ~3))
1277                 return 0;
1278
1279         table_base = gdt->address;
1280
1281         if (selector & 4) {           /* from ldt */
1282                 u16 ldt_selector = kvm_read_ldt();
1283
1284                 if (!(ldt_selector & ~3))
1285                         return 0;
1286
1287                 table_base = segment_base(ldt_selector);
1288         }
1289         d = (struct desc_struct *)(table_base + (selector & ~7));
1290         v = get_desc_base(d);
1291 #ifdef CONFIG_X86_64
1292        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1293                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1294 #endif
1295         return v;
1296 }
1297
1298 static inline unsigned long kvm_read_tr_base(void)
1299 {
1300         u16 tr;
1301         asm("str %0" : "=g"(tr));
1302         return segment_base(tr);
1303 }
1304
1305 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1306 {
1307         struct vcpu_vmx *vmx = to_vmx(vcpu);
1308         int i;
1309
1310         if (vmx->host_state.loaded)
1311                 return;
1312
1313         vmx->host_state.loaded = 1;
1314         /*
1315          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1316          * allow segment selectors with cpl > 0 or ti == 1.
1317          */
1318         vmx->host_state.ldt_sel = kvm_read_ldt();
1319         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1320         savesegment(fs, vmx->host_state.fs_sel);
1321         if (!(vmx->host_state.fs_sel & 7)) {
1322                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1323                 vmx->host_state.fs_reload_needed = 0;
1324         } else {
1325                 vmcs_write16(HOST_FS_SELECTOR, 0);
1326                 vmx->host_state.fs_reload_needed = 1;
1327         }
1328         savesegment(gs, vmx->host_state.gs_sel);
1329         if (!(vmx->host_state.gs_sel & 7))
1330                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1331         else {
1332                 vmcs_write16(HOST_GS_SELECTOR, 0);
1333                 vmx->host_state.gs_ldt_reload_needed = 1;
1334         }
1335
1336 #ifdef CONFIG_X86_64
1337         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1338         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1339 #else
1340         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1341         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1342 #endif
1343
1344 #ifdef CONFIG_X86_64
1345         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1346         if (is_long_mode(&vmx->vcpu))
1347                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1348 #endif
1349         for (i = 0; i < vmx->save_nmsrs; ++i)
1350                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1351                                    vmx->guest_msrs[i].data,
1352                                    vmx->guest_msrs[i].mask);
1353 }
1354
1355 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1356 {
1357         if (!vmx->host_state.loaded)
1358                 return;
1359
1360         ++vmx->vcpu.stat.host_state_reload;
1361         vmx->host_state.loaded = 0;
1362 #ifdef CONFIG_X86_64
1363         if (is_long_mode(&vmx->vcpu))
1364                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1365 #endif
1366         if (vmx->host_state.gs_ldt_reload_needed) {
1367                 kvm_load_ldt(vmx->host_state.ldt_sel);
1368 #ifdef CONFIG_X86_64
1369                 load_gs_index(vmx->host_state.gs_sel);
1370 #else
1371                 loadsegment(gs, vmx->host_state.gs_sel);
1372 #endif
1373         }
1374         if (vmx->host_state.fs_reload_needed)
1375                 loadsegment(fs, vmx->host_state.fs_sel);
1376         reload_tss();
1377 #ifdef CONFIG_X86_64
1378         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1379 #endif
1380         if (current_thread_info()->status & TS_USEDFPU)
1381                 clts();
1382         load_gdt(&__get_cpu_var(host_gdt));
1383 }
1384
1385 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1386 {
1387         preempt_disable();
1388         __vmx_load_host_state(vmx);
1389         preempt_enable();
1390 }
1391
1392 /*
1393  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1394  * vcpu mutex is already taken.
1395  */
1396 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1397 {
1398         struct vcpu_vmx *vmx = to_vmx(vcpu);
1399         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1400
1401         if (!vmm_exclusive)
1402                 kvm_cpu_vmxon(phys_addr);
1403         else if (vmx->loaded_vmcs->cpu != cpu)
1404                 loaded_vmcs_clear(vmx->loaded_vmcs);
1405
1406         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1407                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1408                 vmcs_load(vmx->loaded_vmcs->vmcs);
1409         }
1410
1411         if (vmx->loaded_vmcs->cpu != cpu) {
1412                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1413                 unsigned long sysenter_esp;
1414
1415                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1416                 local_irq_disable();
1417                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1418                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1419                 local_irq_enable();
1420
1421                 /*
1422                  * Linux uses per-cpu TSS and GDT, so set these when switching
1423                  * processors.
1424                  */
1425                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1426                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1427
1428                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1429                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1430                 vmx->loaded_vmcs->cpu = cpu;
1431         }
1432 }
1433
1434 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1435 {
1436         __vmx_load_host_state(to_vmx(vcpu));
1437         if (!vmm_exclusive) {
1438                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1439                 vcpu->cpu = -1;
1440                 kvm_cpu_vmxoff();
1441         }
1442 }
1443
1444 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1445 {
1446         ulong cr0;
1447
1448         if (vcpu->fpu_active)
1449                 return;
1450         vcpu->fpu_active = 1;
1451         cr0 = vmcs_readl(GUEST_CR0);
1452         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1453         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1454         vmcs_writel(GUEST_CR0, cr0);
1455         update_exception_bitmap(vcpu);
1456         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1457         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1458 }
1459
1460 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1461
1462 /*
1463  * Return the cr0 value that a nested guest would read. This is a combination
1464  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1465  * its hypervisor (cr0_read_shadow).
1466  */
1467 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1468 {
1469         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1470                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1471 }
1472 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1473 {
1474         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1475                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1476 }
1477
1478 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1479 {
1480         vmx_decache_cr0_guest_bits(vcpu);
1481         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1482         update_exception_bitmap(vcpu);
1483         vcpu->arch.cr0_guest_owned_bits = 0;
1484         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1485         vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1486 }
1487
1488 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1489 {
1490         unsigned long rflags, save_rflags;
1491
1492         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1493                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1494                 rflags = vmcs_readl(GUEST_RFLAGS);
1495                 if (to_vmx(vcpu)->rmode.vm86_active) {
1496                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1497                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1498                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1499                 }
1500                 to_vmx(vcpu)->rflags = rflags;
1501         }
1502         return to_vmx(vcpu)->rflags;
1503 }
1504
1505 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1506 {
1507         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1508         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1509         to_vmx(vcpu)->rflags = rflags;
1510         if (to_vmx(vcpu)->rmode.vm86_active) {
1511                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1512                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1513         }
1514         vmcs_writel(GUEST_RFLAGS, rflags);
1515 }
1516
1517 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1518 {
1519         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1520         int ret = 0;
1521
1522         if (interruptibility & GUEST_INTR_STATE_STI)
1523                 ret |= KVM_X86_SHADOW_INT_STI;
1524         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1525                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1526
1527         return ret & mask;
1528 }
1529
1530 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1531 {
1532         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1533         u32 interruptibility = interruptibility_old;
1534
1535         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1536
1537         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1538                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1539         else if (mask & KVM_X86_SHADOW_INT_STI)
1540                 interruptibility |= GUEST_INTR_STATE_STI;
1541
1542         if ((interruptibility != interruptibility_old))
1543                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1544 }
1545
1546 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1547 {
1548         unsigned long rip;
1549
1550         rip = kvm_rip_read(vcpu);
1551         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1552         kvm_rip_write(vcpu, rip);
1553
1554         /* skipping an emulated instruction also counts */
1555         vmx_set_interrupt_shadow(vcpu, 0);
1556 }
1557
1558 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1559 {
1560         /* Ensure that we clear the HLT state in the VMCS.  We don't need to
1561          * explicitly skip the instruction because if the HLT state is set, then
1562          * the instruction is already executing and RIP has already been
1563          * advanced. */
1564         if (!yield_on_hlt &&
1565             vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1566                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1567 }
1568
1569 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1570                                 bool has_error_code, u32 error_code,
1571                                 bool reinject)
1572 {
1573         struct vcpu_vmx *vmx = to_vmx(vcpu);
1574         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1575
1576         if (has_error_code) {
1577                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1578                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1579         }
1580
1581         if (vmx->rmode.vm86_active) {
1582                 int inc_eip = 0;
1583                 if (kvm_exception_is_soft(nr))
1584                         inc_eip = vcpu->arch.event_exit_inst_len;
1585                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1586                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1587                 return;
1588         }
1589
1590         if (kvm_exception_is_soft(nr)) {
1591                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1592                              vmx->vcpu.arch.event_exit_inst_len);
1593                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1594         } else
1595                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1596
1597         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1598         vmx_clear_hlt(vcpu);
1599 }
1600
1601 static bool vmx_rdtscp_supported(void)
1602 {
1603         return cpu_has_vmx_rdtscp();
1604 }
1605
1606 /*
1607  * Swap MSR entry in host/guest MSR entry array.
1608  */
1609 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1610 {
1611         struct shared_msr_entry tmp;
1612
1613         tmp = vmx->guest_msrs[to];
1614         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1615         vmx->guest_msrs[from] = tmp;
1616 }
1617
1618 /*
1619  * Set up the vmcs to automatically save and restore system
1620  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1621  * mode, as fiddling with msrs is very expensive.
1622  */
1623 static void setup_msrs(struct vcpu_vmx *vmx)
1624 {
1625         int save_nmsrs, index;
1626         unsigned long *msr_bitmap;
1627
1628         vmx_load_host_state(vmx);
1629         save_nmsrs = 0;
1630 #ifdef CONFIG_X86_64
1631         if (is_long_mode(&vmx->vcpu)) {
1632                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1633                 if (index >= 0)
1634                         move_msr_up(vmx, index, save_nmsrs++);
1635                 index = __find_msr_index(vmx, MSR_LSTAR);
1636                 if (index >= 0)
1637                         move_msr_up(vmx, index, save_nmsrs++);
1638                 index = __find_msr_index(vmx, MSR_CSTAR);
1639                 if (index >= 0)
1640                         move_msr_up(vmx, index, save_nmsrs++);
1641                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1642                 if (index >= 0 && vmx->rdtscp_enabled)
1643                         move_msr_up(vmx, index, save_nmsrs++);
1644                 /*
1645                  * MSR_STAR is only needed on long mode guests, and only
1646                  * if efer.sce is enabled.
1647                  */
1648                 index = __find_msr_index(vmx, MSR_STAR);
1649                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1650                         move_msr_up(vmx, index, save_nmsrs++);
1651         }
1652 #endif
1653         index = __find_msr_index(vmx, MSR_EFER);
1654         if (index >= 0 && update_transition_efer(vmx, index))
1655                 move_msr_up(vmx, index, save_nmsrs++);
1656
1657         vmx->save_nmsrs = save_nmsrs;
1658
1659         if (cpu_has_vmx_msr_bitmap()) {
1660                 if (is_long_mode(&vmx->vcpu))
1661                         msr_bitmap = vmx_msr_bitmap_longmode;
1662                 else
1663                         msr_bitmap = vmx_msr_bitmap_legacy;
1664
1665                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1666         }
1667 }
1668
1669 /*
1670  * reads and returns guest's timestamp counter "register"
1671  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1672  */
1673 static u64 guest_read_tsc(void)
1674 {
1675         u64 host_tsc, tsc_offset;
1676
1677         rdtscll(host_tsc);
1678         tsc_offset = vmcs_read64(TSC_OFFSET);
1679         return host_tsc + tsc_offset;
1680 }
1681
1682 /*
1683  * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1684  * ioctl. In this case the call-back should update internal vmx state to make
1685  * the changes effective.
1686  */
1687 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1688 {
1689         /* Nothing to do here */
1690 }
1691
1692 /*
1693  * writes 'offset' into guest's timestamp counter offset register
1694  */
1695 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1696 {
1697         vmcs_write64(TSC_OFFSET, offset);
1698 }
1699
1700 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1701 {
1702         u64 offset = vmcs_read64(TSC_OFFSET);
1703         vmcs_write64(TSC_OFFSET, offset + adjustment);
1704 }
1705
1706 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1707 {
1708         return target_tsc - native_read_tsc();
1709 }
1710
1711 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1712 {
1713         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1714         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1715 }
1716
1717 /*
1718  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1719  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1720  * all guests if the "nested" module option is off, and can also be disabled
1721  * for a single guest by disabling its VMX cpuid bit.
1722  */
1723 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1724 {
1725         return nested && guest_cpuid_has_vmx(vcpu);
1726 }
1727
1728 /*
1729  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1730  * returned for the various VMX controls MSRs when nested VMX is enabled.
1731  * The same values should also be used to verify that vmcs12 control fields are
1732  * valid during nested entry from L1 to L2.
1733  * Each of these control msrs has a low and high 32-bit half: A low bit is on
1734  * if the corresponding bit in the (32-bit) control field *must* be on, and a
1735  * bit in the high half is on if the corresponding bit in the control field
1736  * may be on. See also vmx_control_verify().
1737  * TODO: allow these variables to be modified (downgraded) by module options
1738  * or other means.
1739  */
1740 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1741 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1742 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1743 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1744 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1745 static __init void nested_vmx_setup_ctls_msrs(void)
1746 {
1747         /*
1748          * Note that as a general rule, the high half of the MSRs (bits in
1749          * the control fields which may be 1) should be initialized by the
1750          * intersection of the underlying hardware's MSR (i.e., features which
1751          * can be supported) and the list of features we want to expose -
1752          * because they are known to be properly supported in our code.
1753          * Also, usually, the low half of the MSRs (bits which must be 1) can
1754          * be set to 0, meaning that L1 may turn off any of these bits. The
1755          * reason is that if one of these bits is necessary, it will appear
1756          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1757          * fields of vmcs01 and vmcs02, will turn these bits off - and
1758          * nested_vmx_exit_handled() will not pass related exits to L1.
1759          * These rules have exceptions below.
1760          */
1761
1762         /* pin-based controls */
1763         /*
1764          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1765          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1766          */
1767         nested_vmx_pinbased_ctls_low = 0x16 ;
1768         nested_vmx_pinbased_ctls_high = 0x16 |
1769                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1770                 PIN_BASED_VIRTUAL_NMIS;
1771
1772         /* exit controls */
1773         nested_vmx_exit_ctls_low = 0;
1774 #ifdef CONFIG_X86_64
1775         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1776 #else
1777         nested_vmx_exit_ctls_high = 0;
1778 #endif
1779
1780         /* entry controls */
1781         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1782                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1783         nested_vmx_entry_ctls_low = 0;
1784         nested_vmx_entry_ctls_high &=
1785                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1786
1787         /* cpu-based controls */
1788         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1789                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1790         nested_vmx_procbased_ctls_low = 0;
1791         nested_vmx_procbased_ctls_high &=
1792                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1793                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1794                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1795                 CPU_BASED_CR3_STORE_EXITING |
1796 #ifdef CONFIG_X86_64
1797                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1798 #endif
1799                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1800                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1801                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1802         /*
1803          * We can allow some features even when not supported by the
1804          * hardware. For example, L1 can specify an MSR bitmap - and we
1805          * can use it to avoid exits to L1 - even when L0 runs L2
1806          * without MSR bitmaps.
1807          */
1808         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1809
1810         /* secondary cpu-based controls */
1811         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1812                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1813         nested_vmx_secondary_ctls_low = 0;
1814         nested_vmx_secondary_ctls_high &=
1815                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1816 }
1817
1818 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1819 {
1820         /*
1821          * Bits 0 in high must be 0, and bits 1 in low must be 1.
1822          */
1823         return ((control & high) | low) == control;
1824 }
1825
1826 static inline u64 vmx_control_msr(u32 low, u32 high)
1827 {
1828         return low | ((u64)high << 32);
1829 }
1830
1831 /*
1832  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1833  * also let it use VMX-specific MSRs.
1834  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1835  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1836  * like all other MSRs).
1837  */
1838 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1839 {
1840         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1841                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
1842                 /*
1843                  * According to the spec, processors which do not support VMX
1844                  * should throw a #GP(0) when VMX capability MSRs are read.
1845                  */
1846                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
1847                 return 1;
1848         }
1849
1850         switch (msr_index) {
1851         case MSR_IA32_FEATURE_CONTROL:
1852                 *pdata = 0;
1853                 break;
1854         case MSR_IA32_VMX_BASIC:
1855                 /*
1856                  * This MSR reports some information about VMX support. We
1857                  * should return information about the VMX we emulate for the
1858                  * guest, and the VMCS structure we give it - not about the
1859                  * VMX support of the underlying hardware.
1860                  */
1861                 *pdata = VMCS12_REVISION |
1862                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
1863                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
1864                 break;
1865         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1866         case MSR_IA32_VMX_PINBASED_CTLS:
1867                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
1868                                         nested_vmx_pinbased_ctls_high);
1869                 break;
1870         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1871         case MSR_IA32_VMX_PROCBASED_CTLS:
1872                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
1873                                         nested_vmx_procbased_ctls_high);
1874                 break;
1875         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1876         case MSR_IA32_VMX_EXIT_CTLS:
1877                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
1878                                         nested_vmx_exit_ctls_high);
1879                 break;
1880         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1881         case MSR_IA32_VMX_ENTRY_CTLS:
1882                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
1883                                         nested_vmx_entry_ctls_high);
1884                 break;
1885         case MSR_IA32_VMX_MISC:
1886                 *pdata = 0;
1887                 break;
1888         /*
1889          * These MSRs specify bits which the guest must keep fixed (on or off)
1890          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
1891          * We picked the standard core2 setting.
1892          */
1893 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
1894 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
1895         case MSR_IA32_VMX_CR0_FIXED0:
1896                 *pdata = VMXON_CR0_ALWAYSON;
1897                 break;
1898         case MSR_IA32_VMX_CR0_FIXED1:
1899                 *pdata = -1ULL;
1900                 break;
1901         case MSR_IA32_VMX_CR4_FIXED0:
1902                 *pdata = VMXON_CR4_ALWAYSON;
1903                 break;
1904         case MSR_IA32_VMX_CR4_FIXED1:
1905                 *pdata = -1ULL;
1906                 break;
1907         case MSR_IA32_VMX_VMCS_ENUM:
1908                 *pdata = 0x1f;
1909                 break;
1910         case MSR_IA32_VMX_PROCBASED_CTLS2:
1911                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
1912                                         nested_vmx_secondary_ctls_high);
1913                 break;
1914         case MSR_IA32_VMX_EPT_VPID_CAP:
1915                 /* Currently, no nested ept or nested vpid */
1916                 *pdata = 0;
1917                 break;
1918         default:
1919                 return 0;
1920         }
1921
1922         return 1;
1923 }
1924
1925 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1926 {
1927         if (!nested_vmx_allowed(vcpu))
1928                 return 0;
1929
1930         if (msr_index == MSR_IA32_FEATURE_CONTROL)
1931                 /* TODO: the right thing. */
1932                 return 1;
1933         /*
1934          * No need to treat VMX capability MSRs specially: If we don't handle
1935          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
1936          */
1937         return 0;
1938 }
1939
1940 /*
1941  * Reads an msr value (of 'msr_index') into 'pdata'.
1942  * Returns 0 on success, non-0 otherwise.
1943  * Assumes vcpu_load() was already called.
1944  */
1945 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1946 {
1947         u64 data;
1948         struct shared_msr_entry *msr;
1949
1950         if (!pdata) {
1951                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1952                 return -EINVAL;
1953         }
1954
1955         switch (msr_index) {
1956 #ifdef CONFIG_X86_64
1957         case MSR_FS_BASE:
1958                 data = vmcs_readl(GUEST_FS_BASE);
1959                 break;
1960         case MSR_GS_BASE:
1961                 data = vmcs_readl(GUEST_GS_BASE);
1962                 break;
1963         case MSR_KERNEL_GS_BASE:
1964                 vmx_load_host_state(to_vmx(vcpu));
1965                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1966                 break;
1967 #endif
1968         case MSR_EFER:
1969                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1970         case MSR_IA32_TSC:
1971                 data = guest_read_tsc();
1972                 break;
1973         case MSR_IA32_SYSENTER_CS:
1974                 data = vmcs_read32(GUEST_SYSENTER_CS);
1975                 break;
1976         case MSR_IA32_SYSENTER_EIP:
1977                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1978                 break;
1979         case MSR_IA32_SYSENTER_ESP:
1980                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1981                 break;
1982         case MSR_TSC_AUX:
1983                 if (!to_vmx(vcpu)->rdtscp_enabled)
1984                         return 1;
1985                 /* Otherwise falls through */
1986         default:
1987                 vmx_load_host_state(to_vmx(vcpu));
1988                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
1989                         return 0;
1990                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1991                 if (msr) {
1992                         vmx_load_host_state(to_vmx(vcpu));
1993                         data = msr->data;
1994                         break;
1995                 }
1996                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1997         }
1998
1999         *pdata = data;
2000         return 0;
2001 }
2002
2003 /*
2004  * Writes msr value into into the appropriate "register".
2005  * Returns 0 on success, non-0 otherwise.
2006  * Assumes vcpu_load() was already called.
2007  */
2008 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2009 {
2010         struct vcpu_vmx *vmx = to_vmx(vcpu);
2011         struct shared_msr_entry *msr;
2012         int ret = 0;
2013
2014         switch (msr_index) {
2015         case MSR_EFER:
2016                 vmx_load_host_state(vmx);
2017                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2018                 break;
2019 #ifdef CONFIG_X86_64
2020         case MSR_FS_BASE:
2021                 vmx_segment_cache_clear(vmx);
2022                 vmcs_writel(GUEST_FS_BASE, data);
2023                 break;
2024         case MSR_GS_BASE:
2025                 vmx_segment_cache_clear(vmx);
2026                 vmcs_writel(GUEST_GS_BASE, data);
2027                 break;
2028         case MSR_KERNEL_GS_BASE:
2029                 vmx_load_host_state(vmx);
2030                 vmx->msr_guest_kernel_gs_base = data;
2031                 break;
2032 #endif
2033         case MSR_IA32_SYSENTER_CS:
2034                 vmcs_write32(GUEST_SYSENTER_CS, data);
2035                 break;
2036         case MSR_IA32_SYSENTER_EIP:
2037                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2038                 break;
2039         case MSR_IA32_SYSENTER_ESP:
2040                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2041                 break;
2042         case MSR_IA32_TSC:
2043                 kvm_write_tsc(vcpu, data);
2044                 break;
2045         case MSR_IA32_CR_PAT:
2046                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2047                         vmcs_write64(GUEST_IA32_PAT, data);
2048                         vcpu->arch.pat = data;
2049                         break;
2050                 }
2051                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2052                 break;
2053         case MSR_TSC_AUX:
2054                 if (!vmx->rdtscp_enabled)
2055                         return 1;
2056                 /* Check reserved bit, higher 32 bits should be zero */
2057                 if ((data >> 32) != 0)
2058                         return 1;
2059                 /* Otherwise falls through */
2060         default:
2061                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2062                         break;
2063                 msr = find_msr_entry(vmx, msr_index);
2064                 if (msr) {
2065                         vmx_load_host_state(vmx);
2066                         msr->data = data;
2067                         break;
2068                 }
2069                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2070         }
2071
2072         return ret;
2073 }
2074
2075 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2076 {
2077         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2078         switch (reg) {
2079         case VCPU_REGS_RSP:
2080                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2081                 break;
2082         case VCPU_REGS_RIP:
2083                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2084                 break;
2085         case VCPU_EXREG_PDPTR:
2086                 if (enable_ept)
2087                         ept_save_pdptrs(vcpu);
2088                 break;
2089         default:
2090                 break;
2091         }
2092 }
2093
2094 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2095 {
2096         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2097                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2098         else
2099                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2100
2101         update_exception_bitmap(vcpu);
2102 }
2103
2104 static __init int cpu_has_kvm_support(void)
2105 {
2106         return cpu_has_vmx();
2107 }
2108
2109 static __init int vmx_disabled_by_bios(void)
2110 {
2111         u64 msr;
2112
2113         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2114         if (msr & FEATURE_CONTROL_LOCKED) {
2115                 /* launched w/ TXT and VMX disabled */
2116                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2117                         && tboot_enabled())
2118                         return 1;
2119                 /* launched w/o TXT and VMX only enabled w/ TXT */
2120                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2121                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2122                         && !tboot_enabled()) {
2123                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2124                                 "activate TXT before enabling KVM\n");
2125                         return 1;
2126                 }
2127                 /* launched w/o TXT and VMX disabled */
2128                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2129                         && !tboot_enabled())
2130                         return 1;
2131         }
2132
2133         return 0;
2134 }
2135
2136 static void kvm_cpu_vmxon(u64 addr)
2137 {
2138         asm volatile (ASM_VMX_VMXON_RAX
2139                         : : "a"(&addr), "m"(addr)
2140                         : "memory", "cc");
2141 }
2142
2143 static int hardware_enable(void *garbage)
2144 {
2145         int cpu = raw_smp_processor_id();
2146         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2147         u64 old, test_bits;
2148
2149         if (read_cr4() & X86_CR4_VMXE)
2150                 return -EBUSY;
2151
2152         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2153         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2154
2155         test_bits = FEATURE_CONTROL_LOCKED;
2156         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2157         if (tboot_enabled())
2158                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2159
2160         if ((old & test_bits) != test_bits) {
2161                 /* enable and lock */
2162                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2163         }
2164         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2165
2166         if (vmm_exclusive) {
2167                 kvm_cpu_vmxon(phys_addr);
2168                 ept_sync_global();
2169         }
2170
2171         store_gdt(&__get_cpu_var(host_gdt));
2172
2173         return 0;
2174 }
2175
2176 static void vmclear_local_loaded_vmcss(void)
2177 {
2178         int cpu = raw_smp_processor_id();
2179         struct loaded_vmcs *v, *n;
2180
2181         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2182                                  loaded_vmcss_on_cpu_link)
2183                 __loaded_vmcs_clear(v);
2184 }
2185
2186
2187 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2188  * tricks.
2189  */
2190 static void kvm_cpu_vmxoff(void)
2191 {
2192         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2193 }
2194
2195 static void hardware_disable(void *garbage)
2196 {
2197         if (vmm_exclusive) {
2198                 vmclear_local_loaded_vmcss();
2199                 kvm_cpu_vmxoff();
2200         }
2201         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2202 }
2203
2204 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2205                                       u32 msr, u32 *result)
2206 {
2207         u32 vmx_msr_low, vmx_msr_high;
2208         u32 ctl = ctl_min | ctl_opt;
2209
2210         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2211
2212         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2213         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2214
2215         /* Ensure minimum (required) set of control bits are supported. */
2216         if (ctl_min & ~ctl)
2217                 return -EIO;
2218
2219         *result = ctl;
2220         return 0;
2221 }
2222
2223 static __init bool allow_1_setting(u32 msr, u32 ctl)
2224 {
2225         u32 vmx_msr_low, vmx_msr_high;
2226
2227         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2228         return vmx_msr_high & ctl;
2229 }
2230
2231 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2232 {
2233         u32 vmx_msr_low, vmx_msr_high;
2234         u32 min, opt, min2, opt2;
2235         u32 _pin_based_exec_control = 0;
2236         u32 _cpu_based_exec_control = 0;
2237         u32 _cpu_based_2nd_exec_control = 0;
2238         u32 _vmexit_control = 0;
2239         u32 _vmentry_control = 0;
2240
2241         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2242         opt = PIN_BASED_VIRTUAL_NMIS;
2243         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2244                                 &_pin_based_exec_control) < 0)
2245                 return -EIO;
2246
2247         min =
2248 #ifdef CONFIG_X86_64
2249               CPU_BASED_CR8_LOAD_EXITING |
2250               CPU_BASED_CR8_STORE_EXITING |
2251 #endif
2252               CPU_BASED_CR3_LOAD_EXITING |
2253               CPU_BASED_CR3_STORE_EXITING |
2254               CPU_BASED_USE_IO_BITMAPS |
2255               CPU_BASED_MOV_DR_EXITING |
2256               CPU_BASED_USE_TSC_OFFSETING |
2257               CPU_BASED_MWAIT_EXITING |
2258               CPU_BASED_MONITOR_EXITING |
2259               CPU_BASED_INVLPG_EXITING;
2260
2261         if (yield_on_hlt)
2262                 min |= CPU_BASED_HLT_EXITING;
2263
2264         opt = CPU_BASED_TPR_SHADOW |
2265               CPU_BASED_USE_MSR_BITMAPS |
2266               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2267         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2268                                 &_cpu_based_exec_control) < 0)
2269                 return -EIO;
2270 #ifdef CONFIG_X86_64
2271         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2272                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2273                                            ~CPU_BASED_CR8_STORE_EXITING;
2274 #endif
2275         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2276                 min2 = 0;
2277                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2278                         SECONDARY_EXEC_WBINVD_EXITING |
2279                         SECONDARY_EXEC_ENABLE_VPID |
2280                         SECONDARY_EXEC_ENABLE_EPT |
2281                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2282                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2283                         SECONDARY_EXEC_RDTSCP;
2284                 if (adjust_vmx_controls(min2, opt2,
2285                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2286                                         &_cpu_based_2nd_exec_control) < 0)
2287                         return -EIO;
2288         }
2289 #ifndef CONFIG_X86_64
2290         if (!(_cpu_based_2nd_exec_control &
2291                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2292                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2293 #endif
2294         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2295                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2296                    enabled */
2297                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2298                                              CPU_BASED_CR3_STORE_EXITING |
2299                                              CPU_BASED_INVLPG_EXITING);
2300                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2301                       vmx_capability.ept, vmx_capability.vpid);
2302         }
2303
2304         min = 0;
2305 #ifdef CONFIG_X86_64
2306         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2307 #endif
2308         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2309         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2310                                 &_vmexit_control) < 0)
2311                 return -EIO;
2312
2313         min = 0;
2314         opt = VM_ENTRY_LOAD_IA32_PAT;
2315         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2316                                 &_vmentry_control) < 0)
2317                 return -EIO;
2318
2319         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2320
2321         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2322         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2323                 return -EIO;
2324
2325 #ifdef CONFIG_X86_64
2326         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2327         if (vmx_msr_high & (1u<<16))
2328                 return -EIO;
2329 #endif
2330
2331         /* Require Write-Back (WB) memory type for VMCS accesses. */
2332         if (((vmx_msr_high >> 18) & 15) != 6)
2333                 return -EIO;
2334
2335         vmcs_conf->size = vmx_msr_high & 0x1fff;
2336         vmcs_conf->order = get_order(vmcs_config.size);
2337         vmcs_conf->revision_id = vmx_msr_low;
2338
2339         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2340         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2341         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2342         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2343         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2344
2345         cpu_has_load_ia32_efer =
2346                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2347                                 VM_ENTRY_LOAD_IA32_EFER)
2348                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2349                                    VM_EXIT_LOAD_IA32_EFER);
2350
2351         return 0;
2352 }
2353
2354 static struct vmcs *alloc_vmcs_cpu(int cpu)
2355 {
2356         int node = cpu_to_node(cpu);
2357         struct page *pages;
2358         struct vmcs *vmcs;
2359
2360         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2361         if (!pages)
2362                 return NULL;
2363         vmcs = page_address(pages);
2364         memset(vmcs, 0, vmcs_config.size);
2365         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2366         return vmcs;
2367 }
2368
2369 static struct vmcs *alloc_vmcs(void)
2370 {
2371         return alloc_vmcs_cpu(raw_smp_processor_id());
2372 }
2373
2374 static void free_vmcs(struct vmcs *vmcs)
2375 {
2376         free_pages((unsigned long)vmcs, vmcs_config.order);
2377 }
2378
2379 /*
2380  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2381  */
2382 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2383 {
2384         if (!loaded_vmcs->vmcs)
2385                 return;
2386         loaded_vmcs_clear(loaded_vmcs);
2387         free_vmcs(loaded_vmcs->vmcs);
2388         loaded_vmcs->vmcs = NULL;
2389 }
2390
2391 static void free_kvm_area(void)
2392 {
2393         int cpu;
2394
2395         for_each_possible_cpu(cpu) {
2396                 free_vmcs(per_cpu(vmxarea, cpu));
2397                 per_cpu(vmxarea, cpu) = NULL;
2398         }
2399 }
2400
2401 static __init int alloc_kvm_area(void)
2402 {
2403         int cpu;
2404
2405         for_each_possible_cpu(cpu) {
2406                 struct vmcs *vmcs;
2407
2408                 vmcs = alloc_vmcs_cpu(cpu);
2409                 if (!vmcs) {
2410                         free_kvm_area();
2411                         return -ENOMEM;
2412                 }
2413
2414                 per_cpu(vmxarea, cpu) = vmcs;
2415         }
2416         return 0;
2417 }
2418
2419 static __init int hardware_setup(void)
2420 {
2421         if (setup_vmcs_config(&vmcs_config) < 0)
2422                 return -EIO;
2423
2424         if (boot_cpu_has(X86_FEATURE_NX))
2425                 kvm_enable_efer_bits(EFER_NX);
2426
2427         if (!cpu_has_vmx_vpid())
2428                 enable_vpid = 0;
2429
2430         if (!cpu_has_vmx_ept() ||
2431             !cpu_has_vmx_ept_4levels()) {
2432                 enable_ept = 0;
2433                 enable_unrestricted_guest = 0;
2434         }
2435
2436         if (!cpu_has_vmx_unrestricted_guest())
2437                 enable_unrestricted_guest = 0;
2438
2439         if (!cpu_has_vmx_flexpriority())
2440                 flexpriority_enabled = 0;
2441
2442         if (!cpu_has_vmx_tpr_shadow())
2443                 kvm_x86_ops->update_cr8_intercept = NULL;
2444
2445         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2446                 kvm_disable_largepages();
2447
2448         if (!cpu_has_vmx_ple())
2449                 ple_gap = 0;
2450
2451         if (nested)
2452                 nested_vmx_setup_ctls_msrs();
2453
2454         return alloc_kvm_area();
2455 }
2456
2457 static __exit void hardware_unsetup(void)
2458 {
2459         free_kvm_area();
2460 }
2461
2462 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2463 {
2464         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2465
2466         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2467                 vmcs_write16(sf->selector, save->selector);
2468                 vmcs_writel(sf->base, save->base);
2469                 vmcs_write32(sf->limit, save->limit);
2470                 vmcs_write32(sf->ar_bytes, save->ar);
2471         } else {
2472                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2473                         << AR_DPL_SHIFT;
2474                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2475         }
2476 }
2477
2478 static void enter_pmode(struct kvm_vcpu *vcpu)
2479 {
2480         unsigned long flags;
2481         struct vcpu_vmx *vmx = to_vmx(vcpu);
2482
2483         vmx->emulation_required = 1;
2484         vmx->rmode.vm86_active = 0;
2485
2486         vmx_segment_cache_clear(vmx);
2487
2488         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2489         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2490         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2491         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2492
2493         flags = vmcs_readl(GUEST_RFLAGS);
2494         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2495         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2496         vmcs_writel(GUEST_RFLAGS, flags);
2497
2498         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2499                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2500
2501         update_exception_bitmap(vcpu);
2502
2503         if (emulate_invalid_guest_state)
2504                 return;
2505
2506         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2507         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2508         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2509         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2510
2511         vmx_segment_cache_clear(vmx);
2512
2513         vmcs_write16(GUEST_SS_SELECTOR, 0);
2514         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2515
2516         vmcs_write16(GUEST_CS_SELECTOR,
2517                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2518         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2519 }
2520
2521 static gva_t rmode_tss_base(struct kvm *kvm)
2522 {
2523         if (!kvm->arch.tss_addr) {
2524                 struct kvm_memslots *slots;
2525                 gfn_t base_gfn;
2526
2527                 slots = kvm_memslots(kvm);
2528                 base_gfn = slots->memslots[0].base_gfn +
2529                                  kvm->memslots->memslots[0].npages - 3;
2530                 return base_gfn << PAGE_SHIFT;
2531         }
2532         return kvm->arch.tss_addr;
2533 }
2534
2535 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2536 {
2537         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2538
2539         save->selector = vmcs_read16(sf->selector);
2540         save->base = vmcs_readl(sf->base);
2541         save->limit = vmcs_read32(sf->limit);
2542         save->ar = vmcs_read32(sf->ar_bytes);
2543         vmcs_write16(sf->selector, save->base >> 4);
2544         vmcs_write32(sf->base, save->base & 0xffff0);
2545         vmcs_write32(sf->limit, 0xffff);
2546         vmcs_write32(sf->ar_bytes, 0xf3);
2547         if (save->base & 0xf)
2548                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2549                             " aligned when entering protected mode (seg=%d)",
2550                             seg);
2551 }
2552
2553 static void enter_rmode(struct kvm_vcpu *vcpu)
2554 {
2555         unsigned long flags;
2556         struct vcpu_vmx *vmx = to_vmx(vcpu);
2557
2558         if (enable_unrestricted_guest)
2559                 return;
2560
2561         vmx->emulation_required = 1;
2562         vmx->rmode.vm86_active = 1;
2563
2564         /*
2565          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2566          * vcpu. Call it here with phys address pointing 16M below 4G.
2567          */
2568         if (!vcpu->kvm->arch.tss_addr) {
2569                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2570                              "called before entering vcpu\n");
2571                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2572                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2573                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2574         }
2575
2576         vmx_segment_cache_clear(vmx);
2577
2578         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2579         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2580         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2581
2582         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2583         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2584
2585         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2586         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2587
2588         flags = vmcs_readl(GUEST_RFLAGS);
2589         vmx->rmode.save_rflags = flags;
2590
2591         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2592
2593         vmcs_writel(GUEST_RFLAGS, flags);
2594         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2595         update_exception_bitmap(vcpu);
2596
2597         if (emulate_invalid_guest_state)
2598                 goto continue_rmode;
2599
2600         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2601         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2602         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2603
2604         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
2605         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2606         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2607                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
2608         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2609
2610         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2611         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2612         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2613         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
2614
2615 continue_rmode:
2616         kvm_mmu_reset_context(vcpu);
2617 }
2618
2619 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2620 {
2621         struct vcpu_vmx *vmx = to_vmx(vcpu);
2622         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2623
2624         if (!msr)
2625                 return;
2626
2627         /*
2628          * Force kernel_gs_base reloading before EFER changes, as control
2629          * of this msr depends on is_long_mode().
2630          */
2631         vmx_load_host_state(to_vmx(vcpu));
2632         vcpu->arch.efer = efer;
2633         if (efer & EFER_LMA) {
2634                 vmcs_write32(VM_ENTRY_CONTROLS,
2635                              vmcs_read32(VM_ENTRY_CONTROLS) |
2636                              VM_ENTRY_IA32E_MODE);
2637                 msr->data = efer;
2638         } else {
2639                 vmcs_write32(VM_ENTRY_CONTROLS,
2640                              vmcs_read32(VM_ENTRY_CONTROLS) &
2641                              ~VM_ENTRY_IA32E_MODE);
2642
2643                 msr->data = efer & ~EFER_LME;
2644         }
2645         setup_msrs(vmx);
2646 }
2647
2648 #ifdef CONFIG_X86_64
2649
2650 static void enter_lmode(struct kvm_vcpu *vcpu)
2651 {
2652         u32 guest_tr_ar;
2653
2654         vmx_segment_cache_clear(to_vmx(vcpu));
2655
2656         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2657         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2658                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
2659                        __func__);
2660                 vmcs_write32(GUEST_TR_AR_BYTES,
2661                              (guest_tr_ar & ~AR_TYPE_MASK)
2662                              | AR_TYPE_BUSY_64_TSS);
2663         }
2664         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2665 }
2666
2667 static void exit_lmode(struct kvm_vcpu *vcpu)
2668 {
2669         vmcs_write32(VM_ENTRY_CONTROLS,
2670                      vmcs_read32(VM_ENTRY_CONTROLS)
2671                      & ~VM_ENTRY_IA32E_MODE);
2672         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2673 }
2674
2675 #endif
2676
2677 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2678 {
2679         vpid_sync_context(to_vmx(vcpu));
2680         if (enable_ept) {
2681                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2682                         return;
2683                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2684         }
2685 }
2686
2687 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2688 {
2689         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2690
2691         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2692         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2693 }
2694
2695 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2696 {
2697         if (enable_ept && is_paging(vcpu))
2698                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2699         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2700 }
2701
2702 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2703 {
2704         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2705
2706         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2707         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2708 }
2709
2710 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2711 {
2712         if (!test_bit(VCPU_EXREG_PDPTR,
2713                       (unsigned long *)&vcpu->arch.regs_dirty))
2714                 return;
2715
2716         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2717                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2718                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2719                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2720                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2721         }
2722 }
2723
2724 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2725 {
2726         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2727                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2728                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2729                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2730                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2731         }
2732
2733         __set_bit(VCPU_EXREG_PDPTR,
2734                   (unsigned long *)&vcpu->arch.regs_avail);
2735         __set_bit(VCPU_EXREG_PDPTR,
2736                   (unsigned long *)&vcpu->arch.regs_dirty);
2737 }
2738
2739 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2740
2741 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2742                                         unsigned long cr0,
2743                                         struct kvm_vcpu *vcpu)
2744 {
2745         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2746                 vmx_decache_cr3(vcpu);
2747         if (!(cr0 & X86_CR0_PG)) {
2748                 /* From paging/starting to nonpaging */
2749                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2750                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2751                              (CPU_BASED_CR3_LOAD_EXITING |
2752                               CPU_BASED_CR3_STORE_EXITING));
2753                 vcpu->arch.cr0 = cr0;
2754                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2755         } else if (!is_paging(vcpu)) {
2756                 /* From nonpaging to paging */
2757                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2758                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2759                              ~(CPU_BASED_CR3_LOAD_EXITING |
2760                                CPU_BASED_CR3_STORE_EXITING));
2761                 vcpu->arch.cr0 = cr0;
2762                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2763         }
2764
2765         if (!(cr0 & X86_CR0_WP))
2766                 *hw_cr0 &= ~X86_CR0_WP;
2767 }
2768
2769 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2770 {
2771         struct vcpu_vmx *vmx = to_vmx(vcpu);
2772         unsigned long hw_cr0;
2773
2774         if (enable_unrestricted_guest)
2775                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2776                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2777         else
2778                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2779
2780         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2781                 enter_pmode(vcpu);
2782
2783         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2784                 enter_rmode(vcpu);
2785
2786 #ifdef CONFIG_X86_64
2787         if (vcpu->arch.efer & EFER_LME) {
2788                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2789                         enter_lmode(vcpu);
2790                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2791                         exit_lmode(vcpu);
2792         }
2793 #endif
2794
2795         if (enable_ept)
2796                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2797
2798         if (!vcpu->fpu_active)
2799                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2800
2801         vmcs_writel(CR0_READ_SHADOW, cr0);
2802         vmcs_writel(GUEST_CR0, hw_cr0);
2803         vcpu->arch.cr0 = cr0;
2804         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2805 }
2806
2807 static u64 construct_eptp(unsigned long root_hpa)
2808 {
2809         u64 eptp;
2810
2811         /* TODO write the value reading from MSR */
2812         eptp = VMX_EPT_DEFAULT_MT |
2813                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2814         eptp |= (root_hpa & PAGE_MASK);
2815
2816         return eptp;
2817 }
2818
2819 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2820 {
2821         unsigned long guest_cr3;
2822         u64 eptp;
2823
2824         guest_cr3 = cr3;
2825         if (enable_ept) {
2826                 eptp = construct_eptp(cr3);
2827                 vmcs_write64(EPT_POINTER, eptp);
2828                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
2829                         vcpu->kvm->arch.ept_identity_map_addr;
2830                 ept_load_pdptrs(vcpu);
2831         }
2832
2833         vmx_flush_tlb(vcpu);
2834         vmcs_writel(GUEST_CR3, guest_cr3);
2835 }
2836
2837 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2838 {
2839         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
2840                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2841
2842         if (cr4 & X86_CR4_VMXE) {
2843                 /*
2844                  * To use VMXON (and later other VMX instructions), a guest
2845                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
2846                  * So basically the check on whether to allow nested VMX
2847                  * is here.
2848                  */
2849                 if (!nested_vmx_allowed(vcpu))
2850                         return 1;
2851         } else if (to_vmx(vcpu)->nested.vmxon)
2852                 return 1;
2853
2854         vcpu->arch.cr4 = cr4;
2855         if (enable_ept) {
2856                 if (!is_paging(vcpu)) {
2857                         hw_cr4 &= ~X86_CR4_PAE;
2858                         hw_cr4 |= X86_CR4_PSE;
2859                 } else if (!(cr4 & X86_CR4_PAE)) {
2860                         hw_cr4 &= ~X86_CR4_PAE;
2861                 }
2862         }
2863
2864         vmcs_writel(CR4_READ_SHADOW, cr4);
2865         vmcs_writel(GUEST_CR4, hw_cr4);
2866         return 0;
2867 }
2868
2869 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2870                             struct kvm_segment *var, int seg)
2871 {
2872         struct vcpu_vmx *vmx = to_vmx(vcpu);
2873         struct kvm_save_segment *save;
2874         u32 ar;
2875
2876         if (vmx->rmode.vm86_active
2877             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2878                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2879                 || seg == VCPU_SREG_GS)
2880             && !emulate_invalid_guest_state) {
2881                 switch (seg) {
2882                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2883                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2884                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2885                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2886                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2887                 default: BUG();
2888                 }
2889                 var->selector = save->selector;
2890                 var->base = save->base;
2891                 var->limit = save->limit;
2892                 ar = save->ar;
2893                 if (seg == VCPU_SREG_TR
2894                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
2895                         goto use_saved_rmode_seg;
2896         }
2897         var->base = vmx_read_guest_seg_base(vmx, seg);
2898         var->limit = vmx_read_guest_seg_limit(vmx, seg);
2899         var->selector = vmx_read_guest_seg_selector(vmx, seg);
2900         ar = vmx_read_guest_seg_ar(vmx, seg);
2901 use_saved_rmode_seg:
2902         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2903                 ar = 0;
2904         var->type = ar & 15;
2905         var->s = (ar >> 4) & 1;
2906         var->dpl = (ar >> 5) & 3;
2907         var->present = (ar >> 7) & 1;
2908         var->avl = (ar >> 12) & 1;
2909         var->l = (ar >> 13) & 1;
2910         var->db = (ar >> 14) & 1;
2911         var->g = (ar >> 15) & 1;
2912         var->unusable = (ar >> 16) & 1;
2913 }
2914
2915 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2916 {
2917         struct kvm_segment s;
2918
2919         if (to_vmx(vcpu)->rmode.vm86_active) {
2920                 vmx_get_segment(vcpu, &s, seg);
2921                 return s.base;
2922         }
2923         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
2924 }
2925
2926 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2927 {
2928         if (!is_protmode(vcpu))
2929                 return 0;
2930
2931         if (!is_long_mode(vcpu)
2932             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2933                 return 3;
2934
2935         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2936 }
2937
2938 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2939 {
2940         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
2941                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2942                 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
2943         }
2944         return to_vmx(vcpu)->cpl;
2945 }
2946
2947
2948 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2949 {
2950         u32 ar;
2951
2952         if (var->unusable)
2953                 ar = 1 << 16;
2954         else {
2955                 ar = var->type & 15;
2956                 ar |= (var->s & 1) << 4;
2957                 ar |= (var->dpl & 3) << 5;
2958                 ar |= (var->present & 1) << 7;
2959                 ar |= (var->avl & 1) << 12;
2960                 ar |= (var->l & 1) << 13;
2961                 ar |= (var->db & 1) << 14;
2962                 ar |= (var->g & 1) << 15;
2963         }
2964         if (ar == 0) /* a 0 value means unusable */
2965                 ar = AR_UNUSABLE_MASK;
2966
2967         return ar;
2968 }
2969
2970 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2971                             struct kvm_segment *var, int seg)
2972 {
2973         struct vcpu_vmx *vmx = to_vmx(vcpu);
2974         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2975         u32 ar;
2976
2977         vmx_segment_cache_clear(vmx);
2978
2979         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2980                 vmcs_write16(sf->selector, var->selector);
2981                 vmx->rmode.tr.selector = var->selector;
2982                 vmx->rmode.tr.base = var->base;
2983                 vmx->rmode.tr.limit = var->limit;
2984                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2985                 return;
2986         }
2987         vmcs_writel(sf->base, var->base);
2988         vmcs_write32(sf->limit, var->limit);
2989         vmcs_write16(sf->selector, var->selector);
2990         if (vmx->rmode.vm86_active && var->s) {
2991                 /*
2992                  * Hack real-mode segments into vm86 compatibility.
2993                  */
2994                 if (var->base == 0xffff0000 && var->selector == 0xf000)
2995                         vmcs_writel(sf->base, 0xf0000);
2996                 ar = 0xf3;
2997         } else
2998                 ar = vmx_segment_access_rights(var);
2999
3000         /*
3001          *   Fix the "Accessed" bit in AR field of segment registers for older
3002          * qemu binaries.
3003          *   IA32 arch specifies that at the time of processor reset the
3004          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3005          * is setting it to 0 in the usedland code. This causes invalid guest
3006          * state vmexit when "unrestricted guest" mode is turned on.
3007          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3008          * tree. Newer qemu binaries with that qemu fix would not need this
3009          * kvm hack.
3010          */
3011         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3012                 ar |= 0x1; /* Accessed */
3013
3014         vmcs_write32(sf->ar_bytes, ar);
3015         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3016 }
3017
3018 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3019 {
3020         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3021
3022         *db = (ar >> 14) & 1;
3023         *l = (ar >> 13) & 1;
3024 }
3025
3026 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3027 {
3028         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3029         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3030 }
3031
3032 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3033 {
3034         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3035         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3036 }
3037
3038 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3039 {
3040         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3041         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3042 }
3043
3044 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3045 {
3046         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3047         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3048 }
3049
3050 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3051 {
3052         struct kvm_segment var;
3053         u32 ar;
3054
3055         vmx_get_segment(vcpu, &var, seg);
3056         ar = vmx_segment_access_rights(&var);
3057
3058         if (var.base != (var.selector << 4))
3059                 return false;
3060         if (var.limit != 0xffff)
3061                 return false;
3062         if (ar != 0xf3)
3063                 return false;
3064
3065         return true;
3066 }
3067
3068 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3069 {
3070         struct kvm_segment cs;
3071         unsigned int cs_rpl;
3072
3073         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3074         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3075
3076         if (cs.unusable)
3077                 return false;
3078         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3079                 return false;
3080         if (!cs.s)
3081                 return false;
3082         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3083                 if (cs.dpl > cs_rpl)
3084                         return false;
3085         } else {
3086                 if (cs.dpl != cs_rpl)
3087                         return false;
3088         }
3089         if (!cs.present)
3090                 return false;
3091
3092         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3093         return true;
3094 }
3095
3096 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3097 {
3098         struct kvm_segment ss;
3099         unsigned int ss_rpl;
3100
3101         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3102         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3103
3104         if (ss.unusable)
3105                 return true;
3106         if (ss.type != 3 && ss.type != 7)
3107                 return false;
3108         if (!ss.s)
3109                 return false;
3110         if (ss.dpl != ss_rpl) /* DPL != RPL */
3111                 return false;
3112         if (!ss.present)
3113                 return false;
3114
3115         return true;
3116 }
3117
3118 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3119 {
3120         struct kvm_segment var;
3121         unsigned int rpl;
3122
3123         vmx_get_segment(vcpu, &var, seg);
3124         rpl = var.selector & SELECTOR_RPL_MASK;
3125
3126         if (var.unusable)
3127                 return true;
3128         if (!var.s)
3129                 return false;
3130         if (!var.present)
3131                 return false;
3132         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3133                 if (var.dpl < rpl) /* DPL < RPL */
3134                         return false;
3135         }
3136
3137         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3138          * rights flags
3139          */
3140         return true;
3141 }
3142
3143 static bool tr_valid(struct kvm_vcpu *vcpu)
3144 {
3145         struct kvm_segment tr;
3146
3147         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3148
3149         if (tr.unusable)
3150                 return false;
3151         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3152                 return false;
3153         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3154                 return false;
3155         if (!tr.present)
3156                 return false;
3157
3158         return true;
3159 }
3160
3161 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3162 {
3163         struct kvm_segment ldtr;
3164
3165         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3166
3167         if (ldtr.unusable)
3168                 return true;
3169         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3170                 return false;
3171         if (ldtr.type != 2)
3172                 return false;
3173         if (!ldtr.present)
3174                 return false;
3175
3176         return true;
3177 }
3178
3179 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3180 {
3181         struct kvm_segment cs, ss;
3182
3183         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3184         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3185
3186         return ((cs.selector & SELECTOR_RPL_MASK) ==
3187                  (ss.selector & SELECTOR_RPL_MASK));
3188 }
3189
3190 /*
3191  * Check if guest state is valid. Returns true if valid, false if
3192  * not.
3193  * We assume that registers are always usable
3194  */
3195 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3196 {
3197         /* real mode guest state checks */
3198         if (!is_protmode(vcpu)) {
3199                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3200                         return false;
3201                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3202                         return false;
3203                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3204                         return false;
3205                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3206                         return false;
3207                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3208                         return false;
3209                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3210                         return false;
3211         } else {
3212         /* protected mode guest state checks */
3213                 if (!cs_ss_rpl_check(vcpu))
3214                         return false;
3215                 if (!code_segment_valid(vcpu))
3216                         return false;
3217                 if (!stack_segment_valid(vcpu))
3218                         return false;
3219                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3220                         return false;
3221                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3222                         return false;
3223                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3224                         return false;
3225                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3226                         return false;
3227                 if (!tr_valid(vcpu))
3228                         return false;
3229                 if (!ldtr_valid(vcpu))
3230                         return false;
3231         }
3232         /* TODO:
3233          * - Add checks on RIP
3234          * - Add checks on RFLAGS
3235          */
3236
3237         return true;
3238 }
3239
3240 static int init_rmode_tss(struct kvm *kvm)
3241 {
3242         gfn_t fn;
3243         u16 data = 0;
3244         int r, idx, ret = 0;
3245
3246         idx = srcu_read_lock(&kvm->srcu);
3247         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3248         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3249         if (r < 0)
3250                 goto out;
3251         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3252         r = kvm_write_guest_page(kvm, fn++, &data,
3253                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3254         if (r < 0)
3255                 goto out;
3256         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3257         if (r < 0)
3258                 goto out;
3259         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3260         if (r < 0)
3261                 goto out;
3262         data = ~0;
3263         r = kvm_write_guest_page(kvm, fn, &data,
3264                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3265                                  sizeof(u8));
3266         if (r < 0)
3267                 goto out;
3268
3269         ret = 1;
3270 out:
3271         srcu_read_unlock(&kvm->srcu, idx);
3272         return ret;
3273 }
3274
3275 static int init_rmode_identity_map(struct kvm *kvm)
3276 {
3277         int i, idx, r, ret;
3278         pfn_t identity_map_pfn;
3279         u32 tmp;
3280
3281         if (!enable_ept)
3282                 return 1;
3283         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3284                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3285                         "haven't been allocated!\n");
3286                 return 0;
3287         }
3288         if (likely(kvm->arch.ept_identity_pagetable_done))
3289                 return 1;
3290         ret = 0;
3291         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3292         idx = srcu_read_lock(&kvm->srcu);
3293         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3294         if (r < 0)
3295                 goto out;
3296         /* Set up identity-mapping pagetable for EPT in real mode */
3297         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3298                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3299                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3300                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3301                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3302                 if (r < 0)
3303                         goto out;
3304         }
3305         kvm->arch.ept_identity_pagetable_done = true;
3306         ret = 1;
3307 out:
3308         srcu_read_unlock(&kvm->srcu, idx);
3309         return ret;
3310 }
3311
3312 static void seg_setup(int seg)
3313 {
3314         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3315         unsigned int ar;
3316
3317         vmcs_write16(sf->selector, 0);
3318         vmcs_writel(sf->base, 0);
3319         vmcs_write32(sf->limit, 0xffff);
3320         if (enable_unrestricted_guest) {
3321                 ar = 0x93;
3322                 if (seg == VCPU_SREG_CS)
3323                         ar |= 0x08; /* code segment */
3324         } else
3325                 ar = 0xf3;
3326
3327         vmcs_write32(sf->ar_bytes, ar);
3328 }
3329
3330 static int alloc_apic_access_page(struct kvm *kvm)
3331 {
3332         struct kvm_userspace_memory_region kvm_userspace_mem;
3333         int r = 0;
3334
3335         mutex_lock(&kvm->slots_lock);
3336         if (kvm->arch.apic_access_page)
3337                 goto out;
3338         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3339         kvm_userspace_mem.flags = 0;
3340         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3341         kvm_userspace_mem.memory_size = PAGE_SIZE;
3342         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3343         if (r)
3344                 goto out;
3345
3346         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3347 out:
3348         mutex_unlock(&kvm->slots_lock);
3349         return r;
3350 }
3351
3352 static int alloc_identity_pagetable(struct kvm *kvm)
3353 {
3354         struct kvm_userspace_memory_region kvm_userspace_mem;
3355         int r = 0;
3356
3357         mutex_lock(&kvm->slots_lock);
3358         if (kvm->arch.ept_identity_pagetable)
3359                 goto out;
3360         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3361         kvm_userspace_mem.flags = 0;
3362         kvm_userspace_mem.guest_phys_addr =
3363                 kvm->arch.ept_identity_map_addr;
3364         kvm_userspace_mem.memory_size = PAGE_SIZE;
3365         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3366         if (r)
3367                 goto out;
3368
3369         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3370                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3371 out:
3372         mutex_unlock(&kvm->slots_lock);
3373         return r;
3374 }
3375
3376 static void allocate_vpid(struct vcpu_vmx *vmx)
3377 {
3378         int vpid;
3379
3380         vmx->vpid = 0;
3381         if (!enable_vpid)
3382                 return;
3383         spin_lock(&vmx_vpid_lock);
3384         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3385         if (vpid < VMX_NR_VPIDS) {
3386                 vmx->vpid = vpid;
3387                 __set_bit(vpid, vmx_vpid_bitmap);
3388         }
3389         spin_unlock(&vmx_vpid_lock);
3390 }
3391
3392 static void free_vpid(struct vcpu_vmx *vmx)
3393 {
3394         if (!enable_vpid)
3395                 return;
3396         spin_lock(&vmx_vpid_lock);
3397         if (vmx->vpid != 0)
3398                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3399         spin_unlock(&vmx_vpid_lock);
3400 }
3401
3402 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3403 {
3404         int f = sizeof(unsigned long);
3405
3406         if (!cpu_has_vmx_msr_bitmap())
3407                 return;
3408
3409         /*
3410          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3411          * have the write-low and read-high bitmap offsets the wrong way round.
3412          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3413          */
3414         if (msr <= 0x1fff) {
3415                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3416                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3417         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3418                 msr &= 0x1fff;
3419                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3420                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3421         }
3422 }
3423
3424 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3425 {
3426         if (!longmode_only)
3427                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3428         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3429 }
3430
3431 /*
3432  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3433  * will not change in the lifetime of the guest.
3434  * Note that host-state that does change is set elsewhere. E.g., host-state
3435  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3436  */
3437 static void vmx_set_constant_host_state(void)
3438 {
3439         u32 low32, high32;
3440         unsigned long tmpl;
3441         struct desc_ptr dt;
3442
3443         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
3444         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
3445         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
3446
3447         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3448         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3449         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3450         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3451         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3452
3453         native_store_idt(&dt);
3454         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3455
3456         asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3457         vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3458
3459         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3460         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3461         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3462         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3463
3464         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3465                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3466                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3467         }
3468 }
3469
3470 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3471 {
3472         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3473         if (enable_ept)
3474                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3475         if (is_guest_mode(&vmx->vcpu))
3476                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3477                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3478         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3479 }
3480
3481 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3482 {
3483         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3484         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3485                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3486 #ifdef CONFIG_X86_64
3487                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3488                                 CPU_BASED_CR8_LOAD_EXITING;
3489 #endif
3490         }
3491         if (!enable_ept)
3492                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3493                                 CPU_BASED_CR3_LOAD_EXITING  |
3494                                 CPU_BASED_INVLPG_EXITING;
3495         return exec_control;
3496 }
3497
3498 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3499 {
3500         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3501         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3502                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3503         if (vmx->vpid == 0)
3504                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3505         if (!enable_ept) {
3506                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3507                 enable_unrestricted_guest = 0;
3508         }
3509         if (!enable_unrestricted_guest)
3510                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3511         if (!ple_gap)
3512                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3513         return exec_control;
3514 }
3515
3516 /*
3517  * Sets up the vmcs for emulated real mode.
3518  */
3519 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3520 {
3521         unsigned long a;
3522         int i;
3523
3524         /* I/O */
3525         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3526         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3527
3528         if (cpu_has_vmx_msr_bitmap())
3529                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3530
3531         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3532
3533         /* Control */
3534         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3535                 vmcs_config.pin_based_exec_ctrl);
3536
3537         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3538
3539         if (cpu_has_secondary_exec_ctrls()) {
3540                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3541                                 vmx_secondary_exec_control(vmx));
3542         }
3543
3544         if (ple_gap) {
3545                 vmcs_write32(PLE_GAP, ple_gap);
3546                 vmcs_write32(PLE_WINDOW, ple_window);
3547         }
3548
3549         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
3550         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
3551         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
3552
3553         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
3554         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
3555         vmx_set_constant_host_state();
3556 #ifdef CONFIG_X86_64
3557         rdmsrl(MSR_FS_BASE, a);
3558         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3559         rdmsrl(MSR_GS_BASE, a);
3560         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3561 #else
3562         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3563         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3564 #endif
3565
3566         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3567         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3568         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3569         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3570         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3571
3572         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3573                 u32 msr_low, msr_high;
3574                 u64 host_pat;
3575                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3576                 host_pat = msr_low | ((u64) msr_high << 32);
3577                 /* Write the default value follow host pat */
3578                 vmcs_write64(GUEST_IA32_PAT, host_pat);
3579                 /* Keep arch.pat sync with GUEST_IA32_PAT */
3580                 vmx->vcpu.arch.pat = host_pat;
3581         }
3582
3583         for (i = 0; i < NR_VMX_MSR; ++i) {
3584                 u32 index = vmx_msr_index[i];
3585                 u32 data_low, data_high;
3586                 int j = vmx->nmsrs;
3587
3588                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3589                         continue;
3590                 if (wrmsr_safe(index, data_low, data_high) < 0)
3591                         continue;
3592                 vmx->guest_msrs[j].index = i;
3593                 vmx->guest_msrs[j].data = 0;
3594                 vmx->guest_msrs[j].mask = -1ull;
3595                 ++vmx->nmsrs;
3596         }
3597
3598         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3599
3600         /* 22.2.1, 20.8.1 */
3601         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3602
3603         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3604         set_cr4_guest_host_mask(vmx);
3605
3606         kvm_write_tsc(&vmx->vcpu, 0);
3607
3608         return 0;
3609 }
3610
3611 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3612 {
3613         struct vcpu_vmx *vmx = to_vmx(vcpu);
3614         u64 msr;
3615         int ret;
3616
3617         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3618
3619         vmx->rmode.vm86_active = 0;
3620
3621         vmx->soft_vnmi_blocked = 0;
3622
3623         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3624         kvm_set_cr8(&vmx->vcpu, 0);
3625         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3626         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3627                 msr |= MSR_IA32_APICBASE_BSP;
3628         kvm_set_apic_base(&vmx->vcpu, msr);
3629
3630         ret = fx_init(&vmx->vcpu);
3631         if (ret != 0)
3632                 goto out;
3633
3634         vmx_segment_cache_clear(vmx);
3635
3636         seg_setup(VCPU_SREG_CS);
3637         /*
3638          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3639          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
3640          */
3641         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3642                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3643                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3644         } else {
3645                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3646                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3647         }
3648
3649         seg_setup(VCPU_SREG_DS);
3650         seg_setup(VCPU_SREG_ES);
3651         seg_setup(VCPU_SREG_FS);
3652         seg_setup(VCPU_SREG_GS);
3653         seg_setup(VCPU_SREG_SS);
3654
3655         vmcs_write16(GUEST_TR_SELECTOR, 0);
3656         vmcs_writel(GUEST_TR_BASE, 0);
3657         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3658         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3659
3660         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3661         vmcs_writel(GUEST_LDTR_BASE, 0);
3662         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3663         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3664
3665         vmcs_write32(GUEST_SYSENTER_CS, 0);
3666         vmcs_writel(GUEST_SYSENTER_ESP, 0);
3667         vmcs_writel(GUEST_SYSENTER_EIP, 0);
3668
3669         vmcs_writel(GUEST_RFLAGS, 0x02);
3670         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3671                 kvm_rip_write(vcpu, 0xfff0);
3672         else
3673                 kvm_rip_write(vcpu, 0);
3674         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3675
3676         vmcs_writel(GUEST_DR7, 0x400);
3677
3678         vmcs_writel(GUEST_GDTR_BASE, 0);
3679         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3680
3681         vmcs_writel(GUEST_IDTR_BASE, 0);
3682         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3683
3684         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3685         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3686         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3687
3688         /* Special registers */
3689         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3690
3691         setup_msrs(vmx);
3692
3693         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
3694
3695         if (cpu_has_vmx_tpr_shadow()) {
3696                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3697                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3698                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3699                                      __pa(vmx->vcpu.arch.apic->regs));
3700                 vmcs_write32(TPR_THRESHOLD, 0);
3701         }
3702
3703         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3704                 vmcs_write64(APIC_ACCESS_ADDR,
3705                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3706
3707         if (vmx->vpid != 0)
3708                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3709
3710         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3711         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3712         vmx_set_cr4(&vmx->vcpu, 0);
3713         vmx_set_efer(&vmx->vcpu, 0);
3714         vmx_fpu_activate(&vmx->vcpu);
3715         update_exception_bitmap(&vmx->vcpu);
3716
3717         vpid_sync_context(vmx);
3718
3719         ret = 0;
3720
3721         /* HACK: Don't enable emulation on guest boot/reset */
3722         vmx->emulation_required = 0;
3723
3724 out:
3725         return ret;
3726 }
3727
3728 static void enable_irq_window(struct kvm_vcpu *vcpu)
3729 {
3730         u32 cpu_based_vm_exec_control;
3731
3732         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3733         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3734         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3735 }
3736
3737 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3738 {
3739         u32 cpu_based_vm_exec_control;
3740
3741         if (!cpu_has_virtual_nmis()) {
3742                 enable_irq_window(vcpu);
3743                 return;
3744         }
3745
3746         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3747                 enable_irq_window(vcpu);
3748                 return;
3749         }
3750         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3751         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3752         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3753 }
3754
3755 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
3756 {
3757         struct vcpu_vmx *vmx = to_vmx(vcpu);
3758         uint32_t intr;
3759         int irq = vcpu->arch.interrupt.nr;
3760
3761         trace_kvm_inj_virq(irq);
3762
3763         ++vcpu->stat.irq_injections;
3764         if (vmx->rmode.vm86_active) {
3765                 int inc_eip = 0;
3766                 if (vcpu->arch.interrupt.soft)
3767                         inc_eip = vcpu->arch.event_exit_inst_len;
3768                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
3769                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3770                 return;
3771         }
3772         intr = irq | INTR_INFO_VALID_MASK;
3773         if (vcpu->arch.interrupt.soft) {
3774                 intr |= INTR_TYPE_SOFT_INTR;
3775                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3776                              vmx->vcpu.arch.event_exit_inst_len);
3777         } else
3778                 intr |= INTR_TYPE_EXT_INTR;
3779         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
3780         vmx_clear_hlt(vcpu);
3781 }
3782
3783 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
3784 {
3785         struct vcpu_vmx *vmx = to_vmx(vcpu);
3786
3787         if (!cpu_has_virtual_nmis()) {
3788                 /*
3789                  * Tracking the NMI-blocked state in software is built upon
3790                  * finding the next open IRQ window. This, in turn, depends on
3791                  * well-behaving guests: They have to keep IRQs disabled at
3792                  * least as long as the NMI handler runs. Otherwise we may
3793                  * cause NMI nesting, maybe breaking the guest. But as this is
3794                  * highly unlikely, we can live with the residual risk.
3795                  */
3796                 vmx->soft_vnmi_blocked = 1;
3797                 vmx->vnmi_blocked_time = 0;
3798         }
3799
3800         ++vcpu->stat.nmi_injections;
3801         vmx->nmi_known_unmasked = false;
3802         if (vmx->rmode.vm86_active) {
3803                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
3804                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3805                 return;
3806         }
3807         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
3808                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
3809         vmx_clear_hlt(vcpu);
3810 }
3811
3812 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
3813 {
3814         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
3815                 return 0;
3816
3817         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3818                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
3819                    | GUEST_INTR_STATE_NMI));
3820 }
3821
3822 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3823 {
3824         if (!cpu_has_virtual_nmis())
3825                 return to_vmx(vcpu)->soft_vnmi_blocked;
3826         if (to_vmx(vcpu)->nmi_known_unmasked)
3827                 return false;
3828         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3829 }
3830
3831 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3832 {
3833         struct vcpu_vmx *vmx = to_vmx(vcpu);
3834
3835         if (!cpu_has_virtual_nmis()) {
3836                 if (vmx->soft_vnmi_blocked != masked) {
3837                         vmx->soft_vnmi_blocked = masked;
3838                         vmx->vnmi_blocked_time = 0;
3839                 }
3840         } else {
3841                 vmx->nmi_known_unmasked = !masked;
3842                 if (masked)
3843                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3844                                       GUEST_INTR_STATE_NMI);
3845                 else
3846                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3847                                         GUEST_INTR_STATE_NMI);
3848         }
3849 }
3850
3851 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
3852 {
3853         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
3854                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3855                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
3856 }
3857
3858 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
3859 {
3860         int ret;
3861         struct kvm_userspace_memory_region tss_mem = {
3862                 .slot = TSS_PRIVATE_MEMSLOT,
3863                 .guest_phys_addr = addr,
3864                 .memory_size = PAGE_SIZE * 3,
3865                 .flags = 0,
3866         };
3867
3868         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3869         if (ret)
3870                 return ret;
3871         kvm->arch.tss_addr = addr;
3872         if (!init_rmode_tss(kvm))
3873                 return  -ENOMEM;
3874
3875         return 0;
3876 }
3877
3878 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3879                                   int vec, u32 err_code)
3880 {
3881         /*
3882          * Instruction with address size override prefix opcode 0x67
3883          * Cause the #SS fault with 0 error code in VM86 mode.
3884          */
3885         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3886                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
3887                         return 1;
3888         /*
3889          * Forward all other exceptions that are valid in real mode.
3890          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3891          *        the required debugging infrastructure rework.
3892          */
3893         switch (vec) {
3894         case DB_VECTOR:
3895                 if (vcpu->guest_debug &
3896                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
3897                         return 0;
3898                 kvm_queue_exception(vcpu, vec);
3899                 return 1;
3900         case BP_VECTOR:
3901                 /*
3902                  * Update instruction length as we may reinject the exception
3903                  * from user space while in guest debugging mode.
3904                  */
3905                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3906                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3907                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3908                         return 0;
3909                 /* fall through */
3910         case DE_VECTOR:
3911         case OF_VECTOR:
3912         case BR_VECTOR:
3913         case UD_VECTOR:
3914         case DF_VECTOR:
3915         case SS_VECTOR:
3916         case GP_VECTOR:
3917         case MF_VECTOR:
3918                 kvm_queue_exception(vcpu, vec);
3919                 return 1;
3920         }
3921         return 0;
3922 }
3923
3924 /*
3925  * Trigger machine check on the host. We assume all the MSRs are already set up
3926  * by the CPU and that we still run on the same CPU as the MCE occurred on.
3927  * We pass a fake environment to the machine check handler because we want
3928  * the guest to be always treated like user space, no matter what context
3929  * it used internally.
3930  */
3931 static void kvm_machine_check(void)
3932 {
3933 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3934         struct pt_regs regs = {
3935                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3936                 .flags = X86_EFLAGS_IF,
3937         };
3938
3939         do_machine_check(&regs, 0);
3940 #endif
3941 }
3942
3943 static int handle_machine_check(struct kvm_vcpu *vcpu)
3944 {
3945         /* already handled by vcpu_run */
3946         return 1;
3947 }
3948
3949 static int handle_exception(struct kvm_vcpu *vcpu)
3950 {
3951         struct vcpu_vmx *vmx = to_vmx(vcpu);
3952         struct kvm_run *kvm_run = vcpu->run;
3953         u32 intr_info, ex_no, error_code;
3954         unsigned long cr2, rip, dr6;
3955         u32 vect_info;
3956         enum emulation_result er;
3957
3958         vect_info = vmx->idt_vectoring_info;
3959         intr_info = vmx->exit_intr_info;
3960
3961         if (is_machine_check(intr_info))
3962                 return handle_machine_check(vcpu);
3963
3964         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3965             !is_page_fault(intr_info)) {
3966                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3967                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3968                 vcpu->run->internal.ndata = 2;
3969                 vcpu->run->internal.data[0] = vect_info;
3970                 vcpu->run->internal.data[1] = intr_info;
3971                 return 0;
3972         }
3973
3974         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3975                 return 1;  /* already handled by vmx_vcpu_run() */
3976
3977         if (is_no_device(intr_info)) {
3978                 vmx_fpu_activate(vcpu);
3979                 return 1;
3980         }
3981
3982         if (is_invalid_opcode(intr_info)) {
3983                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
3984                 if (er != EMULATE_DONE)
3985                         kvm_queue_exception(vcpu, UD_VECTOR);
3986                 return 1;
3987         }
3988
3989         error_code = 0;
3990         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3991                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3992         if (is_page_fault(intr_info)) {
3993                 /* EPT won't cause page fault directly */
3994                 if (enable_ept)
3995                         BUG();
3996                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3997                 trace_kvm_page_fault(cr2, error_code);
3998
3999                 if (kvm_event_needs_reinjection(vcpu))
4000                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4001                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4002         }
4003
4004         if (vmx->rmode.vm86_active &&
4005             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4006                                                                 error_code)) {
4007                 if (vcpu->arch.halt_request) {
4008                         vcpu->arch.halt_request = 0;
4009                         return kvm_emulate_halt(vcpu);
4010                 }
4011                 return 1;
4012         }
4013
4014         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4015         switch (ex_no) {
4016         case DB_VECTOR:
4017                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4018                 if (!(vcpu->guest_debug &
4019                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4020                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4021                         kvm_queue_exception(vcpu, DB_VECTOR);
4022                         return 1;
4023                 }
4024                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4025                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4026                 /* fall through */
4027         case BP_VECTOR:
4028                 /*
4029                  * Update instruction length as we may reinject #BP from
4030                  * user space while in guest debugging mode. Reading it for
4031                  * #DB as well causes no harm, it is not used in that case.
4032                  */
4033                 vmx->vcpu.arch.event_exit_inst_len =
4034                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4035                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4036                 rip = kvm_rip_read(vcpu);
4037                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4038                 kvm_run->debug.arch.exception = ex_no;
4039                 break;
4040         default:
4041                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4042                 kvm_run->ex.exception = ex_no;
4043                 kvm_run->ex.error_code = error_code;
4044                 break;
4045         }
4046         return 0;
4047 }
4048
4049 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4050 {
4051         ++vcpu->stat.irq_exits;
4052         return 1;
4053 }
4054
4055 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4056 {
4057         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4058         return 0;
4059 }
4060
4061 static int handle_io(struct kvm_vcpu *vcpu)
4062 {
4063         unsigned long exit_qualification;
4064         int size, in, string;
4065         unsigned port;
4066
4067         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4068         string = (exit_qualification & 16) != 0;
4069         in = (exit_qualification & 8) != 0;
4070
4071         ++vcpu->stat.io_exits;
4072
4073         if (string || in)
4074                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4075
4076         port = exit_qualification >> 16;
4077         size = (exit_qualification & 7) + 1;
4078         skip_emulated_instruction(vcpu);
4079
4080         return kvm_fast_pio_out(vcpu, size, port);
4081 }
4082
4083 static void
4084 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4085 {
4086         /*
4087          * Patch in the VMCALL instruction:
4088          */
4089         hypercall[0] = 0x0f;
4090         hypercall[1] = 0x01;
4091         hypercall[2] = 0xc1;
4092 }
4093
4094 static int handle_cr(struct kvm_vcpu *vcpu)
4095 {
4096         unsigned long exit_qualification, val;
4097         int cr;
4098         int reg;
4099         int err;
4100
4101         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4102         cr = exit_qualification & 15;
4103         reg = (exit_qualification >> 8) & 15;
4104         switch ((exit_qualification >> 4) & 3) {
4105         case 0: /* mov to cr */
4106                 val = kvm_register_read(vcpu, reg);
4107                 trace_kvm_cr_write(cr, val);
4108                 switch (cr) {
4109                 case 0:
4110                         err = kvm_set_cr0(vcpu, val);
4111                         kvm_complete_insn_gp(vcpu, err);
4112                         return 1;
4113                 case 3:
4114                         err = kvm_set_cr3(vcpu, val);
4115                         kvm_complete_insn_gp(vcpu, err);
4116                         return 1;
4117                 case 4:
4118                         err = kvm_set_cr4(vcpu, val);
4119                         kvm_complete_insn_gp(vcpu, err);
4120                         return 1;
4121                 case 8: {
4122                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4123                                 u8 cr8 = kvm_register_read(vcpu, reg);
4124                                 err = kvm_set_cr8(vcpu, cr8);
4125                                 kvm_complete_insn_gp(vcpu, err);
4126                                 if (irqchip_in_kernel(vcpu->kvm))
4127                                         return 1;
4128                                 if (cr8_prev <= cr8)
4129                                         return 1;
4130                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4131                                 return 0;
4132                         }
4133                 };
4134                 break;
4135         case 2: /* clts */
4136                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4137                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4138                 skip_emulated_instruction(vcpu);
4139                 vmx_fpu_activate(vcpu);
4140                 return 1;
4141         case 1: /*mov from cr*/
4142                 switch (cr) {
4143                 case 3:
4144                         val = kvm_read_cr3(vcpu);
4145                         kvm_register_write(vcpu, reg, val);
4146                         trace_kvm_cr_read(cr, val);
4147                         skip_emulated_instruction(vcpu);
4148                         return 1;
4149                 case 8:
4150                         val = kvm_get_cr8(vcpu);
4151                         kvm_register_write(vcpu, reg, val);
4152                         trace_kvm_cr_read(cr, val);
4153                         skip_emulated_instruction(vcpu);
4154                         return 1;
4155                 }
4156                 break;
4157         case 3: /* lmsw */
4158                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4159                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4160                 kvm_lmsw(vcpu, val);
4161
4162                 skip_emulated_instruction(vcpu);
4163                 return 1;
4164         default:
4165                 break;
4166         }
4167         vcpu->run->exit_reason = 0;
4168         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4169                (int)(exit_qualification >> 4) & 3, cr);
4170         return 0;
4171 }
4172
4173 static int handle_dr(struct kvm_vcpu *vcpu)
4174 {
4175         unsigned long exit_qualification;
4176         int dr, reg;
4177
4178         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4179         if (!kvm_require_cpl(vcpu, 0))
4180                 return 1;
4181         dr = vmcs_readl(GUEST_DR7);
4182         if (dr & DR7_GD) {
4183                 /*
4184                  * As the vm-exit takes precedence over the debug trap, we
4185                  * need to emulate the latter, either for the host or the
4186                  * guest debugging itself.
4187                  */
4188                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4189                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4190                         vcpu->run->debug.arch.dr7 = dr;
4191                         vcpu->run->debug.arch.pc =
4192                                 vmcs_readl(GUEST_CS_BASE) +
4193                                 vmcs_readl(GUEST_RIP);
4194                         vcpu->run->debug.arch.exception = DB_VECTOR;
4195                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4196                         return 0;
4197                 } else {
4198                         vcpu->arch.dr7 &= ~DR7_GD;
4199                         vcpu->arch.dr6 |= DR6_BD;
4200                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4201                         kvm_queue_exception(vcpu, DB_VECTOR);
4202                         return 1;
4203                 }
4204         }
4205
4206         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4207         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4208         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4209         if (exit_qualification & TYPE_MOV_FROM_DR) {
4210                 unsigned long val;
4211                 if (!kvm_get_dr(vcpu, dr, &val))
4212                         kvm_register_write(vcpu, reg, val);
4213         } else
4214                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4215         skip_emulated_instruction(vcpu);
4216         return 1;
4217 }
4218
4219 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4220 {
4221         vmcs_writel(GUEST_DR7, val);
4222 }
4223
4224 static int handle_cpuid(struct kvm_vcpu *vcpu)
4225 {
4226         kvm_emulate_cpuid(vcpu);
4227         return 1;
4228 }
4229
4230 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4231 {
4232         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4233         u64 data;
4234
4235         if (vmx_get_msr(vcpu, ecx, &data)) {
4236                 trace_kvm_msr_read_ex(ecx);
4237                 kvm_inject_gp(vcpu, 0);
4238                 return 1;
4239         }
4240
4241         trace_kvm_msr_read(ecx, data);
4242
4243         /* FIXME: handling of bits 32:63 of rax, rdx */
4244         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4245         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4246         skip_emulated_instruction(vcpu);
4247         return 1;
4248 }
4249
4250 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4251 {
4252         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4253         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4254                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4255
4256         if (vmx_set_msr(vcpu, ecx, data) != 0) {
4257                 trace_kvm_msr_write_ex(ecx, data);
4258                 kvm_inject_gp(vcpu, 0);
4259                 return 1;
4260         }
4261
4262         trace_kvm_msr_write(ecx, data);
4263         skip_emulated_instruction(vcpu);
4264         return 1;
4265 }
4266
4267 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4268 {
4269         kvm_make_request(KVM_REQ_EVENT, vcpu);
4270         return 1;
4271 }
4272
4273 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4274 {
4275         u32 cpu_based_vm_exec_control;
4276
4277         /* clear pending irq */
4278         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4279         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4280         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4281
4282         kvm_make_request(KVM_REQ_EVENT, vcpu);
4283
4284         ++vcpu->stat.irq_window_exits;
4285
4286         /*
4287          * If the user space waits to inject interrupts, exit as soon as
4288          * possible
4289          */
4290         if (!irqchip_in_kernel(vcpu->kvm) &&
4291             vcpu->run->request_interrupt_window &&
4292             !kvm_cpu_has_interrupt(vcpu)) {
4293                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4294                 return 0;
4295         }
4296         return 1;
4297 }
4298
4299 static int handle_halt(struct kvm_vcpu *vcpu)
4300 {
4301         skip_emulated_instruction(vcpu);
4302         return kvm_emulate_halt(vcpu);
4303 }
4304
4305 static int handle_vmcall(struct kvm_vcpu *vcpu)
4306 {
4307         skip_emulated_instruction(vcpu);
4308         kvm_emulate_hypercall(vcpu);
4309         return 1;
4310 }
4311
4312 static int handle_invd(struct kvm_vcpu *vcpu)
4313 {
4314         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4315 }
4316
4317 static int handle_invlpg(struct kvm_vcpu *vcpu)
4318 {
4319         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4320
4321         kvm_mmu_invlpg(vcpu, exit_qualification);
4322         skip_emulated_instruction(vcpu);
4323         return 1;
4324 }
4325
4326 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4327 {
4328         skip_emulated_instruction(vcpu);
4329         kvm_emulate_wbinvd(vcpu);
4330         return 1;
4331 }
4332
4333 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4334 {
4335         u64 new_bv = kvm_read_edx_eax(vcpu);
4336         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4337
4338         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4339                 skip_emulated_instruction(vcpu);
4340         return 1;
4341 }
4342
4343 static int handle_apic_access(struct kvm_vcpu *vcpu)
4344 {
4345         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4346 }
4347
4348 static int handle_task_switch(struct kvm_vcpu *vcpu)
4349 {
4350         struct vcpu_vmx *vmx = to_vmx(vcpu);
4351         unsigned long exit_qualification;
4352         bool has_error_code = false;
4353         u32 error_code = 0;
4354         u16 tss_selector;
4355         int reason, type, idt_v;
4356
4357         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4358         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4359
4360         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4361
4362         reason = (u32)exit_qualification >> 30;
4363         if (reason == TASK_SWITCH_GATE && idt_v) {
4364                 switch (type) {
4365                 case INTR_TYPE_NMI_INTR:
4366                         vcpu->arch.nmi_injected = false;
4367                         vmx_set_nmi_mask(vcpu, true);
4368                         break;
4369                 case INTR_TYPE_EXT_INTR:
4370                 case INTR_TYPE_SOFT_INTR:
4371                         kvm_clear_interrupt_queue(vcpu);
4372                         break;
4373                 case INTR_TYPE_HARD_EXCEPTION:
4374                         if (vmx->idt_vectoring_info &
4375                             VECTORING_INFO_DELIVER_CODE_MASK) {
4376                                 has_error_code = true;
4377                                 error_code =
4378                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
4379                         }
4380                         /* fall through */
4381                 case INTR_TYPE_SOFT_EXCEPTION:
4382                         kvm_clear_exception_queue(vcpu);
4383                         break;
4384                 default:
4385                         break;
4386                 }
4387         }
4388         tss_selector = exit_qualification;
4389
4390         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4391                        type != INTR_TYPE_EXT_INTR &&
4392                        type != INTR_TYPE_NMI_INTR))
4393                 skip_emulated_instruction(vcpu);
4394
4395         if (kvm_task_switch(vcpu, tss_selector, reason,
4396                                 has_error_code, error_code) == EMULATE_FAIL) {
4397                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4398                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4399                 vcpu->run->internal.ndata = 0;
4400                 return 0;
4401         }
4402
4403         /* clear all local breakpoint enable flags */
4404         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4405
4406         /*
4407          * TODO: What about debug traps on tss switch?
4408          *       Are we supposed to inject them and update dr6?
4409          */
4410
4411         return 1;
4412 }
4413
4414 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4415 {
4416         unsigned long exit_qualification;
4417         gpa_t gpa;
4418         int gla_validity;
4419
4420         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4421
4422         if (exit_qualification & (1 << 6)) {
4423                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4424                 return -EINVAL;
4425         }
4426
4427         gla_validity = (exit_qualification >> 7) & 0x3;
4428         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4429                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4430                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4431                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4432                         vmcs_readl(GUEST_LINEAR_ADDRESS));
4433                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4434                         (long unsigned int)exit_qualification);
4435                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4436                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4437                 return 0;
4438         }
4439
4440         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4441         trace_kvm_page_fault(gpa, exit_qualification);
4442         return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
4443 }
4444
4445 static u64 ept_rsvd_mask(u64 spte, int level)
4446 {
4447         int i;
4448         u64 mask = 0;
4449
4450         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4451                 mask |= (1ULL << i);
4452
4453         if (level > 2)
4454                 /* bits 7:3 reserved */
4455                 mask |= 0xf8;
4456         else if (level == 2) {
4457                 if (spte & (1ULL << 7))
4458                         /* 2MB ref, bits 20:12 reserved */
4459                         mask |= 0x1ff000;
4460                 else
4461                         /* bits 6:3 reserved */
4462                         mask |= 0x78;
4463         }
4464
4465         return mask;
4466 }
4467
4468 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4469                                        int level)
4470 {
4471         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4472
4473         /* 010b (write-only) */
4474         WARN_ON((spte & 0x7) == 0x2);
4475
4476         /* 110b (write/execute) */
4477         WARN_ON((spte & 0x7) == 0x6);
4478
4479         /* 100b (execute-only) and value not supported by logical processor */
4480         if (!cpu_has_vmx_ept_execute_only())
4481                 WARN_ON((spte & 0x7) == 0x4);
4482
4483         /* not 000b */
4484         if ((spte & 0x7)) {
4485                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4486
4487                 if (rsvd_bits != 0) {
4488                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4489                                          __func__, rsvd_bits);
4490                         WARN_ON(1);
4491                 }
4492
4493                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4494                         u64 ept_mem_type = (spte & 0x38) >> 3;
4495
4496                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
4497                             ept_mem_type == 7) {
4498                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4499                                                 __func__, ept_mem_type);
4500                                 WARN_ON(1);
4501                         }
4502                 }
4503         }
4504 }
4505
4506 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4507 {
4508         u64 sptes[4];
4509         int nr_sptes, i;
4510         gpa_t gpa;
4511
4512         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4513
4514         printk(KERN_ERR "EPT: Misconfiguration.\n");
4515         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4516
4517         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4518
4519         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4520                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4521
4522         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4523         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4524
4525         return 0;
4526 }
4527
4528 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4529 {
4530         u32 cpu_based_vm_exec_control;
4531
4532         /* clear pending NMI */
4533         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4534         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4535         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4536         ++vcpu->stat.nmi_window_exits;
4537         kvm_make_request(KVM_REQ_EVENT, vcpu);
4538
4539         return 1;
4540 }
4541
4542 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4543 {
4544         struct vcpu_vmx *vmx = to_vmx(vcpu);
4545         enum emulation_result err = EMULATE_DONE;
4546         int ret = 1;
4547         u32 cpu_exec_ctrl;
4548         bool intr_window_requested;
4549
4550         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4551         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4552
4553         while (!guest_state_valid(vcpu)) {
4554                 if (intr_window_requested
4555                     && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4556                         return handle_interrupt_window(&vmx->vcpu);
4557
4558                 err = emulate_instruction(vcpu, 0);
4559
4560                 if (err == EMULATE_DO_MMIO) {
4561                         ret = 0;
4562                         goto out;
4563                 }
4564
4565                 if (err != EMULATE_DONE)
4566                         return 0;
4567
4568                 if (signal_pending(current))
4569                         goto out;
4570                 if (need_resched())
4571                         schedule();
4572         }
4573
4574         vmx->emulation_required = 0;
4575 out:
4576         return ret;
4577 }
4578
4579 /*
4580  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4581  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4582  */
4583 static int handle_pause(struct kvm_vcpu *vcpu)
4584 {
4585         skip_emulated_instruction(vcpu);
4586         kvm_vcpu_on_spin(vcpu);
4587
4588         return 1;
4589 }
4590
4591 static int handle_invalid_op(struct kvm_vcpu *vcpu)
4592 {
4593         kvm_queue_exception(vcpu, UD_VECTOR);
4594         return 1;
4595 }
4596
4597 /*
4598  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4599  * We could reuse a single VMCS for all the L2 guests, but we also want the
4600  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4601  * allows keeping them loaded on the processor, and in the future will allow
4602  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4603  * every entry if they never change.
4604  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4605  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4606  *
4607  * The following functions allocate and free a vmcs02 in this pool.
4608  */
4609
4610 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4611 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4612 {
4613         struct vmcs02_list *item;
4614         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4615                 if (item->vmptr == vmx->nested.current_vmptr) {
4616                         list_move(&item->list, &vmx->nested.vmcs02_pool);
4617                         return &item->vmcs02;
4618                 }
4619
4620         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4621                 /* Recycle the least recently used VMCS. */
4622                 item = list_entry(vmx->nested.vmcs02_pool.prev,
4623                         struct vmcs02_list, list);
4624                 item->vmptr = vmx->nested.current_vmptr;
4625                 list_move(&item->list, &vmx->nested.vmcs02_pool);
4626                 return &item->vmcs02;
4627         }
4628
4629         /* Create a new VMCS */
4630         item = (struct vmcs02_list *)
4631                 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4632         if (!item)
4633                 return NULL;
4634         item->vmcs02.vmcs = alloc_vmcs();
4635         if (!item->vmcs02.vmcs) {
4636                 kfree(item);
4637                 return NULL;
4638         }
4639         loaded_vmcs_init(&item->vmcs02);
4640         item->vmptr = vmx->nested.current_vmptr;
4641         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4642         vmx->nested.vmcs02_num++;
4643         return &item->vmcs02;
4644 }
4645
4646 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4647 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4648 {
4649         struct vmcs02_list *item;
4650         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4651                 if (item->vmptr == vmptr) {
4652                         free_loaded_vmcs(&item->vmcs02);
4653                         list_del(&item->list);
4654                         kfree(item);
4655                         vmx->nested.vmcs02_num--;
4656                         return;
4657                 }
4658 }
4659
4660 /*
4661  * Free all VMCSs saved for this vcpu, except the one pointed by
4662  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4663  * currently used, if running L2), and vmcs01 when running L2.
4664  */
4665 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4666 {
4667         struct vmcs02_list *item, *n;
4668         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4669                 if (vmx->loaded_vmcs != &item->vmcs02)
4670                         free_loaded_vmcs(&item->vmcs02);
4671                 list_del(&item->list);
4672                 kfree(item);
4673         }
4674         vmx->nested.vmcs02_num = 0;
4675
4676         if (vmx->loaded_vmcs != &vmx->vmcs01)
4677                 free_loaded_vmcs(&vmx->vmcs01);
4678 }
4679
4680 /*
4681  * Emulate the VMXON instruction.
4682  * Currently, we just remember that VMX is active, and do not save or even
4683  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4684  * do not currently need to store anything in that guest-allocated memory
4685  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
4686  * argument is different from the VMXON pointer (which the spec says they do).
4687  */
4688 static int handle_vmon(struct kvm_vcpu *vcpu)
4689 {
4690         struct kvm_segment cs;
4691         struct vcpu_vmx *vmx = to_vmx(vcpu);
4692
4693         /* The Intel VMX Instruction Reference lists a bunch of bits that
4694          * are prerequisite to running VMXON, most notably cr4.VMXE must be
4695          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
4696          * Otherwise, we should fail with #UD. We test these now:
4697          */
4698         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
4699             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
4700             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4701                 kvm_queue_exception(vcpu, UD_VECTOR);
4702                 return 1;
4703         }
4704
4705         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4706         if (is_long_mode(vcpu) && !cs.l) {
4707                 kvm_queue_exception(vcpu, UD_VECTOR);
4708                 return 1;
4709         }
4710
4711         if (vmx_get_cpl(vcpu)) {
4712                 kvm_inject_gp(vcpu, 0);
4713                 return 1;
4714         }
4715
4716         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
4717         vmx->nested.vmcs02_num = 0;
4718
4719         vmx->nested.vmxon = true;
4720
4721         skip_emulated_instruction(vcpu);
4722         return 1;
4723 }
4724
4725 /*
4726  * Intel's VMX Instruction Reference specifies a common set of prerequisites
4727  * for running VMX instructions (except VMXON, whose prerequisites are
4728  * slightly different). It also specifies what exception to inject otherwise.
4729  */
4730 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
4731 {
4732         struct kvm_segment cs;
4733         struct vcpu_vmx *vmx = to_vmx(vcpu);
4734
4735         if (!vmx->nested.vmxon) {
4736                 kvm_queue_exception(vcpu, UD_VECTOR);
4737                 return 0;
4738         }
4739
4740         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4741         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
4742             (is_long_mode(vcpu) && !cs.l)) {
4743                 kvm_queue_exception(vcpu, UD_VECTOR);
4744                 return 0;
4745         }
4746
4747         if (vmx_get_cpl(vcpu)) {
4748                 kvm_inject_gp(vcpu, 0);
4749                 return 0;
4750         }
4751
4752         return 1;
4753 }
4754
4755 /*
4756  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
4757  * just stops using VMX.
4758  */
4759 static void free_nested(struct vcpu_vmx *vmx)
4760 {
4761         if (!vmx->nested.vmxon)
4762                 return;
4763         vmx->nested.vmxon = false;
4764         if (vmx->nested.current_vmptr != -1ull) {
4765                 kunmap(vmx->nested.current_vmcs12_page);
4766                 nested_release_page(vmx->nested.current_vmcs12_page);
4767                 vmx->nested.current_vmptr = -1ull;
4768                 vmx->nested.current_vmcs12 = NULL;
4769         }
4770         /* Unpin physical memory we referred to in current vmcs02 */
4771         if (vmx->nested.apic_access_page) {
4772                 nested_release_page(vmx->nested.apic_access_page);
4773                 vmx->nested.apic_access_page = 0;
4774         }
4775
4776         nested_free_all_saved_vmcss(vmx);
4777 }
4778
4779 /* Emulate the VMXOFF instruction */
4780 static int handle_vmoff(struct kvm_vcpu *vcpu)
4781 {
4782         if (!nested_vmx_check_permission(vcpu))
4783                 return 1;
4784         free_nested(to_vmx(vcpu));
4785         skip_emulated_instruction(vcpu);
4786         return 1;
4787 }
4788
4789 /*
4790  * Decode the memory-address operand of a vmx instruction, as recorded on an
4791  * exit caused by such an instruction (run by a guest hypervisor).
4792  * On success, returns 0. When the operand is invalid, returns 1 and throws
4793  * #UD or #GP.
4794  */
4795 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
4796                                  unsigned long exit_qualification,
4797                                  u32 vmx_instruction_info, gva_t *ret)
4798 {
4799         /*
4800          * According to Vol. 3B, "Information for VM Exits Due to Instruction
4801          * Execution", on an exit, vmx_instruction_info holds most of the
4802          * addressing components of the operand. Only the displacement part
4803          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
4804          * For how an actual address is calculated from all these components,
4805          * refer to Vol. 1, "Operand Addressing".
4806          */
4807         int  scaling = vmx_instruction_info & 3;
4808         int  addr_size = (vmx_instruction_info >> 7) & 7;
4809         bool is_reg = vmx_instruction_info & (1u << 10);
4810         int  seg_reg = (vmx_instruction_info >> 15) & 7;
4811         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
4812         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
4813         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
4814         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
4815
4816         if (is_reg) {
4817                 kvm_queue_exception(vcpu, UD_VECTOR);
4818                 return 1;
4819         }
4820
4821         /* Addr = segment_base + offset */
4822         /* offset = base + [index * scale] + displacement */
4823         *ret = vmx_get_segment_base(vcpu, seg_reg);
4824         if (base_is_valid)
4825                 *ret += kvm_register_read(vcpu, base_reg);
4826         if (index_is_valid)
4827                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
4828         *ret += exit_qualification; /* holds the displacement */
4829
4830         if (addr_size == 1) /* 32 bit */
4831                 *ret &= 0xffffffff;
4832
4833         /*
4834          * TODO: throw #GP (and return 1) in various cases that the VM*
4835          * instructions require it - e.g., offset beyond segment limit,
4836          * unusable or unreadable/unwritable segment, non-canonical 64-bit
4837          * address, and so on. Currently these are not checked.
4838          */
4839         return 0;
4840 }
4841
4842 /*
4843  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
4844  * set the success or error code of an emulated VMX instruction, as specified
4845  * by Vol 2B, VMX Instruction Reference, "Conventions".
4846  */
4847 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
4848 {
4849         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
4850                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
4851                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
4852 }
4853
4854 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
4855 {
4856         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
4857                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
4858                             X86_EFLAGS_SF | X86_EFLAGS_OF))
4859                         | X86_EFLAGS_CF);
4860 }
4861
4862 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
4863                                         u32 vm_instruction_error)
4864 {
4865         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
4866                 /*
4867                  * failValid writes the error number to the current VMCS, which
4868                  * can't be done there isn't a current VMCS.
4869                  */
4870                 nested_vmx_failInvalid(vcpu);
4871                 return;
4872         }
4873         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
4874                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
4875                             X86_EFLAGS_SF | X86_EFLAGS_OF))
4876                         | X86_EFLAGS_ZF);
4877         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
4878 }
4879
4880 /* Emulate the VMCLEAR instruction */
4881 static int handle_vmclear(struct kvm_vcpu *vcpu)
4882 {
4883         struct vcpu_vmx *vmx = to_vmx(vcpu);
4884         gva_t gva;
4885         gpa_t vmptr;
4886         struct vmcs12 *vmcs12;
4887         struct page *page;
4888         struct x86_exception e;
4889
4890         if (!nested_vmx_check_permission(vcpu))
4891                 return 1;
4892
4893         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
4894                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
4895                 return 1;
4896
4897         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
4898                                 sizeof(vmptr), &e)) {
4899                 kvm_inject_page_fault(vcpu, &e);
4900                 return 1;
4901         }
4902
4903         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
4904                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
4905                 skip_emulated_instruction(vcpu);
4906                 return 1;
4907         }
4908
4909         if (vmptr == vmx->nested.current_vmptr) {
4910                 kunmap(vmx->nested.current_vmcs12_page);
4911                 nested_release_page(vmx->nested.current_vmcs12_page);
4912                 vmx->nested.current_vmptr = -1ull;
4913                 vmx->nested.current_vmcs12 = NULL;
4914         }
4915
4916         page = nested_get_page(vcpu, vmptr);
4917         if (page == NULL) {
4918                 /*
4919                  * For accurate processor emulation, VMCLEAR beyond available
4920                  * physical memory should do nothing at all. However, it is
4921                  * possible that a nested vmx bug, not a guest hypervisor bug,
4922                  * resulted in this case, so let's shut down before doing any
4923                  * more damage:
4924                  */
4925                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4926                 return 1;
4927         }
4928         vmcs12 = kmap(page);
4929         vmcs12->launch_state = 0;
4930         kunmap(page);
4931         nested_release_page(page);
4932
4933         nested_free_vmcs02(vmx, vmptr);
4934
4935         skip_emulated_instruction(vcpu);
4936         nested_vmx_succeed(vcpu);
4937         return 1;
4938 }
4939
4940 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
4941
4942 /* Emulate the VMLAUNCH instruction */
4943 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
4944 {
4945         return nested_vmx_run(vcpu, true);
4946 }
4947
4948 /* Emulate the VMRESUME instruction */
4949 static int handle_vmresume(struct kvm_vcpu *vcpu)
4950 {
4951
4952         return nested_vmx_run(vcpu, false);
4953 }
4954
4955 enum vmcs_field_type {
4956         VMCS_FIELD_TYPE_U16 = 0,
4957         VMCS_FIELD_TYPE_U64 = 1,
4958         VMCS_FIELD_TYPE_U32 = 2,
4959         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
4960 };
4961
4962 static inline int vmcs_field_type(unsigned long field)
4963 {
4964         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
4965                 return VMCS_FIELD_TYPE_U32;
4966         return (field >> 13) & 0x3 ;
4967 }
4968
4969 static inline int vmcs_field_readonly(unsigned long field)
4970 {
4971         return (((field >> 10) & 0x3) == 1);
4972 }
4973
4974 /*
4975  * Read a vmcs12 field. Since these can have varying lengths and we return
4976  * one type, we chose the biggest type (u64) and zero-extend the return value
4977  * to that size. Note that the caller, handle_vmread, might need to use only
4978  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
4979  * 64-bit fields are to be returned).
4980  */
4981 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
4982                                         unsigned long field, u64 *ret)
4983 {
4984         short offset = vmcs_field_to_offset(field);
4985         char *p;
4986
4987         if (offset < 0)
4988                 return 0;
4989
4990         p = ((char *)(get_vmcs12(vcpu))) + offset;
4991
4992         switch (vmcs_field_type(field)) {
4993         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
4994                 *ret = *((natural_width *)p);
4995                 return 1;
4996         case VMCS_FIELD_TYPE_U16:
4997                 *ret = *((u16 *)p);
4998                 return 1;
4999         case VMCS_FIELD_TYPE_U32:
5000                 *ret = *((u32 *)p);
5001                 return 1;
5002         case VMCS_FIELD_TYPE_U64:
5003                 *ret = *((u64 *)p);
5004                 return 1;
5005         default:
5006                 return 0; /* can never happen. */
5007         }
5008 }
5009
5010 /*
5011  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5012  * used before) all generate the same failure when it is missing.
5013  */
5014 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5015 {
5016         struct vcpu_vmx *vmx = to_vmx(vcpu);
5017         if (vmx->nested.current_vmptr == -1ull) {
5018                 nested_vmx_failInvalid(vcpu);
5019                 skip_emulated_instruction(vcpu);
5020                 return 0;
5021         }
5022         return 1;
5023 }
5024
5025 static int handle_vmread(struct kvm_vcpu *vcpu)
5026 {
5027         unsigned long field;
5028         u64 field_value;
5029         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5030         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5031         gva_t gva = 0;
5032
5033         if (!nested_vmx_check_permission(vcpu) ||
5034             !nested_vmx_check_vmcs12(vcpu))
5035                 return 1;
5036
5037         /* Decode instruction info and find the field to read */
5038         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5039         /* Read the field, zero-extended to a u64 field_value */
5040         if (!vmcs12_read_any(vcpu, field, &field_value)) {
5041                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5042                 skip_emulated_instruction(vcpu);
5043                 return 1;
5044         }
5045         /*
5046          * Now copy part of this value to register or memory, as requested.
5047          * Note that the number of bits actually copied is 32 or 64 depending
5048          * on the guest's mode (32 or 64 bit), not on the given field's length.
5049          */
5050         if (vmx_instruction_info & (1u << 10)) {
5051                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5052                         field_value);
5053         } else {
5054                 if (get_vmx_mem_address(vcpu, exit_qualification,
5055                                 vmx_instruction_info, &gva))
5056                         return 1;
5057                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5058                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5059                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5060         }
5061
5062         nested_vmx_succeed(vcpu);
5063         skip_emulated_instruction(vcpu);
5064         return 1;
5065 }
5066
5067
5068 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5069 {
5070         unsigned long field;
5071         gva_t gva;
5072         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5073         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5074         char *p;
5075         short offset;
5076         /* The value to write might be 32 or 64 bits, depending on L1's long
5077          * mode, and eventually we need to write that into a field of several
5078          * possible lengths. The code below first zero-extends the value to 64
5079          * bit (field_value), and then copies only the approriate number of
5080          * bits into the vmcs12 field.
5081          */
5082         u64 field_value = 0;
5083         struct x86_exception e;
5084
5085         if (!nested_vmx_check_permission(vcpu) ||
5086             !nested_vmx_check_vmcs12(vcpu))
5087                 return 1;
5088
5089         if (vmx_instruction_info & (1u << 10))
5090                 field_value = kvm_register_read(vcpu,
5091                         (((vmx_instruction_info) >> 3) & 0xf));
5092         else {
5093                 if (get_vmx_mem_address(vcpu, exit_qualification,
5094                                 vmx_instruction_info, &gva))
5095                         return 1;
5096                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5097                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5098                         kvm_inject_page_fault(vcpu, &e);
5099                         return 1;
5100                 }
5101         }
5102
5103
5104         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5105         if (vmcs_field_readonly(field)) {
5106                 nested_vmx_failValid(vcpu,
5107                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5108                 skip_emulated_instruction(vcpu);
5109                 return 1;
5110         }
5111
5112         offset = vmcs_field_to_offset(field);
5113         if (offset < 0) {
5114                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5115                 skip_emulated_instruction(vcpu);
5116                 return 1;
5117         }
5118         p = ((char *) get_vmcs12(vcpu)) + offset;
5119
5120         switch (vmcs_field_type(field)) {
5121         case VMCS_FIELD_TYPE_U16:
5122                 *(u16 *)p = field_value;
5123                 break;
5124         case VMCS_FIELD_TYPE_U32:
5125                 *(u32 *)p = field_value;
5126                 break;
5127         case VMCS_FIELD_TYPE_U64:
5128                 *(u64 *)p = field_value;
5129                 break;
5130         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5131                 *(natural_width *)p = field_value;
5132                 break;
5133         default:
5134                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5135                 skip_emulated_instruction(vcpu);
5136                 return 1;
5137         }
5138
5139         nested_vmx_succeed(vcpu);
5140         skip_emulated_instruction(vcpu);
5141         return 1;
5142 }
5143
5144 /* Emulate the VMPTRLD instruction */
5145 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5146 {
5147         struct vcpu_vmx *vmx = to_vmx(vcpu);
5148         gva_t gva;
5149         gpa_t vmptr;
5150         struct x86_exception e;
5151
5152         if (!nested_vmx_check_permission(vcpu))
5153                 return 1;
5154
5155         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5156                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5157                 return 1;
5158
5159         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5160                                 sizeof(vmptr), &e)) {
5161                 kvm_inject_page_fault(vcpu, &e);
5162                 return 1;
5163         }
5164
5165         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5166                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5167                 skip_emulated_instruction(vcpu);
5168                 return 1;
5169         }
5170
5171         if (vmx->nested.current_vmptr != vmptr) {
5172                 struct vmcs12 *new_vmcs12;
5173                 struct page *page;
5174                 page = nested_get_page(vcpu, vmptr);
5175                 if (page == NULL) {
5176                         nested_vmx_failInvalid(vcpu);
5177                         skip_emulated_instruction(vcpu);
5178                         return 1;
5179                 }
5180                 new_vmcs12 = kmap(page);
5181                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5182                         kunmap(page);
5183                         nested_release_page_clean(page);
5184                         nested_vmx_failValid(vcpu,
5185                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5186                         skip_emulated_instruction(vcpu);
5187                         return 1;
5188                 }
5189                 if (vmx->nested.current_vmptr != -1ull) {
5190                         kunmap(vmx->nested.current_vmcs12_page);
5191                         nested_release_page(vmx->nested.current_vmcs12_page);
5192                 }
5193
5194                 vmx->nested.current_vmptr = vmptr;
5195                 vmx->nested.current_vmcs12 = new_vmcs12;
5196                 vmx->nested.current_vmcs12_page = page;
5197         }
5198
5199         nested_vmx_succeed(vcpu);
5200         skip_emulated_instruction(vcpu);
5201         return 1;
5202 }
5203
5204 /* Emulate the VMPTRST instruction */
5205 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5206 {
5207         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5208         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5209         gva_t vmcs_gva;
5210         struct x86_exception e;
5211
5212         if (!nested_vmx_check_permission(vcpu))
5213                 return 1;
5214
5215         if (get_vmx_mem_address(vcpu, exit_qualification,
5216                         vmx_instruction_info, &vmcs_gva))
5217                 return 1;
5218         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5219         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5220                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
5221                                  sizeof(u64), &e)) {
5222                 kvm_inject_page_fault(vcpu, &e);
5223                 return 1;
5224         }
5225         nested_vmx_succeed(vcpu);
5226         skip_emulated_instruction(vcpu);
5227         return 1;
5228 }
5229
5230 /*
5231  * The exit handlers return 1 if the exit was handled fully and guest execution
5232  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5233  * to be done to userspace and return 0.
5234  */
5235 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5236         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
5237         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5238         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5239         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5240         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5241         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5242         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5243         [EXIT_REASON_CPUID]                   = handle_cpuid,
5244         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5245         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5246         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5247         [EXIT_REASON_HLT]                     = handle_halt,
5248         [EXIT_REASON_INVD]                    = handle_invd,
5249         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5250         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5251         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
5252         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
5253         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
5254         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
5255         [EXIT_REASON_VMREAD]                  = handle_vmread,
5256         [EXIT_REASON_VMRESUME]                = handle_vmresume,
5257         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
5258         [EXIT_REASON_VMOFF]                   = handle_vmoff,
5259         [EXIT_REASON_VMON]                    = handle_vmon,
5260         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5261         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5262         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5263         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5264         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5265         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5266         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5267         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5268         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5269         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
5270         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
5271 };
5272
5273 static const int kvm_vmx_max_exit_handlers =
5274         ARRAY_SIZE(kvm_vmx_exit_handlers);
5275
5276 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5277 {
5278         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5279         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5280 }
5281
5282 /*
5283  * The guest has exited.  See if we can fix it or if we need userspace
5284  * assistance.
5285  */
5286 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5287 {
5288         struct vcpu_vmx *vmx = to_vmx(vcpu);
5289         u32 exit_reason = vmx->exit_reason;
5290         u32 vectoring_info = vmx->idt_vectoring_info;
5291
5292         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5293
5294         /* If guest state is invalid, start emulating */
5295         if (vmx->emulation_required && emulate_invalid_guest_state)
5296                 return handle_invalid_guest_state(vcpu);
5297
5298         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5299                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5300                 vcpu->run->fail_entry.hardware_entry_failure_reason
5301                         = exit_reason;
5302                 return 0;
5303         }
5304
5305         if (unlikely(vmx->fail)) {
5306                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5307                 vcpu->run->fail_entry.hardware_entry_failure_reason
5308                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5309                 return 0;
5310         }
5311
5312         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5313                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5314                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5315                         exit_reason != EXIT_REASON_TASK_SWITCH))
5316                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5317                        "(0x%x) and exit reason is 0x%x\n",
5318                        __func__, vectoring_info, exit_reason);
5319
5320         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
5321                 if (vmx_interrupt_allowed(vcpu)) {
5322                         vmx->soft_vnmi_blocked = 0;
5323                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
5324                            vcpu->arch.nmi_pending) {
5325                         /*
5326                          * This CPU don't support us in finding the end of an
5327                          * NMI-blocked window if the guest runs with IRQs
5328                          * disabled. So we pull the trigger after 1 s of
5329                          * futile waiting, but inform the user about this.
5330                          */
5331                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5332                                "state on VCPU %d after 1 s timeout\n",
5333                                __func__, vcpu->vcpu_id);
5334                         vmx->soft_vnmi_blocked = 0;
5335                 }
5336         }
5337
5338         if (exit_reason < kvm_vmx_max_exit_handlers
5339             && kvm_vmx_exit_handlers[exit_reason])
5340                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5341         else {
5342                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5343                 vcpu->run->hw.hardware_exit_reason = exit_reason;
5344         }
5345         return 0;
5346 }
5347
5348 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5349 {
5350         if (irr == -1 || tpr < irr) {
5351                 vmcs_write32(TPR_THRESHOLD, 0);
5352                 return;
5353         }
5354
5355         vmcs_write32(TPR_THRESHOLD, irr);
5356 }
5357
5358 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
5359 {
5360         u32 exit_intr_info;
5361
5362         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5363               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5364                 return;
5365
5366         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5367         exit_intr_info = vmx->exit_intr_info;
5368
5369         /* Handle machine checks before interrupts are enabled */
5370         if (is_machine_check(exit_intr_info))
5371                 kvm_machine_check();
5372
5373         /* We need to handle NMIs before interrupts are enabled */
5374         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
5375             (exit_intr_info & INTR_INFO_VALID_MASK)) {
5376                 kvm_before_handle_nmi(&vmx->vcpu);
5377                 asm("int $2");
5378                 kvm_after_handle_nmi(&vmx->vcpu);
5379         }
5380 }
5381
5382 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5383 {
5384         u32 exit_intr_info;
5385         bool unblock_nmi;
5386         u8 vector;
5387         bool idtv_info_valid;
5388
5389         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5390
5391         if (cpu_has_virtual_nmis()) {
5392                 if (vmx->nmi_known_unmasked)
5393                         return;
5394                 /*
5395                  * Can't use vmx->exit_intr_info since we're not sure what
5396                  * the exit reason is.
5397                  */
5398                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5399                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5400                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5401                 /*
5402                  * SDM 3: 27.7.1.2 (September 2008)
5403                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
5404                  * a guest IRET fault.
5405                  * SDM 3: 23.2.2 (September 2008)
5406                  * Bit 12 is undefined in any of the following cases:
5407                  *  If the VM exit sets the valid bit in the IDT-vectoring
5408                  *   information field.
5409                  *  If the VM exit is due to a double fault.
5410                  */
5411                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5412                     vector != DF_VECTOR && !idtv_info_valid)
5413                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5414                                       GUEST_INTR_STATE_NMI);
5415                 else
5416                         vmx->nmi_known_unmasked =
5417                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5418                                   & GUEST_INTR_STATE_NMI);
5419         } else if (unlikely(vmx->soft_vnmi_blocked))
5420                 vmx->vnmi_blocked_time +=
5421                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
5422 }
5423
5424 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5425                                       u32 idt_vectoring_info,
5426                                       int instr_len_field,
5427                                       int error_code_field)
5428 {
5429         u8 vector;
5430         int type;
5431         bool idtv_info_valid;
5432
5433         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5434
5435         vmx->vcpu.arch.nmi_injected = false;
5436         kvm_clear_exception_queue(&vmx->vcpu);
5437         kvm_clear_interrupt_queue(&vmx->vcpu);
5438
5439         if (!idtv_info_valid)
5440                 return;
5441
5442         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5443
5444         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
5445         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
5446
5447         switch (type) {
5448         case INTR_TYPE_NMI_INTR:
5449                 vmx->vcpu.arch.nmi_injected = true;
5450                 /*
5451                  * SDM 3: 27.7.1.2 (September 2008)
5452                  * Clear bit "block by NMI" before VM entry if a NMI
5453                  * delivery faulted.
5454                  */
5455                 vmx_set_nmi_mask(&vmx->vcpu, false);
5456                 break;
5457         case INTR_TYPE_SOFT_EXCEPTION:
5458                 vmx->vcpu.arch.event_exit_inst_len =
5459                         vmcs_read32(instr_len_field);
5460                 /* fall through */
5461         case INTR_TYPE_HARD_EXCEPTION:
5462                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
5463                         u32 err = vmcs_read32(error_code_field);
5464                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
5465                 } else
5466                         kvm_queue_exception(&vmx->vcpu, vector);
5467                 break;
5468         case INTR_TYPE_SOFT_INTR:
5469                 vmx->vcpu.arch.event_exit_inst_len =
5470                         vmcs_read32(instr_len_field);
5471                 /* fall through */
5472         case INTR_TYPE_EXT_INTR:
5473                 kvm_queue_interrupt(&vmx->vcpu, vector,
5474                         type == INTR_TYPE_SOFT_INTR);
5475                 break;
5476         default:
5477                 break;
5478         }
5479 }
5480
5481 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
5482 {
5483         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
5484                                   VM_EXIT_INSTRUCTION_LEN,
5485                                   IDT_VECTORING_ERROR_CODE);
5486 }
5487
5488 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
5489 {
5490         __vmx_complete_interrupts(to_vmx(vcpu),
5491                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5492                                   VM_ENTRY_INSTRUCTION_LEN,
5493                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
5494
5495         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
5496 }
5497
5498 #ifdef CONFIG_X86_64
5499 #define R "r"
5500 #define Q "q"
5501 #else
5502 #define R "e"
5503 #define Q "l"
5504 #endif
5505
5506 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
5507 {
5508         struct vcpu_vmx *vmx = to_vmx(vcpu);
5509
5510         /* Record the guest's net vcpu time for enforced NMI injections. */
5511         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
5512                 vmx->entry_time = ktime_get();
5513
5514         /* Don't enter VMX if guest state is invalid, let the exit handler
5515            start emulation until we arrive back to a valid state */
5516         if (vmx->emulation_required && emulate_invalid_guest_state)
5517                 return;
5518
5519         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
5520                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
5521         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
5522                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
5523
5524         /* When single-stepping over STI and MOV SS, we must clear the
5525          * corresponding interruptibility bits in the guest state. Otherwise
5526          * vmentry fails as it then expects bit 14 (BS) in pending debug
5527          * exceptions being set, but that's not correct for the guest debugging
5528          * case. */
5529         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5530                 vmx_set_interrupt_shadow(vcpu, 0);
5531
5532         vmx->__launched = vmx->loaded_vmcs->launched;
5533         asm(
5534                 /* Store host registers */
5535                 "push %%"R"dx; push %%"R"bp;"
5536                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
5537                 "push %%"R"cx \n\t"
5538                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
5539                 "je 1f \n\t"
5540                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
5541                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
5542                 "1: \n\t"
5543                 /* Reload cr2 if changed */
5544                 "mov %c[cr2](%0), %%"R"ax \n\t"
5545                 "mov %%cr2, %%"R"dx \n\t"
5546                 "cmp %%"R"ax, %%"R"dx \n\t"
5547                 "je 2f \n\t"
5548                 "mov %%"R"ax, %%cr2 \n\t"
5549                 "2: \n\t"
5550                 /* Check if vmlaunch of vmresume is needed */
5551                 "cmpl $0, %c[launched](%0) \n\t"
5552                 /* Load guest registers.  Don't clobber flags. */
5553                 "mov %c[rax](%0), %%"R"ax \n\t"
5554                 "mov %c[rbx](%0), %%"R"bx \n\t"
5555                 "mov %c[rdx](%0), %%"R"dx \n\t"
5556                 "mov %c[rsi](%0), %%"R"si \n\t"
5557                 "mov %c[rdi](%0), %%"R"di \n\t"
5558                 "mov %c[rbp](%0), %%"R"bp \n\t"
5559 #ifdef CONFIG_X86_64
5560                 "mov %c[r8](%0),  %%r8  \n\t"
5561                 "mov %c[r9](%0),  %%r9  \n\t"
5562                 "mov %c[r10](%0), %%r10 \n\t"
5563                 "mov %c[r11](%0), %%r11 \n\t"
5564                 "mov %c[r12](%0), %%r12 \n\t"
5565                 "mov %c[r13](%0), %%r13 \n\t"
5566                 "mov %c[r14](%0), %%r14 \n\t"
5567                 "mov %c[r15](%0), %%r15 \n\t"
5568 #endif
5569                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
5570
5571                 /* Enter guest mode */
5572                 "jne .Llaunched \n\t"
5573                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
5574                 "jmp .Lkvm_vmx_return \n\t"
5575                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
5576                 ".Lkvm_vmx_return: "
5577                 /* Save guest registers, load host registers, keep flags */
5578                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
5579                 "pop %0 \n\t"
5580                 "mov %%"R"ax, %c[rax](%0) \n\t"
5581                 "mov %%"R"bx, %c[rbx](%0) \n\t"
5582                 "pop"Q" %c[rcx](%0) \n\t"
5583                 "mov %%"R"dx, %c[rdx](%0) \n\t"
5584                 "mov %%"R"si, %c[rsi](%0) \n\t"
5585                 "mov %%"R"di, %c[rdi](%0) \n\t"
5586                 "mov %%"R"bp, %c[rbp](%0) \n\t"
5587 #ifdef CONFIG_X86_64
5588                 "mov %%r8,  %c[r8](%0) \n\t"
5589                 "mov %%r9,  %c[r9](%0) \n\t"
5590                 "mov %%r10, %c[r10](%0) \n\t"
5591                 "mov %%r11, %c[r11](%0) \n\t"
5592                 "mov %%r12, %c[r12](%0) \n\t"
5593                 "mov %%r13, %c[r13](%0) \n\t"
5594                 "mov %%r14, %c[r14](%0) \n\t"
5595                 "mov %%r15, %c[r15](%0) \n\t"
5596 #endif
5597                 "mov %%cr2, %%"R"ax   \n\t"
5598                 "mov %%"R"ax, %c[cr2](%0) \n\t"
5599
5600                 "pop  %%"R"bp; pop  %%"R"dx \n\t"
5601                 "setbe %c[fail](%0) \n\t"
5602               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
5603                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
5604                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
5605                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
5606                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
5607                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
5608                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
5609                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
5610                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
5611                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
5612                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
5613 #ifdef CONFIG_X86_64
5614                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
5615                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
5616                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
5617                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
5618                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
5619                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
5620                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
5621                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
5622 #endif
5623                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
5624                 [wordsize]"i"(sizeof(ulong))
5625               : "cc", "memory"
5626                 , R"ax", R"bx", R"di", R"si"
5627 #ifdef CONFIG_X86_64
5628                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5629 #endif
5630               );
5631
5632         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
5633                                   | (1 << VCPU_EXREG_RFLAGS)
5634                                   | (1 << VCPU_EXREG_CPL)
5635                                   | (1 << VCPU_EXREG_PDPTR)
5636                                   | (1 << VCPU_EXREG_SEGMENTS)
5637                                   | (1 << VCPU_EXREG_CR3));
5638         vcpu->arch.regs_dirty = 0;
5639
5640         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
5641
5642         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
5643         vmx->loaded_vmcs->launched = 1;
5644
5645         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
5646
5647         vmx_complete_atomic_exit(vmx);
5648         vmx_recover_nmi_blocking(vmx);
5649         vmx_complete_interrupts(vmx);
5650 }
5651
5652 #undef R
5653 #undef Q
5654
5655 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
5656 {
5657         struct vcpu_vmx *vmx = to_vmx(vcpu);
5658
5659         free_vpid(vmx);
5660         free_nested(vmx);
5661         free_loaded_vmcs(vmx->loaded_vmcs);
5662         kfree(vmx->guest_msrs);
5663         kvm_vcpu_uninit(vcpu);
5664         kmem_cache_free(kvm_vcpu_cache, vmx);
5665 }
5666
5667 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
5668 {
5669         int err;
5670         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
5671         int cpu;
5672
5673         if (!vmx)
5674                 return ERR_PTR(-ENOMEM);
5675
5676         allocate_vpid(vmx);
5677
5678         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
5679         if (err)
5680                 goto free_vcpu;
5681
5682         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
5683         err = -ENOMEM;
5684         if (!vmx->guest_msrs) {
5685                 goto uninit_vcpu;
5686         }
5687
5688         vmx->loaded_vmcs = &vmx->vmcs01;
5689         vmx->loaded_vmcs->vmcs = alloc_vmcs();
5690         if (!vmx->loaded_vmcs->vmcs)
5691                 goto free_msrs;
5692         if (!vmm_exclusive)
5693                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
5694         loaded_vmcs_init(vmx->loaded_vmcs);
5695         if (!vmm_exclusive)
5696                 kvm_cpu_vmxoff();
5697
5698         cpu = get_cpu();
5699         vmx_vcpu_load(&vmx->vcpu, cpu);
5700         vmx->vcpu.cpu = cpu;
5701         err = vmx_vcpu_setup(vmx);
5702         vmx_vcpu_put(&vmx->vcpu);
5703         put_cpu();
5704         if (err)
5705                 goto free_vmcs;
5706         if (vm_need_virtualize_apic_accesses(kvm))
5707                 err = alloc_apic_access_page(kvm);
5708                 if (err)
5709                         goto free_vmcs;
5710
5711         if (enable_ept) {
5712                 if (!kvm->arch.ept_identity_map_addr)
5713                         kvm->arch.ept_identity_map_addr =
5714                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
5715                 err = -ENOMEM;
5716                 if (alloc_identity_pagetable(kvm) != 0)
5717                         goto free_vmcs;
5718                 if (!init_rmode_identity_map(kvm))
5719                         goto free_vmcs;
5720         }
5721
5722         vmx->nested.current_vmptr = -1ull;
5723         vmx->nested.current_vmcs12 = NULL;
5724
5725         return &vmx->vcpu;
5726
5727 free_vmcs:
5728         free_vmcs(vmx->loaded_vmcs->vmcs);
5729 free_msrs:
5730         kfree(vmx->guest_msrs);
5731 uninit_vcpu:
5732         kvm_vcpu_uninit(&vmx->vcpu);
5733 free_vcpu:
5734         free_vpid(vmx);
5735         kmem_cache_free(kvm_vcpu_cache, vmx);
5736         return ERR_PTR(err);
5737 }
5738
5739 static void __init vmx_check_processor_compat(void *rtn)
5740 {
5741         struct vmcs_config vmcs_conf;
5742
5743         *(int *)rtn = 0;
5744         if (setup_vmcs_config(&vmcs_conf) < 0)
5745                 *(int *)rtn = -EIO;
5746         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
5747                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
5748                                 smp_processor_id());
5749                 *(int *)rtn = -EIO;
5750         }
5751 }
5752
5753 static int get_ept_level(void)
5754 {
5755         return VMX_EPT_DEFAULT_GAW + 1;
5756 }
5757
5758 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5759 {
5760         u64 ret;
5761
5762         /* For VT-d and EPT combination
5763          * 1. MMIO: always map as UC
5764          * 2. EPT with VT-d:
5765          *   a. VT-d without snooping control feature: can't guarantee the
5766          *      result, try to trust guest.
5767          *   b. VT-d with snooping control feature: snooping control feature of
5768          *      VT-d engine can guarantee the cache correctness. Just set it
5769          *      to WB to keep consistent with host. So the same as item 3.
5770          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
5771          *    consistent with host MTRR
5772          */
5773         if (is_mmio)
5774                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
5775         else if (vcpu->kvm->arch.iommu_domain &&
5776                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
5777                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
5778                       VMX_EPT_MT_EPTE_SHIFT;
5779         else
5780                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
5781                         | VMX_EPT_IPAT_BIT;
5782
5783         return ret;
5784 }
5785
5786 #define _ER(x) { EXIT_REASON_##x, #x }
5787
5788 static const struct trace_print_flags vmx_exit_reasons_str[] = {
5789         _ER(EXCEPTION_NMI),
5790         _ER(EXTERNAL_INTERRUPT),
5791         _ER(TRIPLE_FAULT),
5792         _ER(PENDING_INTERRUPT),
5793         _ER(NMI_WINDOW),
5794         _ER(TASK_SWITCH),
5795         _ER(CPUID),
5796         _ER(HLT),
5797         _ER(INVLPG),
5798         _ER(RDPMC),
5799         _ER(RDTSC),
5800         _ER(VMCALL),
5801         _ER(VMCLEAR),
5802         _ER(VMLAUNCH),
5803         _ER(VMPTRLD),
5804         _ER(VMPTRST),
5805         _ER(VMREAD),
5806         _ER(VMRESUME),
5807         _ER(VMWRITE),
5808         _ER(VMOFF),
5809         _ER(VMON),
5810         _ER(CR_ACCESS),
5811         _ER(DR_ACCESS),
5812         _ER(IO_INSTRUCTION),
5813         _ER(MSR_READ),
5814         _ER(MSR_WRITE),
5815         _ER(MWAIT_INSTRUCTION),
5816         _ER(MONITOR_INSTRUCTION),
5817         _ER(PAUSE_INSTRUCTION),
5818         _ER(MCE_DURING_VMENTRY),
5819         _ER(TPR_BELOW_THRESHOLD),
5820         _ER(APIC_ACCESS),
5821         _ER(EPT_VIOLATION),
5822         _ER(EPT_MISCONFIG),
5823         _ER(WBINVD),
5824         { -1, NULL }
5825 };
5826
5827 #undef _ER
5828
5829 static int vmx_get_lpage_level(void)
5830 {
5831         if (enable_ept && !cpu_has_vmx_ept_1g_page())
5832                 return PT_DIRECTORY_LEVEL;
5833         else
5834                 /* For shadow and EPT supported 1GB page */
5835                 return PT_PDPE_LEVEL;
5836 }
5837
5838 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
5839 {
5840         struct kvm_cpuid_entry2 *best;
5841         struct vcpu_vmx *vmx = to_vmx(vcpu);
5842         u32 exec_control;
5843
5844         vmx->rdtscp_enabled = false;
5845         if (vmx_rdtscp_supported()) {
5846                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5847                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
5848                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
5849                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
5850                                 vmx->rdtscp_enabled = true;
5851                         else {
5852                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
5853                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5854                                                 exec_control);
5855                         }
5856                 }
5857         }
5858 }
5859
5860 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5861 {
5862 }
5863
5864 /*
5865  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
5866  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
5867  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
5868  * guest in a way that will both be appropriate to L1's requests, and our
5869  * needs. In addition to modifying the active vmcs (which is vmcs02), this
5870  * function also has additional necessary side-effects, like setting various
5871  * vcpu->arch fields.
5872  */
5873 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
5874 {
5875         struct vcpu_vmx *vmx = to_vmx(vcpu);
5876         u32 exec_control;
5877
5878         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
5879         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
5880         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
5881         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
5882         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
5883         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
5884         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
5885         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
5886         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
5887         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
5888         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
5889         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
5890         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
5891         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
5892         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
5893         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
5894         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
5895         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
5896         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
5897         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
5898         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
5899         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
5900         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
5901         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
5902         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
5903         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
5904         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
5905         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
5906         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
5907         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
5908         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
5909         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
5910         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
5911         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
5912         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
5913         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
5914
5915         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
5916         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5917                 vmcs12->vm_entry_intr_info_field);
5918         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
5919                 vmcs12->vm_entry_exception_error_code);
5920         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5921                 vmcs12->vm_entry_instruction_len);
5922         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
5923                 vmcs12->guest_interruptibility_info);
5924         vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
5925         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
5926         vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
5927         vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
5928         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
5929                 vmcs12->guest_pending_dbg_exceptions);
5930         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
5931         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
5932
5933         vmcs_write64(VMCS_LINK_POINTER, -1ull);
5934
5935         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
5936                 (vmcs_config.pin_based_exec_ctrl |
5937                  vmcs12->pin_based_vm_exec_control));
5938
5939         /*
5940          * Whether page-faults are trapped is determined by a combination of
5941          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
5942          * If enable_ept, L0 doesn't care about page faults and we should
5943          * set all of these to L1's desires. However, if !enable_ept, L0 does
5944          * care about (at least some) page faults, and because it is not easy
5945          * (if at all possible?) to merge L0 and L1's desires, we simply ask
5946          * to exit on each and every L2 page fault. This is done by setting
5947          * MASK=MATCH=0 and (see below) EB.PF=1.
5948          * Note that below we don't need special code to set EB.PF beyond the
5949          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
5950          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
5951          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
5952          *
5953          * A problem with this approach (when !enable_ept) is that L1 may be
5954          * injected with more page faults than it asked for. This could have
5955          * caused problems, but in practice existing hypervisors don't care.
5956          * To fix this, we will need to emulate the PFEC checking (on the L1
5957          * page tables), using walk_addr(), when injecting PFs to L1.
5958          */
5959         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
5960                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
5961         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
5962                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
5963
5964         if (cpu_has_secondary_exec_ctrls()) {
5965                 u32 exec_control = vmx_secondary_exec_control(vmx);
5966                 if (!vmx->rdtscp_enabled)
5967                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
5968                 /* Take the following fields only from vmcs12 */
5969                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5970                 if (nested_cpu_has(vmcs12,
5971                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
5972                         exec_control |= vmcs12->secondary_vm_exec_control;
5973
5974                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
5975                         /*
5976                          * Translate L1 physical address to host physical
5977                          * address for vmcs02. Keep the page pinned, so this
5978                          * physical address remains valid. We keep a reference
5979                          * to it so we can release it later.
5980                          */
5981                         if (vmx->nested.apic_access_page) /* shouldn't happen */
5982                                 nested_release_page(vmx->nested.apic_access_page);
5983                         vmx->nested.apic_access_page =
5984                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
5985                         /*
5986                          * If translation failed, no matter: This feature asks
5987                          * to exit when accessing the given address, and if it
5988                          * can never be accessed, this feature won't do
5989                          * anything anyway.
5990                          */
5991                         if (!vmx->nested.apic_access_page)
5992                                 exec_control &=
5993                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5994                         else
5995                                 vmcs_write64(APIC_ACCESS_ADDR,
5996                                   page_to_phys(vmx->nested.apic_access_page));
5997                 }
5998
5999                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6000         }
6001
6002
6003         /*
6004          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6005          * Some constant fields are set here by vmx_set_constant_host_state().
6006          * Other fields are different per CPU, and will be set later when
6007          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6008          */
6009         vmx_set_constant_host_state();
6010
6011         /*
6012          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6013          * entry, but only if the current (host) sp changed from the value
6014          * we wrote last (vmx->host_rsp). This cache is no longer relevant
6015          * if we switch vmcs, and rather than hold a separate cache per vmcs,
6016          * here we just force the write to happen on entry.
6017          */
6018         vmx->host_rsp = 0;
6019
6020         exec_control = vmx_exec_control(vmx); /* L0's desires */
6021         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6022         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6023         exec_control &= ~CPU_BASED_TPR_SHADOW;
6024         exec_control |= vmcs12->cpu_based_vm_exec_control;
6025         /*
6026          * Merging of IO and MSR bitmaps not currently supported.
6027          * Rather, exit every time.
6028          */
6029         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6030         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6031         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6032
6033         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6034
6035         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6036          * bitwise-or of what L1 wants to trap for L2, and what we want to
6037          * trap. Note that CR0.TS also needs updating - we do this later.
6038          */
6039         update_exception_bitmap(vcpu);
6040         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6041         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6042
6043         /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6044         vmcs_write32(VM_EXIT_CONTROLS,
6045                 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6046         vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6047                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6048
6049         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6050                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6051         else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6052                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6053
6054
6055         set_cr4_guest_host_mask(vmx);
6056
6057         vmcs_write64(TSC_OFFSET,
6058                 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6059
6060         if (enable_vpid) {
6061                 /*
6062                  * Trivially support vpid by letting L2s share their parent
6063                  * L1's vpid. TODO: move to a more elaborate solution, giving
6064                  * each L2 its own vpid and exposing the vpid feature to L1.
6065                  */
6066                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6067                 vmx_flush_tlb(vcpu);
6068         }
6069
6070         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6071                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6072         if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6073                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6074         else
6075                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6076         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6077         vmx_set_efer(vcpu, vcpu->arch.efer);
6078
6079         /*
6080          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6081          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6082          * The CR0_READ_SHADOW is what L2 should have expected to read given
6083          * the specifications by L1; It's not enough to take
6084          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6085          * have more bits than L1 expected.
6086          */
6087         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6088         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6089
6090         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6091         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6092
6093         /* shadow page tables on either EPT or shadow page tables */
6094         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6095         kvm_mmu_reset_context(vcpu);
6096
6097         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6098         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6099 }
6100
6101 /*
6102  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6103  * for running an L2 nested guest.
6104  */
6105 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6106 {
6107         struct vmcs12 *vmcs12;
6108         struct vcpu_vmx *vmx = to_vmx(vcpu);
6109         int cpu;
6110         struct loaded_vmcs *vmcs02;
6111
6112         if (!nested_vmx_check_permission(vcpu) ||
6113             !nested_vmx_check_vmcs12(vcpu))
6114                 return 1;
6115
6116         skip_emulated_instruction(vcpu);
6117         vmcs12 = get_vmcs12(vcpu);
6118
6119         vmcs02 = nested_get_current_vmcs02(vmx);
6120         if (!vmcs02)
6121                 return -ENOMEM;
6122
6123         enter_guest_mode(vcpu);
6124
6125         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6126
6127         cpu = get_cpu();
6128         vmx->loaded_vmcs = vmcs02;
6129         vmx_vcpu_put(vcpu);
6130         vmx_vcpu_load(vcpu, cpu);
6131         vcpu->cpu = cpu;
6132         put_cpu();
6133
6134         vmcs12->launch_state = 1;
6135
6136         prepare_vmcs02(vcpu, vmcs12);
6137
6138         /*
6139          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6140          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6141          * returned as far as L1 is concerned. It will only return (and set
6142          * the success flag) when L2 exits (see nested_vmx_vmexit()).
6143          */
6144         return 1;
6145 }
6146
6147 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
6148                                struct x86_instruction_info *info,
6149                                enum x86_intercept_stage stage)
6150 {
6151         return X86EMUL_CONTINUE;
6152 }
6153
6154 static struct kvm_x86_ops vmx_x86_ops = {
6155         .cpu_has_kvm_support = cpu_has_kvm_support,
6156         .disabled_by_bios = vmx_disabled_by_bios,
6157         .hardware_setup = hardware_setup,
6158         .hardware_unsetup = hardware_unsetup,
6159         .check_processor_compatibility = vmx_check_processor_compat,
6160         .hardware_enable = hardware_enable,
6161         .hardware_disable = hardware_disable,
6162         .cpu_has_accelerated_tpr = report_flexpriority,
6163
6164         .vcpu_create = vmx_create_vcpu,
6165         .vcpu_free = vmx_free_vcpu,
6166         .vcpu_reset = vmx_vcpu_reset,
6167
6168         .prepare_guest_switch = vmx_save_host_state,
6169         .vcpu_load = vmx_vcpu_load,
6170         .vcpu_put = vmx_vcpu_put,
6171
6172         .set_guest_debug = set_guest_debug,
6173         .get_msr = vmx_get_msr,
6174         .set_msr = vmx_set_msr,
6175         .get_segment_base = vmx_get_segment_base,
6176         .get_segment = vmx_get_segment,
6177         .set_segment = vmx_set_segment,
6178         .get_cpl = vmx_get_cpl,
6179         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
6180         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
6181         .decache_cr3 = vmx_decache_cr3,
6182         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6183         .set_cr0 = vmx_set_cr0,
6184         .set_cr3 = vmx_set_cr3,
6185         .set_cr4 = vmx_set_cr4,
6186         .set_efer = vmx_set_efer,
6187         .get_idt = vmx_get_idt,
6188         .set_idt = vmx_set_idt,
6189         .get_gdt = vmx_get_gdt,
6190         .set_gdt = vmx_set_gdt,
6191         .set_dr7 = vmx_set_dr7,
6192         .cache_reg = vmx_cache_reg,
6193         .get_rflags = vmx_get_rflags,
6194         .set_rflags = vmx_set_rflags,
6195         .fpu_activate = vmx_fpu_activate,
6196         .fpu_deactivate = vmx_fpu_deactivate,
6197
6198         .tlb_flush = vmx_flush_tlb,
6199
6200         .run = vmx_vcpu_run,
6201         .handle_exit = vmx_handle_exit,
6202         .skip_emulated_instruction = skip_emulated_instruction,
6203         .set_interrupt_shadow = vmx_set_interrupt_shadow,
6204         .get_interrupt_shadow = vmx_get_interrupt_shadow,
6205         .patch_hypercall = vmx_patch_hypercall,
6206         .set_irq = vmx_inject_irq,
6207         .set_nmi = vmx_inject_nmi,
6208         .queue_exception = vmx_queue_exception,
6209         .cancel_injection = vmx_cancel_injection,
6210         .interrupt_allowed = vmx_interrupt_allowed,
6211         .nmi_allowed = vmx_nmi_allowed,
6212         .get_nmi_mask = vmx_get_nmi_mask,
6213         .set_nmi_mask = vmx_set_nmi_mask,
6214         .enable_nmi_window = enable_nmi_window,
6215         .enable_irq_window = enable_irq_window,
6216         .update_cr8_intercept = update_cr8_intercept,
6217
6218         .set_tss_addr = vmx_set_tss_addr,
6219         .get_tdp_level = get_ept_level,
6220         .get_mt_mask = vmx_get_mt_mask,
6221
6222         .get_exit_info = vmx_get_exit_info,
6223         .exit_reasons_str = vmx_exit_reasons_str,
6224
6225         .get_lpage_level = vmx_get_lpage_level,
6226
6227         .cpuid_update = vmx_cpuid_update,
6228
6229         .rdtscp_supported = vmx_rdtscp_supported,
6230
6231         .set_supported_cpuid = vmx_set_supported_cpuid,
6232
6233         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
6234
6235         .set_tsc_khz = vmx_set_tsc_khz,
6236         .write_tsc_offset = vmx_write_tsc_offset,
6237         .adjust_tsc_offset = vmx_adjust_tsc_offset,
6238         .compute_tsc_offset = vmx_compute_tsc_offset,
6239
6240         .set_tdp_cr3 = vmx_set_cr3,
6241
6242         .check_intercept = vmx_check_intercept,
6243 };
6244
6245 static int __init vmx_init(void)
6246 {
6247         int r, i;
6248
6249         rdmsrl_safe(MSR_EFER, &host_efer);
6250
6251         for (i = 0; i < NR_VMX_MSR; ++i)
6252                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6253
6254         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6255         if (!vmx_io_bitmap_a)
6256                 return -ENOMEM;
6257
6258         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6259         if (!vmx_io_bitmap_b) {
6260                 r = -ENOMEM;
6261                 goto out;
6262         }
6263
6264         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6265         if (!vmx_msr_bitmap_legacy) {
6266                 r = -ENOMEM;
6267                 goto out1;
6268         }
6269
6270         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6271         if (!vmx_msr_bitmap_longmode) {
6272                 r = -ENOMEM;
6273                 goto out2;
6274         }
6275
6276         /*
6277          * Allow direct access to the PC debug port (it is often used for I/O
6278          * delays, but the vmexits simply slow things down).
6279          */
6280         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6281         clear_bit(0x80, vmx_io_bitmap_a);
6282
6283         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6284
6285         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6286         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6287
6288         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6289
6290         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
6291                      __alignof__(struct vcpu_vmx), THIS_MODULE);
6292         if (r)
6293                 goto out3;
6294
6295         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6296         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6297         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6298         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6299         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6300         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6301
6302         if (enable_ept) {
6303                 bypass_guest_pf = 0;
6304                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
6305                                 VMX_EPT_EXECUTABLE_MASK);
6306                 kvm_enable_tdp();
6307         } else
6308                 kvm_disable_tdp();
6309
6310         if (bypass_guest_pf)
6311                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
6312
6313         return 0;
6314
6315 out3:
6316         free_page((unsigned long)vmx_msr_bitmap_longmode);
6317 out2:
6318         free_page((unsigned long)vmx_msr_bitmap_legacy);
6319 out1:
6320         free_page((unsigned long)vmx_io_bitmap_b);
6321 out:
6322         free_page((unsigned long)vmx_io_bitmap_a);
6323         return r;
6324 }
6325
6326 static void __exit vmx_exit(void)
6327 {
6328         free_page((unsigned long)vmx_msr_bitmap_legacy);
6329         free_page((unsigned long)vmx_msr_bitmap_longmode);
6330         free_page((unsigned long)vmx_io_bitmap_b);
6331         free_page((unsigned long)vmx_io_bitmap_a);
6332
6333         kvm_exit();
6334 }
6335
6336 module_init(vmx_init)
6337 module_exit(vmx_exit)