arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affilates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/kvm_host.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31 #include <linux/tboot.h>
  32 #include "kvm_cache_regs.h"
  33 #include "x86.h"
  34
  35 #include <asm/io.h>
  36 #include <asm/desc.h>
  37 #include <asm/vmx.h>
  38 #include <asm/virtext.h>
  39 #include <asm/mce.h>
  40 #include <asm/i387.h>
  41 #include <asm/xcr.h>
  42
  43 #include "trace.h"
  44
  45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  46
  47 MODULE_AUTHOR("Qumranet");
  48 MODULE_LICENSE("GPL");
  49
  50 static int __read_mostly bypass_guest_pf = 1;
  51 module_param(bypass_guest_pf, bool, S_IRUGO);
  52
  53 static int __read_mostly enable_vpid = 1;
  54 module_param_named(vpid, enable_vpid, bool, 0444);
  55
  56 static int __read_mostly flexpriority_enabled = 1;
  57 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  58
  59 static int __read_mostly enable_ept = 1;
  60 module_param_named(ept, enable_ept, bool, S_IRUGO);
  61
  62 static int __read_mostly enable_unrestricted_guest = 1;
  63 module_param_named(unrestricted_guest,
  64                         enable_unrestricted_guest, bool, S_IRUGO);
  65
  66 static int __read_mostly emulate_invalid_guest_state = 0;
  67 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  68
  69 static int __read_mostly vmm_exclusive = 1;
  70 module_param(vmm_exclusive, bool, S_IRUGO);
  71
  72 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  73         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  74 #define KVM_GUEST_CR0_MASK                                              \
  75         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  76 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  77         (X86_CR0_WP | X86_CR0_NE)
  78 #define KVM_VM_CR0_ALWAYS_ON                                            \
  79         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  80 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  81         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  82          | X86_CR4_OSXMMEXCPT)
  83
  84 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  85 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  86
  87 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
  88
  89 /*
  90  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
  91  * ple_gap:    upper bound on the amount of time between two successive
  92  *             executions of PAUSE in a loop. Also indicate if ple enabled.
  93  *             According to test, this time is usually small than 41 cycles.
  94  * ple_window: upper bound on the amount of time a guest is allowed to execute
  95  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
  96  *             less than 2^12 cycles
  97  * Time is measured based on a counter that runs at the same rate as the TSC,
  98  * refer SDM volume 3b section 21.6.13 & 22.1.3.
  99  */
 100 #define KVM_VMX_DEFAULT_PLE_GAP    41
 101 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 102 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 103 module_param(ple_gap, int, S_IRUGO);
 104
 105 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 106 module_param(ple_window, int, S_IRUGO);
 107
 108 #define NR_AUTOLOAD_MSRS 1
 109
 110 struct vmcs {
 111         u32 revision_id;
 112         u32 abort;
 113         char data[0];
 114 };
 115
 116 struct shared_msr_entry {
 117         unsigned index;
 118         u64 data;
 119         u64 mask;
 120 };
 121
 122 struct vcpu_vmx {
 123         struct kvm_vcpu       vcpu;
 124         struct list_head      local_vcpus_link;
 125         unsigned long         host_rsp;
 126         int                   launched;
 127         u8                    fail;
 128         u32                   idt_vectoring_info;
 129         struct shared_msr_entry *guest_msrs;
 130         int                   nmsrs;
 131         int                   save_nmsrs;
 132 #ifdef CONFIG_X86_64
 133         u64                   msr_host_kernel_gs_base;
 134         u64                   msr_guest_kernel_gs_base;
 135 #endif
 136         struct vmcs          *vmcs;
 137         struct msr_autoload {
 138                 unsigned nr;
 139                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 140                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 141         } msr_autoload;
 142         struct {
 143                 int           loaded;
 144                 u16           fs_sel, gs_sel, ldt_sel;
 145                 int           gs_ldt_reload_needed;
 146                 int           fs_reload_needed;
 147         } host_state;
 148         struct {
 149                 int vm86_active;
 150                 ulong save_rflags;
 151                 struct kvm_save_segment {
 152                         u16 selector;
 153                         unsigned long base;
 154                         u32 limit;
 155                         u32 ar;
 156                 } tr, es, ds, fs, gs;
 157                 struct {
 158                         bool pending;
 159                         u8 vector;
 160                         unsigned rip;
 161                 } irq;
 162         } rmode;
 163         int vpid;
 164         bool emulation_required;
 165
 166         /* Support for vnmi-less CPUs */
 167         int soft_vnmi_blocked;
 168         ktime_t entry_time;
 169         s64 vnmi_blocked_time;
 170         u32 exit_reason;
 171
 172         bool rdtscp_enabled;
 173 };
 174
 175 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 176 {
 177         return container_of(vcpu, struct vcpu_vmx, vcpu);
 178 }
 179
 180 static int init_rmode(struct kvm *kvm);
 181 static u64 construct_eptp(unsigned long root_hpa);
 182 static void kvm_cpu_vmxon(u64 addr);
 183 static void kvm_cpu_vmxoff(void);
 184
 185 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 186 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 187 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 188 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 189
 190 static unsigned long *vmx_io_bitmap_a;
 191 static unsigned long *vmx_io_bitmap_b;
 192 static unsigned long *vmx_msr_bitmap_legacy;
 193 static unsigned long *vmx_msr_bitmap_longmode;
 194
 195 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 196 static DEFINE_SPINLOCK(vmx_vpid_lock);
 197
 198 static struct vmcs_config {
 199         int size;
 200         int order;
 201         u32 revision_id;
 202         u32 pin_based_exec_ctrl;
 203         u32 cpu_based_exec_ctrl;
 204         u32 cpu_based_2nd_exec_ctrl;
 205         u32 vmexit_ctrl;
 206         u32 vmentry_ctrl;
 207 } vmcs_config;
 208
 209 static struct vmx_capability {
 210         u32 ept;
 211         u32 vpid;
 212 } vmx_capability;
 213
 214 #define VMX_SEGMENT_FIELD(seg)                                  \
 215         [VCPU_SREG_##seg] = {                                   \
 216                 .selector = GUEST_##seg##_SELECTOR,             \
 217                 .base = GUEST_##seg##_BASE,                     \
 218                 .limit = GUEST_##seg##_LIMIT,                   \
 219                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 220         }
 221
 222 static struct kvm_vmx_segment_field {
 223         unsigned selector;
 224         unsigned base;
 225         unsigned limit;
 226         unsigned ar_bytes;
 227 } kvm_vmx_segment_fields[] = {
 228         VMX_SEGMENT_FIELD(CS),
 229         VMX_SEGMENT_FIELD(DS),
 230         VMX_SEGMENT_FIELD(ES),
 231         VMX_SEGMENT_FIELD(FS),
 232         VMX_SEGMENT_FIELD(GS),
 233         VMX_SEGMENT_FIELD(SS),
 234         VMX_SEGMENT_FIELD(TR),
 235         VMX_SEGMENT_FIELD(LDTR),
 236 };
 237
 238 static u64 host_efer;
 239
 240 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 241
 242 /*
 243  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 244  * away by decrementing the array size.
 245  */
 246 static const u32 vmx_msr_index[] = {
 247 #ifdef CONFIG_X86_64
 248         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 249 #endif
 250         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 251 };
 252 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 253
 254 static inline bool is_page_fault(u32 intr_info)
 255 {
 256         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 257                              INTR_INFO_VALID_MASK)) ==
 258                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 259 }
 260
 261 static inline bool is_no_device(u32 intr_info)
 262 {
 263         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 264                              INTR_INFO_VALID_MASK)) ==
 265                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 266 }
 267
 268 static inline bool is_invalid_opcode(u32 intr_info)
 269 {
 270         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 271                              INTR_INFO_VALID_MASK)) ==
 272                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 273 }
 274
 275 static inline bool is_external_interrupt(u32 intr_info)
 276 {
 277         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 278                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 279 }
 280
 281 static inline bool is_machine_check(u32 intr_info)
 282 {
 283         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 284                              INTR_INFO_VALID_MASK)) ==
 285                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 286 }
 287
 288 static inline bool cpu_has_vmx_msr_bitmap(void)
 289 {
 290         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 291 }
 292
 293 static inline bool cpu_has_vmx_tpr_shadow(void)
 294 {
 295         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 296 }
 297
 298 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 299 {
 300         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 301 }
 302
 303 static inline bool cpu_has_secondary_exec_ctrls(void)
 304 {
 305         return vmcs_config.cpu_based_exec_ctrl &
 306                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 307 }
 308
 309 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 310 {
 311         return vmcs_config.cpu_based_2nd_exec_ctrl &
 312                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 313 }
 314
 315 static inline bool cpu_has_vmx_flexpriority(void)
 316 {
 317         return cpu_has_vmx_tpr_shadow() &&
 318                 cpu_has_vmx_virtualize_apic_accesses();
 319 }
 320
 321 static inline bool cpu_has_vmx_ept_execute_only(void)
 322 {
 323         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 324 }
 325
 326 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 327 {
 328         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 329 }
 330
 331 static inline bool cpu_has_vmx_eptp_writeback(void)
 332 {
 333         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 334 }
 335
 336 static inline bool cpu_has_vmx_ept_2m_page(void)
 337 {
 338         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 339 }
 340
 341 static inline bool cpu_has_vmx_ept_1g_page(void)
 342 {
 343         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 344 }
 345
 346 static inline bool cpu_has_vmx_ept_4levels(void)
 347 {
 348         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 349 }
 350
 351 static inline bool cpu_has_vmx_invept_individual_addr(void)
 352 {
 353         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 354 }
 355
 356 static inline bool cpu_has_vmx_invept_context(void)
 357 {
 358         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 359 }
 360
 361 static inline bool cpu_has_vmx_invept_global(void)
 362 {
 363         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 364 }
 365
 366 static inline bool cpu_has_vmx_invvpid_single(void)
 367 {
 368         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 369 }
 370
 371 static inline bool cpu_has_vmx_invvpid_global(void)
 372 {
 373         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 374 }
 375
 376 static inline bool cpu_has_vmx_ept(void)
 377 {
 378         return vmcs_config.cpu_based_2nd_exec_ctrl &
 379                 SECONDARY_EXEC_ENABLE_EPT;
 380 }
 381
 382 static inline bool cpu_has_vmx_unrestricted_guest(void)
 383 {
 384         return vmcs_config.cpu_based_2nd_exec_ctrl &
 385                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 386 }
 387
 388 static inline bool cpu_has_vmx_ple(void)
 389 {
 390         return vmcs_config.cpu_based_2nd_exec_ctrl &
 391                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 392 }
 393
 394 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 395 {
 396         return flexpriority_enabled && irqchip_in_kernel(kvm);
 397 }
 398
 399 static inline bool cpu_has_vmx_vpid(void)
 400 {
 401         return vmcs_config.cpu_based_2nd_exec_ctrl &
 402                 SECONDARY_EXEC_ENABLE_VPID;
 403 }
 404
 405 static inline bool cpu_has_vmx_rdtscp(void)
 406 {
 407         return vmcs_config.cpu_based_2nd_exec_ctrl &
 408                 SECONDARY_EXEC_RDTSCP;
 409 }
 410
 411 static inline bool cpu_has_virtual_nmis(void)
 412 {
 413         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 414 }
 415
 416 static inline bool cpu_has_vmx_wbinvd_exit(void)
 417 {
 418         return vmcs_config.cpu_based_2nd_exec_ctrl &
 419                 SECONDARY_EXEC_WBINVD_EXITING;
 420 }
 421
 422 static inline bool report_flexpriority(void)
 423 {
 424         return flexpriority_enabled;
 425 }
 426
 427 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 428 {
 429         int i;
 430
 431         for (i = 0; i < vmx->nmsrs; ++i)
 432                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 433                         return i;
 434         return -1;
 435 }
 436
 437 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 438 {
 439     struct {
 440         u64 vpid : 16;
 441         u64 rsvd : 48;
 442         u64 gva;
 443     } operand = { vpid, 0, gva };
 444
 445     asm volatile (__ex(ASM_VMX_INVVPID)
 446                   /* CF==1 or ZF==1 --> rc = -1 */
 447                   "; ja 1f ; ud2 ; 1:"
 448                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 449 }
 450
 451 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 452 {
 453         struct {
 454                 u64 eptp, gpa;
 455         } operand = {eptp, gpa};
 456
 457         asm volatile (__ex(ASM_VMX_INVEPT)
 458                         /* CF==1 or ZF==1 --> rc = -1 */
 459                         "; ja 1f ; ud2 ; 1:\n"
 460                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 461 }
 462
 463 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 464 {
 465         int i;
 466
 467         i = __find_msr_index(vmx, msr);
 468         if (i >= 0)
 469                 return &vmx->guest_msrs[i];
 470         return NULL;
 471 }
 472
 473 static void vmcs_clear(struct vmcs *vmcs)
 474 {
 475         u64 phys_addr = __pa(vmcs);
 476         u8 error;
 477
 478         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 479                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 480                       : "cc", "memory");
 481         if (error)
 482                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 483                        vmcs, phys_addr);
 484 }
 485
 486 static void vmcs_load(struct vmcs *vmcs)
 487 {
 488         u64 phys_addr = __pa(vmcs);
 489         u8 error;
 490
 491         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 492                         : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 493                         : "cc", "memory");
 494         if (error)
 495                 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 496                        vmcs, phys_addr);
 497 }
 498
 499 static void __vcpu_clear(void *arg)
 500 {
 501         struct vcpu_vmx *vmx = arg;
 502         int cpu = raw_smp_processor_id();
 503
 504         if (vmx->vcpu.cpu == cpu)
 505                 vmcs_clear(vmx->vmcs);
 506         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 507                 per_cpu(current_vmcs, cpu) = NULL;
 508         rdtscll(vmx->vcpu.arch.host_tsc);
 509         list_del(&vmx->local_vcpus_link);
 510         vmx->vcpu.cpu = -1;
 511         vmx->launched = 0;
 512 }
 513
 514 static void vcpu_clear(struct vcpu_vmx *vmx)
 515 {
 516         if (vmx->vcpu.cpu == -1)
 517                 return;
 518         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 519 }
 520
 521 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
 522 {
 523         if (vmx->vpid == 0)
 524                 return;
 525
 526         if (cpu_has_vmx_invvpid_single())
 527                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 528 }
 529
 530 static inline void vpid_sync_vcpu_global(void)
 531 {
 532         if (cpu_has_vmx_invvpid_global())
 533                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
 534 }
 535
 536 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
 537 {
 538         if (cpu_has_vmx_invvpid_single())
 539                 vpid_sync_vcpu_single(vmx);
 540         else
 541                 vpid_sync_vcpu_global();
 542 }
 543
 544 static inline void ept_sync_global(void)
 545 {
 546         if (cpu_has_vmx_invept_global())
 547                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 548 }
 549
 550 static inline void ept_sync_context(u64 eptp)
 551 {
 552         if (enable_ept) {
 553                 if (cpu_has_vmx_invept_context())
 554                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 555                 else
 556                         ept_sync_global();
 557         }
 558 }
 559
 560 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 561 {
 562         if (enable_ept) {
 563                 if (cpu_has_vmx_invept_individual_addr())
 564                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 565                                         eptp, gpa);
 566                 else
 567                         ept_sync_context(eptp);
 568         }
 569 }
 570
 571 static unsigned long vmcs_readl(unsigned long field)
 572 {
 573         unsigned long value;
 574
 575         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 576                       : "=a"(value) : "d"(field) : "cc");
 577         return value;
 578 }
 579
 580 static u16 vmcs_read16(unsigned long field)
 581 {
 582         return vmcs_readl(field);
 583 }
 584
 585 static u32 vmcs_read32(unsigned long field)
 586 {
 587         return vmcs_readl(field);
 588 }
 589
 590 static u64 vmcs_read64(unsigned long field)
 591 {
 592 #ifdef CONFIG_X86_64
 593         return vmcs_readl(field);
 594 #else
 595         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 596 #endif
 597 }
 598
 599 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 600 {
 601         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 602                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 603         dump_stack();
 604 }
 605
 606 static void vmcs_writel(unsigned long field, unsigned long value)
 607 {
 608         u8 error;
 609
 610         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 611                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 612         if (unlikely(error))
 613                 vmwrite_error(field, value);
 614 }
 615
 616 static void vmcs_write16(unsigned long field, u16 value)
 617 {
 618         vmcs_writel(field, value);
 619 }
 620
 621 static void vmcs_write32(unsigned long field, u32 value)
 622 {
 623         vmcs_writel(field, value);
 624 }
 625
 626 static void vmcs_write64(unsigned long field, u64 value)
 627 {
 628         vmcs_writel(field, value);
 629 #ifndef CONFIG_X86_64
 630         asm volatile ("");
 631         vmcs_writel(field+1, value >> 32);
 632 #endif
 633 }
 634
 635 static void vmcs_clear_bits(unsigned long field, u32 mask)
 636 {
 637         vmcs_writel(field, vmcs_readl(field) & ~mask);
 638 }
 639
 640 static void vmcs_set_bits(unsigned long field, u32 mask)
 641 {
 642         vmcs_writel(field, vmcs_readl(field) | mask);
 643 }
 644
 645 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 646 {
 647         u32 eb;
 648
 649         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 650              (1u << NM_VECTOR) | (1u << DB_VECTOR);
 651         if ((vcpu->guest_debug &
 652              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 653             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 654                 eb |= 1u << BP_VECTOR;
 655         if (to_vmx(vcpu)->rmode.vm86_active)
 656                 eb = ~0;
 657         if (enable_ept)
 658                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 659         if (vcpu->fpu_active)
 660                 eb &= ~(1u << NM_VECTOR);
 661         vmcs_write32(EXCEPTION_BITMAP, eb);
 662 }
 663
 664 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 665 {
 666         unsigned i;
 667         struct msr_autoload *m = &vmx->msr_autoload;
 668
 669         for (i = 0; i < m->nr; ++i)
 670                 if (m->guest[i].index == msr)
 671                         break;
 672
 673         if (i == m->nr)
 674                 return;
 675         --m->nr;
 676         m->guest[i] = m->guest[m->nr];
 677         m->host[i] = m->host[m->nr];
 678         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
 679         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
 680 }
 681
 682 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 683                                   u64 guest_val, u64 host_val)
 684 {
 685         unsigned i;
 686         struct msr_autoload *m = &vmx->msr_autoload;
 687
 688         for (i = 0; i < m->nr; ++i)
 689                 if (m->guest[i].index == msr)
 690                         break;
 691
 692         if (i == m->nr) {
 693                 ++m->nr;
 694                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
 695                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
 696         }
 697
 698         m->guest[i].index = msr;
 699         m->guest[i].value = guest_val;
 700         m->host[i].index = msr;
 701         m->host[i].value = host_val;
 702 }
 703
 704 static void reload_tss(void)
 705 {
 706         /*
 707          * VT restores TR but not its size.  Useless.
 708          */
 709         struct desc_ptr gdt;
 710         struct desc_struct *descs;
 711
 712         native_store_gdt(&gdt);
 713         descs = (void *)gdt.address;
 714         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 715         load_TR_desc();
 716 }
 717
 718 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 719 {
 720         u64 guest_efer;
 721         u64 ignore_bits;
 722
 723         guest_efer = vmx->vcpu.arch.efer;
 724
 725         /*
 726          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 727          * outside long mode
 728          */
 729         ignore_bits = EFER_NX | EFER_SCE;
 730 #ifdef CONFIG_X86_64
 731         ignore_bits |= EFER_LMA | EFER_LME;
 732         /* SCE is meaningful only in long mode on Intel */
 733         if (guest_efer & EFER_LMA)
 734                 ignore_bits &= ~(u64)EFER_SCE;
 735 #endif
 736         guest_efer &= ~ignore_bits;
 737         guest_efer |= host_efer & ignore_bits;
 738         vmx->guest_msrs[efer_offset].data = guest_efer;
 739         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
 740
 741         clear_atomic_switch_msr(vmx, MSR_EFER);
 742         /* On ept, can't emulate nx, and must switch nx atomically */
 743         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
 744                 guest_efer = vmx->vcpu.arch.efer;
 745                 if (!(guest_efer & EFER_LMA))
 746                         guest_efer &= ~EFER_LME;
 747                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
 748                 return false;
 749         }
 750
 751         return true;
 752 }
 753
 754 static unsigned long segment_base(u16 selector)
 755 {
 756         struct desc_ptr gdt;
 757         struct desc_struct *d;
 758         unsigned long table_base;
 759         unsigned long v;
 760
 761         if (!(selector & ~3))
 762                 return 0;
 763
 764         native_store_gdt(&gdt);
 765         table_base = gdt.address;
 766
 767         if (selector & 4) {           /* from ldt */
 768                 u16 ldt_selector = kvm_read_ldt();
 769
 770                 if (!(ldt_selector & ~3))
 771                         return 0;
 772
 773                 table_base = segment_base(ldt_selector);
 774         }
 775         d = (struct desc_struct *)(table_base + (selector & ~7));
 776         v = get_desc_base(d);
 777 #ifdef CONFIG_X86_64
 778        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
 779                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
 780 #endif
 781         return v;
 782 }
 783
 784 static inline unsigned long kvm_read_tr_base(void)
 785 {
 786         u16 tr;
 787         asm("str %0" : "=g"(tr));
 788         return segment_base(tr);
 789 }
 790
 791 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 792 {
 793         struct vcpu_vmx *vmx = to_vmx(vcpu);
 794         int i;
 795
 796         if (vmx->host_state.loaded)
 797                 return;
 798
 799         vmx->host_state.loaded = 1;
 800         /*
 801          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 802          * allow segment selectors with cpl > 0 or ti == 1.
 803          */
 804         vmx->host_state.ldt_sel = kvm_read_ldt();
 805         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 806         vmx->host_state.fs_sel = kvm_read_fs();
 807         if (!(vmx->host_state.fs_sel & 7)) {
 808                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 809                 vmx->host_state.fs_reload_needed = 0;
 810         } else {
 811                 vmcs_write16(HOST_FS_SELECTOR, 0);
 812                 vmx->host_state.fs_reload_needed = 1;
 813         }
 814         vmx->host_state.gs_sel = kvm_read_gs();
 815         if (!(vmx->host_state.gs_sel & 7))
 816                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 817         else {
 818                 vmcs_write16(HOST_GS_SELECTOR, 0);
 819                 vmx->host_state.gs_ldt_reload_needed = 1;
 820         }
 821
 822 #ifdef CONFIG_X86_64
 823         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 824         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 825 #else
 826         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 827         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 828 #endif
 829
 830 #ifdef CONFIG_X86_64
 831         if (is_long_mode(&vmx->vcpu)) {
 832                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 833                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 834         }
 835 #endif
 836         for (i = 0; i < vmx->save_nmsrs; ++i)
 837                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
 838                                    vmx->guest_msrs[i].data,
 839                                    vmx->guest_msrs[i].mask);
 840 }
 841
 842 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 843 {
 844         unsigned long flags;
 845
 846         if (!vmx->host_state.loaded)
 847                 return;
 848
 849         ++vmx->vcpu.stat.host_state_reload;
 850         vmx->host_state.loaded = 0;
 851         if (vmx->host_state.fs_reload_needed)
 852                 kvm_load_fs(vmx->host_state.fs_sel);
 853         if (vmx->host_state.gs_ldt_reload_needed) {
 854                 kvm_load_ldt(vmx->host_state.ldt_sel);
 855                 /*
 856                  * If we have to reload gs, we must take care to
 857                  * preserve our gs base.
 858                  */
 859                 local_irq_save(flags);
 860                 kvm_load_gs(vmx->host_state.gs_sel);
 861 #ifdef CONFIG_X86_64
 862                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 863 #endif
 864                 local_irq_restore(flags);
 865         }
 866         reload_tss();
 867 #ifdef CONFIG_X86_64
 868         if (is_long_mode(&vmx->vcpu)) {
 869                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 870                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 871         }
 872 #endif
 873         if (current_thread_info()->status & TS_USEDFPU)
 874                 clts();
 875         load_gdt(&__get_cpu_var(host_gdt));
 876 }
 877
 878 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 879 {
 880         preempt_disable();
 881         __vmx_load_host_state(vmx);
 882         preempt_enable();
 883 }
 884
 885 /*
 886  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 887  * vcpu mutex is already taken.
 888  */
 889 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 890 {
 891         struct vcpu_vmx *vmx = to_vmx(vcpu);
 892         u64 tsc_this, delta, new_offset;
 893         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
 894
 895         if (!vmm_exclusive)
 896                 kvm_cpu_vmxon(phys_addr);
 897         else if (vcpu->cpu != cpu)
 898                 vcpu_clear(vmx);
 899
 900         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 901                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 902                 vmcs_load(vmx->vmcs);
 903         }
 904
 905         if (vcpu->cpu != cpu) {
 906                 struct desc_ptr dt;
 907                 unsigned long sysenter_esp;
 908
 909                 kvm_migrate_timers(vcpu);
 910                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
 911                 local_irq_disable();
 912                 list_add(&vmx->local_vcpus_link,
 913                          &per_cpu(vcpus_on_cpu, cpu));
 914                 local_irq_enable();
 915
 916                 vcpu->cpu = cpu;
 917                 /*
 918                  * Linux uses per-cpu TSS and GDT, so set these when switching
 919                  * processors.
 920                  */
 921                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 922                 native_store_gdt(&dt);
 923                 vmcs_writel(HOST_GDTR_BASE, dt.address);   /* 22.2.4 */
 924
 925                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 926                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 927
 928                 /*
 929                  * Make sure the time stamp counter is monotonous.
 930                  */
 931                 rdtscll(tsc_this);
 932                 if (tsc_this < vcpu->arch.host_tsc) {
 933                         delta = vcpu->arch.host_tsc - tsc_this;
 934                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 935                         vmcs_write64(TSC_OFFSET, new_offset);
 936                 }
 937         }
 938 }
 939
 940 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 941 {
 942         __vmx_load_host_state(to_vmx(vcpu));
 943         if (!vmm_exclusive) {
 944                 __vcpu_clear(to_vmx(vcpu));
 945                 kvm_cpu_vmxoff();
 946         }
 947 }
 948
 949 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 950 {
 951         ulong cr0;
 952
 953         if (vcpu->fpu_active)
 954                 return;
 955         vcpu->fpu_active = 1;
 956         cr0 = vmcs_readl(GUEST_CR0);
 957         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
 958         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
 959         vmcs_writel(GUEST_CR0, cr0);
 960         update_exception_bitmap(vcpu);
 961         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
 962         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 963 }
 964
 965 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
 966
 967 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 968 {
 969         vmx_decache_cr0_guest_bits(vcpu);
 970         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
 971         update_exception_bitmap(vcpu);
 972         vcpu->arch.cr0_guest_owned_bits = 0;
 973         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 974         vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
 975 }
 976
 977 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 978 {
 979         unsigned long rflags, save_rflags;
 980
 981         rflags = vmcs_readl(GUEST_RFLAGS);
 982         if (to_vmx(vcpu)->rmode.vm86_active) {
 983                 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
 984                 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
 985                 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
 986         }
 987         return rflags;
 988 }
 989
 990 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 991 {
 992         if (to_vmx(vcpu)->rmode.vm86_active) {
 993                 to_vmx(vcpu)->rmode.save_rflags = rflags;
 994                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 995         }
 996         vmcs_writel(GUEST_RFLAGS, rflags);
 997 }
 998
 999 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1000 {
1001         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1002         int ret = 0;
1003
1004         if (interruptibility & GUEST_INTR_STATE_STI)
1005                 ret |= KVM_X86_SHADOW_INT_STI;
1006         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1007                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1008
1009         return ret & mask;
1010 }
1011
1012 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1013 {
1014         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1015         u32 interruptibility = interruptibility_old;
1016
1017         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1018
1019         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1020                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1021         else if (mask & KVM_X86_SHADOW_INT_STI)
1022                 interruptibility |= GUEST_INTR_STATE_STI;
1023
1024         if ((interruptibility != interruptibility_old))
1025                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1026 }
1027
1028 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1029 {
1030         unsigned long rip;
1031
1032         rip = kvm_rip_read(vcpu);
1033         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1034         kvm_rip_write(vcpu, rip);
1035
1036         /* skipping an emulated instruction also counts */
1037         vmx_set_interrupt_shadow(vcpu, 0);
1038 }
1039
1040 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1041                                 bool has_error_code, u32 error_code,
1042                                 bool reinject)
1043 {
1044         struct vcpu_vmx *vmx = to_vmx(vcpu);
1045         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1046
1047         if (has_error_code) {
1048                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1049                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1050         }
1051
1052         if (vmx->rmode.vm86_active) {
1053                 vmx->rmode.irq.pending = true;
1054                 vmx->rmode.irq.vector = nr;
1055                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
1056                 if (kvm_exception_is_soft(nr))
1057                         vmx->rmode.irq.rip +=
1058                                 vmx->vcpu.arch.event_exit_inst_len;
1059                 intr_info |= INTR_TYPE_SOFT_INTR;
1060                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1061                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1062                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
1063                 return;
1064         }
1065
1066         if (kvm_exception_is_soft(nr)) {
1067                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1068                              vmx->vcpu.arch.event_exit_inst_len);
1069                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1070         } else
1071                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1072
1073         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1074 }
1075
1076 static bool vmx_rdtscp_supported(void)
1077 {
1078         return cpu_has_vmx_rdtscp();
1079 }
1080
1081 /*
1082  * Swap MSR entry in host/guest MSR entry array.
1083  */
1084 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1085 {
1086         struct shared_msr_entry tmp;
1087
1088         tmp = vmx->guest_msrs[to];
1089         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1090         vmx->guest_msrs[from] = tmp;
1091 }
1092
1093 /*
1094  * Set up the vmcs to automatically save and restore system
1095  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1096  * mode, as fiddling with msrs is very expensive.
1097  */
1098 static void setup_msrs(struct vcpu_vmx *vmx)
1099 {
1100         int save_nmsrs, index;
1101         unsigned long *msr_bitmap;
1102
1103         vmx_load_host_state(vmx);
1104         save_nmsrs = 0;
1105 #ifdef CONFIG_X86_64
1106         if (is_long_mode(&vmx->vcpu)) {
1107                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1108                 if (index >= 0)
1109                         move_msr_up(vmx, index, save_nmsrs++);
1110                 index = __find_msr_index(vmx, MSR_LSTAR);
1111                 if (index >= 0)
1112                         move_msr_up(vmx, index, save_nmsrs++);
1113                 index = __find_msr_index(vmx, MSR_CSTAR);
1114                 if (index >= 0)
1115                         move_msr_up(vmx, index, save_nmsrs++);
1116                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1117                 if (index >= 0 && vmx->rdtscp_enabled)
1118                         move_msr_up(vmx, index, save_nmsrs++);
1119                 /*
1120                  * MSR_STAR is only needed on long mode guests, and only
1121                  * if efer.sce is enabled.
1122                  */
1123                 index = __find_msr_index(vmx, MSR_STAR);
1124                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1125                         move_msr_up(vmx, index, save_nmsrs++);
1126         }
1127 #endif
1128         index = __find_msr_index(vmx, MSR_EFER);
1129         if (index >= 0 && update_transition_efer(vmx, index))
1130                 move_msr_up(vmx, index, save_nmsrs++);
1131
1132         vmx->save_nmsrs = save_nmsrs;
1133
1134         if (cpu_has_vmx_msr_bitmap()) {
1135                 if (is_long_mode(&vmx->vcpu))
1136                         msr_bitmap = vmx_msr_bitmap_longmode;
1137                 else
1138                         msr_bitmap = vmx_msr_bitmap_legacy;
1139
1140                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1141         }
1142 }
1143
1144 /*
1145  * reads and returns guest's timestamp counter "register"
1146  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1147  */
1148 static u64 guest_read_tsc(void)
1149 {
1150         u64 host_tsc, tsc_offset;
1151
1152         rdtscll(host_tsc);
1153         tsc_offset = vmcs_read64(TSC_OFFSET);
1154         return host_tsc + tsc_offset;
1155 }
1156
1157 /*
1158  * writes 'guest_tsc' into guest's timestamp counter "register"
1159  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
1160  */
1161 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
1162 {
1163         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
1164 }
1165
1166 /*
1167  * Reads an msr value (of 'msr_index') into 'pdata'.
1168  * Returns 0 on success, non-0 otherwise.
1169  * Assumes vcpu_load() was already called.
1170  */
1171 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1172 {
1173         u64 data;
1174         struct shared_msr_entry *msr;
1175
1176         if (!pdata) {
1177                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1178                 return -EINVAL;
1179         }
1180
1181         switch (msr_index) {
1182 #ifdef CONFIG_X86_64
1183         case MSR_FS_BASE:
1184                 data = vmcs_readl(GUEST_FS_BASE);
1185                 break;
1186         case MSR_GS_BASE:
1187                 data = vmcs_readl(GUEST_GS_BASE);
1188                 break;
1189         case MSR_KERNEL_GS_BASE:
1190                 vmx_load_host_state(to_vmx(vcpu));
1191                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1192                 break;
1193 #endif
1194         case MSR_EFER:
1195                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1196         case MSR_IA32_TSC:
1197                 data = guest_read_tsc();
1198                 break;
1199         case MSR_IA32_SYSENTER_CS:
1200                 data = vmcs_read32(GUEST_SYSENTER_CS);
1201                 break;
1202         case MSR_IA32_SYSENTER_EIP:
1203                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1204                 break;
1205         case MSR_IA32_SYSENTER_ESP:
1206                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1207                 break;
1208         case MSR_TSC_AUX:
1209                 if (!to_vmx(vcpu)->rdtscp_enabled)
1210                         return 1;
1211                 /* Otherwise falls through */
1212         default:
1213                 vmx_load_host_state(to_vmx(vcpu));
1214                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1215                 if (msr) {
1216                         vmx_load_host_state(to_vmx(vcpu));
1217                         data = msr->data;
1218                         break;
1219                 }
1220                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1221         }
1222
1223         *pdata = data;
1224         return 0;
1225 }
1226
1227 /*
1228  * Writes msr value into into the appropriate "register".
1229  * Returns 0 on success, non-0 otherwise.
1230  * Assumes vcpu_load() was already called.
1231  */
1232 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1233 {
1234         struct vcpu_vmx *vmx = to_vmx(vcpu);
1235         struct shared_msr_entry *msr;
1236         u64 host_tsc;
1237         int ret = 0;
1238
1239         switch (msr_index) {
1240         case MSR_EFER:
1241                 vmx_load_host_state(vmx);
1242                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1243                 break;
1244 #ifdef CONFIG_X86_64
1245         case MSR_FS_BASE:
1246                 vmcs_writel(GUEST_FS_BASE, data);
1247                 break;
1248         case MSR_GS_BASE:
1249                 vmcs_writel(GUEST_GS_BASE, data);
1250                 break;
1251         case MSR_KERNEL_GS_BASE:
1252                 vmx_load_host_state(vmx);
1253                 vmx->msr_guest_kernel_gs_base = data;
1254                 break;
1255 #endif
1256         case MSR_IA32_SYSENTER_CS:
1257                 vmcs_write32(GUEST_SYSENTER_CS, data);
1258                 break;
1259         case MSR_IA32_SYSENTER_EIP:
1260                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1261                 break;
1262         case MSR_IA32_SYSENTER_ESP:
1263                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1264                 break;
1265         case MSR_IA32_TSC:
1266                 rdtscll(host_tsc);
1267                 guest_write_tsc(data, host_tsc);
1268                 break;
1269         case MSR_IA32_CR_PAT:
1270                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1271                         vmcs_write64(GUEST_IA32_PAT, data);
1272                         vcpu->arch.pat = data;
1273                         break;
1274                 }
1275                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1276                 break;
1277         case MSR_TSC_AUX:
1278                 if (!vmx->rdtscp_enabled)
1279                         return 1;
1280                 /* Check reserved bit, higher 32 bits should be zero */
1281                 if ((data >> 32) != 0)
1282                         return 1;
1283                 /* Otherwise falls through */
1284         default:
1285                 msr = find_msr_entry(vmx, msr_index);
1286                 if (msr) {
1287                         vmx_load_host_state(vmx);
1288                         msr->data = data;
1289                         break;
1290                 }
1291                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1292         }
1293
1294         return ret;
1295 }
1296
1297 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1298 {
1299         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1300         switch (reg) {
1301         case VCPU_REGS_RSP:
1302                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1303                 break;
1304         case VCPU_REGS_RIP:
1305                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1306                 break;
1307         case VCPU_EXREG_PDPTR:
1308                 if (enable_ept)
1309                         ept_save_pdptrs(vcpu);
1310                 break;
1311         default:
1312                 break;
1313         }
1314 }
1315
1316 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1317 {
1318         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1319                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1320         else
1321                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1322
1323         update_exception_bitmap(vcpu);
1324 }
1325
1326 static __init int cpu_has_kvm_support(void)
1327 {
1328         return cpu_has_vmx();
1329 }
1330
1331 static __init int vmx_disabled_by_bios(void)
1332 {
1333         u64 msr;
1334
1335         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1336         if (msr & FEATURE_CONTROL_LOCKED) {
1337                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1338                         && tboot_enabled())
1339                         return 1;
1340                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1341                         && !tboot_enabled())
1342                         return 1;
1343         }
1344
1345         return 0;
1346         /* locked but not enabled */
1347 }
1348
1349 static void kvm_cpu_vmxon(u64 addr)
1350 {
1351         asm volatile (ASM_VMX_VMXON_RAX
1352                         : : "a"(&addr), "m"(addr)
1353                         : "memory", "cc");
1354 }
1355
1356 static int hardware_enable(void *garbage)
1357 {
1358         int cpu = raw_smp_processor_id();
1359         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1360         u64 old, test_bits;
1361
1362         if (read_cr4() & X86_CR4_VMXE)
1363                 return -EBUSY;
1364
1365         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1366         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1367
1368         test_bits = FEATURE_CONTROL_LOCKED;
1369         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1370         if (tboot_enabled())
1371                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1372
1373         if ((old & test_bits) != test_bits) {
1374                 /* enable and lock */
1375                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1376         }
1377         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1378
1379         if (vmm_exclusive) {
1380                 kvm_cpu_vmxon(phys_addr);
1381                 ept_sync_global();
1382         }
1383
1384         store_gdt(&__get_cpu_var(host_gdt));
1385
1386         return 0;
1387 }
1388
1389 static void vmclear_local_vcpus(void)
1390 {
1391         int cpu = raw_smp_processor_id();
1392         struct vcpu_vmx *vmx, *n;
1393
1394         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1395                                  local_vcpus_link)
1396                 __vcpu_clear(vmx);
1397 }
1398
1399
1400 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1401  * tricks.
1402  */
1403 static void kvm_cpu_vmxoff(void)
1404 {
1405         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1406 }
1407
1408 static void hardware_disable(void *garbage)
1409 {
1410         if (vmm_exclusive) {
1411                 vmclear_local_vcpus();
1412                 kvm_cpu_vmxoff();
1413         }
1414         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1415 }
1416
1417 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1418                                       u32 msr, u32 *result)
1419 {
1420         u32 vmx_msr_low, vmx_msr_high;
1421         u32 ctl = ctl_min | ctl_opt;
1422
1423         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1424
1425         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1426         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1427
1428         /* Ensure minimum (required) set of control bits are supported. */
1429         if (ctl_min & ~ctl)
1430                 return -EIO;
1431
1432         *result = ctl;
1433         return 0;
1434 }
1435
1436 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1437 {
1438         u32 vmx_msr_low, vmx_msr_high;
1439         u32 min, opt, min2, opt2;
1440         u32 _pin_based_exec_control = 0;
1441         u32 _cpu_based_exec_control = 0;
1442         u32 _cpu_based_2nd_exec_control = 0;
1443         u32 _vmexit_control = 0;
1444         u32 _vmentry_control = 0;
1445
1446         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1447         opt = PIN_BASED_VIRTUAL_NMIS;
1448         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1449                                 &_pin_based_exec_control) < 0)
1450                 return -EIO;
1451
1452         min = CPU_BASED_HLT_EXITING |
1453 #ifdef CONFIG_X86_64
1454               CPU_BASED_CR8_LOAD_EXITING |
1455               CPU_BASED_CR8_STORE_EXITING |
1456 #endif
1457               CPU_BASED_CR3_LOAD_EXITING |
1458               CPU_BASED_CR3_STORE_EXITING |
1459               CPU_BASED_USE_IO_BITMAPS |
1460               CPU_BASED_MOV_DR_EXITING |
1461               CPU_BASED_USE_TSC_OFFSETING |
1462               CPU_BASED_MWAIT_EXITING |
1463               CPU_BASED_MONITOR_EXITING |
1464               CPU_BASED_INVLPG_EXITING;
1465         opt = CPU_BASED_TPR_SHADOW |
1466               CPU_BASED_USE_MSR_BITMAPS |
1467               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1468         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1469                                 &_cpu_based_exec_control) < 0)
1470                 return -EIO;
1471 #ifdef CONFIG_X86_64
1472         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1473                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1474                                            ~CPU_BASED_CR8_STORE_EXITING;
1475 #endif
1476         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1477                 min2 = 0;
1478                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1479                         SECONDARY_EXEC_WBINVD_EXITING |
1480                         SECONDARY_EXEC_ENABLE_VPID |
1481                         SECONDARY_EXEC_ENABLE_EPT |
1482                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
1483                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1484                         SECONDARY_EXEC_RDTSCP;
1485                 if (adjust_vmx_controls(min2, opt2,
1486                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1487                                         &_cpu_based_2nd_exec_control) < 0)
1488                         return -EIO;
1489         }
1490 #ifndef CONFIG_X86_64
1491         if (!(_cpu_based_2nd_exec_control &
1492                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1493                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1494 #endif
1495         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1496                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1497                    enabled */
1498                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1499                                              CPU_BASED_CR3_STORE_EXITING |
1500                                              CPU_BASED_INVLPG_EXITING);
1501                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1502                       vmx_capability.ept, vmx_capability.vpid);
1503         }
1504
1505         min = 0;
1506 #ifdef CONFIG_X86_64
1507         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1508 #endif
1509         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1510         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1511                                 &_vmexit_control) < 0)
1512                 return -EIO;
1513
1514         min = 0;
1515         opt = VM_ENTRY_LOAD_IA32_PAT;
1516         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1517                                 &_vmentry_control) < 0)
1518                 return -EIO;
1519
1520         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1521
1522         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1523         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1524                 return -EIO;
1525
1526 #ifdef CONFIG_X86_64
1527         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1528         if (vmx_msr_high & (1u<<16))
1529                 return -EIO;
1530 #endif
1531
1532         /* Require Write-Back (WB) memory type for VMCS accesses. */
1533         if (((vmx_msr_high >> 18) & 15) != 6)
1534                 return -EIO;
1535
1536         vmcs_conf->size = vmx_msr_high & 0x1fff;
1537         vmcs_conf->order = get_order(vmcs_config.size);
1538         vmcs_conf->revision_id = vmx_msr_low;
1539
1540         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1541         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1542         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1543         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1544         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1545
1546         return 0;
1547 }
1548
1549 static struct vmcs *alloc_vmcs_cpu(int cpu)
1550 {
1551         int node = cpu_to_node(cpu);
1552         struct page *pages;
1553         struct vmcs *vmcs;
1554
1555         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1556         if (!pages)
1557                 return NULL;
1558         vmcs = page_address(pages);
1559         memset(vmcs, 0, vmcs_config.size);
1560         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1561         return vmcs;
1562 }
1563
1564 static struct vmcs *alloc_vmcs(void)
1565 {
1566         return alloc_vmcs_cpu(raw_smp_processor_id());
1567 }
1568
1569 static void free_vmcs(struct vmcs *vmcs)
1570 {
1571         free_pages((unsigned long)vmcs, vmcs_config.order);
1572 }
1573
1574 static void free_kvm_area(void)
1575 {
1576         int cpu;
1577
1578         for_each_possible_cpu(cpu) {
1579                 free_vmcs(per_cpu(vmxarea, cpu));
1580                 per_cpu(vmxarea, cpu) = NULL;
1581         }
1582 }
1583
1584 static __init int alloc_kvm_area(void)
1585 {
1586         int cpu;
1587
1588         for_each_possible_cpu(cpu) {
1589                 struct vmcs *vmcs;
1590
1591                 vmcs = alloc_vmcs_cpu(cpu);
1592                 if (!vmcs) {
1593                         free_kvm_area();
1594                         return -ENOMEM;
1595                 }
1596
1597                 per_cpu(vmxarea, cpu) = vmcs;
1598         }
1599         return 0;
1600 }
1601
1602 static __init int hardware_setup(void)
1603 {
1604         if (setup_vmcs_config(&vmcs_config) < 0)
1605                 return -EIO;
1606
1607         if (boot_cpu_has(X86_FEATURE_NX))
1608                 kvm_enable_efer_bits(EFER_NX);
1609
1610         if (!cpu_has_vmx_vpid())
1611                 enable_vpid = 0;
1612
1613         if (!cpu_has_vmx_ept() ||
1614             !cpu_has_vmx_ept_4levels()) {
1615                 enable_ept = 0;
1616                 enable_unrestricted_guest = 0;
1617         }
1618
1619         if (!cpu_has_vmx_unrestricted_guest())
1620                 enable_unrestricted_guest = 0;
1621
1622         if (!cpu_has_vmx_flexpriority())
1623                 flexpriority_enabled = 0;
1624
1625         if (!cpu_has_vmx_tpr_shadow())
1626                 kvm_x86_ops->update_cr8_intercept = NULL;
1627
1628         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1629                 kvm_disable_largepages();
1630
1631         if (!cpu_has_vmx_ple())
1632                 ple_gap = 0;
1633
1634         return alloc_kvm_area();
1635 }
1636
1637 static __exit void hardware_unsetup(void)
1638 {
1639         free_kvm_area();
1640 }
1641
1642 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1643 {
1644         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1645
1646         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1647                 vmcs_write16(sf->selector, save->selector);
1648                 vmcs_writel(sf->base, save->base);
1649                 vmcs_write32(sf->limit, save->limit);
1650                 vmcs_write32(sf->ar_bytes, save->ar);
1651         } else {
1652                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1653                         << AR_DPL_SHIFT;
1654                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1655         }
1656 }
1657
1658 static void enter_pmode(struct kvm_vcpu *vcpu)
1659 {
1660         unsigned long flags;
1661         struct vcpu_vmx *vmx = to_vmx(vcpu);
1662
1663         vmx->emulation_required = 1;
1664         vmx->rmode.vm86_active = 0;
1665
1666         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1667         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1668         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1669
1670         flags = vmcs_readl(GUEST_RFLAGS);
1671         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1672         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1673         vmcs_writel(GUEST_RFLAGS, flags);
1674
1675         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1676                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1677
1678         update_exception_bitmap(vcpu);
1679
1680         if (emulate_invalid_guest_state)
1681                 return;
1682
1683         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1684         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1685         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1686         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1687
1688         vmcs_write16(GUEST_SS_SELECTOR, 0);
1689         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1690
1691         vmcs_write16(GUEST_CS_SELECTOR,
1692                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1693         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1694 }
1695
1696 static gva_t rmode_tss_base(struct kvm *kvm)
1697 {
1698         if (!kvm->arch.tss_addr) {
1699                 struct kvm_memslots *slots;
1700                 gfn_t base_gfn;
1701
1702                 slots = kvm_memslots(kvm);
1703                 base_gfn = slots->memslots[0].base_gfn +
1704                                  kvm->memslots->memslots[0].npages - 3;
1705                 return base_gfn << PAGE_SHIFT;
1706         }
1707         return kvm->arch.tss_addr;
1708 }
1709
1710 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1711 {
1712         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1713
1714         save->selector = vmcs_read16(sf->selector);
1715         save->base = vmcs_readl(sf->base);
1716         save->limit = vmcs_read32(sf->limit);
1717         save->ar = vmcs_read32(sf->ar_bytes);
1718         vmcs_write16(sf->selector, save->base >> 4);
1719         vmcs_write32(sf->base, save->base & 0xfffff);
1720         vmcs_write32(sf->limit, 0xffff);
1721         vmcs_write32(sf->ar_bytes, 0xf3);
1722 }
1723
1724 static void enter_rmode(struct kvm_vcpu *vcpu)
1725 {
1726         unsigned long flags;
1727         struct vcpu_vmx *vmx = to_vmx(vcpu);
1728
1729         if (enable_unrestricted_guest)
1730                 return;
1731
1732         vmx->emulation_required = 1;
1733         vmx->rmode.vm86_active = 1;
1734
1735         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1736         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1737
1738         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1739         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1740
1741         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1742         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1743
1744         flags = vmcs_readl(GUEST_RFLAGS);
1745         vmx->rmode.save_rflags = flags;
1746
1747         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1748
1749         vmcs_writel(GUEST_RFLAGS, flags);
1750         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1751         update_exception_bitmap(vcpu);
1752
1753         if (emulate_invalid_guest_state)
1754                 goto continue_rmode;
1755
1756         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1757         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1758         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1759
1760         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1761         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1762         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1763                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1764         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1765
1766         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1767         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1768         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1769         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1770
1771 continue_rmode:
1772         kvm_mmu_reset_context(vcpu);
1773         init_rmode(vcpu->kvm);
1774 }
1775
1776 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1777 {
1778         struct vcpu_vmx *vmx = to_vmx(vcpu);
1779         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1780
1781         if (!msr)
1782                 return;
1783
1784         /*
1785          * Force kernel_gs_base reloading before EFER changes, as control
1786          * of this msr depends on is_long_mode().
1787          */
1788         vmx_load_host_state(to_vmx(vcpu));
1789         vcpu->arch.efer = efer;
1790         if (efer & EFER_LMA) {
1791                 vmcs_write32(VM_ENTRY_CONTROLS,
1792                              vmcs_read32(VM_ENTRY_CONTROLS) |
1793                              VM_ENTRY_IA32E_MODE);
1794                 msr->data = efer;
1795         } else {
1796                 vmcs_write32(VM_ENTRY_CONTROLS,
1797                              vmcs_read32(VM_ENTRY_CONTROLS) &
1798                              ~VM_ENTRY_IA32E_MODE);
1799
1800                 msr->data = efer & ~EFER_LME;
1801         }
1802         setup_msrs(vmx);
1803 }
1804
1805 #ifdef CONFIG_X86_64
1806
1807 static void enter_lmode(struct kvm_vcpu *vcpu)
1808 {
1809         u32 guest_tr_ar;
1810
1811         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1812         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1813                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1814                        __func__);
1815                 vmcs_write32(GUEST_TR_AR_BYTES,
1816                              (guest_tr_ar & ~AR_TYPE_MASK)
1817                              | AR_TYPE_BUSY_64_TSS);
1818         }
1819         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
1820 }
1821
1822 static void exit_lmode(struct kvm_vcpu *vcpu)
1823 {
1824         vmcs_write32(VM_ENTRY_CONTROLS,
1825                      vmcs_read32(VM_ENTRY_CONTROLS)
1826                      & ~VM_ENTRY_IA32E_MODE);
1827         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
1828 }
1829
1830 #endif
1831
1832 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1833 {
1834         vpid_sync_context(to_vmx(vcpu));
1835         if (enable_ept) {
1836                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1837                         return;
1838                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1839         }
1840 }
1841
1842 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1843 {
1844         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1845
1846         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1847         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1848 }
1849
1850 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1851 {
1852         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1853
1854         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1855         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1856 }
1857
1858 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1859 {
1860         if (!test_bit(VCPU_EXREG_PDPTR,
1861                       (unsigned long *)&vcpu->arch.regs_dirty))
1862                 return;
1863
1864         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1865                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1866                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1867                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1868                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1869         }
1870 }
1871
1872 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1873 {
1874         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1875                 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1876                 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1877                 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1878                 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1879         }
1880
1881         __set_bit(VCPU_EXREG_PDPTR,
1882                   (unsigned long *)&vcpu->arch.regs_avail);
1883         __set_bit(VCPU_EXREG_PDPTR,
1884                   (unsigned long *)&vcpu->arch.regs_dirty);
1885 }
1886
1887 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1888
1889 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1890                                         unsigned long cr0,
1891                                         struct kvm_vcpu *vcpu)
1892 {
1893         if (!(cr0 & X86_CR0_PG)) {
1894                 /* From paging/starting to nonpaging */
1895                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1896                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1897                              (CPU_BASED_CR3_LOAD_EXITING |
1898                               CPU_BASED_CR3_STORE_EXITING));
1899                 vcpu->arch.cr0 = cr0;
1900                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1901         } else if (!is_paging(vcpu)) {
1902                 /* From nonpaging to paging */
1903                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1904                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1905                              ~(CPU_BASED_CR3_LOAD_EXITING |
1906                                CPU_BASED_CR3_STORE_EXITING));
1907                 vcpu->arch.cr0 = cr0;
1908                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1909         }
1910
1911         if (!(cr0 & X86_CR0_WP))
1912                 *hw_cr0 &= ~X86_CR0_WP;
1913 }
1914
1915 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1916 {
1917         struct vcpu_vmx *vmx = to_vmx(vcpu);
1918         unsigned long hw_cr0;
1919
1920         if (enable_unrestricted_guest)
1921                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1922                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1923         else
1924                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1925
1926         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1927                 enter_pmode(vcpu);
1928
1929         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1930                 enter_rmode(vcpu);
1931
1932 #ifdef CONFIG_X86_64
1933         if (vcpu->arch.efer & EFER_LME) {
1934                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1935                         enter_lmode(vcpu);
1936                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1937                         exit_lmode(vcpu);
1938         }
1939 #endif
1940
1941         if (enable_ept)
1942                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1943
1944         if (!vcpu->fpu_active)
1945                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1946
1947         vmcs_writel(CR0_READ_SHADOW, cr0);
1948         vmcs_writel(GUEST_CR0, hw_cr0);
1949         vcpu->arch.cr0 = cr0;
1950 }
1951
1952 static u64 construct_eptp(unsigned long root_hpa)
1953 {
1954         u64 eptp;
1955
1956         /* TODO write the value reading from MSR */
1957         eptp = VMX_EPT_DEFAULT_MT |
1958                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1959         eptp |= (root_hpa & PAGE_MASK);
1960
1961         return eptp;
1962 }
1963
1964 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1965 {
1966         unsigned long guest_cr3;
1967         u64 eptp;
1968
1969         guest_cr3 = cr3;
1970         if (enable_ept) {
1971                 eptp = construct_eptp(cr3);
1972                 vmcs_write64(EPT_POINTER, eptp);
1973                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1974                         vcpu->kvm->arch.ept_identity_map_addr;
1975                 ept_load_pdptrs(vcpu);
1976         }
1977
1978         vmx_flush_tlb(vcpu);
1979         vmcs_writel(GUEST_CR3, guest_cr3);
1980 }
1981
1982 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1983 {
1984         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1985                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1986
1987         vcpu->arch.cr4 = cr4;
1988         if (enable_ept) {
1989                 if (!is_paging(vcpu)) {
1990                         hw_cr4 &= ~X86_CR4_PAE;
1991                         hw_cr4 |= X86_CR4_PSE;
1992                 } else if (!(cr4 & X86_CR4_PAE)) {
1993                         hw_cr4 &= ~X86_CR4_PAE;
1994                 }
1995         }
1996
1997         vmcs_writel(CR4_READ_SHADOW, cr4);
1998         vmcs_writel(GUEST_CR4, hw_cr4);
1999 }
2000
2001 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2002 {
2003         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2004
2005         return vmcs_readl(sf->base);
2006 }
2007
2008 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2009                             struct kvm_segment *var, int seg)
2010 {
2011         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2012         u32 ar;
2013
2014         var->base = vmcs_readl(sf->base);
2015         var->limit = vmcs_read32(sf->limit);
2016         var->selector = vmcs_read16(sf->selector);
2017         ar = vmcs_read32(sf->ar_bytes);
2018         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2019                 ar = 0;
2020         var->type = ar & 15;
2021         var->s = (ar >> 4) & 1;
2022         var->dpl = (ar >> 5) & 3;
2023         var->present = (ar >> 7) & 1;
2024         var->avl = (ar >> 12) & 1;
2025         var->l = (ar >> 13) & 1;
2026         var->db = (ar >> 14) & 1;
2027         var->g = (ar >> 15) & 1;
2028         var->unusable = (ar >> 16) & 1;
2029 }
2030
2031 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2032 {
2033         if (!is_protmode(vcpu))
2034                 return 0;
2035
2036         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2037                 return 3;
2038
2039         return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2040 }
2041
2042 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2043 {
2044         u32 ar;
2045
2046         if (var->unusable)
2047                 ar = 1 << 16;
2048         else {
2049                 ar = var->type & 15;
2050                 ar |= (var->s & 1) << 4;
2051                 ar |= (var->dpl & 3) << 5;
2052                 ar |= (var->present & 1) << 7;
2053                 ar |= (var->avl & 1) << 12;
2054                 ar |= (var->l & 1) << 13;
2055                 ar |= (var->db & 1) << 14;
2056                 ar |= (var->g & 1) << 15;
2057         }
2058         if (ar == 0) /* a 0 value means unusable */
2059                 ar = AR_UNUSABLE_MASK;
2060
2061         return ar;
2062 }
2063
2064 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2065                             struct kvm_segment *var, int seg)
2066 {
2067         struct vcpu_vmx *vmx = to_vmx(vcpu);
2068         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2069         u32 ar;
2070
2071         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2072                 vmx->rmode.tr.selector = var->selector;
2073                 vmx->rmode.tr.base = var->base;
2074                 vmx->rmode.tr.limit = var->limit;
2075                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2076                 return;
2077         }
2078         vmcs_writel(sf->base, var->base);
2079         vmcs_write32(sf->limit, var->limit);
2080         vmcs_write16(sf->selector, var->selector);
2081         if (vmx->rmode.vm86_active && var->s) {
2082                 /*
2083                  * Hack real-mode segments into vm86 compatibility.
2084                  */
2085                 if (var->base == 0xffff0000 && var->selector == 0xf000)
2086                         vmcs_writel(sf->base, 0xf0000);
2087                 ar = 0xf3;
2088         } else
2089                 ar = vmx_segment_access_rights(var);
2090
2091         /*
2092          *   Fix the "Accessed" bit in AR field of segment registers for older
2093          * qemu binaries.
2094          *   IA32 arch specifies that at the time of processor reset the
2095          * "Accessed" bit in the AR field of segment registers is 1. And qemu
2096          * is setting it to 0 in the usedland code. This causes invalid guest
2097          * state vmexit when "unrestricted guest" mode is turned on.
2098          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
2099          * tree. Newer qemu binaries with that qemu fix would not need this
2100          * kvm hack.
2101          */
2102         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2103                 ar |= 0x1; /* Accessed */
2104
2105         vmcs_write32(sf->ar_bytes, ar);
2106 }
2107
2108 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2109 {
2110         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2111
2112         *db = (ar >> 14) & 1;
2113         *l = (ar >> 13) & 1;
2114 }
2115
2116 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2117 {
2118         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2119         dt->address = vmcs_readl(GUEST_IDTR_BASE);
2120 }
2121
2122 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2123 {
2124         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2125         vmcs_writel(GUEST_IDTR_BASE, dt->address);
2126 }
2127
2128 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2129 {
2130         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2131         dt->address = vmcs_readl(GUEST_GDTR_BASE);
2132 }
2133
2134 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2135 {
2136         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2137         vmcs_writel(GUEST_GDTR_BASE, dt->address);
2138 }
2139
2140 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2141 {
2142         struct kvm_segment var;
2143         u32 ar;
2144
2145         vmx_get_segment(vcpu, &var, seg);
2146         ar = vmx_segment_access_rights(&var);
2147
2148         if (var.base != (var.selector << 4))
2149                 return false;
2150         if (var.limit != 0xffff)
2151                 return false;
2152         if (ar != 0xf3)
2153                 return false;
2154
2155         return true;
2156 }
2157
2158 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2159 {
2160         struct kvm_segment cs;
2161         unsigned int cs_rpl;
2162
2163         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2164         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2165
2166         if (cs.unusable)
2167                 return false;
2168         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2169                 return false;
2170         if (!cs.s)
2171                 return false;
2172         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2173                 if (cs.dpl > cs_rpl)
2174                         return false;
2175         } else {
2176                 if (cs.dpl != cs_rpl)
2177                         return false;
2178         }
2179         if (!cs.present)
2180                 return false;
2181
2182         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2183         return true;
2184 }
2185
2186 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2187 {
2188         struct kvm_segment ss;
2189         unsigned int ss_rpl;
2190
2191         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2192         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2193
2194         if (ss.unusable)
2195                 return true;
2196         if (ss.type != 3 && ss.type != 7)
2197                 return false;
2198         if (!ss.s)
2199                 return false;
2200         if (ss.dpl != ss_rpl) /* DPL != RPL */
2201                 return false;
2202         if (!ss.present)
2203                 return false;
2204
2205         return true;
2206 }
2207
2208 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2209 {
2210         struct kvm_segment var;
2211         unsigned int rpl;
2212
2213         vmx_get_segment(vcpu, &var, seg);
2214         rpl = var.selector & SELECTOR_RPL_MASK;
2215
2216         if (var.unusable)
2217                 return true;
2218         if (!var.s)
2219                 return false;
2220         if (!var.present)
2221                 return false;
2222         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2223                 if (var.dpl < rpl) /* DPL < RPL */
2224                         return false;
2225         }
2226
2227         /* TODO: Add other members to kvm_segment_field to allow checking for other access
2228          * rights flags
2229          */
2230         return true;
2231 }
2232
2233 static bool tr_valid(struct kvm_vcpu *vcpu)
2234 {
2235         struct kvm_segment tr;
2236
2237         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2238
2239         if (tr.unusable)
2240                 return false;
2241         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
2242                 return false;
2243         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2244                 return false;
2245         if (!tr.present)
2246                 return false;
2247
2248         return true;
2249 }
2250
2251 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2252 {
2253         struct kvm_segment ldtr;
2254
2255         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2256
2257         if (ldtr.unusable)
2258                 return true;
2259         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2260                 return false;
2261         if (ldtr.type != 2)
2262                 return false;
2263         if (!ldtr.present)
2264                 return false;
2265
2266         return true;
2267 }
2268
2269 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2270 {
2271         struct kvm_segment cs, ss;
2272
2273         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2274         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2275
2276         return ((cs.selector & SELECTOR_RPL_MASK) ==
2277                  (ss.selector & SELECTOR_RPL_MASK));
2278 }
2279
2280 /*
2281  * Check if guest state is valid. Returns true if valid, false if
2282  * not.
2283  * We assume that registers are always usable
2284  */
2285 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2286 {
2287         /* real mode guest state checks */
2288         if (!is_protmode(vcpu)) {
2289                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2290                         return false;
2291                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2292                         return false;
2293                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2294                         return false;
2295                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2296                         return false;
2297                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2298                         return false;
2299                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2300                         return false;
2301         } else {
2302         /* protected mode guest state checks */
2303                 if (!cs_ss_rpl_check(vcpu))
2304                         return false;
2305                 if (!code_segment_valid(vcpu))
2306                         return false;
2307                 if (!stack_segment_valid(vcpu))
2308                         return false;
2309                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2310                         return false;
2311                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2312                         return false;
2313                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2314                         return false;
2315                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2316                         return false;
2317                 if (!tr_valid(vcpu))
2318                         return false;
2319                 if (!ldtr_valid(vcpu))
2320                         return false;
2321         }
2322         /* TODO:
2323          * - Add checks on RIP
2324          * - Add checks on RFLAGS
2325          */
2326
2327         return true;
2328 }
2329
2330 static int init_rmode_tss(struct kvm *kvm)
2331 {
2332         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2333         u16 data = 0;
2334         int ret = 0;
2335         int r;
2336
2337         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2338         if (r < 0)
2339                 goto out;
2340         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2341         r = kvm_write_guest_page(kvm, fn++, &data,
2342                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2343         if (r < 0)
2344                 goto out;
2345         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2346         if (r < 0)
2347                 goto out;
2348         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2349         if (r < 0)
2350                 goto out;
2351         data = ~0;
2352         r = kvm_write_guest_page(kvm, fn, &data,
2353                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2354                                  sizeof(u8));
2355         if (r < 0)
2356                 goto out;
2357
2358         ret = 1;
2359 out:
2360         return ret;
2361 }
2362
2363 static int init_rmode_identity_map(struct kvm *kvm)
2364 {
2365         int i, r, ret;
2366         pfn_t identity_map_pfn;
2367         u32 tmp;
2368
2369         if (!enable_ept)
2370                 return 1;
2371         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2372                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2373                         "haven't been allocated!\n");
2374                 return 0;
2375         }
2376         if (likely(kvm->arch.ept_identity_pagetable_done))
2377                 return 1;
2378         ret = 0;
2379         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2380         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2381         if (r < 0)
2382                 goto out;
2383         /* Set up identity-mapping pagetable for EPT in real mode */
2384         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2385                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2386                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2387                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2388                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2389                 if (r < 0)
2390                         goto out;
2391         }
2392         kvm->arch.ept_identity_pagetable_done = true;
2393         ret = 1;
2394 out:
2395         return ret;
2396 }
2397
2398 static void seg_setup(int seg)
2399 {
2400         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2401         unsigned int ar;
2402
2403         vmcs_write16(sf->selector, 0);
2404         vmcs_writel(sf->base, 0);
2405         vmcs_write32(sf->limit, 0xffff);
2406         if (enable_unrestricted_guest) {
2407                 ar = 0x93;
2408                 if (seg == VCPU_SREG_CS)
2409                         ar |= 0x08; /* code segment */
2410         } else
2411                 ar = 0xf3;
2412
2413         vmcs_write32(sf->ar_bytes, ar);
2414 }
2415
2416 static int alloc_apic_access_page(struct kvm *kvm)
2417 {
2418         struct kvm_userspace_memory_region kvm_userspace_mem;
2419         int r = 0;
2420
2421         mutex_lock(&kvm->slots_lock);
2422         if (kvm->arch.apic_access_page)
2423                 goto out;
2424         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2425         kvm_userspace_mem.flags = 0;
2426         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2427         kvm_userspace_mem.memory_size = PAGE_SIZE;
2428         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2429         if (r)
2430                 goto out;
2431
2432         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2433 out:
2434         mutex_unlock(&kvm->slots_lock);
2435         return r;
2436 }
2437
2438 static int alloc_identity_pagetable(struct kvm *kvm)
2439 {
2440         struct kvm_userspace_memory_region kvm_userspace_mem;
2441         int r = 0;
2442
2443         mutex_lock(&kvm->slots_lock);
2444         if (kvm->arch.ept_identity_pagetable)
2445                 goto out;
2446         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2447         kvm_userspace_mem.flags = 0;
2448         kvm_userspace_mem.guest_phys_addr =
2449                 kvm->arch.ept_identity_map_addr;
2450         kvm_userspace_mem.memory_size = PAGE_SIZE;
2451         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2452         if (r)
2453                 goto out;
2454
2455         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2456                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2457 out:
2458         mutex_unlock(&kvm->slots_lock);
2459         return r;
2460 }
2461
2462 static void allocate_vpid(struct vcpu_vmx *vmx)
2463 {
2464         int vpid;
2465
2466         vmx->vpid = 0;
2467         if (!enable_vpid)
2468                 return;
2469         spin_lock(&vmx_vpid_lock);
2470         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2471         if (vpid < VMX_NR_VPIDS) {
2472                 vmx->vpid = vpid;
2473                 __set_bit(vpid, vmx_vpid_bitmap);
2474         }
2475         spin_unlock(&vmx_vpid_lock);
2476 }
2477
2478 static void free_vpid(struct vcpu_vmx *vmx)
2479 {
2480         if (!enable_vpid)
2481                 return;
2482         spin_lock(&vmx_vpid_lock);
2483         if (vmx->vpid != 0)
2484                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2485         spin_unlock(&vmx_vpid_lock);
2486 }
2487
2488 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2489 {
2490         int f = sizeof(unsigned long);
2491
2492         if (!cpu_has_vmx_msr_bitmap())
2493                 return;
2494
2495         /*
2496          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2497          * have the write-low and read-high bitmap offsets the wrong way round.
2498          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2499          */
2500         if (msr <= 0x1fff) {
2501                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2502                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2503         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2504                 msr &= 0x1fff;
2505                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2506                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2507         }
2508 }
2509
2510 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2511 {
2512         if (!longmode_only)
2513                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2514         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2515 }
2516
2517 /*
2518  * Sets up the vmcs for emulated real mode.
2519  */
2520 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2521 {
2522         u32 host_sysenter_cs, msr_low, msr_high;
2523         u32 junk;
2524         u64 host_pat, tsc_this, tsc_base;
2525         unsigned long a;
2526         struct desc_ptr dt;
2527         int i;
2528         unsigned long kvm_vmx_return;
2529         u32 exec_control;
2530
2531         /* I/O */
2532         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2533         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2534
2535         if (cpu_has_vmx_msr_bitmap())
2536                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2537
2538         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2539
2540         /* Control */
2541         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2542                 vmcs_config.pin_based_exec_ctrl);
2543
2544         exec_control = vmcs_config.cpu_based_exec_ctrl;
2545         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2546                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2547 #ifdef CONFIG_X86_64
2548                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2549                                 CPU_BASED_CR8_LOAD_EXITING;
2550 #endif
2551         }
2552         if (!enable_ept)
2553                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2554                                 CPU_BASED_CR3_LOAD_EXITING  |
2555                                 CPU_BASED_INVLPG_EXITING;
2556         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2557
2558         if (cpu_has_secondary_exec_ctrls()) {
2559                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2560                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2561                         exec_control &=
2562                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2563                 if (vmx->vpid == 0)
2564                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2565                 if (!enable_ept) {
2566                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2567                         enable_unrestricted_guest = 0;
2568                 }
2569                 if (!enable_unrestricted_guest)
2570                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2571                 if (!ple_gap)
2572                         exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2573                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2574         }
2575
2576         if (ple_gap) {
2577                 vmcs_write32(PLE_GAP, ple_gap);
2578                 vmcs_write32(PLE_WINDOW, ple_window);
2579         }
2580
2581         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2582         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2583         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2584
2585         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
2586         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2587         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2588
2589         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2590         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2591         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2592         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
2593         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
2594         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2595 #ifdef CONFIG_X86_64
2596         rdmsrl(MSR_FS_BASE, a);
2597         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2598         rdmsrl(MSR_GS_BASE, a);
2599         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2600 #else
2601         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2602         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2603 #endif
2604
2605         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2606
2607         native_store_idt(&dt);
2608         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
2609
2610         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2611         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2612         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2613         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2614         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2615         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2616         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2617
2618         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2619         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2620         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2621         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2622         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2623         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2624
2625         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2626                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2627                 host_pat = msr_low | ((u64) msr_high << 32);
2628                 vmcs_write64(HOST_IA32_PAT, host_pat);
2629         }
2630         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2631                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2632                 host_pat = msr_low | ((u64) msr_high << 32);
2633                 /* Write the default value follow host pat */
2634                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2635                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2636                 vmx->vcpu.arch.pat = host_pat;
2637         }
2638
2639         for (i = 0; i < NR_VMX_MSR; ++i) {
2640                 u32 index = vmx_msr_index[i];
2641                 u32 data_low, data_high;
2642                 int j = vmx->nmsrs;
2643
2644                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2645                         continue;
2646                 if (wrmsr_safe(index, data_low, data_high) < 0)
2647                         continue;
2648                 vmx->guest_msrs[j].index = i;
2649                 vmx->guest_msrs[j].data = 0;
2650                 vmx->guest_msrs[j].mask = -1ull;
2651                 ++vmx->nmsrs;
2652         }
2653
2654         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2655
2656         /* 22.2.1, 20.8.1 */
2657         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2658
2659         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2660         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2661         if (enable_ept)
2662                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2663         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2664
2665         tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2666         rdtscll(tsc_this);
2667         if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2668                 tsc_base = tsc_this;
2669
2670         guest_write_tsc(0, tsc_base);
2671
2672         return 0;
2673 }
2674
2675 static int init_rmode(struct kvm *kvm)
2676 {
2677         int idx, ret = 0;
2678
2679         idx = srcu_read_lock(&kvm->srcu);
2680         if (!init_rmode_tss(kvm))
2681                 goto exit;
2682         if (!init_rmode_identity_map(kvm))
2683                 goto exit;
2684
2685         ret = 1;
2686 exit:
2687         srcu_read_unlock(&kvm->srcu, idx);
2688         return ret;
2689 }
2690
2691 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2692 {
2693         struct vcpu_vmx *vmx = to_vmx(vcpu);
2694         u64 msr;
2695         int ret;
2696
2697         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2698         if (!init_rmode(vmx->vcpu.kvm)) {
2699                 ret = -ENOMEM;
2700                 goto out;
2701         }
2702
2703         vmx->rmode.vm86_active = 0;
2704
2705         vmx->soft_vnmi_blocked = 0;
2706
2707         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2708         kvm_set_cr8(&vmx->vcpu, 0);
2709         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2710         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2711                 msr |= MSR_IA32_APICBASE_BSP;
2712         kvm_set_apic_base(&vmx->vcpu, msr);
2713
2714         ret = fx_init(&vmx->vcpu);
2715         if (ret != 0)
2716                 goto out;
2717
2718         seg_setup(VCPU_SREG_CS);
2719         /*
2720          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2721          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2722          */
2723         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2724                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2725                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2726         } else {
2727                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2728                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2729         }
2730
2731         seg_setup(VCPU_SREG_DS);
2732         seg_setup(VCPU_SREG_ES);
2733         seg_setup(VCPU_SREG_FS);
2734         seg_setup(VCPU_SREG_GS);
2735         seg_setup(VCPU_SREG_SS);
2736
2737         vmcs_write16(GUEST_TR_SELECTOR, 0);
2738         vmcs_writel(GUEST_TR_BASE, 0);
2739         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2740         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2741
2742         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2743         vmcs_writel(GUEST_LDTR_BASE, 0);
2744         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2745         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2746
2747         vmcs_write32(GUEST_SYSENTER_CS, 0);
2748         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2749         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2750
2751         vmcs_writel(GUEST_RFLAGS, 0x02);
2752         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2753                 kvm_rip_write(vcpu, 0xfff0);
2754         else
2755                 kvm_rip_write(vcpu, 0);
2756         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2757
2758         vmcs_writel(GUEST_DR7, 0x400);
2759
2760         vmcs_writel(GUEST_GDTR_BASE, 0);
2761         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2762
2763         vmcs_writel(GUEST_IDTR_BASE, 0);
2764         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2765
2766         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2767         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2768         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2769
2770         /* Special registers */
2771         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2772
2773         setup_msrs(vmx);
2774
2775         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2776
2777         if (cpu_has_vmx_tpr_shadow()) {
2778                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2779                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2780                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2781                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2782                 vmcs_write32(TPR_THRESHOLD, 0);
2783         }
2784
2785         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2786                 vmcs_write64(APIC_ACCESS_ADDR,
2787                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2788
2789         if (vmx->vpid != 0)
2790                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2791
2792         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2793         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2794         vmx_set_cr4(&vmx->vcpu, 0);
2795         vmx_set_efer(&vmx->vcpu, 0);
2796         vmx_fpu_activate(&vmx->vcpu);
2797         update_exception_bitmap(&vmx->vcpu);
2798
2799         vpid_sync_context(vmx);
2800
2801         ret = 0;
2802
2803         /* HACK: Don't enable emulation on guest boot/reset */
2804         vmx->emulation_required = 0;
2805
2806 out:
2807         return ret;
2808 }
2809
2810 static void enable_irq_window(struct kvm_vcpu *vcpu)
2811 {
2812         u32 cpu_based_vm_exec_control;
2813
2814         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2815         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2816         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2817 }
2818
2819 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2820 {
2821         u32 cpu_based_vm_exec_control;
2822
2823         if (!cpu_has_virtual_nmis()) {
2824                 enable_irq_window(vcpu);
2825                 return;
2826         }
2827
2828         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2829         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2830         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2831 }
2832
2833 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2834 {
2835         struct vcpu_vmx *vmx = to_vmx(vcpu);
2836         uint32_t intr;
2837         int irq = vcpu->arch.interrupt.nr;
2838
2839         trace_kvm_inj_virq(irq);
2840
2841         ++vcpu->stat.irq_injections;
2842         if (vmx->rmode.vm86_active) {
2843                 vmx->rmode.irq.pending = true;
2844                 vmx->rmode.irq.vector = irq;
2845                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2846                 if (vcpu->arch.interrupt.soft)
2847                         vmx->rmode.irq.rip +=
2848                                 vmx->vcpu.arch.event_exit_inst_len;
2849                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2850                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2851                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2852                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2853                 return;
2854         }
2855         intr = irq | INTR_INFO_VALID_MASK;
2856         if (vcpu->arch.interrupt.soft) {
2857                 intr |= INTR_TYPE_SOFT_INTR;
2858                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2859                              vmx->vcpu.arch.event_exit_inst_len);
2860         } else
2861                 intr |= INTR_TYPE_EXT_INTR;
2862         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2863 }
2864
2865 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2866 {
2867         struct vcpu_vmx *vmx = to_vmx(vcpu);
2868
2869         if (!cpu_has_virtual_nmis()) {
2870                 /*
2871                  * Tracking the NMI-blocked state in software is built upon
2872                  * finding the next open IRQ window. This, in turn, depends on
2873                  * well-behaving guests: They have to keep IRQs disabled at
2874                  * least as long as the NMI handler runs. Otherwise we may
2875                  * cause NMI nesting, maybe breaking the guest. But as this is
2876                  * highly unlikely, we can live with the residual risk.
2877                  */
2878                 vmx->soft_vnmi_blocked = 1;
2879                 vmx->vnmi_blocked_time = 0;
2880         }
2881
2882         ++vcpu->stat.nmi_injections;
2883         if (vmx->rmode.vm86_active) {
2884                 vmx->rmode.irq.pending = true;
2885                 vmx->rmode.irq.vector = NMI_VECTOR;
2886                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2887                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2888                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2889                              INTR_INFO_VALID_MASK);
2890                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2891                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2892                 return;
2893         }
2894         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2895                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2896 }
2897
2898 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2899 {
2900         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2901                 return 0;
2902
2903         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2904                         (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_NMI));
2905 }
2906
2907 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2908 {
2909         if (!cpu_has_virtual_nmis())
2910                 return to_vmx(vcpu)->soft_vnmi_blocked;
2911         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
2912 }
2913
2914 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2915 {
2916         struct vcpu_vmx *vmx = to_vmx(vcpu);
2917
2918         if (!cpu_has_virtual_nmis()) {
2919                 if (vmx->soft_vnmi_blocked != masked) {
2920                         vmx->soft_vnmi_blocked = masked;
2921                         vmx->vnmi_blocked_time = 0;
2922                 }
2923         } else {
2924                 if (masked)
2925                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2926                                       GUEST_INTR_STATE_NMI);
2927                 else
2928                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2929                                         GUEST_INTR_STATE_NMI);
2930         }
2931 }
2932
2933 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2934 {
2935         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2936                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2937                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2938 }
2939
2940 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2941 {
2942         int ret;
2943         struct kvm_userspace_memory_region tss_mem = {
2944                 .slot = TSS_PRIVATE_MEMSLOT,
2945                 .guest_phys_addr = addr,
2946                 .memory_size = PAGE_SIZE * 3,
2947                 .flags = 0,
2948         };
2949
2950         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2951         if (ret)
2952                 return ret;
2953         kvm->arch.tss_addr = addr;
2954         return 0;
2955 }
2956
2957 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2958                                   int vec, u32 err_code)
2959 {
2960         /*
2961          * Instruction with address size override prefix opcode 0x67
2962          * Cause the #SS fault with 0 error code in VM86 mode.
2963          */
2964         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2965                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2966                         return 1;
2967         /*
2968          * Forward all other exceptions that are valid in real mode.
2969          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2970          *        the required debugging infrastructure rework.
2971          */
2972         switch (vec) {
2973         case DB_VECTOR:
2974                 if (vcpu->guest_debug &
2975                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2976                         return 0;
2977                 kvm_queue_exception(vcpu, vec);
2978                 return 1;
2979         case BP_VECTOR:
2980                 /*
2981                  * Update instruction length as we may reinject the exception
2982                  * from user space while in guest debugging mode.
2983                  */
2984                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2985                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2986                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2987                         return 0;
2988                 /* fall through */
2989         case DE_VECTOR:
2990         case OF_VECTOR:
2991         case BR_VECTOR:
2992         case UD_VECTOR:
2993         case DF_VECTOR:
2994         case SS_VECTOR:
2995         case GP_VECTOR:
2996         case MF_VECTOR:
2997                 kvm_queue_exception(vcpu, vec);
2998                 return 1;
2999         }
3000         return 0;
3001 }
3002
3003 /*
3004  * Trigger machine check on the host. We assume all the MSRs are already set up
3005  * by the CPU and that we still run on the same CPU as the MCE occurred on.
3006  * We pass a fake environment to the machine check handler because we want
3007  * the guest to be always treated like user space, no matter what context
3008  * it used internally.
3009  */
3010 static void kvm_machine_check(void)
3011 {
3012 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3013         struct pt_regs regs = {
3014                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3015                 .flags = X86_EFLAGS_IF,
3016         };
3017
3018         do_machine_check(&regs, 0);
3019 #endif
3020 }
3021
3022 static int handle_machine_check(struct kvm_vcpu *vcpu)
3023 {
3024         /* already handled by vcpu_run */
3025         return 1;
3026 }
3027
3028 static int handle_exception(struct kvm_vcpu *vcpu)
3029 {
3030         struct vcpu_vmx *vmx = to_vmx(vcpu);
3031         struct kvm_run *kvm_run = vcpu->run;
3032         u32 intr_info, ex_no, error_code;
3033         unsigned long cr2, rip, dr6;
3034         u32 vect_info;
3035         enum emulation_result er;
3036
3037         vect_info = vmx->idt_vectoring_info;
3038         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3039
3040         if (is_machine_check(intr_info))
3041                 return handle_machine_check(vcpu);
3042
3043         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3044             !is_page_fault(intr_info)) {
3045                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3046                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3047                 vcpu->run->internal.ndata = 2;
3048                 vcpu->run->internal.data[0] = vect_info;
3049                 vcpu->run->internal.data[1] = intr_info;
3050                 return 0;
3051         }
3052
3053         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3054                 return 1;  /* already handled by vmx_vcpu_run() */
3055
3056         if (is_no_device(intr_info)) {
3057                 vmx_fpu_activate(vcpu);
3058                 return 1;
3059         }
3060
3061         if (is_invalid_opcode(intr_info)) {
3062                 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
3063                 if (er != EMULATE_DONE)
3064                         kvm_queue_exception(vcpu, UD_VECTOR);
3065                 return 1;
3066         }
3067
3068         error_code = 0;
3069         rip = kvm_rip_read(vcpu);
3070         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3071                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3072         if (is_page_fault(intr_info)) {
3073                 /* EPT won't cause page fault directly */
3074                 if (enable_ept)
3075                         BUG();
3076                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3077                 trace_kvm_page_fault(cr2, error_code);
3078
3079                 if (kvm_event_needs_reinjection(vcpu))
3080                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
3081                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
3082         }
3083
3084         if (vmx->rmode.vm86_active &&
3085             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3086                                                                 error_code)) {
3087                 if (vcpu->arch.halt_request) {
3088                         vcpu->arch.halt_request = 0;
3089                         return kvm_emulate_halt(vcpu);
3090                 }
3091                 return 1;
3092         }
3093
3094         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3095         switch (ex_no) {
3096         case DB_VECTOR:
3097                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3098                 if (!(vcpu->guest_debug &
3099                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3100                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3101                         kvm_queue_exception(vcpu, DB_VECTOR);
3102                         return 1;
3103                 }
3104                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3105                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3106                 /* fall through */
3107         case BP_VECTOR:
3108                 /*
3109                  * Update instruction length as we may reinject #BP from
3110                  * user space while in guest debugging mode. Reading it for
3111                  * #DB as well causes no harm, it is not used in that case.
3112                  */
3113                 vmx->vcpu.arch.event_exit_inst_len =
3114                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3115                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3116                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3117                 kvm_run->debug.arch.exception = ex_no;
3118                 break;
3119         default:
3120                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3121                 kvm_run->ex.exception = ex_no;
3122                 kvm_run->ex.error_code = error_code;
3123                 break;
3124         }
3125         return 0;
3126 }
3127
3128 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3129 {
3130         ++vcpu->stat.irq_exits;
3131         return 1;
3132 }
3133
3134 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3135 {
3136         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3137         return 0;
3138 }
3139
3140 static int handle_io(struct kvm_vcpu *vcpu)
3141 {
3142         unsigned long exit_qualification;
3143         int size, in, string;
3144         unsigned port;
3145
3146         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3147         string = (exit_qualification & 16) != 0;
3148         in = (exit_qualification & 8) != 0;
3149
3150         ++vcpu->stat.io_exits;
3151
3152         if (string || in)
3153                 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3154
3155         port = exit_qualification >> 16;
3156         size = (exit_qualification & 7) + 1;
3157         skip_emulated_instruction(vcpu);
3158
3159         return kvm_fast_pio_out(vcpu, size, port);
3160 }
3161
3162 static void
3163 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3164 {
3165         /*
3166          * Patch in the VMCALL instruction:
3167          */
3168         hypercall[0] = 0x0f;
3169         hypercall[1] = 0x01;
3170         hypercall[2] = 0xc1;
3171 }
3172
3173 static void complete_insn_gp(struct kvm_vcpu *vcpu, int err)
3174 {
3175         if (err)
3176                 kvm_inject_gp(vcpu, 0);
3177         else
3178                 skip_emulated_instruction(vcpu);
3179 }
3180
3181 static int handle_cr(struct kvm_vcpu *vcpu)
3182 {
3183         unsigned long exit_qualification, val;
3184         int cr;
3185         int reg;
3186         int err;
3187
3188         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3189         cr = exit_qualification & 15;
3190         reg = (exit_qualification >> 8) & 15;
3191         switch ((exit_qualification >> 4) & 3) {
3192         case 0: /* mov to cr */
3193                 val = kvm_register_read(vcpu, reg);
3194                 trace_kvm_cr_write(cr, val);
3195                 switch (cr) {
3196                 case 0:
3197                         err = kvm_set_cr0(vcpu, val);
3198                         complete_insn_gp(vcpu, err);
3199                         return 1;
3200                 case 3:
3201                         err = kvm_set_cr3(vcpu, val);
3202                         complete_insn_gp(vcpu, err);
3203                         return 1;
3204                 case 4:
3205                         err = kvm_set_cr4(vcpu, val);
3206                         complete_insn_gp(vcpu, err);
3207                         return 1;
3208                 case 8: {
3209                                 u8 cr8_prev = kvm_get_cr8(vcpu);
3210                                 u8 cr8 = kvm_register_read(vcpu, reg);
3211                                 kvm_set_cr8(vcpu, cr8);
3212                                 skip_emulated_instruction(vcpu);
3213                                 if (irqchip_in_kernel(vcpu->kvm))
3214                                         return 1;
3215                                 if (cr8_prev <= cr8)
3216                                         return 1;
3217                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3218                                 return 0;
3219                         }
3220                 };
3221                 break;
3222         case 2: /* clts */
3223                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3224                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3225                 skip_emulated_instruction(vcpu);
3226                 vmx_fpu_activate(vcpu);
3227                 return 1;
3228         case 1: /*mov from cr*/
3229                 switch (cr) {
3230                 case 3:
3231                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
3232                         trace_kvm_cr_read(cr, vcpu->arch.cr3);
3233                         skip_emulated_instruction(vcpu);
3234                         return 1;
3235                 case 8:
3236                         val = kvm_get_cr8(vcpu);
3237                         kvm_register_write(vcpu, reg, val);
3238                         trace_kvm_cr_read(cr, val);
3239                         skip_emulated_instruction(vcpu);
3240                         return 1;
3241                 }
3242                 break;
3243         case 3: /* lmsw */
3244                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3245                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3246                 kvm_lmsw(vcpu, val);
3247
3248                 skip_emulated_instruction(vcpu);
3249                 return 1;
3250         default:
3251                 break;
3252         }
3253         vcpu->run->exit_reason = 0;
3254         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3255                (int)(exit_qualification >> 4) & 3, cr);
3256         return 0;
3257 }
3258
3259 static int handle_dr(struct kvm_vcpu *vcpu)
3260 {
3261         unsigned long exit_qualification;
3262         int dr, reg;
3263
3264         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3265         if (!kvm_require_cpl(vcpu, 0))
3266                 return 1;
3267         dr = vmcs_readl(GUEST_DR7);
3268         if (dr & DR7_GD) {
3269                 /*
3270                  * As the vm-exit takes precedence over the debug trap, we
3271                  * need to emulate the latter, either for the host or the
3272                  * guest debugging itself.
3273                  */
3274                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3275                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3276                         vcpu->run->debug.arch.dr7 = dr;
3277                         vcpu->run->debug.arch.pc =
3278                                 vmcs_readl(GUEST_CS_BASE) +
3279                                 vmcs_readl(GUEST_RIP);
3280                         vcpu->run->debug.arch.exception = DB_VECTOR;
3281                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3282                         return 0;
3283                 } else {
3284                         vcpu->arch.dr7 &= ~DR7_GD;
3285                         vcpu->arch.dr6 |= DR6_BD;
3286                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3287                         kvm_queue_exception(vcpu, DB_VECTOR);
3288                         return 1;
3289                 }
3290         }
3291
3292         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3293         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3294         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3295         if (exit_qualification & TYPE_MOV_FROM_DR) {
3296                 unsigned long val;
3297                 if (!kvm_get_dr(vcpu, dr, &val))
3298                         kvm_register_write(vcpu, reg, val);
3299         } else
3300                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3301         skip_emulated_instruction(vcpu);
3302         return 1;
3303 }
3304
3305 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3306 {
3307         vmcs_writel(GUEST_DR7, val);
3308 }
3309
3310 static int handle_cpuid(struct kvm_vcpu *vcpu)
3311 {
3312         kvm_emulate_cpuid(vcpu);
3313         return 1;
3314 }
3315
3316 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3317 {
3318         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3319         u64 data;
3320
3321         if (vmx_get_msr(vcpu, ecx, &data)) {
3322                 trace_kvm_msr_read_ex(ecx);
3323                 kvm_inject_gp(vcpu, 0);
3324                 return 1;
3325         }
3326
3327         trace_kvm_msr_read(ecx, data);
3328
3329         /* FIXME: handling of bits 32:63 of rax, rdx */
3330         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3331         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3332         skip_emulated_instruction(vcpu);
3333         return 1;
3334 }
3335
3336 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3337 {
3338         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3339         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3340                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3341
3342         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3343                 trace_kvm_msr_write_ex(ecx, data);
3344                 kvm_inject_gp(vcpu, 0);
3345                 return 1;
3346         }
3347
3348         trace_kvm_msr_write(ecx, data);
3349         skip_emulated_instruction(vcpu);
3350         return 1;
3351 }
3352
3353 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3354 {
3355         return 1;
3356 }
3357
3358 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3359 {
3360         u32 cpu_based_vm_exec_control;
3361
3362         /* clear pending irq */
3363         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3364         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3365         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3366
3367         ++vcpu->stat.irq_window_exits;
3368
3369         /*
3370          * If the user space waits to inject interrupts, exit as soon as
3371          * possible
3372          */
3373         if (!irqchip_in_kernel(vcpu->kvm) &&
3374             vcpu->run->request_interrupt_window &&
3375             !kvm_cpu_has_interrupt(vcpu)) {
3376                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3377                 return 0;
3378         }
3379         return 1;
3380 }
3381
3382 static int handle_halt(struct kvm_vcpu *vcpu)
3383 {
3384         skip_emulated_instruction(vcpu);
3385         return kvm_emulate_halt(vcpu);
3386 }
3387
3388 static int handle_vmcall(struct kvm_vcpu *vcpu)
3389 {
3390         skip_emulated_instruction(vcpu);
3391         kvm_emulate_hypercall(vcpu);
3392         return 1;
3393 }
3394
3395 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3396 {
3397         kvm_queue_exception(vcpu, UD_VECTOR);
3398         return 1;
3399 }
3400
3401 static int handle_invlpg(struct kvm_vcpu *vcpu)
3402 {
3403         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3404
3405         kvm_mmu_invlpg(vcpu, exit_qualification);
3406         skip_emulated_instruction(vcpu);
3407         return 1;
3408 }
3409
3410 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3411 {
3412         skip_emulated_instruction(vcpu);
3413         kvm_emulate_wbinvd(vcpu);
3414         return 1;
3415 }
3416
3417 static int handle_xsetbv(struct kvm_vcpu *vcpu)
3418 {
3419         u64 new_bv = kvm_read_edx_eax(vcpu);
3420         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3421
3422         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3423                 skip_emulated_instruction(vcpu);
3424         return 1;
3425 }
3426
3427 static int handle_apic_access(struct kvm_vcpu *vcpu)
3428 {
3429         return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3430 }
3431
3432 static int handle_task_switch(struct kvm_vcpu *vcpu)
3433 {
3434         struct vcpu_vmx *vmx = to_vmx(vcpu);
3435         unsigned long exit_qualification;
3436         bool has_error_code = false;
3437         u32 error_code = 0;
3438         u16 tss_selector;
3439         int reason, type, idt_v;
3440
3441         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3442         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3443
3444         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3445
3446         reason = (u32)exit_qualification >> 30;
3447         if (reason == TASK_SWITCH_GATE && idt_v) {
3448                 switch (type) {
3449                 case INTR_TYPE_NMI_INTR:
3450                         vcpu->arch.nmi_injected = false;
3451                         if (cpu_has_virtual_nmis())
3452                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3453                                               GUEST_INTR_STATE_NMI);
3454                         break;
3455                 case INTR_TYPE_EXT_INTR:
3456                 case INTR_TYPE_SOFT_INTR:
3457                         kvm_clear_interrupt_queue(vcpu);
3458                         break;
3459                 case INTR_TYPE_HARD_EXCEPTION:
3460                         if (vmx->idt_vectoring_info &
3461                             VECTORING_INFO_DELIVER_CODE_MASK) {
3462                                 has_error_code = true;
3463                                 error_code =
3464                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
3465                         }
3466                         /* fall through */
3467                 case INTR_TYPE_SOFT_EXCEPTION:
3468                         kvm_clear_exception_queue(vcpu);
3469                         break;
3470                 default:
3471                         break;
3472                 }
3473         }
3474         tss_selector = exit_qualification;
3475
3476         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3477                        type != INTR_TYPE_EXT_INTR &&
3478                        type != INTR_TYPE_NMI_INTR))
3479                 skip_emulated_instruction(vcpu);
3480
3481         if (kvm_task_switch(vcpu, tss_selector, reason,
3482                                 has_error_code, error_code) == EMULATE_FAIL) {
3483                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3484                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3485                 vcpu->run->internal.ndata = 0;
3486                 return 0;
3487         }
3488
3489         /* clear all local breakpoint enable flags */
3490         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3491
3492         /*
3493          * TODO: What about debug traps on tss switch?
3494          *       Are we supposed to inject them and update dr6?
3495          */
3496
3497         return 1;
3498 }
3499
3500 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3501 {
3502         unsigned long exit_qualification;
3503         gpa_t gpa;
3504         int gla_validity;
3505
3506         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3507
3508         if (exit_qualification & (1 << 6)) {
3509                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3510                 return -EINVAL;
3511         }
3512
3513         gla_validity = (exit_qualification >> 7) & 0x3;
3514         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3515                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3516                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3517                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3518                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3519                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3520                         (long unsigned int)exit_qualification);
3521                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3522                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3523                 return 0;
3524         }
3525
3526         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3527         trace_kvm_page_fault(gpa, exit_qualification);
3528         return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3529 }
3530
3531 static u64 ept_rsvd_mask(u64 spte, int level)
3532 {
3533         int i;
3534         u64 mask = 0;
3535
3536         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3537                 mask |= (1ULL << i);
3538
3539         if (level > 2)
3540                 /* bits 7:3 reserved */
3541                 mask |= 0xf8;
3542         else if (level == 2) {
3543                 if (spte & (1ULL << 7))
3544                         /* 2MB ref, bits 20:12 reserved */
3545                         mask |= 0x1ff000;
3546                 else
3547                         /* bits 6:3 reserved */
3548                         mask |= 0x78;
3549         }
3550
3551         return mask;
3552 }
3553
3554 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3555                                        int level)
3556 {
3557         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3558
3559         /* 010b (write-only) */
3560         WARN_ON((spte & 0x7) == 0x2);
3561
3562         /* 110b (write/execute) */
3563         WARN_ON((spte & 0x7) == 0x6);
3564
3565         /* 100b (execute-only) and value not supported by logical processor */
3566         if (!cpu_has_vmx_ept_execute_only())
3567                 WARN_ON((spte & 0x7) == 0x4);
3568
3569         /* not 000b */
3570         if ((spte & 0x7)) {
3571                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3572
3573                 if (rsvd_bits != 0) {
3574                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3575                                          __func__, rsvd_bits);
3576                         WARN_ON(1);
3577                 }
3578
3579                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3580                         u64 ept_mem_type = (spte & 0x38) >> 3;
3581
3582                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3583                             ept_mem_type == 7) {
3584                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3585                                                 __func__, ept_mem_type);
3586                                 WARN_ON(1);
3587                         }
3588                 }
3589         }
3590 }
3591
3592 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3593 {
3594         u64 sptes[4];
3595         int nr_sptes, i;
3596         gpa_t gpa;
3597
3598         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3599
3600         printk(KERN_ERR "EPT: Misconfiguration.\n");
3601         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3602
3603         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3604
3605         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3606                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3607
3608         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3609         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3610
3611         return 0;
3612 }
3613
3614 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3615 {
3616         u32 cpu_based_vm_exec_control;
3617
3618         /* clear pending NMI */
3619         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3620         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3621         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3622         ++vcpu->stat.nmi_window_exits;
3623
3624         return 1;
3625 }
3626
3627 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3628 {
3629         struct vcpu_vmx *vmx = to_vmx(vcpu);
3630         enum emulation_result err = EMULATE_DONE;
3631         int ret = 1;
3632
3633         while (!guest_state_valid(vcpu)) {
3634                 err = emulate_instruction(vcpu, 0, 0, 0);
3635
3636                 if (err == EMULATE_DO_MMIO) {
3637                         ret = 0;
3638                         goto out;
3639                 }
3640
3641                 if (err != EMULATE_DONE)
3642                         return 0;
3643
3644                 if (signal_pending(current))
3645                         goto out;
3646                 if (need_resched())
3647                         schedule();
3648         }
3649
3650         vmx->emulation_required = 0;
3651 out:
3652         return ret;
3653 }
3654
3655 /*
3656  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3657  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3658  */
3659 static int handle_pause(struct kvm_vcpu *vcpu)
3660 {
3661         skip_emulated_instruction(vcpu);
3662         kvm_vcpu_on_spin(vcpu);
3663
3664         return 1;
3665 }
3666
3667 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3668 {
3669         kvm_queue_exception(vcpu, UD_VECTOR);
3670         return 1;
3671 }
3672
3673 /*
3674  * The exit handlers return 1 if the exit was handled fully and guest execution
3675  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3676  * to be done to userspace and return 0.
3677  */
3678 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3679         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3680         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3681         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3682         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3683         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3684         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3685         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3686         [EXIT_REASON_CPUID]                   = handle_cpuid,
3687         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3688         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3689         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3690         [EXIT_REASON_HLT]                     = handle_halt,
3691         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3692         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3693         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3694         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3695         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3696         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3697         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3698         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3699         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3700         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3701         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3702         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3703         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3704         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3705         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
3706         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3707         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3708         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3709         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
3710         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
3711         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
3712         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
3713 };
3714
3715 static const int kvm_vmx_max_exit_handlers =
3716         ARRAY_SIZE(kvm_vmx_exit_handlers);
3717
3718 /*
3719  * The guest has exited.  See if we can fix it or if we need userspace
3720  * assistance.
3721  */
3722 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3723 {
3724         struct vcpu_vmx *vmx = to_vmx(vcpu);
3725         u32 exit_reason = vmx->exit_reason;
3726         u32 vectoring_info = vmx->idt_vectoring_info;
3727
3728         trace_kvm_exit(exit_reason, vcpu);
3729
3730         /* If guest state is invalid, start emulating */
3731         if (vmx->emulation_required && emulate_invalid_guest_state)
3732                 return handle_invalid_guest_state(vcpu);
3733
3734         /* Access CR3 don't cause VMExit in paging mode, so we need
3735          * to sync with guest real CR3. */
3736         if (enable_ept && is_paging(vcpu))
3737                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3738
3739         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3740                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3741                 vcpu->run->fail_entry.hardware_entry_failure_reason
3742                         = exit_reason;
3743                 return 0;
3744         }
3745
3746         if (unlikely(vmx->fail)) {
3747                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3748                 vcpu->run->fail_entry.hardware_entry_failure_reason
3749                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3750                 return 0;
3751         }
3752
3753         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3754                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3755                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3756                         exit_reason != EXIT_REASON_TASK_SWITCH))
3757                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3758                        "(0x%x) and exit reason is 0x%x\n",
3759                        __func__, vectoring_info, exit_reason);
3760
3761         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3762                 if (vmx_interrupt_allowed(vcpu)) {
3763                         vmx->soft_vnmi_blocked = 0;
3764                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3765                            vcpu->arch.nmi_pending) {
3766                         /*
3767                          * This CPU don't support us in finding the end of an
3768                          * NMI-blocked window if the guest runs with IRQs
3769                          * disabled. So we pull the trigger after 1 s of
3770                          * futile waiting, but inform the user about this.
3771                          */
3772                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3773                                "state on VCPU %d after 1 s timeout\n",
3774                                __func__, vcpu->vcpu_id);
3775                         vmx->soft_vnmi_blocked = 0;
3776                 }
3777         }
3778
3779         if (exit_reason < kvm_vmx_max_exit_handlers
3780             && kvm_vmx_exit_handlers[exit_reason])
3781                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3782         else {
3783                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3784                 vcpu->run->hw.hardware_exit_reason = exit_reason;
3785         }
3786         return 0;
3787 }
3788
3789 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3790 {
3791         if (irr == -1 || tpr < irr) {
3792                 vmcs_write32(TPR_THRESHOLD, 0);
3793                 return;
3794         }
3795
3796         vmcs_write32(TPR_THRESHOLD, irr);
3797 }
3798
3799 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3800 {
3801         u32 exit_intr_info;
3802         u32 idt_vectoring_info = vmx->idt_vectoring_info;
3803         bool unblock_nmi;
3804         u8 vector;
3805         int type;
3806         bool idtv_info_valid;
3807
3808         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3809
3810         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3811
3812         /* Handle machine checks before interrupts are enabled */
3813         if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3814             || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3815                 && is_machine_check(exit_intr_info)))
3816                 kvm_machine_check();
3817
3818         /* We need to handle NMIs before interrupts are enabled */
3819         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3820             (exit_intr_info & INTR_INFO_VALID_MASK)) {
3821                 kvm_before_handle_nmi(&vmx->vcpu);
3822                 asm("int $2");
3823                 kvm_after_handle_nmi(&vmx->vcpu);
3824         }
3825
3826         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3827
3828         if (cpu_has_virtual_nmis()) {
3829                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3830                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3831                 /*
3832                  * SDM 3: 27.7.1.2 (September 2008)
3833                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3834                  * a guest IRET fault.
3835                  * SDM 3: 23.2.2 (September 2008)
3836                  * Bit 12 is undefined in any of the following cases:
3837                  *  If the VM exit sets the valid bit in the IDT-vectoring
3838                  *   information field.
3839                  *  If the VM exit is due to a double fault.
3840                  */
3841                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3842                     vector != DF_VECTOR && !idtv_info_valid)
3843                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3844                                       GUEST_INTR_STATE_NMI);
3845         } else if (unlikely(vmx->soft_vnmi_blocked))
3846                 vmx->vnmi_blocked_time +=
3847                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3848
3849         vmx->vcpu.arch.nmi_injected = false;
3850         kvm_clear_exception_queue(&vmx->vcpu);
3851         kvm_clear_interrupt_queue(&vmx->vcpu);
3852
3853         if (!idtv_info_valid)
3854                 return;
3855
3856         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3857         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3858
3859         switch (type) {
3860         case INTR_TYPE_NMI_INTR:
3861                 vmx->vcpu.arch.nmi_injected = true;
3862                 /*
3863                  * SDM 3: 27.7.1.2 (September 2008)
3864                  * Clear bit "block by NMI" before VM entry if a NMI
3865                  * delivery faulted.
3866                  */
3867                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3868                                 GUEST_INTR_STATE_NMI);
3869                 break;
3870         case INTR_TYPE_SOFT_EXCEPTION:
3871                 vmx->vcpu.arch.event_exit_inst_len =
3872                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3873                 /* fall through */
3874         case INTR_TYPE_HARD_EXCEPTION:
3875                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3876                         u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3877                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
3878                 } else
3879                         kvm_queue_exception(&vmx->vcpu, vector);
3880                 break;
3881         case INTR_TYPE_SOFT_INTR:
3882                 vmx->vcpu.arch.event_exit_inst_len =
3883                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3884                 /* fall through */
3885         case INTR_TYPE_EXT_INTR:
3886                 kvm_queue_interrupt(&vmx->vcpu, vector,
3887                         type == INTR_TYPE_SOFT_INTR);
3888                 break;
3889         default:
3890                 break;
3891         }
3892 }
3893
3894 /*
3895  * Failure to inject an interrupt should give us the information
3896  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3897  * when fetching the interrupt redirection bitmap in the real-mode
3898  * tss, this doesn't happen.  So we do it ourselves.
3899  */
3900 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3901 {
3902         vmx->rmode.irq.pending = 0;
3903         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3904                 return;
3905         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3906         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3907                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3908                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3909                 return;
3910         }
3911         vmx->idt_vectoring_info =
3912                 VECTORING_INFO_VALID_MASK
3913                 | INTR_TYPE_EXT_INTR
3914                 | vmx->rmode.irq.vector;
3915 }
3916
3917 #ifdef CONFIG_X86_64
3918 #define R "r"
3919 #define Q "q"
3920 #else
3921 #define R "e"
3922 #define Q "l"
3923 #endif
3924
3925 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3926 {
3927         struct vcpu_vmx *vmx = to_vmx(vcpu);
3928
3929         /* Record the guest's net vcpu time for enforced NMI injections. */
3930         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3931                 vmx->entry_time = ktime_get();
3932
3933         /* Don't enter VMX if guest state is invalid, let the exit handler
3934            start emulation until we arrive back to a valid state */
3935         if (vmx->emulation_required && emulate_invalid_guest_state)
3936                 return;
3937
3938         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3939                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3940         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3941                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3942
3943         /* When single-stepping over STI and MOV SS, we must clear the
3944          * corresponding interruptibility bits in the guest state. Otherwise
3945          * vmentry fails as it then expects bit 14 (BS) in pending debug
3946          * exceptions being set, but that's not correct for the guest debugging
3947          * case. */
3948         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3949                 vmx_set_interrupt_shadow(vcpu, 0);
3950
3951         asm(
3952                 /* Store host registers */
3953                 "push %%"R"dx; push %%"R"bp;"
3954                 "push %%"R"cx \n\t"
3955                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3956                 "je 1f \n\t"
3957                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3958                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3959                 "1: \n\t"
3960                 /* Reload cr2 if changed */
3961                 "mov %c[cr2](%0), %%"R"ax \n\t"
3962                 "mov %%cr2, %%"R"dx \n\t"
3963                 "cmp %%"R"ax, %%"R"dx \n\t"
3964                 "je 2f \n\t"
3965                 "mov %%"R"ax, %%cr2 \n\t"
3966                 "2: \n\t"
3967                 /* Check if vmlaunch of vmresume is needed */
3968                 "cmpl $0, %c[launched](%0) \n\t"
3969                 /* Load guest registers.  Don't clobber flags. */
3970                 "mov %c[rax](%0), %%"R"ax \n\t"
3971                 "mov %c[rbx](%0), %%"R"bx \n\t"
3972                 "mov %c[rdx](%0), %%"R"dx \n\t"
3973                 "mov %c[rsi](%0), %%"R"si \n\t"
3974                 "mov %c[rdi](%0), %%"R"di \n\t"
3975                 "mov %c[rbp](%0), %%"R"bp \n\t"
3976 #ifdef CONFIG_X86_64
3977                 "mov %c[r8](%0),  %%r8  \n\t"
3978                 "mov %c[r9](%0),  %%r9  \n\t"
3979                 "mov %c[r10](%0), %%r10 \n\t"
3980                 "mov %c[r11](%0), %%r11 \n\t"
3981                 "mov %c[r12](%0), %%r12 \n\t"
3982                 "mov %c[r13](%0), %%r13 \n\t"
3983                 "mov %c[r14](%0), %%r14 \n\t"
3984                 "mov %c[r15](%0), %%r15 \n\t"
3985 #endif
3986                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3987
3988                 /* Enter guest mode */
3989                 "jne .Llaunched \n\t"
3990                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3991                 "jmp .Lkvm_vmx_return \n\t"
3992                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3993                 ".Lkvm_vmx_return: "
3994                 /* Save guest registers, load host registers, keep flags */
3995                 "xchg %0,     (%%"R"sp) \n\t"
3996                 "mov %%"R"ax, %c[rax](%0) \n\t"
3997                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3998                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3999                 "mov %%"R"dx, %c[rdx](%0) \n\t"
4000                 "mov %%"R"si, %c[rsi](%0) \n\t"
4001                 "mov %%"R"di, %c[rdi](%0) \n\t"
4002                 "mov %%"R"bp, %c[rbp](%0) \n\t"
4003 #ifdef CONFIG_X86_64
4004                 "mov %%r8,  %c[r8](%0) \n\t"
4005                 "mov %%r9,  %c[r9](%0) \n\t"
4006                 "mov %%r10, %c[r10](%0) \n\t"
4007                 "mov %%r11, %c[r11](%0) \n\t"
4008                 "mov %%r12, %c[r12](%0) \n\t"
4009                 "mov %%r13, %c[r13](%0) \n\t"
4010                 "mov %%r14, %c[r14](%0) \n\t"
4011                 "mov %%r15, %c[r15](%0) \n\t"
4012 #endif
4013                 "mov %%cr2, %%"R"ax   \n\t"
4014                 "mov %%"R"ax, %c[cr2](%0) \n\t"
4015
4016                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
4017                 "setbe %c[fail](%0) \n\t"
4018               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4019                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4020                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
4021                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
4022                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4023                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4024                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4025                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4026                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4027                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4028                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
4029 #ifdef CONFIG_X86_64
4030                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4031                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4032                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4033                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4034                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4035                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4036                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4037                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
4038 #endif
4039                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
4040               : "cc", "memory"
4041                 , R"bx", R"di", R"si"
4042 #ifdef CONFIG_X86_64
4043                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4044 #endif
4045               );
4046
4047         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4048                                   | (1 << VCPU_EXREG_PDPTR));
4049         vcpu->arch.regs_dirty = 0;
4050
4051         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4052         if (vmx->rmode.irq.pending)
4053                 fixup_rmode_irq(vmx);
4054
4055         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
4056         vmx->launched = 1;
4057
4058         vmx_complete_interrupts(vmx);
4059 }
4060
4061 #undef R
4062 #undef Q
4063
4064 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4065 {
4066         struct vcpu_vmx *vmx = to_vmx(vcpu);
4067
4068         if (vmx->vmcs) {
4069                 vcpu_clear(vmx);
4070                 free_vmcs(vmx->vmcs);
4071                 vmx->vmcs = NULL;
4072         }
4073 }
4074
4075 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4076 {
4077         struct vcpu_vmx *vmx = to_vmx(vcpu);
4078
4079         free_vpid(vmx);
4080         vmx_free_vmcs(vcpu);
4081         kfree(vmx->guest_msrs);
4082         kvm_vcpu_uninit(vcpu);
4083         kmem_cache_free(kvm_vcpu_cache, vmx);
4084 }
4085
4086 static inline void vmcs_init(struct vmcs *vmcs)
4087 {
4088         u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4089
4090         if (!vmm_exclusive)
4091                 kvm_cpu_vmxon(phys_addr);
4092
4093         vmcs_clear(vmcs);
4094
4095         if (!vmm_exclusive)
4096                 kvm_cpu_vmxoff();
4097 }
4098
4099 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4100 {
4101         int err;
4102         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4103         int cpu;
4104
4105         if (!vmx)
4106                 return ERR_PTR(-ENOMEM);
4107
4108         allocate_vpid(vmx);
4109
4110         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4111         if (err)
4112                 goto free_vcpu;
4113
4114         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4115         if (!vmx->guest_msrs) {
4116                 err = -ENOMEM;
4117                 goto uninit_vcpu;
4118         }
4119
4120         vmx->vmcs = alloc_vmcs();
4121         if (!vmx->vmcs)
4122                 goto free_msrs;
4123
4124         vmcs_init(vmx->vmcs);
4125
4126         cpu = get_cpu();
4127         vmx_vcpu_load(&vmx->vcpu, cpu);
4128         err = vmx_vcpu_setup(vmx);
4129         vmx_vcpu_put(&vmx->vcpu);
4130         put_cpu();
4131         if (err)
4132                 goto free_vmcs;
4133         if (vm_need_virtualize_apic_accesses(kvm))
4134                 if (alloc_apic_access_page(kvm) != 0)
4135                         goto free_vmcs;
4136
4137         if (enable_ept) {
4138                 if (!kvm->arch.ept_identity_map_addr)
4139                         kvm->arch.ept_identity_map_addr =
4140                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4141                 if (alloc_identity_pagetable(kvm) != 0)
4142                         goto free_vmcs;
4143         }
4144
4145         return &vmx->vcpu;
4146
4147 free_vmcs:
4148         free_vmcs(vmx->vmcs);
4149 free_msrs:
4150         kfree(vmx->guest_msrs);
4151 uninit_vcpu:
4152         kvm_vcpu_uninit(&vmx->vcpu);
4153 free_vcpu:
4154         free_vpid(vmx);
4155         kmem_cache_free(kvm_vcpu_cache, vmx);
4156         return ERR_PTR(err);
4157 }
4158
4159 static void __init vmx_check_processor_compat(void *rtn)
4160 {
4161         struct vmcs_config vmcs_conf;
4162
4163         *(int *)rtn = 0;
4164         if (setup_vmcs_config(&vmcs_conf) < 0)
4165                 *(int *)rtn = -EIO;
4166         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4167                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4168                                 smp_processor_id());
4169                 *(int *)rtn = -EIO;
4170         }
4171 }
4172
4173 static int get_ept_level(void)
4174 {
4175         return VMX_EPT_DEFAULT_GAW + 1;
4176 }
4177
4178 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4179 {
4180         u64 ret;
4181
4182         /* For VT-d and EPT combination
4183          * 1. MMIO: always map as UC
4184          * 2. EPT with VT-d:
4185          *   a. VT-d without snooping control feature: can't guarantee the
4186          *      result, try to trust guest.
4187          *   b. VT-d with snooping control feature: snooping control feature of
4188          *      VT-d engine can guarantee the cache correctness. Just set it
4189          *      to WB to keep consistent with host. So the same as item 3.
4190          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4191          *    consistent with host MTRR
4192          */
4193         if (is_mmio)
4194                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4195         else if (vcpu->kvm->arch.iommu_domain &&
4196                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4197                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4198                       VMX_EPT_MT_EPTE_SHIFT;
4199         else
4200                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4201                         | VMX_EPT_IPAT_BIT;
4202
4203         return ret;
4204 }
4205
4206 #define _ER(x) { EXIT_REASON_##x, #x }
4207
4208 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4209         _ER(EXCEPTION_NMI),
4210         _ER(EXTERNAL_INTERRUPT),
4211         _ER(TRIPLE_FAULT),
4212         _ER(PENDING_INTERRUPT),
4213         _ER(NMI_WINDOW),
4214         _ER(TASK_SWITCH),
4215         _ER(CPUID),
4216         _ER(HLT),
4217         _ER(INVLPG),
4218         _ER(RDPMC),
4219         _ER(RDTSC),
4220         _ER(VMCALL),
4221         _ER(VMCLEAR),
4222         _ER(VMLAUNCH),
4223         _ER(VMPTRLD),
4224         _ER(VMPTRST),
4225         _ER(VMREAD),
4226         _ER(VMRESUME),
4227         _ER(VMWRITE),
4228         _ER(VMOFF),
4229         _ER(VMON),
4230         _ER(CR_ACCESS),
4231         _ER(DR_ACCESS),
4232         _ER(IO_INSTRUCTION),
4233         _ER(MSR_READ),
4234         _ER(MSR_WRITE),
4235         _ER(MWAIT_INSTRUCTION),
4236         _ER(MONITOR_INSTRUCTION),
4237         _ER(PAUSE_INSTRUCTION),
4238         _ER(MCE_DURING_VMENTRY),
4239         _ER(TPR_BELOW_THRESHOLD),
4240         _ER(APIC_ACCESS),
4241         _ER(EPT_VIOLATION),
4242         _ER(EPT_MISCONFIG),
4243         _ER(WBINVD),
4244         { -1, NULL }
4245 };
4246
4247 #undef _ER
4248
4249 static int vmx_get_lpage_level(void)
4250 {
4251         if (enable_ept && !cpu_has_vmx_ept_1g_page())
4252                 return PT_DIRECTORY_LEVEL;
4253         else
4254                 /* For shadow and EPT supported 1GB page */
4255                 return PT_PDPE_LEVEL;
4256 }
4257
4258 static inline u32 bit(int bitno)
4259 {
4260         return 1 << (bitno & 31);
4261 }
4262
4263 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4264 {
4265         struct kvm_cpuid_entry2 *best;
4266         struct vcpu_vmx *vmx = to_vmx(vcpu);
4267         u32 exec_control;
4268
4269         vmx->rdtscp_enabled = false;
4270         if (vmx_rdtscp_supported()) {
4271                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4272                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4273                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4274                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4275                                 vmx->rdtscp_enabled = true;
4276                         else {
4277                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4278                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4279                                                 exec_control);
4280                         }
4281                 }
4282         }
4283 }
4284
4285 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4286 {
4287 }
4288
4289 static struct kvm_x86_ops vmx_x86_ops = {
4290         .cpu_has_kvm_support = cpu_has_kvm_support,
4291         .disabled_by_bios = vmx_disabled_by_bios,
4292         .hardware_setup = hardware_setup,
4293         .hardware_unsetup = hardware_unsetup,
4294         .check_processor_compatibility = vmx_check_processor_compat,
4295         .hardware_enable = hardware_enable,
4296         .hardware_disable = hardware_disable,
4297         .cpu_has_accelerated_tpr = report_flexpriority,
4298
4299         .vcpu_create = vmx_create_vcpu,
4300         .vcpu_free = vmx_free_vcpu,
4301         .vcpu_reset = vmx_vcpu_reset,
4302
4303         .prepare_guest_switch = vmx_save_host_state,
4304         .vcpu_load = vmx_vcpu_load,
4305         .vcpu_put = vmx_vcpu_put,
4306
4307         .set_guest_debug = set_guest_debug,
4308         .get_msr = vmx_get_msr,
4309         .set_msr = vmx_set_msr,
4310         .get_segment_base = vmx_get_segment_base,
4311         .get_segment = vmx_get_segment,
4312         .set_segment = vmx_set_segment,
4313         .get_cpl = vmx_get_cpl,
4314         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4315         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4316         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4317         .set_cr0 = vmx_set_cr0,
4318         .set_cr3 = vmx_set_cr3,
4319         .set_cr4 = vmx_set_cr4,
4320         .set_efer = vmx_set_efer,
4321         .get_idt = vmx_get_idt,
4322         .set_idt = vmx_set_idt,
4323         .get_gdt = vmx_get_gdt,
4324         .set_gdt = vmx_set_gdt,
4325         .set_dr7 = vmx_set_dr7,
4326         .cache_reg = vmx_cache_reg,
4327         .get_rflags = vmx_get_rflags,
4328         .set_rflags = vmx_set_rflags,
4329         .fpu_activate = vmx_fpu_activate,
4330         .fpu_deactivate = vmx_fpu_deactivate,
4331
4332         .tlb_flush = vmx_flush_tlb,
4333
4334         .run = vmx_vcpu_run,
4335         .handle_exit = vmx_handle_exit,
4336         .skip_emulated_instruction = skip_emulated_instruction,
4337         .set_interrupt_shadow = vmx_set_interrupt_shadow,
4338         .get_interrupt_shadow = vmx_get_interrupt_shadow,
4339         .patch_hypercall = vmx_patch_hypercall,
4340         .set_irq = vmx_inject_irq,
4341         .set_nmi = vmx_inject_nmi,
4342         .queue_exception = vmx_queue_exception,
4343         .interrupt_allowed = vmx_interrupt_allowed,
4344         .nmi_allowed = vmx_nmi_allowed,
4345         .get_nmi_mask = vmx_get_nmi_mask,
4346         .set_nmi_mask = vmx_set_nmi_mask,
4347         .enable_nmi_window = enable_nmi_window,
4348         .enable_irq_window = enable_irq_window,
4349         .update_cr8_intercept = update_cr8_intercept,
4350
4351         .set_tss_addr = vmx_set_tss_addr,
4352         .get_tdp_level = get_ept_level,
4353         .get_mt_mask = vmx_get_mt_mask,
4354
4355         .exit_reasons_str = vmx_exit_reasons_str,
4356         .get_lpage_level = vmx_get_lpage_level,
4357
4358         .cpuid_update = vmx_cpuid_update,
4359
4360         .rdtscp_supported = vmx_rdtscp_supported,
4361
4362         .set_supported_cpuid = vmx_set_supported_cpuid,
4363
4364         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
4365 };
4366
4367 static int __init vmx_init(void)
4368 {
4369         int r, i;
4370
4371         rdmsrl_safe(MSR_EFER, &host_efer);
4372
4373         for (i = 0; i < NR_VMX_MSR; ++i)
4374                 kvm_define_shared_msr(i, vmx_msr_index[i]);
4375
4376         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4377         if (!vmx_io_bitmap_a)
4378                 return -ENOMEM;
4379
4380         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4381         if (!vmx_io_bitmap_b) {
4382                 r = -ENOMEM;
4383                 goto out;
4384         }
4385
4386         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4387         if (!vmx_msr_bitmap_legacy) {
4388                 r = -ENOMEM;
4389                 goto out1;
4390         }
4391
4392         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4393         if (!vmx_msr_bitmap_longmode) {
4394                 r = -ENOMEM;
4395                 goto out2;
4396         }
4397
4398         /*
4399          * Allow direct access to the PC debug port (it is often used for I/O
4400          * delays, but the vmexits simply slow things down).
4401          */
4402         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4403         clear_bit(0x80, vmx_io_bitmap_a);
4404
4405         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4406
4407         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4408         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4409
4410         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4411
4412         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4413                      __alignof__(struct vcpu_vmx), THIS_MODULE);
4414         if (r)
4415                 goto out3;
4416
4417         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4418         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4419         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4420         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4421         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4422         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4423
4424         if (enable_ept) {
4425                 bypass_guest_pf = 0;
4426                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4427                         VMX_EPT_WRITABLE_MASK);
4428                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4429                                 VMX_EPT_EXECUTABLE_MASK);
4430                 kvm_enable_tdp();
4431         } else
4432                 kvm_disable_tdp();
4433
4434         if (bypass_guest_pf)
4435                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4436
4437         return 0;
4438
4439 out3:
4440         free_page((unsigned long)vmx_msr_bitmap_longmode);
4441 out2:
4442         free_page((unsigned long)vmx_msr_bitmap_legacy);
4443 out1:
4444         free_page((unsigned long)vmx_io_bitmap_b);
4445 out:
4446         free_page((unsigned long)vmx_io_bitmap_a);
4447         return r;
4448 }
4449
4450 static void __exit vmx_exit(void)
4451 {
4452         free_page((unsigned long)vmx_msr_bitmap_legacy);
4453         free_page((unsigned long)vmx_msr_bitmap_longmode);
4454         free_page((unsigned long)vmx_io_bitmap_b);
4455         free_page((unsigned long)vmx_io_bitmap_a);
4456
4457         kvm_exit();
4458 }
4459
4460 module_init(vmx_init)
4461 module_exit(vmx_exit)