arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/kvm_host.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31 #include <linux/tboot.h>
  32 #include "kvm_cache_regs.h"
  33 #include "x86.h"
  34
  35 #include <asm/io.h>
  36 #include <asm/desc.h>
  37 #include <asm/vmx.h>
  38 #include <asm/virtext.h>
  39 #include <asm/mce.h>
  40 #include <asm/i387.h>
  41 #include <asm/xcr.h>
  42
  43 #include "trace.h"
  44
  45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  46 #define __ex_clear(x, reg) \
  47         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  48
  49 MODULE_AUTHOR("Qumranet");
  50 MODULE_LICENSE("GPL");
  51
  52 static int __read_mostly bypass_guest_pf = 1;
  53 module_param(bypass_guest_pf, bool, S_IRUGO);
  54
  55 static int __read_mostly enable_vpid = 1;
  56 module_param_named(vpid, enable_vpid, bool, 0444);
  57
  58 static int __read_mostly flexpriority_enabled = 1;
  59 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  60
  61 static int __read_mostly enable_ept = 1;
  62 module_param_named(ept, enable_ept, bool, S_IRUGO);
  63
  64 static int __read_mostly enable_unrestricted_guest = 1;
  65 module_param_named(unrestricted_guest,
  66                         enable_unrestricted_guest, bool, S_IRUGO);
  67
  68 static int __read_mostly emulate_invalid_guest_state = 0;
  69 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  70
  71 static int __read_mostly vmm_exclusive = 1;
  72 module_param(vmm_exclusive, bool, S_IRUGO);
  73
  74 static int __read_mostly yield_on_hlt = 1;
  75 module_param(yield_on_hlt, bool, S_IRUGO);
  76
  77 /*
  78  * If nested=1, nested virtualization is supported, i.e., guests may use
  79  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  80  * use VMX instructions.
  81  */
  82 static int __read_mostly nested = 0;
  83 module_param(nested, bool, S_IRUGO);
  84
  85 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  86         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  87 #define KVM_GUEST_CR0_MASK                                              \
  88         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  89 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  90         (X86_CR0_WP | X86_CR0_NE)
  91 #define KVM_VM_CR0_ALWAYS_ON                                            \
  92         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  93 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  94         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  95          | X86_CR4_OSXMMEXCPT)
  96
  97 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  98 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  99
 100 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 101
 102 /*
 103  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 104  * ple_gap:    upper bound on the amount of time between two successive
 105  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 106  *             According to test, this time is usually smaller than 128 cycles.
 107  * ple_window: upper bound on the amount of time a guest is allowed to execute
 108  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 109  *             less than 2^12 cycles
 110  * Time is measured based on a counter that runs at the same rate as the TSC,
 111  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 112  */
 113 #define KVM_VMX_DEFAULT_PLE_GAP    128
 114 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 115 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 116 module_param(ple_gap, int, S_IRUGO);
 117
 118 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 119 module_param(ple_window, int, S_IRUGO);
 120
 121 #define NR_AUTOLOAD_MSRS 1
 122 #define VMCS02_POOL_SIZE 1
 123
 124 struct vmcs {
 125         u32 revision_id;
 126         u32 abort;
 127         char data[0];
 128 };
 129
 130 /*
 131  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 132  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 133  * loaded on this CPU (so we can clear them if the CPU goes down).
 134  */
 135 struct loaded_vmcs {
 136         struct vmcs *vmcs;
 137         int cpu;
 138         int launched;
 139         struct list_head loaded_vmcss_on_cpu_link;
 140 };
 141
 142 struct shared_msr_entry {
 143         unsigned index;
 144         u64 data;
 145         u64 mask;
 146 };
 147
 148 /*
 149  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 150  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 151  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 152  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 153  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 154  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 155  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 156  * underlying hardware which will be used to run L2.
 157  * This structure is packed to ensure that its layout is identical across
 158  * machines (necessary for live migration).
 159  * If there are changes in this struct, VMCS12_REVISION must be changed.
 160  */
 161 typedef u64 natural_width;
 162 struct __packed vmcs12 {
 163         /* According to the Intel spec, a VMCS region must start with the
 164          * following two fields. Then follow implementation-specific data.
 165          */
 166         u32 revision_id;
 167         u32 abort;
 168
 169         u64 io_bitmap_a;
 170         u64 io_bitmap_b;
 171         u64 msr_bitmap;
 172         u64 vm_exit_msr_store_addr;
 173         u64 vm_exit_msr_load_addr;
 174         u64 vm_entry_msr_load_addr;
 175         u64 tsc_offset;
 176         u64 virtual_apic_page_addr;
 177         u64 apic_access_addr;
 178         u64 ept_pointer;
 179         u64 guest_physical_address;
 180         u64 vmcs_link_pointer;
 181         u64 guest_ia32_debugctl;
 182         u64 guest_ia32_pat;
 183         u64 guest_ia32_efer;
 184         u64 guest_ia32_perf_global_ctrl;
 185         u64 guest_pdptr0;
 186         u64 guest_pdptr1;
 187         u64 guest_pdptr2;
 188         u64 guest_pdptr3;
 189         u64 host_ia32_pat;
 190         u64 host_ia32_efer;
 191         u64 host_ia32_perf_global_ctrl;
 192         u64 padding64[8]; /* room for future expansion */
 193         /*
 194          * To allow migration of L1 (complete with its L2 guests) between
 195          * machines of different natural widths (32 or 64 bit), we cannot have
 196          * unsigned long fields with no explict size. We use u64 (aliased
 197          * natural_width) instead. Luckily, x86 is little-endian.
 198          */
 199         natural_width cr0_guest_host_mask;
 200         natural_width cr4_guest_host_mask;
 201         natural_width cr0_read_shadow;
 202         natural_width cr4_read_shadow;
 203         natural_width cr3_target_value0;
 204         natural_width cr3_target_value1;
 205         natural_width cr3_target_value2;
 206         natural_width cr3_target_value3;
 207         natural_width exit_qualification;
 208         natural_width guest_linear_address;
 209         natural_width guest_cr0;
 210         natural_width guest_cr3;
 211         natural_width guest_cr4;
 212         natural_width guest_es_base;
 213         natural_width guest_cs_base;
 214         natural_width guest_ss_base;
 215         natural_width guest_ds_base;
 216         natural_width guest_fs_base;
 217         natural_width guest_gs_base;
 218         natural_width guest_ldtr_base;
 219         natural_width guest_tr_base;
 220         natural_width guest_gdtr_base;
 221         natural_width guest_idtr_base;
 222         natural_width guest_dr7;
 223         natural_width guest_rsp;
 224         natural_width guest_rip;
 225         natural_width guest_rflags;
 226         natural_width guest_pending_dbg_exceptions;
 227         natural_width guest_sysenter_esp;
 228         natural_width guest_sysenter_eip;
 229         natural_width host_cr0;
 230         natural_width host_cr3;
 231         natural_width host_cr4;
 232         natural_width host_fs_base;
 233         natural_width host_gs_base;
 234         natural_width host_tr_base;
 235         natural_width host_gdtr_base;
 236         natural_width host_idtr_base;
 237         natural_width host_ia32_sysenter_esp;
 238         natural_width host_ia32_sysenter_eip;
 239         natural_width host_rsp;
 240         natural_width host_rip;
 241         natural_width paddingl[8]; /* room for future expansion */
 242         u32 pin_based_vm_exec_control;
 243         u32 cpu_based_vm_exec_control;
 244         u32 exception_bitmap;
 245         u32 page_fault_error_code_mask;
 246         u32 page_fault_error_code_match;
 247         u32 cr3_target_count;
 248         u32 vm_exit_controls;
 249         u32 vm_exit_msr_store_count;
 250         u32 vm_exit_msr_load_count;
 251         u32 vm_entry_controls;
 252         u32 vm_entry_msr_load_count;
 253         u32 vm_entry_intr_info_field;
 254         u32 vm_entry_exception_error_code;
 255         u32 vm_entry_instruction_len;
 256         u32 tpr_threshold;
 257         u32 secondary_vm_exec_control;
 258         u32 vm_instruction_error;
 259         u32 vm_exit_reason;
 260         u32 vm_exit_intr_info;
 261         u32 vm_exit_intr_error_code;
 262         u32 idt_vectoring_info_field;
 263         u32 idt_vectoring_error_code;
 264         u32 vm_exit_instruction_len;
 265         u32 vmx_instruction_info;
 266         u32 guest_es_limit;
 267         u32 guest_cs_limit;
 268         u32 guest_ss_limit;
 269         u32 guest_ds_limit;
 270         u32 guest_fs_limit;
 271         u32 guest_gs_limit;
 272         u32 guest_ldtr_limit;
 273         u32 guest_tr_limit;
 274         u32 guest_gdtr_limit;
 275         u32 guest_idtr_limit;
 276         u32 guest_es_ar_bytes;
 277         u32 guest_cs_ar_bytes;
 278         u32 guest_ss_ar_bytes;
 279         u32 guest_ds_ar_bytes;
 280         u32 guest_fs_ar_bytes;
 281         u32 guest_gs_ar_bytes;
 282         u32 guest_ldtr_ar_bytes;
 283         u32 guest_tr_ar_bytes;
 284         u32 guest_interruptibility_info;
 285         u32 guest_activity_state;
 286         u32 guest_sysenter_cs;
 287         u32 host_ia32_sysenter_cs;
 288         u32 padding32[8]; /* room for future expansion */
 289         u16 virtual_processor_id;
 290         u16 guest_es_selector;
 291         u16 guest_cs_selector;
 292         u16 guest_ss_selector;
 293         u16 guest_ds_selector;
 294         u16 guest_fs_selector;
 295         u16 guest_gs_selector;
 296         u16 guest_ldtr_selector;
 297         u16 guest_tr_selector;
 298         u16 host_es_selector;
 299         u16 host_cs_selector;
 300         u16 host_ss_selector;
 301         u16 host_ds_selector;
 302         u16 host_fs_selector;
 303         u16 host_gs_selector;
 304         u16 host_tr_selector;
 305 };
 306
 307 /*
 308  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 309  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 310  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 311  */
 312 #define VMCS12_REVISION 0x11e57ed0
 313
 314 /*
 315  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 316  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 317  * current implementation, 4K are reserved to avoid future complications.
 318  */
 319 #define VMCS12_SIZE 0x1000
 320
 321 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 322 struct vmcs02_list {
 323         struct list_head list;
 324         gpa_t vmptr;
 325         struct loaded_vmcs vmcs02;
 326 };
 327
 328 /*
 329  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 330  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 331  */
 332 struct nested_vmx {
 333         /* Has the level1 guest done vmxon? */
 334         bool vmxon;
 335
 336         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 337         gpa_t current_vmptr;
 338         /* The host-usable pointer to the above */
 339         struct page *current_vmcs12_page;
 340         struct vmcs12 *current_vmcs12;
 341
 342         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 343         struct list_head vmcs02_pool;
 344         int vmcs02_num;
 345 };
 346
 347 struct vcpu_vmx {
 348         struct kvm_vcpu       vcpu;
 349         unsigned long         host_rsp;
 350         u8                    fail;
 351         u8                    cpl;
 352         bool                  nmi_known_unmasked;
 353         u32                   exit_intr_info;
 354         u32                   idt_vectoring_info;
 355         ulong                 rflags;
 356         struct shared_msr_entry *guest_msrs;
 357         int                   nmsrs;
 358         int                   save_nmsrs;
 359 #ifdef CONFIG_X86_64
 360         u64                   msr_host_kernel_gs_base;
 361         u64                   msr_guest_kernel_gs_base;
 362 #endif
 363         /*
 364          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 365          * non-nested (L1) guest, it always points to vmcs01. For a nested
 366          * guest (L2), it points to a different VMCS.
 367          */
 368         struct loaded_vmcs    vmcs01;
 369         struct loaded_vmcs   *loaded_vmcs;
 370         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 371         struct msr_autoload {
 372                 unsigned nr;
 373                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 374                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 375         } msr_autoload;
 376         struct {
 377                 int           loaded;
 378                 u16           fs_sel, gs_sel, ldt_sel;
 379                 int           gs_ldt_reload_needed;
 380                 int           fs_reload_needed;
 381         } host_state;
 382         struct {
 383                 int vm86_active;
 384                 ulong save_rflags;
 385                 struct kvm_save_segment {
 386                         u16 selector;
 387                         unsigned long base;
 388                         u32 limit;
 389                         u32 ar;
 390                 } tr, es, ds, fs, gs;
 391         } rmode;
 392         struct {
 393                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 394                 struct kvm_save_segment seg[8];
 395         } segment_cache;
 396         int vpid;
 397         bool emulation_required;
 398
 399         /* Support for vnmi-less CPUs */
 400         int soft_vnmi_blocked;
 401         ktime_t entry_time;
 402         s64 vnmi_blocked_time;
 403         u32 exit_reason;
 404
 405         bool rdtscp_enabled;
 406
 407         /* Support for a guest hypervisor (nested VMX) */
 408         struct nested_vmx nested;
 409 };
 410
 411 enum segment_cache_field {
 412         SEG_FIELD_SEL = 0,
 413         SEG_FIELD_BASE = 1,
 414         SEG_FIELD_LIMIT = 2,
 415         SEG_FIELD_AR = 3,
 416
 417         SEG_FIELD_NR = 4
 418 };
 419
 420 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 421 {
 422         return container_of(vcpu, struct vcpu_vmx, vcpu);
 423 }
 424
 425 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 426 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 427 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 428                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 429
 430 static unsigned short vmcs_field_to_offset_table[] = {
 431         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 432         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 433         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 434         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 435         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 436         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 437         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 438         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 439         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 440         FIELD(HOST_ES_SELECTOR, host_es_selector),
 441         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 442         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 443         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 444         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 445         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 446         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 447         FIELD64(IO_BITMAP_A, io_bitmap_a),
 448         FIELD64(IO_BITMAP_B, io_bitmap_b),
 449         FIELD64(MSR_BITMAP, msr_bitmap),
 450         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 451         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 452         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 453         FIELD64(TSC_OFFSET, tsc_offset),
 454         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 455         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 456         FIELD64(EPT_POINTER, ept_pointer),
 457         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 458         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 459         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 460         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 461         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 462         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 463         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 464         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 465         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 466         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 467         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 468         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 469         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 470         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 471         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 472         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 473         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 474         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 475         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 476         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 477         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 478         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 479         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 480         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 481         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 482         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 483         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 484         FIELD(TPR_THRESHOLD, tpr_threshold),
 485         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 486         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 487         FIELD(VM_EXIT_REASON, vm_exit_reason),
 488         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 489         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 490         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 491         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 492         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 493         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 494         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 495         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 496         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 497         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 498         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 499         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 500         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 501         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 502         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 503         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 504         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 505         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 506         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 507         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 508         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 509         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 510         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 511         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 512         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 513         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 514         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 515         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 516         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 517         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 518         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 519         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 520         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 521         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 522         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 523         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 524         FIELD(EXIT_QUALIFICATION, exit_qualification),
 525         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 526         FIELD(GUEST_CR0, guest_cr0),
 527         FIELD(GUEST_CR3, guest_cr3),
 528         FIELD(GUEST_CR4, guest_cr4),
 529         FIELD(GUEST_ES_BASE, guest_es_base),
 530         FIELD(GUEST_CS_BASE, guest_cs_base),
 531         FIELD(GUEST_SS_BASE, guest_ss_base),
 532         FIELD(GUEST_DS_BASE, guest_ds_base),
 533         FIELD(GUEST_FS_BASE, guest_fs_base),
 534         FIELD(GUEST_GS_BASE, guest_gs_base),
 535         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 536         FIELD(GUEST_TR_BASE, guest_tr_base),
 537         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 538         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 539         FIELD(GUEST_DR7, guest_dr7),
 540         FIELD(GUEST_RSP, guest_rsp),
 541         FIELD(GUEST_RIP, guest_rip),
 542         FIELD(GUEST_RFLAGS, guest_rflags),
 543         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 544         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 545         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 546         FIELD(HOST_CR0, host_cr0),
 547         FIELD(HOST_CR3, host_cr3),
 548         FIELD(HOST_CR4, host_cr4),
 549         FIELD(HOST_FS_BASE, host_fs_base),
 550         FIELD(HOST_GS_BASE, host_gs_base),
 551         FIELD(HOST_TR_BASE, host_tr_base),
 552         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 553         FIELD(HOST_IDTR_BASE, host_idtr_base),
 554         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 555         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 556         FIELD(HOST_RSP, host_rsp),
 557         FIELD(HOST_RIP, host_rip),
 558 };
 559 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 560
 561 static inline short vmcs_field_to_offset(unsigned long field)
 562 {
 563         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 564                 return -1;
 565         return vmcs_field_to_offset_table[field];
 566 }
 567
 568 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 569 {
 570         return to_vmx(vcpu)->nested.current_vmcs12;
 571 }
 572
 573 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 574 {
 575         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 576         if (is_error_page(page)) {
 577                 kvm_release_page_clean(page);
 578                 return NULL;
 579         }
 580         return page;
 581 }
 582
 583 static void nested_release_page(struct page *page)
 584 {
 585         kvm_release_page_dirty(page);
 586 }
 587
 588 static void nested_release_page_clean(struct page *page)
 589 {
 590         kvm_release_page_clean(page);
 591 }
 592
 593 static u64 construct_eptp(unsigned long root_hpa);
 594 static void kvm_cpu_vmxon(u64 addr);
 595 static void kvm_cpu_vmxoff(void);
 596 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 597 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 598
 599 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 600 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 601 /*
 602  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 603  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 604  */
 605 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 606 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 607
 608 static unsigned long *vmx_io_bitmap_a;
 609 static unsigned long *vmx_io_bitmap_b;
 610 static unsigned long *vmx_msr_bitmap_legacy;
 611 static unsigned long *vmx_msr_bitmap_longmode;
 612
 613 static bool cpu_has_load_ia32_efer;
 614
 615 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 616 static DEFINE_SPINLOCK(vmx_vpid_lock);
 617
 618 static struct vmcs_config {
 619         int size;
 620         int order;
 621         u32 revision_id;
 622         u32 pin_based_exec_ctrl;
 623         u32 cpu_based_exec_ctrl;
 624         u32 cpu_based_2nd_exec_ctrl;
 625         u32 vmexit_ctrl;
 626         u32 vmentry_ctrl;
 627 } vmcs_config;
 628
 629 static struct vmx_capability {
 630         u32 ept;
 631         u32 vpid;
 632 } vmx_capability;
 633
 634 #define VMX_SEGMENT_FIELD(seg)                                  \
 635         [VCPU_SREG_##seg] = {                                   \
 636                 .selector = GUEST_##seg##_SELECTOR,             \
 637                 .base = GUEST_##seg##_BASE,                     \
 638                 .limit = GUEST_##seg##_LIMIT,                   \
 639                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 640         }
 641
 642 static struct kvm_vmx_segment_field {
 643         unsigned selector;
 644         unsigned base;
 645         unsigned limit;
 646         unsigned ar_bytes;
 647 } kvm_vmx_segment_fields[] = {
 648         VMX_SEGMENT_FIELD(CS),
 649         VMX_SEGMENT_FIELD(DS),
 650         VMX_SEGMENT_FIELD(ES),
 651         VMX_SEGMENT_FIELD(FS),
 652         VMX_SEGMENT_FIELD(GS),
 653         VMX_SEGMENT_FIELD(SS),
 654         VMX_SEGMENT_FIELD(TR),
 655         VMX_SEGMENT_FIELD(LDTR),
 656 };
 657
 658 static u64 host_efer;
 659
 660 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 661
 662 /*
 663  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 664  * away by decrementing the array size.
 665  */
 666 static const u32 vmx_msr_index[] = {
 667 #ifdef CONFIG_X86_64
 668         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 669 #endif
 670         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 671 };
 672 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 673
 674 static inline bool is_page_fault(u32 intr_info)
 675 {
 676         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 677                              INTR_INFO_VALID_MASK)) ==
 678                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 679 }
 680
 681 static inline bool is_no_device(u32 intr_info)
 682 {
 683         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 684                              INTR_INFO_VALID_MASK)) ==
 685                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 686 }
 687
 688 static inline bool is_invalid_opcode(u32 intr_info)
 689 {
 690         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 691                              INTR_INFO_VALID_MASK)) ==
 692                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 693 }
 694
 695 static inline bool is_external_interrupt(u32 intr_info)
 696 {
 697         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 698                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 699 }
 700
 701 static inline bool is_machine_check(u32 intr_info)
 702 {
 703         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 704                              INTR_INFO_VALID_MASK)) ==
 705                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 706 }
 707
 708 static inline bool cpu_has_vmx_msr_bitmap(void)
 709 {
 710         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 711 }
 712
 713 static inline bool cpu_has_vmx_tpr_shadow(void)
 714 {
 715         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 716 }
 717
 718 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 719 {
 720         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 721 }
 722
 723 static inline bool cpu_has_secondary_exec_ctrls(void)
 724 {
 725         return vmcs_config.cpu_based_exec_ctrl &
 726                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 727 }
 728
 729 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 730 {
 731         return vmcs_config.cpu_based_2nd_exec_ctrl &
 732                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 733 }
 734
 735 static inline bool cpu_has_vmx_flexpriority(void)
 736 {
 737         return cpu_has_vmx_tpr_shadow() &&
 738                 cpu_has_vmx_virtualize_apic_accesses();
 739 }
 740
 741 static inline bool cpu_has_vmx_ept_execute_only(void)
 742 {
 743         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 744 }
 745
 746 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 747 {
 748         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 749 }
 750
 751 static inline bool cpu_has_vmx_eptp_writeback(void)
 752 {
 753         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 754 }
 755
 756 static inline bool cpu_has_vmx_ept_2m_page(void)
 757 {
 758         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 759 }
 760
 761 static inline bool cpu_has_vmx_ept_1g_page(void)
 762 {
 763         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 764 }
 765
 766 static inline bool cpu_has_vmx_ept_4levels(void)
 767 {
 768         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 769 }
 770
 771 static inline bool cpu_has_vmx_invept_individual_addr(void)
 772 {
 773         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 774 }
 775
 776 static inline bool cpu_has_vmx_invept_context(void)
 777 {
 778         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 779 }
 780
 781 static inline bool cpu_has_vmx_invept_global(void)
 782 {
 783         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 784 }
 785
 786 static inline bool cpu_has_vmx_invvpid_single(void)
 787 {
 788         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 789 }
 790
 791 static inline bool cpu_has_vmx_invvpid_global(void)
 792 {
 793         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 794 }
 795
 796 static inline bool cpu_has_vmx_ept(void)
 797 {
 798         return vmcs_config.cpu_based_2nd_exec_ctrl &
 799                 SECONDARY_EXEC_ENABLE_EPT;
 800 }
 801
 802 static inline bool cpu_has_vmx_unrestricted_guest(void)
 803 {
 804         return vmcs_config.cpu_based_2nd_exec_ctrl &
 805                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 806 }
 807
 808 static inline bool cpu_has_vmx_ple(void)
 809 {
 810         return vmcs_config.cpu_based_2nd_exec_ctrl &
 811                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 812 }
 813
 814 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 815 {
 816         return flexpriority_enabled && irqchip_in_kernel(kvm);
 817 }
 818
 819 static inline bool cpu_has_vmx_vpid(void)
 820 {
 821         return vmcs_config.cpu_based_2nd_exec_ctrl &
 822                 SECONDARY_EXEC_ENABLE_VPID;
 823 }
 824
 825 static inline bool cpu_has_vmx_rdtscp(void)
 826 {
 827         return vmcs_config.cpu_based_2nd_exec_ctrl &
 828                 SECONDARY_EXEC_RDTSCP;
 829 }
 830
 831 static inline bool cpu_has_virtual_nmis(void)
 832 {
 833         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 834 }
 835
 836 static inline bool cpu_has_vmx_wbinvd_exit(void)
 837 {
 838         return vmcs_config.cpu_based_2nd_exec_ctrl &
 839                 SECONDARY_EXEC_WBINVD_EXITING;
 840 }
 841
 842 static inline bool report_flexpriority(void)
 843 {
 844         return flexpriority_enabled;
 845 }
 846
 847 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 848 {
 849         int i;
 850
 851         for (i = 0; i < vmx->nmsrs; ++i)
 852                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 853                         return i;
 854         return -1;
 855 }
 856
 857 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 858 {
 859     struct {
 860         u64 vpid : 16;
 861         u64 rsvd : 48;
 862         u64 gva;
 863     } operand = { vpid, 0, gva };
 864
 865     asm volatile (__ex(ASM_VMX_INVVPID)
 866                   /* CF==1 or ZF==1 --> rc = -1 */
 867                   "; ja 1f ; ud2 ; 1:"
 868                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 869 }
 870
 871 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 872 {
 873         struct {
 874                 u64 eptp, gpa;
 875         } operand = {eptp, gpa};
 876
 877         asm volatile (__ex(ASM_VMX_INVEPT)
 878                         /* CF==1 or ZF==1 --> rc = -1 */
 879                         "; ja 1f ; ud2 ; 1:\n"
 880                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 881 }
 882
 883 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 884 {
 885         int i;
 886
 887         i = __find_msr_index(vmx, msr);
 888         if (i >= 0)
 889                 return &vmx->guest_msrs[i];
 890         return NULL;
 891 }
 892
 893 static void vmcs_clear(struct vmcs *vmcs)
 894 {
 895         u64 phys_addr = __pa(vmcs);
 896         u8 error;
 897
 898         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 899                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 900                       : "cc", "memory");
 901         if (error)
 902                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 903                        vmcs, phys_addr);
 904 }
 905
 906 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 907 {
 908         vmcs_clear(loaded_vmcs->vmcs);
 909         loaded_vmcs->cpu = -1;
 910         loaded_vmcs->launched = 0;
 911 }
 912
 913 static void vmcs_load(struct vmcs *vmcs)
 914 {
 915         u64 phys_addr = __pa(vmcs);
 916         u8 error;
 917
 918         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 919                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 920                         : "cc", "memory");
 921         if (error)
 922                 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 923                        vmcs, phys_addr);
 924 }
 925
 926 static void __loaded_vmcs_clear(void *arg)
 927 {
 928         struct loaded_vmcs *loaded_vmcs = arg;
 929         int cpu = raw_smp_processor_id();
 930
 931         if (loaded_vmcs->cpu != cpu)
 932                 return; /* vcpu migration can race with cpu offline */
 933         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 934                 per_cpu(current_vmcs, cpu) = NULL;
 935         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 936         loaded_vmcs_init(loaded_vmcs);
 937 }
 938
 939 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 940 {
 941         if (loaded_vmcs->cpu != -1)
 942                 smp_call_function_single(
 943                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
 944 }
 945
 946 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
 947 {
 948         if (vmx->vpid == 0)
 949                 return;
 950
 951         if (cpu_has_vmx_invvpid_single())
 952                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 953 }
 954
 955 static inline void vpid_sync_vcpu_global(void)
 956 {
 957         if (cpu_has_vmx_invvpid_global())
 958                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
 959 }
 960
 961 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
 962 {
 963         if (cpu_has_vmx_invvpid_single())
 964                 vpid_sync_vcpu_single(vmx);
 965         else
 966                 vpid_sync_vcpu_global();
 967 }
 968
 969 static inline void ept_sync_global(void)
 970 {
 971         if (cpu_has_vmx_invept_global())
 972                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 973 }
 974
 975 static inline void ept_sync_context(u64 eptp)
 976 {
 977         if (enable_ept) {
 978                 if (cpu_has_vmx_invept_context())
 979                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 980                 else
 981                         ept_sync_global();
 982         }
 983 }
 984
 985 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 986 {
 987         if (enable_ept) {
 988                 if (cpu_has_vmx_invept_individual_addr())
 989                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 990                                         eptp, gpa);
 991                 else
 992                         ept_sync_context(eptp);
 993         }
 994 }
 995
 996 static __always_inline unsigned long vmcs_readl(unsigned long field)
 997 {
 998         unsigned long value;
 999
1000         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1001                       : "=a"(value) : "d"(field) : "cc");
1002         return value;
1003 }
1004
1005 static __always_inline u16 vmcs_read16(unsigned long field)
1006 {
1007         return vmcs_readl(field);
1008 }
1009
1010 static __always_inline u32 vmcs_read32(unsigned long field)
1011 {
1012         return vmcs_readl(field);
1013 }
1014
1015 static __always_inline u64 vmcs_read64(unsigned long field)
1016 {
1017 #ifdef CONFIG_X86_64
1018         return vmcs_readl(field);
1019 #else
1020         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1021 #endif
1022 }
1023
1024 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1025 {
1026         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1027                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1028         dump_stack();
1029 }
1030
1031 static void vmcs_writel(unsigned long field, unsigned long value)
1032 {
1033         u8 error;
1034
1035         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1036                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1037         if (unlikely(error))
1038                 vmwrite_error(field, value);
1039 }
1040
1041 static void vmcs_write16(unsigned long field, u16 value)
1042 {
1043         vmcs_writel(field, value);
1044 }
1045
1046 static void vmcs_write32(unsigned long field, u32 value)
1047 {
1048         vmcs_writel(field, value);
1049 }
1050
1051 static void vmcs_write64(unsigned long field, u64 value)
1052 {
1053         vmcs_writel(field, value);
1054 #ifndef CONFIG_X86_64
1055         asm volatile ("");
1056         vmcs_writel(field+1, value >> 32);
1057 #endif
1058 }
1059
1060 static void vmcs_clear_bits(unsigned long field, u32 mask)
1061 {
1062         vmcs_writel(field, vmcs_readl(field) & ~mask);
1063 }
1064
1065 static void vmcs_set_bits(unsigned long field, u32 mask)
1066 {
1067         vmcs_writel(field, vmcs_readl(field) | mask);
1068 }
1069
1070 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1071 {
1072         vmx->segment_cache.bitmask = 0;
1073 }
1074
1075 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1076                                        unsigned field)
1077 {
1078         bool ret;
1079         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1080
1081         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1082                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1083                 vmx->segment_cache.bitmask = 0;
1084         }
1085         ret = vmx->segment_cache.bitmask & mask;
1086         vmx->segment_cache.bitmask |= mask;
1087         return ret;
1088 }
1089
1090 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1091 {
1092         u16 *p = &vmx->segment_cache.seg[seg].selector;
1093
1094         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1095                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1096         return *p;
1097 }
1098
1099 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1100 {
1101         ulong *p = &vmx->segment_cache.seg[seg].base;
1102
1103         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1104                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1105         return *p;
1106 }
1107
1108 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1109 {
1110         u32 *p = &vmx->segment_cache.seg[seg].limit;
1111
1112         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1113                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1114         return *p;
1115 }
1116
1117 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1118 {
1119         u32 *p = &vmx->segment_cache.seg[seg].ar;
1120
1121         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1122                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1123         return *p;
1124 }
1125
1126 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1127 {
1128         u32 eb;
1129
1130         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1131              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1132         if ((vcpu->guest_debug &
1133              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1134             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1135                 eb |= 1u << BP_VECTOR;
1136         if (to_vmx(vcpu)->rmode.vm86_active)
1137                 eb = ~0;
1138         if (enable_ept)
1139                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1140         if (vcpu->fpu_active)
1141                 eb &= ~(1u << NM_VECTOR);
1142         vmcs_write32(EXCEPTION_BITMAP, eb);
1143 }
1144
1145 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1146 {
1147         unsigned i;
1148         struct msr_autoload *m = &vmx->msr_autoload;
1149
1150         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1151                 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1152                 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1153                 return;
1154         }
1155
1156         for (i = 0; i < m->nr; ++i)
1157                 if (m->guest[i].index == msr)
1158                         break;
1159
1160         if (i == m->nr)
1161                 return;
1162         --m->nr;
1163         m->guest[i] = m->guest[m->nr];
1164         m->host[i] = m->host[m->nr];
1165         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1166         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1167 }
1168
1169 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1170                                   u64 guest_val, u64 host_val)
1171 {
1172         unsigned i;
1173         struct msr_autoload *m = &vmx->msr_autoload;
1174
1175         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1176                 vmcs_write64(GUEST_IA32_EFER, guest_val);
1177                 vmcs_write64(HOST_IA32_EFER, host_val);
1178                 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1179                 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1180                 return;
1181         }
1182
1183         for (i = 0; i < m->nr; ++i)
1184                 if (m->guest[i].index == msr)
1185                         break;
1186
1187         if (i == m->nr) {
1188                 ++m->nr;
1189                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1190                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1191         }
1192
1193         m->guest[i].index = msr;
1194         m->guest[i].value = guest_val;
1195         m->host[i].index = msr;
1196         m->host[i].value = host_val;
1197 }
1198
1199 static void reload_tss(void)
1200 {
1201         /*
1202          * VT restores TR but not its size.  Useless.
1203          */
1204         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1205         struct desc_struct *descs;
1206
1207         descs = (void *)gdt->address;
1208         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1209         load_TR_desc();
1210 }
1211
1212 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1213 {
1214         u64 guest_efer;
1215         u64 ignore_bits;
1216
1217         guest_efer = vmx->vcpu.arch.efer;
1218
1219         /*
1220          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1221          * outside long mode
1222          */
1223         ignore_bits = EFER_NX | EFER_SCE;
1224 #ifdef CONFIG_X86_64
1225         ignore_bits |= EFER_LMA | EFER_LME;
1226         /* SCE is meaningful only in long mode on Intel */
1227         if (guest_efer & EFER_LMA)
1228                 ignore_bits &= ~(u64)EFER_SCE;
1229 #endif
1230         guest_efer &= ~ignore_bits;
1231         guest_efer |= host_efer & ignore_bits;
1232         vmx->guest_msrs[efer_offset].data = guest_efer;
1233         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1234
1235         clear_atomic_switch_msr(vmx, MSR_EFER);
1236         /* On ept, can't emulate nx, and must switch nx atomically */
1237         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1238                 guest_efer = vmx->vcpu.arch.efer;
1239                 if (!(guest_efer & EFER_LMA))
1240                         guest_efer &= ~EFER_LME;
1241                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1242                 return false;
1243         }
1244
1245         return true;
1246 }
1247
1248 static unsigned long segment_base(u16 selector)
1249 {
1250         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1251         struct desc_struct *d;
1252         unsigned long table_base;
1253         unsigned long v;
1254
1255         if (!(selector & ~3))
1256                 return 0;
1257
1258         table_base = gdt->address;
1259
1260         if (selector & 4) {           /* from ldt */
1261                 u16 ldt_selector = kvm_read_ldt();
1262
1263                 if (!(ldt_selector & ~3))
1264                         return 0;
1265
1266                 table_base = segment_base(ldt_selector);
1267         }
1268         d = (struct desc_struct *)(table_base + (selector & ~7));
1269         v = get_desc_base(d);
1270 #ifdef CONFIG_X86_64
1271        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1272                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1273 #endif
1274         return v;
1275 }
1276
1277 static inline unsigned long kvm_read_tr_base(void)
1278 {
1279         u16 tr;
1280         asm("str %0" : "=g"(tr));
1281         return segment_base(tr);
1282 }
1283
1284 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1285 {
1286         struct vcpu_vmx *vmx = to_vmx(vcpu);
1287         int i;
1288
1289         if (vmx->host_state.loaded)
1290                 return;
1291
1292         vmx->host_state.loaded = 1;
1293         /*
1294          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1295          * allow segment selectors with cpl > 0 or ti == 1.
1296          */
1297         vmx->host_state.ldt_sel = kvm_read_ldt();
1298         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1299         savesegment(fs, vmx->host_state.fs_sel);
1300         if (!(vmx->host_state.fs_sel & 7)) {
1301                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1302                 vmx->host_state.fs_reload_needed = 0;
1303         } else {
1304                 vmcs_write16(HOST_FS_SELECTOR, 0);
1305                 vmx->host_state.fs_reload_needed = 1;
1306         }
1307         savesegment(gs, vmx->host_state.gs_sel);
1308         if (!(vmx->host_state.gs_sel & 7))
1309                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1310         else {
1311                 vmcs_write16(HOST_GS_SELECTOR, 0);
1312                 vmx->host_state.gs_ldt_reload_needed = 1;
1313         }
1314
1315 #ifdef CONFIG_X86_64
1316         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1317         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1318 #else
1319         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1320         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1321 #endif
1322
1323 #ifdef CONFIG_X86_64
1324         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1325         if (is_long_mode(&vmx->vcpu))
1326                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1327 #endif
1328         for (i = 0; i < vmx->save_nmsrs; ++i)
1329                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1330                                    vmx->guest_msrs[i].data,
1331                                    vmx->guest_msrs[i].mask);
1332 }
1333
1334 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1335 {
1336         if (!vmx->host_state.loaded)
1337                 return;
1338
1339         ++vmx->vcpu.stat.host_state_reload;
1340         vmx->host_state.loaded = 0;
1341 #ifdef CONFIG_X86_64
1342         if (is_long_mode(&vmx->vcpu))
1343                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1344 #endif
1345         if (vmx->host_state.gs_ldt_reload_needed) {
1346                 kvm_load_ldt(vmx->host_state.ldt_sel);
1347 #ifdef CONFIG_X86_64
1348                 load_gs_index(vmx->host_state.gs_sel);
1349 #else
1350                 loadsegment(gs, vmx->host_state.gs_sel);
1351 #endif
1352         }
1353         if (vmx->host_state.fs_reload_needed)
1354                 loadsegment(fs, vmx->host_state.fs_sel);
1355         reload_tss();
1356 #ifdef CONFIG_X86_64
1357         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1358 #endif
1359         if (current_thread_info()->status & TS_USEDFPU)
1360                 clts();
1361         load_gdt(&__get_cpu_var(host_gdt));
1362 }
1363
1364 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1365 {
1366         preempt_disable();
1367         __vmx_load_host_state(vmx);
1368         preempt_enable();
1369 }
1370
1371 /*
1372  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1373  * vcpu mutex is already taken.
1374  */
1375 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1376 {
1377         struct vcpu_vmx *vmx = to_vmx(vcpu);
1378         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1379
1380         if (!vmm_exclusive)
1381                 kvm_cpu_vmxon(phys_addr);
1382         else if (vmx->loaded_vmcs->cpu != cpu)
1383                 loaded_vmcs_clear(vmx->loaded_vmcs);
1384
1385         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1386                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1387                 vmcs_load(vmx->loaded_vmcs->vmcs);
1388         }
1389
1390         if (vmx->loaded_vmcs->cpu != cpu) {
1391                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1392                 unsigned long sysenter_esp;
1393
1394                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1395                 local_irq_disable();
1396                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1397                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1398                 local_irq_enable();
1399
1400                 /*
1401                  * Linux uses per-cpu TSS and GDT, so set these when switching
1402                  * processors.
1403                  */
1404                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1405                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1406
1407                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1408                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1409                 vmx->loaded_vmcs->cpu = cpu;
1410         }
1411 }
1412
1413 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1414 {
1415         __vmx_load_host_state(to_vmx(vcpu));
1416         if (!vmm_exclusive) {
1417                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1418                 vcpu->cpu = -1;
1419                 kvm_cpu_vmxoff();
1420         }
1421 }
1422
1423 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1424 {
1425         ulong cr0;
1426
1427         if (vcpu->fpu_active)
1428                 return;
1429         vcpu->fpu_active = 1;
1430         cr0 = vmcs_readl(GUEST_CR0);
1431         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1432         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1433         vmcs_writel(GUEST_CR0, cr0);
1434         update_exception_bitmap(vcpu);
1435         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1436         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1437 }
1438
1439 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1440
1441 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1442 {
1443         vmx_decache_cr0_guest_bits(vcpu);
1444         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1445         update_exception_bitmap(vcpu);
1446         vcpu->arch.cr0_guest_owned_bits = 0;
1447         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1448         vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1449 }
1450
1451 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1452 {
1453         unsigned long rflags, save_rflags;
1454
1455         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1456                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1457                 rflags = vmcs_readl(GUEST_RFLAGS);
1458                 if (to_vmx(vcpu)->rmode.vm86_active) {
1459                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1460                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1461                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1462                 }
1463                 to_vmx(vcpu)->rflags = rflags;
1464         }
1465         return to_vmx(vcpu)->rflags;
1466 }
1467
1468 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1469 {
1470         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1471         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1472         to_vmx(vcpu)->rflags = rflags;
1473         if (to_vmx(vcpu)->rmode.vm86_active) {
1474                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1475                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1476         }
1477         vmcs_writel(GUEST_RFLAGS, rflags);
1478 }
1479
1480 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1481 {
1482         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1483         int ret = 0;
1484
1485         if (interruptibility & GUEST_INTR_STATE_STI)
1486                 ret |= KVM_X86_SHADOW_INT_STI;
1487         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1488                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1489
1490         return ret & mask;
1491 }
1492
1493 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1494 {
1495         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1496         u32 interruptibility = interruptibility_old;
1497
1498         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1499
1500         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1501                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1502         else if (mask & KVM_X86_SHADOW_INT_STI)
1503                 interruptibility |= GUEST_INTR_STATE_STI;
1504
1505         if ((interruptibility != interruptibility_old))
1506                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1507 }
1508
1509 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1510 {
1511         unsigned long rip;
1512
1513         rip = kvm_rip_read(vcpu);
1514         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1515         kvm_rip_write(vcpu, rip);
1516
1517         /* skipping an emulated instruction also counts */
1518         vmx_set_interrupt_shadow(vcpu, 0);
1519 }
1520
1521 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1522 {
1523         /* Ensure that we clear the HLT state in the VMCS.  We don't need to
1524          * explicitly skip the instruction because if the HLT state is set, then
1525          * the instruction is already executing and RIP has already been
1526          * advanced. */
1527         if (!yield_on_hlt &&
1528             vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1529                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1530 }
1531
1532 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1533                                 bool has_error_code, u32 error_code,
1534                                 bool reinject)
1535 {
1536         struct vcpu_vmx *vmx = to_vmx(vcpu);
1537         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1538
1539         if (has_error_code) {
1540                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1541                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1542         }
1543
1544         if (vmx->rmode.vm86_active) {
1545                 int inc_eip = 0;
1546                 if (kvm_exception_is_soft(nr))
1547                         inc_eip = vcpu->arch.event_exit_inst_len;
1548                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1549                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1550                 return;
1551         }
1552
1553         if (kvm_exception_is_soft(nr)) {
1554                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1555                              vmx->vcpu.arch.event_exit_inst_len);
1556                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1557         } else
1558                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1559
1560         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1561         vmx_clear_hlt(vcpu);
1562 }
1563
1564 static bool vmx_rdtscp_supported(void)
1565 {
1566         return cpu_has_vmx_rdtscp();
1567 }
1568
1569 /*
1570  * Swap MSR entry in host/guest MSR entry array.
1571  */
1572 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1573 {
1574         struct shared_msr_entry tmp;
1575
1576         tmp = vmx->guest_msrs[to];
1577         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1578         vmx->guest_msrs[from] = tmp;
1579 }
1580
1581 /*
1582  * Set up the vmcs to automatically save and restore system
1583  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1584  * mode, as fiddling with msrs is very expensive.
1585  */
1586 static void setup_msrs(struct vcpu_vmx *vmx)
1587 {
1588         int save_nmsrs, index;
1589         unsigned long *msr_bitmap;
1590
1591         vmx_load_host_state(vmx);
1592         save_nmsrs = 0;
1593 #ifdef CONFIG_X86_64
1594         if (is_long_mode(&vmx->vcpu)) {
1595                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1596                 if (index >= 0)
1597                         move_msr_up(vmx, index, save_nmsrs++);
1598                 index = __find_msr_index(vmx, MSR_LSTAR);
1599                 if (index >= 0)
1600                         move_msr_up(vmx, index, save_nmsrs++);
1601                 index = __find_msr_index(vmx, MSR_CSTAR);
1602                 if (index >= 0)
1603                         move_msr_up(vmx, index, save_nmsrs++);
1604                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1605                 if (index >= 0 && vmx->rdtscp_enabled)
1606                         move_msr_up(vmx, index, save_nmsrs++);
1607                 /*
1608                  * MSR_STAR is only needed on long mode guests, and only
1609                  * if efer.sce is enabled.
1610                  */
1611                 index = __find_msr_index(vmx, MSR_STAR);
1612                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1613                         move_msr_up(vmx, index, save_nmsrs++);
1614         }
1615 #endif
1616         index = __find_msr_index(vmx, MSR_EFER);
1617         if (index >= 0 && update_transition_efer(vmx, index))
1618                 move_msr_up(vmx, index, save_nmsrs++);
1619
1620         vmx->save_nmsrs = save_nmsrs;
1621
1622         if (cpu_has_vmx_msr_bitmap()) {
1623                 if (is_long_mode(&vmx->vcpu))
1624                         msr_bitmap = vmx_msr_bitmap_longmode;
1625                 else
1626                         msr_bitmap = vmx_msr_bitmap_legacy;
1627
1628                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1629         }
1630 }
1631
1632 /*
1633  * reads and returns guest's timestamp counter "register"
1634  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1635  */
1636 static u64 guest_read_tsc(void)
1637 {
1638         u64 host_tsc, tsc_offset;
1639
1640         rdtscll(host_tsc);
1641         tsc_offset = vmcs_read64(TSC_OFFSET);
1642         return host_tsc + tsc_offset;
1643 }
1644
1645 /*
1646  * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1647  * ioctl. In this case the call-back should update internal vmx state to make
1648  * the changes effective.
1649  */
1650 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1651 {
1652         /* Nothing to do here */
1653 }
1654
1655 /*
1656  * writes 'offset' into guest's timestamp counter offset register
1657  */
1658 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1659 {
1660         vmcs_write64(TSC_OFFSET, offset);
1661 }
1662
1663 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1664 {
1665         u64 offset = vmcs_read64(TSC_OFFSET);
1666         vmcs_write64(TSC_OFFSET, offset + adjustment);
1667 }
1668
1669 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1670 {
1671         return target_tsc - native_read_tsc();
1672 }
1673
1674 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1675 {
1676         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1677         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1678 }
1679
1680 /*
1681  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1682  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1683  * all guests if the "nested" module option is off, and can also be disabled
1684  * for a single guest by disabling its VMX cpuid bit.
1685  */
1686 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1687 {
1688         return nested && guest_cpuid_has_vmx(vcpu);
1689 }
1690
1691 /*
1692  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1693  * returned for the various VMX controls MSRs when nested VMX is enabled.
1694  * The same values should also be used to verify that vmcs12 control fields are
1695  * valid during nested entry from L1 to L2.
1696  * Each of these control msrs has a low and high 32-bit half: A low bit is on
1697  * if the corresponding bit in the (32-bit) control field *must* be on, and a
1698  * bit in the high half is on if the corresponding bit in the control field
1699  * may be on. See also vmx_control_verify().
1700  * TODO: allow these variables to be modified (downgraded) by module options
1701  * or other means.
1702  */
1703 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1704 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1705 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1706 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1707 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1708 static __init void nested_vmx_setup_ctls_msrs(void)
1709 {
1710         /*
1711          * Note that as a general rule, the high half of the MSRs (bits in
1712          * the control fields which may be 1) should be initialized by the
1713          * intersection of the underlying hardware's MSR (i.e., features which
1714          * can be supported) and the list of features we want to expose -
1715          * because they are known to be properly supported in our code.
1716          * Also, usually, the low half of the MSRs (bits which must be 1) can
1717          * be set to 0, meaning that L1 may turn off any of these bits. The
1718          * reason is that if one of these bits is necessary, it will appear
1719          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1720          * fields of vmcs01 and vmcs02, will turn these bits off - and
1721          * nested_vmx_exit_handled() will not pass related exits to L1.
1722          * These rules have exceptions below.
1723          */
1724
1725         /* pin-based controls */
1726         /*
1727          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1728          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1729          */
1730         nested_vmx_pinbased_ctls_low = 0x16 ;
1731         nested_vmx_pinbased_ctls_high = 0x16 |
1732                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1733                 PIN_BASED_VIRTUAL_NMIS;
1734
1735         /* exit controls */
1736         nested_vmx_exit_ctls_low = 0;
1737 #ifdef CONFIG_X86_64
1738         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1739 #else
1740         nested_vmx_exit_ctls_high = 0;
1741 #endif
1742
1743         /* entry controls */
1744         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1745                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1746         nested_vmx_entry_ctls_low = 0;
1747         nested_vmx_entry_ctls_high &=
1748                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1749
1750         /* cpu-based controls */
1751         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1752                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1753         nested_vmx_procbased_ctls_low = 0;
1754         nested_vmx_procbased_ctls_high &=
1755                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1756                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1757                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1758                 CPU_BASED_CR3_STORE_EXITING |
1759 #ifdef CONFIG_X86_64
1760                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1761 #endif
1762                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1763                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1764                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1765         /*
1766          * We can allow some features even when not supported by the
1767          * hardware. For example, L1 can specify an MSR bitmap - and we
1768          * can use it to avoid exits to L1 - even when L0 runs L2
1769          * without MSR bitmaps.
1770          */
1771         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1772
1773         /* secondary cpu-based controls */
1774         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1775                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1776         nested_vmx_secondary_ctls_low = 0;
1777         nested_vmx_secondary_ctls_high &=
1778                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1779 }
1780
1781 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1782 {
1783         /*
1784          * Bits 0 in high must be 0, and bits 1 in low must be 1.
1785          */
1786         return ((control & high) | low) == control;
1787 }
1788
1789 static inline u64 vmx_control_msr(u32 low, u32 high)
1790 {
1791         return low | ((u64)high << 32);
1792 }
1793
1794 /*
1795  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1796  * also let it use VMX-specific MSRs.
1797  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1798  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1799  * like all other MSRs).
1800  */
1801 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1802 {
1803         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1804                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
1805                 /*
1806                  * According to the spec, processors which do not support VMX
1807                  * should throw a #GP(0) when VMX capability MSRs are read.
1808                  */
1809                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
1810                 return 1;
1811         }
1812
1813         switch (msr_index) {
1814         case MSR_IA32_FEATURE_CONTROL:
1815                 *pdata = 0;
1816                 break;
1817         case MSR_IA32_VMX_BASIC:
1818                 /*
1819                  * This MSR reports some information about VMX support. We
1820                  * should return information about the VMX we emulate for the
1821                  * guest, and the VMCS structure we give it - not about the
1822                  * VMX support of the underlying hardware.
1823                  */
1824                 *pdata = VMCS12_REVISION |
1825                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
1826                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
1827                 break;
1828         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1829         case MSR_IA32_VMX_PINBASED_CTLS:
1830                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
1831                                         nested_vmx_pinbased_ctls_high);
1832                 break;
1833         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1834         case MSR_IA32_VMX_PROCBASED_CTLS:
1835                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
1836                                         nested_vmx_procbased_ctls_high);
1837                 break;
1838         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1839         case MSR_IA32_VMX_EXIT_CTLS:
1840                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
1841                                         nested_vmx_exit_ctls_high);
1842                 break;
1843         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1844         case MSR_IA32_VMX_ENTRY_CTLS:
1845                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
1846                                         nested_vmx_entry_ctls_high);
1847                 break;
1848         case MSR_IA32_VMX_MISC:
1849                 *pdata = 0;
1850                 break;
1851         /*
1852          * These MSRs specify bits which the guest must keep fixed (on or off)
1853          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
1854          * We picked the standard core2 setting.
1855          */
1856 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
1857 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
1858         case MSR_IA32_VMX_CR0_FIXED0:
1859                 *pdata = VMXON_CR0_ALWAYSON;
1860                 break;
1861         case MSR_IA32_VMX_CR0_FIXED1:
1862                 *pdata = -1ULL;
1863                 break;
1864         case MSR_IA32_VMX_CR4_FIXED0:
1865                 *pdata = VMXON_CR4_ALWAYSON;
1866                 break;
1867         case MSR_IA32_VMX_CR4_FIXED1:
1868                 *pdata = -1ULL;
1869                 break;
1870         case MSR_IA32_VMX_VMCS_ENUM:
1871                 *pdata = 0x1f;
1872                 break;
1873         case MSR_IA32_VMX_PROCBASED_CTLS2:
1874                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
1875                                         nested_vmx_secondary_ctls_high);
1876                 break;
1877         case MSR_IA32_VMX_EPT_VPID_CAP:
1878                 /* Currently, no nested ept or nested vpid */
1879                 *pdata = 0;
1880                 break;
1881         default:
1882                 return 0;
1883         }
1884
1885         return 1;
1886 }
1887
1888 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1889 {
1890         if (!nested_vmx_allowed(vcpu))
1891                 return 0;
1892
1893         if (msr_index == MSR_IA32_FEATURE_CONTROL)
1894                 /* TODO: the right thing. */
1895                 return 1;
1896         /*
1897          * No need to treat VMX capability MSRs specially: If we don't handle
1898          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
1899          */
1900         return 0;
1901 }
1902
1903 /*
1904  * Reads an msr value (of 'msr_index') into 'pdata'.
1905  * Returns 0 on success, non-0 otherwise.
1906  * Assumes vcpu_load() was already called.
1907  */
1908 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1909 {
1910         u64 data;
1911         struct shared_msr_entry *msr;
1912
1913         if (!pdata) {
1914                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1915                 return -EINVAL;
1916         }
1917
1918         switch (msr_index) {
1919 #ifdef CONFIG_X86_64
1920         case MSR_FS_BASE:
1921                 data = vmcs_readl(GUEST_FS_BASE);
1922                 break;
1923         case MSR_GS_BASE:
1924                 data = vmcs_readl(GUEST_GS_BASE);
1925                 break;
1926         case MSR_KERNEL_GS_BASE:
1927                 vmx_load_host_state(to_vmx(vcpu));
1928                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1929                 break;
1930 #endif
1931         case MSR_EFER:
1932                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1933         case MSR_IA32_TSC:
1934                 data = guest_read_tsc();
1935                 break;
1936         case MSR_IA32_SYSENTER_CS:
1937                 data = vmcs_read32(GUEST_SYSENTER_CS);
1938                 break;
1939         case MSR_IA32_SYSENTER_EIP:
1940                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1941                 break;
1942         case MSR_IA32_SYSENTER_ESP:
1943                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1944                 break;
1945         case MSR_TSC_AUX:
1946                 if (!to_vmx(vcpu)->rdtscp_enabled)
1947                         return 1;
1948                 /* Otherwise falls through */
1949         default:
1950                 vmx_load_host_state(to_vmx(vcpu));
1951                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
1952                         return 0;
1953                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1954                 if (msr) {
1955                         vmx_load_host_state(to_vmx(vcpu));
1956                         data = msr->data;
1957                         break;
1958                 }
1959                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1960         }
1961
1962         *pdata = data;
1963         return 0;
1964 }
1965
1966 /*
1967  * Writes msr value into into the appropriate "register".
1968  * Returns 0 on success, non-0 otherwise.
1969  * Assumes vcpu_load() was already called.
1970  */
1971 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1972 {
1973         struct vcpu_vmx *vmx = to_vmx(vcpu);
1974         struct shared_msr_entry *msr;
1975         int ret = 0;
1976
1977         switch (msr_index) {
1978         case MSR_EFER:
1979                 vmx_load_host_state(vmx);
1980                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1981                 break;
1982 #ifdef CONFIG_X86_64
1983         case MSR_FS_BASE:
1984                 vmx_segment_cache_clear(vmx);
1985                 vmcs_writel(GUEST_FS_BASE, data);
1986                 break;
1987         case MSR_GS_BASE:
1988                 vmx_segment_cache_clear(vmx);
1989                 vmcs_writel(GUEST_GS_BASE, data);
1990                 break;
1991         case MSR_KERNEL_GS_BASE:
1992                 vmx_load_host_state(vmx);
1993                 vmx->msr_guest_kernel_gs_base = data;
1994                 break;
1995 #endif
1996         case MSR_IA32_SYSENTER_CS:
1997                 vmcs_write32(GUEST_SYSENTER_CS, data);
1998                 break;
1999         case MSR_IA32_SYSENTER_EIP:
2000                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2001                 break;
2002         case MSR_IA32_SYSENTER_ESP:
2003                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2004                 break;
2005         case MSR_IA32_TSC:
2006                 kvm_write_tsc(vcpu, data);
2007                 break;
2008         case MSR_IA32_CR_PAT:
2009                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2010                         vmcs_write64(GUEST_IA32_PAT, data);
2011                         vcpu->arch.pat = data;
2012                         break;
2013                 }
2014                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2015                 break;
2016         case MSR_TSC_AUX:
2017                 if (!vmx->rdtscp_enabled)
2018                         return 1;
2019                 /* Check reserved bit, higher 32 bits should be zero */
2020                 if ((data >> 32) != 0)
2021                         return 1;
2022                 /* Otherwise falls through */
2023         default:
2024                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2025                         break;
2026                 msr = find_msr_entry(vmx, msr_index);
2027                 if (msr) {
2028                         vmx_load_host_state(vmx);
2029                         msr->data = data;
2030                         break;
2031                 }
2032                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2033         }
2034
2035         return ret;
2036 }
2037
2038 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2039 {
2040         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2041         switch (reg) {
2042         case VCPU_REGS_RSP:
2043                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2044                 break;
2045         case VCPU_REGS_RIP:
2046                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2047                 break;
2048         case VCPU_EXREG_PDPTR:
2049                 if (enable_ept)
2050                         ept_save_pdptrs(vcpu);
2051                 break;
2052         default:
2053                 break;
2054         }
2055 }
2056
2057 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2058 {
2059         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2060                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2061         else
2062                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2063
2064         update_exception_bitmap(vcpu);
2065 }
2066
2067 static __init int cpu_has_kvm_support(void)
2068 {
2069         return cpu_has_vmx();
2070 }
2071
2072 static __init int vmx_disabled_by_bios(void)
2073 {
2074         u64 msr;
2075
2076         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2077         if (msr & FEATURE_CONTROL_LOCKED) {
2078                 /* launched w/ TXT and VMX disabled */
2079                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2080                         && tboot_enabled())
2081                         return 1;
2082                 /* launched w/o TXT and VMX only enabled w/ TXT */
2083                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2084                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2085                         && !tboot_enabled()) {
2086                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2087                                 "activate TXT before enabling KVM\n");
2088                         return 1;
2089                 }
2090                 /* launched w/o TXT and VMX disabled */
2091                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2092                         && !tboot_enabled())
2093                         return 1;
2094         }
2095
2096         return 0;
2097 }
2098
2099 static void kvm_cpu_vmxon(u64 addr)
2100 {
2101         asm volatile (ASM_VMX_VMXON_RAX
2102                         : : "a"(&addr), "m"(addr)
2103                         : "memory", "cc");
2104 }
2105
2106 static int hardware_enable(void *garbage)
2107 {
2108         int cpu = raw_smp_processor_id();
2109         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2110         u64 old, test_bits;
2111
2112         if (read_cr4() & X86_CR4_VMXE)
2113                 return -EBUSY;
2114
2115         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2116         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2117
2118         test_bits = FEATURE_CONTROL_LOCKED;
2119         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2120         if (tboot_enabled())
2121                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2122
2123         if ((old & test_bits) != test_bits) {
2124                 /* enable and lock */
2125                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2126         }
2127         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2128
2129         if (vmm_exclusive) {
2130                 kvm_cpu_vmxon(phys_addr);
2131                 ept_sync_global();
2132         }
2133
2134         store_gdt(&__get_cpu_var(host_gdt));
2135
2136         return 0;
2137 }
2138
2139 static void vmclear_local_loaded_vmcss(void)
2140 {
2141         int cpu = raw_smp_processor_id();
2142         struct loaded_vmcs *v, *n;
2143
2144         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2145                                  loaded_vmcss_on_cpu_link)
2146                 __loaded_vmcs_clear(v);
2147 }
2148
2149
2150 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2151  * tricks.
2152  */
2153 static void kvm_cpu_vmxoff(void)
2154 {
2155         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2156 }
2157
2158 static void hardware_disable(void *garbage)
2159 {
2160         if (vmm_exclusive) {
2161                 vmclear_local_loaded_vmcss();
2162                 kvm_cpu_vmxoff();
2163         }
2164         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2165 }
2166
2167 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2168                                       u32 msr, u32 *result)
2169 {
2170         u32 vmx_msr_low, vmx_msr_high;
2171         u32 ctl = ctl_min | ctl_opt;
2172
2173         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2174
2175         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2176         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2177
2178         /* Ensure minimum (required) set of control bits are supported. */
2179         if (ctl_min & ~ctl)
2180                 return -EIO;
2181
2182         *result = ctl;
2183         return 0;
2184 }
2185
2186 static __init bool allow_1_setting(u32 msr, u32 ctl)
2187 {
2188         u32 vmx_msr_low, vmx_msr_high;
2189
2190         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2191         return vmx_msr_high & ctl;
2192 }
2193
2194 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2195 {
2196         u32 vmx_msr_low, vmx_msr_high;
2197         u32 min, opt, min2, opt2;
2198         u32 _pin_based_exec_control = 0;
2199         u32 _cpu_based_exec_control = 0;
2200         u32 _cpu_based_2nd_exec_control = 0;
2201         u32 _vmexit_control = 0;
2202         u32 _vmentry_control = 0;
2203
2204         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2205         opt = PIN_BASED_VIRTUAL_NMIS;
2206         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2207                                 &_pin_based_exec_control) < 0)
2208                 return -EIO;
2209
2210         min =
2211 #ifdef CONFIG_X86_64
2212               CPU_BASED_CR8_LOAD_EXITING |
2213               CPU_BASED_CR8_STORE_EXITING |
2214 #endif
2215               CPU_BASED_CR3_LOAD_EXITING |
2216               CPU_BASED_CR3_STORE_EXITING |
2217               CPU_BASED_USE_IO_BITMAPS |
2218               CPU_BASED_MOV_DR_EXITING |
2219               CPU_BASED_USE_TSC_OFFSETING |
2220               CPU_BASED_MWAIT_EXITING |
2221               CPU_BASED_MONITOR_EXITING |
2222               CPU_BASED_INVLPG_EXITING;
2223
2224         if (yield_on_hlt)
2225                 min |= CPU_BASED_HLT_EXITING;
2226
2227         opt = CPU_BASED_TPR_SHADOW |
2228               CPU_BASED_USE_MSR_BITMAPS |
2229               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2230         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2231                                 &_cpu_based_exec_control) < 0)
2232                 return -EIO;
2233 #ifdef CONFIG_X86_64
2234         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2235                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2236                                            ~CPU_BASED_CR8_STORE_EXITING;
2237 #endif
2238         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2239                 min2 = 0;
2240                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2241                         SECONDARY_EXEC_WBINVD_EXITING |
2242                         SECONDARY_EXEC_ENABLE_VPID |
2243                         SECONDARY_EXEC_ENABLE_EPT |
2244                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2245                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2246                         SECONDARY_EXEC_RDTSCP;
2247                 if (adjust_vmx_controls(min2, opt2,
2248                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2249                                         &_cpu_based_2nd_exec_control) < 0)
2250                         return -EIO;
2251         }
2252 #ifndef CONFIG_X86_64
2253         if (!(_cpu_based_2nd_exec_control &
2254                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2255                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2256 #endif
2257         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2258                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2259                    enabled */
2260                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2261                                              CPU_BASED_CR3_STORE_EXITING |
2262                                              CPU_BASED_INVLPG_EXITING);
2263                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2264                       vmx_capability.ept, vmx_capability.vpid);
2265         }
2266
2267         min = 0;
2268 #ifdef CONFIG_X86_64
2269         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2270 #endif
2271         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2272         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2273                                 &_vmexit_control) < 0)
2274                 return -EIO;
2275
2276         min = 0;
2277         opt = VM_ENTRY_LOAD_IA32_PAT;
2278         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2279                                 &_vmentry_control) < 0)
2280                 return -EIO;
2281
2282         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2283
2284         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2285         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2286                 return -EIO;
2287
2288 #ifdef CONFIG_X86_64
2289         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2290         if (vmx_msr_high & (1u<<16))
2291                 return -EIO;
2292 #endif
2293
2294         /* Require Write-Back (WB) memory type for VMCS accesses. */
2295         if (((vmx_msr_high >> 18) & 15) != 6)
2296                 return -EIO;
2297
2298         vmcs_conf->size = vmx_msr_high & 0x1fff;
2299         vmcs_conf->order = get_order(vmcs_config.size);
2300         vmcs_conf->revision_id = vmx_msr_low;
2301
2302         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2303         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2304         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2305         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2306         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2307
2308         cpu_has_load_ia32_efer =
2309                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2310                                 VM_ENTRY_LOAD_IA32_EFER)
2311                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2312                                    VM_EXIT_LOAD_IA32_EFER);
2313
2314         return 0;
2315 }
2316
2317 static struct vmcs *alloc_vmcs_cpu(int cpu)
2318 {
2319         int node = cpu_to_node(cpu);
2320         struct page *pages;
2321         struct vmcs *vmcs;
2322
2323         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2324         if (!pages)
2325                 return NULL;
2326         vmcs = page_address(pages);
2327         memset(vmcs, 0, vmcs_config.size);
2328         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2329         return vmcs;
2330 }
2331
2332 static struct vmcs *alloc_vmcs(void)
2333 {
2334         return alloc_vmcs_cpu(raw_smp_processor_id());
2335 }
2336
2337 static void free_vmcs(struct vmcs *vmcs)
2338 {
2339         free_pages((unsigned long)vmcs, vmcs_config.order);
2340 }
2341
2342 /*
2343  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2344  */
2345 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2346 {
2347         if (!loaded_vmcs->vmcs)
2348                 return;
2349         loaded_vmcs_clear(loaded_vmcs);
2350         free_vmcs(loaded_vmcs->vmcs);
2351         loaded_vmcs->vmcs = NULL;
2352 }
2353
2354 static void free_kvm_area(void)
2355 {
2356         int cpu;
2357
2358         for_each_possible_cpu(cpu) {
2359                 free_vmcs(per_cpu(vmxarea, cpu));
2360                 per_cpu(vmxarea, cpu) = NULL;
2361         }
2362 }
2363
2364 static __init int alloc_kvm_area(void)
2365 {
2366         int cpu;
2367
2368         for_each_possible_cpu(cpu) {
2369                 struct vmcs *vmcs;
2370
2371                 vmcs = alloc_vmcs_cpu(cpu);
2372                 if (!vmcs) {
2373                         free_kvm_area();
2374                         return -ENOMEM;
2375                 }
2376
2377                 per_cpu(vmxarea, cpu) = vmcs;
2378         }
2379         return 0;
2380 }
2381
2382 static __init int hardware_setup(void)
2383 {
2384         if (setup_vmcs_config(&vmcs_config) < 0)
2385                 return -EIO;
2386
2387         if (boot_cpu_has(X86_FEATURE_NX))
2388                 kvm_enable_efer_bits(EFER_NX);
2389
2390         if (!cpu_has_vmx_vpid())
2391                 enable_vpid = 0;
2392
2393         if (!cpu_has_vmx_ept() ||
2394             !cpu_has_vmx_ept_4levels()) {
2395                 enable_ept = 0;
2396                 enable_unrestricted_guest = 0;
2397         }
2398
2399         if (!cpu_has_vmx_unrestricted_guest())
2400                 enable_unrestricted_guest = 0;
2401
2402         if (!cpu_has_vmx_flexpriority())
2403                 flexpriority_enabled = 0;
2404
2405         if (!cpu_has_vmx_tpr_shadow())
2406                 kvm_x86_ops->update_cr8_intercept = NULL;
2407
2408         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2409                 kvm_disable_largepages();
2410
2411         if (!cpu_has_vmx_ple())
2412                 ple_gap = 0;
2413
2414         if (nested)
2415                 nested_vmx_setup_ctls_msrs();
2416
2417         return alloc_kvm_area();
2418 }
2419
2420 static __exit void hardware_unsetup(void)
2421 {
2422         free_kvm_area();
2423 }
2424
2425 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2426 {
2427         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2428
2429         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2430                 vmcs_write16(sf->selector, save->selector);
2431                 vmcs_writel(sf->base, save->base);
2432                 vmcs_write32(sf->limit, save->limit);
2433                 vmcs_write32(sf->ar_bytes, save->ar);
2434         } else {
2435                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2436                         << AR_DPL_SHIFT;
2437                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2438         }
2439 }
2440
2441 static void enter_pmode(struct kvm_vcpu *vcpu)
2442 {
2443         unsigned long flags;
2444         struct vcpu_vmx *vmx = to_vmx(vcpu);
2445
2446         vmx->emulation_required = 1;
2447         vmx->rmode.vm86_active = 0;
2448
2449         vmx_segment_cache_clear(vmx);
2450
2451         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2452         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2453         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2454         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2455
2456         flags = vmcs_readl(GUEST_RFLAGS);
2457         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2458         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2459         vmcs_writel(GUEST_RFLAGS, flags);
2460
2461         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2462                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2463
2464         update_exception_bitmap(vcpu);
2465
2466         if (emulate_invalid_guest_state)
2467                 return;
2468
2469         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2470         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2471         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2472         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2473
2474         vmx_segment_cache_clear(vmx);
2475
2476         vmcs_write16(GUEST_SS_SELECTOR, 0);
2477         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2478
2479         vmcs_write16(GUEST_CS_SELECTOR,
2480                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2481         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2482 }
2483
2484 static gva_t rmode_tss_base(struct kvm *kvm)
2485 {
2486         if (!kvm->arch.tss_addr) {
2487                 struct kvm_memslots *slots;
2488                 gfn_t base_gfn;
2489
2490                 slots = kvm_memslots(kvm);
2491                 base_gfn = slots->memslots[0].base_gfn +
2492                                  kvm->memslots->memslots[0].npages - 3;
2493                 return base_gfn << PAGE_SHIFT;
2494         }
2495         return kvm->arch.tss_addr;
2496 }
2497
2498 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2499 {
2500         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2501
2502         save->selector = vmcs_read16(sf->selector);
2503         save->base = vmcs_readl(sf->base);
2504         save->limit = vmcs_read32(sf->limit);
2505         save->ar = vmcs_read32(sf->ar_bytes);
2506         vmcs_write16(sf->selector, save->base >> 4);
2507         vmcs_write32(sf->base, save->base & 0xffff0);
2508         vmcs_write32(sf->limit, 0xffff);
2509         vmcs_write32(sf->ar_bytes, 0xf3);
2510         if (save->base & 0xf)
2511                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2512                             " aligned when entering protected mode (seg=%d)",
2513                             seg);
2514 }
2515
2516 static void enter_rmode(struct kvm_vcpu *vcpu)
2517 {
2518         unsigned long flags;
2519         struct vcpu_vmx *vmx = to_vmx(vcpu);
2520
2521         if (enable_unrestricted_guest)
2522                 return;
2523
2524         vmx->emulation_required = 1;
2525         vmx->rmode.vm86_active = 1;
2526
2527         /*
2528          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2529          * vcpu. Call it here with phys address pointing 16M below 4G.
2530          */
2531         if (!vcpu->kvm->arch.tss_addr) {
2532                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2533                              "called before entering vcpu\n");
2534                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2535                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2536                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2537         }
2538
2539         vmx_segment_cache_clear(vmx);
2540
2541         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2542         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2543         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2544
2545         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2546         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2547
2548         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2549         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2550
2551         flags = vmcs_readl(GUEST_RFLAGS);
2552         vmx->rmode.save_rflags = flags;
2553
2554         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2555
2556         vmcs_writel(GUEST_RFLAGS, flags);
2557         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2558         update_exception_bitmap(vcpu);
2559
2560         if (emulate_invalid_guest_state)
2561                 goto continue_rmode;
2562
2563         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2564         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2565         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2566
2567         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
2568         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2569         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2570                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
2571         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2572
2573         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2574         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2575         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2576         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
2577
2578 continue_rmode:
2579         kvm_mmu_reset_context(vcpu);
2580 }
2581
2582 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2583 {
2584         struct vcpu_vmx *vmx = to_vmx(vcpu);
2585         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2586
2587         if (!msr)
2588                 return;
2589
2590         /*
2591          * Force kernel_gs_base reloading before EFER changes, as control
2592          * of this msr depends on is_long_mode().
2593          */
2594         vmx_load_host_state(to_vmx(vcpu));
2595         vcpu->arch.efer = efer;
2596         if (efer & EFER_LMA) {
2597                 vmcs_write32(VM_ENTRY_CONTROLS,
2598                              vmcs_read32(VM_ENTRY_CONTROLS) |
2599                              VM_ENTRY_IA32E_MODE);
2600                 msr->data = efer;
2601         } else {
2602                 vmcs_write32(VM_ENTRY_CONTROLS,
2603                              vmcs_read32(VM_ENTRY_CONTROLS) &
2604                              ~VM_ENTRY_IA32E_MODE);
2605
2606                 msr->data = efer & ~EFER_LME;
2607         }
2608         setup_msrs(vmx);
2609 }
2610
2611 #ifdef CONFIG_X86_64
2612
2613 static void enter_lmode(struct kvm_vcpu *vcpu)
2614 {
2615         u32 guest_tr_ar;
2616
2617         vmx_segment_cache_clear(to_vmx(vcpu));
2618
2619         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2620         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2621                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
2622                        __func__);
2623                 vmcs_write32(GUEST_TR_AR_BYTES,
2624                              (guest_tr_ar & ~AR_TYPE_MASK)
2625                              | AR_TYPE_BUSY_64_TSS);
2626         }
2627         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2628 }
2629
2630 static void exit_lmode(struct kvm_vcpu *vcpu)
2631 {
2632         vmcs_write32(VM_ENTRY_CONTROLS,
2633                      vmcs_read32(VM_ENTRY_CONTROLS)
2634                      & ~VM_ENTRY_IA32E_MODE);
2635         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2636 }
2637
2638 #endif
2639
2640 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2641 {
2642         vpid_sync_context(to_vmx(vcpu));
2643         if (enable_ept) {
2644                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2645                         return;
2646                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2647         }
2648 }
2649
2650 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2651 {
2652         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2653
2654         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2655         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2656 }
2657
2658 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2659 {
2660         if (enable_ept && is_paging(vcpu))
2661                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2662         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2663 }
2664
2665 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2666 {
2667         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2668
2669         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2670         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2671 }
2672
2673 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2674 {
2675         if (!test_bit(VCPU_EXREG_PDPTR,
2676                       (unsigned long *)&vcpu->arch.regs_dirty))
2677                 return;
2678
2679         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2680                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2681                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2682                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2683                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2684         }
2685 }
2686
2687 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2688 {
2689         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2690                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2691                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2692                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2693                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2694         }
2695
2696         __set_bit(VCPU_EXREG_PDPTR,
2697                   (unsigned long *)&vcpu->arch.regs_avail);
2698         __set_bit(VCPU_EXREG_PDPTR,
2699                   (unsigned long *)&vcpu->arch.regs_dirty);
2700 }
2701
2702 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2703
2704 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2705                                         unsigned long cr0,
2706                                         struct kvm_vcpu *vcpu)
2707 {
2708         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2709                 vmx_decache_cr3(vcpu);
2710         if (!(cr0 & X86_CR0_PG)) {
2711                 /* From paging/starting to nonpaging */
2712                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2713                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2714                              (CPU_BASED_CR3_LOAD_EXITING |
2715                               CPU_BASED_CR3_STORE_EXITING));
2716                 vcpu->arch.cr0 = cr0;
2717                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2718         } else if (!is_paging(vcpu)) {
2719                 /* From nonpaging to paging */
2720                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2721                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2722                              ~(CPU_BASED_CR3_LOAD_EXITING |
2723                                CPU_BASED_CR3_STORE_EXITING));
2724                 vcpu->arch.cr0 = cr0;
2725                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2726         }
2727
2728         if (!(cr0 & X86_CR0_WP))
2729                 *hw_cr0 &= ~X86_CR0_WP;
2730 }
2731
2732 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2733 {
2734         struct vcpu_vmx *vmx = to_vmx(vcpu);
2735         unsigned long hw_cr0;
2736
2737         if (enable_unrestricted_guest)
2738                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2739                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2740         else
2741                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2742
2743         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2744                 enter_pmode(vcpu);
2745
2746         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2747                 enter_rmode(vcpu);
2748
2749 #ifdef CONFIG_X86_64
2750         if (vcpu->arch.efer & EFER_LME) {
2751                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2752                         enter_lmode(vcpu);
2753                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2754                         exit_lmode(vcpu);
2755         }
2756 #endif
2757
2758         if (enable_ept)
2759                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2760
2761         if (!vcpu->fpu_active)
2762                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2763
2764         vmcs_writel(CR0_READ_SHADOW, cr0);
2765         vmcs_writel(GUEST_CR0, hw_cr0);
2766         vcpu->arch.cr0 = cr0;
2767         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2768 }
2769
2770 static u64 construct_eptp(unsigned long root_hpa)
2771 {
2772         u64 eptp;
2773
2774         /* TODO write the value reading from MSR */
2775         eptp = VMX_EPT_DEFAULT_MT |
2776                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2777         eptp |= (root_hpa & PAGE_MASK);
2778
2779         return eptp;
2780 }
2781
2782 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2783 {
2784         unsigned long guest_cr3;
2785         u64 eptp;
2786
2787         guest_cr3 = cr3;
2788         if (enable_ept) {
2789                 eptp = construct_eptp(cr3);
2790                 vmcs_write64(EPT_POINTER, eptp);
2791                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
2792                         vcpu->kvm->arch.ept_identity_map_addr;
2793                 ept_load_pdptrs(vcpu);
2794         }
2795
2796         vmx_flush_tlb(vcpu);
2797         vmcs_writel(GUEST_CR3, guest_cr3);
2798 }
2799
2800 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2801 {
2802         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
2803                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2804
2805         if (cr4 & X86_CR4_VMXE) {
2806                 /*
2807                  * To use VMXON (and later other VMX instructions), a guest
2808                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
2809                  * So basically the check on whether to allow nested VMX
2810                  * is here.
2811                  */
2812                 if (!nested_vmx_allowed(vcpu))
2813                         return 1;
2814         } else if (to_vmx(vcpu)->nested.vmxon)
2815                 return 1;
2816
2817         vcpu->arch.cr4 = cr4;
2818         if (enable_ept) {
2819                 if (!is_paging(vcpu)) {
2820                         hw_cr4 &= ~X86_CR4_PAE;
2821                         hw_cr4 |= X86_CR4_PSE;
2822                 } else if (!(cr4 & X86_CR4_PAE)) {
2823                         hw_cr4 &= ~X86_CR4_PAE;
2824                 }
2825         }
2826
2827         vmcs_writel(CR4_READ_SHADOW, cr4);
2828         vmcs_writel(GUEST_CR4, hw_cr4);
2829         return 0;
2830 }
2831
2832 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2833                             struct kvm_segment *var, int seg)
2834 {
2835         struct vcpu_vmx *vmx = to_vmx(vcpu);
2836         struct kvm_save_segment *save;
2837         u32 ar;
2838
2839         if (vmx->rmode.vm86_active
2840             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2841                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2842                 || seg == VCPU_SREG_GS)
2843             && !emulate_invalid_guest_state) {
2844                 switch (seg) {
2845                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2846                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2847                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2848                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2849                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2850                 default: BUG();
2851                 }
2852                 var->selector = save->selector;
2853                 var->base = save->base;
2854                 var->limit = save->limit;
2855                 ar = save->ar;
2856                 if (seg == VCPU_SREG_TR
2857                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
2858                         goto use_saved_rmode_seg;
2859         }
2860         var->base = vmx_read_guest_seg_base(vmx, seg);
2861         var->limit = vmx_read_guest_seg_limit(vmx, seg);
2862         var->selector = vmx_read_guest_seg_selector(vmx, seg);
2863         ar = vmx_read_guest_seg_ar(vmx, seg);
2864 use_saved_rmode_seg:
2865         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2866                 ar = 0;
2867         var->type = ar & 15;
2868         var->s = (ar >> 4) & 1;
2869         var->dpl = (ar >> 5) & 3;
2870         var->present = (ar >> 7) & 1;
2871         var->avl = (ar >> 12) & 1;
2872         var->l = (ar >> 13) & 1;
2873         var->db = (ar >> 14) & 1;
2874         var->g = (ar >> 15) & 1;
2875         var->unusable = (ar >> 16) & 1;
2876 }
2877
2878 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2879 {
2880         struct kvm_segment s;
2881
2882         if (to_vmx(vcpu)->rmode.vm86_active) {
2883                 vmx_get_segment(vcpu, &s, seg);
2884                 return s.base;
2885         }
2886         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
2887 }
2888
2889 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2890 {
2891         if (!is_protmode(vcpu))
2892                 return 0;
2893
2894         if (!is_long_mode(vcpu)
2895             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2896                 return 3;
2897
2898         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2899 }
2900
2901 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2902 {
2903         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
2904                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2905                 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
2906         }
2907         return to_vmx(vcpu)->cpl;
2908 }
2909
2910
2911 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2912 {
2913         u32 ar;
2914
2915         if (var->unusable)
2916                 ar = 1 << 16;
2917         else {
2918                 ar = var->type & 15;
2919                 ar |= (var->s & 1) << 4;
2920                 ar |= (var->dpl & 3) << 5;
2921                 ar |= (var->present & 1) << 7;
2922                 ar |= (var->avl & 1) << 12;
2923                 ar |= (var->l & 1) << 13;
2924                 ar |= (var->db & 1) << 14;
2925                 ar |= (var->g & 1) << 15;
2926         }
2927         if (ar == 0) /* a 0 value means unusable */
2928                 ar = AR_UNUSABLE_MASK;
2929
2930         return ar;
2931 }
2932
2933 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2934                             struct kvm_segment *var, int seg)
2935 {
2936         struct vcpu_vmx *vmx = to_vmx(vcpu);
2937         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2938         u32 ar;
2939
2940         vmx_segment_cache_clear(vmx);
2941
2942         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2943                 vmcs_write16(sf->selector, var->selector);
2944                 vmx->rmode.tr.selector = var->selector;
2945                 vmx->rmode.tr.base = var->base;
2946                 vmx->rmode.tr.limit = var->limit;
2947                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2948                 return;
2949         }
2950         vmcs_writel(sf->base, var->base);
2951         vmcs_write32(sf->limit, var->limit);
2952         vmcs_write16(sf->selector, var->selector);
2953         if (vmx->rmode.vm86_active && var->s) {
2954                 /*
2955                  * Hack real-mode segments into vm86 compatibility.
2956                  */
2957                 if (var->base == 0xffff0000 && var->selector == 0xf000)
2958                         vmcs_writel(sf->base, 0xf0000);
2959                 ar = 0xf3;
2960         } else
2961                 ar = vmx_segment_access_rights(var);
2962
2963         /*
2964          *   Fix the "Accessed" bit in AR field of segment registers for older
2965          * qemu binaries.
2966          *   IA32 arch specifies that at the time of processor reset the
2967          * "Accessed" bit in the AR field of segment registers is 1. And qemu
2968          * is setting it to 0 in the usedland code. This causes invalid guest
2969          * state vmexit when "unrestricted guest" mode is turned on.
2970          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
2971          * tree. Newer qemu binaries with that qemu fix would not need this
2972          * kvm hack.
2973          */
2974         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2975                 ar |= 0x1; /* Accessed */
2976
2977         vmcs_write32(sf->ar_bytes, ar);
2978         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2979 }
2980
2981 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2982 {
2983         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
2984
2985         *db = (ar >> 14) & 1;
2986         *l = (ar >> 13) & 1;
2987 }
2988
2989 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2990 {
2991         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2992         dt->address = vmcs_readl(GUEST_IDTR_BASE);
2993 }
2994
2995 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2996 {
2997         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2998         vmcs_writel(GUEST_IDTR_BASE, dt->address);
2999 }
3000
3001 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3002 {
3003         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3004         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3005 }
3006
3007 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3008 {
3009         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3010         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3011 }
3012
3013 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3014 {
3015         struct kvm_segment var;
3016         u32 ar;
3017
3018         vmx_get_segment(vcpu, &var, seg);
3019         ar = vmx_segment_access_rights(&var);
3020
3021         if (var.base != (var.selector << 4))
3022                 return false;
3023         if (var.limit != 0xffff)
3024                 return false;
3025         if (ar != 0xf3)
3026                 return false;
3027
3028         return true;
3029 }
3030
3031 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3032 {
3033         struct kvm_segment cs;
3034         unsigned int cs_rpl;
3035
3036         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3037         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3038
3039         if (cs.unusable)
3040                 return false;
3041         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3042                 return false;
3043         if (!cs.s)
3044                 return false;
3045         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3046                 if (cs.dpl > cs_rpl)
3047                         return false;
3048         } else {
3049                 if (cs.dpl != cs_rpl)
3050                         return false;
3051         }
3052         if (!cs.present)
3053                 return false;
3054
3055         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3056         return true;
3057 }
3058
3059 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3060 {
3061         struct kvm_segment ss;
3062         unsigned int ss_rpl;
3063
3064         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3065         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3066
3067         if (ss.unusable)
3068                 return true;
3069         if (ss.type != 3 && ss.type != 7)
3070                 return false;
3071         if (!ss.s)
3072                 return false;
3073         if (ss.dpl != ss_rpl) /* DPL != RPL */
3074                 return false;
3075         if (!ss.present)
3076                 return false;
3077
3078         return true;
3079 }
3080
3081 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3082 {
3083         struct kvm_segment var;
3084         unsigned int rpl;
3085
3086         vmx_get_segment(vcpu, &var, seg);
3087         rpl = var.selector & SELECTOR_RPL_MASK;
3088
3089         if (var.unusable)
3090                 return true;
3091         if (!var.s)
3092                 return false;
3093         if (!var.present)
3094                 return false;
3095         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3096                 if (var.dpl < rpl) /* DPL < RPL */
3097                         return false;
3098         }
3099
3100         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3101          * rights flags
3102          */
3103         return true;
3104 }
3105
3106 static bool tr_valid(struct kvm_vcpu *vcpu)
3107 {
3108         struct kvm_segment tr;
3109
3110         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3111
3112         if (tr.unusable)
3113                 return false;
3114         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3115                 return false;
3116         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3117                 return false;
3118         if (!tr.present)
3119                 return false;
3120
3121         return true;
3122 }
3123
3124 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3125 {
3126         struct kvm_segment ldtr;
3127
3128         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3129
3130         if (ldtr.unusable)
3131                 return true;
3132         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3133                 return false;
3134         if (ldtr.type != 2)
3135                 return false;
3136         if (!ldtr.present)
3137                 return false;
3138
3139         return true;
3140 }
3141
3142 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3143 {
3144         struct kvm_segment cs, ss;
3145
3146         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3147         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3148
3149         return ((cs.selector & SELECTOR_RPL_MASK) ==
3150                  (ss.selector & SELECTOR_RPL_MASK));
3151 }
3152
3153 /*
3154  * Check if guest state is valid. Returns true if valid, false if
3155  * not.
3156  * We assume that registers are always usable
3157  */
3158 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3159 {
3160         /* real mode guest state checks */
3161         if (!is_protmode(vcpu)) {
3162                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3163                         return false;
3164                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3165                         return false;
3166                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3167                         return false;
3168                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3169                         return false;
3170                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3171                         return false;
3172                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3173                         return false;
3174         } else {
3175         /* protected mode guest state checks */
3176                 if (!cs_ss_rpl_check(vcpu))
3177                         return false;
3178                 if (!code_segment_valid(vcpu))
3179                         return false;
3180                 if (!stack_segment_valid(vcpu))
3181                         return false;
3182                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3183                         return false;
3184                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3185                         return false;
3186                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3187                         return false;
3188                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3189                         return false;
3190                 if (!tr_valid(vcpu))
3191                         return false;
3192                 if (!ldtr_valid(vcpu))
3193                         return false;
3194         }
3195         /* TODO:
3196          * - Add checks on RIP
3197          * - Add checks on RFLAGS
3198          */
3199
3200         return true;
3201 }
3202
3203 static int init_rmode_tss(struct kvm *kvm)
3204 {
3205         gfn_t fn;
3206         u16 data = 0;
3207         int r, idx, ret = 0;
3208
3209         idx = srcu_read_lock(&kvm->srcu);
3210         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3211         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3212         if (r < 0)
3213                 goto out;
3214         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3215         r = kvm_write_guest_page(kvm, fn++, &data,
3216                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3217         if (r < 0)
3218                 goto out;
3219         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3220         if (r < 0)
3221                 goto out;
3222         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3223         if (r < 0)
3224                 goto out;
3225         data = ~0;
3226         r = kvm_write_guest_page(kvm, fn, &data,
3227                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3228                                  sizeof(u8));
3229         if (r < 0)
3230                 goto out;
3231
3232         ret = 1;
3233 out:
3234         srcu_read_unlock(&kvm->srcu, idx);
3235         return ret;
3236 }
3237
3238 static int init_rmode_identity_map(struct kvm *kvm)
3239 {
3240         int i, idx, r, ret;
3241         pfn_t identity_map_pfn;
3242         u32 tmp;
3243
3244         if (!enable_ept)
3245                 return 1;
3246         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3247                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3248                         "haven't been allocated!\n");
3249                 return 0;
3250         }
3251         if (likely(kvm->arch.ept_identity_pagetable_done))
3252                 return 1;
3253         ret = 0;
3254         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3255         idx = srcu_read_lock(&kvm->srcu);
3256         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3257         if (r < 0)
3258                 goto out;
3259         /* Set up identity-mapping pagetable for EPT in real mode */
3260         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3261                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3262                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3263                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3264                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3265                 if (r < 0)
3266                         goto out;
3267         }
3268         kvm->arch.ept_identity_pagetable_done = true;
3269         ret = 1;
3270 out:
3271         srcu_read_unlock(&kvm->srcu, idx);
3272         return ret;
3273 }
3274
3275 static void seg_setup(int seg)
3276 {
3277         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3278         unsigned int ar;
3279
3280         vmcs_write16(sf->selector, 0);
3281         vmcs_writel(sf->base, 0);
3282         vmcs_write32(sf->limit, 0xffff);
3283         if (enable_unrestricted_guest) {
3284                 ar = 0x93;
3285                 if (seg == VCPU_SREG_CS)
3286                         ar |= 0x08; /* code segment */
3287         } else
3288                 ar = 0xf3;
3289
3290         vmcs_write32(sf->ar_bytes, ar);
3291 }
3292
3293 static int alloc_apic_access_page(struct kvm *kvm)
3294 {
3295         struct kvm_userspace_memory_region kvm_userspace_mem;
3296         int r = 0;
3297
3298         mutex_lock(&kvm->slots_lock);
3299         if (kvm->arch.apic_access_page)
3300                 goto out;
3301         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3302         kvm_userspace_mem.flags = 0;
3303         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3304         kvm_userspace_mem.memory_size = PAGE_SIZE;
3305         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3306         if (r)
3307                 goto out;
3308
3309         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3310 out:
3311         mutex_unlock(&kvm->slots_lock);
3312         return r;
3313 }
3314
3315 static int alloc_identity_pagetable(struct kvm *kvm)
3316 {
3317         struct kvm_userspace_memory_region kvm_userspace_mem;
3318         int r = 0;
3319
3320         mutex_lock(&kvm->slots_lock);
3321         if (kvm->arch.ept_identity_pagetable)
3322                 goto out;
3323         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3324         kvm_userspace_mem.flags = 0;
3325         kvm_userspace_mem.guest_phys_addr =
3326                 kvm->arch.ept_identity_map_addr;
3327         kvm_userspace_mem.memory_size = PAGE_SIZE;
3328         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3329         if (r)
3330                 goto out;
3331
3332         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3333                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3334 out:
3335         mutex_unlock(&kvm->slots_lock);
3336         return r;
3337 }
3338
3339 static void allocate_vpid(struct vcpu_vmx *vmx)
3340 {
3341         int vpid;
3342
3343         vmx->vpid = 0;
3344         if (!enable_vpid)
3345                 return;
3346         spin_lock(&vmx_vpid_lock);
3347         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3348         if (vpid < VMX_NR_VPIDS) {
3349                 vmx->vpid = vpid;
3350                 __set_bit(vpid, vmx_vpid_bitmap);
3351         }
3352         spin_unlock(&vmx_vpid_lock);
3353 }
3354
3355 static void free_vpid(struct vcpu_vmx *vmx)
3356 {
3357         if (!enable_vpid)
3358                 return;
3359         spin_lock(&vmx_vpid_lock);
3360         if (vmx->vpid != 0)
3361                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3362         spin_unlock(&vmx_vpid_lock);
3363 }
3364
3365 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3366 {
3367         int f = sizeof(unsigned long);
3368
3369         if (!cpu_has_vmx_msr_bitmap())
3370                 return;
3371
3372         /*
3373          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3374          * have the write-low and read-high bitmap offsets the wrong way round.
3375          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3376          */
3377         if (msr <= 0x1fff) {
3378                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3379                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3380         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3381                 msr &= 0x1fff;
3382                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3383                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3384         }
3385 }
3386
3387 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3388 {
3389         if (!longmode_only)
3390                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3391         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3392 }
3393
3394 /*
3395  * Sets up the vmcs for emulated real mode.
3396  */
3397 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3398 {
3399         u32 host_sysenter_cs, msr_low, msr_high;
3400         u32 junk;
3401         u64 host_pat;
3402         unsigned long a;
3403         struct desc_ptr dt;
3404         int i;
3405         unsigned long kvm_vmx_return;
3406         u32 exec_control;
3407
3408         /* I/O */
3409         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3410         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3411
3412         if (cpu_has_vmx_msr_bitmap())
3413                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3414
3415         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3416
3417         /* Control */
3418         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3419                 vmcs_config.pin_based_exec_ctrl);
3420
3421         exec_control = vmcs_config.cpu_based_exec_ctrl;
3422         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3423                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3424 #ifdef CONFIG_X86_64
3425                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3426                                 CPU_BASED_CR8_LOAD_EXITING;
3427 #endif
3428         }
3429         if (!enable_ept)
3430                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3431                                 CPU_BASED_CR3_LOAD_EXITING  |
3432                                 CPU_BASED_INVLPG_EXITING;
3433         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
3434
3435         if (cpu_has_secondary_exec_ctrls()) {
3436                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3437                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3438                         exec_control &=
3439                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3440                 if (vmx->vpid == 0)
3441                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3442                 if (!enable_ept) {
3443                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3444                         enable_unrestricted_guest = 0;
3445                 }
3446                 if (!enable_unrestricted_guest)
3447                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3448                 if (!ple_gap)
3449                         exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3450                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
3451         }
3452
3453         if (ple_gap) {
3454                 vmcs_write32(PLE_GAP, ple_gap);
3455                 vmcs_write32(PLE_WINDOW, ple_window);
3456         }
3457
3458         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
3459         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
3460         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
3461
3462         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
3463         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
3464         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
3465
3466         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3467         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3468         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3469         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
3470         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
3471         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3472 #ifdef CONFIG_X86_64
3473         rdmsrl(MSR_FS_BASE, a);
3474         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3475         rdmsrl(MSR_GS_BASE, a);
3476         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3477 #else
3478         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3479         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3480 #endif
3481
3482         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3483
3484         native_store_idt(&dt);
3485         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3486
3487         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
3488         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
3489         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3490         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3491         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3492         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3493         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3494
3495         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
3496         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
3497         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
3498         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
3499         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
3500         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
3501
3502         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3503                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3504                 host_pat = msr_low | ((u64) msr_high << 32);
3505                 vmcs_write64(HOST_IA32_PAT, host_pat);
3506         }
3507         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3508                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3509                 host_pat = msr_low | ((u64) msr_high << 32);
3510                 /* Write the default value follow host pat */
3511                 vmcs_write64(GUEST_IA32_PAT, host_pat);
3512                 /* Keep arch.pat sync with GUEST_IA32_PAT */
3513                 vmx->vcpu.arch.pat = host_pat;
3514         }
3515
3516         for (i = 0; i < NR_VMX_MSR; ++i) {
3517                 u32 index = vmx_msr_index[i];
3518                 u32 data_low, data_high;
3519                 int j = vmx->nmsrs;
3520
3521                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3522                         continue;
3523                 if (wrmsr_safe(index, data_low, data_high) < 0)
3524                         continue;
3525                 vmx->guest_msrs[j].index = i;
3526                 vmx->guest_msrs[j].data = 0;
3527                 vmx->guest_msrs[j].mask = -1ull;
3528                 ++vmx->nmsrs;
3529         }
3530
3531         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3532
3533         /* 22.2.1, 20.8.1 */
3534         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3535
3536         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3537         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3538         if (enable_ept)
3539                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3540         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3541
3542         kvm_write_tsc(&vmx->vcpu, 0);
3543
3544         return 0;
3545 }
3546
3547 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3548 {
3549         struct vcpu_vmx *vmx = to_vmx(vcpu);
3550         u64 msr;
3551         int ret;
3552
3553         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3554
3555         vmx->rmode.vm86_active = 0;
3556
3557         vmx->soft_vnmi_blocked = 0;
3558
3559         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3560         kvm_set_cr8(&vmx->vcpu, 0);
3561         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3562         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3563                 msr |= MSR_IA32_APICBASE_BSP;
3564         kvm_set_apic_base(&vmx->vcpu, msr);
3565
3566         ret = fx_init(&vmx->vcpu);
3567         if (ret != 0)
3568                 goto out;
3569
3570         vmx_segment_cache_clear(vmx);
3571
3572         seg_setup(VCPU_SREG_CS);
3573         /*
3574          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3575          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
3576          */
3577         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3578                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3579                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3580         } else {
3581                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3582                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3583         }
3584
3585         seg_setup(VCPU_SREG_DS);
3586         seg_setup(VCPU_SREG_ES);
3587         seg_setup(VCPU_SREG_FS);
3588         seg_setup(VCPU_SREG_GS);
3589         seg_setup(VCPU_SREG_SS);
3590
3591         vmcs_write16(GUEST_TR_SELECTOR, 0);
3592         vmcs_writel(GUEST_TR_BASE, 0);
3593         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3594         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3595
3596         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3597         vmcs_writel(GUEST_LDTR_BASE, 0);
3598         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3599         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3600
3601         vmcs_write32(GUEST_SYSENTER_CS, 0);
3602         vmcs_writel(GUEST_SYSENTER_ESP, 0);
3603         vmcs_writel(GUEST_SYSENTER_EIP, 0);
3604
3605         vmcs_writel(GUEST_RFLAGS, 0x02);
3606         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3607                 kvm_rip_write(vcpu, 0xfff0);
3608         else
3609                 kvm_rip_write(vcpu, 0);
3610         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3611
3612         vmcs_writel(GUEST_DR7, 0x400);
3613
3614         vmcs_writel(GUEST_GDTR_BASE, 0);
3615         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3616
3617         vmcs_writel(GUEST_IDTR_BASE, 0);
3618         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3619
3620         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3621         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3622         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3623
3624         /* Special registers */
3625         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3626
3627         setup_msrs(vmx);
3628
3629         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
3630
3631         if (cpu_has_vmx_tpr_shadow()) {
3632                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3633                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3634                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3635                                      __pa(vmx->vcpu.arch.apic->regs));
3636                 vmcs_write32(TPR_THRESHOLD, 0);
3637         }
3638
3639         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3640                 vmcs_write64(APIC_ACCESS_ADDR,
3641                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3642
3643         if (vmx->vpid != 0)
3644                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3645
3646         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3647         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3648         vmx_set_cr4(&vmx->vcpu, 0);
3649         vmx_set_efer(&vmx->vcpu, 0);
3650         vmx_fpu_activate(&vmx->vcpu);
3651         update_exception_bitmap(&vmx->vcpu);
3652
3653         vpid_sync_context(vmx);
3654
3655         ret = 0;
3656
3657         /* HACK: Don't enable emulation on guest boot/reset */
3658         vmx->emulation_required = 0;
3659
3660 out:
3661         return ret;
3662 }
3663
3664 static void enable_irq_window(struct kvm_vcpu *vcpu)
3665 {
3666         u32 cpu_based_vm_exec_control;
3667
3668         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3669         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3670         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3671 }
3672
3673 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3674 {
3675         u32 cpu_based_vm_exec_control;
3676
3677         if (!cpu_has_virtual_nmis()) {
3678                 enable_irq_window(vcpu);
3679                 return;
3680         }
3681
3682         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3683                 enable_irq_window(vcpu);
3684                 return;
3685         }
3686         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3687         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3688         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3689 }
3690
3691 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
3692 {
3693         struct vcpu_vmx *vmx = to_vmx(vcpu);
3694         uint32_t intr;
3695         int irq = vcpu->arch.interrupt.nr;
3696
3697         trace_kvm_inj_virq(irq);
3698
3699         ++vcpu->stat.irq_injections;
3700         if (vmx->rmode.vm86_active) {
3701                 int inc_eip = 0;
3702                 if (vcpu->arch.interrupt.soft)
3703                         inc_eip = vcpu->arch.event_exit_inst_len;
3704                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
3705                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3706                 return;
3707         }
3708         intr = irq | INTR_INFO_VALID_MASK;
3709         if (vcpu->arch.interrupt.soft) {
3710                 intr |= INTR_TYPE_SOFT_INTR;
3711                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3712                              vmx->vcpu.arch.event_exit_inst_len);
3713         } else
3714                 intr |= INTR_TYPE_EXT_INTR;
3715         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
3716         vmx_clear_hlt(vcpu);
3717 }
3718
3719 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
3720 {
3721         struct vcpu_vmx *vmx = to_vmx(vcpu);
3722
3723         if (!cpu_has_virtual_nmis()) {
3724                 /*
3725                  * Tracking the NMI-blocked state in software is built upon
3726                  * finding the next open IRQ window. This, in turn, depends on
3727                  * well-behaving guests: They have to keep IRQs disabled at
3728                  * least as long as the NMI handler runs. Otherwise we may
3729                  * cause NMI nesting, maybe breaking the guest. But as this is
3730                  * highly unlikely, we can live with the residual risk.
3731                  */
3732                 vmx->soft_vnmi_blocked = 1;
3733                 vmx->vnmi_blocked_time = 0;
3734         }
3735
3736         ++vcpu->stat.nmi_injections;
3737         vmx->nmi_known_unmasked = false;
3738         if (vmx->rmode.vm86_active) {
3739                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
3740                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3741                 return;
3742         }
3743         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
3744                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
3745         vmx_clear_hlt(vcpu);
3746 }
3747
3748 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
3749 {
3750         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
3751                 return 0;
3752
3753         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3754                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
3755                    | GUEST_INTR_STATE_NMI));
3756 }
3757
3758 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3759 {
3760         if (!cpu_has_virtual_nmis())
3761                 return to_vmx(vcpu)->soft_vnmi_blocked;
3762         if (to_vmx(vcpu)->nmi_known_unmasked)
3763                 return false;
3764         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3765 }
3766
3767 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3768 {
3769         struct vcpu_vmx *vmx = to_vmx(vcpu);
3770
3771         if (!cpu_has_virtual_nmis()) {
3772                 if (vmx->soft_vnmi_blocked != masked) {
3773                         vmx->soft_vnmi_blocked = masked;
3774                         vmx->vnmi_blocked_time = 0;
3775                 }
3776         } else {
3777                 vmx->nmi_known_unmasked = !masked;
3778                 if (masked)
3779                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3780                                       GUEST_INTR_STATE_NMI);
3781                 else
3782                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3783                                         GUEST_INTR_STATE_NMI);
3784         }
3785 }
3786
3787 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
3788 {
3789         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
3790                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3791                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
3792 }
3793
3794 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
3795 {
3796         int ret;
3797         struct kvm_userspace_memory_region tss_mem = {
3798                 .slot = TSS_PRIVATE_MEMSLOT,
3799                 .guest_phys_addr = addr,
3800                 .memory_size = PAGE_SIZE * 3,
3801                 .flags = 0,
3802         };
3803
3804         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3805         if (ret)
3806                 return ret;
3807         kvm->arch.tss_addr = addr;
3808         if (!init_rmode_tss(kvm))
3809                 return  -ENOMEM;
3810
3811         return 0;
3812 }
3813
3814 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3815                                   int vec, u32 err_code)
3816 {
3817         /*
3818          * Instruction with address size override prefix opcode 0x67
3819          * Cause the #SS fault with 0 error code in VM86 mode.
3820          */
3821         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3822                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
3823                         return 1;
3824         /*
3825          * Forward all other exceptions that are valid in real mode.
3826          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3827          *        the required debugging infrastructure rework.
3828          */
3829         switch (vec) {
3830         case DB_VECTOR:
3831                 if (vcpu->guest_debug &
3832                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
3833                         return 0;
3834                 kvm_queue_exception(vcpu, vec);
3835                 return 1;
3836         case BP_VECTOR:
3837                 /*
3838                  * Update instruction length as we may reinject the exception
3839                  * from user space while in guest debugging mode.
3840                  */
3841                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3842                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3843                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3844                         return 0;
3845                 /* fall through */
3846         case DE_VECTOR:
3847         case OF_VECTOR:
3848         case BR_VECTOR:
3849         case UD_VECTOR:
3850         case DF_VECTOR:
3851         case SS_VECTOR:
3852         case GP_VECTOR:
3853         case MF_VECTOR:
3854                 kvm_queue_exception(vcpu, vec);
3855                 return 1;
3856         }
3857         return 0;
3858 }
3859
3860 /*
3861  * Trigger machine check on the host. We assume all the MSRs are already set up
3862  * by the CPU and that we still run on the same CPU as the MCE occurred on.
3863  * We pass a fake environment to the machine check handler because we want
3864  * the guest to be always treated like user space, no matter what context
3865  * it used internally.
3866  */
3867 static void kvm_machine_check(void)
3868 {
3869 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3870         struct pt_regs regs = {
3871                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3872                 .flags = X86_EFLAGS_IF,
3873         };
3874
3875         do_machine_check(&regs, 0);
3876 #endif
3877 }
3878
3879 static int handle_machine_check(struct kvm_vcpu *vcpu)
3880 {
3881         /* already handled by vcpu_run */
3882         return 1;
3883 }
3884
3885 static int handle_exception(struct kvm_vcpu *vcpu)
3886 {
3887         struct vcpu_vmx *vmx = to_vmx(vcpu);
3888         struct kvm_run *kvm_run = vcpu->run;
3889         u32 intr_info, ex_no, error_code;
3890         unsigned long cr2, rip, dr6;
3891         u32 vect_info;
3892         enum emulation_result er;
3893
3894         vect_info = vmx->idt_vectoring_info;
3895         intr_info = vmx->exit_intr_info;
3896
3897         if (is_machine_check(intr_info))
3898                 return handle_machine_check(vcpu);
3899
3900         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3901             !is_page_fault(intr_info)) {
3902                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3903                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3904                 vcpu->run->internal.ndata = 2;
3905                 vcpu->run->internal.data[0] = vect_info;
3906                 vcpu->run->internal.data[1] = intr_info;
3907                 return 0;
3908         }
3909
3910         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3911                 return 1;  /* already handled by vmx_vcpu_run() */
3912
3913         if (is_no_device(intr_info)) {
3914                 vmx_fpu_activate(vcpu);
3915                 return 1;
3916         }
3917
3918         if (is_invalid_opcode(intr_info)) {
3919                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
3920                 if (er != EMULATE_DONE)
3921                         kvm_queue_exception(vcpu, UD_VECTOR);
3922                 return 1;
3923         }
3924
3925         error_code = 0;
3926         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3927                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3928         if (is_page_fault(intr_info)) {
3929                 /* EPT won't cause page fault directly */
3930                 if (enable_ept)
3931                         BUG();
3932                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3933                 trace_kvm_page_fault(cr2, error_code);
3934
3935                 if (kvm_event_needs_reinjection(vcpu))
3936                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
3937                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
3938         }
3939
3940         if (vmx->rmode.vm86_active &&
3941             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3942                                                                 error_code)) {
3943                 if (vcpu->arch.halt_request) {
3944                         vcpu->arch.halt_request = 0;
3945                         return kvm_emulate_halt(vcpu);
3946                 }
3947                 return 1;
3948         }
3949
3950         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3951         switch (ex_no) {
3952         case DB_VECTOR:
3953                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3954                 if (!(vcpu->guest_debug &
3955                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3956                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3957                         kvm_queue_exception(vcpu, DB_VECTOR);
3958                         return 1;
3959                 }
3960                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3961                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3962                 /* fall through */
3963         case BP_VECTOR:
3964                 /*
3965                  * Update instruction length as we may reinject #BP from
3966                  * user space while in guest debugging mode. Reading it for
3967                  * #DB as well causes no harm, it is not used in that case.
3968                  */
3969                 vmx->vcpu.arch.event_exit_inst_len =
3970                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3971                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3972                 rip = kvm_rip_read(vcpu);
3973                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3974                 kvm_run->debug.arch.exception = ex_no;
3975                 break;
3976         default:
3977                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3978                 kvm_run->ex.exception = ex_no;
3979                 kvm_run->ex.error_code = error_code;
3980                 break;
3981         }
3982         return 0;
3983 }
3984
3985 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3986 {
3987         ++vcpu->stat.irq_exits;
3988         return 1;
3989 }
3990
3991 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3992 {
3993         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3994         return 0;
3995 }
3996
3997 static int handle_io(struct kvm_vcpu *vcpu)
3998 {
3999         unsigned long exit_qualification;
4000         int size, in, string;
4001         unsigned port;
4002
4003         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4004         string = (exit_qualification & 16) != 0;
4005         in = (exit_qualification & 8) != 0;
4006
4007         ++vcpu->stat.io_exits;
4008
4009         if (string || in)
4010                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4011
4012         port = exit_qualification >> 16;
4013         size = (exit_qualification & 7) + 1;
4014         skip_emulated_instruction(vcpu);
4015
4016         return kvm_fast_pio_out(vcpu, size, port);
4017 }
4018
4019 static void
4020 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4021 {
4022         /*
4023          * Patch in the VMCALL instruction:
4024          */
4025         hypercall[0] = 0x0f;
4026         hypercall[1] = 0x01;
4027         hypercall[2] = 0xc1;
4028 }
4029
4030 static int handle_cr(struct kvm_vcpu *vcpu)
4031 {
4032         unsigned long exit_qualification, val;
4033         int cr;
4034         int reg;
4035         int err;
4036
4037         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4038         cr = exit_qualification & 15;
4039         reg = (exit_qualification >> 8) & 15;
4040         switch ((exit_qualification >> 4) & 3) {
4041         case 0: /* mov to cr */
4042                 val = kvm_register_read(vcpu, reg);
4043                 trace_kvm_cr_write(cr, val);
4044                 switch (cr) {
4045                 case 0:
4046                         err = kvm_set_cr0(vcpu, val);
4047                         kvm_complete_insn_gp(vcpu, err);
4048                         return 1;
4049                 case 3:
4050                         err = kvm_set_cr3(vcpu, val);
4051                         kvm_complete_insn_gp(vcpu, err);
4052                         return 1;
4053                 case 4:
4054                         err = kvm_set_cr4(vcpu, val);
4055                         kvm_complete_insn_gp(vcpu, err);
4056                         return 1;
4057                 case 8: {
4058                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4059                                 u8 cr8 = kvm_register_read(vcpu, reg);
4060                                 err = kvm_set_cr8(vcpu, cr8);
4061                                 kvm_complete_insn_gp(vcpu, err);
4062                                 if (irqchip_in_kernel(vcpu->kvm))
4063                                         return 1;
4064                                 if (cr8_prev <= cr8)
4065                                         return 1;
4066                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4067                                 return 0;
4068                         }
4069                 };
4070                 break;
4071         case 2: /* clts */
4072                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4073                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4074                 skip_emulated_instruction(vcpu);
4075                 vmx_fpu_activate(vcpu);
4076                 return 1;
4077         case 1: /*mov from cr*/
4078                 switch (cr) {
4079                 case 3:
4080                         val = kvm_read_cr3(vcpu);
4081                         kvm_register_write(vcpu, reg, val);
4082                         trace_kvm_cr_read(cr, val);
4083                         skip_emulated_instruction(vcpu);
4084                         return 1;
4085                 case 8:
4086                         val = kvm_get_cr8(vcpu);
4087                         kvm_register_write(vcpu, reg, val);
4088                         trace_kvm_cr_read(cr, val);
4089                         skip_emulated_instruction(vcpu);
4090                         return 1;
4091                 }
4092                 break;
4093         case 3: /* lmsw */
4094                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4095                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4096                 kvm_lmsw(vcpu, val);
4097
4098                 skip_emulated_instruction(vcpu);
4099                 return 1;
4100         default:
4101                 break;
4102         }
4103         vcpu->run->exit_reason = 0;
4104         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4105                (int)(exit_qualification >> 4) & 3, cr);
4106         return 0;
4107 }
4108
4109 static int handle_dr(struct kvm_vcpu *vcpu)
4110 {
4111         unsigned long exit_qualification;
4112         int dr, reg;
4113
4114         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4115         if (!kvm_require_cpl(vcpu, 0))
4116                 return 1;
4117         dr = vmcs_readl(GUEST_DR7);
4118         if (dr & DR7_GD) {
4119                 /*
4120                  * As the vm-exit takes precedence over the debug trap, we
4121                  * need to emulate the latter, either for the host or the
4122                  * guest debugging itself.
4123                  */
4124                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4125                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4126                         vcpu->run->debug.arch.dr7 = dr;
4127                         vcpu->run->debug.arch.pc =
4128                                 vmcs_readl(GUEST_CS_BASE) +
4129                                 vmcs_readl(GUEST_RIP);
4130                         vcpu->run->debug.arch.exception = DB_VECTOR;
4131                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4132                         return 0;
4133                 } else {
4134                         vcpu->arch.dr7 &= ~DR7_GD;
4135                         vcpu->arch.dr6 |= DR6_BD;
4136                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4137                         kvm_queue_exception(vcpu, DB_VECTOR);
4138                         return 1;
4139                 }
4140         }
4141
4142         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4143         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4144         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4145         if (exit_qualification & TYPE_MOV_FROM_DR) {
4146                 unsigned long val;
4147                 if (!kvm_get_dr(vcpu, dr, &val))
4148                         kvm_register_write(vcpu, reg, val);
4149         } else
4150                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4151         skip_emulated_instruction(vcpu);
4152         return 1;
4153 }
4154
4155 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4156 {
4157         vmcs_writel(GUEST_DR7, val);
4158 }
4159
4160 static int handle_cpuid(struct kvm_vcpu *vcpu)
4161 {
4162         kvm_emulate_cpuid(vcpu);
4163         return 1;
4164 }
4165
4166 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4167 {
4168         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4169         u64 data;
4170
4171         if (vmx_get_msr(vcpu, ecx, &data)) {
4172                 trace_kvm_msr_read_ex(ecx);
4173                 kvm_inject_gp(vcpu, 0);
4174                 return 1;
4175         }
4176
4177         trace_kvm_msr_read(ecx, data);
4178
4179         /* FIXME: handling of bits 32:63 of rax, rdx */
4180         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4181         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4182         skip_emulated_instruction(vcpu);
4183         return 1;
4184 }
4185
4186 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4187 {
4188         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4189         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4190                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4191
4192         if (vmx_set_msr(vcpu, ecx, data) != 0) {
4193                 trace_kvm_msr_write_ex(ecx, data);
4194                 kvm_inject_gp(vcpu, 0);
4195                 return 1;
4196         }
4197
4198         trace_kvm_msr_write(ecx, data);
4199         skip_emulated_instruction(vcpu);
4200         return 1;
4201 }
4202
4203 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4204 {
4205         kvm_make_request(KVM_REQ_EVENT, vcpu);
4206         return 1;
4207 }
4208
4209 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4210 {
4211         u32 cpu_based_vm_exec_control;
4212
4213         /* clear pending irq */
4214         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4215         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4216         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4217
4218         kvm_make_request(KVM_REQ_EVENT, vcpu);
4219
4220         ++vcpu->stat.irq_window_exits;
4221
4222         /*
4223          * If the user space waits to inject interrupts, exit as soon as
4224          * possible
4225          */
4226         if (!irqchip_in_kernel(vcpu->kvm) &&
4227             vcpu->run->request_interrupt_window &&
4228             !kvm_cpu_has_interrupt(vcpu)) {
4229                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4230                 return 0;
4231         }
4232         return 1;
4233 }
4234
4235 static int handle_halt(struct kvm_vcpu *vcpu)
4236 {
4237         skip_emulated_instruction(vcpu);
4238         return kvm_emulate_halt(vcpu);
4239 }
4240
4241 static int handle_vmcall(struct kvm_vcpu *vcpu)
4242 {
4243         skip_emulated_instruction(vcpu);
4244         kvm_emulate_hypercall(vcpu);
4245         return 1;
4246 }
4247
4248 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
4249 {
4250         kvm_queue_exception(vcpu, UD_VECTOR);
4251         return 1;
4252 }
4253
4254 static int handle_invd(struct kvm_vcpu *vcpu)
4255 {
4256         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4257 }
4258
4259 static int handle_invlpg(struct kvm_vcpu *vcpu)
4260 {
4261         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4262
4263         kvm_mmu_invlpg(vcpu, exit_qualification);
4264         skip_emulated_instruction(vcpu);
4265         return 1;
4266 }
4267
4268 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4269 {
4270         skip_emulated_instruction(vcpu);
4271         kvm_emulate_wbinvd(vcpu);
4272         return 1;
4273 }
4274
4275 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4276 {
4277         u64 new_bv = kvm_read_edx_eax(vcpu);
4278         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4279
4280         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4281                 skip_emulated_instruction(vcpu);
4282         return 1;
4283 }
4284
4285 static int handle_apic_access(struct kvm_vcpu *vcpu)
4286 {
4287         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4288 }
4289
4290 static int handle_task_switch(struct kvm_vcpu *vcpu)
4291 {
4292         struct vcpu_vmx *vmx = to_vmx(vcpu);
4293         unsigned long exit_qualification;
4294         bool has_error_code = false;
4295         u32 error_code = 0;
4296         u16 tss_selector;
4297         int reason, type, idt_v;
4298
4299         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4300         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4301
4302         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4303
4304         reason = (u32)exit_qualification >> 30;
4305         if (reason == TASK_SWITCH_GATE && idt_v) {
4306                 switch (type) {
4307                 case INTR_TYPE_NMI_INTR:
4308                         vcpu->arch.nmi_injected = false;
4309                         vmx_set_nmi_mask(vcpu, true);
4310                         break;
4311                 case INTR_TYPE_EXT_INTR:
4312                 case INTR_TYPE_SOFT_INTR:
4313                         kvm_clear_interrupt_queue(vcpu);
4314                         break;
4315                 case INTR_TYPE_HARD_EXCEPTION:
4316                         if (vmx->idt_vectoring_info &
4317                             VECTORING_INFO_DELIVER_CODE_MASK) {
4318                                 has_error_code = true;
4319                                 error_code =
4320                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
4321                         }
4322                         /* fall through */
4323                 case INTR_TYPE_SOFT_EXCEPTION:
4324                         kvm_clear_exception_queue(vcpu);
4325                         break;
4326                 default:
4327                         break;
4328                 }
4329         }
4330         tss_selector = exit_qualification;
4331
4332         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4333                        type != INTR_TYPE_EXT_INTR &&
4334                        type != INTR_TYPE_NMI_INTR))
4335                 skip_emulated_instruction(vcpu);
4336
4337         if (kvm_task_switch(vcpu, tss_selector, reason,
4338                                 has_error_code, error_code) == EMULATE_FAIL) {
4339                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4340                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4341                 vcpu->run->internal.ndata = 0;
4342                 return 0;
4343         }
4344
4345         /* clear all local breakpoint enable flags */
4346         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4347
4348         /*
4349          * TODO: What about debug traps on tss switch?
4350          *       Are we supposed to inject them and update dr6?
4351          */
4352
4353         return 1;
4354 }
4355
4356 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4357 {
4358         unsigned long exit_qualification;
4359         gpa_t gpa;
4360         int gla_validity;
4361
4362         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4363
4364         if (exit_qualification & (1 << 6)) {
4365                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4366                 return -EINVAL;
4367         }
4368
4369         gla_validity = (exit_qualification >> 7) & 0x3;
4370         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4371                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4372                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4373                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4374                         vmcs_readl(GUEST_LINEAR_ADDRESS));
4375                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4376                         (long unsigned int)exit_qualification);
4377                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4378                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4379                 return 0;
4380         }
4381
4382         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4383         trace_kvm_page_fault(gpa, exit_qualification);
4384         return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
4385 }
4386
4387 static u64 ept_rsvd_mask(u64 spte, int level)
4388 {
4389         int i;
4390         u64 mask = 0;
4391
4392         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4393                 mask |= (1ULL << i);
4394
4395         if (level > 2)
4396                 /* bits 7:3 reserved */
4397                 mask |= 0xf8;
4398         else if (level == 2) {
4399                 if (spte & (1ULL << 7))
4400                         /* 2MB ref, bits 20:12 reserved */
4401                         mask |= 0x1ff000;
4402                 else
4403                         /* bits 6:3 reserved */
4404                         mask |= 0x78;
4405         }
4406
4407         return mask;
4408 }
4409
4410 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4411                                        int level)
4412 {
4413         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4414
4415         /* 010b (write-only) */
4416         WARN_ON((spte & 0x7) == 0x2);
4417
4418         /* 110b (write/execute) */
4419         WARN_ON((spte & 0x7) == 0x6);
4420
4421         /* 100b (execute-only) and value not supported by logical processor */
4422         if (!cpu_has_vmx_ept_execute_only())
4423                 WARN_ON((spte & 0x7) == 0x4);
4424
4425         /* not 000b */
4426         if ((spte & 0x7)) {
4427                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4428
4429                 if (rsvd_bits != 0) {
4430                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4431                                          __func__, rsvd_bits);
4432                         WARN_ON(1);
4433                 }
4434
4435                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4436                         u64 ept_mem_type = (spte & 0x38) >> 3;
4437
4438                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
4439                             ept_mem_type == 7) {
4440                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4441                                                 __func__, ept_mem_type);
4442                                 WARN_ON(1);
4443                         }
4444                 }
4445         }
4446 }
4447
4448 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4449 {
4450         u64 sptes[4];
4451         int nr_sptes, i;
4452         gpa_t gpa;
4453
4454         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4455
4456         printk(KERN_ERR "EPT: Misconfiguration.\n");
4457         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4458
4459         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4460
4461         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4462                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4463
4464         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4465         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4466
4467         return 0;
4468 }
4469
4470 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4471 {
4472         u32 cpu_based_vm_exec_control;
4473
4474         /* clear pending NMI */
4475         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4476         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4477         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4478         ++vcpu->stat.nmi_window_exits;
4479         kvm_make_request(KVM_REQ_EVENT, vcpu);
4480
4481         return 1;
4482 }
4483
4484 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4485 {
4486         struct vcpu_vmx *vmx = to_vmx(vcpu);
4487         enum emulation_result err = EMULATE_DONE;
4488         int ret = 1;
4489         u32 cpu_exec_ctrl;
4490         bool intr_window_requested;
4491
4492         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4493         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4494
4495         while (!guest_state_valid(vcpu)) {
4496                 if (intr_window_requested
4497                     && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4498                         return handle_interrupt_window(&vmx->vcpu);
4499
4500                 err = emulate_instruction(vcpu, 0);
4501
4502                 if (err == EMULATE_DO_MMIO) {
4503                         ret = 0;
4504                         goto out;
4505                 }
4506
4507                 if (err != EMULATE_DONE)
4508                         return 0;
4509
4510                 if (signal_pending(current))
4511                         goto out;
4512                 if (need_resched())
4513                         schedule();
4514         }
4515
4516         vmx->emulation_required = 0;
4517 out:
4518         return ret;
4519 }
4520
4521 /*
4522  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4523  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4524  */
4525 static int handle_pause(struct kvm_vcpu *vcpu)
4526 {
4527         skip_emulated_instruction(vcpu);
4528         kvm_vcpu_on_spin(vcpu);
4529
4530         return 1;
4531 }
4532
4533 static int handle_invalid_op(struct kvm_vcpu *vcpu)
4534 {
4535         kvm_queue_exception(vcpu, UD_VECTOR);
4536         return 1;
4537 }
4538
4539 /*
4540  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4541  * We could reuse a single VMCS for all the L2 guests, but we also want the
4542  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4543  * allows keeping them loaded on the processor, and in the future will allow
4544  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4545  * every entry if they never change.
4546  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4547  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4548  *
4549  * The following functions allocate and free a vmcs02 in this pool.
4550  */
4551
4552 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4553 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4554 {
4555         struct vmcs02_list *item;
4556         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4557                 if (item->vmptr == vmx->nested.current_vmptr) {
4558                         list_move(&item->list, &vmx->nested.vmcs02_pool);
4559                         return &item->vmcs02;
4560                 }
4561
4562         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4563                 /* Recycle the least recently used VMCS. */
4564                 item = list_entry(vmx->nested.vmcs02_pool.prev,
4565                         struct vmcs02_list, list);
4566                 item->vmptr = vmx->nested.current_vmptr;
4567                 list_move(&item->list, &vmx->nested.vmcs02_pool);
4568                 return &item->vmcs02;
4569         }
4570
4571         /* Create a new VMCS */
4572         item = (struct vmcs02_list *)
4573                 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4574         if (!item)
4575                 return NULL;
4576         item->vmcs02.vmcs = alloc_vmcs();
4577         if (!item->vmcs02.vmcs) {
4578                 kfree(item);
4579                 return NULL;
4580         }
4581         loaded_vmcs_init(&item->vmcs02);
4582         item->vmptr = vmx->nested.current_vmptr;
4583         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4584         vmx->nested.vmcs02_num++;
4585         return &item->vmcs02;
4586 }
4587
4588 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4589 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4590 {
4591         struct vmcs02_list *item;
4592         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4593                 if (item->vmptr == vmptr) {
4594                         free_loaded_vmcs(&item->vmcs02);
4595                         list_del(&item->list);
4596                         kfree(item);
4597                         vmx->nested.vmcs02_num--;
4598                         return;
4599                 }
4600 }
4601
4602 /*
4603  * Free all VMCSs saved for this vcpu, except the one pointed by
4604  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4605  * currently used, if running L2), and vmcs01 when running L2.
4606  */
4607 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4608 {
4609         struct vmcs02_list *item, *n;
4610         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4611                 if (vmx->loaded_vmcs != &item->vmcs02)
4612                         free_loaded_vmcs(&item->vmcs02);
4613                 list_del(&item->list);
4614                 kfree(item);
4615         }
4616         vmx->nested.vmcs02_num = 0;
4617
4618         if (vmx->loaded_vmcs != &vmx->vmcs01)
4619                 free_loaded_vmcs(&vmx->vmcs01);
4620 }
4621
4622 /*
4623  * Emulate the VMXON instruction.
4624  * Currently, we just remember that VMX is active, and do not save or even
4625  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4626  * do not currently need to store anything in that guest-allocated memory
4627  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
4628  * argument is different from the VMXON pointer (which the spec says they do).
4629  */
4630 static int handle_vmon(struct kvm_vcpu *vcpu)
4631 {
4632         struct kvm_segment cs;
4633         struct vcpu_vmx *vmx = to_vmx(vcpu);
4634
4635         /* The Intel VMX Instruction Reference lists a bunch of bits that
4636          * are prerequisite to running VMXON, most notably cr4.VMXE must be
4637          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
4638          * Otherwise, we should fail with #UD. We test these now:
4639          */
4640         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
4641             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
4642             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4643                 kvm_queue_exception(vcpu, UD_VECTOR);
4644                 return 1;
4645         }
4646
4647         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4648         if (is_long_mode(vcpu) && !cs.l) {
4649                 kvm_queue_exception(vcpu, UD_VECTOR);
4650                 return 1;
4651         }
4652
4653         if (vmx_get_cpl(vcpu)) {
4654                 kvm_inject_gp(vcpu, 0);
4655                 return 1;
4656         }
4657
4658         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
4659         vmx->nested.vmcs02_num = 0;
4660
4661         vmx->nested.vmxon = true;
4662
4663         skip_emulated_instruction(vcpu);
4664         return 1;
4665 }
4666
4667 /*
4668  * Intel's VMX Instruction Reference specifies a common set of prerequisites
4669  * for running VMX instructions (except VMXON, whose prerequisites are
4670  * slightly different). It also specifies what exception to inject otherwise.
4671  */
4672 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
4673 {
4674         struct kvm_segment cs;
4675         struct vcpu_vmx *vmx = to_vmx(vcpu);
4676
4677         if (!vmx->nested.vmxon) {
4678                 kvm_queue_exception(vcpu, UD_VECTOR);
4679                 return 0;
4680         }
4681
4682         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4683         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
4684             (is_long_mode(vcpu) && !cs.l)) {
4685                 kvm_queue_exception(vcpu, UD_VECTOR);
4686                 return 0;
4687         }
4688
4689         if (vmx_get_cpl(vcpu)) {
4690                 kvm_inject_gp(vcpu, 0);
4691                 return 0;
4692         }
4693
4694         return 1;
4695 }
4696
4697 /*
4698  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
4699  * just stops using VMX.
4700  */
4701 static void free_nested(struct vcpu_vmx *vmx)
4702 {
4703         if (!vmx->nested.vmxon)
4704                 return;
4705         vmx->nested.vmxon = false;
4706         if (vmx->nested.current_vmptr != -1ull) {
4707                 kunmap(vmx->nested.current_vmcs12_page);
4708                 nested_release_page(vmx->nested.current_vmcs12_page);
4709                 vmx->nested.current_vmptr = -1ull;
4710                 vmx->nested.current_vmcs12 = NULL;
4711         }
4712
4713         nested_free_all_saved_vmcss(vmx);
4714 }
4715
4716 /* Emulate the VMXOFF instruction */
4717 static int handle_vmoff(struct kvm_vcpu *vcpu)
4718 {
4719         if (!nested_vmx_check_permission(vcpu))
4720                 return 1;
4721         free_nested(to_vmx(vcpu));
4722         skip_emulated_instruction(vcpu);
4723         return 1;
4724 }
4725
4726 /*
4727  * Decode the memory-address operand of a vmx instruction, as recorded on an
4728  * exit caused by such an instruction (run by a guest hypervisor).
4729  * On success, returns 0. When the operand is invalid, returns 1 and throws
4730  * #UD or #GP.
4731  */
4732 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
4733                                  unsigned long exit_qualification,
4734                                  u32 vmx_instruction_info, gva_t *ret)
4735 {
4736         /*
4737          * According to Vol. 3B, "Information for VM Exits Due to Instruction
4738          * Execution", on an exit, vmx_instruction_info holds most of the
4739          * addressing components of the operand. Only the displacement part
4740          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
4741          * For how an actual address is calculated from all these components,
4742          * refer to Vol. 1, "Operand Addressing".
4743          */
4744         int  scaling = vmx_instruction_info & 3;
4745         int  addr_size = (vmx_instruction_info >> 7) & 7;
4746         bool is_reg = vmx_instruction_info & (1u << 10);
4747         int  seg_reg = (vmx_instruction_info >> 15) & 7;
4748         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
4749         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
4750         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
4751         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
4752
4753         if (is_reg) {
4754                 kvm_queue_exception(vcpu, UD_VECTOR);
4755                 return 1;
4756         }
4757
4758         /* Addr = segment_base + offset */
4759         /* offset = base + [index * scale] + displacement */
4760         *ret = vmx_get_segment_base(vcpu, seg_reg);
4761         if (base_is_valid)
4762                 *ret += kvm_register_read(vcpu, base_reg);
4763         if (index_is_valid)
4764                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
4765         *ret += exit_qualification; /* holds the displacement */
4766
4767         if (addr_size == 1) /* 32 bit */
4768                 *ret &= 0xffffffff;
4769
4770         /*
4771          * TODO: throw #GP (and return 1) in various cases that the VM*
4772          * instructions require it - e.g., offset beyond segment limit,
4773          * unusable or unreadable/unwritable segment, non-canonical 64-bit
4774          * address, and so on. Currently these are not checked.
4775          */
4776         return 0;
4777 }
4778
4779 /*
4780  * The exit handlers return 1 if the exit was handled fully and guest execution
4781  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
4782  * to be done to userspace and return 0.
4783  */
4784 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
4785         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
4786         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
4787         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
4788         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
4789         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
4790         [EXIT_REASON_CR_ACCESS]               = handle_cr,
4791         [EXIT_REASON_DR_ACCESS]               = handle_dr,
4792         [EXIT_REASON_CPUID]                   = handle_cpuid,
4793         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
4794         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
4795         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
4796         [EXIT_REASON_HLT]                     = handle_halt,
4797         [EXIT_REASON_INVD]                    = handle_invd,
4798         [EXIT_REASON_INVLPG]                  = handle_invlpg,
4799         [EXIT_REASON_VMCALL]                  = handle_vmcall,
4800         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
4801         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
4802         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
4803         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
4804         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
4805         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
4806         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
4807         [EXIT_REASON_VMOFF]                   = handle_vmoff,
4808         [EXIT_REASON_VMON]                    = handle_vmon,
4809         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
4810         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
4811         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
4812         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
4813         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
4814         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
4815         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
4816         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
4817         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
4818         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
4819         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
4820 };
4821
4822 static const int kvm_vmx_max_exit_handlers =
4823         ARRAY_SIZE(kvm_vmx_exit_handlers);
4824
4825 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4826 {
4827         *info1 = vmcs_readl(EXIT_QUALIFICATION);
4828         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
4829 }
4830
4831 /*
4832  * The guest has exited.  See if we can fix it or if we need userspace
4833  * assistance.
4834  */
4835 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
4836 {
4837         struct vcpu_vmx *vmx = to_vmx(vcpu);
4838         u32 exit_reason = vmx->exit_reason;
4839         u32 vectoring_info = vmx->idt_vectoring_info;
4840
4841         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
4842
4843         /* If guest state is invalid, start emulating */
4844         if (vmx->emulation_required && emulate_invalid_guest_state)
4845                 return handle_invalid_guest_state(vcpu);
4846
4847         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
4848                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4849                 vcpu->run->fail_entry.hardware_entry_failure_reason
4850                         = exit_reason;
4851                 return 0;
4852         }
4853
4854         if (unlikely(vmx->fail)) {
4855                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4856                 vcpu->run->fail_entry.hardware_entry_failure_reason
4857                         = vmcs_read32(VM_INSTRUCTION_ERROR);
4858                 return 0;
4859         }
4860
4861         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
4862                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
4863                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
4864                         exit_reason != EXIT_REASON_TASK_SWITCH))
4865                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
4866                        "(0x%x) and exit reason is 0x%x\n",
4867                        __func__, vectoring_info, exit_reason);
4868
4869         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
4870                 if (vmx_interrupt_allowed(vcpu)) {
4871                         vmx->soft_vnmi_blocked = 0;
4872                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4873                            vcpu->arch.nmi_pending) {
4874                         /*
4875                          * This CPU don't support us in finding the end of an
4876                          * NMI-blocked window if the guest runs with IRQs
4877                          * disabled. So we pull the trigger after 1 s of
4878                          * futile waiting, but inform the user about this.
4879                          */
4880                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
4881                                "state on VCPU %d after 1 s timeout\n",
4882                                __func__, vcpu->vcpu_id);
4883                         vmx->soft_vnmi_blocked = 0;
4884                 }
4885         }
4886
4887         if (exit_reason < kvm_vmx_max_exit_handlers
4888             && kvm_vmx_exit_handlers[exit_reason])
4889                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
4890         else {
4891                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4892                 vcpu->run->hw.hardware_exit_reason = exit_reason;
4893         }
4894         return 0;
4895 }
4896
4897 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
4898 {
4899         if (irr == -1 || tpr < irr) {
4900                 vmcs_write32(TPR_THRESHOLD, 0);
4901                 return;
4902         }
4903
4904         vmcs_write32(TPR_THRESHOLD, irr);
4905 }
4906
4907 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
4908 {
4909         u32 exit_intr_info;
4910
4911         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
4912               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
4913                 return;
4914
4915         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4916         exit_intr_info = vmx->exit_intr_info;
4917
4918         /* Handle machine checks before interrupts are enabled */
4919         if (is_machine_check(exit_intr_info))
4920                 kvm_machine_check();
4921
4922         /* We need to handle NMIs before interrupts are enabled */
4923         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
4924             (exit_intr_info & INTR_INFO_VALID_MASK)) {
4925                 kvm_before_handle_nmi(&vmx->vcpu);
4926                 asm("int $2");
4927                 kvm_after_handle_nmi(&vmx->vcpu);
4928         }
4929 }
4930
4931 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
4932 {
4933         u32 exit_intr_info;
4934         bool unblock_nmi;
4935         u8 vector;
4936         bool idtv_info_valid;
4937
4938         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
4939
4940         if (cpu_has_virtual_nmis()) {
4941                 if (vmx->nmi_known_unmasked)
4942                         return;
4943                 /*
4944                  * Can't use vmx->exit_intr_info since we're not sure what
4945                  * the exit reason is.
4946                  */
4947                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4948                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
4949                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
4950                 /*
4951                  * SDM 3: 27.7.1.2 (September 2008)
4952                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
4953                  * a guest IRET fault.
4954                  * SDM 3: 23.2.2 (September 2008)
4955                  * Bit 12 is undefined in any of the following cases:
4956                  *  If the VM exit sets the valid bit in the IDT-vectoring
4957                  *   information field.
4958                  *  If the VM exit is due to a double fault.
4959                  */
4960                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
4961                     vector != DF_VECTOR && !idtv_info_valid)
4962                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4963                                       GUEST_INTR_STATE_NMI);
4964                 else
4965                         vmx->nmi_known_unmasked =
4966                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
4967                                   & GUEST_INTR_STATE_NMI);
4968         } else if (unlikely(vmx->soft_vnmi_blocked))
4969                 vmx->vnmi_blocked_time +=
4970                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
4971 }
4972
4973 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
4974                                       u32 idt_vectoring_info,
4975                                       int instr_len_field,
4976                                       int error_code_field)
4977 {
4978         u8 vector;
4979         int type;
4980         bool idtv_info_valid;
4981
4982         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
4983
4984         vmx->vcpu.arch.nmi_injected = false;
4985         kvm_clear_exception_queue(&vmx->vcpu);
4986         kvm_clear_interrupt_queue(&vmx->vcpu);
4987
4988         if (!idtv_info_valid)
4989                 return;
4990
4991         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
4992
4993         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
4994         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
4995
4996         switch (type) {
4997         case INTR_TYPE_NMI_INTR:
4998                 vmx->vcpu.arch.nmi_injected = true;
4999                 /*
5000                  * SDM 3: 27.7.1.2 (September 2008)
5001                  * Clear bit "block by NMI" before VM entry if a NMI
5002                  * delivery faulted.
5003                  */
5004                 vmx_set_nmi_mask(&vmx->vcpu, false);
5005                 break;
5006         case INTR_TYPE_SOFT_EXCEPTION:
5007                 vmx->vcpu.arch.event_exit_inst_len =
5008                         vmcs_read32(instr_len_field);
5009                 /* fall through */
5010         case INTR_TYPE_HARD_EXCEPTION:
5011                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
5012                         u32 err = vmcs_read32(error_code_field);
5013                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
5014                 } else
5015                         kvm_queue_exception(&vmx->vcpu, vector);
5016                 break;
5017         case INTR_TYPE_SOFT_INTR:
5018                 vmx->vcpu.arch.event_exit_inst_len =
5019                         vmcs_read32(instr_len_field);
5020                 /* fall through */
5021         case INTR_TYPE_EXT_INTR:
5022                 kvm_queue_interrupt(&vmx->vcpu, vector,
5023                         type == INTR_TYPE_SOFT_INTR);
5024                 break;
5025         default:
5026                 break;
5027         }
5028 }
5029
5030 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
5031 {
5032         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
5033                                   VM_EXIT_INSTRUCTION_LEN,
5034                                   IDT_VECTORING_ERROR_CODE);
5035 }
5036
5037 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
5038 {
5039         __vmx_complete_interrupts(to_vmx(vcpu),
5040                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5041                                   VM_ENTRY_INSTRUCTION_LEN,
5042                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
5043
5044         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
5045 }
5046
5047 #ifdef CONFIG_X86_64
5048 #define R "r"
5049 #define Q "q"
5050 #else
5051 #define R "e"
5052 #define Q "l"
5053 #endif
5054
5055 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
5056 {
5057         struct vcpu_vmx *vmx = to_vmx(vcpu);
5058
5059         /* Record the guest's net vcpu time for enforced NMI injections. */
5060         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
5061                 vmx->entry_time = ktime_get();
5062
5063         /* Don't enter VMX if guest state is invalid, let the exit handler
5064            start emulation until we arrive back to a valid state */
5065         if (vmx->emulation_required && emulate_invalid_guest_state)
5066                 return;
5067
5068         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
5069                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
5070         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
5071                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
5072
5073         /* When single-stepping over STI and MOV SS, we must clear the
5074          * corresponding interruptibility bits in the guest state. Otherwise
5075          * vmentry fails as it then expects bit 14 (BS) in pending debug
5076          * exceptions being set, but that's not correct for the guest debugging
5077          * case. */
5078         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5079                 vmx_set_interrupt_shadow(vcpu, 0);
5080
5081         vmx->__launched = vmx->loaded_vmcs->launched;
5082         asm(
5083                 /* Store host registers */
5084                 "push %%"R"dx; push %%"R"bp;"
5085                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
5086                 "push %%"R"cx \n\t"
5087                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
5088                 "je 1f \n\t"
5089                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
5090                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
5091                 "1: \n\t"
5092                 /* Reload cr2 if changed */
5093                 "mov %c[cr2](%0), %%"R"ax \n\t"
5094                 "mov %%cr2, %%"R"dx \n\t"
5095                 "cmp %%"R"ax, %%"R"dx \n\t"
5096                 "je 2f \n\t"
5097                 "mov %%"R"ax, %%cr2 \n\t"
5098                 "2: \n\t"
5099                 /* Check if vmlaunch of vmresume is needed */
5100                 "cmpl $0, %c[launched](%0) \n\t"
5101                 /* Load guest registers.  Don't clobber flags. */
5102                 "mov %c[rax](%0), %%"R"ax \n\t"
5103                 "mov %c[rbx](%0), %%"R"bx \n\t"
5104                 "mov %c[rdx](%0), %%"R"dx \n\t"
5105                 "mov %c[rsi](%0), %%"R"si \n\t"
5106                 "mov %c[rdi](%0), %%"R"di \n\t"
5107                 "mov %c[rbp](%0), %%"R"bp \n\t"
5108 #ifdef CONFIG_X86_64
5109                 "mov %c[r8](%0),  %%r8  \n\t"
5110                 "mov %c[r9](%0),  %%r9  \n\t"
5111                 "mov %c[r10](%0), %%r10 \n\t"
5112                 "mov %c[r11](%0), %%r11 \n\t"
5113                 "mov %c[r12](%0), %%r12 \n\t"
5114                 "mov %c[r13](%0), %%r13 \n\t"
5115                 "mov %c[r14](%0), %%r14 \n\t"
5116                 "mov %c[r15](%0), %%r15 \n\t"
5117 #endif
5118                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
5119
5120                 /* Enter guest mode */
5121                 "jne .Llaunched \n\t"
5122                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
5123                 "jmp .Lkvm_vmx_return \n\t"
5124                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
5125                 ".Lkvm_vmx_return: "
5126                 /* Save guest registers, load host registers, keep flags */
5127                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
5128                 "pop %0 \n\t"
5129                 "mov %%"R"ax, %c[rax](%0) \n\t"
5130                 "mov %%"R"bx, %c[rbx](%0) \n\t"
5131                 "pop"Q" %c[rcx](%0) \n\t"
5132                 "mov %%"R"dx, %c[rdx](%0) \n\t"
5133                 "mov %%"R"si, %c[rsi](%0) \n\t"
5134                 "mov %%"R"di, %c[rdi](%0) \n\t"
5135                 "mov %%"R"bp, %c[rbp](%0) \n\t"
5136 #ifdef CONFIG_X86_64
5137                 "mov %%r8,  %c[r8](%0) \n\t"
5138                 "mov %%r9,  %c[r9](%0) \n\t"
5139                 "mov %%r10, %c[r10](%0) \n\t"
5140                 "mov %%r11, %c[r11](%0) \n\t"
5141                 "mov %%r12, %c[r12](%0) \n\t"
5142                 "mov %%r13, %c[r13](%0) \n\t"
5143                 "mov %%r14, %c[r14](%0) \n\t"
5144                 "mov %%r15, %c[r15](%0) \n\t"
5145 #endif
5146                 "mov %%cr2, %%"R"ax   \n\t"
5147                 "mov %%"R"ax, %c[cr2](%0) \n\t"
5148
5149                 "pop  %%"R"bp; pop  %%"R"dx \n\t"
5150                 "setbe %c[fail](%0) \n\t"
5151               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
5152                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
5153                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
5154                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
5155                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
5156                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
5157                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
5158                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
5159                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
5160                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
5161                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
5162 #ifdef CONFIG_X86_64
5163                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
5164                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
5165                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
5166                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
5167                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
5168                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
5169                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
5170                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
5171 #endif
5172                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
5173                 [wordsize]"i"(sizeof(ulong))
5174               : "cc", "memory"
5175                 , R"ax", R"bx", R"di", R"si"
5176 #ifdef CONFIG_X86_64
5177                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5178 #endif
5179               );
5180
5181         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
5182                                   | (1 << VCPU_EXREG_RFLAGS)
5183                                   | (1 << VCPU_EXREG_CPL)
5184                                   | (1 << VCPU_EXREG_PDPTR)
5185                                   | (1 << VCPU_EXREG_SEGMENTS)
5186                                   | (1 << VCPU_EXREG_CR3));
5187         vcpu->arch.regs_dirty = 0;
5188
5189         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
5190
5191         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
5192         vmx->loaded_vmcs->launched = 1;
5193
5194         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
5195
5196         vmx_complete_atomic_exit(vmx);
5197         vmx_recover_nmi_blocking(vmx);
5198         vmx_complete_interrupts(vmx);
5199 }
5200
5201 #undef R
5202 #undef Q
5203
5204 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
5205 {
5206         struct vcpu_vmx *vmx = to_vmx(vcpu);
5207
5208         free_vpid(vmx);
5209         free_nested(vmx);
5210         free_loaded_vmcs(vmx->loaded_vmcs);
5211         kfree(vmx->guest_msrs);
5212         kvm_vcpu_uninit(vcpu);
5213         kmem_cache_free(kvm_vcpu_cache, vmx);
5214 }
5215
5216 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
5217 {
5218         int err;
5219         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
5220         int cpu;
5221
5222         if (!vmx)
5223                 return ERR_PTR(-ENOMEM);
5224
5225         allocate_vpid(vmx);
5226
5227         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
5228         if (err)
5229                 goto free_vcpu;
5230
5231         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
5232         err = -ENOMEM;
5233         if (!vmx->guest_msrs) {
5234                 goto uninit_vcpu;
5235         }
5236
5237         vmx->loaded_vmcs = &vmx->vmcs01;
5238         vmx->loaded_vmcs->vmcs = alloc_vmcs();
5239         if (!vmx->loaded_vmcs->vmcs)
5240                 goto free_msrs;
5241         if (!vmm_exclusive)
5242                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
5243         loaded_vmcs_init(vmx->loaded_vmcs);
5244         if (!vmm_exclusive)
5245                 kvm_cpu_vmxoff();
5246
5247         cpu = get_cpu();
5248         vmx_vcpu_load(&vmx->vcpu, cpu);
5249         vmx->vcpu.cpu = cpu;
5250         err = vmx_vcpu_setup(vmx);
5251         vmx_vcpu_put(&vmx->vcpu);
5252         put_cpu();
5253         if (err)
5254                 goto free_vmcs;
5255         if (vm_need_virtualize_apic_accesses(kvm))
5256                 err = alloc_apic_access_page(kvm);
5257                 if (err)
5258                         goto free_vmcs;
5259
5260         if (enable_ept) {
5261                 if (!kvm->arch.ept_identity_map_addr)
5262                         kvm->arch.ept_identity_map_addr =
5263                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
5264                 err = -ENOMEM;
5265                 if (alloc_identity_pagetable(kvm) != 0)
5266                         goto free_vmcs;
5267                 if (!init_rmode_identity_map(kvm))
5268                         goto free_vmcs;
5269         }
5270
5271         vmx->nested.current_vmptr = -1ull;
5272         vmx->nested.current_vmcs12 = NULL;
5273
5274         return &vmx->vcpu;
5275
5276 free_vmcs:
5277         free_vmcs(vmx->loaded_vmcs->vmcs);
5278 free_msrs:
5279         kfree(vmx->guest_msrs);
5280 uninit_vcpu:
5281         kvm_vcpu_uninit(&vmx->vcpu);
5282 free_vcpu:
5283         free_vpid(vmx);
5284         kmem_cache_free(kvm_vcpu_cache, vmx);
5285         return ERR_PTR(err);
5286 }
5287
5288 static void __init vmx_check_processor_compat(void *rtn)
5289 {
5290         struct vmcs_config vmcs_conf;
5291
5292         *(int *)rtn = 0;
5293         if (setup_vmcs_config(&vmcs_conf) < 0)
5294                 *(int *)rtn = -EIO;
5295         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
5296                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
5297                                 smp_processor_id());
5298                 *(int *)rtn = -EIO;
5299         }
5300 }
5301
5302 static int get_ept_level(void)
5303 {
5304         return VMX_EPT_DEFAULT_GAW + 1;
5305 }
5306
5307 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5308 {
5309         u64 ret;
5310
5311         /* For VT-d and EPT combination
5312          * 1. MMIO: always map as UC
5313          * 2. EPT with VT-d:
5314          *   a. VT-d without snooping control feature: can't guarantee the
5315          *      result, try to trust guest.
5316          *   b. VT-d with snooping control feature: snooping control feature of
5317          *      VT-d engine can guarantee the cache correctness. Just set it
5318          *      to WB to keep consistent with host. So the same as item 3.
5319          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
5320          *    consistent with host MTRR
5321          */
5322         if (is_mmio)
5323                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
5324         else if (vcpu->kvm->arch.iommu_domain &&
5325                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
5326                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
5327                       VMX_EPT_MT_EPTE_SHIFT;
5328         else
5329                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
5330                         | VMX_EPT_IPAT_BIT;
5331
5332         return ret;
5333 }
5334
5335 #define _ER(x) { EXIT_REASON_##x, #x }
5336
5337 static const struct trace_print_flags vmx_exit_reasons_str[] = {
5338         _ER(EXCEPTION_NMI),
5339         _ER(EXTERNAL_INTERRUPT),
5340         _ER(TRIPLE_FAULT),
5341         _ER(PENDING_INTERRUPT),
5342         _ER(NMI_WINDOW),
5343         _ER(TASK_SWITCH),
5344         _ER(CPUID),
5345         _ER(HLT),
5346         _ER(INVLPG),
5347         _ER(RDPMC),
5348         _ER(RDTSC),
5349         _ER(VMCALL),
5350         _ER(VMCLEAR),
5351         _ER(VMLAUNCH),
5352         _ER(VMPTRLD),
5353         _ER(VMPTRST),
5354         _ER(VMREAD),
5355         _ER(VMRESUME),
5356         _ER(VMWRITE),
5357         _ER(VMOFF),
5358         _ER(VMON),
5359         _ER(CR_ACCESS),
5360         _ER(DR_ACCESS),
5361         _ER(IO_INSTRUCTION),
5362         _ER(MSR_READ),
5363         _ER(MSR_WRITE),
5364         _ER(MWAIT_INSTRUCTION),
5365         _ER(MONITOR_INSTRUCTION),
5366         _ER(PAUSE_INSTRUCTION),
5367         _ER(MCE_DURING_VMENTRY),
5368         _ER(TPR_BELOW_THRESHOLD),
5369         _ER(APIC_ACCESS),
5370         _ER(EPT_VIOLATION),
5371         _ER(EPT_MISCONFIG),
5372         _ER(WBINVD),
5373         { -1, NULL }
5374 };
5375
5376 #undef _ER
5377
5378 static int vmx_get_lpage_level(void)
5379 {
5380         if (enable_ept && !cpu_has_vmx_ept_1g_page())
5381                 return PT_DIRECTORY_LEVEL;
5382         else
5383                 /* For shadow and EPT supported 1GB page */
5384                 return PT_PDPE_LEVEL;
5385 }
5386
5387 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
5388 {
5389         struct kvm_cpuid_entry2 *best;
5390         struct vcpu_vmx *vmx = to_vmx(vcpu);
5391         u32 exec_control;
5392
5393         vmx->rdtscp_enabled = false;
5394         if (vmx_rdtscp_supported()) {
5395                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5396                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
5397                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
5398                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
5399                                 vmx->rdtscp_enabled = true;
5400                         else {
5401                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
5402                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5403                                                 exec_control);
5404                         }
5405                 }
5406         }
5407 }
5408
5409 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5410 {
5411 }
5412
5413 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
5414                                struct x86_instruction_info *info,
5415                                enum x86_intercept_stage stage)
5416 {
5417         return X86EMUL_CONTINUE;
5418 }
5419
5420 static struct kvm_x86_ops vmx_x86_ops = {
5421         .cpu_has_kvm_support = cpu_has_kvm_support,
5422         .disabled_by_bios = vmx_disabled_by_bios,
5423         .hardware_setup = hardware_setup,
5424         .hardware_unsetup = hardware_unsetup,
5425         .check_processor_compatibility = vmx_check_processor_compat,
5426         .hardware_enable = hardware_enable,
5427         .hardware_disable = hardware_disable,
5428         .cpu_has_accelerated_tpr = report_flexpriority,
5429
5430         .vcpu_create = vmx_create_vcpu,
5431         .vcpu_free = vmx_free_vcpu,
5432         .vcpu_reset = vmx_vcpu_reset,
5433
5434         .prepare_guest_switch = vmx_save_host_state,
5435         .vcpu_load = vmx_vcpu_load,
5436         .vcpu_put = vmx_vcpu_put,
5437
5438         .set_guest_debug = set_guest_debug,
5439         .get_msr = vmx_get_msr,
5440         .set_msr = vmx_set_msr,
5441         .get_segment_base = vmx_get_segment_base,
5442         .get_segment = vmx_get_segment,
5443         .set_segment = vmx_set_segment,
5444         .get_cpl = vmx_get_cpl,
5445         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
5446         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
5447         .decache_cr3 = vmx_decache_cr3,
5448         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
5449         .set_cr0 = vmx_set_cr0,
5450         .set_cr3 = vmx_set_cr3,
5451         .set_cr4 = vmx_set_cr4,
5452         .set_efer = vmx_set_efer,
5453         .get_idt = vmx_get_idt,
5454         .set_idt = vmx_set_idt,
5455         .get_gdt = vmx_get_gdt,
5456         .set_gdt = vmx_set_gdt,
5457         .set_dr7 = vmx_set_dr7,
5458         .cache_reg = vmx_cache_reg,
5459         .get_rflags = vmx_get_rflags,
5460         .set_rflags = vmx_set_rflags,
5461         .fpu_activate = vmx_fpu_activate,
5462         .fpu_deactivate = vmx_fpu_deactivate,
5463
5464         .tlb_flush = vmx_flush_tlb,
5465
5466         .run = vmx_vcpu_run,
5467         .handle_exit = vmx_handle_exit,
5468         .skip_emulated_instruction = skip_emulated_instruction,
5469         .set_interrupt_shadow = vmx_set_interrupt_shadow,
5470         .get_interrupt_shadow = vmx_get_interrupt_shadow,
5471         .patch_hypercall = vmx_patch_hypercall,
5472         .set_irq = vmx_inject_irq,
5473         .set_nmi = vmx_inject_nmi,
5474         .queue_exception = vmx_queue_exception,
5475         .cancel_injection = vmx_cancel_injection,
5476         .interrupt_allowed = vmx_interrupt_allowed,
5477         .nmi_allowed = vmx_nmi_allowed,
5478         .get_nmi_mask = vmx_get_nmi_mask,
5479         .set_nmi_mask = vmx_set_nmi_mask,
5480         .enable_nmi_window = enable_nmi_window,
5481         .enable_irq_window = enable_irq_window,
5482         .update_cr8_intercept = update_cr8_intercept,
5483
5484         .set_tss_addr = vmx_set_tss_addr,
5485         .get_tdp_level = get_ept_level,
5486         .get_mt_mask = vmx_get_mt_mask,
5487
5488         .get_exit_info = vmx_get_exit_info,
5489         .exit_reasons_str = vmx_exit_reasons_str,
5490
5491         .get_lpage_level = vmx_get_lpage_level,
5492
5493         .cpuid_update = vmx_cpuid_update,
5494
5495         .rdtscp_supported = vmx_rdtscp_supported,
5496
5497         .set_supported_cpuid = vmx_set_supported_cpuid,
5498
5499         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
5500
5501         .set_tsc_khz = vmx_set_tsc_khz,
5502         .write_tsc_offset = vmx_write_tsc_offset,
5503         .adjust_tsc_offset = vmx_adjust_tsc_offset,
5504         .compute_tsc_offset = vmx_compute_tsc_offset,
5505
5506         .set_tdp_cr3 = vmx_set_cr3,
5507
5508         .check_intercept = vmx_check_intercept,
5509 };
5510
5511 static int __init vmx_init(void)
5512 {
5513         int r, i;
5514
5515         rdmsrl_safe(MSR_EFER, &host_efer);
5516
5517         for (i = 0; i < NR_VMX_MSR; ++i)
5518                 kvm_define_shared_msr(i, vmx_msr_index[i]);
5519
5520         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
5521         if (!vmx_io_bitmap_a)
5522                 return -ENOMEM;
5523
5524         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
5525         if (!vmx_io_bitmap_b) {
5526                 r = -ENOMEM;
5527                 goto out;
5528         }
5529
5530         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
5531         if (!vmx_msr_bitmap_legacy) {
5532                 r = -ENOMEM;
5533                 goto out1;
5534         }
5535
5536         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
5537         if (!vmx_msr_bitmap_longmode) {
5538                 r = -ENOMEM;
5539                 goto out2;
5540         }
5541
5542         /*
5543          * Allow direct access to the PC debug port (it is often used for I/O
5544          * delays, but the vmexits simply slow things down).
5545          */
5546         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
5547         clear_bit(0x80, vmx_io_bitmap_a);
5548
5549         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
5550
5551         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
5552         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
5553
5554         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
5555
5556         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
5557                      __alignof__(struct vcpu_vmx), THIS_MODULE);
5558         if (r)
5559                 goto out3;
5560
5561         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
5562         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
5563         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
5564         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
5565         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
5566         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
5567
5568         if (enable_ept) {
5569                 bypass_guest_pf = 0;
5570                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
5571                                 VMX_EPT_EXECUTABLE_MASK);
5572                 kvm_enable_tdp();
5573         } else
5574                 kvm_disable_tdp();
5575
5576         if (bypass_guest_pf)
5577                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
5578
5579         return 0;
5580
5581 out3:
5582         free_page((unsigned long)vmx_msr_bitmap_longmode);
5583 out2:
5584         free_page((unsigned long)vmx_msr_bitmap_legacy);
5585 out1:
5586         free_page((unsigned long)vmx_io_bitmap_b);
5587 out:
5588         free_page((unsigned long)vmx_io_bitmap_a);
5589         return r;
5590 }
5591
5592 static void __exit vmx_exit(void)
5593 {
5594         free_page((unsigned long)vmx_msr_bitmap_legacy);
5595         free_page((unsigned long)vmx_msr_bitmap_longmode);
5596         free_page((unsigned long)vmx_io_bitmap_b);
5597         free_page((unsigned long)vmx_io_bitmap_a);
5598
5599         kvm_exit();
5600 }
5601
5602 module_init(vmx_init)
5603 module_exit(vmx_exit)