arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/kvm_host.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31 #include <linux/tboot.h>
  32 #include "kvm_cache_regs.h"
  33 #include "x86.h"
  34
  35 #include <asm/io.h>
  36 #include <asm/desc.h>
  37 #include <asm/vmx.h>
  38 #include <asm/virtext.h>
  39 #include <asm/mce.h>
  40 #include <asm/i387.h>
  41 #include <asm/xcr.h>
  42
  43 #include "trace.h"
  44
  45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  46
  47 MODULE_AUTHOR("Qumranet");
  48 MODULE_LICENSE("GPL");
  49
  50 static int __read_mostly bypass_guest_pf = 1;
  51 module_param(bypass_guest_pf, bool, S_IRUGO);
  52
  53 static int __read_mostly enable_vpid = 1;
  54 module_param_named(vpid, enable_vpid, bool, 0444);
  55
  56 static int __read_mostly flexpriority_enabled = 1;
  57 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  58
  59 static int __read_mostly enable_ept = 1;
  60 module_param_named(ept, enable_ept, bool, S_IRUGO);
  61
  62 static int __read_mostly enable_unrestricted_guest = 1;
  63 module_param_named(unrestricted_guest,
  64                         enable_unrestricted_guest, bool, S_IRUGO);
  65
  66 static int __read_mostly emulate_invalid_guest_state = 0;
  67 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  68
  69 static int __read_mostly vmm_exclusive = 1;
  70 module_param(vmm_exclusive, bool, S_IRUGO);
  71
  72 static int __read_mostly yield_on_hlt = 1;
  73 module_param(yield_on_hlt, bool, S_IRUGO);
  74
  75 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  76         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  77 #define KVM_GUEST_CR0_MASK                                              \
  78         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  79 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  80         (X86_CR0_WP | X86_CR0_NE)
  81 #define KVM_VM_CR0_ALWAYS_ON                                            \
  82         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  83 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  84         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  85          | X86_CR4_OSXMMEXCPT)
  86
  87 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  88 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  89
  90 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
  91
  92 /*
  93  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
  94  * ple_gap:    upper bound on the amount of time between two successive
  95  *             executions of PAUSE in a loop. Also indicate if ple enabled.
  96  *             According to test, this time is usually small than 41 cycles.
  97  * ple_window: upper bound on the amount of time a guest is allowed to execute
  98  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
  99  *             less than 2^12 cycles
 100  * Time is measured based on a counter that runs at the same rate as the TSC,
 101  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 102  */
 103 #define KVM_VMX_DEFAULT_PLE_GAP    41
 104 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 105 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 106 module_param(ple_gap, int, S_IRUGO);
 107
 108 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 109 module_param(ple_window, int, S_IRUGO);
 110
 111 #define NR_AUTOLOAD_MSRS 1
 112
 113 struct vmcs {
 114         u32 revision_id;
 115         u32 abort;
 116         char data[0];
 117 };
 118
 119 struct shared_msr_entry {
 120         unsigned index;
 121         u64 data;
 122         u64 mask;
 123 };
 124
 125 struct vcpu_vmx {
 126         struct kvm_vcpu       vcpu;
 127         struct list_head      local_vcpus_link;
 128         unsigned long         host_rsp;
 129         int                   launched;
 130         u8                    fail;
 131         u32                   exit_intr_info;
 132         u32                   idt_vectoring_info;
 133         struct shared_msr_entry *guest_msrs;
 134         int                   nmsrs;
 135         int                   save_nmsrs;
 136 #ifdef CONFIG_X86_64
 137         u64                   msr_host_kernel_gs_base;
 138         u64                   msr_guest_kernel_gs_base;
 139 #endif
 140         struct vmcs          *vmcs;
 141         struct msr_autoload {
 142                 unsigned nr;
 143                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 144                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 145         } msr_autoload;
 146         struct {
 147                 int           loaded;
 148                 u16           fs_sel, gs_sel, ldt_sel;
 149                 int           gs_ldt_reload_needed;
 150                 int           fs_reload_needed;
 151         } host_state;
 152         struct {
 153                 int vm86_active;
 154                 ulong save_rflags;
 155                 struct kvm_save_segment {
 156                         u16 selector;
 157                         unsigned long base;
 158                         u32 limit;
 159                         u32 ar;
 160                 } tr, es, ds, fs, gs;
 161         } rmode;
 162         int vpid;
 163         bool emulation_required;
 164
 165         /* Support for vnmi-less CPUs */
 166         int soft_vnmi_blocked;
 167         ktime_t entry_time;
 168         s64 vnmi_blocked_time;
 169         u32 exit_reason;
 170
 171         bool rdtscp_enabled;
 172 };
 173
 174 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 175 {
 176         return container_of(vcpu, struct vcpu_vmx, vcpu);
 177 }
 178
 179 static int init_rmode(struct kvm *kvm);
 180 static u64 construct_eptp(unsigned long root_hpa);
 181 static void kvm_cpu_vmxon(u64 addr);
 182 static void kvm_cpu_vmxoff(void);
 183
 184 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 185 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 186 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 187 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 188
 189 static unsigned long *vmx_io_bitmap_a;
 190 static unsigned long *vmx_io_bitmap_b;
 191 static unsigned long *vmx_msr_bitmap_legacy;
 192 static unsigned long *vmx_msr_bitmap_longmode;
 193
 194 static bool cpu_has_load_ia32_efer;
 195
 196 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 197 static DEFINE_SPINLOCK(vmx_vpid_lock);
 198
 199 static struct vmcs_config {
 200         int size;
 201         int order;
 202         u32 revision_id;
 203         u32 pin_based_exec_ctrl;
 204         u32 cpu_based_exec_ctrl;
 205         u32 cpu_based_2nd_exec_ctrl;
 206         u32 vmexit_ctrl;
 207         u32 vmentry_ctrl;
 208 } vmcs_config;
 209
 210 static struct vmx_capability {
 211         u32 ept;
 212         u32 vpid;
 213 } vmx_capability;
 214
 215 #define VMX_SEGMENT_FIELD(seg)                                  \
 216         [VCPU_SREG_##seg] = {                                   \
 217                 .selector = GUEST_##seg##_SELECTOR,             \
 218                 .base = GUEST_##seg##_BASE,                     \
 219                 .limit = GUEST_##seg##_LIMIT,                   \
 220                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 221         }
 222
 223 static struct kvm_vmx_segment_field {
 224         unsigned selector;
 225         unsigned base;
 226         unsigned limit;
 227         unsigned ar_bytes;
 228 } kvm_vmx_segment_fields[] = {
 229         VMX_SEGMENT_FIELD(CS),
 230         VMX_SEGMENT_FIELD(DS),
 231         VMX_SEGMENT_FIELD(ES),
 232         VMX_SEGMENT_FIELD(FS),
 233         VMX_SEGMENT_FIELD(GS),
 234         VMX_SEGMENT_FIELD(SS),
 235         VMX_SEGMENT_FIELD(TR),
 236         VMX_SEGMENT_FIELD(LDTR),
 237 };
 238
 239 static u64 host_efer;
 240
 241 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 242
 243 /*
 244  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 245  * away by decrementing the array size.
 246  */
 247 static const u32 vmx_msr_index[] = {
 248 #ifdef CONFIG_X86_64
 249         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 250 #endif
 251         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 252 };
 253 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 254
 255 static inline bool is_page_fault(u32 intr_info)
 256 {
 257         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 258                              INTR_INFO_VALID_MASK)) ==
 259                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 260 }
 261
 262 static inline bool is_no_device(u32 intr_info)
 263 {
 264         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 265                              INTR_INFO_VALID_MASK)) ==
 266                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 267 }
 268
 269 static inline bool is_invalid_opcode(u32 intr_info)
 270 {
 271         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 272                              INTR_INFO_VALID_MASK)) ==
 273                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 274 }
 275
 276 static inline bool is_external_interrupt(u32 intr_info)
 277 {
 278         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 279                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 280 }
 281
 282 static inline bool is_machine_check(u32 intr_info)
 283 {
 284         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 285                              INTR_INFO_VALID_MASK)) ==
 286                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 287 }
 288
 289 static inline bool cpu_has_vmx_msr_bitmap(void)
 290 {
 291         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 292 }
 293
 294 static inline bool cpu_has_vmx_tpr_shadow(void)
 295 {
 296         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 297 }
 298
 299 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 300 {
 301         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 302 }
 303
 304 static inline bool cpu_has_secondary_exec_ctrls(void)
 305 {
 306         return vmcs_config.cpu_based_exec_ctrl &
 307                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 308 }
 309
 310 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 311 {
 312         return vmcs_config.cpu_based_2nd_exec_ctrl &
 313                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 314 }
 315
 316 static inline bool cpu_has_vmx_flexpriority(void)
 317 {
 318         return cpu_has_vmx_tpr_shadow() &&
 319                 cpu_has_vmx_virtualize_apic_accesses();
 320 }
 321
 322 static inline bool cpu_has_vmx_ept_execute_only(void)
 323 {
 324         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 325 }
 326
 327 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 328 {
 329         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 330 }
 331
 332 static inline bool cpu_has_vmx_eptp_writeback(void)
 333 {
 334         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 335 }
 336
 337 static inline bool cpu_has_vmx_ept_2m_page(void)
 338 {
 339         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 340 }
 341
 342 static inline bool cpu_has_vmx_ept_1g_page(void)
 343 {
 344         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 345 }
 346
 347 static inline bool cpu_has_vmx_ept_4levels(void)
 348 {
 349         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 350 }
 351
 352 static inline bool cpu_has_vmx_invept_individual_addr(void)
 353 {
 354         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 355 }
 356
 357 static inline bool cpu_has_vmx_invept_context(void)
 358 {
 359         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 360 }
 361
 362 static inline bool cpu_has_vmx_invept_global(void)
 363 {
 364         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 365 }
 366
 367 static inline bool cpu_has_vmx_invvpid_single(void)
 368 {
 369         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 370 }
 371
 372 static inline bool cpu_has_vmx_invvpid_global(void)
 373 {
 374         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 375 }
 376
 377 static inline bool cpu_has_vmx_ept(void)
 378 {
 379         return vmcs_config.cpu_based_2nd_exec_ctrl &
 380                 SECONDARY_EXEC_ENABLE_EPT;
 381 }
 382
 383 static inline bool cpu_has_vmx_unrestricted_guest(void)
 384 {
 385         return vmcs_config.cpu_based_2nd_exec_ctrl &
 386                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 387 }
 388
 389 static inline bool cpu_has_vmx_ple(void)
 390 {
 391         return vmcs_config.cpu_based_2nd_exec_ctrl &
 392                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 393 }
 394
 395 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 396 {
 397         return flexpriority_enabled && irqchip_in_kernel(kvm);
 398 }
 399
 400 static inline bool cpu_has_vmx_vpid(void)
 401 {
 402         return vmcs_config.cpu_based_2nd_exec_ctrl &
 403                 SECONDARY_EXEC_ENABLE_VPID;
 404 }
 405
 406 static inline bool cpu_has_vmx_rdtscp(void)
 407 {
 408         return vmcs_config.cpu_based_2nd_exec_ctrl &
 409                 SECONDARY_EXEC_RDTSCP;
 410 }
 411
 412 static inline bool cpu_has_virtual_nmis(void)
 413 {
 414         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 415 }
 416
 417 static inline bool cpu_has_vmx_wbinvd_exit(void)
 418 {
 419         return vmcs_config.cpu_based_2nd_exec_ctrl &
 420                 SECONDARY_EXEC_WBINVD_EXITING;
 421 }
 422
 423 static inline bool report_flexpriority(void)
 424 {
 425         return flexpriority_enabled;
 426 }
 427
 428 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 429 {
 430         int i;
 431
 432         for (i = 0; i < vmx->nmsrs; ++i)
 433                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 434                         return i;
 435         return -1;
 436 }
 437
 438 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 439 {
 440     struct {
 441         u64 vpid : 16;
 442         u64 rsvd : 48;
 443         u64 gva;
 444     } operand = { vpid, 0, gva };
 445
 446     asm volatile (__ex(ASM_VMX_INVVPID)
 447                   /* CF==1 or ZF==1 --> rc = -1 */
 448                   "; ja 1f ; ud2 ; 1:"
 449                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 450 }
 451
 452 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 453 {
 454         struct {
 455                 u64 eptp, gpa;
 456         } operand = {eptp, gpa};
 457
 458         asm volatile (__ex(ASM_VMX_INVEPT)
 459                         /* CF==1 or ZF==1 --> rc = -1 */
 460                         "; ja 1f ; ud2 ; 1:\n"
 461                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 462 }
 463
 464 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 465 {
 466         int i;
 467
 468         i = __find_msr_index(vmx, msr);
 469         if (i >= 0)
 470                 return &vmx->guest_msrs[i];
 471         return NULL;
 472 }
 473
 474 static void vmcs_clear(struct vmcs *vmcs)
 475 {
 476         u64 phys_addr = __pa(vmcs);
 477         u8 error;
 478
 479         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 480                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 481                       : "cc", "memory");
 482         if (error)
 483                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 484                        vmcs, phys_addr);
 485 }
 486
 487 static void vmcs_load(struct vmcs *vmcs)
 488 {
 489         u64 phys_addr = __pa(vmcs);
 490         u8 error;
 491
 492         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 493                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 494                         : "cc", "memory");
 495         if (error)
 496                 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 497                        vmcs, phys_addr);
 498 }
 499
 500 static void __vcpu_clear(void *arg)
 501 {
 502         struct vcpu_vmx *vmx = arg;
 503         int cpu = raw_smp_processor_id();
 504
 505         if (vmx->vcpu.cpu == cpu)
 506                 vmcs_clear(vmx->vmcs);
 507         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 508                 per_cpu(current_vmcs, cpu) = NULL;
 509         list_del(&vmx->local_vcpus_link);
 510         vmx->vcpu.cpu = -1;
 511         vmx->launched = 0;
 512 }
 513
 514 static void vcpu_clear(struct vcpu_vmx *vmx)
 515 {
 516         if (vmx->vcpu.cpu == -1)
 517                 return;
 518         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 519 }
 520
 521 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
 522 {
 523         if (vmx->vpid == 0)
 524                 return;
 525
 526         if (cpu_has_vmx_invvpid_single())
 527                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 528 }
 529
 530 static inline void vpid_sync_vcpu_global(void)
 531 {
 532         if (cpu_has_vmx_invvpid_global())
 533                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
 534 }
 535
 536 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
 537 {
 538         if (cpu_has_vmx_invvpid_single())
 539                 vpid_sync_vcpu_single(vmx);
 540         else
 541                 vpid_sync_vcpu_global();
 542 }
 543
 544 static inline void ept_sync_global(void)
 545 {
 546         if (cpu_has_vmx_invept_global())
 547                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 548 }
 549
 550 static inline void ept_sync_context(u64 eptp)
 551 {
 552         if (enable_ept) {
 553                 if (cpu_has_vmx_invept_context())
 554                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 555                 else
 556                         ept_sync_global();
 557         }
 558 }
 559
 560 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 561 {
 562         if (enable_ept) {
 563                 if (cpu_has_vmx_invept_individual_addr())
 564                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 565                                         eptp, gpa);
 566                 else
 567                         ept_sync_context(eptp);
 568         }
 569 }
 570
 571 static unsigned long vmcs_readl(unsigned long field)
 572 {
 573         unsigned long value = 0;
 574
 575         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 576                       : "+a"(value) : "d"(field) : "cc");
 577         return value;
 578 }
 579
 580 static u16 vmcs_read16(unsigned long field)
 581 {
 582         return vmcs_readl(field);
 583 }
 584
 585 static u32 vmcs_read32(unsigned long field)
 586 {
 587         return vmcs_readl(field);
 588 }
 589
 590 static u64 vmcs_read64(unsigned long field)
 591 {
 592 #ifdef CONFIG_X86_64
 593         return vmcs_readl(field);
 594 #else
 595         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 596 #endif
 597 }
 598
 599 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 600 {
 601         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 602                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 603         dump_stack();
 604 }
 605
 606 static void vmcs_writel(unsigned long field, unsigned long value)
 607 {
 608         u8 error;
 609
 610         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 611                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 612         if (unlikely(error))
 613                 vmwrite_error(field, value);
 614 }
 615
 616 static void vmcs_write16(unsigned long field, u16 value)
 617 {
 618         vmcs_writel(field, value);
 619 }
 620
 621 static void vmcs_write32(unsigned long field, u32 value)
 622 {
 623         vmcs_writel(field, value);
 624 }
 625
 626 static void vmcs_write64(unsigned long field, u64 value)
 627 {
 628         vmcs_writel(field, value);
 629 #ifndef CONFIG_X86_64
 630         asm volatile ("");
 631         vmcs_writel(field+1, value >> 32);
 632 #endif
 633 }
 634
 635 static void vmcs_clear_bits(unsigned long field, u32 mask)
 636 {
 637         vmcs_writel(field, vmcs_readl(field) & ~mask);
 638 }
 639
 640 static void vmcs_set_bits(unsigned long field, u32 mask)
 641 {
 642         vmcs_writel(field, vmcs_readl(field) | mask);
 643 }
 644
 645 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 646 {
 647         u32 eb;
 648
 649         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 650              (1u << NM_VECTOR) | (1u << DB_VECTOR);
 651         if ((vcpu->guest_debug &
 652              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 653             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 654                 eb |= 1u << BP_VECTOR;
 655         if (to_vmx(vcpu)->rmode.vm86_active)
 656                 eb = ~0;
 657         if (enable_ept)
 658                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 659         if (vcpu->fpu_active)
 660                 eb &= ~(1u << NM_VECTOR);
 661         vmcs_write32(EXCEPTION_BITMAP, eb);
 662 }
 663
 664 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 665 {
 666         unsigned i;
 667         struct msr_autoload *m = &vmx->msr_autoload;
 668
 669         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
 670                 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
 671                 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
 672                 return;
 673         }
 674
 675         for (i = 0; i < m->nr; ++i)
 676                 if (m->guest[i].index == msr)
 677                         break;
 678
 679         if (i == m->nr)
 680                 return;
 681         --m->nr;
 682         m->guest[i] = m->guest[m->nr];
 683         m->host[i] = m->host[m->nr];
 684         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
 685         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
 686 }
 687
 688 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 689                                   u64 guest_val, u64 host_val)
 690 {
 691         unsigned i;
 692         struct msr_autoload *m = &vmx->msr_autoload;
 693
 694         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
 695                 vmcs_write64(GUEST_IA32_EFER, guest_val);
 696                 vmcs_write64(HOST_IA32_EFER, host_val);
 697                 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
 698                 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
 699                 return;
 700         }
 701
 702         for (i = 0; i < m->nr; ++i)
 703                 if (m->guest[i].index == msr)
 704                         break;
 705
 706         if (i == m->nr) {
 707                 ++m->nr;
 708                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
 709                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
 710         }
 711
 712         m->guest[i].index = msr;
 713         m->guest[i].value = guest_val;
 714         m->host[i].index = msr;
 715         m->host[i].value = host_val;
 716 }
 717
 718 static void reload_tss(void)
 719 {
 720         /*
 721          * VT restores TR but not its size.  Useless.
 722          */
 723         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
 724         struct desc_struct *descs;
 725
 726         descs = (void *)gdt->address;
 727         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 728         load_TR_desc();
 729 }
 730
 731 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 732 {
 733         u64 guest_efer;
 734         u64 ignore_bits;
 735
 736         guest_efer = vmx->vcpu.arch.efer;
 737
 738         /*
 739          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 740          * outside long mode
 741          */
 742         ignore_bits = EFER_NX | EFER_SCE;
 743 #ifdef CONFIG_X86_64
 744         ignore_bits |= EFER_LMA | EFER_LME;
 745         /* SCE is meaningful only in long mode on Intel */
 746         if (guest_efer & EFER_LMA)
 747                 ignore_bits &= ~(u64)EFER_SCE;
 748 #endif
 749         guest_efer &= ~ignore_bits;
 750         guest_efer |= host_efer & ignore_bits;
 751         vmx->guest_msrs[efer_offset].data = guest_efer;
 752         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
 753
 754         clear_atomic_switch_msr(vmx, MSR_EFER);
 755         /* On ept, can't emulate nx, and must switch nx atomically */
 756         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
 757                 guest_efer = vmx->vcpu.arch.efer;
 758                 if (!(guest_efer & EFER_LMA))
 759                         guest_efer &= ~EFER_LME;
 760                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
 761                 return false;
 762         }
 763
 764         return true;
 765 }
 766
 767 static unsigned long segment_base(u16 selector)
 768 {
 769         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
 770         struct desc_struct *d;
 771         unsigned long table_base;
 772         unsigned long v;
 773
 774         if (!(selector & ~3))
 775                 return 0;
 776
 777         table_base = gdt->address;
 778
 779         if (selector & 4) {           /* from ldt */
 780                 u16 ldt_selector = kvm_read_ldt();
 781
 782                 if (!(ldt_selector & ~3))
 783                         return 0;
 784
 785                 table_base = segment_base(ldt_selector);
 786         }
 787         d = (struct desc_struct *)(table_base + (selector & ~7));
 788         v = get_desc_base(d);
 789 #ifdef CONFIG_X86_64
 790        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
 791                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
 792 #endif
 793         return v;
 794 }
 795
 796 static inline unsigned long kvm_read_tr_base(void)
 797 {
 798         u16 tr;
 799         asm("str %0" : "=g"(tr));
 800         return segment_base(tr);
 801 }
 802
 803 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 804 {
 805         struct vcpu_vmx *vmx = to_vmx(vcpu);
 806         int i;
 807
 808         if (vmx->host_state.loaded)
 809                 return;
 810
 811         vmx->host_state.loaded = 1;
 812         /*
 813          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 814          * allow segment selectors with cpl > 0 or ti == 1.
 815          */
 816         vmx->host_state.ldt_sel = kvm_read_ldt();
 817         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 818         savesegment(fs, vmx->host_state.fs_sel);
 819         if (!(vmx->host_state.fs_sel & 7)) {
 820                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 821                 vmx->host_state.fs_reload_needed = 0;
 822         } else {
 823                 vmcs_write16(HOST_FS_SELECTOR, 0);
 824                 vmx->host_state.fs_reload_needed = 1;
 825         }
 826         savesegment(gs, vmx->host_state.gs_sel);
 827         if (!(vmx->host_state.gs_sel & 7))
 828                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 829         else {
 830                 vmcs_write16(HOST_GS_SELECTOR, 0);
 831                 vmx->host_state.gs_ldt_reload_needed = 1;
 832         }
 833
 834 #ifdef CONFIG_X86_64
 835         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 836         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 837 #else
 838         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 839         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 840 #endif
 841
 842 #ifdef CONFIG_X86_64
 843         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 844         if (is_long_mode(&vmx->vcpu))
 845                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 846 #endif
 847         for (i = 0; i < vmx->save_nmsrs; ++i)
 848                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
 849                                    vmx->guest_msrs[i].data,
 850                                    vmx->guest_msrs[i].mask);
 851 }
 852
 853 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 854 {
 855         if (!vmx->host_state.loaded)
 856                 return;
 857
 858         ++vmx->vcpu.stat.host_state_reload;
 859         vmx->host_state.loaded = 0;
 860 #ifdef CONFIG_X86_64
 861         if (is_long_mode(&vmx->vcpu))
 862                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 863 #endif
 864         if (vmx->host_state.gs_ldt_reload_needed) {
 865                 kvm_load_ldt(vmx->host_state.ldt_sel);
 866 #ifdef CONFIG_X86_64
 867                 load_gs_index(vmx->host_state.gs_sel);
 868 #else
 869                 loadsegment(gs, vmx->host_state.gs_sel);
 870 #endif
 871         }
 872         if (vmx->host_state.fs_reload_needed)
 873                 loadsegment(fs, vmx->host_state.fs_sel);
 874         reload_tss();
 875 #ifdef CONFIG_X86_64
 876         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 877 #endif
 878         if (current_thread_info()->status & TS_USEDFPU)
 879                 clts();
 880         load_gdt(&__get_cpu_var(host_gdt));
 881 }
 882
 883 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 884 {
 885         preempt_disable();
 886         __vmx_load_host_state(vmx);
 887         preempt_enable();
 888 }
 889
 890 /*
 891  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 892  * vcpu mutex is already taken.
 893  */
 894 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 895 {
 896         struct vcpu_vmx *vmx = to_vmx(vcpu);
 897         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
 898
 899         if (!vmm_exclusive)
 900                 kvm_cpu_vmxon(phys_addr);
 901         else if (vcpu->cpu != cpu)
 902                 vcpu_clear(vmx);
 903
 904         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 905                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 906                 vmcs_load(vmx->vmcs);
 907         }
 908
 909         if (vcpu->cpu != cpu) {
 910                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
 911                 unsigned long sysenter_esp;
 912
 913                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
 914                 local_irq_disable();
 915                 list_add(&vmx->local_vcpus_link,
 916                          &per_cpu(vcpus_on_cpu, cpu));
 917                 local_irq_enable();
 918
 919                 /*
 920                  * Linux uses per-cpu TSS and GDT, so set these when switching
 921                  * processors.
 922                  */
 923                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 924                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
 925
 926                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 927                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 928         }
 929 }
 930
 931 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 932 {
 933         __vmx_load_host_state(to_vmx(vcpu));
 934         if (!vmm_exclusive) {
 935                 __vcpu_clear(to_vmx(vcpu));
 936                 kvm_cpu_vmxoff();
 937         }
 938 }
 939
 940 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 941 {
 942         ulong cr0;
 943
 944         if (vcpu->fpu_active)
 945                 return;
 946         vcpu->fpu_active = 1;
 947         cr0 = vmcs_readl(GUEST_CR0);
 948         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
 949         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
 950         vmcs_writel(GUEST_CR0, cr0);
 951         update_exception_bitmap(vcpu);
 952         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
 953         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 954 }
 955
 956 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
 957
 958 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 959 {
 960         vmx_decache_cr0_guest_bits(vcpu);
 961         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
 962         update_exception_bitmap(vcpu);
 963         vcpu->arch.cr0_guest_owned_bits = 0;
 964         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 965         vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
 966 }
 967
 968 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 969 {
 970         unsigned long rflags, save_rflags;
 971
 972         rflags = vmcs_readl(GUEST_RFLAGS);
 973         if (to_vmx(vcpu)->rmode.vm86_active) {
 974                 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
 975                 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
 976                 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
 977         }
 978         return rflags;
 979 }
 980
 981 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 982 {
 983         if (to_vmx(vcpu)->rmode.vm86_active) {
 984                 to_vmx(vcpu)->rmode.save_rflags = rflags;
 985                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 986         }
 987         vmcs_writel(GUEST_RFLAGS, rflags);
 988 }
 989
 990 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 991 {
 992         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 993         int ret = 0;
 994
 995         if (interruptibility & GUEST_INTR_STATE_STI)
 996                 ret |= KVM_X86_SHADOW_INT_STI;
 997         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
 998                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
 999
1000         return ret & mask;
1001 }
1002
1003 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1004 {
1005         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1006         u32 interruptibility = interruptibility_old;
1007
1008         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1009
1010         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1011                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1012         else if (mask & KVM_X86_SHADOW_INT_STI)
1013                 interruptibility |= GUEST_INTR_STATE_STI;
1014
1015         if ((interruptibility != interruptibility_old))
1016                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1017 }
1018
1019 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1020 {
1021         unsigned long rip;
1022
1023         rip = kvm_rip_read(vcpu);
1024         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1025         kvm_rip_write(vcpu, rip);
1026
1027         /* skipping an emulated instruction also counts */
1028         vmx_set_interrupt_shadow(vcpu, 0);
1029 }
1030
1031 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1032 {
1033         /* Ensure that we clear the HLT state in the VMCS.  We don't need to
1034          * explicitly skip the instruction because if the HLT state is set, then
1035          * the instruction is already executing and RIP has already been
1036          * advanced. */
1037         if (!yield_on_hlt &&
1038             vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1039                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1040 }
1041
1042 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1043                                 bool has_error_code, u32 error_code,
1044                                 bool reinject)
1045 {
1046         struct vcpu_vmx *vmx = to_vmx(vcpu);
1047         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1048
1049         if (has_error_code) {
1050                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1051                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1052         }
1053
1054         if (vmx->rmode.vm86_active) {
1055                 if (kvm_inject_realmode_interrupt(vcpu, nr) != EMULATE_DONE)
1056                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1057                 return;
1058         }
1059
1060         if (kvm_exception_is_soft(nr)) {
1061                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1062                              vmx->vcpu.arch.event_exit_inst_len);
1063                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1064         } else
1065                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1066
1067         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1068         vmx_clear_hlt(vcpu);
1069 }
1070
1071 static bool vmx_rdtscp_supported(void)
1072 {
1073         return cpu_has_vmx_rdtscp();
1074 }
1075
1076 /*
1077  * Swap MSR entry in host/guest MSR entry array.
1078  */
1079 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1080 {
1081         struct shared_msr_entry tmp;
1082
1083         tmp = vmx->guest_msrs[to];
1084         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1085         vmx->guest_msrs[from] = tmp;
1086 }
1087
1088 /*
1089  * Set up the vmcs to automatically save and restore system
1090  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1091  * mode, as fiddling with msrs is very expensive.
1092  */
1093 static void setup_msrs(struct vcpu_vmx *vmx)
1094 {
1095         int save_nmsrs, index;
1096         unsigned long *msr_bitmap;
1097
1098         vmx_load_host_state(vmx);
1099         save_nmsrs = 0;
1100 #ifdef CONFIG_X86_64
1101         if (is_long_mode(&vmx->vcpu)) {
1102                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1103                 if (index >= 0)
1104                         move_msr_up(vmx, index, save_nmsrs++);
1105                 index = __find_msr_index(vmx, MSR_LSTAR);
1106                 if (index >= 0)
1107                         move_msr_up(vmx, index, save_nmsrs++);
1108                 index = __find_msr_index(vmx, MSR_CSTAR);
1109                 if (index >= 0)
1110                         move_msr_up(vmx, index, save_nmsrs++);
1111                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1112                 if (index >= 0 && vmx->rdtscp_enabled)
1113                         move_msr_up(vmx, index, save_nmsrs++);
1114                 /*
1115                  * MSR_STAR is only needed on long mode guests, and only
1116                  * if efer.sce is enabled.
1117                  */
1118                 index = __find_msr_index(vmx, MSR_STAR);
1119                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1120                         move_msr_up(vmx, index, save_nmsrs++);
1121         }
1122 #endif
1123         index = __find_msr_index(vmx, MSR_EFER);
1124         if (index >= 0 && update_transition_efer(vmx, index))
1125                 move_msr_up(vmx, index, save_nmsrs++);
1126
1127         vmx->save_nmsrs = save_nmsrs;
1128
1129         if (cpu_has_vmx_msr_bitmap()) {
1130                 if (is_long_mode(&vmx->vcpu))
1131                         msr_bitmap = vmx_msr_bitmap_longmode;
1132                 else
1133                         msr_bitmap = vmx_msr_bitmap_legacy;
1134
1135                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1136         }
1137 }
1138
1139 /*
1140  * reads and returns guest's timestamp counter "register"
1141  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1142  */
1143 static u64 guest_read_tsc(void)
1144 {
1145         u64 host_tsc, tsc_offset;
1146
1147         rdtscll(host_tsc);
1148         tsc_offset = vmcs_read64(TSC_OFFSET);
1149         return host_tsc + tsc_offset;
1150 }
1151
1152 /*
1153  * writes 'offset' into guest's timestamp counter offset register
1154  */
1155 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1156 {
1157         vmcs_write64(TSC_OFFSET, offset);
1158 }
1159
1160 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1161 {
1162         u64 offset = vmcs_read64(TSC_OFFSET);
1163         vmcs_write64(TSC_OFFSET, offset + adjustment);
1164 }
1165
1166 /*
1167  * Reads an msr value (of 'msr_index') into 'pdata'.
1168  * Returns 0 on success, non-0 otherwise.
1169  * Assumes vcpu_load() was already called.
1170  */
1171 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1172 {
1173         u64 data;
1174         struct shared_msr_entry *msr;
1175
1176         if (!pdata) {
1177                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1178                 return -EINVAL;
1179         }
1180
1181         switch (msr_index) {
1182 #ifdef CONFIG_X86_64
1183         case MSR_FS_BASE:
1184                 data = vmcs_readl(GUEST_FS_BASE);
1185                 break;
1186         case MSR_GS_BASE:
1187                 data = vmcs_readl(GUEST_GS_BASE);
1188                 break;
1189         case MSR_KERNEL_GS_BASE:
1190                 vmx_load_host_state(to_vmx(vcpu));
1191                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1192                 break;
1193 #endif
1194         case MSR_EFER:
1195                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1196         case MSR_IA32_TSC:
1197                 data = guest_read_tsc();
1198                 break;
1199         case MSR_IA32_SYSENTER_CS:
1200                 data = vmcs_read32(GUEST_SYSENTER_CS);
1201                 break;
1202         case MSR_IA32_SYSENTER_EIP:
1203                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1204                 break;
1205         case MSR_IA32_SYSENTER_ESP:
1206                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1207                 break;
1208         case MSR_TSC_AUX:
1209                 if (!to_vmx(vcpu)->rdtscp_enabled)
1210                         return 1;
1211                 /* Otherwise falls through */
1212         default:
1213                 vmx_load_host_state(to_vmx(vcpu));
1214                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1215                 if (msr) {
1216                         vmx_load_host_state(to_vmx(vcpu));
1217                         data = msr->data;
1218                         break;
1219                 }
1220                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1221         }
1222
1223         *pdata = data;
1224         return 0;
1225 }
1226
1227 /*
1228  * Writes msr value into into the appropriate "register".
1229  * Returns 0 on success, non-0 otherwise.
1230  * Assumes vcpu_load() was already called.
1231  */
1232 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1233 {
1234         struct vcpu_vmx *vmx = to_vmx(vcpu);
1235         struct shared_msr_entry *msr;
1236         int ret = 0;
1237
1238         switch (msr_index) {
1239         case MSR_EFER:
1240                 vmx_load_host_state(vmx);
1241                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1242                 break;
1243 #ifdef CONFIG_X86_64
1244         case MSR_FS_BASE:
1245                 vmcs_writel(GUEST_FS_BASE, data);
1246                 break;
1247         case MSR_GS_BASE:
1248                 vmcs_writel(GUEST_GS_BASE, data);
1249                 break;
1250         case MSR_KERNEL_GS_BASE:
1251                 vmx_load_host_state(vmx);
1252                 vmx->msr_guest_kernel_gs_base = data;
1253                 break;
1254 #endif
1255         case MSR_IA32_SYSENTER_CS:
1256                 vmcs_write32(GUEST_SYSENTER_CS, data);
1257                 break;
1258         case MSR_IA32_SYSENTER_EIP:
1259                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1260                 break;
1261         case MSR_IA32_SYSENTER_ESP:
1262                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1263                 break;
1264         case MSR_IA32_TSC:
1265                 kvm_write_tsc(vcpu, data);
1266                 break;
1267         case MSR_IA32_CR_PAT:
1268                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1269                         vmcs_write64(GUEST_IA32_PAT, data);
1270                         vcpu->arch.pat = data;
1271                         break;
1272                 }
1273                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1274                 break;
1275         case MSR_TSC_AUX:
1276                 if (!vmx->rdtscp_enabled)
1277                         return 1;
1278                 /* Check reserved bit, higher 32 bits should be zero */
1279                 if ((data >> 32) != 0)
1280                         return 1;
1281                 /* Otherwise falls through */
1282         default:
1283                 msr = find_msr_entry(vmx, msr_index);
1284                 if (msr) {
1285                         vmx_load_host_state(vmx);
1286                         msr->data = data;
1287                         break;
1288                 }
1289                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1290         }
1291
1292         return ret;
1293 }
1294
1295 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1296 {
1297         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1298         switch (reg) {
1299         case VCPU_REGS_RSP:
1300                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1301                 break;
1302         case VCPU_REGS_RIP:
1303                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1304                 break;
1305         case VCPU_EXREG_PDPTR:
1306                 if (enable_ept)
1307                         ept_save_pdptrs(vcpu);
1308                 break;
1309         default:
1310                 break;
1311         }
1312 }
1313
1314 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1315 {
1316         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1317                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1318         else
1319                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1320
1321         update_exception_bitmap(vcpu);
1322 }
1323
1324 static __init int cpu_has_kvm_support(void)
1325 {
1326         return cpu_has_vmx();
1327 }
1328
1329 static __init int vmx_disabled_by_bios(void)
1330 {
1331         u64 msr;
1332
1333         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1334         if (msr & FEATURE_CONTROL_LOCKED) {
1335                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1336                         && tboot_enabled())
1337                         return 1;
1338                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1339                         && !tboot_enabled()) {
1340                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
1341                                 " activate TXT before enabling KVM\n");
1342                         return 1;
1343                 }
1344         }
1345
1346         return 0;
1347         /* locked but not enabled */
1348 }
1349
1350 static void kvm_cpu_vmxon(u64 addr)
1351 {
1352         asm volatile (ASM_VMX_VMXON_RAX
1353                         : : "a"(&addr), "m"(addr)
1354                         : "memory", "cc");
1355 }
1356
1357 static int hardware_enable(void *garbage)
1358 {
1359         int cpu = raw_smp_processor_id();
1360         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1361         u64 old, test_bits;
1362
1363         if (read_cr4() & X86_CR4_VMXE)
1364                 return -EBUSY;
1365
1366         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1367         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1368
1369         test_bits = FEATURE_CONTROL_LOCKED;
1370         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1371         if (tboot_enabled())
1372                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1373
1374         if ((old & test_bits) != test_bits) {
1375                 /* enable and lock */
1376                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1377         }
1378         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1379
1380         if (vmm_exclusive) {
1381                 kvm_cpu_vmxon(phys_addr);
1382                 ept_sync_global();
1383         }
1384
1385         store_gdt(&__get_cpu_var(host_gdt));
1386
1387         return 0;
1388 }
1389
1390 static void vmclear_local_vcpus(void)
1391 {
1392         int cpu = raw_smp_processor_id();
1393         struct vcpu_vmx *vmx, *n;
1394
1395         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1396                                  local_vcpus_link)
1397                 __vcpu_clear(vmx);
1398 }
1399
1400
1401 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1402  * tricks.
1403  */
1404 static void kvm_cpu_vmxoff(void)
1405 {
1406         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1407 }
1408
1409 static void hardware_disable(void *garbage)
1410 {
1411         if (vmm_exclusive) {
1412                 vmclear_local_vcpus();
1413                 kvm_cpu_vmxoff();
1414         }
1415         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1416 }
1417
1418 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1419                                       u32 msr, u32 *result)
1420 {
1421         u32 vmx_msr_low, vmx_msr_high;
1422         u32 ctl = ctl_min | ctl_opt;
1423
1424         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1425
1426         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1427         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1428
1429         /* Ensure minimum (required) set of control bits are supported. */
1430         if (ctl_min & ~ctl)
1431                 return -EIO;
1432
1433         *result = ctl;
1434         return 0;
1435 }
1436
1437 static __init bool allow_1_setting(u32 msr, u32 ctl)
1438 {
1439         u32 vmx_msr_low, vmx_msr_high;
1440
1441         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1442         return vmx_msr_high & ctl;
1443 }
1444
1445 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1446 {
1447         u32 vmx_msr_low, vmx_msr_high;
1448         u32 min, opt, min2, opt2;
1449         u32 _pin_based_exec_control = 0;
1450         u32 _cpu_based_exec_control = 0;
1451         u32 _cpu_based_2nd_exec_control = 0;
1452         u32 _vmexit_control = 0;
1453         u32 _vmentry_control = 0;
1454
1455         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1456         opt = PIN_BASED_VIRTUAL_NMIS;
1457         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1458                                 &_pin_based_exec_control) < 0)
1459                 return -EIO;
1460
1461         min =
1462 #ifdef CONFIG_X86_64
1463               CPU_BASED_CR8_LOAD_EXITING |
1464               CPU_BASED_CR8_STORE_EXITING |
1465 #endif
1466               CPU_BASED_CR3_LOAD_EXITING |
1467               CPU_BASED_CR3_STORE_EXITING |
1468               CPU_BASED_USE_IO_BITMAPS |
1469               CPU_BASED_MOV_DR_EXITING |
1470               CPU_BASED_USE_TSC_OFFSETING |
1471               CPU_BASED_MWAIT_EXITING |
1472               CPU_BASED_MONITOR_EXITING |
1473               CPU_BASED_INVLPG_EXITING;
1474
1475         if (yield_on_hlt)
1476                 min |= CPU_BASED_HLT_EXITING;
1477
1478         opt = CPU_BASED_TPR_SHADOW |
1479               CPU_BASED_USE_MSR_BITMAPS |
1480               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1481         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1482                                 &_cpu_based_exec_control) < 0)
1483                 return -EIO;
1484 #ifdef CONFIG_X86_64
1485         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1486                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1487                                            ~CPU_BASED_CR8_STORE_EXITING;
1488 #endif
1489         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1490                 min2 = 0;
1491                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1492                         SECONDARY_EXEC_WBINVD_EXITING |
1493                         SECONDARY_EXEC_ENABLE_VPID |
1494                         SECONDARY_EXEC_ENABLE_EPT |
1495                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
1496                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1497                         SECONDARY_EXEC_RDTSCP;
1498                 if (adjust_vmx_controls(min2, opt2,
1499                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1500                                         &_cpu_based_2nd_exec_control) < 0)
1501                         return -EIO;
1502         }
1503 #ifndef CONFIG_X86_64
1504         if (!(_cpu_based_2nd_exec_control &
1505                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1506                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1507 #endif
1508         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1509                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1510                    enabled */
1511                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1512                                              CPU_BASED_CR3_STORE_EXITING |
1513                                              CPU_BASED_INVLPG_EXITING);
1514                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1515                       vmx_capability.ept, vmx_capability.vpid);
1516         }
1517
1518         min = 0;
1519 #ifdef CONFIG_X86_64
1520         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1521 #endif
1522         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1523         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1524                                 &_vmexit_control) < 0)
1525                 return -EIO;
1526
1527         min = 0;
1528         opt = VM_ENTRY_LOAD_IA32_PAT;
1529         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1530                                 &_vmentry_control) < 0)
1531                 return -EIO;
1532
1533         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1534
1535         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1536         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1537                 return -EIO;
1538
1539 #ifdef CONFIG_X86_64
1540         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1541         if (vmx_msr_high & (1u<<16))
1542                 return -EIO;
1543 #endif
1544
1545         /* Require Write-Back (WB) memory type for VMCS accesses. */
1546         if (((vmx_msr_high >> 18) & 15) != 6)
1547                 return -EIO;
1548
1549         vmcs_conf->size = vmx_msr_high & 0x1fff;
1550         vmcs_conf->order = get_order(vmcs_config.size);
1551         vmcs_conf->revision_id = vmx_msr_low;
1552
1553         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1554         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1555         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1556         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1557         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1558
1559         cpu_has_load_ia32_efer =
1560                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
1561                                 VM_ENTRY_LOAD_IA32_EFER)
1562                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
1563                                    VM_EXIT_LOAD_IA32_EFER);
1564
1565         return 0;
1566 }
1567
1568 static struct vmcs *alloc_vmcs_cpu(int cpu)
1569 {
1570         int node = cpu_to_node(cpu);
1571         struct page *pages;
1572         struct vmcs *vmcs;
1573
1574         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1575         if (!pages)
1576                 return NULL;
1577         vmcs = page_address(pages);
1578         memset(vmcs, 0, vmcs_config.size);
1579         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1580         return vmcs;
1581 }
1582
1583 static struct vmcs *alloc_vmcs(void)
1584 {
1585         return alloc_vmcs_cpu(raw_smp_processor_id());
1586 }
1587
1588 static void free_vmcs(struct vmcs *vmcs)
1589 {
1590         free_pages((unsigned long)vmcs, vmcs_config.order);
1591 }
1592
1593 static void free_kvm_area(void)
1594 {
1595         int cpu;
1596
1597         for_each_possible_cpu(cpu) {
1598                 free_vmcs(per_cpu(vmxarea, cpu));
1599                 per_cpu(vmxarea, cpu) = NULL;
1600         }
1601 }
1602
1603 static __init int alloc_kvm_area(void)
1604 {
1605         int cpu;
1606
1607         for_each_possible_cpu(cpu) {
1608                 struct vmcs *vmcs;
1609
1610                 vmcs = alloc_vmcs_cpu(cpu);
1611                 if (!vmcs) {
1612                         free_kvm_area();
1613                         return -ENOMEM;
1614                 }
1615
1616                 per_cpu(vmxarea, cpu) = vmcs;
1617         }
1618         return 0;
1619 }
1620
1621 static __init int hardware_setup(void)
1622 {
1623         if (setup_vmcs_config(&vmcs_config) < 0)
1624                 return -EIO;
1625
1626         if (boot_cpu_has(X86_FEATURE_NX))
1627                 kvm_enable_efer_bits(EFER_NX);
1628
1629         if (!cpu_has_vmx_vpid())
1630                 enable_vpid = 0;
1631
1632         if (!cpu_has_vmx_ept() ||
1633             !cpu_has_vmx_ept_4levels()) {
1634                 enable_ept = 0;
1635                 enable_unrestricted_guest = 0;
1636         }
1637
1638         if (!cpu_has_vmx_unrestricted_guest())
1639                 enable_unrestricted_guest = 0;
1640
1641         if (!cpu_has_vmx_flexpriority())
1642                 flexpriority_enabled = 0;
1643
1644         if (!cpu_has_vmx_tpr_shadow())
1645                 kvm_x86_ops->update_cr8_intercept = NULL;
1646
1647         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1648                 kvm_disable_largepages();
1649
1650         if (!cpu_has_vmx_ple())
1651                 ple_gap = 0;
1652
1653         return alloc_kvm_area();
1654 }
1655
1656 static __exit void hardware_unsetup(void)
1657 {
1658         free_kvm_area();
1659 }
1660
1661 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1662 {
1663         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1664
1665         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1666                 vmcs_write16(sf->selector, save->selector);
1667                 vmcs_writel(sf->base, save->base);
1668                 vmcs_write32(sf->limit, save->limit);
1669                 vmcs_write32(sf->ar_bytes, save->ar);
1670         } else {
1671                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1672                         << AR_DPL_SHIFT;
1673                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1674         }
1675 }
1676
1677 static void enter_pmode(struct kvm_vcpu *vcpu)
1678 {
1679         unsigned long flags;
1680         struct vcpu_vmx *vmx = to_vmx(vcpu);
1681
1682         vmx->emulation_required = 1;
1683         vmx->rmode.vm86_active = 0;
1684
1685         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1686         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1687         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1688
1689         flags = vmcs_readl(GUEST_RFLAGS);
1690         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1691         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1692         vmcs_writel(GUEST_RFLAGS, flags);
1693
1694         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1695                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1696
1697         update_exception_bitmap(vcpu);
1698
1699         if (emulate_invalid_guest_state)
1700                 return;
1701
1702         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1703         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1704         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1705         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1706
1707         vmcs_write16(GUEST_SS_SELECTOR, 0);
1708         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1709
1710         vmcs_write16(GUEST_CS_SELECTOR,
1711                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1712         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1713 }
1714
1715 static gva_t rmode_tss_base(struct kvm *kvm)
1716 {
1717         if (!kvm->arch.tss_addr) {
1718                 struct kvm_memslots *slots;
1719                 gfn_t base_gfn;
1720
1721                 slots = kvm_memslots(kvm);
1722                 base_gfn = slots->memslots[0].base_gfn +
1723                                  kvm->memslots->memslots[0].npages - 3;
1724                 return base_gfn << PAGE_SHIFT;
1725         }
1726         return kvm->arch.tss_addr;
1727 }
1728
1729 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1730 {
1731         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1732
1733         save->selector = vmcs_read16(sf->selector);
1734         save->base = vmcs_readl(sf->base);
1735         save->limit = vmcs_read32(sf->limit);
1736         save->ar = vmcs_read32(sf->ar_bytes);
1737         vmcs_write16(sf->selector, save->base >> 4);
1738         vmcs_write32(sf->base, save->base & 0xfffff);
1739         vmcs_write32(sf->limit, 0xffff);
1740         vmcs_write32(sf->ar_bytes, 0xf3);
1741 }
1742
1743 static void enter_rmode(struct kvm_vcpu *vcpu)
1744 {
1745         unsigned long flags;
1746         struct vcpu_vmx *vmx = to_vmx(vcpu);
1747
1748         if (enable_unrestricted_guest)
1749                 return;
1750
1751         vmx->emulation_required = 1;
1752         vmx->rmode.vm86_active = 1;
1753
1754         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1755         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1756
1757         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1758         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1759
1760         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1761         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1762
1763         flags = vmcs_readl(GUEST_RFLAGS);
1764         vmx->rmode.save_rflags = flags;
1765
1766         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1767
1768         vmcs_writel(GUEST_RFLAGS, flags);
1769         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1770         update_exception_bitmap(vcpu);
1771
1772         if (emulate_invalid_guest_state)
1773                 goto continue_rmode;
1774
1775         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1776         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1777         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1778
1779         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1780         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1781         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1782                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1783         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1784
1785         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1786         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1787         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1788         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1789
1790 continue_rmode:
1791         kvm_mmu_reset_context(vcpu);
1792         init_rmode(vcpu->kvm);
1793 }
1794
1795 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1796 {
1797         struct vcpu_vmx *vmx = to_vmx(vcpu);
1798         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1799
1800         if (!msr)
1801                 return;
1802
1803         /*
1804          * Force kernel_gs_base reloading before EFER changes, as control
1805          * of this msr depends on is_long_mode().
1806          */
1807         vmx_load_host_state(to_vmx(vcpu));
1808         vcpu->arch.efer = efer;
1809         if (efer & EFER_LMA) {
1810                 vmcs_write32(VM_ENTRY_CONTROLS,
1811                              vmcs_read32(VM_ENTRY_CONTROLS) |
1812                              VM_ENTRY_IA32E_MODE);
1813                 msr->data = efer;
1814         } else {
1815                 vmcs_write32(VM_ENTRY_CONTROLS,
1816                              vmcs_read32(VM_ENTRY_CONTROLS) &
1817                              ~VM_ENTRY_IA32E_MODE);
1818
1819                 msr->data = efer & ~EFER_LME;
1820         }
1821         setup_msrs(vmx);
1822 }
1823
1824 #ifdef CONFIG_X86_64
1825
1826 static void enter_lmode(struct kvm_vcpu *vcpu)
1827 {
1828         u32 guest_tr_ar;
1829
1830         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1831         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1832                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1833                        __func__);
1834                 vmcs_write32(GUEST_TR_AR_BYTES,
1835                              (guest_tr_ar & ~AR_TYPE_MASK)
1836                              | AR_TYPE_BUSY_64_TSS);
1837         }
1838         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
1839 }
1840
1841 static void exit_lmode(struct kvm_vcpu *vcpu)
1842 {
1843         vmcs_write32(VM_ENTRY_CONTROLS,
1844                      vmcs_read32(VM_ENTRY_CONTROLS)
1845                      & ~VM_ENTRY_IA32E_MODE);
1846         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
1847 }
1848
1849 #endif
1850
1851 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1852 {
1853         vpid_sync_context(to_vmx(vcpu));
1854         if (enable_ept) {
1855                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1856                         return;
1857                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1858         }
1859 }
1860
1861 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1862 {
1863         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1864
1865         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1866         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1867 }
1868
1869 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1870 {
1871         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1872
1873         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1874         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1875 }
1876
1877 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1878 {
1879         if (!test_bit(VCPU_EXREG_PDPTR,
1880                       (unsigned long *)&vcpu->arch.regs_dirty))
1881                 return;
1882
1883         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1884                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
1885                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
1886                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
1887                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1888         }
1889 }
1890
1891 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1892 {
1893         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1894                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1895                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1896                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1897                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1898         }
1899
1900         __set_bit(VCPU_EXREG_PDPTR,
1901                   (unsigned long *)&vcpu->arch.regs_avail);
1902         __set_bit(VCPU_EXREG_PDPTR,
1903                   (unsigned long *)&vcpu->arch.regs_dirty);
1904 }
1905
1906 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1907
1908 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1909                                         unsigned long cr0,
1910                                         struct kvm_vcpu *vcpu)
1911 {
1912         if (!(cr0 & X86_CR0_PG)) {
1913                 /* From paging/starting to nonpaging */
1914                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1915                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1916                              (CPU_BASED_CR3_LOAD_EXITING |
1917                               CPU_BASED_CR3_STORE_EXITING));
1918                 vcpu->arch.cr0 = cr0;
1919                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1920         } else if (!is_paging(vcpu)) {
1921                 /* From nonpaging to paging */
1922                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1923                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1924                              ~(CPU_BASED_CR3_LOAD_EXITING |
1925                                CPU_BASED_CR3_STORE_EXITING));
1926                 vcpu->arch.cr0 = cr0;
1927                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1928         }
1929
1930         if (!(cr0 & X86_CR0_WP))
1931                 *hw_cr0 &= ~X86_CR0_WP;
1932 }
1933
1934 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1935 {
1936         struct vcpu_vmx *vmx = to_vmx(vcpu);
1937         unsigned long hw_cr0;
1938
1939         if (enable_unrestricted_guest)
1940                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1941                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1942         else
1943                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1944
1945         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1946                 enter_pmode(vcpu);
1947
1948         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1949                 enter_rmode(vcpu);
1950
1951 #ifdef CONFIG_X86_64
1952         if (vcpu->arch.efer & EFER_LME) {
1953                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1954                         enter_lmode(vcpu);
1955                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1956                         exit_lmode(vcpu);
1957         }
1958 #endif
1959
1960         if (enable_ept)
1961                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1962
1963         if (!vcpu->fpu_active)
1964                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1965
1966         vmcs_writel(CR0_READ_SHADOW, cr0);
1967         vmcs_writel(GUEST_CR0, hw_cr0);
1968         vcpu->arch.cr0 = cr0;
1969 }
1970
1971 static u64 construct_eptp(unsigned long root_hpa)
1972 {
1973         u64 eptp;
1974
1975         /* TODO write the value reading from MSR */
1976         eptp = VMX_EPT_DEFAULT_MT |
1977                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1978         eptp |= (root_hpa & PAGE_MASK);
1979
1980         return eptp;
1981 }
1982
1983 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1984 {
1985         unsigned long guest_cr3;
1986         u64 eptp;
1987
1988         guest_cr3 = cr3;
1989         if (enable_ept) {
1990                 eptp = construct_eptp(cr3);
1991                 vmcs_write64(EPT_POINTER, eptp);
1992                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1993                         vcpu->kvm->arch.ept_identity_map_addr;
1994                 ept_load_pdptrs(vcpu);
1995         }
1996
1997         vmx_flush_tlb(vcpu);
1998         vmcs_writel(GUEST_CR3, guest_cr3);
1999 }
2000
2001 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2002 {
2003         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
2004                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2005
2006         vcpu->arch.cr4 = cr4;
2007         if (enable_ept) {
2008                 if (!is_paging(vcpu)) {
2009                         hw_cr4 &= ~X86_CR4_PAE;
2010                         hw_cr4 |= X86_CR4_PSE;
2011                 } else if (!(cr4 & X86_CR4_PAE)) {
2012                         hw_cr4 &= ~X86_CR4_PAE;
2013                 }
2014         }
2015
2016         vmcs_writel(CR4_READ_SHADOW, cr4);
2017         vmcs_writel(GUEST_CR4, hw_cr4);
2018 }
2019
2020 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2021 {
2022         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2023
2024         return vmcs_readl(sf->base);
2025 }
2026
2027 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2028                             struct kvm_segment *var, int seg)
2029 {
2030         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2031         u32 ar;
2032
2033         var->base = vmcs_readl(sf->base);
2034         var->limit = vmcs_read32(sf->limit);
2035         var->selector = vmcs_read16(sf->selector);
2036         ar = vmcs_read32(sf->ar_bytes);
2037         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2038                 ar = 0;
2039         var->type = ar & 15;
2040         var->s = (ar >> 4) & 1;
2041         var->dpl = (ar >> 5) & 3;
2042         var->present = (ar >> 7) & 1;
2043         var->avl = (ar >> 12) & 1;
2044         var->l = (ar >> 13) & 1;
2045         var->db = (ar >> 14) & 1;
2046         var->g = (ar >> 15) & 1;
2047         var->unusable = (ar >> 16) & 1;
2048 }
2049
2050 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2051 {
2052         if (!is_protmode(vcpu))
2053                 return 0;
2054
2055         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2056                 return 3;
2057
2058         return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2059 }
2060
2061 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2062 {
2063         u32 ar;
2064
2065         if (var->unusable)
2066                 ar = 1 << 16;
2067         else {
2068                 ar = var->type & 15;
2069                 ar |= (var->s & 1) << 4;
2070                 ar |= (var->dpl & 3) << 5;
2071                 ar |= (var->present & 1) << 7;
2072                 ar |= (var->avl & 1) << 12;
2073                 ar |= (var->l & 1) << 13;
2074                 ar |= (var->db & 1) << 14;
2075                 ar |= (var->g & 1) << 15;
2076         }
2077         if (ar == 0) /* a 0 value means unusable */
2078                 ar = AR_UNUSABLE_MASK;
2079
2080         return ar;
2081 }
2082
2083 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2084                             struct kvm_segment *var, int seg)
2085 {
2086         struct vcpu_vmx *vmx = to_vmx(vcpu);
2087         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2088         u32 ar;
2089
2090         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2091                 vmx->rmode.tr.selector = var->selector;
2092                 vmx->rmode.tr.base = var->base;
2093                 vmx->rmode.tr.limit = var->limit;
2094                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2095                 return;
2096         }
2097         vmcs_writel(sf->base, var->base);
2098         vmcs_write32(sf->limit, var->limit);
2099         vmcs_write16(sf->selector, var->selector);
2100         if (vmx->rmode.vm86_active && var->s) {
2101                 /*
2102                  * Hack real-mode segments into vm86 compatibility.
2103                  */
2104                 if (var->base == 0xffff0000 && var->selector == 0xf000)
2105                         vmcs_writel(sf->base, 0xf0000);
2106                 ar = 0xf3;
2107         } else
2108                 ar = vmx_segment_access_rights(var);
2109
2110         /*
2111          *   Fix the "Accessed" bit in AR field of segment registers for older
2112          * qemu binaries.
2113          *   IA32 arch specifies that at the time of processor reset the
2114          * "Accessed" bit in the AR field of segment registers is 1. And qemu
2115          * is setting it to 0 in the usedland code. This causes invalid guest
2116          * state vmexit when "unrestricted guest" mode is turned on.
2117          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
2118          * tree. Newer qemu binaries with that qemu fix would not need this
2119          * kvm hack.
2120          */
2121         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2122                 ar |= 0x1; /* Accessed */
2123
2124         vmcs_write32(sf->ar_bytes, ar);
2125 }
2126
2127 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2128 {
2129         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2130
2131         *db = (ar >> 14) & 1;
2132         *l = (ar >> 13) & 1;
2133 }
2134
2135 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2136 {
2137         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2138         dt->address = vmcs_readl(GUEST_IDTR_BASE);
2139 }
2140
2141 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2142 {
2143         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2144         vmcs_writel(GUEST_IDTR_BASE, dt->address);
2145 }
2146
2147 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2148 {
2149         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2150         dt->address = vmcs_readl(GUEST_GDTR_BASE);
2151 }
2152
2153 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2154 {
2155         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2156         vmcs_writel(GUEST_GDTR_BASE, dt->address);
2157 }
2158
2159 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2160 {
2161         struct kvm_segment var;
2162         u32 ar;
2163
2164         vmx_get_segment(vcpu, &var, seg);
2165         ar = vmx_segment_access_rights(&var);
2166
2167         if (var.base != (var.selector << 4))
2168                 return false;
2169         if (var.limit != 0xffff)
2170                 return false;
2171         if (ar != 0xf3)
2172                 return false;
2173
2174         return true;
2175 }
2176
2177 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2178 {
2179         struct kvm_segment cs;
2180         unsigned int cs_rpl;
2181
2182         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2183         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2184
2185         if (cs.unusable)
2186                 return false;
2187         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2188                 return false;
2189         if (!cs.s)
2190                 return false;
2191         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2192                 if (cs.dpl > cs_rpl)
2193                         return false;
2194         } else {
2195                 if (cs.dpl != cs_rpl)
2196                         return false;
2197         }
2198         if (!cs.present)
2199                 return false;
2200
2201         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2202         return true;
2203 }
2204
2205 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2206 {
2207         struct kvm_segment ss;
2208         unsigned int ss_rpl;
2209
2210         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2211         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2212
2213         if (ss.unusable)
2214                 return true;
2215         if (ss.type != 3 && ss.type != 7)
2216                 return false;
2217         if (!ss.s)
2218                 return false;
2219         if (ss.dpl != ss_rpl) /* DPL != RPL */
2220                 return false;
2221         if (!ss.present)
2222                 return false;
2223
2224         return true;
2225 }
2226
2227 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2228 {
2229         struct kvm_segment var;
2230         unsigned int rpl;
2231
2232         vmx_get_segment(vcpu, &var, seg);
2233         rpl = var.selector & SELECTOR_RPL_MASK;
2234
2235         if (var.unusable)
2236                 return true;
2237         if (!var.s)
2238                 return false;
2239         if (!var.present)
2240                 return false;
2241         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2242                 if (var.dpl < rpl) /* DPL < RPL */
2243                         return false;
2244         }
2245
2246         /* TODO: Add other members to kvm_segment_field to allow checking for other access
2247          * rights flags
2248          */
2249         return true;
2250 }
2251
2252 static bool tr_valid(struct kvm_vcpu *vcpu)
2253 {
2254         struct kvm_segment tr;
2255
2256         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2257
2258         if (tr.unusable)
2259                 return false;
2260         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
2261                 return false;
2262         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2263                 return false;
2264         if (!tr.present)
2265                 return false;
2266
2267         return true;
2268 }
2269
2270 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2271 {
2272         struct kvm_segment ldtr;
2273
2274         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2275
2276         if (ldtr.unusable)
2277                 return true;
2278         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2279                 return false;
2280         if (ldtr.type != 2)
2281                 return false;
2282         if (!ldtr.present)
2283                 return false;
2284
2285         return true;
2286 }
2287
2288 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2289 {
2290         struct kvm_segment cs, ss;
2291
2292         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2293         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2294
2295         return ((cs.selector & SELECTOR_RPL_MASK) ==
2296                  (ss.selector & SELECTOR_RPL_MASK));
2297 }
2298
2299 /*
2300  * Check if guest state is valid. Returns true if valid, false if
2301  * not.
2302  * We assume that registers are always usable
2303  */
2304 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2305 {
2306         /* real mode guest state checks */
2307         if (!is_protmode(vcpu)) {
2308                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2309                         return false;
2310                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2311                         return false;
2312                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2313                         return false;
2314                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2315                         return false;
2316                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2317                         return false;
2318                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2319                         return false;
2320         } else {
2321         /* protected mode guest state checks */
2322                 if (!cs_ss_rpl_check(vcpu))
2323                         return false;
2324                 if (!code_segment_valid(vcpu))
2325                         return false;
2326                 if (!stack_segment_valid(vcpu))
2327                         return false;
2328                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2329                         return false;
2330                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2331                         return false;
2332                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2333                         return false;
2334                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2335                         return false;
2336                 if (!tr_valid(vcpu))
2337                         return false;
2338                 if (!ldtr_valid(vcpu))
2339                         return false;
2340         }
2341         /* TODO:
2342          * - Add checks on RIP
2343          * - Add checks on RFLAGS
2344          */
2345
2346         return true;
2347 }
2348
2349 static int init_rmode_tss(struct kvm *kvm)
2350 {
2351         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2352         u16 data = 0;
2353         int ret = 0;
2354         int r;
2355
2356         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2357         if (r < 0)
2358                 goto out;
2359         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2360         r = kvm_write_guest_page(kvm, fn++, &data,
2361                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2362         if (r < 0)
2363                 goto out;
2364         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2365         if (r < 0)
2366                 goto out;
2367         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2368         if (r < 0)
2369                 goto out;
2370         data = ~0;
2371         r = kvm_write_guest_page(kvm, fn, &data,
2372                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2373                                  sizeof(u8));
2374         if (r < 0)
2375                 goto out;
2376
2377         ret = 1;
2378 out:
2379         return ret;
2380 }
2381
2382 static int init_rmode_identity_map(struct kvm *kvm)
2383 {
2384         int i, r, ret;
2385         pfn_t identity_map_pfn;
2386         u32 tmp;
2387
2388         if (!enable_ept)
2389                 return 1;
2390         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2391                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2392                         "haven't been allocated!\n");
2393                 return 0;
2394         }
2395         if (likely(kvm->arch.ept_identity_pagetable_done))
2396                 return 1;
2397         ret = 0;
2398         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2399         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2400         if (r < 0)
2401                 goto out;
2402         /* Set up identity-mapping pagetable for EPT in real mode */
2403         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2404                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2405                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2406                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2407                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2408                 if (r < 0)
2409                         goto out;
2410         }
2411         kvm->arch.ept_identity_pagetable_done = true;
2412         ret = 1;
2413 out:
2414         return ret;
2415 }
2416
2417 static void seg_setup(int seg)
2418 {
2419         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2420         unsigned int ar;
2421
2422         vmcs_write16(sf->selector, 0);
2423         vmcs_writel(sf->base, 0);
2424         vmcs_write32(sf->limit, 0xffff);
2425         if (enable_unrestricted_guest) {
2426                 ar = 0x93;
2427                 if (seg == VCPU_SREG_CS)
2428                         ar |= 0x08; /* code segment */
2429         } else
2430                 ar = 0xf3;
2431
2432         vmcs_write32(sf->ar_bytes, ar);
2433 }
2434
2435 static int alloc_apic_access_page(struct kvm *kvm)
2436 {
2437         struct kvm_userspace_memory_region kvm_userspace_mem;
2438         int r = 0;
2439
2440         mutex_lock(&kvm->slots_lock);
2441         if (kvm->arch.apic_access_page)
2442                 goto out;
2443         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2444         kvm_userspace_mem.flags = 0;
2445         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2446         kvm_userspace_mem.memory_size = PAGE_SIZE;
2447         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2448         if (r)
2449                 goto out;
2450
2451         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2452 out:
2453         mutex_unlock(&kvm->slots_lock);
2454         return r;
2455 }
2456
2457 static int alloc_identity_pagetable(struct kvm *kvm)
2458 {
2459         struct kvm_userspace_memory_region kvm_userspace_mem;
2460         int r = 0;
2461
2462         mutex_lock(&kvm->slots_lock);
2463         if (kvm->arch.ept_identity_pagetable)
2464                 goto out;
2465         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2466         kvm_userspace_mem.flags = 0;
2467         kvm_userspace_mem.guest_phys_addr =
2468                 kvm->arch.ept_identity_map_addr;
2469         kvm_userspace_mem.memory_size = PAGE_SIZE;
2470         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2471         if (r)
2472                 goto out;
2473
2474         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2475                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2476 out:
2477         mutex_unlock(&kvm->slots_lock);
2478         return r;
2479 }
2480
2481 static void allocate_vpid(struct vcpu_vmx *vmx)
2482 {
2483         int vpid;
2484
2485         vmx->vpid = 0;
2486         if (!enable_vpid)
2487                 return;
2488         spin_lock(&vmx_vpid_lock);
2489         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2490         if (vpid < VMX_NR_VPIDS) {
2491                 vmx->vpid = vpid;
2492                 __set_bit(vpid, vmx_vpid_bitmap);
2493         }
2494         spin_unlock(&vmx_vpid_lock);
2495 }
2496
2497 static void free_vpid(struct vcpu_vmx *vmx)
2498 {
2499         if (!enable_vpid)
2500                 return;
2501         spin_lock(&vmx_vpid_lock);
2502         if (vmx->vpid != 0)
2503                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2504         spin_unlock(&vmx_vpid_lock);
2505 }
2506
2507 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2508 {
2509         int f = sizeof(unsigned long);
2510
2511         if (!cpu_has_vmx_msr_bitmap())
2512                 return;
2513
2514         /*
2515          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2516          * have the write-low and read-high bitmap offsets the wrong way round.
2517          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2518          */
2519         if (msr <= 0x1fff) {
2520                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2521                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2522         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2523                 msr &= 0x1fff;
2524                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2525                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2526         }
2527 }
2528
2529 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2530 {
2531         if (!longmode_only)
2532                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2533         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2534 }
2535
2536 /*
2537  * Sets up the vmcs for emulated real mode.
2538  */
2539 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2540 {
2541         u32 host_sysenter_cs, msr_low, msr_high;
2542         u32 junk;
2543         u64 host_pat;
2544         unsigned long a;
2545         struct desc_ptr dt;
2546         int i;
2547         unsigned long kvm_vmx_return;
2548         u32 exec_control;
2549
2550         /* I/O */
2551         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2552         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2553
2554         if (cpu_has_vmx_msr_bitmap())
2555                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2556
2557         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2558
2559         /* Control */
2560         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2561                 vmcs_config.pin_based_exec_ctrl);
2562
2563         exec_control = vmcs_config.cpu_based_exec_ctrl;
2564         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2565                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2566 #ifdef CONFIG_X86_64
2567                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2568                                 CPU_BASED_CR8_LOAD_EXITING;
2569 #endif
2570         }
2571         if (!enable_ept)
2572                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2573                                 CPU_BASED_CR3_LOAD_EXITING  |
2574                                 CPU_BASED_INVLPG_EXITING;
2575         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2576
2577         if (cpu_has_secondary_exec_ctrls()) {
2578                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2579                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2580                         exec_control &=
2581                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2582                 if (vmx->vpid == 0)
2583                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2584                 if (!enable_ept) {
2585                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2586                         enable_unrestricted_guest = 0;
2587                 }
2588                 if (!enable_unrestricted_guest)
2589                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2590                 if (!ple_gap)
2591                         exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2592                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2593         }
2594
2595         if (ple_gap) {
2596                 vmcs_write32(PLE_GAP, ple_gap);
2597                 vmcs_write32(PLE_WINDOW, ple_window);
2598         }
2599
2600         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2601         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2602         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2603
2604         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
2605         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2606         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2607
2608         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2609         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2610         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2611         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
2612         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
2613         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2614 #ifdef CONFIG_X86_64
2615         rdmsrl(MSR_FS_BASE, a);
2616         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2617         rdmsrl(MSR_GS_BASE, a);
2618         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2619 #else
2620         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2621         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2622 #endif
2623
2624         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2625
2626         native_store_idt(&dt);
2627         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
2628
2629         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2630         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2631         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2632         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2633         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2634         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2635         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2636
2637         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2638         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2639         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2640         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2641         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2642         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2643
2644         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2645                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2646                 host_pat = msr_low | ((u64) msr_high << 32);
2647                 vmcs_write64(HOST_IA32_PAT, host_pat);
2648         }
2649         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2650                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2651                 host_pat = msr_low | ((u64) msr_high << 32);
2652                 /* Write the default value follow host pat */
2653                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2654                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2655                 vmx->vcpu.arch.pat = host_pat;
2656         }
2657
2658         for (i = 0; i < NR_VMX_MSR; ++i) {
2659                 u32 index = vmx_msr_index[i];
2660                 u32 data_low, data_high;
2661                 int j = vmx->nmsrs;
2662
2663                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2664                         continue;
2665                 if (wrmsr_safe(index, data_low, data_high) < 0)
2666                         continue;
2667                 vmx->guest_msrs[j].index = i;
2668                 vmx->guest_msrs[j].data = 0;
2669                 vmx->guest_msrs[j].mask = -1ull;
2670                 ++vmx->nmsrs;
2671         }
2672
2673         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2674
2675         /* 22.2.1, 20.8.1 */
2676         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2677
2678         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2679         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2680         if (enable_ept)
2681                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2682         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2683
2684         kvm_write_tsc(&vmx->vcpu, 0);
2685
2686         return 0;
2687 }
2688
2689 static int init_rmode(struct kvm *kvm)
2690 {
2691         int idx, ret = 0;
2692
2693         idx = srcu_read_lock(&kvm->srcu);
2694         if (!init_rmode_tss(kvm))
2695                 goto exit;
2696         if (!init_rmode_identity_map(kvm))
2697                 goto exit;
2698
2699         ret = 1;
2700 exit:
2701         srcu_read_unlock(&kvm->srcu, idx);
2702         return ret;
2703 }
2704
2705 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2706 {
2707         struct vcpu_vmx *vmx = to_vmx(vcpu);
2708         u64 msr;
2709         int ret;
2710
2711         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2712         if (!init_rmode(vmx->vcpu.kvm)) {
2713                 ret = -ENOMEM;
2714                 goto out;
2715         }
2716
2717         vmx->rmode.vm86_active = 0;
2718
2719         vmx->soft_vnmi_blocked = 0;
2720
2721         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2722         kvm_set_cr8(&vmx->vcpu, 0);
2723         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2724         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2725                 msr |= MSR_IA32_APICBASE_BSP;
2726         kvm_set_apic_base(&vmx->vcpu, msr);
2727
2728         ret = fx_init(&vmx->vcpu);
2729         if (ret != 0)
2730                 goto out;
2731
2732         seg_setup(VCPU_SREG_CS);
2733         /*
2734          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2735          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2736          */
2737         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2738                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2739                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2740         } else {
2741                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2742                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2743         }
2744
2745         seg_setup(VCPU_SREG_DS);
2746         seg_setup(VCPU_SREG_ES);
2747         seg_setup(VCPU_SREG_FS);
2748         seg_setup(VCPU_SREG_GS);
2749         seg_setup(VCPU_SREG_SS);
2750
2751         vmcs_write16(GUEST_TR_SELECTOR, 0);
2752         vmcs_writel(GUEST_TR_BASE, 0);
2753         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2754         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2755
2756         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2757         vmcs_writel(GUEST_LDTR_BASE, 0);
2758         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2759         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2760
2761         vmcs_write32(GUEST_SYSENTER_CS, 0);
2762         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2763         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2764
2765         vmcs_writel(GUEST_RFLAGS, 0x02);
2766         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2767                 kvm_rip_write(vcpu, 0xfff0);
2768         else
2769                 kvm_rip_write(vcpu, 0);
2770         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2771
2772         vmcs_writel(GUEST_DR7, 0x400);
2773
2774         vmcs_writel(GUEST_GDTR_BASE, 0);
2775         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2776
2777         vmcs_writel(GUEST_IDTR_BASE, 0);
2778         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2779
2780         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
2781         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2782         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2783
2784         /* Special registers */
2785         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2786
2787         setup_msrs(vmx);
2788
2789         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2790
2791         if (cpu_has_vmx_tpr_shadow()) {
2792                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2793                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2794                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2795                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2796                 vmcs_write32(TPR_THRESHOLD, 0);
2797         }
2798
2799         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2800                 vmcs_write64(APIC_ACCESS_ADDR,
2801                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2802
2803         if (vmx->vpid != 0)
2804                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2805
2806         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2807         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2808         vmx_set_cr4(&vmx->vcpu, 0);
2809         vmx_set_efer(&vmx->vcpu, 0);
2810         vmx_fpu_activate(&vmx->vcpu);
2811         update_exception_bitmap(&vmx->vcpu);
2812
2813         vpid_sync_context(vmx);
2814
2815         ret = 0;
2816
2817         /* HACK: Don't enable emulation on guest boot/reset */
2818         vmx->emulation_required = 0;
2819
2820 out:
2821         return ret;
2822 }
2823
2824 static void enable_irq_window(struct kvm_vcpu *vcpu)
2825 {
2826         u32 cpu_based_vm_exec_control;
2827
2828         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2829         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2830         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2831 }
2832
2833 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2834 {
2835         u32 cpu_based_vm_exec_control;
2836
2837         if (!cpu_has_virtual_nmis()) {
2838                 enable_irq_window(vcpu);
2839                 return;
2840         }
2841
2842         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
2843                 enable_irq_window(vcpu);
2844                 return;
2845         }
2846         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2847         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2848         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2849 }
2850
2851 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2852 {
2853         struct vcpu_vmx *vmx = to_vmx(vcpu);
2854         uint32_t intr;
2855         int irq = vcpu->arch.interrupt.nr;
2856
2857         trace_kvm_inj_virq(irq);
2858
2859         ++vcpu->stat.irq_injections;
2860         if (vmx->rmode.vm86_active) {
2861                 if (kvm_inject_realmode_interrupt(vcpu, irq) != EMULATE_DONE)
2862                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2863                 return;
2864         }
2865         intr = irq | INTR_INFO_VALID_MASK;
2866         if (vcpu->arch.interrupt.soft) {
2867                 intr |= INTR_TYPE_SOFT_INTR;
2868                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2869                              vmx->vcpu.arch.event_exit_inst_len);
2870         } else
2871                 intr |= INTR_TYPE_EXT_INTR;
2872         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2873         vmx_clear_hlt(vcpu);
2874 }
2875
2876 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2877 {
2878         struct vcpu_vmx *vmx = to_vmx(vcpu);
2879
2880         if (!cpu_has_virtual_nmis()) {
2881                 /*
2882                  * Tracking the NMI-blocked state in software is built upon
2883                  * finding the next open IRQ window. This, in turn, depends on
2884                  * well-behaving guests: They have to keep IRQs disabled at
2885                  * least as long as the NMI handler runs. Otherwise we may
2886                  * cause NMI nesting, maybe breaking the guest. But as this is
2887                  * highly unlikely, we can live with the residual risk.
2888                  */
2889                 vmx->soft_vnmi_blocked = 1;
2890                 vmx->vnmi_blocked_time = 0;
2891         }
2892
2893         ++vcpu->stat.nmi_injections;
2894         if (vmx->rmode.vm86_active) {
2895                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR) != EMULATE_DONE)
2896                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2897                 return;
2898         }
2899         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2900                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2901         vmx_clear_hlt(vcpu);
2902 }
2903
2904 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2905 {
2906         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2907                 return 0;
2908
2909         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2910                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
2911                    | GUEST_INTR_STATE_NMI));
2912 }
2913
2914 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2915 {
2916         if (!cpu_has_virtual_nmis())
2917                 return to_vmx(vcpu)->soft_vnmi_blocked;
2918         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
2919 }
2920
2921 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2922 {
2923         struct vcpu_vmx *vmx = to_vmx(vcpu);
2924
2925         if (!cpu_has_virtual_nmis()) {
2926                 if (vmx->soft_vnmi_blocked != masked) {
2927                         vmx->soft_vnmi_blocked = masked;
2928                         vmx->vnmi_blocked_time = 0;
2929                 }
2930         } else {
2931                 if (masked)
2932                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2933                                       GUEST_INTR_STATE_NMI);
2934                 else
2935                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2936                                         GUEST_INTR_STATE_NMI);
2937         }
2938 }
2939
2940 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2941 {
2942         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2943                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2944                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2945 }
2946
2947 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2948 {
2949         int ret;
2950         struct kvm_userspace_memory_region tss_mem = {
2951                 .slot = TSS_PRIVATE_MEMSLOT,
2952                 .guest_phys_addr = addr,
2953                 .memory_size = PAGE_SIZE * 3,
2954                 .flags = 0,
2955         };
2956
2957         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2958         if (ret)
2959                 return ret;
2960         kvm->arch.tss_addr = addr;
2961         return 0;
2962 }
2963
2964 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2965                                   int vec, u32 err_code)
2966 {
2967         /*
2968          * Instruction with address size override prefix opcode 0x67
2969          * Cause the #SS fault with 0 error code in VM86 mode.
2970          */
2971         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2972                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
2973                         return 1;
2974         /*
2975          * Forward all other exceptions that are valid in real mode.
2976          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2977          *        the required debugging infrastructure rework.
2978          */
2979         switch (vec) {
2980         case DB_VECTOR:
2981                 if (vcpu->guest_debug &
2982                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2983                         return 0;
2984                 kvm_queue_exception(vcpu, vec);
2985                 return 1;
2986         case BP_VECTOR:
2987                 /*
2988                  * Update instruction length as we may reinject the exception
2989                  * from user space while in guest debugging mode.
2990                  */
2991                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2992                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2993                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2994                         return 0;
2995                 /* fall through */
2996         case DE_VECTOR:
2997         case OF_VECTOR:
2998         case BR_VECTOR:
2999         case UD_VECTOR:
3000         case DF_VECTOR:
3001         case SS_VECTOR:
3002         case GP_VECTOR:
3003         case MF_VECTOR:
3004                 kvm_queue_exception(vcpu, vec);
3005                 return 1;
3006         }
3007         return 0;
3008 }
3009
3010 /*
3011  * Trigger machine check on the host. We assume all the MSRs are already set up
3012  * by the CPU and that we still run on the same CPU as the MCE occurred on.
3013  * We pass a fake environment to the machine check handler because we want
3014  * the guest to be always treated like user space, no matter what context
3015  * it used internally.
3016  */
3017 static void kvm_machine_check(void)
3018 {
3019 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3020         struct pt_regs regs = {
3021                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3022                 .flags = X86_EFLAGS_IF,
3023         };
3024
3025         do_machine_check(&regs, 0);
3026 #endif
3027 }
3028
3029 static int handle_machine_check(struct kvm_vcpu *vcpu)
3030 {
3031         /* already handled by vcpu_run */
3032         return 1;
3033 }
3034
3035 static int handle_exception(struct kvm_vcpu *vcpu)
3036 {
3037         struct vcpu_vmx *vmx = to_vmx(vcpu);
3038         struct kvm_run *kvm_run = vcpu->run;
3039         u32 intr_info, ex_no, error_code;
3040         unsigned long cr2, rip, dr6;
3041         u32 vect_info;
3042         enum emulation_result er;
3043
3044         vect_info = vmx->idt_vectoring_info;
3045         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3046
3047         if (is_machine_check(intr_info))
3048                 return handle_machine_check(vcpu);
3049
3050         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3051             !is_page_fault(intr_info)) {
3052                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3053                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3054                 vcpu->run->internal.ndata = 2;
3055                 vcpu->run->internal.data[0] = vect_info;
3056                 vcpu->run->internal.data[1] = intr_info;
3057                 return 0;
3058         }
3059
3060         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3061                 return 1;  /* already handled by vmx_vcpu_run() */
3062
3063         if (is_no_device(intr_info)) {
3064                 vmx_fpu_activate(vcpu);
3065                 return 1;
3066         }
3067
3068         if (is_invalid_opcode(intr_info)) {
3069                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
3070                 if (er != EMULATE_DONE)
3071                         kvm_queue_exception(vcpu, UD_VECTOR);
3072                 return 1;
3073         }
3074
3075         error_code = 0;
3076         rip = kvm_rip_read(vcpu);
3077         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3078                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3079         if (is_page_fault(intr_info)) {
3080                 /* EPT won't cause page fault directly */
3081                 if (enable_ept)
3082                         BUG();
3083                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3084                 trace_kvm_page_fault(cr2, error_code);
3085
3086                 if (kvm_event_needs_reinjection(vcpu))
3087                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
3088                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
3089         }
3090
3091         if (vmx->rmode.vm86_active &&
3092             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3093                                                                 error_code)) {
3094                 if (vcpu->arch.halt_request) {
3095                         vcpu->arch.halt_request = 0;
3096                         return kvm_emulate_halt(vcpu);
3097                 }
3098                 return 1;
3099         }
3100
3101         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3102         switch (ex_no) {
3103         case DB_VECTOR:
3104                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3105                 if (!(vcpu->guest_debug &
3106                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3107                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3108                         kvm_queue_exception(vcpu, DB_VECTOR);
3109                         return 1;
3110                 }
3111                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3112                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3113                 /* fall through */
3114         case BP_VECTOR:
3115                 /*
3116                  * Update instruction length as we may reinject #BP from
3117                  * user space while in guest debugging mode. Reading it for
3118                  * #DB as well causes no harm, it is not used in that case.
3119                  */
3120                 vmx->vcpu.arch.event_exit_inst_len =
3121                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3122                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3123                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3124                 kvm_run->debug.arch.exception = ex_no;
3125                 break;
3126         default:
3127                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3128                 kvm_run->ex.exception = ex_no;
3129                 kvm_run->ex.error_code = error_code;
3130                 break;
3131         }
3132         return 0;
3133 }
3134
3135 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3136 {
3137         ++vcpu->stat.irq_exits;
3138         return 1;
3139 }
3140
3141 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3142 {
3143         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3144         return 0;
3145 }
3146
3147 static int handle_io(struct kvm_vcpu *vcpu)
3148 {
3149         unsigned long exit_qualification;
3150         int size, in, string;
3151         unsigned port;
3152
3153         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3154         string = (exit_qualification & 16) != 0;
3155         in = (exit_qualification & 8) != 0;
3156
3157         ++vcpu->stat.io_exits;
3158
3159         if (string || in)
3160                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3161
3162         port = exit_qualification >> 16;
3163         size = (exit_qualification & 7) + 1;
3164         skip_emulated_instruction(vcpu);
3165
3166         return kvm_fast_pio_out(vcpu, size, port);
3167 }
3168
3169 static void
3170 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3171 {
3172         /*
3173          * Patch in the VMCALL instruction:
3174          */
3175         hypercall[0] = 0x0f;
3176         hypercall[1] = 0x01;
3177         hypercall[2] = 0xc1;
3178 }
3179
3180 static int handle_cr(struct kvm_vcpu *vcpu)
3181 {
3182         unsigned long exit_qualification, val;
3183         int cr;
3184         int reg;
3185         int err;
3186
3187         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3188         cr = exit_qualification & 15;
3189         reg = (exit_qualification >> 8) & 15;
3190         switch ((exit_qualification >> 4) & 3) {
3191         case 0: /* mov to cr */
3192                 val = kvm_register_read(vcpu, reg);
3193                 trace_kvm_cr_write(cr, val);
3194                 switch (cr) {
3195                 case 0:
3196                         err = kvm_set_cr0(vcpu, val);
3197                         kvm_complete_insn_gp(vcpu, err);
3198                         return 1;
3199                 case 3:
3200                         err = kvm_set_cr3(vcpu, val);
3201                         kvm_complete_insn_gp(vcpu, err);
3202                         return 1;
3203                 case 4:
3204                         err = kvm_set_cr4(vcpu, val);
3205                         kvm_complete_insn_gp(vcpu, err);
3206                         return 1;
3207                 case 8: {
3208                                 u8 cr8_prev = kvm_get_cr8(vcpu);
3209                                 u8 cr8 = kvm_register_read(vcpu, reg);
3210                                 err = kvm_set_cr8(vcpu, cr8);
3211                                 kvm_complete_insn_gp(vcpu, err);
3212                                 if (irqchip_in_kernel(vcpu->kvm))
3213                                         return 1;
3214                                 if (cr8_prev <= cr8)
3215                                         return 1;
3216                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3217                                 return 0;
3218                         }
3219                 };
3220                 break;
3221         case 2: /* clts */
3222                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3223                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3224                 skip_emulated_instruction(vcpu);
3225                 vmx_fpu_activate(vcpu);
3226                 return 1;
3227         case 1: /*mov from cr*/
3228                 switch (cr) {
3229                 case 3:
3230                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
3231                         trace_kvm_cr_read(cr, vcpu->arch.cr3);
3232                         skip_emulated_instruction(vcpu);
3233                         return 1;
3234                 case 8:
3235                         val = kvm_get_cr8(vcpu);
3236                         kvm_register_write(vcpu, reg, val);
3237                         trace_kvm_cr_read(cr, val);
3238                         skip_emulated_instruction(vcpu);
3239                         return 1;
3240                 }
3241                 break;
3242         case 3: /* lmsw */
3243                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3244                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3245                 kvm_lmsw(vcpu, val);
3246
3247                 skip_emulated_instruction(vcpu);
3248                 return 1;
3249         default:
3250                 break;
3251         }
3252         vcpu->run->exit_reason = 0;
3253         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3254                (int)(exit_qualification >> 4) & 3, cr);
3255         return 0;
3256 }
3257
3258 static int handle_dr(struct kvm_vcpu *vcpu)
3259 {
3260         unsigned long exit_qualification;
3261         int dr, reg;
3262
3263         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3264         if (!kvm_require_cpl(vcpu, 0))
3265                 return 1;
3266         dr = vmcs_readl(GUEST_DR7);
3267         if (dr & DR7_GD) {
3268                 /*
3269                  * As the vm-exit takes precedence over the debug trap, we
3270                  * need to emulate the latter, either for the host or the
3271                  * guest debugging itself.
3272                  */
3273                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3274                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3275                         vcpu->run->debug.arch.dr7 = dr;
3276                         vcpu->run->debug.arch.pc =
3277                                 vmcs_readl(GUEST_CS_BASE) +
3278                                 vmcs_readl(GUEST_RIP);
3279                         vcpu->run->debug.arch.exception = DB_VECTOR;
3280                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3281                         return 0;
3282                 } else {
3283                         vcpu->arch.dr7 &= ~DR7_GD;
3284                         vcpu->arch.dr6 |= DR6_BD;
3285                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3286                         kvm_queue_exception(vcpu, DB_VECTOR);
3287                         return 1;
3288                 }
3289         }
3290
3291         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3292         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3293         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3294         if (exit_qualification & TYPE_MOV_FROM_DR) {
3295                 unsigned long val;
3296                 if (!kvm_get_dr(vcpu, dr, &val))
3297                         kvm_register_write(vcpu, reg, val);
3298         } else
3299                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3300         skip_emulated_instruction(vcpu);
3301         return 1;
3302 }
3303
3304 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3305 {
3306         vmcs_writel(GUEST_DR7, val);
3307 }
3308
3309 static int handle_cpuid(struct kvm_vcpu *vcpu)
3310 {
3311         kvm_emulate_cpuid(vcpu);
3312         return 1;
3313 }
3314
3315 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3316 {
3317         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3318         u64 data;
3319
3320         if (vmx_get_msr(vcpu, ecx, &data)) {
3321                 trace_kvm_msr_read_ex(ecx);
3322                 kvm_inject_gp(vcpu, 0);
3323                 return 1;
3324         }
3325
3326         trace_kvm_msr_read(ecx, data);
3327
3328         /* FIXME: handling of bits 32:63 of rax, rdx */
3329         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3330         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3331         skip_emulated_instruction(vcpu);
3332         return 1;
3333 }
3334
3335 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3336 {
3337         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3338         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3339                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3340
3341         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3342                 trace_kvm_msr_write_ex(ecx, data);
3343                 kvm_inject_gp(vcpu, 0);
3344                 return 1;
3345         }
3346
3347         trace_kvm_msr_write(ecx, data);
3348         skip_emulated_instruction(vcpu);
3349         return 1;
3350 }
3351
3352 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3353 {
3354         kvm_make_request(KVM_REQ_EVENT, vcpu);
3355         return 1;
3356 }
3357
3358 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3359 {
3360         u32 cpu_based_vm_exec_control;
3361
3362         /* clear pending irq */
3363         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3364         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3365         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3366
3367         kvm_make_request(KVM_REQ_EVENT, vcpu);
3368
3369         ++vcpu->stat.irq_window_exits;
3370
3371         /*
3372          * If the user space waits to inject interrupts, exit as soon as
3373          * possible
3374          */
3375         if (!irqchip_in_kernel(vcpu->kvm) &&
3376             vcpu->run->request_interrupt_window &&
3377             !kvm_cpu_has_interrupt(vcpu)) {
3378                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3379                 return 0;
3380         }
3381         return 1;
3382 }
3383
3384 static int handle_halt(struct kvm_vcpu *vcpu)
3385 {
3386         skip_emulated_instruction(vcpu);
3387         return kvm_emulate_halt(vcpu);
3388 }
3389
3390 static int handle_vmcall(struct kvm_vcpu *vcpu)
3391 {
3392         skip_emulated_instruction(vcpu);
3393         kvm_emulate_hypercall(vcpu);
3394         return 1;
3395 }
3396
3397 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3398 {
3399         kvm_queue_exception(vcpu, UD_VECTOR);
3400         return 1;
3401 }
3402
3403 static int handle_invd(struct kvm_vcpu *vcpu)
3404 {
3405         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3406 }
3407
3408 static int handle_invlpg(struct kvm_vcpu *vcpu)
3409 {
3410         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3411
3412         kvm_mmu_invlpg(vcpu, exit_qualification);
3413         skip_emulated_instruction(vcpu);
3414         return 1;
3415 }
3416
3417 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3418 {
3419         skip_emulated_instruction(vcpu);
3420         kvm_emulate_wbinvd(vcpu);
3421         return 1;
3422 }
3423
3424 static int handle_xsetbv(struct kvm_vcpu *vcpu)
3425 {
3426         u64 new_bv = kvm_read_edx_eax(vcpu);
3427         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3428
3429         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3430                 skip_emulated_instruction(vcpu);
3431         return 1;
3432 }
3433
3434 static int handle_apic_access(struct kvm_vcpu *vcpu)
3435 {
3436         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3437 }
3438
3439 static int handle_task_switch(struct kvm_vcpu *vcpu)
3440 {
3441         struct vcpu_vmx *vmx = to_vmx(vcpu);
3442         unsigned long exit_qualification;
3443         bool has_error_code = false;
3444         u32 error_code = 0;
3445         u16 tss_selector;
3446         int reason, type, idt_v;
3447
3448         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3449         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3450
3451         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3452
3453         reason = (u32)exit_qualification >> 30;
3454         if (reason == TASK_SWITCH_GATE && idt_v) {
3455                 switch (type) {
3456                 case INTR_TYPE_NMI_INTR:
3457                         vcpu->arch.nmi_injected = false;
3458                         if (cpu_has_virtual_nmis())
3459                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3460                                               GUEST_INTR_STATE_NMI);
3461                         break;
3462                 case INTR_TYPE_EXT_INTR:
3463                 case INTR_TYPE_SOFT_INTR:
3464                         kvm_clear_interrupt_queue(vcpu);
3465                         break;
3466                 case INTR_TYPE_HARD_EXCEPTION:
3467                         if (vmx->idt_vectoring_info &
3468                             VECTORING_INFO_DELIVER_CODE_MASK) {
3469                                 has_error_code = true;
3470                                 error_code =
3471                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
3472                         }
3473                         /* fall through */
3474                 case INTR_TYPE_SOFT_EXCEPTION:
3475                         kvm_clear_exception_queue(vcpu);
3476                         break;
3477                 default:
3478                         break;
3479                 }
3480         }
3481         tss_selector = exit_qualification;
3482
3483         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3484                        type != INTR_TYPE_EXT_INTR &&
3485                        type != INTR_TYPE_NMI_INTR))
3486                 skip_emulated_instruction(vcpu);
3487
3488         if (kvm_task_switch(vcpu, tss_selector, reason,
3489                                 has_error_code, error_code) == EMULATE_FAIL) {
3490                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3491                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3492                 vcpu->run->internal.ndata = 0;
3493                 return 0;
3494         }
3495
3496         /* clear all local breakpoint enable flags */
3497         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3498
3499         /*
3500          * TODO: What about debug traps on tss switch?
3501          *       Are we supposed to inject them and update dr6?
3502          */
3503
3504         return 1;
3505 }
3506
3507 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3508 {
3509         unsigned long exit_qualification;
3510         gpa_t gpa;
3511         int gla_validity;
3512
3513         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3514
3515         if (exit_qualification & (1 << 6)) {
3516                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3517                 return -EINVAL;
3518         }
3519
3520         gla_validity = (exit_qualification >> 7) & 0x3;
3521         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3522                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3523                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3524                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3525                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3526                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3527                         (long unsigned int)exit_qualification);
3528                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3529                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3530                 return 0;
3531         }
3532
3533         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3534         trace_kvm_page_fault(gpa, exit_qualification);
3535         return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
3536 }
3537
3538 static u64 ept_rsvd_mask(u64 spte, int level)
3539 {
3540         int i;
3541         u64 mask = 0;
3542
3543         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3544                 mask |= (1ULL << i);
3545
3546         if (level > 2)
3547                 /* bits 7:3 reserved */
3548                 mask |= 0xf8;
3549         else if (level == 2) {
3550                 if (spte & (1ULL << 7))
3551                         /* 2MB ref, bits 20:12 reserved */
3552                         mask |= 0x1ff000;
3553                 else
3554                         /* bits 6:3 reserved */
3555                         mask |= 0x78;
3556         }
3557
3558         return mask;
3559 }
3560
3561 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3562                                        int level)
3563 {
3564         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3565
3566         /* 010b (write-only) */
3567         WARN_ON((spte & 0x7) == 0x2);
3568
3569         /* 110b (write/execute) */
3570         WARN_ON((spte & 0x7) == 0x6);
3571
3572         /* 100b (execute-only) and value not supported by logical processor */
3573         if (!cpu_has_vmx_ept_execute_only())
3574                 WARN_ON((spte & 0x7) == 0x4);
3575
3576         /* not 000b */
3577         if ((spte & 0x7)) {
3578                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3579
3580                 if (rsvd_bits != 0) {
3581                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3582                                          __func__, rsvd_bits);
3583                         WARN_ON(1);
3584                 }
3585
3586                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3587                         u64 ept_mem_type = (spte & 0x38) >> 3;
3588
3589                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3590                             ept_mem_type == 7) {
3591                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3592                                                 __func__, ept_mem_type);
3593                                 WARN_ON(1);
3594                         }
3595                 }
3596         }
3597 }
3598
3599 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3600 {
3601         u64 sptes[4];
3602         int nr_sptes, i;
3603         gpa_t gpa;
3604
3605         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3606
3607         printk(KERN_ERR "EPT: Misconfiguration.\n");
3608         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3609
3610         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3611
3612         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3613                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3614
3615         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3616         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3617
3618         return 0;
3619 }
3620
3621 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3622 {
3623         u32 cpu_based_vm_exec_control;
3624
3625         /* clear pending NMI */
3626         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3627         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3628         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3629         ++vcpu->stat.nmi_window_exits;
3630         kvm_make_request(KVM_REQ_EVENT, vcpu);
3631
3632         return 1;
3633 }
3634
3635 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3636 {
3637         struct vcpu_vmx *vmx = to_vmx(vcpu);
3638         enum emulation_result err = EMULATE_DONE;
3639         int ret = 1;
3640         u32 cpu_exec_ctrl;
3641         bool intr_window_requested;
3642
3643         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3644         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
3645
3646         while (!guest_state_valid(vcpu)) {
3647                 if (intr_window_requested
3648                     && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
3649                         return handle_interrupt_window(&vmx->vcpu);
3650
3651                 err = emulate_instruction(vcpu, 0);
3652
3653                 if (err == EMULATE_DO_MMIO) {
3654                         ret = 0;
3655                         goto out;
3656                 }
3657
3658                 if (err != EMULATE_DONE)
3659                         return 0;
3660
3661                 if (signal_pending(current))
3662                         goto out;
3663                 if (need_resched())
3664                         schedule();
3665         }
3666
3667         vmx->emulation_required = 0;
3668 out:
3669         return ret;
3670 }
3671
3672 /*
3673  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3674  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3675  */
3676 static int handle_pause(struct kvm_vcpu *vcpu)
3677 {
3678         skip_emulated_instruction(vcpu);
3679         kvm_vcpu_on_spin(vcpu);
3680
3681         return 1;
3682 }
3683
3684 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3685 {
3686         kvm_queue_exception(vcpu, UD_VECTOR);
3687         return 1;
3688 }
3689
3690 /*
3691  * The exit handlers return 1 if the exit was handled fully and guest execution
3692  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3693  * to be done to userspace and return 0.
3694  */
3695 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3696         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3697         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3698         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3699         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3700         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3701         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3702         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3703         [EXIT_REASON_CPUID]                   = handle_cpuid,
3704         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3705         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3706         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3707         [EXIT_REASON_HLT]                     = handle_halt,
3708         [EXIT_REASON_INVD]                    = handle_invd,
3709         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3710         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3711         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3712         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3713         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3714         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3715         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3716         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3717         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3718         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3719         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3720         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3721         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3722         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3723         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
3724         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3725         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3726         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3727         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
3728         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
3729         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
3730         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
3731 };
3732
3733 static const int kvm_vmx_max_exit_handlers =
3734         ARRAY_SIZE(kvm_vmx_exit_handlers);
3735
3736 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3737 {
3738         *info1 = vmcs_readl(EXIT_QUALIFICATION);
3739         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
3740 }
3741
3742 /*
3743  * The guest has exited.  See if we can fix it or if we need userspace
3744  * assistance.
3745  */
3746 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3747 {
3748         struct vcpu_vmx *vmx = to_vmx(vcpu);
3749         u32 exit_reason = vmx->exit_reason;
3750         u32 vectoring_info = vmx->idt_vectoring_info;
3751
3752         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
3753
3754         /* If guest state is invalid, start emulating */
3755         if (vmx->emulation_required && emulate_invalid_guest_state)
3756                 return handle_invalid_guest_state(vcpu);
3757
3758         /* Access CR3 don't cause VMExit in paging mode, so we need
3759          * to sync with guest real CR3. */
3760         if (enable_ept && is_paging(vcpu))
3761                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3762
3763         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3764                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3765                 vcpu->run->fail_entry.hardware_entry_failure_reason
3766                         = exit_reason;
3767                 return 0;
3768         }
3769
3770         if (unlikely(vmx->fail)) {
3771                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3772                 vcpu->run->fail_entry.hardware_entry_failure_reason
3773                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3774                 return 0;
3775         }
3776
3777         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3778                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3779                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3780                         exit_reason != EXIT_REASON_TASK_SWITCH))
3781                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3782                        "(0x%x) and exit reason is 0x%x\n",
3783                        __func__, vectoring_info, exit_reason);
3784
3785         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3786                 if (vmx_interrupt_allowed(vcpu)) {
3787                         vmx->soft_vnmi_blocked = 0;
3788                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3789                            vcpu->arch.nmi_pending) {
3790                         /*
3791                          * This CPU don't support us in finding the end of an
3792                          * NMI-blocked window if the guest runs with IRQs
3793                          * disabled. So we pull the trigger after 1 s of
3794                          * futile waiting, but inform the user about this.
3795                          */
3796                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3797                                "state on VCPU %d after 1 s timeout\n",
3798                                __func__, vcpu->vcpu_id);
3799                         vmx->soft_vnmi_blocked = 0;
3800                 }
3801         }
3802
3803         if (exit_reason < kvm_vmx_max_exit_handlers
3804             && kvm_vmx_exit_handlers[exit_reason])
3805                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3806         else {
3807                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3808                 vcpu->run->hw.hardware_exit_reason = exit_reason;
3809         }
3810         return 0;
3811 }
3812
3813 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3814 {
3815         if (irr == -1 || tpr < irr) {
3816                 vmcs_write32(TPR_THRESHOLD, 0);
3817                 return;
3818         }
3819
3820         vmcs_write32(TPR_THRESHOLD, irr);
3821 }
3822
3823 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
3824 {
3825         u32 exit_intr_info = vmx->exit_intr_info;
3826
3827         /* Handle machine checks before interrupts are enabled */
3828         if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3829             || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3830                 && is_machine_check(exit_intr_info)))
3831                 kvm_machine_check();
3832
3833         /* We need to handle NMIs before interrupts are enabled */
3834         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3835             (exit_intr_info & INTR_INFO_VALID_MASK)) {
3836                 kvm_before_handle_nmi(&vmx->vcpu);
3837                 asm("int $2");
3838                 kvm_after_handle_nmi(&vmx->vcpu);
3839         }
3840 }
3841
3842 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
3843 {
3844         u32 exit_intr_info = vmx->exit_intr_info;
3845         bool unblock_nmi;
3846         u8 vector;
3847         bool idtv_info_valid;
3848
3849         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3850
3851         if (cpu_has_virtual_nmis()) {
3852                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3853                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3854                 /*
3855                  * SDM 3: 27.7.1.2 (September 2008)
3856                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3857                  * a guest IRET fault.
3858                  * SDM 3: 23.2.2 (September 2008)
3859                  * Bit 12 is undefined in any of the following cases:
3860                  *  If the VM exit sets the valid bit in the IDT-vectoring
3861                  *   information field.
3862                  *  If the VM exit is due to a double fault.
3863                  */
3864                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3865                     vector != DF_VECTOR && !idtv_info_valid)
3866                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3867                                       GUEST_INTR_STATE_NMI);
3868         } else if (unlikely(vmx->soft_vnmi_blocked))
3869                 vmx->vnmi_blocked_time +=
3870                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3871 }
3872
3873 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
3874                                       u32 idt_vectoring_info,
3875                                       int instr_len_field,
3876                                       int error_code_field)
3877 {
3878         u8 vector;
3879         int type;
3880         bool idtv_info_valid;
3881
3882         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3883
3884         vmx->vcpu.arch.nmi_injected = false;
3885         kvm_clear_exception_queue(&vmx->vcpu);
3886         kvm_clear_interrupt_queue(&vmx->vcpu);
3887
3888         if (!idtv_info_valid)
3889                 return;
3890
3891         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
3892
3893         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3894         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3895
3896         switch (type) {
3897         case INTR_TYPE_NMI_INTR:
3898                 vmx->vcpu.arch.nmi_injected = true;
3899                 /*
3900                  * SDM 3: 27.7.1.2 (September 2008)
3901                  * Clear bit "block by NMI" before VM entry if a NMI
3902                  * delivery faulted.
3903                  */
3904                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3905                                 GUEST_INTR_STATE_NMI);
3906                 break;
3907         case INTR_TYPE_SOFT_EXCEPTION:
3908                 vmx->vcpu.arch.event_exit_inst_len =
3909                         vmcs_read32(instr_len_field);
3910                 /* fall through */
3911         case INTR_TYPE_HARD_EXCEPTION:
3912                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3913                         u32 err = vmcs_read32(error_code_field);
3914                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
3915                 } else
3916                         kvm_queue_exception(&vmx->vcpu, vector);
3917                 break;
3918         case INTR_TYPE_SOFT_INTR:
3919                 vmx->vcpu.arch.event_exit_inst_len =
3920                         vmcs_read32(instr_len_field);
3921                 /* fall through */
3922         case INTR_TYPE_EXT_INTR:
3923                 kvm_queue_interrupt(&vmx->vcpu, vector,
3924                         type == INTR_TYPE_SOFT_INTR);
3925                 break;
3926         default:
3927                 break;
3928         }
3929 }
3930
3931 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3932 {
3933         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
3934                                   VM_EXIT_INSTRUCTION_LEN,
3935                                   IDT_VECTORING_ERROR_CODE);
3936 }
3937
3938 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
3939 {
3940         __vmx_complete_interrupts(to_vmx(vcpu),
3941                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
3942                                   VM_ENTRY_INSTRUCTION_LEN,
3943                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
3944
3945         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
3946 }
3947
3948 #ifdef CONFIG_X86_64
3949 #define R "r"
3950 #define Q "q"
3951 #else
3952 #define R "e"
3953 #define Q "l"
3954 #endif
3955
3956 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3957 {
3958         struct vcpu_vmx *vmx = to_vmx(vcpu);
3959
3960         /* Record the guest's net vcpu time for enforced NMI injections. */
3961         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3962                 vmx->entry_time = ktime_get();
3963
3964         /* Don't enter VMX if guest state is invalid, let the exit handler
3965            start emulation until we arrive back to a valid state */
3966         if (vmx->emulation_required && emulate_invalid_guest_state)
3967                 return;
3968
3969         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3970                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3971         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3972                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3973
3974         /* When single-stepping over STI and MOV SS, we must clear the
3975          * corresponding interruptibility bits in the guest state. Otherwise
3976          * vmentry fails as it then expects bit 14 (BS) in pending debug
3977          * exceptions being set, but that's not correct for the guest debugging
3978          * case. */
3979         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3980                 vmx_set_interrupt_shadow(vcpu, 0);
3981
3982         asm(
3983                 /* Store host registers */
3984                 "push %%"R"dx; push %%"R"bp;"
3985                 "push %%"R"cx \n\t"
3986                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3987                 "je 1f \n\t"
3988                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3989                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3990                 "1: \n\t"
3991                 /* Reload cr2 if changed */
3992                 "mov %c[cr2](%0), %%"R"ax \n\t"
3993                 "mov %%cr2, %%"R"dx \n\t"
3994                 "cmp %%"R"ax, %%"R"dx \n\t"
3995                 "je 2f \n\t"
3996                 "mov %%"R"ax, %%cr2 \n\t"
3997                 "2: \n\t"
3998                 /* Check if vmlaunch of vmresume is needed */
3999                 "cmpl $0, %c[launched](%0) \n\t"
4000                 /* Load guest registers.  Don't clobber flags. */
4001                 "mov %c[rax](%0), %%"R"ax \n\t"
4002                 "mov %c[rbx](%0), %%"R"bx \n\t"
4003                 "mov %c[rdx](%0), %%"R"dx \n\t"
4004                 "mov %c[rsi](%0), %%"R"si \n\t"
4005                 "mov %c[rdi](%0), %%"R"di \n\t"
4006                 "mov %c[rbp](%0), %%"R"bp \n\t"
4007 #ifdef CONFIG_X86_64
4008                 "mov %c[r8](%0),  %%r8  \n\t"
4009                 "mov %c[r9](%0),  %%r9  \n\t"
4010                 "mov %c[r10](%0), %%r10 \n\t"
4011                 "mov %c[r11](%0), %%r11 \n\t"
4012                 "mov %c[r12](%0), %%r12 \n\t"
4013                 "mov %c[r13](%0), %%r13 \n\t"
4014                 "mov %c[r14](%0), %%r14 \n\t"
4015                 "mov %c[r15](%0), %%r15 \n\t"
4016 #endif
4017                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
4018
4019                 /* Enter guest mode */
4020                 "jne .Llaunched \n\t"
4021                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
4022                 "jmp .Lkvm_vmx_return \n\t"
4023                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
4024                 ".Lkvm_vmx_return: "
4025                 /* Save guest registers, load host registers, keep flags */
4026                 "xchg %0,     (%%"R"sp) \n\t"
4027                 "mov %%"R"ax, %c[rax](%0) \n\t"
4028                 "mov %%"R"bx, %c[rbx](%0) \n\t"
4029                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
4030                 "mov %%"R"dx, %c[rdx](%0) \n\t"
4031                 "mov %%"R"si, %c[rsi](%0) \n\t"
4032                 "mov %%"R"di, %c[rdi](%0) \n\t"
4033                 "mov %%"R"bp, %c[rbp](%0) \n\t"
4034 #ifdef CONFIG_X86_64
4035                 "mov %%r8,  %c[r8](%0) \n\t"
4036                 "mov %%r9,  %c[r9](%0) \n\t"
4037                 "mov %%r10, %c[r10](%0) \n\t"
4038                 "mov %%r11, %c[r11](%0) \n\t"
4039                 "mov %%r12, %c[r12](%0) \n\t"
4040                 "mov %%r13, %c[r13](%0) \n\t"
4041                 "mov %%r14, %c[r14](%0) \n\t"
4042                 "mov %%r15, %c[r15](%0) \n\t"
4043 #endif
4044                 "mov %%cr2, %%"R"ax   \n\t"
4045                 "mov %%"R"ax, %c[cr2](%0) \n\t"
4046
4047                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
4048                 "setbe %c[fail](%0) \n\t"
4049               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4050                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4051                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
4052                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
4053                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4054                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4055                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4056                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4057                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4058                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4059                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
4060 #ifdef CONFIG_X86_64
4061                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4062                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4063                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4064                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4065                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4066                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4067                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4068                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
4069 #endif
4070                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
4071               : "cc", "memory"
4072                 , R"ax", R"bx", R"di", R"si"
4073 #ifdef CONFIG_X86_64
4074                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4075 #endif
4076               );
4077
4078         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4079                                   | (1 << VCPU_EXREG_PDPTR));
4080         vcpu->arch.regs_dirty = 0;
4081
4082         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4083
4084         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
4085         vmx->launched = 1;
4086
4087         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
4088         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4089
4090         vmx_complete_atomic_exit(vmx);
4091         vmx_recover_nmi_blocking(vmx);
4092         vmx_complete_interrupts(vmx);
4093 }
4094
4095 #undef R
4096 #undef Q
4097
4098 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4099 {
4100         struct vcpu_vmx *vmx = to_vmx(vcpu);
4101
4102         if (vmx->vmcs) {
4103                 vcpu_clear(vmx);
4104                 free_vmcs(vmx->vmcs);
4105                 vmx->vmcs = NULL;
4106         }
4107 }
4108
4109 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4110 {
4111         struct vcpu_vmx *vmx = to_vmx(vcpu);
4112
4113         free_vpid(vmx);
4114         vmx_free_vmcs(vcpu);
4115         kfree(vmx->guest_msrs);
4116         kvm_vcpu_uninit(vcpu);
4117         kmem_cache_free(kvm_vcpu_cache, vmx);
4118 }
4119
4120 static inline void vmcs_init(struct vmcs *vmcs)
4121 {
4122         u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4123
4124         if (!vmm_exclusive)
4125                 kvm_cpu_vmxon(phys_addr);
4126
4127         vmcs_clear(vmcs);
4128
4129         if (!vmm_exclusive)
4130                 kvm_cpu_vmxoff();
4131 }
4132
4133 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4134 {
4135         int err;
4136         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4137         int cpu;
4138
4139         if (!vmx)
4140                 return ERR_PTR(-ENOMEM);
4141
4142         allocate_vpid(vmx);
4143
4144         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4145         if (err)
4146                 goto free_vcpu;
4147
4148         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4149         if (!vmx->guest_msrs) {
4150                 err = -ENOMEM;
4151                 goto uninit_vcpu;
4152         }
4153
4154         vmx->vmcs = alloc_vmcs();
4155         if (!vmx->vmcs)
4156                 goto free_msrs;
4157
4158         vmcs_init(vmx->vmcs);
4159
4160         cpu = get_cpu();
4161         vmx_vcpu_load(&vmx->vcpu, cpu);
4162         vmx->vcpu.cpu = cpu;
4163         err = vmx_vcpu_setup(vmx);
4164         vmx_vcpu_put(&vmx->vcpu);
4165         put_cpu();
4166         if (err)
4167                 goto free_vmcs;
4168         if (vm_need_virtualize_apic_accesses(kvm))
4169                 if (alloc_apic_access_page(kvm) != 0)
4170                         goto free_vmcs;
4171
4172         if (enable_ept) {
4173                 if (!kvm->arch.ept_identity_map_addr)
4174                         kvm->arch.ept_identity_map_addr =
4175                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4176                 if (alloc_identity_pagetable(kvm) != 0)
4177                         goto free_vmcs;
4178         }
4179
4180         return &vmx->vcpu;
4181
4182 free_vmcs:
4183         free_vmcs(vmx->vmcs);
4184 free_msrs:
4185         kfree(vmx->guest_msrs);
4186 uninit_vcpu:
4187         kvm_vcpu_uninit(&vmx->vcpu);
4188 free_vcpu:
4189         free_vpid(vmx);
4190         kmem_cache_free(kvm_vcpu_cache, vmx);
4191         return ERR_PTR(err);
4192 }
4193
4194 static void __init vmx_check_processor_compat(void *rtn)
4195 {
4196         struct vmcs_config vmcs_conf;
4197
4198         *(int *)rtn = 0;
4199         if (setup_vmcs_config(&vmcs_conf) < 0)
4200                 *(int *)rtn = -EIO;
4201         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4202                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4203                                 smp_processor_id());
4204                 *(int *)rtn = -EIO;
4205         }
4206 }
4207
4208 static int get_ept_level(void)
4209 {
4210         return VMX_EPT_DEFAULT_GAW + 1;
4211 }
4212
4213 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4214 {
4215         u64 ret;
4216
4217         /* For VT-d and EPT combination
4218          * 1. MMIO: always map as UC
4219          * 2. EPT with VT-d:
4220          *   a. VT-d without snooping control feature: can't guarantee the
4221          *      result, try to trust guest.
4222          *   b. VT-d with snooping control feature: snooping control feature of
4223          *      VT-d engine can guarantee the cache correctness. Just set it
4224          *      to WB to keep consistent with host. So the same as item 3.
4225          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4226          *    consistent with host MTRR
4227          */
4228         if (is_mmio)
4229                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4230         else if (vcpu->kvm->arch.iommu_domain &&
4231                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4232                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4233                       VMX_EPT_MT_EPTE_SHIFT;
4234         else
4235                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4236                         | VMX_EPT_IPAT_BIT;
4237
4238         return ret;
4239 }
4240
4241 #define _ER(x) { EXIT_REASON_##x, #x }
4242
4243 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4244         _ER(EXCEPTION_NMI),
4245         _ER(EXTERNAL_INTERRUPT),
4246         _ER(TRIPLE_FAULT),
4247         _ER(PENDING_INTERRUPT),
4248         _ER(NMI_WINDOW),
4249         _ER(TASK_SWITCH),
4250         _ER(CPUID),
4251         _ER(HLT),
4252         _ER(INVLPG),
4253         _ER(RDPMC),
4254         _ER(RDTSC),
4255         _ER(VMCALL),
4256         _ER(VMCLEAR),
4257         _ER(VMLAUNCH),
4258         _ER(VMPTRLD),
4259         _ER(VMPTRST),
4260         _ER(VMREAD),
4261         _ER(VMRESUME),
4262         _ER(VMWRITE),
4263         _ER(VMOFF),
4264         _ER(VMON),
4265         _ER(CR_ACCESS),
4266         _ER(DR_ACCESS),
4267         _ER(IO_INSTRUCTION),
4268         _ER(MSR_READ),
4269         _ER(MSR_WRITE),
4270         _ER(MWAIT_INSTRUCTION),
4271         _ER(MONITOR_INSTRUCTION),
4272         _ER(PAUSE_INSTRUCTION),
4273         _ER(MCE_DURING_VMENTRY),
4274         _ER(TPR_BELOW_THRESHOLD),
4275         _ER(APIC_ACCESS),
4276         _ER(EPT_VIOLATION),
4277         _ER(EPT_MISCONFIG),
4278         _ER(WBINVD),
4279         { -1, NULL }
4280 };
4281
4282 #undef _ER
4283
4284 static int vmx_get_lpage_level(void)
4285 {
4286         if (enable_ept && !cpu_has_vmx_ept_1g_page())
4287                 return PT_DIRECTORY_LEVEL;
4288         else
4289                 /* For shadow and EPT supported 1GB page */
4290                 return PT_PDPE_LEVEL;
4291 }
4292
4293 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4294 {
4295         struct kvm_cpuid_entry2 *best;
4296         struct vcpu_vmx *vmx = to_vmx(vcpu);
4297         u32 exec_control;
4298
4299         vmx->rdtscp_enabled = false;
4300         if (vmx_rdtscp_supported()) {
4301                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4302                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4303                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4304                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4305                                 vmx->rdtscp_enabled = true;
4306                         else {
4307                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4308                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4309                                                 exec_control);
4310                         }
4311                 }
4312         }
4313 }
4314
4315 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4316 {
4317 }
4318
4319 static struct kvm_x86_ops vmx_x86_ops = {
4320         .cpu_has_kvm_support = cpu_has_kvm_support,
4321         .disabled_by_bios = vmx_disabled_by_bios,
4322         .hardware_setup = hardware_setup,
4323         .hardware_unsetup = hardware_unsetup,
4324         .check_processor_compatibility = vmx_check_processor_compat,
4325         .hardware_enable = hardware_enable,
4326         .hardware_disable = hardware_disable,
4327         .cpu_has_accelerated_tpr = report_flexpriority,
4328
4329         .vcpu_create = vmx_create_vcpu,
4330         .vcpu_free = vmx_free_vcpu,
4331         .vcpu_reset = vmx_vcpu_reset,
4332
4333         .prepare_guest_switch = vmx_save_host_state,
4334         .vcpu_load = vmx_vcpu_load,
4335         .vcpu_put = vmx_vcpu_put,
4336
4337         .set_guest_debug = set_guest_debug,
4338         .get_msr = vmx_get_msr,
4339         .set_msr = vmx_set_msr,
4340         .get_segment_base = vmx_get_segment_base,
4341         .get_segment = vmx_get_segment,
4342         .set_segment = vmx_set_segment,
4343         .get_cpl = vmx_get_cpl,
4344         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4345         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4346         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4347         .set_cr0 = vmx_set_cr0,
4348         .set_cr3 = vmx_set_cr3,
4349         .set_cr4 = vmx_set_cr4,
4350         .set_efer = vmx_set_efer,
4351         .get_idt = vmx_get_idt,
4352         .set_idt = vmx_set_idt,
4353         .get_gdt = vmx_get_gdt,
4354         .set_gdt = vmx_set_gdt,
4355         .set_dr7 = vmx_set_dr7,
4356         .cache_reg = vmx_cache_reg,
4357         .get_rflags = vmx_get_rflags,
4358         .set_rflags = vmx_set_rflags,
4359         .fpu_activate = vmx_fpu_activate,
4360         .fpu_deactivate = vmx_fpu_deactivate,
4361
4362         .tlb_flush = vmx_flush_tlb,
4363
4364         .run = vmx_vcpu_run,
4365         .handle_exit = vmx_handle_exit,
4366         .skip_emulated_instruction = skip_emulated_instruction,
4367         .set_interrupt_shadow = vmx_set_interrupt_shadow,
4368         .get_interrupt_shadow = vmx_get_interrupt_shadow,
4369         .patch_hypercall = vmx_patch_hypercall,
4370         .set_irq = vmx_inject_irq,
4371         .set_nmi = vmx_inject_nmi,
4372         .queue_exception = vmx_queue_exception,
4373         .cancel_injection = vmx_cancel_injection,
4374         .interrupt_allowed = vmx_interrupt_allowed,
4375         .nmi_allowed = vmx_nmi_allowed,
4376         .get_nmi_mask = vmx_get_nmi_mask,
4377         .set_nmi_mask = vmx_set_nmi_mask,
4378         .enable_nmi_window = enable_nmi_window,
4379         .enable_irq_window = enable_irq_window,
4380         .update_cr8_intercept = update_cr8_intercept,
4381
4382         .set_tss_addr = vmx_set_tss_addr,
4383         .get_tdp_level = get_ept_level,
4384         .get_mt_mask = vmx_get_mt_mask,
4385
4386         .get_exit_info = vmx_get_exit_info,
4387         .exit_reasons_str = vmx_exit_reasons_str,
4388
4389         .get_lpage_level = vmx_get_lpage_level,
4390
4391         .cpuid_update = vmx_cpuid_update,
4392
4393         .rdtscp_supported = vmx_rdtscp_supported,
4394
4395         .set_supported_cpuid = vmx_set_supported_cpuid,
4396
4397         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
4398
4399         .write_tsc_offset = vmx_write_tsc_offset,
4400         .adjust_tsc_offset = vmx_adjust_tsc_offset,
4401
4402         .set_tdp_cr3 = vmx_set_cr3,
4403 };
4404
4405 static int __init vmx_init(void)
4406 {
4407         int r, i;
4408
4409         rdmsrl_safe(MSR_EFER, &host_efer);
4410
4411         for (i = 0; i < NR_VMX_MSR; ++i)
4412                 kvm_define_shared_msr(i, vmx_msr_index[i]);
4413
4414         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4415         if (!vmx_io_bitmap_a)
4416                 return -ENOMEM;
4417
4418         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4419         if (!vmx_io_bitmap_b) {
4420                 r = -ENOMEM;
4421                 goto out;
4422         }
4423
4424         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4425         if (!vmx_msr_bitmap_legacy) {
4426                 r = -ENOMEM;
4427                 goto out1;
4428         }
4429
4430         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4431         if (!vmx_msr_bitmap_longmode) {
4432                 r = -ENOMEM;
4433                 goto out2;
4434         }
4435
4436         /*
4437          * Allow direct access to the PC debug port (it is often used for I/O
4438          * delays, but the vmexits simply slow things down).
4439          */
4440         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4441         clear_bit(0x80, vmx_io_bitmap_a);
4442
4443         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4444
4445         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4446         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4447
4448         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4449
4450         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4451                      __alignof__(struct vcpu_vmx), THIS_MODULE);
4452         if (r)
4453                 goto out3;
4454
4455         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4456         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4457         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4458         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4459         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4460         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4461
4462         if (enable_ept) {
4463                 bypass_guest_pf = 0;
4464                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4465                                 VMX_EPT_EXECUTABLE_MASK);
4466                 kvm_enable_tdp();
4467         } else
4468                 kvm_disable_tdp();
4469
4470         if (bypass_guest_pf)
4471                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4472
4473         return 0;
4474
4475 out3:
4476         free_page((unsigned long)vmx_msr_bitmap_longmode);
4477 out2:
4478         free_page((unsigned long)vmx_msr_bitmap_legacy);
4479 out1:
4480         free_page((unsigned long)vmx_io_bitmap_b);
4481 out:
4482         free_page((unsigned long)vmx_io_bitmap_a);
4483         return r;
4484 }
4485
4486 static void __exit vmx_exit(void)
4487 {
4488         free_page((unsigned long)vmx_msr_bitmap_legacy);
4489         free_page((unsigned long)vmx_msr_bitmap_longmode);
4490         free_page((unsigned long)vmx_io_bitmap_b);
4491         free_page((unsigned long)vmx_io_bitmap_a);
4492
4493         kvm_exit();
4494 }
4495
4496 module_init(vmx_init)
4497 module_exit(vmx_exit)