arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/kvm_host.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31 #include <linux/tboot.h>
  32 #include "kvm_cache_regs.h"
  33 #include "x86.h"
  34
  35 #include <asm/io.h>
  36 #include <asm/desc.h>
  37 #include <asm/vmx.h>
  38 #include <asm/virtext.h>
  39 #include <asm/mce.h>
  40 #include <asm/i387.h>
  41 #include <asm/xcr.h>
  42
  43 #include "trace.h"
  44
  45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  46
  47 MODULE_AUTHOR("Qumranet");
  48 MODULE_LICENSE("GPL");
  49
  50 static int __read_mostly bypass_guest_pf = 1;
  51 module_param(bypass_guest_pf, bool, S_IRUGO);
  52
  53 static int __read_mostly enable_vpid = 1;
  54 module_param_named(vpid, enable_vpid, bool, 0444);
  55
  56 static int __read_mostly flexpriority_enabled = 1;
  57 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  58
  59 static int __read_mostly enable_ept = 1;
  60 module_param_named(ept, enable_ept, bool, S_IRUGO);
  61
  62 static int __read_mostly enable_unrestricted_guest = 1;
  63 module_param_named(unrestricted_guest,
  64                         enable_unrestricted_guest, bool, S_IRUGO);
  65
  66 static int __read_mostly emulate_invalid_guest_state = 0;
  67 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  68
  69 static int __read_mostly vmm_exclusive = 1;
  70 module_param(vmm_exclusive, bool, S_IRUGO);
  71
  72 static int __read_mostly yield_on_hlt = 1;
  73 module_param(yield_on_hlt, bool, S_IRUGO);
  74
  75 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  76         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  77 #define KVM_GUEST_CR0_MASK                                              \
  78         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  79 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  80         (X86_CR0_WP | X86_CR0_NE)
  81 #define KVM_VM_CR0_ALWAYS_ON                                            \
  82         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  83 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  84         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  85          | X86_CR4_OSXMMEXCPT)
  86
  87 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  88 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  89
  90 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
  91
  92 /*
  93  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
  94  * ple_gap:    upper bound on the amount of time between two successive
  95  *             executions of PAUSE in a loop. Also indicate if ple enabled.
  96  *             According to test, this time is usually smaller than 128 cycles.
  97  * ple_window: upper bound on the amount of time a guest is allowed to execute
  98  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
  99  *             less than 2^12 cycles
 100  * Time is measured based on a counter that runs at the same rate as the TSC,
 101  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 102  */
 103 #define KVM_VMX_DEFAULT_PLE_GAP    128
 104 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 105 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 106 module_param(ple_gap, int, S_IRUGO);
 107
 108 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 109 module_param(ple_window, int, S_IRUGO);
 110
 111 #define NR_AUTOLOAD_MSRS 1
 112
 113 struct vmcs {
 114         u32 revision_id;
 115         u32 abort;
 116         char data[0];
 117 };
 118
 119 struct shared_msr_entry {
 120         unsigned index;
 121         u64 data;
 122         u64 mask;
 123 };
 124
 125 struct vcpu_vmx {
 126         struct kvm_vcpu       vcpu;
 127         struct list_head      local_vcpus_link;
 128         unsigned long         host_rsp;
 129         int                   launched;
 130         u8                    fail;
 131         u8                    cpl;
 132         bool                  nmi_known_unmasked;
 133         u32                   exit_intr_info;
 134         u32                   idt_vectoring_info;
 135         ulong                 rflags;
 136         struct shared_msr_entry *guest_msrs;
 137         int                   nmsrs;
 138         int                   save_nmsrs;
 139 #ifdef CONFIG_X86_64
 140         u64                   msr_host_kernel_gs_base;
 141         u64                   msr_guest_kernel_gs_base;
 142 #endif
 143         struct vmcs          *vmcs;
 144         struct msr_autoload {
 145                 unsigned nr;
 146                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 147                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 148         } msr_autoload;
 149         struct {
 150                 int           loaded;
 151                 u16           fs_sel, gs_sel, ldt_sel;
 152                 int           gs_ldt_reload_needed;
 153                 int           fs_reload_needed;
 154         } host_state;
 155         struct {
 156                 int vm86_active;
 157                 ulong save_rflags;
 158                 struct kvm_save_segment {
 159                         u16 selector;
 160                         unsigned long base;
 161                         u32 limit;
 162                         u32 ar;
 163                 } tr, es, ds, fs, gs;
 164         } rmode;
 165         int vpid;
 166         bool emulation_required;
 167
 168         /* Support for vnmi-less CPUs */
 169         int soft_vnmi_blocked;
 170         ktime_t entry_time;
 171         s64 vnmi_blocked_time;
 172         u32 exit_reason;
 173
 174         bool rdtscp_enabled;
 175 };
 176
 177 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 178 {
 179         return container_of(vcpu, struct vcpu_vmx, vcpu);
 180 }
 181
 182 static u64 construct_eptp(unsigned long root_hpa);
 183 static void kvm_cpu_vmxon(u64 addr);
 184 static void kvm_cpu_vmxoff(void);
 185 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 186 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 187
 188 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 189 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 190 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 191 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 192
 193 static unsigned long *vmx_io_bitmap_a;
 194 static unsigned long *vmx_io_bitmap_b;
 195 static unsigned long *vmx_msr_bitmap_legacy;
 196 static unsigned long *vmx_msr_bitmap_longmode;
 197
 198 static bool cpu_has_load_ia32_efer;
 199
 200 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 201 static DEFINE_SPINLOCK(vmx_vpid_lock);
 202
 203 static struct vmcs_config {
 204         int size;
 205         int order;
 206         u32 revision_id;
 207         u32 pin_based_exec_ctrl;
 208         u32 cpu_based_exec_ctrl;
 209         u32 cpu_based_2nd_exec_ctrl;
 210         u32 vmexit_ctrl;
 211         u32 vmentry_ctrl;
 212 } vmcs_config;
 213
 214 static struct vmx_capability {
 215         u32 ept;
 216         u32 vpid;
 217 } vmx_capability;
 218
 219 #define VMX_SEGMENT_FIELD(seg)                                  \
 220         [VCPU_SREG_##seg] = {                                   \
 221                 .selector = GUEST_##seg##_SELECTOR,             \
 222                 .base = GUEST_##seg##_BASE,                     \
 223                 .limit = GUEST_##seg##_LIMIT,                   \
 224                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 225         }
 226
 227 static struct kvm_vmx_segment_field {
 228         unsigned selector;
 229         unsigned base;
 230         unsigned limit;
 231         unsigned ar_bytes;
 232 } kvm_vmx_segment_fields[] = {
 233         VMX_SEGMENT_FIELD(CS),
 234         VMX_SEGMENT_FIELD(DS),
 235         VMX_SEGMENT_FIELD(ES),
 236         VMX_SEGMENT_FIELD(FS),
 237         VMX_SEGMENT_FIELD(GS),
 238         VMX_SEGMENT_FIELD(SS),
 239         VMX_SEGMENT_FIELD(TR),
 240         VMX_SEGMENT_FIELD(LDTR),
 241 };
 242
 243 static u64 host_efer;
 244
 245 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 246
 247 /*
 248  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 249  * away by decrementing the array size.
 250  */
 251 static const u32 vmx_msr_index[] = {
 252 #ifdef CONFIG_X86_64
 253         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 254 #endif
 255         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 256 };
 257 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 258
 259 static inline bool is_page_fault(u32 intr_info)
 260 {
 261         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 262                              INTR_INFO_VALID_MASK)) ==
 263                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 264 }
 265
 266 static inline bool is_no_device(u32 intr_info)
 267 {
 268         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 269                              INTR_INFO_VALID_MASK)) ==
 270                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 271 }
 272
 273 static inline bool is_invalid_opcode(u32 intr_info)
 274 {
 275         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 276                              INTR_INFO_VALID_MASK)) ==
 277                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 278 }
 279
 280 static inline bool is_external_interrupt(u32 intr_info)
 281 {
 282         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 283                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 284 }
 285
 286 static inline bool is_machine_check(u32 intr_info)
 287 {
 288         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 289                              INTR_INFO_VALID_MASK)) ==
 290                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 291 }
 292
 293 static inline bool cpu_has_vmx_msr_bitmap(void)
 294 {
 295         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 296 }
 297
 298 static inline bool cpu_has_vmx_tpr_shadow(void)
 299 {
 300         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 301 }
 302
 303 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 304 {
 305         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 306 }
 307
 308 static inline bool cpu_has_secondary_exec_ctrls(void)
 309 {
 310         return vmcs_config.cpu_based_exec_ctrl &
 311                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 312 }
 313
 314 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 315 {
 316         return vmcs_config.cpu_based_2nd_exec_ctrl &
 317                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 318 }
 319
 320 static inline bool cpu_has_vmx_flexpriority(void)
 321 {
 322         return cpu_has_vmx_tpr_shadow() &&
 323                 cpu_has_vmx_virtualize_apic_accesses();
 324 }
 325
 326 static inline bool cpu_has_vmx_ept_execute_only(void)
 327 {
 328         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 329 }
 330
 331 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 332 {
 333         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 334 }
 335
 336 static inline bool cpu_has_vmx_eptp_writeback(void)
 337 {
 338         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 339 }
 340
 341 static inline bool cpu_has_vmx_ept_2m_page(void)
 342 {
 343         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 344 }
 345
 346 static inline bool cpu_has_vmx_ept_1g_page(void)
 347 {
 348         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 349 }
 350
 351 static inline bool cpu_has_vmx_ept_4levels(void)
 352 {
 353         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 354 }
 355
 356 static inline bool cpu_has_vmx_invept_individual_addr(void)
 357 {
 358         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 359 }
 360
 361 static inline bool cpu_has_vmx_invept_context(void)
 362 {
 363         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 364 }
 365
 366 static inline bool cpu_has_vmx_invept_global(void)
 367 {
 368         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 369 }
 370
 371 static inline bool cpu_has_vmx_invvpid_single(void)
 372 {
 373         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 374 }
 375
 376 static inline bool cpu_has_vmx_invvpid_global(void)
 377 {
 378         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 379 }
 380
 381 static inline bool cpu_has_vmx_ept(void)
 382 {
 383         return vmcs_config.cpu_based_2nd_exec_ctrl &
 384                 SECONDARY_EXEC_ENABLE_EPT;
 385 }
 386
 387 static inline bool cpu_has_vmx_unrestricted_guest(void)
 388 {
 389         return vmcs_config.cpu_based_2nd_exec_ctrl &
 390                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 391 }
 392
 393 static inline bool cpu_has_vmx_ple(void)
 394 {
 395         return vmcs_config.cpu_based_2nd_exec_ctrl &
 396                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 397 }
 398
 399 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 400 {
 401         return flexpriority_enabled && irqchip_in_kernel(kvm);
 402 }
 403
 404 static inline bool cpu_has_vmx_vpid(void)
 405 {
 406         return vmcs_config.cpu_based_2nd_exec_ctrl &
 407                 SECONDARY_EXEC_ENABLE_VPID;
 408 }
 409
 410 static inline bool cpu_has_vmx_rdtscp(void)
 411 {
 412         return vmcs_config.cpu_based_2nd_exec_ctrl &
 413                 SECONDARY_EXEC_RDTSCP;
 414 }
 415
 416 static inline bool cpu_has_virtual_nmis(void)
 417 {
 418         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 419 }
 420
 421 static inline bool cpu_has_vmx_wbinvd_exit(void)
 422 {
 423         return vmcs_config.cpu_based_2nd_exec_ctrl &
 424                 SECONDARY_EXEC_WBINVD_EXITING;
 425 }
 426
 427 static inline bool report_flexpriority(void)
 428 {
 429         return flexpriority_enabled;
 430 }
 431
 432 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 433 {
 434         int i;
 435
 436         for (i = 0; i < vmx->nmsrs; ++i)
 437                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 438                         return i;
 439         return -1;
 440 }
 441
 442 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 443 {
 444     struct {
 445         u64 vpid : 16;
 446         u64 rsvd : 48;
 447         u64 gva;
 448     } operand = { vpid, 0, gva };
 449
 450     asm volatile (__ex(ASM_VMX_INVVPID)
 451                   /* CF==1 or ZF==1 --> rc = -1 */
 452                   "; ja 1f ; ud2 ; 1:"
 453                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 454 }
 455
 456 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 457 {
 458         struct {
 459                 u64 eptp, gpa;
 460         } operand = {eptp, gpa};
 461
 462         asm volatile (__ex(ASM_VMX_INVEPT)
 463                         /* CF==1 or ZF==1 --> rc = -1 */
 464                         "; ja 1f ; ud2 ; 1:\n"
 465                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 466 }
 467
 468 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 469 {
 470         int i;
 471
 472         i = __find_msr_index(vmx, msr);
 473         if (i >= 0)
 474                 return &vmx->guest_msrs[i];
 475         return NULL;
 476 }
 477
 478 static void vmcs_clear(struct vmcs *vmcs)
 479 {
 480         u64 phys_addr = __pa(vmcs);
 481         u8 error;
 482
 483         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 484                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 485                       : "cc", "memory");
 486         if (error)
 487                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 488                        vmcs, phys_addr);
 489 }
 490
 491 static void vmcs_load(struct vmcs *vmcs)
 492 {
 493         u64 phys_addr = __pa(vmcs);
 494         u8 error;
 495
 496         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 497                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 498                         : "cc", "memory");
 499         if (error)
 500                 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 501                        vmcs, phys_addr);
 502 }
 503
 504 static void __vcpu_clear(void *arg)
 505 {
 506         struct vcpu_vmx *vmx = arg;
 507         int cpu = raw_smp_processor_id();
 508
 509         if (vmx->vcpu.cpu == cpu)
 510                 vmcs_clear(vmx->vmcs);
 511         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 512                 per_cpu(current_vmcs, cpu) = NULL;
 513         list_del(&vmx->local_vcpus_link);
 514         vmx->vcpu.cpu = -1;
 515         vmx->launched = 0;
 516 }
 517
 518 static void vcpu_clear(struct vcpu_vmx *vmx)
 519 {
 520         if (vmx->vcpu.cpu == -1)
 521                 return;
 522         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 523 }
 524
 525 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
 526 {
 527         if (vmx->vpid == 0)
 528                 return;
 529
 530         if (cpu_has_vmx_invvpid_single())
 531                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 532 }
 533
 534 static inline void vpid_sync_vcpu_global(void)
 535 {
 536         if (cpu_has_vmx_invvpid_global())
 537                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
 538 }
 539
 540 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
 541 {
 542         if (cpu_has_vmx_invvpid_single())
 543                 vpid_sync_vcpu_single(vmx);
 544         else
 545                 vpid_sync_vcpu_global();
 546 }
 547
 548 static inline void ept_sync_global(void)
 549 {
 550         if (cpu_has_vmx_invept_global())
 551                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 552 }
 553
 554 static inline void ept_sync_context(u64 eptp)
 555 {
 556         if (enable_ept) {
 557                 if (cpu_has_vmx_invept_context())
 558                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 559                 else
 560                         ept_sync_global();
 561         }
 562 }
 563
 564 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 565 {
 566         if (enable_ept) {
 567                 if (cpu_has_vmx_invept_individual_addr())
 568                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 569                                         eptp, gpa);
 570                 else
 571                         ept_sync_context(eptp);
 572         }
 573 }
 574
 575 static unsigned long vmcs_readl(unsigned long field)
 576 {
 577         unsigned long value = 0;
 578
 579         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 580                       : "+a"(value) : "d"(field) : "cc");
 581         return value;
 582 }
 583
 584 static u16 vmcs_read16(unsigned long field)
 585 {
 586         return vmcs_readl(field);
 587 }
 588
 589 static u32 vmcs_read32(unsigned long field)
 590 {
 591         return vmcs_readl(field);
 592 }
 593
 594 static u64 vmcs_read64(unsigned long field)
 595 {
 596 #ifdef CONFIG_X86_64
 597         return vmcs_readl(field);
 598 #else
 599         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 600 #endif
 601 }
 602
 603 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 604 {
 605         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 606                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 607         dump_stack();
 608 }
 609
 610 static void vmcs_writel(unsigned long field, unsigned long value)
 611 {
 612         u8 error;
 613
 614         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 615                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 616         if (unlikely(error))
 617                 vmwrite_error(field, value);
 618 }
 619
 620 static void vmcs_write16(unsigned long field, u16 value)
 621 {
 622         vmcs_writel(field, value);
 623 }
 624
 625 static void vmcs_write32(unsigned long field, u32 value)
 626 {
 627         vmcs_writel(field, value);
 628 }
 629
 630 static void vmcs_write64(unsigned long field, u64 value)
 631 {
 632         vmcs_writel(field, value);
 633 #ifndef CONFIG_X86_64
 634         asm volatile ("");
 635         vmcs_writel(field+1, value >> 32);
 636 #endif
 637 }
 638
 639 static void vmcs_clear_bits(unsigned long field, u32 mask)
 640 {
 641         vmcs_writel(field, vmcs_readl(field) & ~mask);
 642 }
 643
 644 static void vmcs_set_bits(unsigned long field, u32 mask)
 645 {
 646         vmcs_writel(field, vmcs_readl(field) | mask);
 647 }
 648
 649 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 650 {
 651         u32 eb;
 652
 653         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 654              (1u << NM_VECTOR) | (1u << DB_VECTOR);
 655         if ((vcpu->guest_debug &
 656              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 657             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 658                 eb |= 1u << BP_VECTOR;
 659         if (to_vmx(vcpu)->rmode.vm86_active)
 660                 eb = ~0;
 661         if (enable_ept)
 662                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 663         if (vcpu->fpu_active)
 664                 eb &= ~(1u << NM_VECTOR);
 665         vmcs_write32(EXCEPTION_BITMAP, eb);
 666 }
 667
 668 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 669 {
 670         unsigned i;
 671         struct msr_autoload *m = &vmx->msr_autoload;
 672
 673         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
 674                 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
 675                 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
 676                 return;
 677         }
 678
 679         for (i = 0; i < m->nr; ++i)
 680                 if (m->guest[i].index == msr)
 681                         break;
 682
 683         if (i == m->nr)
 684                 return;
 685         --m->nr;
 686         m->guest[i] = m->guest[m->nr];
 687         m->host[i] = m->host[m->nr];
 688         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
 689         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
 690 }
 691
 692 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 693                                   u64 guest_val, u64 host_val)
 694 {
 695         unsigned i;
 696         struct msr_autoload *m = &vmx->msr_autoload;
 697
 698         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
 699                 vmcs_write64(GUEST_IA32_EFER, guest_val);
 700                 vmcs_write64(HOST_IA32_EFER, host_val);
 701                 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
 702                 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
 703                 return;
 704         }
 705
 706         for (i = 0; i < m->nr; ++i)
 707                 if (m->guest[i].index == msr)
 708                         break;
 709
 710         if (i == m->nr) {
 711                 ++m->nr;
 712                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
 713                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
 714         }
 715
 716         m->guest[i].index = msr;
 717         m->guest[i].value = guest_val;
 718         m->host[i].index = msr;
 719         m->host[i].value = host_val;
 720 }
 721
 722 static void reload_tss(void)
 723 {
 724         /*
 725          * VT restores TR but not its size.  Useless.
 726          */
 727         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
 728         struct desc_struct *descs;
 729
 730         descs = (void *)gdt->address;
 731         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 732         load_TR_desc();
 733 }
 734
 735 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 736 {
 737         u64 guest_efer;
 738         u64 ignore_bits;
 739
 740         guest_efer = vmx->vcpu.arch.efer;
 741
 742         /*
 743          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 744          * outside long mode
 745          */
 746         ignore_bits = EFER_NX | EFER_SCE;
 747 #ifdef CONFIG_X86_64
 748         ignore_bits |= EFER_LMA | EFER_LME;
 749         /* SCE is meaningful only in long mode on Intel */
 750         if (guest_efer & EFER_LMA)
 751                 ignore_bits &= ~(u64)EFER_SCE;
 752 #endif
 753         guest_efer &= ~ignore_bits;
 754         guest_efer |= host_efer & ignore_bits;
 755         vmx->guest_msrs[efer_offset].data = guest_efer;
 756         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
 757
 758         clear_atomic_switch_msr(vmx, MSR_EFER);
 759         /* On ept, can't emulate nx, and must switch nx atomically */
 760         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
 761                 guest_efer = vmx->vcpu.arch.efer;
 762                 if (!(guest_efer & EFER_LMA))
 763                         guest_efer &= ~EFER_LME;
 764                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
 765                 return false;
 766         }
 767
 768         return true;
 769 }
 770
 771 static unsigned long segment_base(u16 selector)
 772 {
 773         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
 774         struct desc_struct *d;
 775         unsigned long table_base;
 776         unsigned long v;
 777
 778         if (!(selector & ~3))
 779                 return 0;
 780
 781         table_base = gdt->address;
 782
 783         if (selector & 4) {           /* from ldt */
 784                 u16 ldt_selector = kvm_read_ldt();
 785
 786                 if (!(ldt_selector & ~3))
 787                         return 0;
 788
 789                 table_base = segment_base(ldt_selector);
 790         }
 791         d = (struct desc_struct *)(table_base + (selector & ~7));
 792         v = get_desc_base(d);
 793 #ifdef CONFIG_X86_64
 794        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
 795                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
 796 #endif
 797         return v;
 798 }
 799
 800 static inline unsigned long kvm_read_tr_base(void)
 801 {
 802         u16 tr;
 803         asm("str %0" : "=g"(tr));
 804         return segment_base(tr);
 805 }
 806
 807 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 808 {
 809         struct vcpu_vmx *vmx = to_vmx(vcpu);
 810         int i;
 811
 812         if (vmx->host_state.loaded)
 813                 return;
 814
 815         vmx->host_state.loaded = 1;
 816         /*
 817          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 818          * allow segment selectors with cpl > 0 or ti == 1.
 819          */
 820         vmx->host_state.ldt_sel = kvm_read_ldt();
 821         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 822         savesegment(fs, vmx->host_state.fs_sel);
 823         if (!(vmx->host_state.fs_sel & 7)) {
 824                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 825                 vmx->host_state.fs_reload_needed = 0;
 826         } else {
 827                 vmcs_write16(HOST_FS_SELECTOR, 0);
 828                 vmx->host_state.fs_reload_needed = 1;
 829         }
 830         savesegment(gs, vmx->host_state.gs_sel);
 831         if (!(vmx->host_state.gs_sel & 7))
 832                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 833         else {
 834                 vmcs_write16(HOST_GS_SELECTOR, 0);
 835                 vmx->host_state.gs_ldt_reload_needed = 1;
 836         }
 837
 838 #ifdef CONFIG_X86_64
 839         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 840         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 841 #else
 842         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 843         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 844 #endif
 845
 846 #ifdef CONFIG_X86_64
 847         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 848         if (is_long_mode(&vmx->vcpu))
 849                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 850 #endif
 851         for (i = 0; i < vmx->save_nmsrs; ++i)
 852                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
 853                                    vmx->guest_msrs[i].data,
 854                                    vmx->guest_msrs[i].mask);
 855 }
 856
 857 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 858 {
 859         if (!vmx->host_state.loaded)
 860                 return;
 861
 862         ++vmx->vcpu.stat.host_state_reload;
 863         vmx->host_state.loaded = 0;
 864 #ifdef CONFIG_X86_64
 865         if (is_long_mode(&vmx->vcpu))
 866                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 867 #endif
 868         if (vmx->host_state.gs_ldt_reload_needed) {
 869                 kvm_load_ldt(vmx->host_state.ldt_sel);
 870 #ifdef CONFIG_X86_64
 871                 load_gs_index(vmx->host_state.gs_sel);
 872 #else
 873                 loadsegment(gs, vmx->host_state.gs_sel);
 874 #endif
 875         }
 876         if (vmx->host_state.fs_reload_needed)
 877                 loadsegment(fs, vmx->host_state.fs_sel);
 878         reload_tss();
 879 #ifdef CONFIG_X86_64
 880         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 881 #endif
 882         if (current_thread_info()->status & TS_USEDFPU)
 883                 clts();
 884         load_gdt(&__get_cpu_var(host_gdt));
 885 }
 886
 887 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 888 {
 889         preempt_disable();
 890         __vmx_load_host_state(vmx);
 891         preempt_enable();
 892 }
 893
 894 /*
 895  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 896  * vcpu mutex is already taken.
 897  */
 898 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 899 {
 900         struct vcpu_vmx *vmx = to_vmx(vcpu);
 901         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
 902
 903         if (!vmm_exclusive)
 904                 kvm_cpu_vmxon(phys_addr);
 905         else if (vcpu->cpu != cpu)
 906                 vcpu_clear(vmx);
 907
 908         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 909                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 910                 vmcs_load(vmx->vmcs);
 911         }
 912
 913         if (vcpu->cpu != cpu) {
 914                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
 915                 unsigned long sysenter_esp;
 916
 917                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
 918                 local_irq_disable();
 919                 list_add(&vmx->local_vcpus_link,
 920                          &per_cpu(vcpus_on_cpu, cpu));
 921                 local_irq_enable();
 922
 923                 /*
 924                  * Linux uses per-cpu TSS and GDT, so set these when switching
 925                  * processors.
 926                  */
 927                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 928                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
 929
 930                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 931                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 932         }
 933 }
 934
 935 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 936 {
 937         __vmx_load_host_state(to_vmx(vcpu));
 938         if (!vmm_exclusive) {
 939                 __vcpu_clear(to_vmx(vcpu));
 940                 kvm_cpu_vmxoff();
 941         }
 942 }
 943
 944 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 945 {
 946         ulong cr0;
 947
 948         if (vcpu->fpu_active)
 949                 return;
 950         vcpu->fpu_active = 1;
 951         cr0 = vmcs_readl(GUEST_CR0);
 952         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
 953         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
 954         vmcs_writel(GUEST_CR0, cr0);
 955         update_exception_bitmap(vcpu);
 956         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
 957         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 958 }
 959
 960 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
 961
 962 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 963 {
 964         vmx_decache_cr0_guest_bits(vcpu);
 965         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
 966         update_exception_bitmap(vcpu);
 967         vcpu->arch.cr0_guest_owned_bits = 0;
 968         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 969         vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
 970 }
 971
 972 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 973 {
 974         unsigned long rflags, save_rflags;
 975
 976         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
 977                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
 978                 rflags = vmcs_readl(GUEST_RFLAGS);
 979                 if (to_vmx(vcpu)->rmode.vm86_active) {
 980                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
 981                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
 982                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
 983                 }
 984                 to_vmx(vcpu)->rflags = rflags;
 985         }
 986         return to_vmx(vcpu)->rflags;
 987 }
 988
 989 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 990 {
 991         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
 992         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
 993         to_vmx(vcpu)->rflags = rflags;
 994         if (to_vmx(vcpu)->rmode.vm86_active) {
 995                 to_vmx(vcpu)->rmode.save_rflags = rflags;
 996                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 997         }
 998         vmcs_writel(GUEST_RFLAGS, rflags);
 999 }
1000
1001 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1002 {
1003         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1004         int ret = 0;
1005
1006         if (interruptibility & GUEST_INTR_STATE_STI)
1007                 ret |= KVM_X86_SHADOW_INT_STI;
1008         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1009                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1010
1011         return ret & mask;
1012 }
1013
1014 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1015 {
1016         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1017         u32 interruptibility = interruptibility_old;
1018
1019         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1020
1021         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1022                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1023         else if (mask & KVM_X86_SHADOW_INT_STI)
1024                 interruptibility |= GUEST_INTR_STATE_STI;
1025
1026         if ((interruptibility != interruptibility_old))
1027                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1028 }
1029
1030 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1031 {
1032         unsigned long rip;
1033
1034         rip = kvm_rip_read(vcpu);
1035         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1036         kvm_rip_write(vcpu, rip);
1037
1038         /* skipping an emulated instruction also counts */
1039         vmx_set_interrupt_shadow(vcpu, 0);
1040 }
1041
1042 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1043 {
1044         /* Ensure that we clear the HLT state in the VMCS.  We don't need to
1045          * explicitly skip the instruction because if the HLT state is set, then
1046          * the instruction is already executing and RIP has already been
1047          * advanced. */
1048         if (!yield_on_hlt &&
1049             vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1050                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1051 }
1052
1053 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1054                                 bool has_error_code, u32 error_code,
1055                                 bool reinject)
1056 {
1057         struct vcpu_vmx *vmx = to_vmx(vcpu);
1058         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1059
1060         if (has_error_code) {
1061                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1062                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1063         }
1064
1065         if (vmx->rmode.vm86_active) {
1066                 if (kvm_inject_realmode_interrupt(vcpu, nr) != EMULATE_DONE)
1067                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1068                 return;
1069         }
1070
1071         if (kvm_exception_is_soft(nr)) {
1072                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1073                              vmx->vcpu.arch.event_exit_inst_len);
1074                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1075         } else
1076                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1077
1078         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1079         vmx_clear_hlt(vcpu);
1080 }
1081
1082 static bool vmx_rdtscp_supported(void)
1083 {
1084         return cpu_has_vmx_rdtscp();
1085 }
1086
1087 /*
1088  * Swap MSR entry in host/guest MSR entry array.
1089  */
1090 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1091 {
1092         struct shared_msr_entry tmp;
1093
1094         tmp = vmx->guest_msrs[to];
1095         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1096         vmx->guest_msrs[from] = tmp;
1097 }
1098
1099 /*
1100  * Set up the vmcs to automatically save and restore system
1101  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1102  * mode, as fiddling with msrs is very expensive.
1103  */
1104 static void setup_msrs(struct vcpu_vmx *vmx)
1105 {
1106         int save_nmsrs, index;
1107         unsigned long *msr_bitmap;
1108
1109         vmx_load_host_state(vmx);
1110         save_nmsrs = 0;
1111 #ifdef CONFIG_X86_64
1112         if (is_long_mode(&vmx->vcpu)) {
1113                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1114                 if (index >= 0)
1115                         move_msr_up(vmx, index, save_nmsrs++);
1116                 index = __find_msr_index(vmx, MSR_LSTAR);
1117                 if (index >= 0)
1118                         move_msr_up(vmx, index, save_nmsrs++);
1119                 index = __find_msr_index(vmx, MSR_CSTAR);
1120                 if (index >= 0)
1121                         move_msr_up(vmx, index, save_nmsrs++);
1122                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1123                 if (index >= 0 && vmx->rdtscp_enabled)
1124                         move_msr_up(vmx, index, save_nmsrs++);
1125                 /*
1126                  * MSR_STAR is only needed on long mode guests, and only
1127                  * if efer.sce is enabled.
1128                  */
1129                 index = __find_msr_index(vmx, MSR_STAR);
1130                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1131                         move_msr_up(vmx, index, save_nmsrs++);
1132         }
1133 #endif
1134         index = __find_msr_index(vmx, MSR_EFER);
1135         if (index >= 0 && update_transition_efer(vmx, index))
1136                 move_msr_up(vmx, index, save_nmsrs++);
1137
1138         vmx->save_nmsrs = save_nmsrs;
1139
1140         if (cpu_has_vmx_msr_bitmap()) {
1141                 if (is_long_mode(&vmx->vcpu))
1142                         msr_bitmap = vmx_msr_bitmap_longmode;
1143                 else
1144                         msr_bitmap = vmx_msr_bitmap_legacy;
1145
1146                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1147         }
1148 }
1149
1150 /*
1151  * reads and returns guest's timestamp counter "register"
1152  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1153  */
1154 static u64 guest_read_tsc(void)
1155 {
1156         u64 host_tsc, tsc_offset;
1157
1158         rdtscll(host_tsc);
1159         tsc_offset = vmcs_read64(TSC_OFFSET);
1160         return host_tsc + tsc_offset;
1161 }
1162
1163 /*
1164  * writes 'offset' into guest's timestamp counter offset register
1165  */
1166 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1167 {
1168         vmcs_write64(TSC_OFFSET, offset);
1169 }
1170
1171 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1172 {
1173         u64 offset = vmcs_read64(TSC_OFFSET);
1174         vmcs_write64(TSC_OFFSET, offset + adjustment);
1175 }
1176
1177 /*
1178  * Reads an msr value (of 'msr_index') into 'pdata'.
1179  * Returns 0 on success, non-0 otherwise.
1180  * Assumes vcpu_load() was already called.
1181  */
1182 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1183 {
1184         u64 data;
1185         struct shared_msr_entry *msr;
1186
1187         if (!pdata) {
1188                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1189                 return -EINVAL;
1190         }
1191
1192         switch (msr_index) {
1193 #ifdef CONFIG_X86_64
1194         case MSR_FS_BASE:
1195                 data = vmcs_readl(GUEST_FS_BASE);
1196                 break;
1197         case MSR_GS_BASE:
1198                 data = vmcs_readl(GUEST_GS_BASE);
1199                 break;
1200         case MSR_KERNEL_GS_BASE:
1201                 vmx_load_host_state(to_vmx(vcpu));
1202                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1203                 break;
1204 #endif
1205         case MSR_EFER:
1206                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1207         case MSR_IA32_TSC:
1208                 data = guest_read_tsc();
1209                 break;
1210         case MSR_IA32_SYSENTER_CS:
1211                 data = vmcs_read32(GUEST_SYSENTER_CS);
1212                 break;
1213         case MSR_IA32_SYSENTER_EIP:
1214                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1215                 break;
1216         case MSR_IA32_SYSENTER_ESP:
1217                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1218                 break;
1219         case MSR_TSC_AUX:
1220                 if (!to_vmx(vcpu)->rdtscp_enabled)
1221                         return 1;
1222                 /* Otherwise falls through */
1223         default:
1224                 vmx_load_host_state(to_vmx(vcpu));
1225                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1226                 if (msr) {
1227                         vmx_load_host_state(to_vmx(vcpu));
1228                         data = msr->data;
1229                         break;
1230                 }
1231                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1232         }
1233
1234         *pdata = data;
1235         return 0;
1236 }
1237
1238 /*
1239  * Writes msr value into into the appropriate "register".
1240  * Returns 0 on success, non-0 otherwise.
1241  * Assumes vcpu_load() was already called.
1242  */
1243 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1244 {
1245         struct vcpu_vmx *vmx = to_vmx(vcpu);
1246         struct shared_msr_entry *msr;
1247         int ret = 0;
1248
1249         switch (msr_index) {
1250         case MSR_EFER:
1251                 vmx_load_host_state(vmx);
1252                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1253                 break;
1254 #ifdef CONFIG_X86_64
1255         case MSR_FS_BASE:
1256                 vmcs_writel(GUEST_FS_BASE, data);
1257                 break;
1258         case MSR_GS_BASE:
1259                 vmcs_writel(GUEST_GS_BASE, data);
1260                 break;
1261         case MSR_KERNEL_GS_BASE:
1262                 vmx_load_host_state(vmx);
1263                 vmx->msr_guest_kernel_gs_base = data;
1264                 break;
1265 #endif
1266         case MSR_IA32_SYSENTER_CS:
1267                 vmcs_write32(GUEST_SYSENTER_CS, data);
1268                 break;
1269         case MSR_IA32_SYSENTER_EIP:
1270                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1271                 break;
1272         case MSR_IA32_SYSENTER_ESP:
1273                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1274                 break;
1275         case MSR_IA32_TSC:
1276                 kvm_write_tsc(vcpu, data);
1277                 break;
1278         case MSR_IA32_CR_PAT:
1279                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1280                         vmcs_write64(GUEST_IA32_PAT, data);
1281                         vcpu->arch.pat = data;
1282                         break;
1283                 }
1284                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1285                 break;
1286         case MSR_TSC_AUX:
1287                 if (!vmx->rdtscp_enabled)
1288                         return 1;
1289                 /* Check reserved bit, higher 32 bits should be zero */
1290                 if ((data >> 32) != 0)
1291                         return 1;
1292                 /* Otherwise falls through */
1293         default:
1294                 msr = find_msr_entry(vmx, msr_index);
1295                 if (msr) {
1296                         vmx_load_host_state(vmx);
1297                         msr->data = data;
1298                         break;
1299                 }
1300                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1301         }
1302
1303         return ret;
1304 }
1305
1306 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1307 {
1308         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1309         switch (reg) {
1310         case VCPU_REGS_RSP:
1311                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1312                 break;
1313         case VCPU_REGS_RIP:
1314                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1315                 break;
1316         case VCPU_EXREG_PDPTR:
1317                 if (enable_ept)
1318                         ept_save_pdptrs(vcpu);
1319                 break;
1320         default:
1321                 break;
1322         }
1323 }
1324
1325 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1326 {
1327         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1328                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1329         else
1330                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1331
1332         update_exception_bitmap(vcpu);
1333 }
1334
1335 static __init int cpu_has_kvm_support(void)
1336 {
1337         return cpu_has_vmx();
1338 }
1339
1340 static __init int vmx_disabled_by_bios(void)
1341 {
1342         u64 msr;
1343
1344         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1345         if (msr & FEATURE_CONTROL_LOCKED) {
1346                 /* launched w/ TXT and VMX disabled */
1347                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1348                         && tboot_enabled())
1349                         return 1;
1350                 /* launched w/o TXT and VMX only enabled w/ TXT */
1351                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1352                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1353                         && !tboot_enabled()) {
1354                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
1355                                 "activate TXT before enabling KVM\n");
1356                         return 1;
1357                 }
1358                 /* launched w/o TXT and VMX disabled */
1359                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1360                         && !tboot_enabled())
1361                         return 1;
1362         }
1363
1364         return 0;
1365 }
1366
1367 static void kvm_cpu_vmxon(u64 addr)
1368 {
1369         asm volatile (ASM_VMX_VMXON_RAX
1370                         : : "a"(&addr), "m"(addr)
1371                         : "memory", "cc");
1372 }
1373
1374 static int hardware_enable(void *garbage)
1375 {
1376         int cpu = raw_smp_processor_id();
1377         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1378         u64 old, test_bits;
1379
1380         if (read_cr4() & X86_CR4_VMXE)
1381                 return -EBUSY;
1382
1383         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1384         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1385
1386         test_bits = FEATURE_CONTROL_LOCKED;
1387         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1388         if (tboot_enabled())
1389                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1390
1391         if ((old & test_bits) != test_bits) {
1392                 /* enable and lock */
1393                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1394         }
1395         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1396
1397         if (vmm_exclusive) {
1398                 kvm_cpu_vmxon(phys_addr);
1399                 ept_sync_global();
1400         }
1401
1402         store_gdt(&__get_cpu_var(host_gdt));
1403
1404         return 0;
1405 }
1406
1407 static void vmclear_local_vcpus(void)
1408 {
1409         int cpu = raw_smp_processor_id();
1410         struct vcpu_vmx *vmx, *n;
1411
1412         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1413                                  local_vcpus_link)
1414                 __vcpu_clear(vmx);
1415 }
1416
1417
1418 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1419  * tricks.
1420  */
1421 static void kvm_cpu_vmxoff(void)
1422 {
1423         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1424 }
1425
1426 static void hardware_disable(void *garbage)
1427 {
1428         if (vmm_exclusive) {
1429                 vmclear_local_vcpus();
1430                 kvm_cpu_vmxoff();
1431         }
1432         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1433 }
1434
1435 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1436                                       u32 msr, u32 *result)
1437 {
1438         u32 vmx_msr_low, vmx_msr_high;
1439         u32 ctl = ctl_min | ctl_opt;
1440
1441         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1442
1443         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1444         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1445
1446         /* Ensure minimum (required) set of control bits are supported. */
1447         if (ctl_min & ~ctl)
1448                 return -EIO;
1449
1450         *result = ctl;
1451         return 0;
1452 }
1453
1454 static __init bool allow_1_setting(u32 msr, u32 ctl)
1455 {
1456         u32 vmx_msr_low, vmx_msr_high;
1457
1458         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1459         return vmx_msr_high & ctl;
1460 }
1461
1462 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1463 {
1464         u32 vmx_msr_low, vmx_msr_high;
1465         u32 min, opt, min2, opt2;
1466         u32 _pin_based_exec_control = 0;
1467         u32 _cpu_based_exec_control = 0;
1468         u32 _cpu_based_2nd_exec_control = 0;
1469         u32 _vmexit_control = 0;
1470         u32 _vmentry_control = 0;
1471
1472         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1473         opt = PIN_BASED_VIRTUAL_NMIS;
1474         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1475                                 &_pin_based_exec_control) < 0)
1476                 return -EIO;
1477
1478         min =
1479 #ifdef CONFIG_X86_64
1480               CPU_BASED_CR8_LOAD_EXITING |
1481               CPU_BASED_CR8_STORE_EXITING |
1482 #endif
1483               CPU_BASED_CR3_LOAD_EXITING |
1484               CPU_BASED_CR3_STORE_EXITING |
1485               CPU_BASED_USE_IO_BITMAPS |
1486               CPU_BASED_MOV_DR_EXITING |
1487               CPU_BASED_USE_TSC_OFFSETING |
1488               CPU_BASED_MWAIT_EXITING |
1489               CPU_BASED_MONITOR_EXITING |
1490               CPU_BASED_INVLPG_EXITING;
1491
1492         if (yield_on_hlt)
1493                 min |= CPU_BASED_HLT_EXITING;
1494
1495         opt = CPU_BASED_TPR_SHADOW |
1496               CPU_BASED_USE_MSR_BITMAPS |
1497               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1498         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1499                                 &_cpu_based_exec_control) < 0)
1500                 return -EIO;
1501 #ifdef CONFIG_X86_64
1502         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1503                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1504                                            ~CPU_BASED_CR8_STORE_EXITING;
1505 #endif
1506         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1507                 min2 = 0;
1508                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1509                         SECONDARY_EXEC_WBINVD_EXITING |
1510                         SECONDARY_EXEC_ENABLE_VPID |
1511                         SECONDARY_EXEC_ENABLE_EPT |
1512                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
1513                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1514                         SECONDARY_EXEC_RDTSCP;
1515                 if (adjust_vmx_controls(min2, opt2,
1516                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1517                                         &_cpu_based_2nd_exec_control) < 0)
1518                         return -EIO;
1519         }
1520 #ifndef CONFIG_X86_64
1521         if (!(_cpu_based_2nd_exec_control &
1522                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1523                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1524 #endif
1525         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1526                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1527                    enabled */
1528                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1529                                              CPU_BASED_CR3_STORE_EXITING |
1530                                              CPU_BASED_INVLPG_EXITING);
1531                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1532                       vmx_capability.ept, vmx_capability.vpid);
1533         }
1534
1535         min = 0;
1536 #ifdef CONFIG_X86_64
1537         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1538 #endif
1539         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1540         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1541                                 &_vmexit_control) < 0)
1542                 return -EIO;
1543
1544         min = 0;
1545         opt = VM_ENTRY_LOAD_IA32_PAT;
1546         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1547                                 &_vmentry_control) < 0)
1548                 return -EIO;
1549
1550         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1551
1552         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1553         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1554                 return -EIO;
1555
1556 #ifdef CONFIG_X86_64
1557         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1558         if (vmx_msr_high & (1u<<16))
1559                 return -EIO;
1560 #endif
1561
1562         /* Require Write-Back (WB) memory type for VMCS accesses. */
1563         if (((vmx_msr_high >> 18) & 15) != 6)
1564                 return -EIO;
1565
1566         vmcs_conf->size = vmx_msr_high & 0x1fff;
1567         vmcs_conf->order = get_order(vmcs_config.size);
1568         vmcs_conf->revision_id = vmx_msr_low;
1569
1570         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1571         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1572         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1573         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1574         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1575
1576         cpu_has_load_ia32_efer =
1577                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
1578                                 VM_ENTRY_LOAD_IA32_EFER)
1579                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
1580                                    VM_EXIT_LOAD_IA32_EFER);
1581
1582         return 0;
1583 }
1584
1585 static struct vmcs *alloc_vmcs_cpu(int cpu)
1586 {
1587         int node = cpu_to_node(cpu);
1588         struct page *pages;
1589         struct vmcs *vmcs;
1590
1591         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1592         if (!pages)
1593                 return NULL;
1594         vmcs = page_address(pages);
1595         memset(vmcs, 0, vmcs_config.size);
1596         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1597         return vmcs;
1598 }
1599
1600 static struct vmcs *alloc_vmcs(void)
1601 {
1602         return alloc_vmcs_cpu(raw_smp_processor_id());
1603 }
1604
1605 static void free_vmcs(struct vmcs *vmcs)
1606 {
1607         free_pages((unsigned long)vmcs, vmcs_config.order);
1608 }
1609
1610 static void free_kvm_area(void)
1611 {
1612         int cpu;
1613
1614         for_each_possible_cpu(cpu) {
1615                 free_vmcs(per_cpu(vmxarea, cpu));
1616                 per_cpu(vmxarea, cpu) = NULL;
1617         }
1618 }
1619
1620 static __init int alloc_kvm_area(void)
1621 {
1622         int cpu;
1623
1624         for_each_possible_cpu(cpu) {
1625                 struct vmcs *vmcs;
1626
1627                 vmcs = alloc_vmcs_cpu(cpu);
1628                 if (!vmcs) {
1629                         free_kvm_area();
1630                         return -ENOMEM;
1631                 }
1632
1633                 per_cpu(vmxarea, cpu) = vmcs;
1634         }
1635         return 0;
1636 }
1637
1638 static __init int hardware_setup(void)
1639 {
1640         if (setup_vmcs_config(&vmcs_config) < 0)
1641                 return -EIO;
1642
1643         if (boot_cpu_has(X86_FEATURE_NX))
1644                 kvm_enable_efer_bits(EFER_NX);
1645
1646         if (!cpu_has_vmx_vpid())
1647                 enable_vpid = 0;
1648
1649         if (!cpu_has_vmx_ept() ||
1650             !cpu_has_vmx_ept_4levels()) {
1651                 enable_ept = 0;
1652                 enable_unrestricted_guest = 0;
1653         }
1654
1655         if (!cpu_has_vmx_unrestricted_guest())
1656                 enable_unrestricted_guest = 0;
1657
1658         if (!cpu_has_vmx_flexpriority())
1659                 flexpriority_enabled = 0;
1660
1661         if (!cpu_has_vmx_tpr_shadow())
1662                 kvm_x86_ops->update_cr8_intercept = NULL;
1663
1664         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1665                 kvm_disable_largepages();
1666
1667         if (!cpu_has_vmx_ple())
1668                 ple_gap = 0;
1669
1670         return alloc_kvm_area();
1671 }
1672
1673 static __exit void hardware_unsetup(void)
1674 {
1675         free_kvm_area();
1676 }
1677
1678 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1679 {
1680         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1681
1682         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1683                 vmcs_write16(sf->selector, save->selector);
1684                 vmcs_writel(sf->base, save->base);
1685                 vmcs_write32(sf->limit, save->limit);
1686                 vmcs_write32(sf->ar_bytes, save->ar);
1687         } else {
1688                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1689                         << AR_DPL_SHIFT;
1690                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1691         }
1692 }
1693
1694 static void enter_pmode(struct kvm_vcpu *vcpu)
1695 {
1696         unsigned long flags;
1697         struct vcpu_vmx *vmx = to_vmx(vcpu);
1698
1699         vmx->emulation_required = 1;
1700         vmx->rmode.vm86_active = 0;
1701
1702         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
1703         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1704         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1705         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1706
1707         flags = vmcs_readl(GUEST_RFLAGS);
1708         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1709         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1710         vmcs_writel(GUEST_RFLAGS, flags);
1711
1712         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1713                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1714
1715         update_exception_bitmap(vcpu);
1716
1717         if (emulate_invalid_guest_state)
1718                 return;
1719
1720         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1721         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1722         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1723         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1724
1725         vmcs_write16(GUEST_SS_SELECTOR, 0);
1726         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1727
1728         vmcs_write16(GUEST_CS_SELECTOR,
1729                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1730         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1731 }
1732
1733 static gva_t rmode_tss_base(struct kvm *kvm)
1734 {
1735         if (!kvm->arch.tss_addr) {
1736                 struct kvm_memslots *slots;
1737                 gfn_t base_gfn;
1738
1739                 slots = kvm_memslots(kvm);
1740                 base_gfn = slots->memslots[0].base_gfn +
1741                                  kvm->memslots->memslots[0].npages - 3;
1742                 return base_gfn << PAGE_SHIFT;
1743         }
1744         return kvm->arch.tss_addr;
1745 }
1746
1747 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1748 {
1749         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1750
1751         save->selector = vmcs_read16(sf->selector);
1752         save->base = vmcs_readl(sf->base);
1753         save->limit = vmcs_read32(sf->limit);
1754         save->ar = vmcs_read32(sf->ar_bytes);
1755         vmcs_write16(sf->selector, save->base >> 4);
1756         vmcs_write32(sf->base, save->base & 0xffff0);
1757         vmcs_write32(sf->limit, 0xffff);
1758         vmcs_write32(sf->ar_bytes, 0xf3);
1759         if (save->base & 0xf)
1760                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
1761                             " aligned when entering protected mode (seg=%d)",
1762                             seg);
1763 }
1764
1765 static void enter_rmode(struct kvm_vcpu *vcpu)
1766 {
1767         unsigned long flags;
1768         struct vcpu_vmx *vmx = to_vmx(vcpu);
1769
1770         if (enable_unrestricted_guest)
1771                 return;
1772
1773         vmx->emulation_required = 1;
1774         vmx->rmode.vm86_active = 1;
1775
1776         /*
1777          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
1778          * vcpu. Call it here with phys address pointing 16M below 4G.
1779          */
1780         if (!vcpu->kvm->arch.tss_addr) {
1781                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
1782                              "called before entering vcpu\n");
1783                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
1784                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
1785                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
1786         }
1787
1788         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
1789         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1790         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1791
1792         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1793         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1794
1795         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1796         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1797
1798         flags = vmcs_readl(GUEST_RFLAGS);
1799         vmx->rmode.save_rflags = flags;
1800
1801         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1802
1803         vmcs_writel(GUEST_RFLAGS, flags);
1804         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1805         update_exception_bitmap(vcpu);
1806
1807         if (emulate_invalid_guest_state)
1808                 goto continue_rmode;
1809
1810         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1811         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1812         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1813
1814         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1815         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1816         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1817                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1818         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1819
1820         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1821         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1822         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1823         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1824
1825 continue_rmode:
1826         kvm_mmu_reset_context(vcpu);
1827 }
1828
1829 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1830 {
1831         struct vcpu_vmx *vmx = to_vmx(vcpu);
1832         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1833
1834         if (!msr)
1835                 return;
1836
1837         /*
1838          * Force kernel_gs_base reloading before EFER changes, as control
1839          * of this msr depends on is_long_mode().
1840          */
1841         vmx_load_host_state(to_vmx(vcpu));
1842         vcpu->arch.efer = efer;
1843         if (efer & EFER_LMA) {
1844                 vmcs_write32(VM_ENTRY_CONTROLS,
1845                              vmcs_read32(VM_ENTRY_CONTROLS) |
1846                              VM_ENTRY_IA32E_MODE);
1847                 msr->data = efer;
1848         } else {
1849                 vmcs_write32(VM_ENTRY_CONTROLS,
1850                              vmcs_read32(VM_ENTRY_CONTROLS) &
1851                              ~VM_ENTRY_IA32E_MODE);
1852
1853                 msr->data = efer & ~EFER_LME;
1854         }
1855         setup_msrs(vmx);
1856 }
1857
1858 #ifdef CONFIG_X86_64
1859
1860 static void enter_lmode(struct kvm_vcpu *vcpu)
1861 {
1862         u32 guest_tr_ar;
1863
1864         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1865         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1866                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1867                        __func__);
1868                 vmcs_write32(GUEST_TR_AR_BYTES,
1869                              (guest_tr_ar & ~AR_TYPE_MASK)
1870                              | AR_TYPE_BUSY_64_TSS);
1871         }
1872         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
1873 }
1874
1875 static void exit_lmode(struct kvm_vcpu *vcpu)
1876 {
1877         vmcs_write32(VM_ENTRY_CONTROLS,
1878                      vmcs_read32(VM_ENTRY_CONTROLS)
1879                      & ~VM_ENTRY_IA32E_MODE);
1880         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
1881 }
1882
1883 #endif
1884
1885 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1886 {
1887         vpid_sync_context(to_vmx(vcpu));
1888         if (enable_ept) {
1889                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1890                         return;
1891                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1892         }
1893 }
1894
1895 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1896 {
1897         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1898
1899         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1900         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1901 }
1902
1903 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
1904 {
1905         if (enable_ept && is_paging(vcpu))
1906                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1907         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
1908 }
1909
1910 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1911 {
1912         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1913
1914         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1915         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1916 }
1917
1918 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1919 {
1920         if (!test_bit(VCPU_EXREG_PDPTR,
1921                       (unsigned long *)&vcpu->arch.regs_dirty))
1922                 return;
1923
1924         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1925                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
1926                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
1927                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
1928                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1929         }
1930 }
1931
1932 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1933 {
1934         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1935                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1936                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1937                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1938                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1939         }
1940
1941         __set_bit(VCPU_EXREG_PDPTR,
1942                   (unsigned long *)&vcpu->arch.regs_avail);
1943         __set_bit(VCPU_EXREG_PDPTR,
1944                   (unsigned long *)&vcpu->arch.regs_dirty);
1945 }
1946
1947 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1948
1949 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1950                                         unsigned long cr0,
1951                                         struct kvm_vcpu *vcpu)
1952 {
1953         vmx_decache_cr3(vcpu);
1954         if (!(cr0 & X86_CR0_PG)) {
1955                 /* From paging/starting to nonpaging */
1956                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1957                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1958                              (CPU_BASED_CR3_LOAD_EXITING |
1959                               CPU_BASED_CR3_STORE_EXITING));
1960                 vcpu->arch.cr0 = cr0;
1961                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1962         } else if (!is_paging(vcpu)) {
1963                 /* From nonpaging to paging */
1964                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1965                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1966                              ~(CPU_BASED_CR3_LOAD_EXITING |
1967                                CPU_BASED_CR3_STORE_EXITING));
1968                 vcpu->arch.cr0 = cr0;
1969                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1970         }
1971
1972         if (!(cr0 & X86_CR0_WP))
1973                 *hw_cr0 &= ~X86_CR0_WP;
1974 }
1975
1976 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1977 {
1978         struct vcpu_vmx *vmx = to_vmx(vcpu);
1979         unsigned long hw_cr0;
1980
1981         if (enable_unrestricted_guest)
1982                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1983                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1984         else
1985                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1986
1987         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1988                 enter_pmode(vcpu);
1989
1990         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1991                 enter_rmode(vcpu);
1992
1993 #ifdef CONFIG_X86_64
1994         if (vcpu->arch.efer & EFER_LME) {
1995                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1996                         enter_lmode(vcpu);
1997                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1998                         exit_lmode(vcpu);
1999         }
2000 #endif
2001
2002         if (enable_ept)
2003                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2004
2005         if (!vcpu->fpu_active)
2006                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2007
2008         vmcs_writel(CR0_READ_SHADOW, cr0);
2009         vmcs_writel(GUEST_CR0, hw_cr0);
2010         vcpu->arch.cr0 = cr0;
2011         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2012 }
2013
2014 static u64 construct_eptp(unsigned long root_hpa)
2015 {
2016         u64 eptp;
2017
2018         /* TODO write the value reading from MSR */
2019         eptp = VMX_EPT_DEFAULT_MT |
2020                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2021         eptp |= (root_hpa & PAGE_MASK);
2022
2023         return eptp;
2024 }
2025
2026 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2027 {
2028         unsigned long guest_cr3;
2029         u64 eptp;
2030
2031         guest_cr3 = cr3;
2032         if (enable_ept) {
2033                 eptp = construct_eptp(cr3);
2034                 vmcs_write64(EPT_POINTER, eptp);
2035                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
2036                         vcpu->kvm->arch.ept_identity_map_addr;
2037                 ept_load_pdptrs(vcpu);
2038         }
2039
2040         vmx_flush_tlb(vcpu);
2041         vmcs_writel(GUEST_CR3, guest_cr3);
2042 }
2043
2044 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2045 {
2046         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
2047                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2048
2049         vcpu->arch.cr4 = cr4;
2050         if (enable_ept) {
2051                 if (!is_paging(vcpu)) {
2052                         hw_cr4 &= ~X86_CR4_PAE;
2053                         hw_cr4 |= X86_CR4_PSE;
2054                 } else if (!(cr4 & X86_CR4_PAE)) {
2055                         hw_cr4 &= ~X86_CR4_PAE;
2056                 }
2057         }
2058
2059         vmcs_writel(CR4_READ_SHADOW, cr4);
2060         vmcs_writel(GUEST_CR4, hw_cr4);
2061 }
2062
2063 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2064                             struct kvm_segment *var, int seg)
2065 {
2066         struct vcpu_vmx *vmx = to_vmx(vcpu);
2067         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2068         struct kvm_save_segment *save;
2069         u32 ar;
2070
2071         if (vmx->rmode.vm86_active
2072             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2073                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2074                 || seg == VCPU_SREG_GS)
2075             && !emulate_invalid_guest_state) {
2076                 switch (seg) {
2077                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2078                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2079                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2080                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2081                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2082                 default: BUG();
2083                 }
2084                 var->selector = save->selector;
2085                 var->base = save->base;
2086                 var->limit = save->limit;
2087                 ar = save->ar;
2088                 if (seg == VCPU_SREG_TR
2089                     || var->selector == vmcs_read16(sf->selector))
2090                         goto use_saved_rmode_seg;
2091         }
2092         var->base = vmcs_readl(sf->base);
2093         var->limit = vmcs_read32(sf->limit);
2094         var->selector = vmcs_read16(sf->selector);
2095         ar = vmcs_read32(sf->ar_bytes);
2096 use_saved_rmode_seg:
2097         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2098                 ar = 0;
2099         var->type = ar & 15;
2100         var->s = (ar >> 4) & 1;
2101         var->dpl = (ar >> 5) & 3;
2102         var->present = (ar >> 7) & 1;
2103         var->avl = (ar >> 12) & 1;
2104         var->l = (ar >> 13) & 1;
2105         var->db = (ar >> 14) & 1;
2106         var->g = (ar >> 15) & 1;
2107         var->unusable = (ar >> 16) & 1;
2108 }
2109
2110 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2111 {
2112         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2113         struct kvm_segment s;
2114
2115         if (to_vmx(vcpu)->rmode.vm86_active) {
2116                 vmx_get_segment(vcpu, &s, seg);
2117                 return s.base;
2118         }
2119         return vmcs_readl(sf->base);
2120 }
2121
2122 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2123 {
2124         if (!is_protmode(vcpu))
2125                 return 0;
2126
2127         if (!is_long_mode(vcpu)
2128             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2129                 return 3;
2130
2131         return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2132 }
2133
2134 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2135 {
2136         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
2137                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2138                 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
2139         }
2140         return to_vmx(vcpu)->cpl;
2141 }
2142
2143
2144 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2145 {
2146         u32 ar;
2147
2148         if (var->unusable)
2149                 ar = 1 << 16;
2150         else {
2151                 ar = var->type & 15;
2152                 ar |= (var->s & 1) << 4;
2153                 ar |= (var->dpl & 3) << 5;
2154                 ar |= (var->present & 1) << 7;
2155                 ar |= (var->avl & 1) << 12;
2156                 ar |= (var->l & 1) << 13;
2157                 ar |= (var->db & 1) << 14;
2158                 ar |= (var->g & 1) << 15;
2159         }
2160         if (ar == 0) /* a 0 value means unusable */
2161                 ar = AR_UNUSABLE_MASK;
2162
2163         return ar;
2164 }
2165
2166 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2167                             struct kvm_segment *var, int seg)
2168 {
2169         struct vcpu_vmx *vmx = to_vmx(vcpu);
2170         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2171         u32 ar;
2172
2173         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2174                 vmcs_write16(sf->selector, var->selector);
2175                 vmx->rmode.tr.selector = var->selector;
2176                 vmx->rmode.tr.base = var->base;
2177                 vmx->rmode.tr.limit = var->limit;
2178                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2179                 return;
2180         }
2181         vmcs_writel(sf->base, var->base);
2182         vmcs_write32(sf->limit, var->limit);
2183         vmcs_write16(sf->selector, var->selector);
2184         if (vmx->rmode.vm86_active && var->s) {
2185                 /*
2186                  * Hack real-mode segments into vm86 compatibility.
2187                  */
2188                 if (var->base == 0xffff0000 && var->selector == 0xf000)
2189                         vmcs_writel(sf->base, 0xf0000);
2190                 ar = 0xf3;
2191         } else
2192                 ar = vmx_segment_access_rights(var);
2193
2194         /*
2195          *   Fix the "Accessed" bit in AR field of segment registers for older
2196          * qemu binaries.
2197          *   IA32 arch specifies that at the time of processor reset the
2198          * "Accessed" bit in the AR field of segment registers is 1. And qemu
2199          * is setting it to 0 in the usedland code. This causes invalid guest
2200          * state vmexit when "unrestricted guest" mode is turned on.
2201          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
2202          * tree. Newer qemu binaries with that qemu fix would not need this
2203          * kvm hack.
2204          */
2205         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2206                 ar |= 0x1; /* Accessed */
2207
2208         vmcs_write32(sf->ar_bytes, ar);
2209         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2210 }
2211
2212 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2213 {
2214         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2215
2216         *db = (ar >> 14) & 1;
2217         *l = (ar >> 13) & 1;
2218 }
2219
2220 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2221 {
2222         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2223         dt->address = vmcs_readl(GUEST_IDTR_BASE);
2224 }
2225
2226 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2227 {
2228         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2229         vmcs_writel(GUEST_IDTR_BASE, dt->address);
2230 }
2231
2232 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2233 {
2234         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2235         dt->address = vmcs_readl(GUEST_GDTR_BASE);
2236 }
2237
2238 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2239 {
2240         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2241         vmcs_writel(GUEST_GDTR_BASE, dt->address);
2242 }
2243
2244 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2245 {
2246         struct kvm_segment var;
2247         u32 ar;
2248
2249         vmx_get_segment(vcpu, &var, seg);
2250         ar = vmx_segment_access_rights(&var);
2251
2252         if (var.base != (var.selector << 4))
2253                 return false;
2254         if (var.limit != 0xffff)
2255                 return false;
2256         if (ar != 0xf3)
2257                 return false;
2258
2259         return true;
2260 }
2261
2262 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2263 {
2264         struct kvm_segment cs;
2265         unsigned int cs_rpl;
2266
2267         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2268         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2269
2270         if (cs.unusable)
2271                 return false;
2272         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2273                 return false;
2274         if (!cs.s)
2275                 return false;
2276         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2277                 if (cs.dpl > cs_rpl)
2278                         return false;
2279         } else {
2280                 if (cs.dpl != cs_rpl)
2281                         return false;
2282         }
2283         if (!cs.present)
2284                 return false;
2285
2286         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2287         return true;
2288 }
2289
2290 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2291 {
2292         struct kvm_segment ss;
2293         unsigned int ss_rpl;
2294
2295         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2296         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2297
2298         if (ss.unusable)
2299                 return true;
2300         if (ss.type != 3 && ss.type != 7)
2301                 return false;
2302         if (!ss.s)
2303                 return false;
2304         if (ss.dpl != ss_rpl) /* DPL != RPL */
2305                 return false;
2306         if (!ss.present)
2307                 return false;
2308
2309         return true;
2310 }
2311
2312 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2313 {
2314         struct kvm_segment var;
2315         unsigned int rpl;
2316
2317         vmx_get_segment(vcpu, &var, seg);
2318         rpl = var.selector & SELECTOR_RPL_MASK;
2319
2320         if (var.unusable)
2321                 return true;
2322         if (!var.s)
2323                 return false;
2324         if (!var.present)
2325                 return false;
2326         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2327                 if (var.dpl < rpl) /* DPL < RPL */
2328                         return false;
2329         }
2330
2331         /* TODO: Add other members to kvm_segment_field to allow checking for other access
2332          * rights flags
2333          */
2334         return true;
2335 }
2336
2337 static bool tr_valid(struct kvm_vcpu *vcpu)
2338 {
2339         struct kvm_segment tr;
2340
2341         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2342
2343         if (tr.unusable)
2344                 return false;
2345         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
2346                 return false;
2347         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2348                 return false;
2349         if (!tr.present)
2350                 return false;
2351
2352         return true;
2353 }
2354
2355 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2356 {
2357         struct kvm_segment ldtr;
2358
2359         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2360
2361         if (ldtr.unusable)
2362                 return true;
2363         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2364                 return false;
2365         if (ldtr.type != 2)
2366                 return false;
2367         if (!ldtr.present)
2368                 return false;
2369
2370         return true;
2371 }
2372
2373 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2374 {
2375         struct kvm_segment cs, ss;
2376
2377         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2378         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2379
2380         return ((cs.selector & SELECTOR_RPL_MASK) ==
2381                  (ss.selector & SELECTOR_RPL_MASK));
2382 }
2383
2384 /*
2385  * Check if guest state is valid. Returns true if valid, false if
2386  * not.
2387  * We assume that registers are always usable
2388  */
2389 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2390 {
2391         /* real mode guest state checks */
2392         if (!is_protmode(vcpu)) {
2393                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2394                         return false;
2395                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2396                         return false;
2397                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2398                         return false;
2399                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2400                         return false;
2401                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2402                         return false;
2403                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2404                         return false;
2405         } else {
2406         /* protected mode guest state checks */
2407                 if (!cs_ss_rpl_check(vcpu))
2408                         return false;
2409                 if (!code_segment_valid(vcpu))
2410                         return false;
2411                 if (!stack_segment_valid(vcpu))
2412                         return false;
2413                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2414                         return false;
2415                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2416                         return false;
2417                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2418                         return false;
2419                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2420                         return false;
2421                 if (!tr_valid(vcpu))
2422                         return false;
2423                 if (!ldtr_valid(vcpu))
2424                         return false;
2425         }
2426         /* TODO:
2427          * - Add checks on RIP
2428          * - Add checks on RFLAGS
2429          */
2430
2431         return true;
2432 }
2433
2434 static int init_rmode_tss(struct kvm *kvm)
2435 {
2436         gfn_t fn;
2437         u16 data = 0;
2438         int r, idx, ret = 0;
2439
2440         idx = srcu_read_lock(&kvm->srcu);
2441         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2442         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2443         if (r < 0)
2444                 goto out;
2445         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2446         r = kvm_write_guest_page(kvm, fn++, &data,
2447                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2448         if (r < 0)
2449                 goto out;
2450         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2451         if (r < 0)
2452                 goto out;
2453         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2454         if (r < 0)
2455                 goto out;
2456         data = ~0;
2457         r = kvm_write_guest_page(kvm, fn, &data,
2458                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2459                                  sizeof(u8));
2460         if (r < 0)
2461                 goto out;
2462
2463         ret = 1;
2464 out:
2465         srcu_read_unlock(&kvm->srcu, idx);
2466         return ret;
2467 }
2468
2469 static int init_rmode_identity_map(struct kvm *kvm)
2470 {
2471         int i, idx, r, ret;
2472         pfn_t identity_map_pfn;
2473         u32 tmp;
2474
2475         if (!enable_ept)
2476                 return 1;
2477         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2478                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2479                         "haven't been allocated!\n");
2480                 return 0;
2481         }
2482         if (likely(kvm->arch.ept_identity_pagetable_done))
2483                 return 1;
2484         ret = 0;
2485         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2486         idx = srcu_read_lock(&kvm->srcu);
2487         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2488         if (r < 0)
2489                 goto out;
2490         /* Set up identity-mapping pagetable for EPT in real mode */
2491         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2492                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2493                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2494                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2495                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2496                 if (r < 0)
2497                         goto out;
2498         }
2499         kvm->arch.ept_identity_pagetable_done = true;
2500         ret = 1;
2501 out:
2502         srcu_read_unlock(&kvm->srcu, idx);
2503         return ret;
2504 }
2505
2506 static void seg_setup(int seg)
2507 {
2508         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2509         unsigned int ar;
2510
2511         vmcs_write16(sf->selector, 0);
2512         vmcs_writel(sf->base, 0);
2513         vmcs_write32(sf->limit, 0xffff);
2514         if (enable_unrestricted_guest) {
2515                 ar = 0x93;
2516                 if (seg == VCPU_SREG_CS)
2517                         ar |= 0x08; /* code segment */
2518         } else
2519                 ar = 0xf3;
2520
2521         vmcs_write32(sf->ar_bytes, ar);
2522 }
2523
2524 static int alloc_apic_access_page(struct kvm *kvm)
2525 {
2526         struct kvm_userspace_memory_region kvm_userspace_mem;
2527         int r = 0;
2528
2529         mutex_lock(&kvm->slots_lock);
2530         if (kvm->arch.apic_access_page)
2531                 goto out;
2532         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2533         kvm_userspace_mem.flags = 0;
2534         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2535         kvm_userspace_mem.memory_size = PAGE_SIZE;
2536         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2537         if (r)
2538                 goto out;
2539
2540         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2541 out:
2542         mutex_unlock(&kvm->slots_lock);
2543         return r;
2544 }
2545
2546 static int alloc_identity_pagetable(struct kvm *kvm)
2547 {
2548         struct kvm_userspace_memory_region kvm_userspace_mem;
2549         int r = 0;
2550
2551         mutex_lock(&kvm->slots_lock);
2552         if (kvm->arch.ept_identity_pagetable)
2553                 goto out;
2554         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2555         kvm_userspace_mem.flags = 0;
2556         kvm_userspace_mem.guest_phys_addr =
2557                 kvm->arch.ept_identity_map_addr;
2558         kvm_userspace_mem.memory_size = PAGE_SIZE;
2559         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2560         if (r)
2561                 goto out;
2562
2563         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2564                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2565 out:
2566         mutex_unlock(&kvm->slots_lock);
2567         return r;
2568 }
2569
2570 static void allocate_vpid(struct vcpu_vmx *vmx)
2571 {
2572         int vpid;
2573
2574         vmx->vpid = 0;
2575         if (!enable_vpid)
2576                 return;
2577         spin_lock(&vmx_vpid_lock);
2578         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2579         if (vpid < VMX_NR_VPIDS) {
2580                 vmx->vpid = vpid;
2581                 __set_bit(vpid, vmx_vpid_bitmap);
2582         }
2583         spin_unlock(&vmx_vpid_lock);
2584 }
2585
2586 static void free_vpid(struct vcpu_vmx *vmx)
2587 {
2588         if (!enable_vpid)
2589                 return;
2590         spin_lock(&vmx_vpid_lock);
2591         if (vmx->vpid != 0)
2592                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2593         spin_unlock(&vmx_vpid_lock);
2594 }
2595
2596 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2597 {
2598         int f = sizeof(unsigned long);
2599
2600         if (!cpu_has_vmx_msr_bitmap())
2601                 return;
2602
2603         /*
2604          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2605          * have the write-low and read-high bitmap offsets the wrong way round.
2606          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2607          */
2608         if (msr <= 0x1fff) {
2609                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2610                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2611         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2612                 msr &= 0x1fff;
2613                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2614                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2615         }
2616 }
2617
2618 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2619 {
2620         if (!longmode_only)
2621                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2622         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2623 }
2624
2625 /*
2626  * Sets up the vmcs for emulated real mode.
2627  */
2628 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2629 {
2630         u32 host_sysenter_cs, msr_low, msr_high;
2631         u32 junk;
2632         u64 host_pat;
2633         unsigned long a;
2634         struct desc_ptr dt;
2635         int i;
2636         unsigned long kvm_vmx_return;
2637         u32 exec_control;
2638
2639         /* I/O */
2640         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2641         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2642
2643         if (cpu_has_vmx_msr_bitmap())
2644                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2645
2646         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2647
2648         /* Control */
2649         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2650                 vmcs_config.pin_based_exec_ctrl);
2651
2652         exec_control = vmcs_config.cpu_based_exec_ctrl;
2653         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2654                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2655 #ifdef CONFIG_X86_64
2656                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2657                                 CPU_BASED_CR8_LOAD_EXITING;
2658 #endif
2659         }
2660         if (!enable_ept)
2661                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2662                                 CPU_BASED_CR3_LOAD_EXITING  |
2663                                 CPU_BASED_INVLPG_EXITING;
2664         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2665
2666         if (cpu_has_secondary_exec_ctrls()) {
2667                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2668                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2669                         exec_control &=
2670                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2671                 if (vmx->vpid == 0)
2672                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2673                 if (!enable_ept) {
2674                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2675                         enable_unrestricted_guest = 0;
2676                 }
2677                 if (!enable_unrestricted_guest)
2678                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2679                 if (!ple_gap)
2680                         exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2681                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2682         }
2683
2684         if (ple_gap) {
2685                 vmcs_write32(PLE_GAP, ple_gap);
2686                 vmcs_write32(PLE_WINDOW, ple_window);
2687         }
2688
2689         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2690         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2691         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2692
2693         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
2694         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2695         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2696
2697         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2698         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2699         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2700         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
2701         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
2702         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2703 #ifdef CONFIG_X86_64
2704         rdmsrl(MSR_FS_BASE, a);
2705         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2706         rdmsrl(MSR_GS_BASE, a);
2707         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2708 #else
2709         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2710         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2711 #endif
2712
2713         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2714
2715         native_store_idt(&dt);
2716         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
2717
2718         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2719         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2720         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2721         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2722         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2723         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2724         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2725
2726         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2727         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2728         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2729         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2730         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2731         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2732
2733         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2734                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2735                 host_pat = msr_low | ((u64) msr_high << 32);
2736                 vmcs_write64(HOST_IA32_PAT, host_pat);
2737         }
2738         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2739                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2740                 host_pat = msr_low | ((u64) msr_high << 32);
2741                 /* Write the default value follow host pat */
2742                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2743                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2744                 vmx->vcpu.arch.pat = host_pat;
2745         }
2746
2747         for (i = 0; i < NR_VMX_MSR; ++i) {
2748                 u32 index = vmx_msr_index[i];
2749                 u32 data_low, data_high;
2750                 int j = vmx->nmsrs;
2751
2752                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2753                         continue;
2754                 if (wrmsr_safe(index, data_low, data_high) < 0)
2755                         continue;
2756                 vmx->guest_msrs[j].index = i;
2757                 vmx->guest_msrs[j].data = 0;
2758                 vmx->guest_msrs[j].mask = -1ull;
2759                 ++vmx->nmsrs;
2760         }
2761
2762         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2763
2764         /* 22.2.1, 20.8.1 */
2765         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2766
2767         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2768         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2769         if (enable_ept)
2770                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2771         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2772
2773         kvm_write_tsc(&vmx->vcpu, 0);
2774
2775         return 0;
2776 }
2777
2778 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2779 {
2780         struct vcpu_vmx *vmx = to_vmx(vcpu);
2781         u64 msr;
2782         int ret;
2783
2784         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2785
2786         vmx->rmode.vm86_active = 0;
2787
2788         vmx->soft_vnmi_blocked = 0;
2789
2790         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2791         kvm_set_cr8(&vmx->vcpu, 0);
2792         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2793         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2794                 msr |= MSR_IA32_APICBASE_BSP;
2795         kvm_set_apic_base(&vmx->vcpu, msr);
2796
2797         ret = fx_init(&vmx->vcpu);
2798         if (ret != 0)
2799                 goto out;
2800
2801         seg_setup(VCPU_SREG_CS);
2802         /*
2803          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2804          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2805          */
2806         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2807                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2808                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2809         } else {
2810                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2811                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2812         }
2813
2814         seg_setup(VCPU_SREG_DS);
2815         seg_setup(VCPU_SREG_ES);
2816         seg_setup(VCPU_SREG_FS);
2817         seg_setup(VCPU_SREG_GS);
2818         seg_setup(VCPU_SREG_SS);
2819
2820         vmcs_write16(GUEST_TR_SELECTOR, 0);
2821         vmcs_writel(GUEST_TR_BASE, 0);
2822         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2823         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2824
2825         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2826         vmcs_writel(GUEST_LDTR_BASE, 0);
2827         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2828         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2829
2830         vmcs_write32(GUEST_SYSENTER_CS, 0);
2831         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2832         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2833
2834         vmcs_writel(GUEST_RFLAGS, 0x02);
2835         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2836                 kvm_rip_write(vcpu, 0xfff0);
2837         else
2838                 kvm_rip_write(vcpu, 0);
2839         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2840
2841         vmcs_writel(GUEST_DR7, 0x400);
2842
2843         vmcs_writel(GUEST_GDTR_BASE, 0);
2844         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2845
2846         vmcs_writel(GUEST_IDTR_BASE, 0);
2847         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2848
2849         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
2850         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2851         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2852
2853         /* Special registers */
2854         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2855
2856         setup_msrs(vmx);
2857
2858         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2859
2860         if (cpu_has_vmx_tpr_shadow()) {
2861                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2862                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2863                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2864                                      __pa(vmx->vcpu.arch.apic->regs));
2865                 vmcs_write32(TPR_THRESHOLD, 0);
2866         }
2867
2868         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2869                 vmcs_write64(APIC_ACCESS_ADDR,
2870                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2871
2872         if (vmx->vpid != 0)
2873                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2874
2875         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2876         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2877         vmx_set_cr4(&vmx->vcpu, 0);
2878         vmx_set_efer(&vmx->vcpu, 0);
2879         vmx_fpu_activate(&vmx->vcpu);
2880         update_exception_bitmap(&vmx->vcpu);
2881
2882         vpid_sync_context(vmx);
2883
2884         ret = 0;
2885
2886         /* HACK: Don't enable emulation on guest boot/reset */
2887         vmx->emulation_required = 0;
2888
2889 out:
2890         return ret;
2891 }
2892
2893 static void enable_irq_window(struct kvm_vcpu *vcpu)
2894 {
2895         u32 cpu_based_vm_exec_control;
2896
2897         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2898         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2899         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2900 }
2901
2902 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2903 {
2904         u32 cpu_based_vm_exec_control;
2905
2906         if (!cpu_has_virtual_nmis()) {
2907                 enable_irq_window(vcpu);
2908                 return;
2909         }
2910
2911         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
2912                 enable_irq_window(vcpu);
2913                 return;
2914         }
2915         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2916         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2917         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2918 }
2919
2920 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2921 {
2922         struct vcpu_vmx *vmx = to_vmx(vcpu);
2923         uint32_t intr;
2924         int irq = vcpu->arch.interrupt.nr;
2925
2926         trace_kvm_inj_virq(irq);
2927
2928         ++vcpu->stat.irq_injections;
2929         if (vmx->rmode.vm86_active) {
2930                 if (kvm_inject_realmode_interrupt(vcpu, irq) != EMULATE_DONE)
2931                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2932                 return;
2933         }
2934         intr = irq | INTR_INFO_VALID_MASK;
2935         if (vcpu->arch.interrupt.soft) {
2936                 intr |= INTR_TYPE_SOFT_INTR;
2937                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2938                              vmx->vcpu.arch.event_exit_inst_len);
2939         } else
2940                 intr |= INTR_TYPE_EXT_INTR;
2941         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2942         vmx_clear_hlt(vcpu);
2943 }
2944
2945 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2946 {
2947         struct vcpu_vmx *vmx = to_vmx(vcpu);
2948
2949         if (!cpu_has_virtual_nmis()) {
2950                 /*
2951                  * Tracking the NMI-blocked state in software is built upon
2952                  * finding the next open IRQ window. This, in turn, depends on
2953                  * well-behaving guests: They have to keep IRQs disabled at
2954                  * least as long as the NMI handler runs. Otherwise we may
2955                  * cause NMI nesting, maybe breaking the guest. But as this is
2956                  * highly unlikely, we can live with the residual risk.
2957                  */
2958                 vmx->soft_vnmi_blocked = 1;
2959                 vmx->vnmi_blocked_time = 0;
2960         }
2961
2962         ++vcpu->stat.nmi_injections;
2963         vmx->nmi_known_unmasked = false;
2964         if (vmx->rmode.vm86_active) {
2965                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR) != EMULATE_DONE)
2966                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2967                 return;
2968         }
2969         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2970                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2971         vmx_clear_hlt(vcpu);
2972 }
2973
2974 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2975 {
2976         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2977                 return 0;
2978
2979         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2980                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
2981                    | GUEST_INTR_STATE_NMI));
2982 }
2983
2984 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2985 {
2986         if (!cpu_has_virtual_nmis())
2987                 return to_vmx(vcpu)->soft_vnmi_blocked;
2988         if (to_vmx(vcpu)->nmi_known_unmasked)
2989                 return false;
2990         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
2991 }
2992
2993 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2994 {
2995         struct vcpu_vmx *vmx = to_vmx(vcpu);
2996
2997         if (!cpu_has_virtual_nmis()) {
2998                 if (vmx->soft_vnmi_blocked != masked) {
2999                         vmx->soft_vnmi_blocked = masked;
3000                         vmx->vnmi_blocked_time = 0;
3001                 }
3002         } else {
3003                 vmx->nmi_known_unmasked = !masked;
3004                 if (masked)
3005                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3006                                       GUEST_INTR_STATE_NMI);
3007                 else
3008                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3009                                         GUEST_INTR_STATE_NMI);
3010         }
3011 }
3012
3013 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
3014 {
3015         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
3016                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3017                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
3018 }
3019
3020 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
3021 {
3022         int ret;
3023         struct kvm_userspace_memory_region tss_mem = {
3024                 .slot = TSS_PRIVATE_MEMSLOT,
3025                 .guest_phys_addr = addr,
3026                 .memory_size = PAGE_SIZE * 3,
3027                 .flags = 0,
3028         };
3029
3030         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3031         if (ret)
3032                 return ret;
3033         kvm->arch.tss_addr = addr;
3034         if (!init_rmode_tss(kvm))
3035                 return  -ENOMEM;
3036
3037         return 0;
3038 }
3039
3040 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3041                                   int vec, u32 err_code)
3042 {
3043         /*
3044          * Instruction with address size override prefix opcode 0x67
3045          * Cause the #SS fault with 0 error code in VM86 mode.
3046          */
3047         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3048                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
3049                         return 1;
3050         /*
3051          * Forward all other exceptions that are valid in real mode.
3052          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3053          *        the required debugging infrastructure rework.
3054          */
3055         switch (vec) {
3056         case DB_VECTOR:
3057                 if (vcpu->guest_debug &
3058                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
3059                         return 0;
3060                 kvm_queue_exception(vcpu, vec);
3061                 return 1;
3062         case BP_VECTOR:
3063                 /*
3064                  * Update instruction length as we may reinject the exception
3065                  * from user space while in guest debugging mode.
3066                  */
3067                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3068                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3069                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3070                         return 0;
3071                 /* fall through */
3072         case DE_VECTOR:
3073         case OF_VECTOR:
3074         case BR_VECTOR:
3075         case UD_VECTOR:
3076         case DF_VECTOR:
3077         case SS_VECTOR:
3078         case GP_VECTOR:
3079         case MF_VECTOR:
3080                 kvm_queue_exception(vcpu, vec);
3081                 return 1;
3082         }
3083         return 0;
3084 }
3085
3086 /*
3087  * Trigger machine check on the host. We assume all the MSRs are already set up
3088  * by the CPU and that we still run on the same CPU as the MCE occurred on.
3089  * We pass a fake environment to the machine check handler because we want
3090  * the guest to be always treated like user space, no matter what context
3091  * it used internally.
3092  */
3093 static void kvm_machine_check(void)
3094 {
3095 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3096         struct pt_regs regs = {
3097                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3098                 .flags = X86_EFLAGS_IF,
3099         };
3100
3101         do_machine_check(&regs, 0);
3102 #endif
3103 }
3104
3105 static int handle_machine_check(struct kvm_vcpu *vcpu)
3106 {
3107         /* already handled by vcpu_run */
3108         return 1;
3109 }
3110
3111 static int handle_exception(struct kvm_vcpu *vcpu)
3112 {
3113         struct vcpu_vmx *vmx = to_vmx(vcpu);
3114         struct kvm_run *kvm_run = vcpu->run;
3115         u32 intr_info, ex_no, error_code;
3116         unsigned long cr2, rip, dr6;
3117         u32 vect_info;
3118         enum emulation_result er;
3119
3120         vect_info = vmx->idt_vectoring_info;
3121         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3122
3123         if (is_machine_check(intr_info))
3124                 return handle_machine_check(vcpu);
3125
3126         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3127             !is_page_fault(intr_info)) {
3128                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3129                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3130                 vcpu->run->internal.ndata = 2;
3131                 vcpu->run->internal.data[0] = vect_info;
3132                 vcpu->run->internal.data[1] = intr_info;
3133                 return 0;
3134         }
3135
3136         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3137                 return 1;  /* already handled by vmx_vcpu_run() */
3138
3139         if (is_no_device(intr_info)) {
3140                 vmx_fpu_activate(vcpu);
3141                 return 1;
3142         }
3143
3144         if (is_invalid_opcode(intr_info)) {
3145                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
3146                 if (er != EMULATE_DONE)
3147                         kvm_queue_exception(vcpu, UD_VECTOR);
3148                 return 1;
3149         }
3150
3151         error_code = 0;
3152         rip = kvm_rip_read(vcpu);
3153         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3154                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3155         if (is_page_fault(intr_info)) {
3156                 /* EPT won't cause page fault directly */
3157                 if (enable_ept)
3158                         BUG();
3159                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3160                 trace_kvm_page_fault(cr2, error_code);
3161
3162                 if (kvm_event_needs_reinjection(vcpu))
3163                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
3164                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
3165         }
3166
3167         if (vmx->rmode.vm86_active &&
3168             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3169                                                                 error_code)) {
3170                 if (vcpu->arch.halt_request) {
3171                         vcpu->arch.halt_request = 0;
3172                         return kvm_emulate_halt(vcpu);
3173                 }
3174                 return 1;
3175         }
3176
3177         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3178         switch (ex_no) {
3179         case DB_VECTOR:
3180                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3181                 if (!(vcpu->guest_debug &
3182                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3183                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3184                         kvm_queue_exception(vcpu, DB_VECTOR);
3185                         return 1;
3186                 }
3187                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3188                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3189                 /* fall through */
3190         case BP_VECTOR:
3191                 /*
3192                  * Update instruction length as we may reinject #BP from
3193                  * user space while in guest debugging mode. Reading it for
3194                  * #DB as well causes no harm, it is not used in that case.
3195                  */
3196                 vmx->vcpu.arch.event_exit_inst_len =
3197                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3198                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3199                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3200                 kvm_run->debug.arch.exception = ex_no;
3201                 break;
3202         default:
3203                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3204                 kvm_run->ex.exception = ex_no;
3205                 kvm_run->ex.error_code = error_code;
3206                 break;
3207         }
3208         return 0;
3209 }
3210
3211 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3212 {
3213         ++vcpu->stat.irq_exits;
3214         return 1;
3215 }
3216
3217 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3218 {
3219         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3220         return 0;
3221 }
3222
3223 static int handle_io(struct kvm_vcpu *vcpu)
3224 {
3225         unsigned long exit_qualification;
3226         int size, in, string;
3227         unsigned port;
3228
3229         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3230         string = (exit_qualification & 16) != 0;
3231         in = (exit_qualification & 8) != 0;
3232
3233         ++vcpu->stat.io_exits;
3234
3235         if (string || in)
3236                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3237
3238         port = exit_qualification >> 16;
3239         size = (exit_qualification & 7) + 1;
3240         skip_emulated_instruction(vcpu);
3241
3242         return kvm_fast_pio_out(vcpu, size, port);
3243 }
3244
3245 static void
3246 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3247 {
3248         /*
3249          * Patch in the VMCALL instruction:
3250          */
3251         hypercall[0] = 0x0f;
3252         hypercall[1] = 0x01;
3253         hypercall[2] = 0xc1;
3254 }
3255
3256 static int handle_cr(struct kvm_vcpu *vcpu)
3257 {
3258         unsigned long exit_qualification, val;
3259         int cr;
3260         int reg;
3261         int err;
3262
3263         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3264         cr = exit_qualification & 15;
3265         reg = (exit_qualification >> 8) & 15;
3266         switch ((exit_qualification >> 4) & 3) {
3267         case 0: /* mov to cr */
3268                 val = kvm_register_read(vcpu, reg);
3269                 trace_kvm_cr_write(cr, val);
3270                 switch (cr) {
3271                 case 0:
3272                         err = kvm_set_cr0(vcpu, val);
3273                         kvm_complete_insn_gp(vcpu, err);
3274                         return 1;
3275                 case 3:
3276                         err = kvm_set_cr3(vcpu, val);
3277                         kvm_complete_insn_gp(vcpu, err);
3278                         return 1;
3279                 case 4:
3280                         err = kvm_set_cr4(vcpu, val);
3281                         kvm_complete_insn_gp(vcpu, err);
3282                         return 1;
3283                 case 8: {
3284                                 u8 cr8_prev = kvm_get_cr8(vcpu);
3285                                 u8 cr8 = kvm_register_read(vcpu, reg);
3286                                 err = kvm_set_cr8(vcpu, cr8);
3287                                 kvm_complete_insn_gp(vcpu, err);
3288                                 if (irqchip_in_kernel(vcpu->kvm))
3289                                         return 1;
3290                                 if (cr8_prev <= cr8)
3291                                         return 1;
3292                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3293                                 return 0;
3294                         }
3295                 };
3296                 break;
3297         case 2: /* clts */
3298                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3299                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3300                 skip_emulated_instruction(vcpu);
3301                 vmx_fpu_activate(vcpu);
3302                 return 1;
3303         case 1: /*mov from cr*/
3304                 switch (cr) {
3305                 case 3:
3306                         val = kvm_read_cr3(vcpu);
3307                         kvm_register_write(vcpu, reg, val);
3308                         trace_kvm_cr_read(cr, val);
3309                         skip_emulated_instruction(vcpu);
3310                         return 1;
3311                 case 8:
3312                         val = kvm_get_cr8(vcpu);
3313                         kvm_register_write(vcpu, reg, val);
3314                         trace_kvm_cr_read(cr, val);
3315                         skip_emulated_instruction(vcpu);
3316                         return 1;
3317                 }
3318                 break;
3319         case 3: /* lmsw */
3320                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3321                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3322                 kvm_lmsw(vcpu, val);
3323
3324                 skip_emulated_instruction(vcpu);
3325                 return 1;
3326         default:
3327                 break;
3328         }
3329         vcpu->run->exit_reason = 0;
3330         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3331                (int)(exit_qualification >> 4) & 3, cr);
3332         return 0;
3333 }
3334
3335 static int handle_dr(struct kvm_vcpu *vcpu)
3336 {
3337         unsigned long exit_qualification;
3338         int dr, reg;
3339
3340         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3341         if (!kvm_require_cpl(vcpu, 0))
3342                 return 1;
3343         dr = vmcs_readl(GUEST_DR7);
3344         if (dr & DR7_GD) {
3345                 /*
3346                  * As the vm-exit takes precedence over the debug trap, we
3347                  * need to emulate the latter, either for the host or the
3348                  * guest debugging itself.
3349                  */
3350                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3351                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3352                         vcpu->run->debug.arch.dr7 = dr;
3353                         vcpu->run->debug.arch.pc =
3354                                 vmcs_readl(GUEST_CS_BASE) +
3355                                 vmcs_readl(GUEST_RIP);
3356                         vcpu->run->debug.arch.exception = DB_VECTOR;
3357                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3358                         return 0;
3359                 } else {
3360                         vcpu->arch.dr7 &= ~DR7_GD;
3361                         vcpu->arch.dr6 |= DR6_BD;
3362                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3363                         kvm_queue_exception(vcpu, DB_VECTOR);
3364                         return 1;
3365                 }
3366         }
3367
3368         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3369         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3370         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3371         if (exit_qualification & TYPE_MOV_FROM_DR) {
3372                 unsigned long val;
3373                 if (!kvm_get_dr(vcpu, dr, &val))
3374                         kvm_register_write(vcpu, reg, val);
3375         } else
3376                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3377         skip_emulated_instruction(vcpu);
3378         return 1;
3379 }
3380
3381 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3382 {
3383         vmcs_writel(GUEST_DR7, val);
3384 }
3385
3386 static int handle_cpuid(struct kvm_vcpu *vcpu)
3387 {
3388         kvm_emulate_cpuid(vcpu);
3389         return 1;
3390 }
3391
3392 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3393 {
3394         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3395         u64 data;
3396
3397         if (vmx_get_msr(vcpu, ecx, &data)) {
3398                 trace_kvm_msr_read_ex(ecx);
3399                 kvm_inject_gp(vcpu, 0);
3400                 return 1;
3401         }
3402
3403         trace_kvm_msr_read(ecx, data);
3404
3405         /* FIXME: handling of bits 32:63 of rax, rdx */
3406         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3407         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3408         skip_emulated_instruction(vcpu);
3409         return 1;
3410 }
3411
3412 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3413 {
3414         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3415         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3416                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3417
3418         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3419                 trace_kvm_msr_write_ex(ecx, data);
3420                 kvm_inject_gp(vcpu, 0);
3421                 return 1;
3422         }
3423
3424         trace_kvm_msr_write(ecx, data);
3425         skip_emulated_instruction(vcpu);
3426         return 1;
3427 }
3428
3429 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3430 {
3431         kvm_make_request(KVM_REQ_EVENT, vcpu);
3432         return 1;
3433 }
3434
3435 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3436 {
3437         u32 cpu_based_vm_exec_control;
3438
3439         /* clear pending irq */
3440         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3441         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3442         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3443
3444         kvm_make_request(KVM_REQ_EVENT, vcpu);
3445
3446         ++vcpu->stat.irq_window_exits;
3447
3448         /*
3449          * If the user space waits to inject interrupts, exit as soon as
3450          * possible
3451          */
3452         if (!irqchip_in_kernel(vcpu->kvm) &&
3453             vcpu->run->request_interrupt_window &&
3454             !kvm_cpu_has_interrupt(vcpu)) {
3455                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3456                 return 0;
3457         }
3458         return 1;
3459 }
3460
3461 static int handle_halt(struct kvm_vcpu *vcpu)
3462 {
3463         skip_emulated_instruction(vcpu);
3464         return kvm_emulate_halt(vcpu);
3465 }
3466
3467 static int handle_vmcall(struct kvm_vcpu *vcpu)
3468 {
3469         skip_emulated_instruction(vcpu);
3470         kvm_emulate_hypercall(vcpu);
3471         return 1;
3472 }
3473
3474 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3475 {
3476         kvm_queue_exception(vcpu, UD_VECTOR);
3477         return 1;
3478 }
3479
3480 static int handle_invd(struct kvm_vcpu *vcpu)
3481 {
3482         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3483 }
3484
3485 static int handle_invlpg(struct kvm_vcpu *vcpu)
3486 {
3487         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3488
3489         kvm_mmu_invlpg(vcpu, exit_qualification);
3490         skip_emulated_instruction(vcpu);
3491         return 1;
3492 }
3493
3494 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3495 {
3496         skip_emulated_instruction(vcpu);
3497         kvm_emulate_wbinvd(vcpu);
3498         return 1;
3499 }
3500
3501 static int handle_xsetbv(struct kvm_vcpu *vcpu)
3502 {
3503         u64 new_bv = kvm_read_edx_eax(vcpu);
3504         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3505
3506         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3507                 skip_emulated_instruction(vcpu);
3508         return 1;
3509 }
3510
3511 static int handle_apic_access(struct kvm_vcpu *vcpu)
3512 {
3513         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3514 }
3515
3516 static int handle_task_switch(struct kvm_vcpu *vcpu)
3517 {
3518         struct vcpu_vmx *vmx = to_vmx(vcpu);
3519         unsigned long exit_qualification;
3520         bool has_error_code = false;
3521         u32 error_code = 0;
3522         u16 tss_selector;
3523         int reason, type, idt_v;
3524
3525         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3526         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3527
3528         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3529
3530         reason = (u32)exit_qualification >> 30;
3531         if (reason == TASK_SWITCH_GATE && idt_v) {
3532                 switch (type) {
3533                 case INTR_TYPE_NMI_INTR:
3534                         vcpu->arch.nmi_injected = false;
3535                         if (cpu_has_virtual_nmis()) {
3536                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3537                                               GUEST_INTR_STATE_NMI);
3538                                 vmx->nmi_known_unmasked = false;
3539                         }
3540                         break;
3541                 case INTR_TYPE_EXT_INTR:
3542                 case INTR_TYPE_SOFT_INTR:
3543                         kvm_clear_interrupt_queue(vcpu);
3544                         break;
3545                 case INTR_TYPE_HARD_EXCEPTION:
3546                         if (vmx->idt_vectoring_info &
3547                             VECTORING_INFO_DELIVER_CODE_MASK) {
3548                                 has_error_code = true;
3549                                 error_code =
3550                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
3551                         }
3552                         /* fall through */
3553                 case INTR_TYPE_SOFT_EXCEPTION:
3554                         kvm_clear_exception_queue(vcpu);
3555                         break;
3556                 default:
3557                         break;
3558                 }
3559         }
3560         tss_selector = exit_qualification;
3561
3562         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3563                        type != INTR_TYPE_EXT_INTR &&
3564                        type != INTR_TYPE_NMI_INTR))
3565                 skip_emulated_instruction(vcpu);
3566
3567         if (kvm_task_switch(vcpu, tss_selector, reason,
3568                                 has_error_code, error_code) == EMULATE_FAIL) {
3569                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3570                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3571                 vcpu->run->internal.ndata = 0;
3572                 return 0;
3573         }
3574
3575         /* clear all local breakpoint enable flags */
3576         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3577
3578         /*
3579          * TODO: What about debug traps on tss switch?
3580          *       Are we supposed to inject them and update dr6?
3581          */
3582
3583         return 1;
3584 }
3585
3586 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3587 {
3588         unsigned long exit_qualification;
3589         gpa_t gpa;
3590         int gla_validity;
3591
3592         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3593
3594         if (exit_qualification & (1 << 6)) {
3595                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3596                 return -EINVAL;
3597         }
3598
3599         gla_validity = (exit_qualification >> 7) & 0x3;
3600         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3601                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3602                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3603                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3604                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3605                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3606                         (long unsigned int)exit_qualification);
3607                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3608                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3609                 return 0;
3610         }
3611
3612         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3613         trace_kvm_page_fault(gpa, exit_qualification);
3614         return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
3615 }
3616
3617 static u64 ept_rsvd_mask(u64 spte, int level)
3618 {
3619         int i;
3620         u64 mask = 0;
3621
3622         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3623                 mask |= (1ULL << i);
3624
3625         if (level > 2)
3626                 /* bits 7:3 reserved */
3627                 mask |= 0xf8;
3628         else if (level == 2) {
3629                 if (spte & (1ULL << 7))
3630                         /* 2MB ref, bits 20:12 reserved */
3631                         mask |= 0x1ff000;
3632                 else
3633                         /* bits 6:3 reserved */
3634                         mask |= 0x78;
3635         }
3636
3637         return mask;
3638 }
3639
3640 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3641                                        int level)
3642 {
3643         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3644
3645         /* 010b (write-only) */
3646         WARN_ON((spte & 0x7) == 0x2);
3647
3648         /* 110b (write/execute) */
3649         WARN_ON((spte & 0x7) == 0x6);
3650
3651         /* 100b (execute-only) and value not supported by logical processor */
3652         if (!cpu_has_vmx_ept_execute_only())
3653                 WARN_ON((spte & 0x7) == 0x4);
3654
3655         /* not 000b */
3656         if ((spte & 0x7)) {
3657                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3658
3659                 if (rsvd_bits != 0) {
3660                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3661                                          __func__, rsvd_bits);
3662                         WARN_ON(1);
3663                 }
3664
3665                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3666                         u64 ept_mem_type = (spte & 0x38) >> 3;
3667
3668                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3669                             ept_mem_type == 7) {
3670                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3671                                                 __func__, ept_mem_type);
3672                                 WARN_ON(1);
3673                         }
3674                 }
3675         }
3676 }
3677
3678 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3679 {
3680         u64 sptes[4];
3681         int nr_sptes, i;
3682         gpa_t gpa;
3683
3684         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3685
3686         printk(KERN_ERR "EPT: Misconfiguration.\n");
3687         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3688
3689         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3690
3691         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3692                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3693
3694         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3695         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3696
3697         return 0;
3698 }
3699
3700 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3701 {
3702         u32 cpu_based_vm_exec_control;
3703
3704         /* clear pending NMI */
3705         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3706         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3707         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3708         ++vcpu->stat.nmi_window_exits;
3709         kvm_make_request(KVM_REQ_EVENT, vcpu);
3710
3711         return 1;
3712 }
3713
3714 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3715 {
3716         struct vcpu_vmx *vmx = to_vmx(vcpu);
3717         enum emulation_result err = EMULATE_DONE;
3718         int ret = 1;
3719         u32 cpu_exec_ctrl;
3720         bool intr_window_requested;
3721
3722         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3723         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
3724
3725         while (!guest_state_valid(vcpu)) {
3726                 if (intr_window_requested
3727                     && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
3728                         return handle_interrupt_window(&vmx->vcpu);
3729
3730                 err = emulate_instruction(vcpu, 0);
3731
3732                 if (err == EMULATE_DO_MMIO) {
3733                         ret = 0;
3734                         goto out;
3735                 }
3736
3737                 if (err != EMULATE_DONE)
3738                         return 0;
3739
3740                 if (signal_pending(current))
3741                         goto out;
3742                 if (need_resched())
3743                         schedule();
3744         }
3745
3746         vmx->emulation_required = 0;
3747 out:
3748         return ret;
3749 }
3750
3751 /*
3752  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3753  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3754  */
3755 static int handle_pause(struct kvm_vcpu *vcpu)
3756 {
3757         skip_emulated_instruction(vcpu);
3758         kvm_vcpu_on_spin(vcpu);
3759
3760         return 1;
3761 }
3762
3763 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3764 {
3765         kvm_queue_exception(vcpu, UD_VECTOR);
3766         return 1;
3767 }
3768
3769 /*
3770  * The exit handlers return 1 if the exit was handled fully and guest execution
3771  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3772  * to be done to userspace and return 0.
3773  */
3774 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3775         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3776         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3777         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3778         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3779         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3780         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3781         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3782         [EXIT_REASON_CPUID]                   = handle_cpuid,
3783         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3784         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3785         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3786         [EXIT_REASON_HLT]                     = handle_halt,
3787         [EXIT_REASON_INVD]                    = handle_invd,
3788         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3789         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3790         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3791         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3792         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3793         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3794         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3795         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3796         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3797         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3798         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3799         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3800         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3801         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3802         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
3803         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3804         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3805         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3806         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
3807         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
3808         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
3809         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
3810 };
3811
3812 static const int kvm_vmx_max_exit_handlers =
3813         ARRAY_SIZE(kvm_vmx_exit_handlers);
3814
3815 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3816 {
3817         *info1 = vmcs_readl(EXIT_QUALIFICATION);
3818         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
3819 }
3820
3821 /*
3822  * The guest has exited.  See if we can fix it or if we need userspace
3823  * assistance.
3824  */
3825 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3826 {
3827         struct vcpu_vmx *vmx = to_vmx(vcpu);
3828         u32 exit_reason = vmx->exit_reason;
3829         u32 vectoring_info = vmx->idt_vectoring_info;
3830
3831         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
3832
3833         /* If guest state is invalid, start emulating */
3834         if (vmx->emulation_required && emulate_invalid_guest_state)
3835                 return handle_invalid_guest_state(vcpu);
3836
3837         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3838                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3839                 vcpu->run->fail_entry.hardware_entry_failure_reason
3840                         = exit_reason;
3841                 return 0;
3842         }
3843
3844         if (unlikely(vmx->fail)) {
3845                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3846                 vcpu->run->fail_entry.hardware_entry_failure_reason
3847                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3848                 return 0;
3849         }
3850
3851         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3852                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3853                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3854                         exit_reason != EXIT_REASON_TASK_SWITCH))
3855                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3856                        "(0x%x) and exit reason is 0x%x\n",
3857                        __func__, vectoring_info, exit_reason);
3858
3859         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3860                 if (vmx_interrupt_allowed(vcpu)) {
3861                         vmx->soft_vnmi_blocked = 0;
3862                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3863                            vcpu->arch.nmi_pending) {
3864                         /*
3865                          * This CPU don't support us in finding the end of an
3866                          * NMI-blocked window if the guest runs with IRQs
3867                          * disabled. So we pull the trigger after 1 s of
3868                          * futile waiting, but inform the user about this.
3869                          */
3870                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3871                                "state on VCPU %d after 1 s timeout\n",
3872                                __func__, vcpu->vcpu_id);
3873                         vmx->soft_vnmi_blocked = 0;
3874                 }
3875         }
3876
3877         if (exit_reason < kvm_vmx_max_exit_handlers
3878             && kvm_vmx_exit_handlers[exit_reason])
3879                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3880         else {
3881                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3882                 vcpu->run->hw.hardware_exit_reason = exit_reason;
3883         }
3884         return 0;
3885 }
3886
3887 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3888 {
3889         if (irr == -1 || tpr < irr) {
3890                 vmcs_write32(TPR_THRESHOLD, 0);
3891                 return;
3892         }
3893
3894         vmcs_write32(TPR_THRESHOLD, irr);
3895 }
3896
3897 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
3898 {
3899         u32 exit_intr_info;
3900
3901         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
3902               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
3903                 return;
3904
3905         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3906         exit_intr_info = vmx->exit_intr_info;
3907
3908         /* Handle machine checks before interrupts are enabled */
3909         if (is_machine_check(exit_intr_info))
3910                 kvm_machine_check();
3911
3912         /* We need to handle NMIs before interrupts are enabled */
3913         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3914             (exit_intr_info & INTR_INFO_VALID_MASK)) {
3915                 kvm_before_handle_nmi(&vmx->vcpu);
3916                 asm("int $2");
3917                 kvm_after_handle_nmi(&vmx->vcpu);
3918         }
3919 }
3920
3921 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
3922 {
3923         u32 exit_intr_info;
3924         bool unblock_nmi;
3925         u8 vector;
3926         bool idtv_info_valid;
3927
3928         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3929
3930         if (cpu_has_virtual_nmis()) {
3931                 if (vmx->nmi_known_unmasked)
3932                         return;
3933                 /*
3934                  * Can't use vmx->exit_intr_info since we're not sure what
3935                  * the exit reason is.
3936                  */
3937                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3938                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3939                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3940                 /*
3941                  * SDM 3: 27.7.1.2 (September 2008)
3942                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3943                  * a guest IRET fault.
3944                  * SDM 3: 23.2.2 (September 2008)
3945                  * Bit 12 is undefined in any of the following cases:
3946                  *  If the VM exit sets the valid bit in the IDT-vectoring
3947                  *   information field.
3948                  *  If the VM exit is due to a double fault.
3949                  */
3950                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3951                     vector != DF_VECTOR && !idtv_info_valid)
3952                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3953                                       GUEST_INTR_STATE_NMI);
3954                 else
3955                         vmx->nmi_known_unmasked =
3956                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
3957                                   & GUEST_INTR_STATE_NMI);
3958         } else if (unlikely(vmx->soft_vnmi_blocked))
3959                 vmx->vnmi_blocked_time +=
3960                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3961 }
3962
3963 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
3964                                       u32 idt_vectoring_info,
3965                                       int instr_len_field,
3966                                       int error_code_field)
3967 {
3968         u8 vector;
3969         int type;
3970         bool idtv_info_valid;
3971
3972         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3973
3974         vmx->vcpu.arch.nmi_injected = false;
3975         kvm_clear_exception_queue(&vmx->vcpu);
3976         kvm_clear_interrupt_queue(&vmx->vcpu);
3977
3978         if (!idtv_info_valid)
3979                 return;
3980
3981         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
3982
3983         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3984         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3985
3986         switch (type) {
3987         case INTR_TYPE_NMI_INTR:
3988                 vmx->vcpu.arch.nmi_injected = true;
3989                 /*
3990                  * SDM 3: 27.7.1.2 (September 2008)
3991                  * Clear bit "block by NMI" before VM entry if a NMI
3992                  * delivery faulted.
3993                  */
3994                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3995                                 GUEST_INTR_STATE_NMI);
3996                 vmx->nmi_known_unmasked = true;
3997                 break;
3998         case INTR_TYPE_SOFT_EXCEPTION:
3999                 vmx->vcpu.arch.event_exit_inst_len =
4000                         vmcs_read32(instr_len_field);
4001                 /* fall through */
4002         case INTR_TYPE_HARD_EXCEPTION:
4003                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
4004                         u32 err = vmcs_read32(error_code_field);
4005                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
4006                 } else
4007                         kvm_queue_exception(&vmx->vcpu, vector);
4008                 break;
4009         case INTR_TYPE_SOFT_INTR:
4010                 vmx->vcpu.arch.event_exit_inst_len =
4011                         vmcs_read32(instr_len_field);
4012                 /* fall through */
4013         case INTR_TYPE_EXT_INTR:
4014                 kvm_queue_interrupt(&vmx->vcpu, vector,
4015                         type == INTR_TYPE_SOFT_INTR);
4016                 break;
4017         default:
4018                 break;
4019         }
4020 }
4021
4022 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
4023 {
4024         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
4025                                   VM_EXIT_INSTRUCTION_LEN,
4026                                   IDT_VECTORING_ERROR_CODE);
4027 }
4028
4029 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
4030 {
4031         __vmx_complete_interrupts(to_vmx(vcpu),
4032                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
4033                                   VM_ENTRY_INSTRUCTION_LEN,
4034                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
4035
4036         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
4037 }
4038
4039 #ifdef CONFIG_X86_64
4040 #define R "r"
4041 #define Q "q"
4042 #else
4043 #define R "e"
4044 #define Q "l"
4045 #endif
4046
4047 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
4048 {
4049         struct vcpu_vmx *vmx = to_vmx(vcpu);
4050
4051         /* Record the guest's net vcpu time for enforced NMI injections. */
4052         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
4053                 vmx->entry_time = ktime_get();
4054
4055         /* Don't enter VMX if guest state is invalid, let the exit handler
4056            start emulation until we arrive back to a valid state */
4057         if (vmx->emulation_required && emulate_invalid_guest_state)
4058                 return;
4059
4060         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
4061                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
4062         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
4063                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
4064
4065         /* When single-stepping over STI and MOV SS, we must clear the
4066          * corresponding interruptibility bits in the guest state. Otherwise
4067          * vmentry fails as it then expects bit 14 (BS) in pending debug
4068          * exceptions being set, but that's not correct for the guest debugging
4069          * case. */
4070         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
4071                 vmx_set_interrupt_shadow(vcpu, 0);
4072
4073         asm(
4074                 /* Store host registers */
4075                 "push %%"R"dx; push %%"R"bp;"
4076                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
4077                 "push %%"R"cx \n\t"
4078                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
4079                 "je 1f \n\t"
4080                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4081                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
4082                 "1: \n\t"
4083                 /* Reload cr2 if changed */
4084                 "mov %c[cr2](%0), %%"R"ax \n\t"
4085                 "mov %%cr2, %%"R"dx \n\t"
4086                 "cmp %%"R"ax, %%"R"dx \n\t"
4087                 "je 2f \n\t"
4088                 "mov %%"R"ax, %%cr2 \n\t"
4089                 "2: \n\t"
4090                 /* Check if vmlaunch of vmresume is needed */
4091                 "cmpl $0, %c[launched](%0) \n\t"
4092                 /* Load guest registers.  Don't clobber flags. */
4093                 "mov %c[rax](%0), %%"R"ax \n\t"
4094                 "mov %c[rbx](%0), %%"R"bx \n\t"
4095                 "mov %c[rdx](%0), %%"R"dx \n\t"
4096                 "mov %c[rsi](%0), %%"R"si \n\t"
4097                 "mov %c[rdi](%0), %%"R"di \n\t"
4098                 "mov %c[rbp](%0), %%"R"bp \n\t"
4099 #ifdef CONFIG_X86_64
4100                 "mov %c[r8](%0),  %%r8  \n\t"
4101                 "mov %c[r9](%0),  %%r9  \n\t"
4102                 "mov %c[r10](%0), %%r10 \n\t"
4103                 "mov %c[r11](%0), %%r11 \n\t"
4104                 "mov %c[r12](%0), %%r12 \n\t"
4105                 "mov %c[r13](%0), %%r13 \n\t"
4106                 "mov %c[r14](%0), %%r14 \n\t"
4107                 "mov %c[r15](%0), %%r15 \n\t"
4108 #endif
4109                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
4110
4111                 /* Enter guest mode */
4112                 "jne .Llaunched \n\t"
4113                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
4114                 "jmp .Lkvm_vmx_return \n\t"
4115                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
4116                 ".Lkvm_vmx_return: "
4117                 /* Save guest registers, load host registers, keep flags */
4118                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
4119                 "pop %0 \n\t"
4120                 "mov %%"R"ax, %c[rax](%0) \n\t"
4121                 "mov %%"R"bx, %c[rbx](%0) \n\t"
4122                 "pop"Q" %c[rcx](%0) \n\t"
4123                 "mov %%"R"dx, %c[rdx](%0) \n\t"
4124                 "mov %%"R"si, %c[rsi](%0) \n\t"
4125                 "mov %%"R"di, %c[rdi](%0) \n\t"
4126                 "mov %%"R"bp, %c[rbp](%0) \n\t"
4127 #ifdef CONFIG_X86_64
4128                 "mov %%r8,  %c[r8](%0) \n\t"
4129                 "mov %%r9,  %c[r9](%0) \n\t"
4130                 "mov %%r10, %c[r10](%0) \n\t"
4131                 "mov %%r11, %c[r11](%0) \n\t"
4132                 "mov %%r12, %c[r12](%0) \n\t"
4133                 "mov %%r13, %c[r13](%0) \n\t"
4134                 "mov %%r14, %c[r14](%0) \n\t"
4135                 "mov %%r15, %c[r15](%0) \n\t"
4136 #endif
4137                 "mov %%cr2, %%"R"ax   \n\t"
4138                 "mov %%"R"ax, %c[cr2](%0) \n\t"
4139
4140                 "pop  %%"R"bp; pop  %%"R"dx \n\t"
4141                 "setbe %c[fail](%0) \n\t"
4142               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4143                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4144                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
4145                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
4146                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4147                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4148                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4149                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4150                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4151                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4152                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
4153 #ifdef CONFIG_X86_64
4154                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4155                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4156                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4157                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4158                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4159                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4160                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4161                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
4162 #endif
4163                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
4164                 [wordsize]"i"(sizeof(ulong))
4165               : "cc", "memory"
4166                 , R"ax", R"bx", R"di", R"si"
4167 #ifdef CONFIG_X86_64
4168                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4169 #endif
4170               );
4171
4172         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4173                                   | (1 << VCPU_EXREG_RFLAGS)
4174                                   | (1 << VCPU_EXREG_CPL)
4175                                   | (1 << VCPU_EXREG_PDPTR)
4176                                   | (1 << VCPU_EXREG_CR3));
4177         vcpu->arch.regs_dirty = 0;
4178
4179         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4180
4181         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
4182         vmx->launched = 1;
4183
4184         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
4185
4186         vmx_complete_atomic_exit(vmx);
4187         vmx_recover_nmi_blocking(vmx);
4188         vmx_complete_interrupts(vmx);
4189 }
4190
4191 #undef R
4192 #undef Q
4193
4194 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4195 {
4196         struct vcpu_vmx *vmx = to_vmx(vcpu);
4197
4198         if (vmx->vmcs) {
4199                 vcpu_clear(vmx);
4200                 free_vmcs(vmx->vmcs);
4201                 vmx->vmcs = NULL;
4202         }
4203 }
4204
4205 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4206 {
4207         struct vcpu_vmx *vmx = to_vmx(vcpu);
4208
4209         free_vpid(vmx);
4210         vmx_free_vmcs(vcpu);
4211         kfree(vmx->guest_msrs);
4212         kvm_vcpu_uninit(vcpu);
4213         kmem_cache_free(kvm_vcpu_cache, vmx);
4214 }
4215
4216 static inline void vmcs_init(struct vmcs *vmcs)
4217 {
4218         u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4219
4220         if (!vmm_exclusive)
4221                 kvm_cpu_vmxon(phys_addr);
4222
4223         vmcs_clear(vmcs);
4224
4225         if (!vmm_exclusive)
4226                 kvm_cpu_vmxoff();
4227 }
4228
4229 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4230 {
4231         int err;
4232         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4233         int cpu;
4234
4235         if (!vmx)
4236                 return ERR_PTR(-ENOMEM);
4237
4238         allocate_vpid(vmx);
4239
4240         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4241         if (err)
4242                 goto free_vcpu;
4243
4244         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4245         if (!vmx->guest_msrs) {
4246                 err = -ENOMEM;
4247                 goto uninit_vcpu;
4248         }
4249
4250         vmx->vmcs = alloc_vmcs();
4251         if (!vmx->vmcs)
4252                 goto free_msrs;
4253
4254         vmcs_init(vmx->vmcs);
4255
4256         cpu = get_cpu();
4257         vmx_vcpu_load(&vmx->vcpu, cpu);
4258         vmx->vcpu.cpu = cpu;
4259         err = vmx_vcpu_setup(vmx);
4260         vmx_vcpu_put(&vmx->vcpu);
4261         put_cpu();
4262         if (err)
4263                 goto free_vmcs;
4264         if (vm_need_virtualize_apic_accesses(kvm))
4265                 if (alloc_apic_access_page(kvm) != 0)
4266                         goto free_vmcs;
4267
4268         if (enable_ept) {
4269                 if (!kvm->arch.ept_identity_map_addr)
4270                         kvm->arch.ept_identity_map_addr =
4271                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4272                 err = -ENOMEM;
4273                 if (alloc_identity_pagetable(kvm) != 0)
4274                         goto free_vmcs;
4275                 if (!init_rmode_identity_map(kvm))
4276                         goto free_vmcs;
4277         }
4278
4279         return &vmx->vcpu;
4280
4281 free_vmcs:
4282         free_vmcs(vmx->vmcs);
4283 free_msrs:
4284         kfree(vmx->guest_msrs);
4285 uninit_vcpu:
4286         kvm_vcpu_uninit(&vmx->vcpu);
4287 free_vcpu:
4288         free_vpid(vmx);
4289         kmem_cache_free(kvm_vcpu_cache, vmx);
4290         return ERR_PTR(err);
4291 }
4292
4293 static void __init vmx_check_processor_compat(void *rtn)
4294 {
4295         struct vmcs_config vmcs_conf;
4296
4297         *(int *)rtn = 0;
4298         if (setup_vmcs_config(&vmcs_conf) < 0)
4299                 *(int *)rtn = -EIO;
4300         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4301                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4302                                 smp_processor_id());
4303                 *(int *)rtn = -EIO;
4304         }
4305 }
4306
4307 static int get_ept_level(void)
4308 {
4309         return VMX_EPT_DEFAULT_GAW + 1;
4310 }
4311
4312 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4313 {
4314         u64 ret;
4315
4316         /* For VT-d and EPT combination
4317          * 1. MMIO: always map as UC
4318          * 2. EPT with VT-d:
4319          *   a. VT-d without snooping control feature: can't guarantee the
4320          *      result, try to trust guest.
4321          *   b. VT-d with snooping control feature: snooping control feature of
4322          *      VT-d engine can guarantee the cache correctness. Just set it
4323          *      to WB to keep consistent with host. So the same as item 3.
4324          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4325          *    consistent with host MTRR
4326          */
4327         if (is_mmio)
4328                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4329         else if (vcpu->kvm->arch.iommu_domain &&
4330                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4331                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4332                       VMX_EPT_MT_EPTE_SHIFT;
4333         else
4334                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4335                         | VMX_EPT_IPAT_BIT;
4336
4337         return ret;
4338 }
4339
4340 #define _ER(x) { EXIT_REASON_##x, #x }
4341
4342 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4343         _ER(EXCEPTION_NMI),
4344         _ER(EXTERNAL_INTERRUPT),
4345         _ER(TRIPLE_FAULT),
4346         _ER(PENDING_INTERRUPT),
4347         _ER(NMI_WINDOW),
4348         _ER(TASK_SWITCH),
4349         _ER(CPUID),
4350         _ER(HLT),
4351         _ER(INVLPG),
4352         _ER(RDPMC),
4353         _ER(RDTSC),
4354         _ER(VMCALL),
4355         _ER(VMCLEAR),
4356         _ER(VMLAUNCH),
4357         _ER(VMPTRLD),
4358         _ER(VMPTRST),
4359         _ER(VMREAD),
4360         _ER(VMRESUME),
4361         _ER(VMWRITE),
4362         _ER(VMOFF),
4363         _ER(VMON),
4364         _ER(CR_ACCESS),
4365         _ER(DR_ACCESS),
4366         _ER(IO_INSTRUCTION),
4367         _ER(MSR_READ),
4368         _ER(MSR_WRITE),
4369         _ER(MWAIT_INSTRUCTION),
4370         _ER(MONITOR_INSTRUCTION),
4371         _ER(PAUSE_INSTRUCTION),
4372         _ER(MCE_DURING_VMENTRY),
4373         _ER(TPR_BELOW_THRESHOLD),
4374         _ER(APIC_ACCESS),
4375         _ER(EPT_VIOLATION),
4376         _ER(EPT_MISCONFIG),
4377         _ER(WBINVD),
4378         { -1, NULL }
4379 };
4380
4381 #undef _ER
4382
4383 static int vmx_get_lpage_level(void)
4384 {
4385         if (enable_ept && !cpu_has_vmx_ept_1g_page())
4386                 return PT_DIRECTORY_LEVEL;
4387         else
4388                 /* For shadow and EPT supported 1GB page */
4389                 return PT_PDPE_LEVEL;
4390 }
4391
4392 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4393 {
4394         struct kvm_cpuid_entry2 *best;
4395         struct vcpu_vmx *vmx = to_vmx(vcpu);
4396         u32 exec_control;
4397
4398         vmx->rdtscp_enabled = false;
4399         if (vmx_rdtscp_supported()) {
4400                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4401                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4402                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4403                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4404                                 vmx->rdtscp_enabled = true;
4405                         else {
4406                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4407                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4408                                                 exec_control);
4409                         }
4410                 }
4411         }
4412 }
4413
4414 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4415 {
4416 }
4417
4418 static struct kvm_x86_ops vmx_x86_ops = {
4419         .cpu_has_kvm_support = cpu_has_kvm_support,
4420         .disabled_by_bios = vmx_disabled_by_bios,
4421         .hardware_setup = hardware_setup,
4422         .hardware_unsetup = hardware_unsetup,
4423         .check_processor_compatibility = vmx_check_processor_compat,
4424         .hardware_enable = hardware_enable,
4425         .hardware_disable = hardware_disable,
4426         .cpu_has_accelerated_tpr = report_flexpriority,
4427
4428         .vcpu_create = vmx_create_vcpu,
4429         .vcpu_free = vmx_free_vcpu,
4430         .vcpu_reset = vmx_vcpu_reset,
4431
4432         .prepare_guest_switch = vmx_save_host_state,
4433         .vcpu_load = vmx_vcpu_load,
4434         .vcpu_put = vmx_vcpu_put,
4435
4436         .set_guest_debug = set_guest_debug,
4437         .get_msr = vmx_get_msr,
4438         .set_msr = vmx_set_msr,
4439         .get_segment_base = vmx_get_segment_base,
4440         .get_segment = vmx_get_segment,
4441         .set_segment = vmx_set_segment,
4442         .get_cpl = vmx_get_cpl,
4443         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4444         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4445         .decache_cr3 = vmx_decache_cr3,
4446         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4447         .set_cr0 = vmx_set_cr0,
4448         .set_cr3 = vmx_set_cr3,
4449         .set_cr4 = vmx_set_cr4,
4450         .set_efer = vmx_set_efer,
4451         .get_idt = vmx_get_idt,
4452         .set_idt = vmx_set_idt,
4453         .get_gdt = vmx_get_gdt,
4454         .set_gdt = vmx_set_gdt,
4455         .set_dr7 = vmx_set_dr7,
4456         .cache_reg = vmx_cache_reg,
4457         .get_rflags = vmx_get_rflags,
4458         .set_rflags = vmx_set_rflags,
4459         .fpu_activate = vmx_fpu_activate,
4460         .fpu_deactivate = vmx_fpu_deactivate,
4461
4462         .tlb_flush = vmx_flush_tlb,
4463
4464         .run = vmx_vcpu_run,
4465         .handle_exit = vmx_handle_exit,
4466         .skip_emulated_instruction = skip_emulated_instruction,
4467         .set_interrupt_shadow = vmx_set_interrupt_shadow,
4468         .get_interrupt_shadow = vmx_get_interrupt_shadow,
4469         .patch_hypercall = vmx_patch_hypercall,
4470         .set_irq = vmx_inject_irq,
4471         .set_nmi = vmx_inject_nmi,
4472         .queue_exception = vmx_queue_exception,
4473         .cancel_injection = vmx_cancel_injection,
4474         .interrupt_allowed = vmx_interrupt_allowed,
4475         .nmi_allowed = vmx_nmi_allowed,
4476         .get_nmi_mask = vmx_get_nmi_mask,
4477         .set_nmi_mask = vmx_set_nmi_mask,
4478         .enable_nmi_window = enable_nmi_window,
4479         .enable_irq_window = enable_irq_window,
4480         .update_cr8_intercept = update_cr8_intercept,
4481
4482         .set_tss_addr = vmx_set_tss_addr,
4483         .get_tdp_level = get_ept_level,
4484         .get_mt_mask = vmx_get_mt_mask,
4485
4486         .get_exit_info = vmx_get_exit_info,
4487         .exit_reasons_str = vmx_exit_reasons_str,
4488
4489         .get_lpage_level = vmx_get_lpage_level,
4490
4491         .cpuid_update = vmx_cpuid_update,
4492
4493         .rdtscp_supported = vmx_rdtscp_supported,
4494
4495         .set_supported_cpuid = vmx_set_supported_cpuid,
4496
4497         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
4498
4499         .write_tsc_offset = vmx_write_tsc_offset,
4500         .adjust_tsc_offset = vmx_adjust_tsc_offset,
4501
4502         .set_tdp_cr3 = vmx_set_cr3,
4503 };
4504
4505 static int __init vmx_init(void)
4506 {
4507         int r, i;
4508
4509         rdmsrl_safe(MSR_EFER, &host_efer);
4510
4511         for (i = 0; i < NR_VMX_MSR; ++i)
4512                 kvm_define_shared_msr(i, vmx_msr_index[i]);
4513
4514         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4515         if (!vmx_io_bitmap_a)
4516                 return -ENOMEM;
4517
4518         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4519         if (!vmx_io_bitmap_b) {
4520                 r = -ENOMEM;
4521                 goto out;
4522         }
4523
4524         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4525         if (!vmx_msr_bitmap_legacy) {
4526                 r = -ENOMEM;
4527                 goto out1;
4528         }
4529
4530         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4531         if (!vmx_msr_bitmap_longmode) {
4532                 r = -ENOMEM;
4533                 goto out2;
4534         }
4535
4536         /*
4537          * Allow direct access to the PC debug port (it is often used for I/O
4538          * delays, but the vmexits simply slow things down).
4539          */
4540         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4541         clear_bit(0x80, vmx_io_bitmap_a);
4542
4543         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4544
4545         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4546         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4547
4548         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4549
4550         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4551                      __alignof__(struct vcpu_vmx), THIS_MODULE);
4552         if (r)
4553                 goto out3;
4554
4555         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4556         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4557         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4558         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4559         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4560         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4561
4562         if (enable_ept) {
4563                 bypass_guest_pf = 0;
4564                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4565                                 VMX_EPT_EXECUTABLE_MASK);
4566                 kvm_enable_tdp();
4567         } else
4568                 kvm_disable_tdp();
4569
4570         if (bypass_guest_pf)
4571                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4572
4573         return 0;
4574
4575 out3:
4576         free_page((unsigned long)vmx_msr_bitmap_longmode);
4577 out2:
4578         free_page((unsigned long)vmx_msr_bitmap_legacy);
4579 out1:
4580         free_page((unsigned long)vmx_io_bitmap_b);
4581 out:
4582         free_page((unsigned long)vmx_io_bitmap_a);
4583         return r;
4584 }
4585
4586 static void __exit vmx_exit(void)
4587 {
4588         free_page((unsigned long)vmx_msr_bitmap_legacy);
4589         free_page((unsigned long)vmx_msr_bitmap_longmode);
4590         free_page((unsigned long)vmx_io_bitmap_b);
4591         free_page((unsigned long)vmx_io_bitmap_a);
4592
4593         kvm_exit();
4594 }
4595
4596 module_init(vmx_init)
4597 module_exit(vmx_exit)