arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/kvm_host.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31 #include <linux/tboot.h>
  32 #include "kvm_cache_regs.h"
  33 #include "x86.h"
  34
  35 #include <asm/io.h>
  36 #include <asm/desc.h>
  37 #include <asm/vmx.h>
  38 #include <asm/virtext.h>
  39 #include <asm/mce.h>
  40 #include <asm/i387.h>
  41 #include <asm/xcr.h>
  42
  43 #include "trace.h"
  44
  45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  46 #define __ex_clear(x, reg) \
  47         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  48
  49 MODULE_AUTHOR("Qumranet");
  50 MODULE_LICENSE("GPL");
  51
  52 static int __read_mostly enable_vpid = 1;
  53 module_param_named(vpid, enable_vpid, bool, 0444);
  54
  55 static int __read_mostly flexpriority_enabled = 1;
  56 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  57
  58 static int __read_mostly enable_ept = 1;
  59 module_param_named(ept, enable_ept, bool, S_IRUGO);
  60
  61 static int __read_mostly enable_unrestricted_guest = 1;
  62 module_param_named(unrestricted_guest,
  63                         enable_unrestricted_guest, bool, S_IRUGO);
  64
  65 static int __read_mostly emulate_invalid_guest_state = 0;
  66 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  67
  68 static int __read_mostly vmm_exclusive = 1;
  69 module_param(vmm_exclusive, bool, S_IRUGO);
  70
  71 static int __read_mostly yield_on_hlt = 1;
  72 module_param(yield_on_hlt, bool, S_IRUGO);
  73
  74 /*
  75  * If nested=1, nested virtualization is supported, i.e., guests may use
  76  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  77  * use VMX instructions.
  78  */
  79 static int __read_mostly nested = 0;
  80 module_param(nested, bool, S_IRUGO);
  81
  82 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  83         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  84 #define KVM_GUEST_CR0_MASK                                              \
  85         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  86 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  87         (X86_CR0_WP | X86_CR0_NE)
  88 #define KVM_VM_CR0_ALWAYS_ON                                            \
  89         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  90 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  91         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  92          | X86_CR4_OSXMMEXCPT)
  93
  94 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  95 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  96
  97 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
  98
  99 /*
 100  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 101  * ple_gap:    upper bound on the amount of time between two successive
 102  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 103  *             According to test, this time is usually smaller than 128 cycles.
 104  * ple_window: upper bound on the amount of time a guest is allowed to execute
 105  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 106  *             less than 2^12 cycles
 107  * Time is measured based on a counter that runs at the same rate as the TSC,
 108  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 109  */
 110 #define KVM_VMX_DEFAULT_PLE_GAP    128
 111 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 112 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 113 module_param(ple_gap, int, S_IRUGO);
 114
 115 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 116 module_param(ple_window, int, S_IRUGO);
 117
 118 #define NR_AUTOLOAD_MSRS 1
 119 #define VMCS02_POOL_SIZE 1
 120
 121 struct vmcs {
 122         u32 revision_id;
 123         u32 abort;
 124         char data[0];
 125 };
 126
 127 /*
 128  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 129  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 130  * loaded on this CPU (so we can clear them if the CPU goes down).
 131  */
 132 struct loaded_vmcs {
 133         struct vmcs *vmcs;
 134         int cpu;
 135         int launched;
 136         struct list_head loaded_vmcss_on_cpu_link;
 137 };
 138
 139 struct shared_msr_entry {
 140         unsigned index;
 141         u64 data;
 142         u64 mask;
 143 };
 144
 145 /*
 146  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 147  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 148  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 149  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 150  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 151  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 152  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 153  * underlying hardware which will be used to run L2.
 154  * This structure is packed to ensure that its layout is identical across
 155  * machines (necessary for live migration).
 156  * If there are changes in this struct, VMCS12_REVISION must be changed.
 157  */
 158 typedef u64 natural_width;
 159 struct __packed vmcs12 {
 160         /* According to the Intel spec, a VMCS region must start with the
 161          * following two fields. Then follow implementation-specific data.
 162          */
 163         u32 revision_id;
 164         u32 abort;
 165
 166         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 167         u32 padding[7]; /* room for future expansion */
 168
 169         u64 io_bitmap_a;
 170         u64 io_bitmap_b;
 171         u64 msr_bitmap;
 172         u64 vm_exit_msr_store_addr;
 173         u64 vm_exit_msr_load_addr;
 174         u64 vm_entry_msr_load_addr;
 175         u64 tsc_offset;
 176         u64 virtual_apic_page_addr;
 177         u64 apic_access_addr;
 178         u64 ept_pointer;
 179         u64 guest_physical_address;
 180         u64 vmcs_link_pointer;
 181         u64 guest_ia32_debugctl;
 182         u64 guest_ia32_pat;
 183         u64 guest_ia32_efer;
 184         u64 guest_ia32_perf_global_ctrl;
 185         u64 guest_pdptr0;
 186         u64 guest_pdptr1;
 187         u64 guest_pdptr2;
 188         u64 guest_pdptr3;
 189         u64 host_ia32_pat;
 190         u64 host_ia32_efer;
 191         u64 host_ia32_perf_global_ctrl;
 192         u64 padding64[8]; /* room for future expansion */
 193         /*
 194          * To allow migration of L1 (complete with its L2 guests) between
 195          * machines of different natural widths (32 or 64 bit), we cannot have
 196          * unsigned long fields with no explict size. We use u64 (aliased
 197          * natural_width) instead. Luckily, x86 is little-endian.
 198          */
 199         natural_width cr0_guest_host_mask;
 200         natural_width cr4_guest_host_mask;
 201         natural_width cr0_read_shadow;
 202         natural_width cr4_read_shadow;
 203         natural_width cr3_target_value0;
 204         natural_width cr3_target_value1;
 205         natural_width cr3_target_value2;
 206         natural_width cr3_target_value3;
 207         natural_width exit_qualification;
 208         natural_width guest_linear_address;
 209         natural_width guest_cr0;
 210         natural_width guest_cr3;
 211         natural_width guest_cr4;
 212         natural_width guest_es_base;
 213         natural_width guest_cs_base;
 214         natural_width guest_ss_base;
 215         natural_width guest_ds_base;
 216         natural_width guest_fs_base;
 217         natural_width guest_gs_base;
 218         natural_width guest_ldtr_base;
 219         natural_width guest_tr_base;
 220         natural_width guest_gdtr_base;
 221         natural_width guest_idtr_base;
 222         natural_width guest_dr7;
 223         natural_width guest_rsp;
 224         natural_width guest_rip;
 225         natural_width guest_rflags;
 226         natural_width guest_pending_dbg_exceptions;
 227         natural_width guest_sysenter_esp;
 228         natural_width guest_sysenter_eip;
 229         natural_width host_cr0;
 230         natural_width host_cr3;
 231         natural_width host_cr4;
 232         natural_width host_fs_base;
 233         natural_width host_gs_base;
 234         natural_width host_tr_base;
 235         natural_width host_gdtr_base;
 236         natural_width host_idtr_base;
 237         natural_width host_ia32_sysenter_esp;
 238         natural_width host_ia32_sysenter_eip;
 239         natural_width host_rsp;
 240         natural_width host_rip;
 241         natural_width paddingl[8]; /* room for future expansion */
 242         u32 pin_based_vm_exec_control;
 243         u32 cpu_based_vm_exec_control;
 244         u32 exception_bitmap;
 245         u32 page_fault_error_code_mask;
 246         u32 page_fault_error_code_match;
 247         u32 cr3_target_count;
 248         u32 vm_exit_controls;
 249         u32 vm_exit_msr_store_count;
 250         u32 vm_exit_msr_load_count;
 251         u32 vm_entry_controls;
 252         u32 vm_entry_msr_load_count;
 253         u32 vm_entry_intr_info_field;
 254         u32 vm_entry_exception_error_code;
 255         u32 vm_entry_instruction_len;
 256         u32 tpr_threshold;
 257         u32 secondary_vm_exec_control;
 258         u32 vm_instruction_error;
 259         u32 vm_exit_reason;
 260         u32 vm_exit_intr_info;
 261         u32 vm_exit_intr_error_code;
 262         u32 idt_vectoring_info_field;
 263         u32 idt_vectoring_error_code;
 264         u32 vm_exit_instruction_len;
 265         u32 vmx_instruction_info;
 266         u32 guest_es_limit;
 267         u32 guest_cs_limit;
 268         u32 guest_ss_limit;
 269         u32 guest_ds_limit;
 270         u32 guest_fs_limit;
 271         u32 guest_gs_limit;
 272         u32 guest_ldtr_limit;
 273         u32 guest_tr_limit;
 274         u32 guest_gdtr_limit;
 275         u32 guest_idtr_limit;
 276         u32 guest_es_ar_bytes;
 277         u32 guest_cs_ar_bytes;
 278         u32 guest_ss_ar_bytes;
 279         u32 guest_ds_ar_bytes;
 280         u32 guest_fs_ar_bytes;
 281         u32 guest_gs_ar_bytes;
 282         u32 guest_ldtr_ar_bytes;
 283         u32 guest_tr_ar_bytes;
 284         u32 guest_interruptibility_info;
 285         u32 guest_activity_state;
 286         u32 guest_sysenter_cs;
 287         u32 host_ia32_sysenter_cs;
 288         u32 padding32[8]; /* room for future expansion */
 289         u16 virtual_processor_id;
 290         u16 guest_es_selector;
 291         u16 guest_cs_selector;
 292         u16 guest_ss_selector;
 293         u16 guest_ds_selector;
 294         u16 guest_fs_selector;
 295         u16 guest_gs_selector;
 296         u16 guest_ldtr_selector;
 297         u16 guest_tr_selector;
 298         u16 host_es_selector;
 299         u16 host_cs_selector;
 300         u16 host_ss_selector;
 301         u16 host_ds_selector;
 302         u16 host_fs_selector;
 303         u16 host_gs_selector;
 304         u16 host_tr_selector;
 305 };
 306
 307 /*
 308  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 309  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 310  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 311  */
 312 #define VMCS12_REVISION 0x11e57ed0
 313
 314 /*
 315  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 316  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 317  * current implementation, 4K are reserved to avoid future complications.
 318  */
 319 #define VMCS12_SIZE 0x1000
 320
 321 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 322 struct vmcs02_list {
 323         struct list_head list;
 324         gpa_t vmptr;
 325         struct loaded_vmcs vmcs02;
 326 };
 327
 328 /*
 329  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 330  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 331  */
 332 struct nested_vmx {
 333         /* Has the level1 guest done vmxon? */
 334         bool vmxon;
 335
 336         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 337         gpa_t current_vmptr;
 338         /* The host-usable pointer to the above */
 339         struct page *current_vmcs12_page;
 340         struct vmcs12 *current_vmcs12;
 341
 342         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 343         struct list_head vmcs02_pool;
 344         int vmcs02_num;
 345         u64 vmcs01_tsc_offset;
 346         /* L2 must run next, and mustn't decide to exit to L1. */
 347         bool nested_run_pending;
 348         /*
 349          * Guest pages referred to in vmcs02 with host-physical pointers, so
 350          * we must keep them pinned while L2 runs.
 351          */
 352         struct page *apic_access_page;
 353 };
 354
 355 struct vcpu_vmx {
 356         struct kvm_vcpu       vcpu;
 357         unsigned long         host_rsp;
 358         u8                    fail;
 359         u8                    cpl;
 360         bool                  nmi_known_unmasked;
 361         u32                   exit_intr_info;
 362         u32                   idt_vectoring_info;
 363         ulong                 rflags;
 364         struct shared_msr_entry *guest_msrs;
 365         int                   nmsrs;
 366         int                   save_nmsrs;
 367 #ifdef CONFIG_X86_64
 368         u64                   msr_host_kernel_gs_base;
 369         u64                   msr_guest_kernel_gs_base;
 370 #endif
 371         /*
 372          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 373          * non-nested (L1) guest, it always points to vmcs01. For a nested
 374          * guest (L2), it points to a different VMCS.
 375          */
 376         struct loaded_vmcs    vmcs01;
 377         struct loaded_vmcs   *loaded_vmcs;
 378         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 379         struct msr_autoload {
 380                 unsigned nr;
 381                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 382                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 383         } msr_autoload;
 384         struct {
 385                 int           loaded;
 386                 u16           fs_sel, gs_sel, ldt_sel;
 387                 int           gs_ldt_reload_needed;
 388                 int           fs_reload_needed;
 389         } host_state;
 390         struct {
 391                 int vm86_active;
 392                 ulong save_rflags;
 393                 struct kvm_save_segment {
 394                         u16 selector;
 395                         unsigned long base;
 396                         u32 limit;
 397                         u32 ar;
 398                 } tr, es, ds, fs, gs;
 399         } rmode;
 400         struct {
 401                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 402                 struct kvm_save_segment seg[8];
 403         } segment_cache;
 404         int vpid;
 405         bool emulation_required;
 406
 407         /* Support for vnmi-less CPUs */
 408         int soft_vnmi_blocked;
 409         ktime_t entry_time;
 410         s64 vnmi_blocked_time;
 411         u32 exit_reason;
 412
 413         bool rdtscp_enabled;
 414
 415         /* Support for a guest hypervisor (nested VMX) */
 416         struct nested_vmx nested;
 417 };
 418
 419 enum segment_cache_field {
 420         SEG_FIELD_SEL = 0,
 421         SEG_FIELD_BASE = 1,
 422         SEG_FIELD_LIMIT = 2,
 423         SEG_FIELD_AR = 3,
 424
 425         SEG_FIELD_NR = 4
 426 };
 427
 428 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 429 {
 430         return container_of(vcpu, struct vcpu_vmx, vcpu);
 431 }
 432
 433 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 434 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 435 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 436                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 437
 438 static unsigned short vmcs_field_to_offset_table[] = {
 439         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 440         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 441         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 442         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 443         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 444         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 445         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 446         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 447         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 448         FIELD(HOST_ES_SELECTOR, host_es_selector),
 449         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 450         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 451         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 452         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 453         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 454         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 455         FIELD64(IO_BITMAP_A, io_bitmap_a),
 456         FIELD64(IO_BITMAP_B, io_bitmap_b),
 457         FIELD64(MSR_BITMAP, msr_bitmap),
 458         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 459         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 460         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 461         FIELD64(TSC_OFFSET, tsc_offset),
 462         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 463         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 464         FIELD64(EPT_POINTER, ept_pointer),
 465         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 466         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 467         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 468         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 469         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 470         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 471         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 472         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 473         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 474         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 475         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 476         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 477         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 478         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 479         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 480         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 481         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 482         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 483         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 484         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 485         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 486         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 487         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 488         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 489         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 490         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 491         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 492         FIELD(TPR_THRESHOLD, tpr_threshold),
 493         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 494         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 495         FIELD(VM_EXIT_REASON, vm_exit_reason),
 496         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 497         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 498         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 499         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 500         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 501         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 502         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 503         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 504         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 505         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 506         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 507         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 508         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 509         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 510         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 511         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 512         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 513         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 514         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 515         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 516         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 517         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 518         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 519         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 520         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 521         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 522         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 523         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 524         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 525         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 526         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 527         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 528         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 529         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 530         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 531         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 532         FIELD(EXIT_QUALIFICATION, exit_qualification),
 533         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 534         FIELD(GUEST_CR0, guest_cr0),
 535         FIELD(GUEST_CR3, guest_cr3),
 536         FIELD(GUEST_CR4, guest_cr4),
 537         FIELD(GUEST_ES_BASE, guest_es_base),
 538         FIELD(GUEST_CS_BASE, guest_cs_base),
 539         FIELD(GUEST_SS_BASE, guest_ss_base),
 540         FIELD(GUEST_DS_BASE, guest_ds_base),
 541         FIELD(GUEST_FS_BASE, guest_fs_base),
 542         FIELD(GUEST_GS_BASE, guest_gs_base),
 543         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 544         FIELD(GUEST_TR_BASE, guest_tr_base),
 545         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 546         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 547         FIELD(GUEST_DR7, guest_dr7),
 548         FIELD(GUEST_RSP, guest_rsp),
 549         FIELD(GUEST_RIP, guest_rip),
 550         FIELD(GUEST_RFLAGS, guest_rflags),
 551         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 552         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 553         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 554         FIELD(HOST_CR0, host_cr0),
 555         FIELD(HOST_CR3, host_cr3),
 556         FIELD(HOST_CR4, host_cr4),
 557         FIELD(HOST_FS_BASE, host_fs_base),
 558         FIELD(HOST_GS_BASE, host_gs_base),
 559         FIELD(HOST_TR_BASE, host_tr_base),
 560         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 561         FIELD(HOST_IDTR_BASE, host_idtr_base),
 562         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 563         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 564         FIELD(HOST_RSP, host_rsp),
 565         FIELD(HOST_RIP, host_rip),
 566 };
 567 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 568
 569 static inline short vmcs_field_to_offset(unsigned long field)
 570 {
 571         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 572                 return -1;
 573         return vmcs_field_to_offset_table[field];
 574 }
 575
 576 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 577 {
 578         return to_vmx(vcpu)->nested.current_vmcs12;
 579 }
 580
 581 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 582 {
 583         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 584         if (is_error_page(page)) {
 585                 kvm_release_page_clean(page);
 586                 return NULL;
 587         }
 588         return page;
 589 }
 590
 591 static void nested_release_page(struct page *page)
 592 {
 593         kvm_release_page_dirty(page);
 594 }
 595
 596 static void nested_release_page_clean(struct page *page)
 597 {
 598         kvm_release_page_clean(page);
 599 }
 600
 601 static u64 construct_eptp(unsigned long root_hpa);
 602 static void kvm_cpu_vmxon(u64 addr);
 603 static void kvm_cpu_vmxoff(void);
 604 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 605 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 606
 607 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 608 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 609 /*
 610  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 611  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 612  */
 613 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 614 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 615
 616 static unsigned long *vmx_io_bitmap_a;
 617 static unsigned long *vmx_io_bitmap_b;
 618 static unsigned long *vmx_msr_bitmap_legacy;
 619 static unsigned long *vmx_msr_bitmap_longmode;
 620
 621 static bool cpu_has_load_ia32_efer;
 622
 623 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 624 static DEFINE_SPINLOCK(vmx_vpid_lock);
 625
 626 static struct vmcs_config {
 627         int size;
 628         int order;
 629         u32 revision_id;
 630         u32 pin_based_exec_ctrl;
 631         u32 cpu_based_exec_ctrl;
 632         u32 cpu_based_2nd_exec_ctrl;
 633         u32 vmexit_ctrl;
 634         u32 vmentry_ctrl;
 635 } vmcs_config;
 636
 637 static struct vmx_capability {
 638         u32 ept;
 639         u32 vpid;
 640 } vmx_capability;
 641
 642 #define VMX_SEGMENT_FIELD(seg)                                  \
 643         [VCPU_SREG_##seg] = {                                   \
 644                 .selector = GUEST_##seg##_SELECTOR,             \
 645                 .base = GUEST_##seg##_BASE,                     \
 646                 .limit = GUEST_##seg##_LIMIT,                   \
 647                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 648         }
 649
 650 static struct kvm_vmx_segment_field {
 651         unsigned selector;
 652         unsigned base;
 653         unsigned limit;
 654         unsigned ar_bytes;
 655 } kvm_vmx_segment_fields[] = {
 656         VMX_SEGMENT_FIELD(CS),
 657         VMX_SEGMENT_FIELD(DS),
 658         VMX_SEGMENT_FIELD(ES),
 659         VMX_SEGMENT_FIELD(FS),
 660         VMX_SEGMENT_FIELD(GS),
 661         VMX_SEGMENT_FIELD(SS),
 662         VMX_SEGMENT_FIELD(TR),
 663         VMX_SEGMENT_FIELD(LDTR),
 664 };
 665
 666 static u64 host_efer;
 667
 668 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 669
 670 /*
 671  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 672  * away by decrementing the array size.
 673  */
 674 static const u32 vmx_msr_index[] = {
 675 #ifdef CONFIG_X86_64
 676         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 677 #endif
 678         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 679 };
 680 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 681
 682 static inline bool is_page_fault(u32 intr_info)
 683 {
 684         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 685                              INTR_INFO_VALID_MASK)) ==
 686                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 687 }
 688
 689 static inline bool is_no_device(u32 intr_info)
 690 {
 691         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 692                              INTR_INFO_VALID_MASK)) ==
 693                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 694 }
 695
 696 static inline bool is_invalid_opcode(u32 intr_info)
 697 {
 698         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 699                              INTR_INFO_VALID_MASK)) ==
 700                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 701 }
 702
 703 static inline bool is_external_interrupt(u32 intr_info)
 704 {
 705         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 706                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 707 }
 708
 709 static inline bool is_machine_check(u32 intr_info)
 710 {
 711         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 712                              INTR_INFO_VALID_MASK)) ==
 713                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 714 }
 715
 716 static inline bool cpu_has_vmx_msr_bitmap(void)
 717 {
 718         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 719 }
 720
 721 static inline bool cpu_has_vmx_tpr_shadow(void)
 722 {
 723         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 724 }
 725
 726 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 727 {
 728         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 729 }
 730
 731 static inline bool cpu_has_secondary_exec_ctrls(void)
 732 {
 733         return vmcs_config.cpu_based_exec_ctrl &
 734                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 735 }
 736
 737 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 738 {
 739         return vmcs_config.cpu_based_2nd_exec_ctrl &
 740                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 741 }
 742
 743 static inline bool cpu_has_vmx_flexpriority(void)
 744 {
 745         return cpu_has_vmx_tpr_shadow() &&
 746                 cpu_has_vmx_virtualize_apic_accesses();
 747 }
 748
 749 static inline bool cpu_has_vmx_ept_execute_only(void)
 750 {
 751         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 752 }
 753
 754 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 755 {
 756         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 757 }
 758
 759 static inline bool cpu_has_vmx_eptp_writeback(void)
 760 {
 761         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 762 }
 763
 764 static inline bool cpu_has_vmx_ept_2m_page(void)
 765 {
 766         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 767 }
 768
 769 static inline bool cpu_has_vmx_ept_1g_page(void)
 770 {
 771         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 772 }
 773
 774 static inline bool cpu_has_vmx_ept_4levels(void)
 775 {
 776         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 777 }
 778
 779 static inline bool cpu_has_vmx_invept_individual_addr(void)
 780 {
 781         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 782 }
 783
 784 static inline bool cpu_has_vmx_invept_context(void)
 785 {
 786         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 787 }
 788
 789 static inline bool cpu_has_vmx_invept_global(void)
 790 {
 791         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 792 }
 793
 794 static inline bool cpu_has_vmx_invvpid_single(void)
 795 {
 796         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 797 }
 798
 799 static inline bool cpu_has_vmx_invvpid_global(void)
 800 {
 801         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 802 }
 803
 804 static inline bool cpu_has_vmx_ept(void)
 805 {
 806         return vmcs_config.cpu_based_2nd_exec_ctrl &
 807                 SECONDARY_EXEC_ENABLE_EPT;
 808 }
 809
 810 static inline bool cpu_has_vmx_unrestricted_guest(void)
 811 {
 812         return vmcs_config.cpu_based_2nd_exec_ctrl &
 813                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 814 }
 815
 816 static inline bool cpu_has_vmx_ple(void)
 817 {
 818         return vmcs_config.cpu_based_2nd_exec_ctrl &
 819                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 820 }
 821
 822 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 823 {
 824         return flexpriority_enabled && irqchip_in_kernel(kvm);
 825 }
 826
 827 static inline bool cpu_has_vmx_vpid(void)
 828 {
 829         return vmcs_config.cpu_based_2nd_exec_ctrl &
 830                 SECONDARY_EXEC_ENABLE_VPID;
 831 }
 832
 833 static inline bool cpu_has_vmx_rdtscp(void)
 834 {
 835         return vmcs_config.cpu_based_2nd_exec_ctrl &
 836                 SECONDARY_EXEC_RDTSCP;
 837 }
 838
 839 static inline bool cpu_has_virtual_nmis(void)
 840 {
 841         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 842 }
 843
 844 static inline bool cpu_has_vmx_wbinvd_exit(void)
 845 {
 846         return vmcs_config.cpu_based_2nd_exec_ctrl &
 847                 SECONDARY_EXEC_WBINVD_EXITING;
 848 }
 849
 850 static inline bool report_flexpriority(void)
 851 {
 852         return flexpriority_enabled;
 853 }
 854
 855 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
 856 {
 857         return vmcs12->cpu_based_vm_exec_control & bit;
 858 }
 859
 860 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
 861 {
 862         return (vmcs12->cpu_based_vm_exec_control &
 863                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
 864                 (vmcs12->secondary_vm_exec_control & bit);
 865 }
 866
 867 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
 868         struct kvm_vcpu *vcpu)
 869 {
 870         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
 871 }
 872
 873 static inline bool is_exception(u32 intr_info)
 874 {
 875         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 876                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
 877 }
 878
 879 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
 880 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
 881                         struct vmcs12 *vmcs12,
 882                         u32 reason, unsigned long qualification);
 883
 884 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 885 {
 886         int i;
 887
 888         for (i = 0; i < vmx->nmsrs; ++i)
 889                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 890                         return i;
 891         return -1;
 892 }
 893
 894 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 895 {
 896     struct {
 897         u64 vpid : 16;
 898         u64 rsvd : 48;
 899         u64 gva;
 900     } operand = { vpid, 0, gva };
 901
 902     asm volatile (__ex(ASM_VMX_INVVPID)
 903                   /* CF==1 or ZF==1 --> rc = -1 */
 904                   "; ja 1f ; ud2 ; 1:"
 905                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 906 }
 907
 908 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 909 {
 910         struct {
 911                 u64 eptp, gpa;
 912         } operand = {eptp, gpa};
 913
 914         asm volatile (__ex(ASM_VMX_INVEPT)
 915                         /* CF==1 or ZF==1 --> rc = -1 */
 916                         "; ja 1f ; ud2 ; 1:\n"
 917                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 918 }
 919
 920 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 921 {
 922         int i;
 923
 924         i = __find_msr_index(vmx, msr);
 925         if (i >= 0)
 926                 return &vmx->guest_msrs[i];
 927         return NULL;
 928 }
 929
 930 static void vmcs_clear(struct vmcs *vmcs)
 931 {
 932         u64 phys_addr = __pa(vmcs);
 933         u8 error;
 934
 935         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 936                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 937                       : "cc", "memory");
 938         if (error)
 939                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 940                        vmcs, phys_addr);
 941 }
 942
 943 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 944 {
 945         vmcs_clear(loaded_vmcs->vmcs);
 946         loaded_vmcs->cpu = -1;
 947         loaded_vmcs->launched = 0;
 948 }
 949
 950 static void vmcs_load(struct vmcs *vmcs)
 951 {
 952         u64 phys_addr = __pa(vmcs);
 953         u8 error;
 954
 955         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 956                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 957                         : "cc", "memory");
 958         if (error)
 959                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
 960                        vmcs, phys_addr);
 961 }
 962
 963 static void __loaded_vmcs_clear(void *arg)
 964 {
 965         struct loaded_vmcs *loaded_vmcs = arg;
 966         int cpu = raw_smp_processor_id();
 967
 968         if (loaded_vmcs->cpu != cpu)
 969                 return; /* vcpu migration can race with cpu offline */
 970         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 971                 per_cpu(current_vmcs, cpu) = NULL;
 972         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 973         loaded_vmcs_init(loaded_vmcs);
 974 }
 975
 976 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 977 {
 978         if (loaded_vmcs->cpu != -1)
 979                 smp_call_function_single(
 980                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
 981 }
 982
 983 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
 984 {
 985         if (vmx->vpid == 0)
 986                 return;
 987
 988         if (cpu_has_vmx_invvpid_single())
 989                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 990 }
 991
 992 static inline void vpid_sync_vcpu_global(void)
 993 {
 994         if (cpu_has_vmx_invvpid_global())
 995                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
 996 }
 997
 998 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
 999 {
1000         if (cpu_has_vmx_invvpid_single())
1001                 vpid_sync_vcpu_single(vmx);
1002         else
1003                 vpid_sync_vcpu_global();
1004 }
1005
1006 static inline void ept_sync_global(void)
1007 {
1008         if (cpu_has_vmx_invept_global())
1009                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1010 }
1011
1012 static inline void ept_sync_context(u64 eptp)
1013 {
1014         if (enable_ept) {
1015                 if (cpu_has_vmx_invept_context())
1016                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1017                 else
1018                         ept_sync_global();
1019         }
1020 }
1021
1022 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1023 {
1024         if (enable_ept) {
1025                 if (cpu_has_vmx_invept_individual_addr())
1026                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1027                                         eptp, gpa);
1028                 else
1029                         ept_sync_context(eptp);
1030         }
1031 }
1032
1033 static __always_inline unsigned long vmcs_readl(unsigned long field)
1034 {
1035         unsigned long value;
1036
1037         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1038                       : "=a"(value) : "d"(field) : "cc");
1039         return value;
1040 }
1041
1042 static __always_inline u16 vmcs_read16(unsigned long field)
1043 {
1044         return vmcs_readl(field);
1045 }
1046
1047 static __always_inline u32 vmcs_read32(unsigned long field)
1048 {
1049         return vmcs_readl(field);
1050 }
1051
1052 static __always_inline u64 vmcs_read64(unsigned long field)
1053 {
1054 #ifdef CONFIG_X86_64
1055         return vmcs_readl(field);
1056 #else
1057         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1058 #endif
1059 }
1060
1061 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1062 {
1063         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1064                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1065         dump_stack();
1066 }
1067
1068 static void vmcs_writel(unsigned long field, unsigned long value)
1069 {
1070         u8 error;
1071
1072         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1073                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1074         if (unlikely(error))
1075                 vmwrite_error(field, value);
1076 }
1077
1078 static void vmcs_write16(unsigned long field, u16 value)
1079 {
1080         vmcs_writel(field, value);
1081 }
1082
1083 static void vmcs_write32(unsigned long field, u32 value)
1084 {
1085         vmcs_writel(field, value);
1086 }
1087
1088 static void vmcs_write64(unsigned long field, u64 value)
1089 {
1090         vmcs_writel(field, value);
1091 #ifndef CONFIG_X86_64
1092         asm volatile ("");
1093         vmcs_writel(field+1, value >> 32);
1094 #endif
1095 }
1096
1097 static void vmcs_clear_bits(unsigned long field, u32 mask)
1098 {
1099         vmcs_writel(field, vmcs_readl(field) & ~mask);
1100 }
1101
1102 static void vmcs_set_bits(unsigned long field, u32 mask)
1103 {
1104         vmcs_writel(field, vmcs_readl(field) | mask);
1105 }
1106
1107 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1108 {
1109         vmx->segment_cache.bitmask = 0;
1110 }
1111
1112 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1113                                        unsigned field)
1114 {
1115         bool ret;
1116         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1117
1118         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1119                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1120                 vmx->segment_cache.bitmask = 0;
1121         }
1122         ret = vmx->segment_cache.bitmask & mask;
1123         vmx->segment_cache.bitmask |= mask;
1124         return ret;
1125 }
1126
1127 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1128 {
1129         u16 *p = &vmx->segment_cache.seg[seg].selector;
1130
1131         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1132                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1133         return *p;
1134 }
1135
1136 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1137 {
1138         ulong *p = &vmx->segment_cache.seg[seg].base;
1139
1140         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1141                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1142         return *p;
1143 }
1144
1145 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1146 {
1147         u32 *p = &vmx->segment_cache.seg[seg].limit;
1148
1149         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1150                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1151         return *p;
1152 }
1153
1154 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1155 {
1156         u32 *p = &vmx->segment_cache.seg[seg].ar;
1157
1158         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1159                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1160         return *p;
1161 }
1162
1163 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1164 {
1165         u32 eb;
1166
1167         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1168              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1169         if ((vcpu->guest_debug &
1170              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1171             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1172                 eb |= 1u << BP_VECTOR;
1173         if (to_vmx(vcpu)->rmode.vm86_active)
1174                 eb = ~0;
1175         if (enable_ept)
1176                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1177         if (vcpu->fpu_active)
1178                 eb &= ~(1u << NM_VECTOR);
1179
1180         /* When we are running a nested L2 guest and L1 specified for it a
1181          * certain exception bitmap, we must trap the same exceptions and pass
1182          * them to L1. When running L2, we will only handle the exceptions
1183          * specified above if L1 did not want them.
1184          */
1185         if (is_guest_mode(vcpu))
1186                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1187
1188         vmcs_write32(EXCEPTION_BITMAP, eb);
1189 }
1190
1191 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1192 {
1193         unsigned i;
1194         struct msr_autoload *m = &vmx->msr_autoload;
1195
1196         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1197                 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1198                 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1199                 return;
1200         }
1201
1202         for (i = 0; i < m->nr; ++i)
1203                 if (m->guest[i].index == msr)
1204                         break;
1205
1206         if (i == m->nr)
1207                 return;
1208         --m->nr;
1209         m->guest[i] = m->guest[m->nr];
1210         m->host[i] = m->host[m->nr];
1211         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1212         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1213 }
1214
1215 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1216                                   u64 guest_val, u64 host_val)
1217 {
1218         unsigned i;
1219         struct msr_autoload *m = &vmx->msr_autoload;
1220
1221         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1222                 vmcs_write64(GUEST_IA32_EFER, guest_val);
1223                 vmcs_write64(HOST_IA32_EFER, host_val);
1224                 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1225                 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1226                 return;
1227         }
1228
1229         for (i = 0; i < m->nr; ++i)
1230                 if (m->guest[i].index == msr)
1231                         break;
1232
1233         if (i == m->nr) {
1234                 ++m->nr;
1235                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1236                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1237         }
1238
1239         m->guest[i].index = msr;
1240         m->guest[i].value = guest_val;
1241         m->host[i].index = msr;
1242         m->host[i].value = host_val;
1243 }
1244
1245 static void reload_tss(void)
1246 {
1247         /*
1248          * VT restores TR but not its size.  Useless.
1249          */
1250         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1251         struct desc_struct *descs;
1252
1253         descs = (void *)gdt->address;
1254         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1255         load_TR_desc();
1256 }
1257
1258 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1259 {
1260         u64 guest_efer;
1261         u64 ignore_bits;
1262
1263         guest_efer = vmx->vcpu.arch.efer;
1264
1265         /*
1266          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1267          * outside long mode
1268          */
1269         ignore_bits = EFER_NX | EFER_SCE;
1270 #ifdef CONFIG_X86_64
1271         ignore_bits |= EFER_LMA | EFER_LME;
1272         /* SCE is meaningful only in long mode on Intel */
1273         if (guest_efer & EFER_LMA)
1274                 ignore_bits &= ~(u64)EFER_SCE;
1275 #endif
1276         guest_efer &= ~ignore_bits;
1277         guest_efer |= host_efer & ignore_bits;
1278         vmx->guest_msrs[efer_offset].data = guest_efer;
1279         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1280
1281         clear_atomic_switch_msr(vmx, MSR_EFER);
1282         /* On ept, can't emulate nx, and must switch nx atomically */
1283         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1284                 guest_efer = vmx->vcpu.arch.efer;
1285                 if (!(guest_efer & EFER_LMA))
1286                         guest_efer &= ~EFER_LME;
1287                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1288                 return false;
1289         }
1290
1291         return true;
1292 }
1293
1294 static unsigned long segment_base(u16 selector)
1295 {
1296         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1297         struct desc_struct *d;
1298         unsigned long table_base;
1299         unsigned long v;
1300
1301         if (!(selector & ~3))
1302                 return 0;
1303
1304         table_base = gdt->address;
1305
1306         if (selector & 4) {           /* from ldt */
1307                 u16 ldt_selector = kvm_read_ldt();
1308
1309                 if (!(ldt_selector & ~3))
1310                         return 0;
1311
1312                 table_base = segment_base(ldt_selector);
1313         }
1314         d = (struct desc_struct *)(table_base + (selector & ~7));
1315         v = get_desc_base(d);
1316 #ifdef CONFIG_X86_64
1317        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1318                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1319 #endif
1320         return v;
1321 }
1322
1323 static inline unsigned long kvm_read_tr_base(void)
1324 {
1325         u16 tr;
1326         asm("str %0" : "=g"(tr));
1327         return segment_base(tr);
1328 }
1329
1330 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1331 {
1332         struct vcpu_vmx *vmx = to_vmx(vcpu);
1333         int i;
1334
1335         if (vmx->host_state.loaded)
1336                 return;
1337
1338         vmx->host_state.loaded = 1;
1339         /*
1340          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1341          * allow segment selectors with cpl > 0 or ti == 1.
1342          */
1343         vmx->host_state.ldt_sel = kvm_read_ldt();
1344         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1345         savesegment(fs, vmx->host_state.fs_sel);
1346         if (!(vmx->host_state.fs_sel & 7)) {
1347                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1348                 vmx->host_state.fs_reload_needed = 0;
1349         } else {
1350                 vmcs_write16(HOST_FS_SELECTOR, 0);
1351                 vmx->host_state.fs_reload_needed = 1;
1352         }
1353         savesegment(gs, vmx->host_state.gs_sel);
1354         if (!(vmx->host_state.gs_sel & 7))
1355                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1356         else {
1357                 vmcs_write16(HOST_GS_SELECTOR, 0);
1358                 vmx->host_state.gs_ldt_reload_needed = 1;
1359         }
1360
1361 #ifdef CONFIG_X86_64
1362         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1363         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1364 #else
1365         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1366         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1367 #endif
1368
1369 #ifdef CONFIG_X86_64
1370         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1371         if (is_long_mode(&vmx->vcpu))
1372                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1373 #endif
1374         for (i = 0; i < vmx->save_nmsrs; ++i)
1375                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1376                                    vmx->guest_msrs[i].data,
1377                                    vmx->guest_msrs[i].mask);
1378 }
1379
1380 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1381 {
1382         if (!vmx->host_state.loaded)
1383                 return;
1384
1385         ++vmx->vcpu.stat.host_state_reload;
1386         vmx->host_state.loaded = 0;
1387 #ifdef CONFIG_X86_64
1388         if (is_long_mode(&vmx->vcpu))
1389                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1390 #endif
1391         if (vmx->host_state.gs_ldt_reload_needed) {
1392                 kvm_load_ldt(vmx->host_state.ldt_sel);
1393 #ifdef CONFIG_X86_64
1394                 load_gs_index(vmx->host_state.gs_sel);
1395 #else
1396                 loadsegment(gs, vmx->host_state.gs_sel);
1397 #endif
1398         }
1399         if (vmx->host_state.fs_reload_needed)
1400                 loadsegment(fs, vmx->host_state.fs_sel);
1401         reload_tss();
1402 #ifdef CONFIG_X86_64
1403         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1404 #endif
1405         if (current_thread_info()->status & TS_USEDFPU)
1406                 clts();
1407         load_gdt(&__get_cpu_var(host_gdt));
1408 }
1409
1410 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1411 {
1412         preempt_disable();
1413         __vmx_load_host_state(vmx);
1414         preempt_enable();
1415 }
1416
1417 /*
1418  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1419  * vcpu mutex is already taken.
1420  */
1421 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1422 {
1423         struct vcpu_vmx *vmx = to_vmx(vcpu);
1424         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1425
1426         if (!vmm_exclusive)
1427                 kvm_cpu_vmxon(phys_addr);
1428         else if (vmx->loaded_vmcs->cpu != cpu)
1429                 loaded_vmcs_clear(vmx->loaded_vmcs);
1430
1431         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1432                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1433                 vmcs_load(vmx->loaded_vmcs->vmcs);
1434         }
1435
1436         if (vmx->loaded_vmcs->cpu != cpu) {
1437                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1438                 unsigned long sysenter_esp;
1439
1440                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1441                 local_irq_disable();
1442                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1443                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1444                 local_irq_enable();
1445
1446                 /*
1447                  * Linux uses per-cpu TSS and GDT, so set these when switching
1448                  * processors.
1449                  */
1450                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1451                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1452
1453                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1454                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1455                 vmx->loaded_vmcs->cpu = cpu;
1456         }
1457 }
1458
1459 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1460 {
1461         __vmx_load_host_state(to_vmx(vcpu));
1462         if (!vmm_exclusive) {
1463                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1464                 vcpu->cpu = -1;
1465                 kvm_cpu_vmxoff();
1466         }
1467 }
1468
1469 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1470 {
1471         ulong cr0;
1472
1473         if (vcpu->fpu_active)
1474                 return;
1475         vcpu->fpu_active = 1;
1476         cr0 = vmcs_readl(GUEST_CR0);
1477         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1478         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1479         vmcs_writel(GUEST_CR0, cr0);
1480         update_exception_bitmap(vcpu);
1481         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1482         if (is_guest_mode(vcpu))
1483                 vcpu->arch.cr0_guest_owned_bits &=
1484                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1485         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1486 }
1487
1488 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1489
1490 /*
1491  * Return the cr0 value that a nested guest would read. This is a combination
1492  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1493  * its hypervisor (cr0_read_shadow).
1494  */
1495 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1496 {
1497         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1498                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1499 }
1500 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1501 {
1502         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1503                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1504 }
1505
1506 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1507 {
1508         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1509          * set this *before* calling this function.
1510          */
1511         vmx_decache_cr0_guest_bits(vcpu);
1512         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1513         update_exception_bitmap(vcpu);
1514         vcpu->arch.cr0_guest_owned_bits = 0;
1515         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1516         if (is_guest_mode(vcpu)) {
1517                 /*
1518                  * L1's specified read shadow might not contain the TS bit,
1519                  * so now that we turned on shadowing of this bit, we need to
1520                  * set this bit of the shadow. Like in nested_vmx_run we need
1521                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1522                  * up-to-date here because we just decached cr0.TS (and we'll
1523                  * only update vmcs12->guest_cr0 on nested exit).
1524                  */
1525                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1526                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1527                         (vcpu->arch.cr0 & X86_CR0_TS);
1528                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1529         } else
1530                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1531 }
1532
1533 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1534 {
1535         unsigned long rflags, save_rflags;
1536
1537         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1538                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1539                 rflags = vmcs_readl(GUEST_RFLAGS);
1540                 if (to_vmx(vcpu)->rmode.vm86_active) {
1541                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1542                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1543                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1544                 }
1545                 to_vmx(vcpu)->rflags = rflags;
1546         }
1547         return to_vmx(vcpu)->rflags;
1548 }
1549
1550 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1551 {
1552         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1553         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1554         to_vmx(vcpu)->rflags = rflags;
1555         if (to_vmx(vcpu)->rmode.vm86_active) {
1556                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1557                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1558         }
1559         vmcs_writel(GUEST_RFLAGS, rflags);
1560 }
1561
1562 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1563 {
1564         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1565         int ret = 0;
1566
1567         if (interruptibility & GUEST_INTR_STATE_STI)
1568                 ret |= KVM_X86_SHADOW_INT_STI;
1569         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1570                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1571
1572         return ret & mask;
1573 }
1574
1575 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1576 {
1577         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1578         u32 interruptibility = interruptibility_old;
1579
1580         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1581
1582         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1583                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1584         else if (mask & KVM_X86_SHADOW_INT_STI)
1585                 interruptibility |= GUEST_INTR_STATE_STI;
1586
1587         if ((interruptibility != interruptibility_old))
1588                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1589 }
1590
1591 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1592 {
1593         unsigned long rip;
1594
1595         rip = kvm_rip_read(vcpu);
1596         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1597         kvm_rip_write(vcpu, rip);
1598
1599         /* skipping an emulated instruction also counts */
1600         vmx_set_interrupt_shadow(vcpu, 0);
1601 }
1602
1603 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1604 {
1605         /* Ensure that we clear the HLT state in the VMCS.  We don't need to
1606          * explicitly skip the instruction because if the HLT state is set, then
1607          * the instruction is already executing and RIP has already been
1608          * advanced. */
1609         if (!yield_on_hlt &&
1610             vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1611                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1612 }
1613
1614 /*
1615  * KVM wants to inject page-faults which it got to the guest. This function
1616  * checks whether in a nested guest, we need to inject them to L1 or L2.
1617  * This function assumes it is called with the exit reason in vmcs02 being
1618  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1619  * is running).
1620  */
1621 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1622 {
1623         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1624
1625         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1626         if (!(vmcs12->exception_bitmap & PF_VECTOR))
1627                 return 0;
1628
1629         nested_vmx_vmexit(vcpu);
1630         return 1;
1631 }
1632
1633 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1634                                 bool has_error_code, u32 error_code,
1635                                 bool reinject)
1636 {
1637         struct vcpu_vmx *vmx = to_vmx(vcpu);
1638         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1639
1640         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1641                 nested_pf_handled(vcpu))
1642                 return;
1643
1644         if (has_error_code) {
1645                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1646                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1647         }
1648
1649         if (vmx->rmode.vm86_active) {
1650                 int inc_eip = 0;
1651                 if (kvm_exception_is_soft(nr))
1652                         inc_eip = vcpu->arch.event_exit_inst_len;
1653                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1654                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1655                 return;
1656         }
1657
1658         if (kvm_exception_is_soft(nr)) {
1659                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1660                              vmx->vcpu.arch.event_exit_inst_len);
1661                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1662         } else
1663                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1664
1665         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1666         vmx_clear_hlt(vcpu);
1667 }
1668
1669 static bool vmx_rdtscp_supported(void)
1670 {
1671         return cpu_has_vmx_rdtscp();
1672 }
1673
1674 /*
1675  * Swap MSR entry in host/guest MSR entry array.
1676  */
1677 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1678 {
1679         struct shared_msr_entry tmp;
1680
1681         tmp = vmx->guest_msrs[to];
1682         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1683         vmx->guest_msrs[from] = tmp;
1684 }
1685
1686 /*
1687  * Set up the vmcs to automatically save and restore system
1688  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1689  * mode, as fiddling with msrs is very expensive.
1690  */
1691 static void setup_msrs(struct vcpu_vmx *vmx)
1692 {
1693         int save_nmsrs, index;
1694         unsigned long *msr_bitmap;
1695
1696         vmx_load_host_state(vmx);
1697         save_nmsrs = 0;
1698 #ifdef CONFIG_X86_64
1699         if (is_long_mode(&vmx->vcpu)) {
1700                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1701                 if (index >= 0)
1702                         move_msr_up(vmx, index, save_nmsrs++);
1703                 index = __find_msr_index(vmx, MSR_LSTAR);
1704                 if (index >= 0)
1705                         move_msr_up(vmx, index, save_nmsrs++);
1706                 index = __find_msr_index(vmx, MSR_CSTAR);
1707                 if (index >= 0)
1708                         move_msr_up(vmx, index, save_nmsrs++);
1709                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1710                 if (index >= 0 && vmx->rdtscp_enabled)
1711                         move_msr_up(vmx, index, save_nmsrs++);
1712                 /*
1713                  * MSR_STAR is only needed on long mode guests, and only
1714                  * if efer.sce is enabled.
1715                  */
1716                 index = __find_msr_index(vmx, MSR_STAR);
1717                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1718                         move_msr_up(vmx, index, save_nmsrs++);
1719         }
1720 #endif
1721         index = __find_msr_index(vmx, MSR_EFER);
1722         if (index >= 0 && update_transition_efer(vmx, index))
1723                 move_msr_up(vmx, index, save_nmsrs++);
1724
1725         vmx->save_nmsrs = save_nmsrs;
1726
1727         if (cpu_has_vmx_msr_bitmap()) {
1728                 if (is_long_mode(&vmx->vcpu))
1729                         msr_bitmap = vmx_msr_bitmap_longmode;
1730                 else
1731                         msr_bitmap = vmx_msr_bitmap_legacy;
1732
1733                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1734         }
1735 }
1736
1737 /*
1738  * reads and returns guest's timestamp counter "register"
1739  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1740  */
1741 static u64 guest_read_tsc(void)
1742 {
1743         u64 host_tsc, tsc_offset;
1744
1745         rdtscll(host_tsc);
1746         tsc_offset = vmcs_read64(TSC_OFFSET);
1747         return host_tsc + tsc_offset;
1748 }
1749
1750 /*
1751  * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1752  * ioctl. In this case the call-back should update internal vmx state to make
1753  * the changes effective.
1754  */
1755 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1756 {
1757         /* Nothing to do here */
1758 }
1759
1760 /*
1761  * writes 'offset' into guest's timestamp counter offset register
1762  */
1763 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1764 {
1765         vmcs_write64(TSC_OFFSET, offset);
1766         if (is_guest_mode(vcpu))
1767                 /*
1768                  * We're here if L1 chose not to trap the TSC MSR. Since
1769                  * prepare_vmcs12() does not copy tsc_offset, we need to also
1770                  * set the vmcs12 field here.
1771                  */
1772                 get_vmcs12(vcpu)->tsc_offset = offset -
1773                         to_vmx(vcpu)->nested.vmcs01_tsc_offset;
1774 }
1775
1776 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1777 {
1778         u64 offset = vmcs_read64(TSC_OFFSET);
1779         vmcs_write64(TSC_OFFSET, offset + adjustment);
1780         if (is_guest_mode(vcpu)) {
1781                 /* Even when running L2, the adjustment needs to apply to L1 */
1782                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1783         }
1784 }
1785
1786 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1787 {
1788         return target_tsc - native_read_tsc();
1789 }
1790
1791 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1792 {
1793         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1794         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1795 }
1796
1797 /*
1798  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1799  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1800  * all guests if the "nested" module option is off, and can also be disabled
1801  * for a single guest by disabling its VMX cpuid bit.
1802  */
1803 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1804 {
1805         return nested && guest_cpuid_has_vmx(vcpu);
1806 }
1807
1808 /*
1809  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1810  * returned for the various VMX controls MSRs when nested VMX is enabled.
1811  * The same values should also be used to verify that vmcs12 control fields are
1812  * valid during nested entry from L1 to L2.
1813  * Each of these control msrs has a low and high 32-bit half: A low bit is on
1814  * if the corresponding bit in the (32-bit) control field *must* be on, and a
1815  * bit in the high half is on if the corresponding bit in the control field
1816  * may be on. See also vmx_control_verify().
1817  * TODO: allow these variables to be modified (downgraded) by module options
1818  * or other means.
1819  */
1820 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1821 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1822 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1823 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1824 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1825 static __init void nested_vmx_setup_ctls_msrs(void)
1826 {
1827         /*
1828          * Note that as a general rule, the high half of the MSRs (bits in
1829          * the control fields which may be 1) should be initialized by the
1830          * intersection of the underlying hardware's MSR (i.e., features which
1831          * can be supported) and the list of features we want to expose -
1832          * because they are known to be properly supported in our code.
1833          * Also, usually, the low half of the MSRs (bits which must be 1) can
1834          * be set to 0, meaning that L1 may turn off any of these bits. The
1835          * reason is that if one of these bits is necessary, it will appear
1836          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1837          * fields of vmcs01 and vmcs02, will turn these bits off - and
1838          * nested_vmx_exit_handled() will not pass related exits to L1.
1839          * These rules have exceptions below.
1840          */
1841
1842         /* pin-based controls */
1843         /*
1844          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1845          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1846          */
1847         nested_vmx_pinbased_ctls_low = 0x16 ;
1848         nested_vmx_pinbased_ctls_high = 0x16 |
1849                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1850                 PIN_BASED_VIRTUAL_NMIS;
1851
1852         /* exit controls */
1853         nested_vmx_exit_ctls_low = 0;
1854         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1855 #ifdef CONFIG_X86_64
1856         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1857 #else
1858         nested_vmx_exit_ctls_high = 0;
1859 #endif
1860
1861         /* entry controls */
1862         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1863                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1864         nested_vmx_entry_ctls_low = 0;
1865         nested_vmx_entry_ctls_high &=
1866                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1867
1868         /* cpu-based controls */
1869         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1870                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1871         nested_vmx_procbased_ctls_low = 0;
1872         nested_vmx_procbased_ctls_high &=
1873                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1874                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1875                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1876                 CPU_BASED_CR3_STORE_EXITING |
1877 #ifdef CONFIG_X86_64
1878                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1879 #endif
1880                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1881                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1882                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1883         /*
1884          * We can allow some features even when not supported by the
1885          * hardware. For example, L1 can specify an MSR bitmap - and we
1886          * can use it to avoid exits to L1 - even when L0 runs L2
1887          * without MSR bitmaps.
1888          */
1889         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1890
1891         /* secondary cpu-based controls */
1892         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1893                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1894         nested_vmx_secondary_ctls_low = 0;
1895         nested_vmx_secondary_ctls_high &=
1896                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1897 }
1898
1899 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1900 {
1901         /*
1902          * Bits 0 in high must be 0, and bits 1 in low must be 1.
1903          */
1904         return ((control & high) | low) == control;
1905 }
1906
1907 static inline u64 vmx_control_msr(u32 low, u32 high)
1908 {
1909         return low | ((u64)high << 32);
1910 }
1911
1912 /*
1913  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1914  * also let it use VMX-specific MSRs.
1915  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1916  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1917  * like all other MSRs).
1918  */
1919 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1920 {
1921         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1922                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
1923                 /*
1924                  * According to the spec, processors which do not support VMX
1925                  * should throw a #GP(0) when VMX capability MSRs are read.
1926                  */
1927                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
1928                 return 1;
1929         }
1930
1931         switch (msr_index) {
1932         case MSR_IA32_FEATURE_CONTROL:
1933                 *pdata = 0;
1934                 break;
1935         case MSR_IA32_VMX_BASIC:
1936                 /*
1937                  * This MSR reports some information about VMX support. We
1938                  * should return information about the VMX we emulate for the
1939                  * guest, and the VMCS structure we give it - not about the
1940                  * VMX support of the underlying hardware.
1941                  */
1942                 *pdata = VMCS12_REVISION |
1943                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
1944                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
1945                 break;
1946         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1947         case MSR_IA32_VMX_PINBASED_CTLS:
1948                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
1949                                         nested_vmx_pinbased_ctls_high);
1950                 break;
1951         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1952         case MSR_IA32_VMX_PROCBASED_CTLS:
1953                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
1954                                         nested_vmx_procbased_ctls_high);
1955                 break;
1956         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1957         case MSR_IA32_VMX_EXIT_CTLS:
1958                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
1959                                         nested_vmx_exit_ctls_high);
1960                 break;
1961         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1962         case MSR_IA32_VMX_ENTRY_CTLS:
1963                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
1964                                         nested_vmx_entry_ctls_high);
1965                 break;
1966         case MSR_IA32_VMX_MISC:
1967                 *pdata = 0;
1968                 break;
1969         /*
1970          * These MSRs specify bits which the guest must keep fixed (on or off)
1971          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
1972          * We picked the standard core2 setting.
1973          */
1974 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
1975 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
1976         case MSR_IA32_VMX_CR0_FIXED0:
1977                 *pdata = VMXON_CR0_ALWAYSON;
1978                 break;
1979         case MSR_IA32_VMX_CR0_FIXED1:
1980                 *pdata = -1ULL;
1981                 break;
1982         case MSR_IA32_VMX_CR4_FIXED0:
1983                 *pdata = VMXON_CR4_ALWAYSON;
1984                 break;
1985         case MSR_IA32_VMX_CR4_FIXED1:
1986                 *pdata = -1ULL;
1987                 break;
1988         case MSR_IA32_VMX_VMCS_ENUM:
1989                 *pdata = 0x1f;
1990                 break;
1991         case MSR_IA32_VMX_PROCBASED_CTLS2:
1992                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
1993                                         nested_vmx_secondary_ctls_high);
1994                 break;
1995         case MSR_IA32_VMX_EPT_VPID_CAP:
1996                 /* Currently, no nested ept or nested vpid */
1997                 *pdata = 0;
1998                 break;
1999         default:
2000                 return 0;
2001         }
2002
2003         return 1;
2004 }
2005
2006 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2007 {
2008         if (!nested_vmx_allowed(vcpu))
2009                 return 0;
2010
2011         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2012                 /* TODO: the right thing. */
2013                 return 1;
2014         /*
2015          * No need to treat VMX capability MSRs specially: If we don't handle
2016          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2017          */
2018         return 0;
2019 }
2020
2021 /*
2022  * Reads an msr value (of 'msr_index') into 'pdata'.
2023  * Returns 0 on success, non-0 otherwise.
2024  * Assumes vcpu_load() was already called.
2025  */
2026 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2027 {
2028         u64 data;
2029         struct shared_msr_entry *msr;
2030
2031         if (!pdata) {
2032                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2033                 return -EINVAL;
2034         }
2035
2036         switch (msr_index) {
2037 #ifdef CONFIG_X86_64
2038         case MSR_FS_BASE:
2039                 data = vmcs_readl(GUEST_FS_BASE);
2040                 break;
2041         case MSR_GS_BASE:
2042                 data = vmcs_readl(GUEST_GS_BASE);
2043                 break;
2044         case MSR_KERNEL_GS_BASE:
2045                 vmx_load_host_state(to_vmx(vcpu));
2046                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2047                 break;
2048 #endif
2049         case MSR_EFER:
2050                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2051         case MSR_IA32_TSC:
2052                 data = guest_read_tsc();
2053                 break;
2054         case MSR_IA32_SYSENTER_CS:
2055                 data = vmcs_read32(GUEST_SYSENTER_CS);
2056                 break;
2057         case MSR_IA32_SYSENTER_EIP:
2058                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2059                 break;
2060         case MSR_IA32_SYSENTER_ESP:
2061                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2062                 break;
2063         case MSR_TSC_AUX:
2064                 if (!to_vmx(vcpu)->rdtscp_enabled)
2065                         return 1;
2066                 /* Otherwise falls through */
2067         default:
2068                 vmx_load_host_state(to_vmx(vcpu));
2069                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2070                         return 0;
2071                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2072                 if (msr) {
2073                         vmx_load_host_state(to_vmx(vcpu));
2074                         data = msr->data;
2075                         break;
2076                 }
2077                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2078         }
2079
2080         *pdata = data;
2081         return 0;
2082 }
2083
2084 /*
2085  * Writes msr value into into the appropriate "register".
2086  * Returns 0 on success, non-0 otherwise.
2087  * Assumes vcpu_load() was already called.
2088  */
2089 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2090 {
2091         struct vcpu_vmx *vmx = to_vmx(vcpu);
2092         struct shared_msr_entry *msr;
2093         int ret = 0;
2094
2095         switch (msr_index) {
2096         case MSR_EFER:
2097                 vmx_load_host_state(vmx);
2098                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2099                 break;
2100 #ifdef CONFIG_X86_64
2101         case MSR_FS_BASE:
2102                 vmx_segment_cache_clear(vmx);
2103                 vmcs_writel(GUEST_FS_BASE, data);
2104                 break;
2105         case MSR_GS_BASE:
2106                 vmx_segment_cache_clear(vmx);
2107                 vmcs_writel(GUEST_GS_BASE, data);
2108                 break;
2109         case MSR_KERNEL_GS_BASE:
2110                 vmx_load_host_state(vmx);
2111                 vmx->msr_guest_kernel_gs_base = data;
2112                 break;
2113 #endif
2114         case MSR_IA32_SYSENTER_CS:
2115                 vmcs_write32(GUEST_SYSENTER_CS, data);
2116                 break;
2117         case MSR_IA32_SYSENTER_EIP:
2118                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2119                 break;
2120         case MSR_IA32_SYSENTER_ESP:
2121                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2122                 break;
2123         case MSR_IA32_TSC:
2124                 kvm_write_tsc(vcpu, data);
2125                 break;
2126         case MSR_IA32_CR_PAT:
2127                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2128                         vmcs_write64(GUEST_IA32_PAT, data);
2129                         vcpu->arch.pat = data;
2130                         break;
2131                 }
2132                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2133                 break;
2134         case MSR_TSC_AUX:
2135                 if (!vmx->rdtscp_enabled)
2136                         return 1;
2137                 /* Check reserved bit, higher 32 bits should be zero */
2138                 if ((data >> 32) != 0)
2139                         return 1;
2140                 /* Otherwise falls through */
2141         default:
2142                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2143                         break;
2144                 msr = find_msr_entry(vmx, msr_index);
2145                 if (msr) {
2146                         vmx_load_host_state(vmx);
2147                         msr->data = data;
2148                         break;
2149                 }
2150                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2151         }
2152
2153         return ret;
2154 }
2155
2156 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2157 {
2158         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2159         switch (reg) {
2160         case VCPU_REGS_RSP:
2161                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2162                 break;
2163         case VCPU_REGS_RIP:
2164                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2165                 break;
2166         case VCPU_EXREG_PDPTR:
2167                 if (enable_ept)
2168                         ept_save_pdptrs(vcpu);
2169                 break;
2170         default:
2171                 break;
2172         }
2173 }
2174
2175 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2176 {
2177         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2178                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2179         else
2180                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2181
2182         update_exception_bitmap(vcpu);
2183 }
2184
2185 static __init int cpu_has_kvm_support(void)
2186 {
2187         return cpu_has_vmx();
2188 }
2189
2190 static __init int vmx_disabled_by_bios(void)
2191 {
2192         u64 msr;
2193
2194         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2195         if (msr & FEATURE_CONTROL_LOCKED) {
2196                 /* launched w/ TXT and VMX disabled */
2197                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2198                         && tboot_enabled())
2199                         return 1;
2200                 /* launched w/o TXT and VMX only enabled w/ TXT */
2201                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2202                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2203                         && !tboot_enabled()) {
2204                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2205                                 "activate TXT before enabling KVM\n");
2206                         return 1;
2207                 }
2208                 /* launched w/o TXT and VMX disabled */
2209                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2210                         && !tboot_enabled())
2211                         return 1;
2212         }
2213
2214         return 0;
2215 }
2216
2217 static void kvm_cpu_vmxon(u64 addr)
2218 {
2219         asm volatile (ASM_VMX_VMXON_RAX
2220                         : : "a"(&addr), "m"(addr)
2221                         : "memory", "cc");
2222 }
2223
2224 static int hardware_enable(void *garbage)
2225 {
2226         int cpu = raw_smp_processor_id();
2227         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2228         u64 old, test_bits;
2229
2230         if (read_cr4() & X86_CR4_VMXE)
2231                 return -EBUSY;
2232
2233         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2234         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2235
2236         test_bits = FEATURE_CONTROL_LOCKED;
2237         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2238         if (tboot_enabled())
2239                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2240
2241         if ((old & test_bits) != test_bits) {
2242                 /* enable and lock */
2243                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2244         }
2245         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2246
2247         if (vmm_exclusive) {
2248                 kvm_cpu_vmxon(phys_addr);
2249                 ept_sync_global();
2250         }
2251
2252         store_gdt(&__get_cpu_var(host_gdt));
2253
2254         return 0;
2255 }
2256
2257 static void vmclear_local_loaded_vmcss(void)
2258 {
2259         int cpu = raw_smp_processor_id();
2260         struct loaded_vmcs *v, *n;
2261
2262         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2263                                  loaded_vmcss_on_cpu_link)
2264                 __loaded_vmcs_clear(v);
2265 }
2266
2267
2268 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2269  * tricks.
2270  */
2271 static void kvm_cpu_vmxoff(void)
2272 {
2273         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2274 }
2275
2276 static void hardware_disable(void *garbage)
2277 {
2278         if (vmm_exclusive) {
2279                 vmclear_local_loaded_vmcss();
2280                 kvm_cpu_vmxoff();
2281         }
2282         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2283 }
2284
2285 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2286                                       u32 msr, u32 *result)
2287 {
2288         u32 vmx_msr_low, vmx_msr_high;
2289         u32 ctl = ctl_min | ctl_opt;
2290
2291         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2292
2293         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2294         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2295
2296         /* Ensure minimum (required) set of control bits are supported. */
2297         if (ctl_min & ~ctl)
2298                 return -EIO;
2299
2300         *result = ctl;
2301         return 0;
2302 }
2303
2304 static __init bool allow_1_setting(u32 msr, u32 ctl)
2305 {
2306         u32 vmx_msr_low, vmx_msr_high;
2307
2308         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2309         return vmx_msr_high & ctl;
2310 }
2311
2312 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2313 {
2314         u32 vmx_msr_low, vmx_msr_high;
2315         u32 min, opt, min2, opt2;
2316         u32 _pin_based_exec_control = 0;
2317         u32 _cpu_based_exec_control = 0;
2318         u32 _cpu_based_2nd_exec_control = 0;
2319         u32 _vmexit_control = 0;
2320         u32 _vmentry_control = 0;
2321
2322         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2323         opt = PIN_BASED_VIRTUAL_NMIS;
2324         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2325                                 &_pin_based_exec_control) < 0)
2326                 return -EIO;
2327
2328         min =
2329 #ifdef CONFIG_X86_64
2330               CPU_BASED_CR8_LOAD_EXITING |
2331               CPU_BASED_CR8_STORE_EXITING |
2332 #endif
2333               CPU_BASED_CR3_LOAD_EXITING |
2334               CPU_BASED_CR3_STORE_EXITING |
2335               CPU_BASED_USE_IO_BITMAPS |
2336               CPU_BASED_MOV_DR_EXITING |
2337               CPU_BASED_USE_TSC_OFFSETING |
2338               CPU_BASED_MWAIT_EXITING |
2339               CPU_BASED_MONITOR_EXITING |
2340               CPU_BASED_INVLPG_EXITING;
2341
2342         if (yield_on_hlt)
2343                 min |= CPU_BASED_HLT_EXITING;
2344
2345         opt = CPU_BASED_TPR_SHADOW |
2346               CPU_BASED_USE_MSR_BITMAPS |
2347               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2348         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2349                                 &_cpu_based_exec_control) < 0)
2350                 return -EIO;
2351 #ifdef CONFIG_X86_64
2352         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2353                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2354                                            ~CPU_BASED_CR8_STORE_EXITING;
2355 #endif
2356         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2357                 min2 = 0;
2358                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2359                         SECONDARY_EXEC_WBINVD_EXITING |
2360                         SECONDARY_EXEC_ENABLE_VPID |
2361                         SECONDARY_EXEC_ENABLE_EPT |
2362                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2363                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2364                         SECONDARY_EXEC_RDTSCP;
2365                 if (adjust_vmx_controls(min2, opt2,
2366                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2367                                         &_cpu_based_2nd_exec_control) < 0)
2368                         return -EIO;
2369         }
2370 #ifndef CONFIG_X86_64
2371         if (!(_cpu_based_2nd_exec_control &
2372                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2373                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2374 #endif
2375         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2376                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2377                    enabled */
2378                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2379                                              CPU_BASED_CR3_STORE_EXITING |
2380                                              CPU_BASED_INVLPG_EXITING);
2381                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2382                       vmx_capability.ept, vmx_capability.vpid);
2383         }
2384
2385         min = 0;
2386 #ifdef CONFIG_X86_64
2387         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2388 #endif
2389         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2390         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2391                                 &_vmexit_control) < 0)
2392                 return -EIO;
2393
2394         min = 0;
2395         opt = VM_ENTRY_LOAD_IA32_PAT;
2396         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2397                                 &_vmentry_control) < 0)
2398                 return -EIO;
2399
2400         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2401
2402         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2403         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2404                 return -EIO;
2405
2406 #ifdef CONFIG_X86_64
2407         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2408         if (vmx_msr_high & (1u<<16))
2409                 return -EIO;
2410 #endif
2411
2412         /* Require Write-Back (WB) memory type for VMCS accesses. */
2413         if (((vmx_msr_high >> 18) & 15) != 6)
2414                 return -EIO;
2415
2416         vmcs_conf->size = vmx_msr_high & 0x1fff;
2417         vmcs_conf->order = get_order(vmcs_config.size);
2418         vmcs_conf->revision_id = vmx_msr_low;
2419
2420         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2421         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2422         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2423         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2424         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2425
2426         cpu_has_load_ia32_efer =
2427                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2428                                 VM_ENTRY_LOAD_IA32_EFER)
2429                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2430                                    VM_EXIT_LOAD_IA32_EFER);
2431
2432         return 0;
2433 }
2434
2435 static struct vmcs *alloc_vmcs_cpu(int cpu)
2436 {
2437         int node = cpu_to_node(cpu);
2438         struct page *pages;
2439         struct vmcs *vmcs;
2440
2441         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2442         if (!pages)
2443                 return NULL;
2444         vmcs = page_address(pages);
2445         memset(vmcs, 0, vmcs_config.size);
2446         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2447         return vmcs;
2448 }
2449
2450 static struct vmcs *alloc_vmcs(void)
2451 {
2452         return alloc_vmcs_cpu(raw_smp_processor_id());
2453 }
2454
2455 static void free_vmcs(struct vmcs *vmcs)
2456 {
2457         free_pages((unsigned long)vmcs, vmcs_config.order);
2458 }
2459
2460 /*
2461  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2462  */
2463 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2464 {
2465         if (!loaded_vmcs->vmcs)
2466                 return;
2467         loaded_vmcs_clear(loaded_vmcs);
2468         free_vmcs(loaded_vmcs->vmcs);
2469         loaded_vmcs->vmcs = NULL;
2470 }
2471
2472 static void free_kvm_area(void)
2473 {
2474         int cpu;
2475
2476         for_each_possible_cpu(cpu) {
2477                 free_vmcs(per_cpu(vmxarea, cpu));
2478                 per_cpu(vmxarea, cpu) = NULL;
2479         }
2480 }
2481
2482 static __init int alloc_kvm_area(void)
2483 {
2484         int cpu;
2485
2486         for_each_possible_cpu(cpu) {
2487                 struct vmcs *vmcs;
2488
2489                 vmcs = alloc_vmcs_cpu(cpu);
2490                 if (!vmcs) {
2491                         free_kvm_area();
2492                         return -ENOMEM;
2493                 }
2494
2495                 per_cpu(vmxarea, cpu) = vmcs;
2496         }
2497         return 0;
2498 }
2499
2500 static __init int hardware_setup(void)
2501 {
2502         if (setup_vmcs_config(&vmcs_config) < 0)
2503                 return -EIO;
2504
2505         if (boot_cpu_has(X86_FEATURE_NX))
2506                 kvm_enable_efer_bits(EFER_NX);
2507
2508         if (!cpu_has_vmx_vpid())
2509                 enable_vpid = 0;
2510
2511         if (!cpu_has_vmx_ept() ||
2512             !cpu_has_vmx_ept_4levels()) {
2513                 enable_ept = 0;
2514                 enable_unrestricted_guest = 0;
2515         }
2516
2517         if (!cpu_has_vmx_unrestricted_guest())
2518                 enable_unrestricted_guest = 0;
2519
2520         if (!cpu_has_vmx_flexpriority())
2521                 flexpriority_enabled = 0;
2522
2523         if (!cpu_has_vmx_tpr_shadow())
2524                 kvm_x86_ops->update_cr8_intercept = NULL;
2525
2526         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2527                 kvm_disable_largepages();
2528
2529         if (!cpu_has_vmx_ple())
2530                 ple_gap = 0;
2531
2532         if (nested)
2533                 nested_vmx_setup_ctls_msrs();
2534
2535         return alloc_kvm_area();
2536 }
2537
2538 static __exit void hardware_unsetup(void)
2539 {
2540         free_kvm_area();
2541 }
2542
2543 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2544 {
2545         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2546
2547         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2548                 vmcs_write16(sf->selector, save->selector);
2549                 vmcs_writel(sf->base, save->base);
2550                 vmcs_write32(sf->limit, save->limit);
2551                 vmcs_write32(sf->ar_bytes, save->ar);
2552         } else {
2553                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2554                         << AR_DPL_SHIFT;
2555                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2556         }
2557 }
2558
2559 static void enter_pmode(struct kvm_vcpu *vcpu)
2560 {
2561         unsigned long flags;
2562         struct vcpu_vmx *vmx = to_vmx(vcpu);
2563
2564         vmx->emulation_required = 1;
2565         vmx->rmode.vm86_active = 0;
2566
2567         vmx_segment_cache_clear(vmx);
2568
2569         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2570         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2571         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2572         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2573
2574         flags = vmcs_readl(GUEST_RFLAGS);
2575         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2576         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2577         vmcs_writel(GUEST_RFLAGS, flags);
2578
2579         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2580                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2581
2582         update_exception_bitmap(vcpu);
2583
2584         if (emulate_invalid_guest_state)
2585                 return;
2586
2587         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2588         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2589         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2590         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2591
2592         vmx_segment_cache_clear(vmx);
2593
2594         vmcs_write16(GUEST_SS_SELECTOR, 0);
2595         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2596
2597         vmcs_write16(GUEST_CS_SELECTOR,
2598                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2599         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2600 }
2601
2602 static gva_t rmode_tss_base(struct kvm *kvm)
2603 {
2604         if (!kvm->arch.tss_addr) {
2605                 struct kvm_memslots *slots;
2606                 gfn_t base_gfn;
2607
2608                 slots = kvm_memslots(kvm);
2609                 base_gfn = slots->memslots[0].base_gfn +
2610                                  kvm->memslots->memslots[0].npages - 3;
2611                 return base_gfn << PAGE_SHIFT;
2612         }
2613         return kvm->arch.tss_addr;
2614 }
2615
2616 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2617 {
2618         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2619
2620         save->selector = vmcs_read16(sf->selector);
2621         save->base = vmcs_readl(sf->base);
2622         save->limit = vmcs_read32(sf->limit);
2623         save->ar = vmcs_read32(sf->ar_bytes);
2624         vmcs_write16(sf->selector, save->base >> 4);
2625         vmcs_write32(sf->base, save->base & 0xffff0);
2626         vmcs_write32(sf->limit, 0xffff);
2627         vmcs_write32(sf->ar_bytes, 0xf3);
2628         if (save->base & 0xf)
2629                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2630                             " aligned when entering protected mode (seg=%d)",
2631                             seg);
2632 }
2633
2634 static void enter_rmode(struct kvm_vcpu *vcpu)
2635 {
2636         unsigned long flags;
2637         struct vcpu_vmx *vmx = to_vmx(vcpu);
2638
2639         if (enable_unrestricted_guest)
2640                 return;
2641
2642         vmx->emulation_required = 1;
2643         vmx->rmode.vm86_active = 1;
2644
2645         /*
2646          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2647          * vcpu. Call it here with phys address pointing 16M below 4G.
2648          */
2649         if (!vcpu->kvm->arch.tss_addr) {
2650                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2651                              "called before entering vcpu\n");
2652                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2653                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2654                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2655         }
2656
2657         vmx_segment_cache_clear(vmx);
2658
2659         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2660         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2661         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2662
2663         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2664         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2665
2666         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2667         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2668
2669         flags = vmcs_readl(GUEST_RFLAGS);
2670         vmx->rmode.save_rflags = flags;
2671
2672         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2673
2674         vmcs_writel(GUEST_RFLAGS, flags);
2675         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2676         update_exception_bitmap(vcpu);
2677
2678         if (emulate_invalid_guest_state)
2679                 goto continue_rmode;
2680
2681         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2682         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2683         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2684
2685         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
2686         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2687         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2688                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
2689         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2690
2691         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2692         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2693         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2694         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
2695
2696 continue_rmode:
2697         kvm_mmu_reset_context(vcpu);
2698 }
2699
2700 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2701 {
2702         struct vcpu_vmx *vmx = to_vmx(vcpu);
2703         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2704
2705         if (!msr)
2706                 return;
2707
2708         /*
2709          * Force kernel_gs_base reloading before EFER changes, as control
2710          * of this msr depends on is_long_mode().
2711          */
2712         vmx_load_host_state(to_vmx(vcpu));
2713         vcpu->arch.efer = efer;
2714         if (efer & EFER_LMA) {
2715                 vmcs_write32(VM_ENTRY_CONTROLS,
2716                              vmcs_read32(VM_ENTRY_CONTROLS) |
2717                              VM_ENTRY_IA32E_MODE);
2718                 msr->data = efer;
2719         } else {
2720                 vmcs_write32(VM_ENTRY_CONTROLS,
2721                              vmcs_read32(VM_ENTRY_CONTROLS) &
2722                              ~VM_ENTRY_IA32E_MODE);
2723
2724                 msr->data = efer & ~EFER_LME;
2725         }
2726         setup_msrs(vmx);
2727 }
2728
2729 #ifdef CONFIG_X86_64
2730
2731 static void enter_lmode(struct kvm_vcpu *vcpu)
2732 {
2733         u32 guest_tr_ar;
2734
2735         vmx_segment_cache_clear(to_vmx(vcpu));
2736
2737         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2738         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2739                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
2740                        __func__);
2741                 vmcs_write32(GUEST_TR_AR_BYTES,
2742                              (guest_tr_ar & ~AR_TYPE_MASK)
2743                              | AR_TYPE_BUSY_64_TSS);
2744         }
2745         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2746 }
2747
2748 static void exit_lmode(struct kvm_vcpu *vcpu)
2749 {
2750         vmcs_write32(VM_ENTRY_CONTROLS,
2751                      vmcs_read32(VM_ENTRY_CONTROLS)
2752                      & ~VM_ENTRY_IA32E_MODE);
2753         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2754 }
2755
2756 #endif
2757
2758 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2759 {
2760         vpid_sync_context(to_vmx(vcpu));
2761         if (enable_ept) {
2762                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2763                         return;
2764                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2765         }
2766 }
2767
2768 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2769 {
2770         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2771
2772         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2773         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2774 }
2775
2776 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2777 {
2778         if (enable_ept && is_paging(vcpu))
2779                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2780         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2781 }
2782
2783 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2784 {
2785         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2786
2787         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2788         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2789 }
2790
2791 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2792 {
2793         if (!test_bit(VCPU_EXREG_PDPTR,
2794                       (unsigned long *)&vcpu->arch.regs_dirty))
2795                 return;
2796
2797         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2798                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2799                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2800                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2801                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2802         }
2803 }
2804
2805 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2806 {
2807         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2808                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2809                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2810                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2811                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2812         }
2813
2814         __set_bit(VCPU_EXREG_PDPTR,
2815                   (unsigned long *)&vcpu->arch.regs_avail);
2816         __set_bit(VCPU_EXREG_PDPTR,
2817                   (unsigned long *)&vcpu->arch.regs_dirty);
2818 }
2819
2820 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2821
2822 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2823                                         unsigned long cr0,
2824                                         struct kvm_vcpu *vcpu)
2825 {
2826         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2827                 vmx_decache_cr3(vcpu);
2828         if (!(cr0 & X86_CR0_PG)) {
2829                 /* From paging/starting to nonpaging */
2830                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2831                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2832                              (CPU_BASED_CR3_LOAD_EXITING |
2833                               CPU_BASED_CR3_STORE_EXITING));
2834                 vcpu->arch.cr0 = cr0;
2835                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2836         } else if (!is_paging(vcpu)) {
2837                 /* From nonpaging to paging */
2838                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2839                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2840                              ~(CPU_BASED_CR3_LOAD_EXITING |
2841                                CPU_BASED_CR3_STORE_EXITING));
2842                 vcpu->arch.cr0 = cr0;
2843                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2844         }
2845
2846         if (!(cr0 & X86_CR0_WP))
2847                 *hw_cr0 &= ~X86_CR0_WP;
2848 }
2849
2850 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2851 {
2852         struct vcpu_vmx *vmx = to_vmx(vcpu);
2853         unsigned long hw_cr0;
2854
2855         if (enable_unrestricted_guest)
2856                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2857                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2858         else
2859                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2860
2861         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2862                 enter_pmode(vcpu);
2863
2864         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2865                 enter_rmode(vcpu);
2866
2867 #ifdef CONFIG_X86_64
2868         if (vcpu->arch.efer & EFER_LME) {
2869                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2870                         enter_lmode(vcpu);
2871                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2872                         exit_lmode(vcpu);
2873         }
2874 #endif
2875
2876         if (enable_ept)
2877                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2878
2879         if (!vcpu->fpu_active)
2880                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2881
2882         vmcs_writel(CR0_READ_SHADOW, cr0);
2883         vmcs_writel(GUEST_CR0, hw_cr0);
2884         vcpu->arch.cr0 = cr0;
2885         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2886 }
2887
2888 static u64 construct_eptp(unsigned long root_hpa)
2889 {
2890         u64 eptp;
2891
2892         /* TODO write the value reading from MSR */
2893         eptp = VMX_EPT_DEFAULT_MT |
2894                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2895         eptp |= (root_hpa & PAGE_MASK);
2896
2897         return eptp;
2898 }
2899
2900 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2901 {
2902         unsigned long guest_cr3;
2903         u64 eptp;
2904
2905         guest_cr3 = cr3;
2906         if (enable_ept) {
2907                 eptp = construct_eptp(cr3);
2908                 vmcs_write64(EPT_POINTER, eptp);
2909                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
2910                         vcpu->kvm->arch.ept_identity_map_addr;
2911                 ept_load_pdptrs(vcpu);
2912         }
2913
2914         vmx_flush_tlb(vcpu);
2915         vmcs_writel(GUEST_CR3, guest_cr3);
2916 }
2917
2918 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2919 {
2920         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
2921                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2922
2923         if (cr4 & X86_CR4_VMXE) {
2924                 /*
2925                  * To use VMXON (and later other VMX instructions), a guest
2926                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
2927                  * So basically the check on whether to allow nested VMX
2928                  * is here.
2929                  */
2930                 if (!nested_vmx_allowed(vcpu))
2931                         return 1;
2932         } else if (to_vmx(vcpu)->nested.vmxon)
2933                 return 1;
2934
2935         vcpu->arch.cr4 = cr4;
2936         if (enable_ept) {
2937                 if (!is_paging(vcpu)) {
2938                         hw_cr4 &= ~X86_CR4_PAE;
2939                         hw_cr4 |= X86_CR4_PSE;
2940                 } else if (!(cr4 & X86_CR4_PAE)) {
2941                         hw_cr4 &= ~X86_CR4_PAE;
2942                 }
2943         }
2944
2945         vmcs_writel(CR4_READ_SHADOW, cr4);
2946         vmcs_writel(GUEST_CR4, hw_cr4);
2947         return 0;
2948 }
2949
2950 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2951                             struct kvm_segment *var, int seg)
2952 {
2953         struct vcpu_vmx *vmx = to_vmx(vcpu);
2954         struct kvm_save_segment *save;
2955         u32 ar;
2956
2957         if (vmx->rmode.vm86_active
2958             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2959                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2960                 || seg == VCPU_SREG_GS)
2961             && !emulate_invalid_guest_state) {
2962                 switch (seg) {
2963                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2964                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2965                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2966                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2967                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2968                 default: BUG();
2969                 }
2970                 var->selector = save->selector;
2971                 var->base = save->base;
2972                 var->limit = save->limit;
2973                 ar = save->ar;
2974                 if (seg == VCPU_SREG_TR
2975                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
2976                         goto use_saved_rmode_seg;
2977         }
2978         var->base = vmx_read_guest_seg_base(vmx, seg);
2979         var->limit = vmx_read_guest_seg_limit(vmx, seg);
2980         var->selector = vmx_read_guest_seg_selector(vmx, seg);
2981         ar = vmx_read_guest_seg_ar(vmx, seg);
2982 use_saved_rmode_seg:
2983         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2984                 ar = 0;
2985         var->type = ar & 15;
2986         var->s = (ar >> 4) & 1;
2987         var->dpl = (ar >> 5) & 3;
2988         var->present = (ar >> 7) & 1;
2989         var->avl = (ar >> 12) & 1;
2990         var->l = (ar >> 13) & 1;
2991         var->db = (ar >> 14) & 1;
2992         var->g = (ar >> 15) & 1;
2993         var->unusable = (ar >> 16) & 1;
2994 }
2995
2996 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2997 {
2998         struct kvm_segment s;
2999
3000         if (to_vmx(vcpu)->rmode.vm86_active) {
3001                 vmx_get_segment(vcpu, &s, seg);
3002                 return s.base;
3003         }
3004         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3005 }
3006
3007 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3008 {
3009         if (!is_protmode(vcpu))
3010                 return 0;
3011
3012         if (!is_long_mode(vcpu)
3013             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3014                 return 3;
3015
3016         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3017 }
3018
3019 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3020 {
3021         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3022                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3023                 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
3024         }
3025         return to_vmx(vcpu)->cpl;
3026 }
3027
3028
3029 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3030 {
3031         u32 ar;
3032
3033         if (var->unusable)
3034                 ar = 1 << 16;
3035         else {
3036                 ar = var->type & 15;
3037                 ar |= (var->s & 1) << 4;
3038                 ar |= (var->dpl & 3) << 5;
3039                 ar |= (var->present & 1) << 7;
3040                 ar |= (var->avl & 1) << 12;
3041                 ar |= (var->l & 1) << 13;
3042                 ar |= (var->db & 1) << 14;
3043                 ar |= (var->g & 1) << 15;
3044         }
3045         if (ar == 0) /* a 0 value means unusable */
3046                 ar = AR_UNUSABLE_MASK;
3047
3048         return ar;
3049 }
3050
3051 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3052                             struct kvm_segment *var, int seg)
3053 {
3054         struct vcpu_vmx *vmx = to_vmx(vcpu);
3055         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3056         u32 ar;
3057
3058         vmx_segment_cache_clear(vmx);
3059
3060         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3061                 vmcs_write16(sf->selector, var->selector);
3062                 vmx->rmode.tr.selector = var->selector;
3063                 vmx->rmode.tr.base = var->base;
3064                 vmx->rmode.tr.limit = var->limit;
3065                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3066                 return;
3067         }
3068         vmcs_writel(sf->base, var->base);
3069         vmcs_write32(sf->limit, var->limit);
3070         vmcs_write16(sf->selector, var->selector);
3071         if (vmx->rmode.vm86_active && var->s) {
3072                 /*
3073                  * Hack real-mode segments into vm86 compatibility.
3074                  */
3075                 if (var->base == 0xffff0000 && var->selector == 0xf000)
3076                         vmcs_writel(sf->base, 0xf0000);
3077                 ar = 0xf3;
3078         } else
3079                 ar = vmx_segment_access_rights(var);
3080
3081         /*
3082          *   Fix the "Accessed" bit in AR field of segment registers for older
3083          * qemu binaries.
3084          *   IA32 arch specifies that at the time of processor reset the
3085          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3086          * is setting it to 0 in the usedland code. This causes invalid guest
3087          * state vmexit when "unrestricted guest" mode is turned on.
3088          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3089          * tree. Newer qemu binaries with that qemu fix would not need this
3090          * kvm hack.
3091          */
3092         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3093                 ar |= 0x1; /* Accessed */
3094
3095         vmcs_write32(sf->ar_bytes, ar);
3096         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3097 }
3098
3099 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3100 {
3101         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3102
3103         *db = (ar >> 14) & 1;
3104         *l = (ar >> 13) & 1;
3105 }
3106
3107 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3108 {
3109         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3110         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3111 }
3112
3113 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3114 {
3115         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3116         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3117 }
3118
3119 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3120 {
3121         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3122         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3123 }
3124
3125 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3126 {
3127         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3128         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3129 }
3130
3131 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3132 {
3133         struct kvm_segment var;
3134         u32 ar;
3135
3136         vmx_get_segment(vcpu, &var, seg);
3137         ar = vmx_segment_access_rights(&var);
3138
3139         if (var.base != (var.selector << 4))
3140                 return false;
3141         if (var.limit != 0xffff)
3142                 return false;
3143         if (ar != 0xf3)
3144                 return false;
3145
3146         return true;
3147 }
3148
3149 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3150 {
3151         struct kvm_segment cs;
3152         unsigned int cs_rpl;
3153
3154         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3155         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3156
3157         if (cs.unusable)
3158                 return false;
3159         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3160                 return false;
3161         if (!cs.s)
3162                 return false;
3163         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3164                 if (cs.dpl > cs_rpl)
3165                         return false;
3166         } else {
3167                 if (cs.dpl != cs_rpl)
3168                         return false;
3169         }
3170         if (!cs.present)
3171                 return false;
3172
3173         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3174         return true;
3175 }
3176
3177 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3178 {
3179         struct kvm_segment ss;
3180         unsigned int ss_rpl;
3181
3182         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3183         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3184
3185         if (ss.unusable)
3186                 return true;
3187         if (ss.type != 3 && ss.type != 7)
3188                 return false;
3189         if (!ss.s)
3190                 return false;
3191         if (ss.dpl != ss_rpl) /* DPL != RPL */
3192                 return false;
3193         if (!ss.present)
3194                 return false;
3195
3196         return true;
3197 }
3198
3199 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3200 {
3201         struct kvm_segment var;
3202         unsigned int rpl;
3203
3204         vmx_get_segment(vcpu, &var, seg);
3205         rpl = var.selector & SELECTOR_RPL_MASK;
3206
3207         if (var.unusable)
3208                 return true;
3209         if (!var.s)
3210                 return false;
3211         if (!var.present)
3212                 return false;
3213         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3214                 if (var.dpl < rpl) /* DPL < RPL */
3215                         return false;
3216         }
3217
3218         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3219          * rights flags
3220          */
3221         return true;
3222 }
3223
3224 static bool tr_valid(struct kvm_vcpu *vcpu)
3225 {
3226         struct kvm_segment tr;
3227
3228         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3229
3230         if (tr.unusable)
3231                 return false;
3232         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3233                 return false;
3234         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3235                 return false;
3236         if (!tr.present)
3237                 return false;
3238
3239         return true;
3240 }
3241
3242 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3243 {
3244         struct kvm_segment ldtr;
3245
3246         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3247
3248         if (ldtr.unusable)
3249                 return true;
3250         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3251                 return false;
3252         if (ldtr.type != 2)
3253                 return false;
3254         if (!ldtr.present)
3255                 return false;
3256
3257         return true;
3258 }
3259
3260 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3261 {
3262         struct kvm_segment cs, ss;
3263
3264         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3265         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3266
3267         return ((cs.selector & SELECTOR_RPL_MASK) ==
3268                  (ss.selector & SELECTOR_RPL_MASK));
3269 }
3270
3271 /*
3272  * Check if guest state is valid. Returns true if valid, false if
3273  * not.
3274  * We assume that registers are always usable
3275  */
3276 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3277 {
3278         /* real mode guest state checks */
3279         if (!is_protmode(vcpu)) {
3280                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3281                         return false;
3282                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3283                         return false;
3284                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3285                         return false;
3286                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3287                         return false;
3288                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3289                         return false;
3290                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3291                         return false;
3292         } else {
3293         /* protected mode guest state checks */
3294                 if (!cs_ss_rpl_check(vcpu))
3295                         return false;
3296                 if (!code_segment_valid(vcpu))
3297                         return false;
3298                 if (!stack_segment_valid(vcpu))
3299                         return false;
3300                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3301                         return false;
3302                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3303                         return false;
3304                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3305                         return false;
3306                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3307                         return false;
3308                 if (!tr_valid(vcpu))
3309                         return false;
3310                 if (!ldtr_valid(vcpu))
3311                         return false;
3312         }
3313         /* TODO:
3314          * - Add checks on RIP
3315          * - Add checks on RFLAGS
3316          */
3317
3318         return true;
3319 }
3320
3321 static int init_rmode_tss(struct kvm *kvm)
3322 {
3323         gfn_t fn;
3324         u16 data = 0;
3325         int r, idx, ret = 0;
3326
3327         idx = srcu_read_lock(&kvm->srcu);
3328         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3329         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3330         if (r < 0)
3331                 goto out;
3332         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3333         r = kvm_write_guest_page(kvm, fn++, &data,
3334                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3335         if (r < 0)
3336                 goto out;
3337         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3338         if (r < 0)
3339                 goto out;
3340         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3341         if (r < 0)
3342                 goto out;
3343         data = ~0;
3344         r = kvm_write_guest_page(kvm, fn, &data,
3345                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3346                                  sizeof(u8));
3347         if (r < 0)
3348                 goto out;
3349
3350         ret = 1;
3351 out:
3352         srcu_read_unlock(&kvm->srcu, idx);
3353         return ret;
3354 }
3355
3356 static int init_rmode_identity_map(struct kvm *kvm)
3357 {
3358         int i, idx, r, ret;
3359         pfn_t identity_map_pfn;
3360         u32 tmp;
3361
3362         if (!enable_ept)
3363                 return 1;
3364         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3365                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3366                         "haven't been allocated!\n");
3367                 return 0;
3368         }
3369         if (likely(kvm->arch.ept_identity_pagetable_done))
3370                 return 1;
3371         ret = 0;
3372         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3373         idx = srcu_read_lock(&kvm->srcu);
3374         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3375         if (r < 0)
3376                 goto out;
3377         /* Set up identity-mapping pagetable for EPT in real mode */
3378         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3379                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3380                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3381                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3382                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3383                 if (r < 0)
3384                         goto out;
3385         }
3386         kvm->arch.ept_identity_pagetable_done = true;
3387         ret = 1;
3388 out:
3389         srcu_read_unlock(&kvm->srcu, idx);
3390         return ret;
3391 }
3392
3393 static void seg_setup(int seg)
3394 {
3395         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3396         unsigned int ar;
3397
3398         vmcs_write16(sf->selector, 0);
3399         vmcs_writel(sf->base, 0);
3400         vmcs_write32(sf->limit, 0xffff);
3401         if (enable_unrestricted_guest) {
3402                 ar = 0x93;
3403                 if (seg == VCPU_SREG_CS)
3404                         ar |= 0x08; /* code segment */
3405         } else
3406                 ar = 0xf3;
3407
3408         vmcs_write32(sf->ar_bytes, ar);
3409 }
3410
3411 static int alloc_apic_access_page(struct kvm *kvm)
3412 {
3413         struct kvm_userspace_memory_region kvm_userspace_mem;
3414         int r = 0;
3415
3416         mutex_lock(&kvm->slots_lock);
3417         if (kvm->arch.apic_access_page)
3418                 goto out;
3419         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3420         kvm_userspace_mem.flags = 0;
3421         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3422         kvm_userspace_mem.memory_size = PAGE_SIZE;
3423         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3424         if (r)
3425                 goto out;
3426
3427         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3428 out:
3429         mutex_unlock(&kvm->slots_lock);
3430         return r;
3431 }
3432
3433 static int alloc_identity_pagetable(struct kvm *kvm)
3434 {
3435         struct kvm_userspace_memory_region kvm_userspace_mem;
3436         int r = 0;
3437
3438         mutex_lock(&kvm->slots_lock);
3439         if (kvm->arch.ept_identity_pagetable)
3440                 goto out;
3441         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3442         kvm_userspace_mem.flags = 0;
3443         kvm_userspace_mem.guest_phys_addr =
3444                 kvm->arch.ept_identity_map_addr;
3445         kvm_userspace_mem.memory_size = PAGE_SIZE;
3446         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3447         if (r)
3448                 goto out;
3449
3450         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3451                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3452 out:
3453         mutex_unlock(&kvm->slots_lock);
3454         return r;
3455 }
3456
3457 static void allocate_vpid(struct vcpu_vmx *vmx)
3458 {
3459         int vpid;
3460
3461         vmx->vpid = 0;
3462         if (!enable_vpid)
3463                 return;
3464         spin_lock(&vmx_vpid_lock);
3465         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3466         if (vpid < VMX_NR_VPIDS) {
3467                 vmx->vpid = vpid;
3468                 __set_bit(vpid, vmx_vpid_bitmap);
3469         }
3470         spin_unlock(&vmx_vpid_lock);
3471 }
3472
3473 static void free_vpid(struct vcpu_vmx *vmx)
3474 {
3475         if (!enable_vpid)
3476                 return;
3477         spin_lock(&vmx_vpid_lock);
3478         if (vmx->vpid != 0)
3479                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3480         spin_unlock(&vmx_vpid_lock);
3481 }
3482
3483 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3484 {
3485         int f = sizeof(unsigned long);
3486
3487         if (!cpu_has_vmx_msr_bitmap())
3488                 return;
3489
3490         /*
3491          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3492          * have the write-low and read-high bitmap offsets the wrong way round.
3493          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3494          */
3495         if (msr <= 0x1fff) {
3496                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3497                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3498         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3499                 msr &= 0x1fff;
3500                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3501                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3502         }
3503 }
3504
3505 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3506 {
3507         if (!longmode_only)
3508                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3509         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3510 }
3511
3512 /*
3513  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3514  * will not change in the lifetime of the guest.
3515  * Note that host-state that does change is set elsewhere. E.g., host-state
3516  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3517  */
3518 static void vmx_set_constant_host_state(void)
3519 {
3520         u32 low32, high32;
3521         unsigned long tmpl;
3522         struct desc_ptr dt;
3523
3524         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
3525         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
3526         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
3527
3528         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3529         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3530         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3531         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3532         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3533
3534         native_store_idt(&dt);
3535         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3536
3537         asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3538         vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3539
3540         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3541         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3542         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3543         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3544
3545         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3546                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3547                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3548         }
3549 }
3550
3551 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3552 {
3553         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3554         if (enable_ept)
3555                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3556         if (is_guest_mode(&vmx->vcpu))
3557                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3558                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3559         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3560 }
3561
3562 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3563 {
3564         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3565         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3566                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3567 #ifdef CONFIG_X86_64
3568                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3569                                 CPU_BASED_CR8_LOAD_EXITING;
3570 #endif
3571         }
3572         if (!enable_ept)
3573                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3574                                 CPU_BASED_CR3_LOAD_EXITING  |
3575                                 CPU_BASED_INVLPG_EXITING;
3576         return exec_control;
3577 }
3578
3579 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3580 {
3581         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3582         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3583                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3584         if (vmx->vpid == 0)
3585                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3586         if (!enable_ept) {
3587                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3588                 enable_unrestricted_guest = 0;
3589         }
3590         if (!enable_unrestricted_guest)
3591                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3592         if (!ple_gap)
3593                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3594         return exec_control;
3595 }
3596
3597 static void ept_set_mmio_spte_mask(void)
3598 {
3599         /*
3600          * EPT Misconfigurations can be generated if the value of bits 2:0
3601          * of an EPT paging-structure entry is 110b (write/execute).
3602          * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3603          * spte.
3604          */
3605         kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3606 }
3607
3608 /*
3609  * Sets up the vmcs for emulated real mode.
3610  */
3611 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3612 {
3613 #ifdef CONFIG_X86_64
3614         unsigned long a;
3615 #endif
3616         int i;
3617
3618         /* I/O */
3619         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3620         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3621
3622         if (cpu_has_vmx_msr_bitmap())
3623                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3624
3625         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3626
3627         /* Control */
3628         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3629                 vmcs_config.pin_based_exec_ctrl);
3630
3631         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3632
3633         if (cpu_has_secondary_exec_ctrls()) {
3634                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3635                                 vmx_secondary_exec_control(vmx));
3636         }
3637
3638         if (ple_gap) {
3639                 vmcs_write32(PLE_GAP, ple_gap);
3640                 vmcs_write32(PLE_WINDOW, ple_window);
3641         }
3642
3643         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3644         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
3645         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
3646
3647         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
3648         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
3649         vmx_set_constant_host_state();
3650 #ifdef CONFIG_X86_64
3651         rdmsrl(MSR_FS_BASE, a);
3652         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3653         rdmsrl(MSR_GS_BASE, a);
3654         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3655 #else
3656         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3657         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3658 #endif
3659
3660         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3661         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3662         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3663         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3664         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3665
3666         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3667                 u32 msr_low, msr_high;
3668                 u64 host_pat;
3669                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3670                 host_pat = msr_low | ((u64) msr_high << 32);
3671                 /* Write the default value follow host pat */
3672                 vmcs_write64(GUEST_IA32_PAT, host_pat);
3673                 /* Keep arch.pat sync with GUEST_IA32_PAT */
3674                 vmx->vcpu.arch.pat = host_pat;
3675         }
3676
3677         for (i = 0; i < NR_VMX_MSR; ++i) {
3678                 u32 index = vmx_msr_index[i];
3679                 u32 data_low, data_high;
3680                 int j = vmx->nmsrs;
3681
3682                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3683                         continue;
3684                 if (wrmsr_safe(index, data_low, data_high) < 0)
3685                         continue;
3686                 vmx->guest_msrs[j].index = i;
3687                 vmx->guest_msrs[j].data = 0;
3688                 vmx->guest_msrs[j].mask = -1ull;
3689                 ++vmx->nmsrs;
3690         }
3691
3692         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3693
3694         /* 22.2.1, 20.8.1 */
3695         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3696
3697         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3698         set_cr4_guest_host_mask(vmx);
3699
3700         kvm_write_tsc(&vmx->vcpu, 0);
3701
3702         return 0;
3703 }
3704
3705 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3706 {
3707         struct vcpu_vmx *vmx = to_vmx(vcpu);
3708         u64 msr;
3709         int ret;
3710
3711         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3712
3713         vmx->rmode.vm86_active = 0;
3714
3715         vmx->soft_vnmi_blocked = 0;
3716
3717         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3718         kvm_set_cr8(&vmx->vcpu, 0);
3719         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3720         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3721                 msr |= MSR_IA32_APICBASE_BSP;
3722         kvm_set_apic_base(&vmx->vcpu, msr);
3723
3724         ret = fx_init(&vmx->vcpu);
3725         if (ret != 0)
3726                 goto out;
3727
3728         vmx_segment_cache_clear(vmx);
3729
3730         seg_setup(VCPU_SREG_CS);
3731         /*
3732          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3733          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
3734          */
3735         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3736                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3737                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3738         } else {
3739                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3740                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3741         }
3742
3743         seg_setup(VCPU_SREG_DS);
3744         seg_setup(VCPU_SREG_ES);
3745         seg_setup(VCPU_SREG_FS);
3746         seg_setup(VCPU_SREG_GS);
3747         seg_setup(VCPU_SREG_SS);
3748
3749         vmcs_write16(GUEST_TR_SELECTOR, 0);
3750         vmcs_writel(GUEST_TR_BASE, 0);
3751         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3752         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3753
3754         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3755         vmcs_writel(GUEST_LDTR_BASE, 0);
3756         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3757         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3758
3759         vmcs_write32(GUEST_SYSENTER_CS, 0);
3760         vmcs_writel(GUEST_SYSENTER_ESP, 0);
3761         vmcs_writel(GUEST_SYSENTER_EIP, 0);
3762
3763         vmcs_writel(GUEST_RFLAGS, 0x02);
3764         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3765                 kvm_rip_write(vcpu, 0xfff0);
3766         else
3767                 kvm_rip_write(vcpu, 0);
3768         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3769
3770         vmcs_writel(GUEST_DR7, 0x400);
3771
3772         vmcs_writel(GUEST_GDTR_BASE, 0);
3773         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3774
3775         vmcs_writel(GUEST_IDTR_BASE, 0);
3776         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3777
3778         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3779         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3780         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3781
3782         /* Special registers */
3783         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3784
3785         setup_msrs(vmx);
3786
3787         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
3788
3789         if (cpu_has_vmx_tpr_shadow()) {
3790                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3791                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3792                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3793                                      __pa(vmx->vcpu.arch.apic->regs));
3794                 vmcs_write32(TPR_THRESHOLD, 0);
3795         }
3796
3797         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3798                 vmcs_write64(APIC_ACCESS_ADDR,
3799                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3800
3801         if (vmx->vpid != 0)
3802                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3803
3804         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3805         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3806         vmx_set_cr4(&vmx->vcpu, 0);
3807         vmx_set_efer(&vmx->vcpu, 0);
3808         vmx_fpu_activate(&vmx->vcpu);
3809         update_exception_bitmap(&vmx->vcpu);
3810
3811         vpid_sync_context(vmx);
3812
3813         ret = 0;
3814
3815         /* HACK: Don't enable emulation on guest boot/reset */
3816         vmx->emulation_required = 0;
3817
3818 out:
3819         return ret;
3820 }
3821
3822 /*
3823  * In nested virtualization, check if L1 asked to exit on external interrupts.
3824  * For most existing hypervisors, this will always return true.
3825  */
3826 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3827 {
3828         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3829                 PIN_BASED_EXT_INTR_MASK;
3830 }
3831
3832 static void enable_irq_window(struct kvm_vcpu *vcpu)
3833 {
3834         u32 cpu_based_vm_exec_control;
3835         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
3836                 /* We can get here when nested_run_pending caused
3837                  * vmx_interrupt_allowed() to return false. In this case, do
3838                  * nothing - the interrupt will be injected later.
3839                  */
3840                 return;
3841
3842         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3843         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3844         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3845 }
3846
3847 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3848 {
3849         u32 cpu_based_vm_exec_control;
3850
3851         if (!cpu_has_virtual_nmis()) {
3852                 enable_irq_window(vcpu);
3853                 return;
3854         }
3855
3856         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3857                 enable_irq_window(vcpu);
3858                 return;
3859         }
3860         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3861         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3862         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3863 }
3864
3865 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
3866 {
3867         struct vcpu_vmx *vmx = to_vmx(vcpu);
3868         uint32_t intr;
3869         int irq = vcpu->arch.interrupt.nr;
3870
3871         trace_kvm_inj_virq(irq);
3872
3873         ++vcpu->stat.irq_injections;
3874         if (vmx->rmode.vm86_active) {
3875                 int inc_eip = 0;
3876                 if (vcpu->arch.interrupt.soft)
3877                         inc_eip = vcpu->arch.event_exit_inst_len;
3878                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
3879                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3880                 return;
3881         }
3882         intr = irq | INTR_INFO_VALID_MASK;
3883         if (vcpu->arch.interrupt.soft) {
3884                 intr |= INTR_TYPE_SOFT_INTR;
3885                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3886                              vmx->vcpu.arch.event_exit_inst_len);
3887         } else
3888                 intr |= INTR_TYPE_EXT_INTR;
3889         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
3890         vmx_clear_hlt(vcpu);
3891 }
3892
3893 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
3894 {
3895         struct vcpu_vmx *vmx = to_vmx(vcpu);
3896
3897         if (is_guest_mode(vcpu))
3898                 return;
3899
3900         if (!cpu_has_virtual_nmis()) {
3901                 /*
3902                  * Tracking the NMI-blocked state in software is built upon
3903                  * finding the next open IRQ window. This, in turn, depends on
3904                  * well-behaving guests: They have to keep IRQs disabled at
3905                  * least as long as the NMI handler runs. Otherwise we may
3906                  * cause NMI nesting, maybe breaking the guest. But as this is
3907                  * highly unlikely, we can live with the residual risk.
3908                  */
3909                 vmx->soft_vnmi_blocked = 1;
3910                 vmx->vnmi_blocked_time = 0;
3911         }
3912
3913         ++vcpu->stat.nmi_injections;
3914         vmx->nmi_known_unmasked = false;
3915         if (vmx->rmode.vm86_active) {
3916                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
3917                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3918                 return;
3919         }
3920         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
3921                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
3922         vmx_clear_hlt(vcpu);
3923 }
3924
3925 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
3926 {
3927         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
3928                 return 0;
3929
3930         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3931                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
3932                    | GUEST_INTR_STATE_NMI));
3933 }
3934
3935 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3936 {
3937         if (!cpu_has_virtual_nmis())
3938                 return to_vmx(vcpu)->soft_vnmi_blocked;
3939         if (to_vmx(vcpu)->nmi_known_unmasked)
3940                 return false;
3941         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3942 }
3943
3944 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3945 {
3946         struct vcpu_vmx *vmx = to_vmx(vcpu);
3947
3948         if (!cpu_has_virtual_nmis()) {
3949                 if (vmx->soft_vnmi_blocked != masked) {
3950                         vmx->soft_vnmi_blocked = masked;
3951                         vmx->vnmi_blocked_time = 0;
3952                 }
3953         } else {
3954                 vmx->nmi_known_unmasked = !masked;
3955                 if (masked)
3956                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3957                                       GUEST_INTR_STATE_NMI);
3958                 else
3959                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3960                                         GUEST_INTR_STATE_NMI);
3961         }
3962 }
3963
3964 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
3965 {
3966         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
3967                 struct vmcs12 *vmcs12;
3968                 if (to_vmx(vcpu)->nested.nested_run_pending)
3969                         return 0;
3970                 nested_vmx_vmexit(vcpu);
3971                 vmcs12 = get_vmcs12(vcpu);
3972                 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
3973                 vmcs12->vm_exit_intr_info = 0;
3974                 /* fall through to normal code, but now in L1, not L2 */
3975         }
3976
3977         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
3978                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3979                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
3980 }
3981
3982 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
3983 {
3984         int ret;
3985         struct kvm_userspace_memory_region tss_mem = {
3986                 .slot = TSS_PRIVATE_MEMSLOT,
3987                 .guest_phys_addr = addr,
3988                 .memory_size = PAGE_SIZE * 3,
3989                 .flags = 0,
3990         };
3991
3992         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3993         if (ret)
3994                 return ret;
3995         kvm->arch.tss_addr = addr;
3996         if (!init_rmode_tss(kvm))
3997                 return  -ENOMEM;
3998
3999         return 0;
4000 }
4001
4002 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4003                                   int vec, u32 err_code)
4004 {
4005         /*
4006          * Instruction with address size override prefix opcode 0x67
4007          * Cause the #SS fault with 0 error code in VM86 mode.
4008          */
4009         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
4010                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
4011                         return 1;
4012         /*
4013          * Forward all other exceptions that are valid in real mode.
4014          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4015          *        the required debugging infrastructure rework.
4016          */
4017         switch (vec) {
4018         case DB_VECTOR:
4019                 if (vcpu->guest_debug &
4020                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4021                         return 0;
4022                 kvm_queue_exception(vcpu, vec);
4023                 return 1;
4024         case BP_VECTOR:
4025                 /*
4026                  * Update instruction length as we may reinject the exception
4027                  * from user space while in guest debugging mode.
4028                  */
4029                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4030                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4031                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4032                         return 0;
4033                 /* fall through */
4034         case DE_VECTOR:
4035         case OF_VECTOR:
4036         case BR_VECTOR:
4037         case UD_VECTOR:
4038         case DF_VECTOR:
4039         case SS_VECTOR:
4040         case GP_VECTOR:
4041         case MF_VECTOR:
4042                 kvm_queue_exception(vcpu, vec);
4043                 return 1;
4044         }
4045         return 0;
4046 }
4047
4048 /*
4049  * Trigger machine check on the host. We assume all the MSRs are already set up
4050  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4051  * We pass a fake environment to the machine check handler because we want
4052  * the guest to be always treated like user space, no matter what context
4053  * it used internally.
4054  */
4055 static void kvm_machine_check(void)
4056 {
4057 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4058         struct pt_regs regs = {
4059                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4060                 .flags = X86_EFLAGS_IF,
4061         };
4062
4063         do_machine_check(&regs, 0);
4064 #endif
4065 }
4066
4067 static int handle_machine_check(struct kvm_vcpu *vcpu)
4068 {
4069         /* already handled by vcpu_run */
4070         return 1;
4071 }
4072
4073 static int handle_exception(struct kvm_vcpu *vcpu)
4074 {
4075         struct vcpu_vmx *vmx = to_vmx(vcpu);
4076         struct kvm_run *kvm_run = vcpu->run;
4077         u32 intr_info, ex_no, error_code;
4078         unsigned long cr2, rip, dr6;
4079         u32 vect_info;
4080         enum emulation_result er;
4081
4082         vect_info = vmx->idt_vectoring_info;
4083         intr_info = vmx->exit_intr_info;
4084
4085         if (is_machine_check(intr_info))
4086                 return handle_machine_check(vcpu);
4087
4088         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4089             !is_page_fault(intr_info)) {
4090                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4091                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4092                 vcpu->run->internal.ndata = 2;
4093                 vcpu->run->internal.data[0] = vect_info;
4094                 vcpu->run->internal.data[1] = intr_info;
4095                 return 0;
4096         }
4097
4098         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4099                 return 1;  /* already handled by vmx_vcpu_run() */
4100
4101         if (is_no_device(intr_info)) {
4102                 vmx_fpu_activate(vcpu);
4103                 return 1;
4104         }
4105
4106         if (is_invalid_opcode(intr_info)) {
4107                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4108                 if (er != EMULATE_DONE)
4109                         kvm_queue_exception(vcpu, UD_VECTOR);
4110                 return 1;
4111         }
4112
4113         error_code = 0;
4114         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4115                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4116         if (is_page_fault(intr_info)) {
4117                 /* EPT won't cause page fault directly */
4118                 if (enable_ept)
4119                         BUG();
4120                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4121                 trace_kvm_page_fault(cr2, error_code);
4122
4123                 if (kvm_event_needs_reinjection(vcpu))
4124                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4125                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4126         }
4127
4128         if (vmx->rmode.vm86_active &&
4129             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4130                                                                 error_code)) {
4131                 if (vcpu->arch.halt_request) {
4132                         vcpu->arch.halt_request = 0;
4133                         return kvm_emulate_halt(vcpu);
4134                 }
4135                 return 1;
4136         }
4137
4138         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4139         switch (ex_no) {
4140         case DB_VECTOR:
4141                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4142                 if (!(vcpu->guest_debug &
4143                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4144                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4145                         kvm_queue_exception(vcpu, DB_VECTOR);
4146                         return 1;
4147                 }
4148                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4149                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4150                 /* fall through */
4151         case BP_VECTOR:
4152                 /*
4153                  * Update instruction length as we may reinject #BP from
4154                  * user space while in guest debugging mode. Reading it for
4155                  * #DB as well causes no harm, it is not used in that case.
4156                  */
4157                 vmx->vcpu.arch.event_exit_inst_len =
4158                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4159                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4160                 rip = kvm_rip_read(vcpu);
4161                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4162                 kvm_run->debug.arch.exception = ex_no;
4163                 break;
4164         default:
4165                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4166                 kvm_run->ex.exception = ex_no;
4167                 kvm_run->ex.error_code = error_code;
4168                 break;
4169         }
4170         return 0;
4171 }
4172
4173 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4174 {
4175         ++vcpu->stat.irq_exits;
4176         return 1;
4177 }
4178
4179 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4180 {
4181         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4182         return 0;
4183 }
4184
4185 static int handle_io(struct kvm_vcpu *vcpu)
4186 {
4187         unsigned long exit_qualification;
4188         int size, in, string;
4189         unsigned port;
4190
4191         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4192         string = (exit_qualification & 16) != 0;
4193         in = (exit_qualification & 8) != 0;
4194
4195         ++vcpu->stat.io_exits;
4196
4197         if (string || in)
4198                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4199
4200         port = exit_qualification >> 16;
4201         size = (exit_qualification & 7) + 1;
4202         skip_emulated_instruction(vcpu);
4203
4204         return kvm_fast_pio_out(vcpu, size, port);
4205 }
4206
4207 static void
4208 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4209 {
4210         /*
4211          * Patch in the VMCALL instruction:
4212          */
4213         hypercall[0] = 0x0f;
4214         hypercall[1] = 0x01;
4215         hypercall[2] = 0xc1;
4216 }
4217
4218 /* called to set cr0 as approriate for a mov-to-cr0 exit. */
4219 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4220 {
4221         if (to_vmx(vcpu)->nested.vmxon &&
4222             ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4223                 return 1;
4224
4225         if (is_guest_mode(vcpu)) {
4226                 /*
4227                  * We get here when L2 changed cr0 in a way that did not change
4228                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4229                  * but did change L0 shadowed bits. This can currently happen
4230                  * with the TS bit: L0 may want to leave TS on (for lazy fpu
4231                  * loading) while pretending to allow the guest to change it.
4232                  */
4233                 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4234                          (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4235                         return 1;
4236                 vmcs_writel(CR0_READ_SHADOW, val);
4237                 return 0;
4238         } else
4239                 return kvm_set_cr0(vcpu, val);
4240 }
4241
4242 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4243 {
4244         if (is_guest_mode(vcpu)) {
4245                 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4246                          (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4247                         return 1;
4248                 vmcs_writel(CR4_READ_SHADOW, val);
4249                 return 0;
4250         } else
4251                 return kvm_set_cr4(vcpu, val);
4252 }
4253
4254 /* called to set cr0 as approriate for clts instruction exit. */
4255 static void handle_clts(struct kvm_vcpu *vcpu)
4256 {
4257         if (is_guest_mode(vcpu)) {
4258                 /*
4259                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4260                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4261                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4262                  */
4263                 vmcs_writel(CR0_READ_SHADOW,
4264                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4265                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4266         } else
4267                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4268 }
4269
4270 static int handle_cr(struct kvm_vcpu *vcpu)
4271 {
4272         unsigned long exit_qualification, val;
4273         int cr;
4274         int reg;
4275         int err;
4276
4277         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4278         cr = exit_qualification & 15;
4279         reg = (exit_qualification >> 8) & 15;
4280         switch ((exit_qualification >> 4) & 3) {
4281         case 0: /* mov to cr */
4282                 val = kvm_register_read(vcpu, reg);
4283                 trace_kvm_cr_write(cr, val);
4284                 switch (cr) {
4285                 case 0:
4286                         err = handle_set_cr0(vcpu, val);
4287                         kvm_complete_insn_gp(vcpu, err);
4288                         return 1;
4289                 case 3:
4290                         err = kvm_set_cr3(vcpu, val);
4291                         kvm_complete_insn_gp(vcpu, err);
4292                         return 1;
4293                 case 4:
4294                         err = handle_set_cr4(vcpu, val);
4295                         kvm_complete_insn_gp(vcpu, err);
4296                         return 1;
4297                 case 8: {
4298                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4299                                 u8 cr8 = kvm_register_read(vcpu, reg);
4300                                 err = kvm_set_cr8(vcpu, cr8);
4301                                 kvm_complete_insn_gp(vcpu, err);
4302                                 if (irqchip_in_kernel(vcpu->kvm))
4303                                         return 1;
4304                                 if (cr8_prev <= cr8)
4305                                         return 1;
4306                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4307                                 return 0;
4308                         }
4309                 };
4310                 break;
4311         case 2: /* clts */
4312                 handle_clts(vcpu);
4313                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4314                 skip_emulated_instruction(vcpu);
4315                 vmx_fpu_activate(vcpu);
4316                 return 1;
4317         case 1: /*mov from cr*/
4318                 switch (cr) {
4319                 case 3:
4320                         val = kvm_read_cr3(vcpu);
4321                         kvm_register_write(vcpu, reg, val);
4322                         trace_kvm_cr_read(cr, val);
4323                         skip_emulated_instruction(vcpu);
4324                         return 1;
4325                 case 8:
4326                         val = kvm_get_cr8(vcpu);
4327                         kvm_register_write(vcpu, reg, val);
4328                         trace_kvm_cr_read(cr, val);
4329                         skip_emulated_instruction(vcpu);
4330                         return 1;
4331                 }
4332                 break;
4333         case 3: /* lmsw */
4334                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4335                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4336                 kvm_lmsw(vcpu, val);
4337
4338                 skip_emulated_instruction(vcpu);
4339                 return 1;
4340         default:
4341                 break;
4342         }
4343         vcpu->run->exit_reason = 0;
4344         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4345                (int)(exit_qualification >> 4) & 3, cr);
4346         return 0;
4347 }
4348
4349 static int handle_dr(struct kvm_vcpu *vcpu)
4350 {
4351         unsigned long exit_qualification;
4352         int dr, reg;
4353
4354         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4355         if (!kvm_require_cpl(vcpu, 0))
4356                 return 1;
4357         dr = vmcs_readl(GUEST_DR7);
4358         if (dr & DR7_GD) {
4359                 /*
4360                  * As the vm-exit takes precedence over the debug trap, we
4361                  * need to emulate the latter, either for the host or the
4362                  * guest debugging itself.
4363                  */
4364                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4365                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4366                         vcpu->run->debug.arch.dr7 = dr;
4367                         vcpu->run->debug.arch.pc =
4368                                 vmcs_readl(GUEST_CS_BASE) +
4369                                 vmcs_readl(GUEST_RIP);
4370                         vcpu->run->debug.arch.exception = DB_VECTOR;
4371                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4372                         return 0;
4373                 } else {
4374                         vcpu->arch.dr7 &= ~DR7_GD;
4375                         vcpu->arch.dr6 |= DR6_BD;
4376                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4377                         kvm_queue_exception(vcpu, DB_VECTOR);
4378                         return 1;
4379                 }
4380         }
4381
4382         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4383         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4384         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4385         if (exit_qualification & TYPE_MOV_FROM_DR) {
4386                 unsigned long val;
4387                 if (!kvm_get_dr(vcpu, dr, &val))
4388                         kvm_register_write(vcpu, reg, val);
4389         } else
4390                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4391         skip_emulated_instruction(vcpu);
4392         return 1;
4393 }
4394
4395 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4396 {
4397         vmcs_writel(GUEST_DR7, val);
4398 }
4399
4400 static int handle_cpuid(struct kvm_vcpu *vcpu)
4401 {
4402         kvm_emulate_cpuid(vcpu);
4403         return 1;
4404 }
4405
4406 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4407 {
4408         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4409         u64 data;
4410
4411         if (vmx_get_msr(vcpu, ecx, &data)) {
4412                 trace_kvm_msr_read_ex(ecx);
4413                 kvm_inject_gp(vcpu, 0);
4414                 return 1;
4415         }
4416
4417         trace_kvm_msr_read(ecx, data);
4418
4419         /* FIXME: handling of bits 32:63 of rax, rdx */
4420         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4421         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4422         skip_emulated_instruction(vcpu);
4423         return 1;
4424 }
4425
4426 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4427 {
4428         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4429         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4430                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4431
4432         if (vmx_set_msr(vcpu, ecx, data) != 0) {
4433                 trace_kvm_msr_write_ex(ecx, data);
4434                 kvm_inject_gp(vcpu, 0);
4435                 return 1;
4436         }
4437
4438         trace_kvm_msr_write(ecx, data);
4439         skip_emulated_instruction(vcpu);
4440         return 1;
4441 }
4442
4443 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4444 {
4445         kvm_make_request(KVM_REQ_EVENT, vcpu);
4446         return 1;
4447 }
4448
4449 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4450 {
4451         u32 cpu_based_vm_exec_control;
4452
4453         /* clear pending irq */
4454         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4455         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4456         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4457
4458         kvm_make_request(KVM_REQ_EVENT, vcpu);
4459
4460         ++vcpu->stat.irq_window_exits;
4461
4462         /*
4463          * If the user space waits to inject interrupts, exit as soon as
4464          * possible
4465          */
4466         if (!irqchip_in_kernel(vcpu->kvm) &&
4467             vcpu->run->request_interrupt_window &&
4468             !kvm_cpu_has_interrupt(vcpu)) {
4469                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4470                 return 0;
4471         }
4472         return 1;
4473 }
4474
4475 static int handle_halt(struct kvm_vcpu *vcpu)
4476 {
4477         skip_emulated_instruction(vcpu);
4478         return kvm_emulate_halt(vcpu);
4479 }
4480
4481 static int handle_vmcall(struct kvm_vcpu *vcpu)
4482 {
4483         skip_emulated_instruction(vcpu);
4484         kvm_emulate_hypercall(vcpu);
4485         return 1;
4486 }
4487
4488 static int handle_invd(struct kvm_vcpu *vcpu)
4489 {
4490         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4491 }
4492
4493 static int handle_invlpg(struct kvm_vcpu *vcpu)
4494 {
4495         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4496
4497         kvm_mmu_invlpg(vcpu, exit_qualification);
4498         skip_emulated_instruction(vcpu);
4499         return 1;
4500 }
4501
4502 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4503 {
4504         skip_emulated_instruction(vcpu);
4505         kvm_emulate_wbinvd(vcpu);
4506         return 1;
4507 }
4508
4509 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4510 {
4511         u64 new_bv = kvm_read_edx_eax(vcpu);
4512         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4513
4514         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4515                 skip_emulated_instruction(vcpu);
4516         return 1;
4517 }
4518
4519 static int handle_apic_access(struct kvm_vcpu *vcpu)
4520 {
4521         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4522 }
4523
4524 static int handle_task_switch(struct kvm_vcpu *vcpu)
4525 {
4526         struct vcpu_vmx *vmx = to_vmx(vcpu);
4527         unsigned long exit_qualification;
4528         bool has_error_code = false;
4529         u32 error_code = 0;
4530         u16 tss_selector;
4531         int reason, type, idt_v;
4532
4533         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4534         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4535
4536         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4537
4538         reason = (u32)exit_qualification >> 30;
4539         if (reason == TASK_SWITCH_GATE && idt_v) {
4540                 switch (type) {
4541                 case INTR_TYPE_NMI_INTR:
4542                         vcpu->arch.nmi_injected = false;
4543                         vmx_set_nmi_mask(vcpu, true);
4544                         break;
4545                 case INTR_TYPE_EXT_INTR:
4546                 case INTR_TYPE_SOFT_INTR:
4547                         kvm_clear_interrupt_queue(vcpu);
4548                         break;
4549                 case INTR_TYPE_HARD_EXCEPTION:
4550                         if (vmx->idt_vectoring_info &
4551                             VECTORING_INFO_DELIVER_CODE_MASK) {
4552                                 has_error_code = true;
4553                                 error_code =
4554                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
4555                         }
4556                         /* fall through */
4557                 case INTR_TYPE_SOFT_EXCEPTION:
4558                         kvm_clear_exception_queue(vcpu);
4559                         break;
4560                 default:
4561                         break;
4562                 }
4563         }
4564         tss_selector = exit_qualification;
4565
4566         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4567                        type != INTR_TYPE_EXT_INTR &&
4568                        type != INTR_TYPE_NMI_INTR))
4569                 skip_emulated_instruction(vcpu);
4570
4571         if (kvm_task_switch(vcpu, tss_selector, reason,
4572                                 has_error_code, error_code) == EMULATE_FAIL) {
4573                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4574                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4575                 vcpu->run->internal.ndata = 0;
4576                 return 0;
4577         }
4578
4579         /* clear all local breakpoint enable flags */
4580         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4581
4582         /*
4583          * TODO: What about debug traps on tss switch?
4584          *       Are we supposed to inject them and update dr6?
4585          */
4586
4587         return 1;
4588 }
4589
4590 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4591 {
4592         unsigned long exit_qualification;
4593         gpa_t gpa;
4594         int gla_validity;
4595
4596         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4597
4598         if (exit_qualification & (1 << 6)) {
4599                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4600                 return -EINVAL;
4601         }
4602
4603         gla_validity = (exit_qualification >> 7) & 0x3;
4604         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4605                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4606                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4607                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4608                         vmcs_readl(GUEST_LINEAR_ADDRESS));
4609                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4610                         (long unsigned int)exit_qualification);
4611                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4612                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4613                 return 0;
4614         }
4615
4616         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4617         trace_kvm_page_fault(gpa, exit_qualification);
4618         return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
4619 }
4620
4621 static u64 ept_rsvd_mask(u64 spte, int level)
4622 {
4623         int i;
4624         u64 mask = 0;
4625
4626         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4627                 mask |= (1ULL << i);
4628
4629         if (level > 2)
4630                 /* bits 7:3 reserved */
4631                 mask |= 0xf8;
4632         else if (level == 2) {
4633                 if (spte & (1ULL << 7))
4634                         /* 2MB ref, bits 20:12 reserved */
4635                         mask |= 0x1ff000;
4636                 else
4637                         /* bits 6:3 reserved */
4638                         mask |= 0x78;
4639         }
4640
4641         return mask;
4642 }
4643
4644 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4645                                        int level)
4646 {
4647         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4648
4649         /* 010b (write-only) */
4650         WARN_ON((spte & 0x7) == 0x2);
4651
4652         /* 110b (write/execute) */
4653         WARN_ON((spte & 0x7) == 0x6);
4654
4655         /* 100b (execute-only) and value not supported by logical processor */
4656         if (!cpu_has_vmx_ept_execute_only())
4657                 WARN_ON((spte & 0x7) == 0x4);
4658
4659         /* not 000b */
4660         if ((spte & 0x7)) {
4661                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4662
4663                 if (rsvd_bits != 0) {
4664                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4665                                          __func__, rsvd_bits);
4666                         WARN_ON(1);
4667                 }
4668
4669                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4670                         u64 ept_mem_type = (spte & 0x38) >> 3;
4671
4672                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
4673                             ept_mem_type == 7) {
4674                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4675                                                 __func__, ept_mem_type);
4676                                 WARN_ON(1);
4677                         }
4678                 }
4679         }
4680 }
4681
4682 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4683 {
4684         u64 sptes[4];
4685         int nr_sptes, i, ret;
4686         gpa_t gpa;
4687
4688         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4689
4690         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4691         if (likely(ret == 1))
4692                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4693                                               EMULATE_DONE;
4694         if (unlikely(!ret))
4695                 return 1;
4696
4697         /* It is the real ept misconfig */
4698         printk(KERN_ERR "EPT: Misconfiguration.\n");
4699         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4700
4701         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4702
4703         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4704                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4705
4706         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4707         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4708
4709         return 0;
4710 }
4711
4712 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4713 {
4714         u32 cpu_based_vm_exec_control;
4715
4716         /* clear pending NMI */
4717         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4718         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4719         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4720         ++vcpu->stat.nmi_window_exits;
4721         kvm_make_request(KVM_REQ_EVENT, vcpu);
4722
4723         return 1;
4724 }
4725
4726 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4727 {
4728         struct vcpu_vmx *vmx = to_vmx(vcpu);
4729         enum emulation_result err = EMULATE_DONE;
4730         int ret = 1;
4731         u32 cpu_exec_ctrl;
4732         bool intr_window_requested;
4733
4734         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4735         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4736
4737         while (!guest_state_valid(vcpu)) {
4738                 if (intr_window_requested
4739                     && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4740                         return handle_interrupt_window(&vmx->vcpu);
4741
4742                 err = emulate_instruction(vcpu, 0);
4743
4744                 if (err == EMULATE_DO_MMIO) {
4745                         ret = 0;
4746                         goto out;
4747                 }
4748
4749                 if (err != EMULATE_DONE)
4750                         return 0;
4751
4752                 if (signal_pending(current))
4753                         goto out;
4754                 if (need_resched())
4755                         schedule();
4756         }
4757
4758         vmx->emulation_required = 0;
4759 out:
4760         return ret;
4761 }
4762
4763 /*
4764  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4765  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4766  */
4767 static int handle_pause(struct kvm_vcpu *vcpu)
4768 {
4769         skip_emulated_instruction(vcpu);
4770         kvm_vcpu_on_spin(vcpu);
4771
4772         return 1;
4773 }
4774
4775 static int handle_invalid_op(struct kvm_vcpu *vcpu)
4776 {
4777         kvm_queue_exception(vcpu, UD_VECTOR);
4778         return 1;
4779 }
4780
4781 /*
4782  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4783  * We could reuse a single VMCS for all the L2 guests, but we also want the
4784  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4785  * allows keeping them loaded on the processor, and in the future will allow
4786  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4787  * every entry if they never change.
4788  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4789  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4790  *
4791  * The following functions allocate and free a vmcs02 in this pool.
4792  */
4793
4794 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4795 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4796 {
4797         struct vmcs02_list *item;
4798         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4799                 if (item->vmptr == vmx->nested.current_vmptr) {
4800                         list_move(&item->list, &vmx->nested.vmcs02_pool);
4801                         return &item->vmcs02;
4802                 }
4803
4804         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4805                 /* Recycle the least recently used VMCS. */
4806                 item = list_entry(vmx->nested.vmcs02_pool.prev,
4807                         struct vmcs02_list, list);
4808                 item->vmptr = vmx->nested.current_vmptr;
4809                 list_move(&item->list, &vmx->nested.vmcs02_pool);
4810                 return &item->vmcs02;
4811         }
4812
4813         /* Create a new VMCS */
4814         item = (struct vmcs02_list *)
4815                 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4816         if (!item)
4817                 return NULL;
4818         item->vmcs02.vmcs = alloc_vmcs();
4819         if (!item->vmcs02.vmcs) {
4820                 kfree(item);
4821                 return NULL;
4822         }
4823         loaded_vmcs_init(&item->vmcs02);
4824         item->vmptr = vmx->nested.current_vmptr;
4825         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4826         vmx->nested.vmcs02_num++;
4827         return &item->vmcs02;
4828 }
4829
4830 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4831 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4832 {
4833         struct vmcs02_list *item;
4834         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4835                 if (item->vmptr == vmptr) {
4836                         free_loaded_vmcs(&item->vmcs02);
4837                         list_del(&item->list);
4838                         kfree(item);
4839                         vmx->nested.vmcs02_num--;
4840                         return;
4841                 }
4842 }
4843
4844 /*
4845  * Free all VMCSs saved for this vcpu, except the one pointed by
4846  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4847  * currently used, if running L2), and vmcs01 when running L2.
4848  */
4849 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4850 {
4851         struct vmcs02_list *item, *n;
4852         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4853                 if (vmx->loaded_vmcs != &item->vmcs02)
4854                         free_loaded_vmcs(&item->vmcs02);
4855                 list_del(&item->list);
4856                 kfree(item);
4857         }
4858         vmx->nested.vmcs02_num = 0;
4859
4860         if (vmx->loaded_vmcs != &vmx->vmcs01)
4861                 free_loaded_vmcs(&vmx->vmcs01);
4862 }
4863
4864 /*
4865  * Emulate the VMXON instruction.
4866  * Currently, we just remember that VMX is active, and do not save or even
4867  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4868  * do not currently need to store anything in that guest-allocated memory
4869  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
4870  * argument is different from the VMXON pointer (which the spec says they do).
4871  */
4872 static int handle_vmon(struct kvm_vcpu *vcpu)
4873 {
4874         struct kvm_segment cs;
4875         struct vcpu_vmx *vmx = to_vmx(vcpu);
4876
4877         /* The Intel VMX Instruction Reference lists a bunch of bits that
4878          * are prerequisite to running VMXON, most notably cr4.VMXE must be
4879          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
4880          * Otherwise, we should fail with #UD. We test these now:
4881          */
4882         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
4883             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
4884             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4885                 kvm_queue_exception(vcpu, UD_VECTOR);
4886                 return 1;
4887         }
4888
4889         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4890         if (is_long_mode(vcpu) && !cs.l) {
4891                 kvm_queue_exception(vcpu, UD_VECTOR);
4892                 return 1;
4893         }
4894
4895         if (vmx_get_cpl(vcpu)) {
4896                 kvm_inject_gp(vcpu, 0);
4897                 return 1;
4898         }
4899
4900         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
4901         vmx->nested.vmcs02_num = 0;
4902
4903         vmx->nested.vmxon = true;
4904
4905         skip_emulated_instruction(vcpu);
4906         return 1;
4907 }
4908
4909 /*
4910  * Intel's VMX Instruction Reference specifies a common set of prerequisites
4911  * for running VMX instructions (except VMXON, whose prerequisites are
4912  * slightly different). It also specifies what exception to inject otherwise.
4913  */
4914 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
4915 {
4916         struct kvm_segment cs;
4917         struct vcpu_vmx *vmx = to_vmx(vcpu);
4918
4919         if (!vmx->nested.vmxon) {
4920                 kvm_queue_exception(vcpu, UD_VECTOR);
4921                 return 0;
4922         }
4923
4924         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4925         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
4926             (is_long_mode(vcpu) && !cs.l)) {
4927                 kvm_queue_exception(vcpu, UD_VECTOR);
4928                 return 0;
4929         }
4930
4931         if (vmx_get_cpl(vcpu)) {
4932                 kvm_inject_gp(vcpu, 0);
4933                 return 0;
4934         }
4935
4936         return 1;
4937 }
4938
4939 /*
4940  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
4941  * just stops using VMX.
4942  */
4943 static void free_nested(struct vcpu_vmx *vmx)
4944 {
4945         if (!vmx->nested.vmxon)
4946                 return;
4947         vmx->nested.vmxon = false;
4948         if (vmx->nested.current_vmptr != -1ull) {
4949                 kunmap(vmx->nested.current_vmcs12_page);
4950                 nested_release_page(vmx->nested.current_vmcs12_page);
4951                 vmx->nested.current_vmptr = -1ull;
4952                 vmx->nested.current_vmcs12 = NULL;
4953         }
4954         /* Unpin physical memory we referred to in current vmcs02 */
4955         if (vmx->nested.apic_access_page) {
4956                 nested_release_page(vmx->nested.apic_access_page);
4957                 vmx->nested.apic_access_page = 0;
4958         }
4959
4960         nested_free_all_saved_vmcss(vmx);
4961 }
4962
4963 /* Emulate the VMXOFF instruction */
4964 static int handle_vmoff(struct kvm_vcpu *vcpu)
4965 {
4966         if (!nested_vmx_check_permission(vcpu))
4967                 return 1;
4968         free_nested(to_vmx(vcpu));
4969         skip_emulated_instruction(vcpu);
4970         return 1;
4971 }
4972
4973 /*
4974  * Decode the memory-address operand of a vmx instruction, as recorded on an
4975  * exit caused by such an instruction (run by a guest hypervisor).
4976  * On success, returns 0. When the operand is invalid, returns 1 and throws
4977  * #UD or #GP.
4978  */
4979 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
4980                                  unsigned long exit_qualification,
4981                                  u32 vmx_instruction_info, gva_t *ret)
4982 {
4983         /*
4984          * According to Vol. 3B, "Information for VM Exits Due to Instruction
4985          * Execution", on an exit, vmx_instruction_info holds most of the
4986          * addressing components of the operand. Only the displacement part
4987          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
4988          * For how an actual address is calculated from all these components,
4989          * refer to Vol. 1, "Operand Addressing".
4990          */
4991         int  scaling = vmx_instruction_info & 3;
4992         int  addr_size = (vmx_instruction_info >> 7) & 7;
4993         bool is_reg = vmx_instruction_info & (1u << 10);
4994         int  seg_reg = (vmx_instruction_info >> 15) & 7;
4995         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
4996         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
4997         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
4998         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
4999
5000         if (is_reg) {
5001                 kvm_queue_exception(vcpu, UD_VECTOR);
5002                 return 1;
5003         }
5004
5005         /* Addr = segment_base + offset */
5006         /* offset = base + [index * scale] + displacement */
5007         *ret = vmx_get_segment_base(vcpu, seg_reg);
5008         if (base_is_valid)
5009                 *ret += kvm_register_read(vcpu, base_reg);
5010         if (index_is_valid)
5011                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5012         *ret += exit_qualification; /* holds the displacement */
5013
5014         if (addr_size == 1) /* 32 bit */
5015                 *ret &= 0xffffffff;
5016
5017         /*
5018          * TODO: throw #GP (and return 1) in various cases that the VM*
5019          * instructions require it - e.g., offset beyond segment limit,
5020          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5021          * address, and so on. Currently these are not checked.
5022          */
5023         return 0;
5024 }
5025
5026 /*
5027  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5028  * set the success or error code of an emulated VMX instruction, as specified
5029  * by Vol 2B, VMX Instruction Reference, "Conventions".
5030  */
5031 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5032 {
5033         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5034                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5035                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5036 }
5037
5038 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5039 {
5040         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5041                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5042                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5043                         | X86_EFLAGS_CF);
5044 }
5045
5046 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5047                                         u32 vm_instruction_error)
5048 {
5049         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5050                 /*
5051                  * failValid writes the error number to the current VMCS, which
5052                  * can't be done there isn't a current VMCS.
5053                  */
5054                 nested_vmx_failInvalid(vcpu);
5055                 return;
5056         }
5057         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5058                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5059                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5060                         | X86_EFLAGS_ZF);
5061         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5062 }
5063
5064 /* Emulate the VMCLEAR instruction */
5065 static int handle_vmclear(struct kvm_vcpu *vcpu)
5066 {
5067         struct vcpu_vmx *vmx = to_vmx(vcpu);
5068         gva_t gva;
5069         gpa_t vmptr;
5070         struct vmcs12 *vmcs12;
5071         struct page *page;
5072         struct x86_exception e;
5073
5074         if (!nested_vmx_check_permission(vcpu))
5075                 return 1;
5076
5077         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5078                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5079                 return 1;
5080
5081         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5082                                 sizeof(vmptr), &e)) {
5083                 kvm_inject_page_fault(vcpu, &e);
5084                 return 1;
5085         }
5086
5087         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5088                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5089                 skip_emulated_instruction(vcpu);
5090                 return 1;
5091         }
5092
5093         if (vmptr == vmx->nested.current_vmptr) {
5094                 kunmap(vmx->nested.current_vmcs12_page);
5095                 nested_release_page(vmx->nested.current_vmcs12_page);
5096                 vmx->nested.current_vmptr = -1ull;
5097                 vmx->nested.current_vmcs12 = NULL;
5098         }
5099
5100         page = nested_get_page(vcpu, vmptr);
5101         if (page == NULL) {
5102                 /*
5103                  * For accurate processor emulation, VMCLEAR beyond available
5104                  * physical memory should do nothing at all. However, it is
5105                  * possible that a nested vmx bug, not a guest hypervisor bug,
5106                  * resulted in this case, so let's shut down before doing any
5107                  * more damage:
5108                  */
5109                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5110                 return 1;
5111         }
5112         vmcs12 = kmap(page);
5113         vmcs12->launch_state = 0;
5114         kunmap(page);
5115         nested_release_page(page);
5116
5117         nested_free_vmcs02(vmx, vmptr);
5118
5119         skip_emulated_instruction(vcpu);
5120         nested_vmx_succeed(vcpu);
5121         return 1;
5122 }
5123
5124 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5125
5126 /* Emulate the VMLAUNCH instruction */
5127 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5128 {
5129         return nested_vmx_run(vcpu, true);
5130 }
5131
5132 /* Emulate the VMRESUME instruction */
5133 static int handle_vmresume(struct kvm_vcpu *vcpu)
5134 {
5135
5136         return nested_vmx_run(vcpu, false);
5137 }
5138
5139 enum vmcs_field_type {
5140         VMCS_FIELD_TYPE_U16 = 0,
5141         VMCS_FIELD_TYPE_U64 = 1,
5142         VMCS_FIELD_TYPE_U32 = 2,
5143         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5144 };
5145
5146 static inline int vmcs_field_type(unsigned long field)
5147 {
5148         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5149                 return VMCS_FIELD_TYPE_U32;
5150         return (field >> 13) & 0x3 ;
5151 }
5152
5153 static inline int vmcs_field_readonly(unsigned long field)
5154 {
5155         return (((field >> 10) & 0x3) == 1);
5156 }
5157
5158 /*
5159  * Read a vmcs12 field. Since these can have varying lengths and we return
5160  * one type, we chose the biggest type (u64) and zero-extend the return value
5161  * to that size. Note that the caller, handle_vmread, might need to use only
5162  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5163  * 64-bit fields are to be returned).
5164  */
5165 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5166                                         unsigned long field, u64 *ret)
5167 {
5168         short offset = vmcs_field_to_offset(field);
5169         char *p;
5170
5171         if (offset < 0)
5172                 return 0;
5173
5174         p = ((char *)(get_vmcs12(vcpu))) + offset;
5175
5176         switch (vmcs_field_type(field)) {
5177         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5178                 *ret = *((natural_width *)p);
5179                 return 1;
5180         case VMCS_FIELD_TYPE_U16:
5181                 *ret = *((u16 *)p);
5182                 return 1;
5183         case VMCS_FIELD_TYPE_U32:
5184                 *ret = *((u32 *)p);
5185                 return 1;
5186         case VMCS_FIELD_TYPE_U64:
5187                 *ret = *((u64 *)p);
5188                 return 1;
5189         default:
5190                 return 0; /* can never happen. */
5191         }
5192 }
5193
5194 /*
5195  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5196  * used before) all generate the same failure when it is missing.
5197  */
5198 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5199 {
5200         struct vcpu_vmx *vmx = to_vmx(vcpu);
5201         if (vmx->nested.current_vmptr == -1ull) {
5202                 nested_vmx_failInvalid(vcpu);
5203                 skip_emulated_instruction(vcpu);
5204                 return 0;
5205         }
5206         return 1;
5207 }
5208
5209 static int handle_vmread(struct kvm_vcpu *vcpu)
5210 {
5211         unsigned long field;
5212         u64 field_value;
5213         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5214         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5215         gva_t gva = 0;
5216
5217         if (!nested_vmx_check_permission(vcpu) ||
5218             !nested_vmx_check_vmcs12(vcpu))
5219                 return 1;
5220
5221         /* Decode instruction info and find the field to read */
5222         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5223         /* Read the field, zero-extended to a u64 field_value */
5224         if (!vmcs12_read_any(vcpu, field, &field_value)) {
5225                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5226                 skip_emulated_instruction(vcpu);
5227                 return 1;
5228         }
5229         /*
5230          * Now copy part of this value to register or memory, as requested.
5231          * Note that the number of bits actually copied is 32 or 64 depending
5232          * on the guest's mode (32 or 64 bit), not on the given field's length.
5233          */
5234         if (vmx_instruction_info & (1u << 10)) {
5235                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5236                         field_value);
5237         } else {
5238                 if (get_vmx_mem_address(vcpu, exit_qualification,
5239                                 vmx_instruction_info, &gva))
5240                         return 1;
5241                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5242                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5243                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5244         }
5245
5246         nested_vmx_succeed(vcpu);
5247         skip_emulated_instruction(vcpu);
5248         return 1;
5249 }
5250
5251
5252 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5253 {
5254         unsigned long field;
5255         gva_t gva;
5256         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5257         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5258         char *p;
5259         short offset;
5260         /* The value to write might be 32 or 64 bits, depending on L1's long
5261          * mode, and eventually we need to write that into a field of several
5262          * possible lengths. The code below first zero-extends the value to 64
5263          * bit (field_value), and then copies only the approriate number of
5264          * bits into the vmcs12 field.
5265          */
5266         u64 field_value = 0;
5267         struct x86_exception e;
5268
5269         if (!nested_vmx_check_permission(vcpu) ||
5270             !nested_vmx_check_vmcs12(vcpu))
5271                 return 1;
5272
5273         if (vmx_instruction_info & (1u << 10))
5274                 field_value = kvm_register_read(vcpu,
5275                         (((vmx_instruction_info) >> 3) & 0xf));
5276         else {
5277                 if (get_vmx_mem_address(vcpu, exit_qualification,
5278                                 vmx_instruction_info, &gva))
5279                         return 1;
5280                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5281                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5282                         kvm_inject_page_fault(vcpu, &e);
5283                         return 1;
5284                 }
5285         }
5286
5287
5288         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5289         if (vmcs_field_readonly(field)) {
5290                 nested_vmx_failValid(vcpu,
5291                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5292                 skip_emulated_instruction(vcpu);
5293                 return 1;
5294         }
5295
5296         offset = vmcs_field_to_offset(field);
5297         if (offset < 0) {
5298                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5299                 skip_emulated_instruction(vcpu);
5300                 return 1;
5301         }
5302         p = ((char *) get_vmcs12(vcpu)) + offset;
5303
5304         switch (vmcs_field_type(field)) {
5305         case VMCS_FIELD_TYPE_U16:
5306                 *(u16 *)p = field_value;
5307                 break;
5308         case VMCS_FIELD_TYPE_U32:
5309                 *(u32 *)p = field_value;
5310                 break;
5311         case VMCS_FIELD_TYPE_U64:
5312                 *(u64 *)p = field_value;
5313                 break;
5314         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5315                 *(natural_width *)p = field_value;
5316                 break;
5317         default:
5318                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5319                 skip_emulated_instruction(vcpu);
5320                 return 1;
5321         }
5322
5323         nested_vmx_succeed(vcpu);
5324         skip_emulated_instruction(vcpu);
5325         return 1;
5326 }
5327
5328 /* Emulate the VMPTRLD instruction */
5329 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5330 {
5331         struct vcpu_vmx *vmx = to_vmx(vcpu);
5332         gva_t gva;
5333         gpa_t vmptr;
5334         struct x86_exception e;
5335
5336         if (!nested_vmx_check_permission(vcpu))
5337                 return 1;
5338
5339         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5340                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5341                 return 1;
5342
5343         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5344                                 sizeof(vmptr), &e)) {
5345                 kvm_inject_page_fault(vcpu, &e);
5346                 return 1;
5347         }
5348
5349         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5350                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5351                 skip_emulated_instruction(vcpu);
5352                 return 1;
5353         }
5354
5355         if (vmx->nested.current_vmptr != vmptr) {
5356                 struct vmcs12 *new_vmcs12;
5357                 struct page *page;
5358                 page = nested_get_page(vcpu, vmptr);
5359                 if (page == NULL) {
5360                         nested_vmx_failInvalid(vcpu);
5361                         skip_emulated_instruction(vcpu);
5362                         return 1;
5363                 }
5364                 new_vmcs12 = kmap(page);
5365                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5366                         kunmap(page);
5367                         nested_release_page_clean(page);
5368                         nested_vmx_failValid(vcpu,
5369                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5370                         skip_emulated_instruction(vcpu);
5371                         return 1;
5372                 }
5373                 if (vmx->nested.current_vmptr != -1ull) {
5374                         kunmap(vmx->nested.current_vmcs12_page);
5375                         nested_release_page(vmx->nested.current_vmcs12_page);
5376                 }
5377
5378                 vmx->nested.current_vmptr = vmptr;
5379                 vmx->nested.current_vmcs12 = new_vmcs12;
5380                 vmx->nested.current_vmcs12_page = page;
5381         }
5382
5383         nested_vmx_succeed(vcpu);
5384         skip_emulated_instruction(vcpu);
5385         return 1;
5386 }
5387
5388 /* Emulate the VMPTRST instruction */
5389 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5390 {
5391         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5392         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5393         gva_t vmcs_gva;
5394         struct x86_exception e;
5395
5396         if (!nested_vmx_check_permission(vcpu))
5397                 return 1;
5398
5399         if (get_vmx_mem_address(vcpu, exit_qualification,
5400                         vmx_instruction_info, &vmcs_gva))
5401                 return 1;
5402         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5403         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5404                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
5405                                  sizeof(u64), &e)) {
5406                 kvm_inject_page_fault(vcpu, &e);
5407                 return 1;
5408         }
5409         nested_vmx_succeed(vcpu);
5410         skip_emulated_instruction(vcpu);
5411         return 1;
5412 }
5413
5414 /*
5415  * The exit handlers return 1 if the exit was handled fully and guest execution
5416  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5417  * to be done to userspace and return 0.
5418  */
5419 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5420         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
5421         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5422         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5423         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5424         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5425         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5426         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5427         [EXIT_REASON_CPUID]                   = handle_cpuid,
5428         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5429         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5430         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5431         [EXIT_REASON_HLT]                     = handle_halt,
5432         [EXIT_REASON_INVD]                    = handle_invd,
5433         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5434         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5435         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
5436         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
5437         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
5438         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
5439         [EXIT_REASON_VMREAD]                  = handle_vmread,
5440         [EXIT_REASON_VMRESUME]                = handle_vmresume,
5441         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
5442         [EXIT_REASON_VMOFF]                   = handle_vmoff,
5443         [EXIT_REASON_VMON]                    = handle_vmon,
5444         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5445         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5446         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5447         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5448         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5449         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5450         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5451         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5452         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5453         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
5454         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
5455 };
5456
5457 static const int kvm_vmx_max_exit_handlers =
5458         ARRAY_SIZE(kvm_vmx_exit_handlers);
5459
5460 /*
5461  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5462  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5463  * disinterest in the current event (read or write a specific MSR) by using an
5464  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5465  */
5466 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5467         struct vmcs12 *vmcs12, u32 exit_reason)
5468 {
5469         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5470         gpa_t bitmap;
5471
5472         if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5473                 return 1;
5474
5475         /*
5476          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5477          * for the four combinations of read/write and low/high MSR numbers.
5478          * First we need to figure out which of the four to use:
5479          */
5480         bitmap = vmcs12->msr_bitmap;
5481         if (exit_reason == EXIT_REASON_MSR_WRITE)
5482                 bitmap += 2048;
5483         if (msr_index >= 0xc0000000) {
5484                 msr_index -= 0xc0000000;
5485                 bitmap += 1024;
5486         }
5487
5488         /* Then read the msr_index'th bit from this bitmap: */
5489         if (msr_index < 1024*8) {
5490                 unsigned char b;
5491                 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5492                 return 1 & (b >> (msr_index & 7));
5493         } else
5494                 return 1; /* let L1 handle the wrong parameter */
5495 }
5496
5497 /*
5498  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5499  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5500  * intercept (via guest_host_mask etc.) the current event.
5501  */
5502 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5503         struct vmcs12 *vmcs12)
5504 {
5505         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5506         int cr = exit_qualification & 15;
5507         int reg = (exit_qualification >> 8) & 15;
5508         unsigned long val = kvm_register_read(vcpu, reg);
5509
5510         switch ((exit_qualification >> 4) & 3) {
5511         case 0: /* mov to cr */
5512                 switch (cr) {
5513                 case 0:
5514                         if (vmcs12->cr0_guest_host_mask &
5515                             (val ^ vmcs12->cr0_read_shadow))
5516                                 return 1;
5517                         break;
5518                 case 3:
5519                         if ((vmcs12->cr3_target_count >= 1 &&
5520                                         vmcs12->cr3_target_value0 == val) ||
5521                                 (vmcs12->cr3_target_count >= 2 &&
5522                                         vmcs12->cr3_target_value1 == val) ||
5523                                 (vmcs12->cr3_target_count >= 3 &&
5524                                         vmcs12->cr3_target_value2 == val) ||
5525                                 (vmcs12->cr3_target_count >= 4 &&
5526                                         vmcs12->cr3_target_value3 == val))
5527                                 return 0;
5528                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5529                                 return 1;
5530                         break;
5531                 case 4:
5532                         if (vmcs12->cr4_guest_host_mask &
5533                             (vmcs12->cr4_read_shadow ^ val))
5534                                 return 1;
5535                         break;
5536                 case 8:
5537                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5538                                 return 1;
5539                         break;
5540                 }
5541                 break;
5542         case 2: /* clts */
5543                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5544                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
5545                         return 1;
5546                 break;
5547         case 1: /* mov from cr */
5548                 switch (cr) {
5549                 case 3:
5550                         if (vmcs12->cpu_based_vm_exec_control &
5551                             CPU_BASED_CR3_STORE_EXITING)
5552                                 return 1;
5553                         break;
5554                 case 8:
5555                         if (vmcs12->cpu_based_vm_exec_control &
5556                             CPU_BASED_CR8_STORE_EXITING)
5557                                 return 1;
5558                         break;
5559                 }
5560                 break;
5561         case 3: /* lmsw */
5562                 /*
5563                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5564                  * cr0. Other attempted changes are ignored, with no exit.
5565                  */
5566                 if (vmcs12->cr0_guest_host_mask & 0xe &
5567                     (val ^ vmcs12->cr0_read_shadow))
5568                         return 1;
5569                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5570                     !(vmcs12->cr0_read_shadow & 0x1) &&
5571                     (val & 0x1))
5572                         return 1;
5573                 break;
5574         }
5575         return 0;
5576 }
5577
5578 /*
5579  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5580  * should handle it ourselves in L0 (and then continue L2). Only call this
5581  * when in is_guest_mode (L2).
5582  */
5583 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5584 {
5585         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5586         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5587         struct vcpu_vmx *vmx = to_vmx(vcpu);
5588         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5589
5590         if (vmx->nested.nested_run_pending)
5591                 return 0;
5592
5593         if (unlikely(vmx->fail)) {
5594                 printk(KERN_INFO "%s failed vm entry %x\n",
5595                        __func__, vmcs_read32(VM_INSTRUCTION_ERROR));
5596                 return 1;
5597         }
5598
5599         switch (exit_reason) {
5600         case EXIT_REASON_EXCEPTION_NMI:
5601                 if (!is_exception(intr_info))
5602                         return 0;
5603                 else if (is_page_fault(intr_info))
5604                         return enable_ept;
5605                 return vmcs12->exception_bitmap &
5606                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5607         case EXIT_REASON_EXTERNAL_INTERRUPT:
5608                 return 0;
5609         case EXIT_REASON_TRIPLE_FAULT:
5610                 return 1;
5611         case EXIT_REASON_PENDING_INTERRUPT:
5612         case EXIT_REASON_NMI_WINDOW:
5613                 /*
5614                  * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5615                  * (aka Interrupt Window Exiting) only when L1 turned it on,
5616                  * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5617                  * Same for NMI Window Exiting.
5618                  */
5619                 return 1;
5620         case EXIT_REASON_TASK_SWITCH:
5621                 return 1;
5622         case EXIT_REASON_CPUID:
5623                 return 1;
5624         case EXIT_REASON_HLT:
5625                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5626         case EXIT_REASON_INVD:
5627                 return 1;
5628         case EXIT_REASON_INVLPG:
5629                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5630         case EXIT_REASON_RDPMC:
5631                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5632         case EXIT_REASON_RDTSC:
5633                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5634         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5635         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5636         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5637         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5638         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5639                 /*
5640                  * VMX instructions trap unconditionally. This allows L1 to
5641                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
5642                  */
5643                 return 1;
5644         case EXIT_REASON_CR_ACCESS:
5645                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5646         case EXIT_REASON_DR_ACCESS:
5647                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5648         case EXIT_REASON_IO_INSTRUCTION:
5649                 /* TODO: support IO bitmaps */
5650                 return 1;
5651         case EXIT_REASON_MSR_READ:
5652         case EXIT_REASON_MSR_WRITE:
5653                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5654         case EXIT_REASON_INVALID_STATE:
5655                 return 1;
5656         case EXIT_REASON_MWAIT_INSTRUCTION:
5657                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5658         case EXIT_REASON_MONITOR_INSTRUCTION:
5659                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5660         case EXIT_REASON_PAUSE_INSTRUCTION:
5661                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5662                         nested_cpu_has2(vmcs12,
5663                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5664         case EXIT_REASON_MCE_DURING_VMENTRY:
5665                 return 0;
5666         case EXIT_REASON_TPR_BELOW_THRESHOLD:
5667                 return 1;
5668         case EXIT_REASON_APIC_ACCESS:
5669                 return nested_cpu_has2(vmcs12,
5670                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5671         case EXIT_REASON_EPT_VIOLATION:
5672         case EXIT_REASON_EPT_MISCONFIG:
5673                 return 0;
5674         case EXIT_REASON_WBINVD:
5675                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5676         case EXIT_REASON_XSETBV:
5677                 return 1;
5678         default:
5679                 return 1;
5680         }
5681 }
5682
5683 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5684 {
5685         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5686         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5687 }
5688
5689 /*
5690  * The guest has exited.  See if we can fix it or if we need userspace
5691  * assistance.
5692  */
5693 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5694 {
5695         struct vcpu_vmx *vmx = to_vmx(vcpu);
5696         u32 exit_reason = vmx->exit_reason;
5697         u32 vectoring_info = vmx->idt_vectoring_info;
5698
5699         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5700
5701         /* If guest state is invalid, start emulating */
5702         if (vmx->emulation_required && emulate_invalid_guest_state)
5703                 return handle_invalid_guest_state(vcpu);
5704
5705         /*
5706          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5707          * we did not inject a still-pending event to L1 now because of
5708          * nested_run_pending, we need to re-enable this bit.
5709          */
5710         if (vmx->nested.nested_run_pending)
5711                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5712
5713         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5714             exit_reason == EXIT_REASON_VMRESUME))
5715                 vmx->nested.nested_run_pending = 1;
5716         else
5717                 vmx->nested.nested_run_pending = 0;
5718
5719         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5720                 nested_vmx_vmexit(vcpu);
5721                 return 1;
5722         }
5723
5724         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5725                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5726                 vcpu->run->fail_entry.hardware_entry_failure_reason
5727                         = exit_reason;
5728                 return 0;
5729         }
5730
5731         if (unlikely(vmx->fail)) {
5732                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5733                 vcpu->run->fail_entry.hardware_entry_failure_reason
5734                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5735                 return 0;
5736         }
5737
5738         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5739                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5740                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5741                         exit_reason != EXIT_REASON_TASK_SWITCH))
5742                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5743                        "(0x%x) and exit reason is 0x%x\n",
5744                        __func__, vectoring_info, exit_reason);
5745
5746         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5747             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5748                                         get_vmcs12(vcpu), vcpu)))) {
5749                 if (vmx_interrupt_allowed(vcpu)) {
5750                         vmx->soft_vnmi_blocked = 0;
5751                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
5752                            vcpu->arch.nmi_pending) {
5753                         /*
5754                          * This CPU don't support us in finding the end of an
5755                          * NMI-blocked window if the guest runs with IRQs
5756                          * disabled. So we pull the trigger after 1 s of
5757                          * futile waiting, but inform the user about this.
5758                          */
5759                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5760                                "state on VCPU %d after 1 s timeout\n",
5761                                __func__, vcpu->vcpu_id);
5762                         vmx->soft_vnmi_blocked = 0;
5763                 }
5764         }
5765
5766         if (exit_reason < kvm_vmx_max_exit_handlers
5767             && kvm_vmx_exit_handlers[exit_reason])
5768                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5769         else {
5770                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5771                 vcpu->run->hw.hardware_exit_reason = exit_reason;
5772         }
5773         return 0;
5774 }
5775
5776 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5777 {
5778         if (irr == -1 || tpr < irr) {
5779                 vmcs_write32(TPR_THRESHOLD, 0);
5780                 return;
5781         }
5782
5783         vmcs_write32(TPR_THRESHOLD, irr);
5784 }
5785
5786 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
5787 {
5788         u32 exit_intr_info;
5789
5790         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5791               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5792                 return;
5793
5794         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5795         exit_intr_info = vmx->exit_intr_info;
5796
5797         /* Handle machine checks before interrupts are enabled */
5798         if (is_machine_check(exit_intr_info))
5799                 kvm_machine_check();
5800
5801         /* We need to handle NMIs before interrupts are enabled */
5802         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
5803             (exit_intr_info & INTR_INFO_VALID_MASK)) {
5804                 kvm_before_handle_nmi(&vmx->vcpu);
5805                 asm("int $2");
5806                 kvm_after_handle_nmi(&vmx->vcpu);
5807         }
5808 }
5809
5810 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5811 {
5812         u32 exit_intr_info;
5813         bool unblock_nmi;
5814         u8 vector;
5815         bool idtv_info_valid;
5816
5817         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5818
5819         if (cpu_has_virtual_nmis()) {
5820                 if (vmx->nmi_known_unmasked)
5821                         return;
5822                 /*
5823                  * Can't use vmx->exit_intr_info since we're not sure what
5824                  * the exit reason is.
5825                  */
5826                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5827                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5828                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5829                 /*
5830                  * SDM 3: 27.7.1.2 (September 2008)
5831                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
5832                  * a guest IRET fault.
5833                  * SDM 3: 23.2.2 (September 2008)
5834                  * Bit 12 is undefined in any of the following cases:
5835                  *  If the VM exit sets the valid bit in the IDT-vectoring
5836                  *   information field.
5837                  *  If the VM exit is due to a double fault.
5838                  */
5839                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5840                     vector != DF_VECTOR && !idtv_info_valid)
5841                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5842                                       GUEST_INTR_STATE_NMI);
5843                 else
5844                         vmx->nmi_known_unmasked =
5845                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5846                                   & GUEST_INTR_STATE_NMI);
5847         } else if (unlikely(vmx->soft_vnmi_blocked))
5848                 vmx->vnmi_blocked_time +=
5849                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
5850 }
5851
5852 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5853                                       u32 idt_vectoring_info,
5854                                       int instr_len_field,
5855                                       int error_code_field)
5856 {
5857         u8 vector;
5858         int type;
5859         bool idtv_info_valid;
5860
5861         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5862
5863         vmx->vcpu.arch.nmi_injected = false;
5864         kvm_clear_exception_queue(&vmx->vcpu);
5865         kvm_clear_interrupt_queue(&vmx->vcpu);
5866
5867         if (!idtv_info_valid)
5868                 return;
5869
5870         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5871
5872         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
5873         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
5874
5875         switch (type) {
5876         case INTR_TYPE_NMI_INTR:
5877                 vmx->vcpu.arch.nmi_injected = true;
5878                 /*
5879                  * SDM 3: 27.7.1.2 (September 2008)
5880                  * Clear bit "block by NMI" before VM entry if a NMI
5881                  * delivery faulted.
5882                  */
5883                 vmx_set_nmi_mask(&vmx->vcpu, false);
5884                 break;
5885         case INTR_TYPE_SOFT_EXCEPTION:
5886                 vmx->vcpu.arch.event_exit_inst_len =
5887                         vmcs_read32(instr_len_field);
5888                 /* fall through */
5889         case INTR_TYPE_HARD_EXCEPTION:
5890                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
5891                         u32 err = vmcs_read32(error_code_field);
5892                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
5893                 } else
5894                         kvm_queue_exception(&vmx->vcpu, vector);
5895                 break;
5896         case INTR_TYPE_SOFT_INTR:
5897                 vmx->vcpu.arch.event_exit_inst_len =
5898                         vmcs_read32(instr_len_field);
5899                 /* fall through */
5900         case INTR_TYPE_EXT_INTR:
5901                 kvm_queue_interrupt(&vmx->vcpu, vector,
5902                         type == INTR_TYPE_SOFT_INTR);
5903                 break;
5904         default:
5905                 break;
5906         }
5907 }
5908
5909 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
5910 {
5911         if (is_guest_mode(&vmx->vcpu))
5912                 return;
5913         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
5914                                   VM_EXIT_INSTRUCTION_LEN,
5915                                   IDT_VECTORING_ERROR_CODE);
5916 }
5917
5918 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
5919 {
5920         if (is_guest_mode(vcpu))
5921                 return;
5922         __vmx_complete_interrupts(to_vmx(vcpu),
5923                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5924                                   VM_ENTRY_INSTRUCTION_LEN,
5925                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
5926
5927         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
5928 }
5929
5930 #ifdef CONFIG_X86_64
5931 #define R "r"
5932 #define Q "q"
5933 #else
5934 #define R "e"
5935 #define Q "l"
5936 #endif
5937
5938 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
5939 {
5940         struct vcpu_vmx *vmx = to_vmx(vcpu);
5941
5942         if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
5943                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5944                 if (vmcs12->idt_vectoring_info_field &
5945                                 VECTORING_INFO_VALID_MASK) {
5946                         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5947                                 vmcs12->idt_vectoring_info_field);
5948                         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5949                                 vmcs12->vm_exit_instruction_len);
5950                         if (vmcs12->idt_vectoring_info_field &
5951                                         VECTORING_INFO_DELIVER_CODE_MASK)
5952                                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
5953                                         vmcs12->idt_vectoring_error_code);
5954                 }
5955         }
5956
5957         /* Record the guest's net vcpu time for enforced NMI injections. */
5958         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
5959                 vmx->entry_time = ktime_get();
5960
5961         /* Don't enter VMX if guest state is invalid, let the exit handler
5962            start emulation until we arrive back to a valid state */
5963         if (vmx->emulation_required && emulate_invalid_guest_state)
5964                 return;
5965
5966         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
5967                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
5968         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
5969                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
5970
5971         /* When single-stepping over STI and MOV SS, we must clear the
5972          * corresponding interruptibility bits in the guest state. Otherwise
5973          * vmentry fails as it then expects bit 14 (BS) in pending debug
5974          * exceptions being set, but that's not correct for the guest debugging
5975          * case. */
5976         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5977                 vmx_set_interrupt_shadow(vcpu, 0);
5978
5979         vmx->__launched = vmx->loaded_vmcs->launched;
5980         asm(
5981                 /* Store host registers */
5982                 "push %%"R"dx; push %%"R"bp;"
5983                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
5984                 "push %%"R"cx \n\t"
5985                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
5986                 "je 1f \n\t"
5987                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
5988                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
5989                 "1: \n\t"
5990                 /* Reload cr2 if changed */
5991                 "mov %c[cr2](%0), %%"R"ax \n\t"
5992                 "mov %%cr2, %%"R"dx \n\t"
5993                 "cmp %%"R"ax, %%"R"dx \n\t"
5994                 "je 2f \n\t"
5995                 "mov %%"R"ax, %%cr2 \n\t"
5996                 "2: \n\t"
5997                 /* Check if vmlaunch of vmresume is needed */
5998                 "cmpl $0, %c[launched](%0) \n\t"
5999                 /* Load guest registers.  Don't clobber flags. */
6000                 "mov %c[rax](%0), %%"R"ax \n\t"
6001                 "mov %c[rbx](%0), %%"R"bx \n\t"
6002                 "mov %c[rdx](%0), %%"R"dx \n\t"
6003                 "mov %c[rsi](%0), %%"R"si \n\t"
6004                 "mov %c[rdi](%0), %%"R"di \n\t"
6005                 "mov %c[rbp](%0), %%"R"bp \n\t"
6006 #ifdef CONFIG_X86_64
6007                 "mov %c[r8](%0),  %%r8  \n\t"
6008                 "mov %c[r9](%0),  %%r9  \n\t"
6009                 "mov %c[r10](%0), %%r10 \n\t"
6010                 "mov %c[r11](%0), %%r11 \n\t"
6011                 "mov %c[r12](%0), %%r12 \n\t"
6012                 "mov %c[r13](%0), %%r13 \n\t"
6013                 "mov %c[r14](%0), %%r14 \n\t"
6014                 "mov %c[r15](%0), %%r15 \n\t"
6015 #endif
6016                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6017
6018                 /* Enter guest mode */
6019                 "jne .Llaunched \n\t"
6020                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6021                 "jmp .Lkvm_vmx_return \n\t"
6022                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
6023                 ".Lkvm_vmx_return: "
6024                 /* Save guest registers, load host registers, keep flags */
6025                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6026                 "pop %0 \n\t"
6027                 "mov %%"R"ax, %c[rax](%0) \n\t"
6028                 "mov %%"R"bx, %c[rbx](%0) \n\t"
6029                 "pop"Q" %c[rcx](%0) \n\t"
6030                 "mov %%"R"dx, %c[rdx](%0) \n\t"
6031                 "mov %%"R"si, %c[rsi](%0) \n\t"
6032                 "mov %%"R"di, %c[rdi](%0) \n\t"
6033                 "mov %%"R"bp, %c[rbp](%0) \n\t"
6034 #ifdef CONFIG_X86_64
6035                 "mov %%r8,  %c[r8](%0) \n\t"
6036                 "mov %%r9,  %c[r9](%0) \n\t"
6037                 "mov %%r10, %c[r10](%0) \n\t"
6038                 "mov %%r11, %c[r11](%0) \n\t"
6039                 "mov %%r12, %c[r12](%0) \n\t"
6040                 "mov %%r13, %c[r13](%0) \n\t"
6041                 "mov %%r14, %c[r14](%0) \n\t"
6042                 "mov %%r15, %c[r15](%0) \n\t"
6043 #endif
6044                 "mov %%cr2, %%"R"ax   \n\t"
6045                 "mov %%"R"ax, %c[cr2](%0) \n\t"
6046
6047                 "pop  %%"R"bp; pop  %%"R"dx \n\t"
6048                 "setbe %c[fail](%0) \n\t"
6049               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6050                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6051                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6052                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6053                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6054                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6055                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6056                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6057                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6058                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6059                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6060 #ifdef CONFIG_X86_64
6061                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6062                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6063                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6064                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6065                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6066                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6067                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6068                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6069 #endif
6070                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6071                 [wordsize]"i"(sizeof(ulong))
6072               : "cc", "memory"
6073                 , R"ax", R"bx", R"di", R"si"
6074 #ifdef CONFIG_X86_64
6075                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6076 #endif
6077               );
6078
6079         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6080                                   | (1 << VCPU_EXREG_RFLAGS)
6081                                   | (1 << VCPU_EXREG_CPL)
6082                                   | (1 << VCPU_EXREG_PDPTR)
6083                                   | (1 << VCPU_EXREG_SEGMENTS)
6084                                   | (1 << VCPU_EXREG_CR3));
6085         vcpu->arch.regs_dirty = 0;
6086
6087         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6088
6089         if (is_guest_mode(vcpu)) {
6090                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6091                 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6092                 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6093                         vmcs12->idt_vectoring_error_code =
6094                                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6095                         vmcs12->vm_exit_instruction_len =
6096                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6097                 }
6098         }
6099
6100         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
6101         vmx->loaded_vmcs->launched = 1;
6102
6103         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6104
6105         vmx_complete_atomic_exit(vmx);
6106         vmx_recover_nmi_blocking(vmx);
6107         vmx_complete_interrupts(vmx);
6108 }
6109
6110 #undef R
6111 #undef Q
6112
6113 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6114 {
6115         struct vcpu_vmx *vmx = to_vmx(vcpu);
6116
6117         free_vpid(vmx);
6118         free_nested(vmx);
6119         free_loaded_vmcs(vmx->loaded_vmcs);
6120         kfree(vmx->guest_msrs);
6121         kvm_vcpu_uninit(vcpu);
6122         kmem_cache_free(kvm_vcpu_cache, vmx);
6123 }
6124
6125 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6126 {
6127         int err;
6128         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6129         int cpu;
6130
6131         if (!vmx)
6132                 return ERR_PTR(-ENOMEM);
6133
6134         allocate_vpid(vmx);
6135
6136         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6137         if (err)
6138                 goto free_vcpu;
6139
6140         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6141         err = -ENOMEM;
6142         if (!vmx->guest_msrs) {
6143                 goto uninit_vcpu;
6144         }
6145
6146         vmx->loaded_vmcs = &vmx->vmcs01;
6147         vmx->loaded_vmcs->vmcs = alloc_vmcs();
6148         if (!vmx->loaded_vmcs->vmcs)
6149                 goto free_msrs;
6150         if (!vmm_exclusive)
6151                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6152         loaded_vmcs_init(vmx->loaded_vmcs);
6153         if (!vmm_exclusive)
6154                 kvm_cpu_vmxoff();
6155
6156         cpu = get_cpu();
6157         vmx_vcpu_load(&vmx->vcpu, cpu);
6158         vmx->vcpu.cpu = cpu;
6159         err = vmx_vcpu_setup(vmx);
6160         vmx_vcpu_put(&vmx->vcpu);
6161         put_cpu();
6162         if (err)
6163                 goto free_vmcs;
6164         if (vm_need_virtualize_apic_accesses(kvm))
6165                 err = alloc_apic_access_page(kvm);
6166                 if (err)
6167                         goto free_vmcs;
6168
6169         if (enable_ept) {
6170                 if (!kvm->arch.ept_identity_map_addr)
6171                         kvm->arch.ept_identity_map_addr =
6172                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6173                 err = -ENOMEM;
6174                 if (alloc_identity_pagetable(kvm) != 0)
6175                         goto free_vmcs;
6176                 if (!init_rmode_identity_map(kvm))
6177                         goto free_vmcs;
6178         }
6179
6180         vmx->nested.current_vmptr = -1ull;
6181         vmx->nested.current_vmcs12 = NULL;
6182
6183         return &vmx->vcpu;
6184
6185 free_vmcs:
6186         free_vmcs(vmx->loaded_vmcs->vmcs);
6187 free_msrs:
6188         kfree(vmx->guest_msrs);
6189 uninit_vcpu:
6190         kvm_vcpu_uninit(&vmx->vcpu);
6191 free_vcpu:
6192         free_vpid(vmx);
6193         kmem_cache_free(kvm_vcpu_cache, vmx);
6194         return ERR_PTR(err);
6195 }
6196
6197 static void __init vmx_check_processor_compat(void *rtn)
6198 {
6199         struct vmcs_config vmcs_conf;
6200
6201         *(int *)rtn = 0;
6202         if (setup_vmcs_config(&vmcs_conf) < 0)
6203                 *(int *)rtn = -EIO;
6204         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6205                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6206                                 smp_processor_id());
6207                 *(int *)rtn = -EIO;
6208         }
6209 }
6210
6211 static int get_ept_level(void)
6212 {
6213         return VMX_EPT_DEFAULT_GAW + 1;
6214 }
6215
6216 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6217 {
6218         u64 ret;
6219
6220         /* For VT-d and EPT combination
6221          * 1. MMIO: always map as UC
6222          * 2. EPT with VT-d:
6223          *   a. VT-d without snooping control feature: can't guarantee the
6224          *      result, try to trust guest.
6225          *   b. VT-d with snooping control feature: snooping control feature of
6226          *      VT-d engine can guarantee the cache correctness. Just set it
6227          *      to WB to keep consistent with host. So the same as item 3.
6228          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6229          *    consistent with host MTRR
6230          */
6231         if (is_mmio)
6232                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6233         else if (vcpu->kvm->arch.iommu_domain &&
6234                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6235                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6236                       VMX_EPT_MT_EPTE_SHIFT;
6237         else
6238                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6239                         | VMX_EPT_IPAT_BIT;
6240
6241         return ret;
6242 }
6243
6244 #define _ER(x) { EXIT_REASON_##x, #x }
6245
6246 static const struct trace_print_flags vmx_exit_reasons_str[] = {
6247         _ER(EXCEPTION_NMI),
6248         _ER(EXTERNAL_INTERRUPT),
6249         _ER(TRIPLE_FAULT),
6250         _ER(PENDING_INTERRUPT),
6251         _ER(NMI_WINDOW),
6252         _ER(TASK_SWITCH),
6253         _ER(CPUID),
6254         _ER(HLT),
6255         _ER(INVLPG),
6256         _ER(RDPMC),
6257         _ER(RDTSC),
6258         _ER(VMCALL),
6259         _ER(VMCLEAR),
6260         _ER(VMLAUNCH),
6261         _ER(VMPTRLD),
6262         _ER(VMPTRST),
6263         _ER(VMREAD),
6264         _ER(VMRESUME),
6265         _ER(VMWRITE),
6266         _ER(VMOFF),
6267         _ER(VMON),
6268         _ER(CR_ACCESS),
6269         _ER(DR_ACCESS),
6270         _ER(IO_INSTRUCTION),
6271         _ER(MSR_READ),
6272         _ER(MSR_WRITE),
6273         _ER(MWAIT_INSTRUCTION),
6274         _ER(MONITOR_INSTRUCTION),
6275         _ER(PAUSE_INSTRUCTION),
6276         _ER(MCE_DURING_VMENTRY),
6277         _ER(TPR_BELOW_THRESHOLD),
6278         _ER(APIC_ACCESS),
6279         _ER(EPT_VIOLATION),
6280         _ER(EPT_MISCONFIG),
6281         _ER(WBINVD),
6282         { -1, NULL }
6283 };
6284
6285 #undef _ER
6286
6287 static int vmx_get_lpage_level(void)
6288 {
6289         if (enable_ept && !cpu_has_vmx_ept_1g_page())
6290                 return PT_DIRECTORY_LEVEL;
6291         else
6292                 /* For shadow and EPT supported 1GB page */
6293                 return PT_PDPE_LEVEL;
6294 }
6295
6296 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6297 {
6298         struct kvm_cpuid_entry2 *best;
6299         struct vcpu_vmx *vmx = to_vmx(vcpu);
6300         u32 exec_control;
6301
6302         vmx->rdtscp_enabled = false;
6303         if (vmx_rdtscp_supported()) {
6304                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6305                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6306                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6307                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6308                                 vmx->rdtscp_enabled = true;
6309                         else {
6310                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6311                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6312                                                 exec_control);
6313                         }
6314                 }
6315         }
6316 }
6317
6318 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6319 {
6320         if (func == 1 && nested)
6321                 entry->ecx |= bit(X86_FEATURE_VMX);
6322 }
6323
6324 /*
6325  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6326  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6327  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6328  * guest in a way that will both be appropriate to L1's requests, and our
6329  * needs. In addition to modifying the active vmcs (which is vmcs02), this
6330  * function also has additional necessary side-effects, like setting various
6331  * vcpu->arch fields.
6332  */
6333 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6334 {
6335         struct vcpu_vmx *vmx = to_vmx(vcpu);
6336         u32 exec_control;
6337
6338         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6339         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6340         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6341         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6342         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6343         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6344         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6345         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6346         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6347         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6348         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6349         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6350         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6351         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6352         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6353         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6354         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6355         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6356         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6357         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6358         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6359         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6360         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6361         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6362         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6363         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6364         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6365         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6366         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6367         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6368         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6369         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6370         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6371         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6372         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6373         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6374
6375         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6376         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6377                 vmcs12->vm_entry_intr_info_field);
6378         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6379                 vmcs12->vm_entry_exception_error_code);
6380         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6381                 vmcs12->vm_entry_instruction_len);
6382         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6383                 vmcs12->guest_interruptibility_info);
6384         vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6385         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6386         vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6387         vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6388         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6389                 vmcs12->guest_pending_dbg_exceptions);
6390         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6391         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6392
6393         vmcs_write64(VMCS_LINK_POINTER, -1ull);
6394
6395         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6396                 (vmcs_config.pin_based_exec_ctrl |
6397                  vmcs12->pin_based_vm_exec_control));
6398
6399         /*
6400          * Whether page-faults are trapped is determined by a combination of
6401          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6402          * If enable_ept, L0 doesn't care about page faults and we should
6403          * set all of these to L1's desires. However, if !enable_ept, L0 does
6404          * care about (at least some) page faults, and because it is not easy
6405          * (if at all possible?) to merge L0 and L1's desires, we simply ask
6406          * to exit on each and every L2 page fault. This is done by setting
6407          * MASK=MATCH=0 and (see below) EB.PF=1.
6408          * Note that below we don't need special code to set EB.PF beyond the
6409          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6410          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6411          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6412          *
6413          * A problem with this approach (when !enable_ept) is that L1 may be
6414          * injected with more page faults than it asked for. This could have
6415          * caused problems, but in practice existing hypervisors don't care.
6416          * To fix this, we will need to emulate the PFEC checking (on the L1
6417          * page tables), using walk_addr(), when injecting PFs to L1.
6418          */
6419         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6420                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6421         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6422                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6423
6424         if (cpu_has_secondary_exec_ctrls()) {
6425                 u32 exec_control = vmx_secondary_exec_control(vmx);
6426                 if (!vmx->rdtscp_enabled)
6427                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
6428                 /* Take the following fields only from vmcs12 */
6429                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6430                 if (nested_cpu_has(vmcs12,
6431                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6432                         exec_control |= vmcs12->secondary_vm_exec_control;
6433
6434                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6435                         /*
6436                          * Translate L1 physical address to host physical
6437                          * address for vmcs02. Keep the page pinned, so this
6438                          * physical address remains valid. We keep a reference
6439                          * to it so we can release it later.
6440                          */
6441                         if (vmx->nested.apic_access_page) /* shouldn't happen */
6442                                 nested_release_page(vmx->nested.apic_access_page);
6443                         vmx->nested.apic_access_page =
6444                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
6445                         /*
6446                          * If translation failed, no matter: This feature asks
6447                          * to exit when accessing the given address, and if it
6448                          * can never be accessed, this feature won't do
6449                          * anything anyway.
6450                          */
6451                         if (!vmx->nested.apic_access_page)
6452                                 exec_control &=
6453                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6454                         else
6455                                 vmcs_write64(APIC_ACCESS_ADDR,
6456                                   page_to_phys(vmx->nested.apic_access_page));
6457                 }
6458
6459                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6460         }
6461
6462
6463         /*
6464          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6465          * Some constant fields are set here by vmx_set_constant_host_state().
6466          * Other fields are different per CPU, and will be set later when
6467          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6468          */
6469         vmx_set_constant_host_state();
6470
6471         /*
6472          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6473          * entry, but only if the current (host) sp changed from the value
6474          * we wrote last (vmx->host_rsp). This cache is no longer relevant
6475          * if we switch vmcs, and rather than hold a separate cache per vmcs,
6476          * here we just force the write to happen on entry.
6477          */
6478         vmx->host_rsp = 0;
6479
6480         exec_control = vmx_exec_control(vmx); /* L0's desires */
6481         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6482         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6483         exec_control &= ~CPU_BASED_TPR_SHADOW;
6484         exec_control |= vmcs12->cpu_based_vm_exec_control;
6485         /*
6486          * Merging of IO and MSR bitmaps not currently supported.
6487          * Rather, exit every time.
6488          */
6489         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6490         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6491         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6492
6493         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6494
6495         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6496          * bitwise-or of what L1 wants to trap for L2, and what we want to
6497          * trap. Note that CR0.TS also needs updating - we do this later.
6498          */
6499         update_exception_bitmap(vcpu);
6500         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6501         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6502
6503         /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6504         vmcs_write32(VM_EXIT_CONTROLS,
6505                 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6506         vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6507                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6508
6509         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6510                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6511         else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6512                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6513
6514
6515         set_cr4_guest_host_mask(vmx);
6516
6517         vmcs_write64(TSC_OFFSET,
6518                 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6519
6520         if (enable_vpid) {
6521                 /*
6522                  * Trivially support vpid by letting L2s share their parent
6523                  * L1's vpid. TODO: move to a more elaborate solution, giving
6524                  * each L2 its own vpid and exposing the vpid feature to L1.
6525                  */
6526                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6527                 vmx_flush_tlb(vcpu);
6528         }
6529
6530         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6531                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6532         if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6533                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6534         else
6535                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6536         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6537         vmx_set_efer(vcpu, vcpu->arch.efer);
6538
6539         /*
6540          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6541          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6542          * The CR0_READ_SHADOW is what L2 should have expected to read given
6543          * the specifications by L1; It's not enough to take
6544          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6545          * have more bits than L1 expected.
6546          */
6547         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6548         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6549
6550         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6551         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6552
6553         /* shadow page tables on either EPT or shadow page tables */
6554         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6555         kvm_mmu_reset_context(vcpu);
6556
6557         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6558         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6559 }
6560
6561 /*
6562  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6563  * for running an L2 nested guest.
6564  */
6565 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6566 {
6567         struct vmcs12 *vmcs12;
6568         struct vcpu_vmx *vmx = to_vmx(vcpu);
6569         int cpu;
6570         struct loaded_vmcs *vmcs02;
6571
6572         if (!nested_vmx_check_permission(vcpu) ||
6573             !nested_vmx_check_vmcs12(vcpu))
6574                 return 1;
6575
6576         skip_emulated_instruction(vcpu);
6577         vmcs12 = get_vmcs12(vcpu);
6578
6579         /*
6580          * The nested entry process starts with enforcing various prerequisites
6581          * on vmcs12 as required by the Intel SDM, and act appropriately when
6582          * they fail: As the SDM explains, some conditions should cause the
6583          * instruction to fail, while others will cause the instruction to seem
6584          * to succeed, but return an EXIT_REASON_INVALID_STATE.
6585          * To speed up the normal (success) code path, we should avoid checking
6586          * for misconfigurations which will anyway be caught by the processor
6587          * when using the merged vmcs02.
6588          */
6589         if (vmcs12->launch_state == launch) {
6590                 nested_vmx_failValid(vcpu,
6591                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6592                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6593                 return 1;
6594         }
6595
6596         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6597                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6598                 /*TODO: Also verify bits beyond physical address width are 0*/
6599                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6600                 return 1;
6601         }
6602
6603         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6604                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6605                 /*TODO: Also verify bits beyond physical address width are 0*/
6606                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6607                 return 1;
6608         }
6609
6610         if (vmcs12->vm_entry_msr_load_count > 0 ||
6611             vmcs12->vm_exit_msr_load_count > 0 ||
6612             vmcs12->vm_exit_msr_store_count > 0) {
6613                 if (printk_ratelimit())
6614                         printk(KERN_WARNING
6615                           "%s: VMCS MSR_{LOAD,STORE} unsupported\n", __func__);
6616                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6617                 return 1;
6618         }
6619
6620         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6621               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6622             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6623               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6624             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6625               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6626             !vmx_control_verify(vmcs12->vm_exit_controls,
6627               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6628             !vmx_control_verify(vmcs12->vm_entry_controls,
6629               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6630         {
6631                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6632                 return 1;
6633         }
6634
6635         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6636             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6637                 nested_vmx_failValid(vcpu,
6638                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6639                 return 1;
6640         }
6641
6642         if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6643             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6644                 nested_vmx_entry_failure(vcpu, vmcs12,
6645                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6646                 return 1;
6647         }
6648         if (vmcs12->vmcs_link_pointer != -1ull) {
6649                 nested_vmx_entry_failure(vcpu, vmcs12,
6650                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6651                 return 1;
6652         }
6653
6654         /*
6655          * We're finally done with prerequisite checking, and can start with
6656          * the nested entry.
6657          */
6658
6659         vmcs02 = nested_get_current_vmcs02(vmx);
6660         if (!vmcs02)
6661                 return -ENOMEM;
6662
6663         enter_guest_mode(vcpu);
6664
6665         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6666
6667         cpu = get_cpu();
6668         vmx->loaded_vmcs = vmcs02;
6669         vmx_vcpu_put(vcpu);
6670         vmx_vcpu_load(vcpu, cpu);
6671         vcpu->cpu = cpu;
6672         put_cpu();
6673
6674         vmcs12->launch_state = 1;
6675
6676         prepare_vmcs02(vcpu, vmcs12);
6677
6678         /*
6679          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6680          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6681          * returned as far as L1 is concerned. It will only return (and set
6682          * the success flag) when L2 exits (see nested_vmx_vmexit()).
6683          */
6684         return 1;
6685 }
6686
6687 /*
6688  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6689  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6690  * This function returns the new value we should put in vmcs12.guest_cr0.
6691  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6692  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6693  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6694  *     didn't trap the bit, because if L1 did, so would L0).
6695  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6696  *     been modified by L2, and L1 knows it. So just leave the old value of
6697  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6698  *     isn't relevant, because if L0 traps this bit it can set it to anything.
6699  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6700  *     changed these bits, and therefore they need to be updated, but L0
6701  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6702  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6703  */
6704 static inline unsigned long
6705 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6706 {
6707         return
6708         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6709         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6710         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6711                         vcpu->arch.cr0_guest_owned_bits));
6712 }
6713
6714 static inline unsigned long
6715 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6716 {
6717         return
6718         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6719         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6720         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6721                         vcpu->arch.cr4_guest_owned_bits));
6722 }
6723
6724 /*
6725  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6726  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6727  * and this function updates it to reflect the changes to the guest state while
6728  * L2 was running (and perhaps made some exits which were handled directly by L0
6729  * without going back to L1), and to reflect the exit reason.
6730  * Note that we do not have to copy here all VMCS fields, just those that
6731  * could have changed by the L2 guest or the exit - i.e., the guest-state and
6732  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6733  * which already writes to vmcs12 directly.
6734  */
6735 void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6736 {
6737         /* update guest state fields: */
6738         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6739         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6740
6741         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6742         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6743         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6744         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6745
6746         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6747         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6748         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6749         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6750         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6751         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6752         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6753         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6754         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6755         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6756         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6757         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6758         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6759         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6760         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6761         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6762         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6763         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6764         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6765         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6766         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6767         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6768         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6769         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6770         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6771         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6772         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6773         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6774         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6775         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6776         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6777         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6778         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6779         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6780         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6781         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6782
6783         vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
6784         vmcs12->guest_interruptibility_info =
6785                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
6786         vmcs12->guest_pending_dbg_exceptions =
6787                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
6788
6789         /* TODO: These cannot have changed unless we have MSR bitmaps and
6790          * the relevant bit asks not to trap the change */
6791         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
6792         if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
6793                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
6794         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
6795         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
6796         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
6797
6798         /* update exit information fields: */
6799
6800         vmcs12->vm_exit_reason  = vmcs_read32(VM_EXIT_REASON);
6801         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6802
6803         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6804         vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6805         vmcs12->idt_vectoring_info_field =
6806                 vmcs_read32(IDT_VECTORING_INFO_FIELD);
6807         vmcs12->idt_vectoring_error_code =
6808                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6809         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6810         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6811
6812         /* clear vm-entry fields which are to be cleared on exit */
6813         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6814                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
6815 }
6816
6817 /*
6818  * A part of what we need to when the nested L2 guest exits and we want to
6819  * run its L1 parent, is to reset L1's guest state to the host state specified
6820  * in vmcs12.
6821  * This function is to be called not only on normal nested exit, but also on
6822  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6823  * Failures During or After Loading Guest State").
6824  * This function should be called when the active VMCS is L1's (vmcs01).
6825  */
6826 void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6827 {
6828         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
6829                 vcpu->arch.efer = vmcs12->host_ia32_efer;
6830         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
6831                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6832         else
6833                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6834         vmx_set_efer(vcpu, vcpu->arch.efer);
6835
6836         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
6837         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
6838         /*
6839          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
6840          * actually changed, because it depends on the current state of
6841          * fpu_active (which may have changed).
6842          * Note that vmx_set_cr0 refers to efer set above.
6843          */
6844         kvm_set_cr0(vcpu, vmcs12->host_cr0);
6845         /*
6846          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
6847          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
6848          * but we also need to update cr0_guest_host_mask and exception_bitmap.
6849          */
6850         update_exception_bitmap(vcpu);
6851         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
6852         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6853
6854         /*
6855          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
6856          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
6857          */
6858         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
6859         kvm_set_cr4(vcpu, vmcs12->host_cr4);
6860
6861         /* shadow page tables on either EPT or shadow page tables */
6862         kvm_set_cr3(vcpu, vmcs12->host_cr3);
6863         kvm_mmu_reset_context(vcpu);
6864
6865         if (enable_vpid) {
6866                 /*
6867                  * Trivially support vpid by letting L2s share their parent
6868                  * L1's vpid. TODO: move to a more elaborate solution, giving
6869                  * each L2 its own vpid and exposing the vpid feature to L1.
6870                  */
6871                 vmx_flush_tlb(vcpu);
6872         }
6873
6874
6875         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
6876         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
6877         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
6878         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
6879         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
6880         vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
6881         vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
6882         vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
6883         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
6884         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
6885         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
6886         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
6887         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
6888         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
6889         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
6890
6891         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
6892                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
6893         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
6894                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
6895                         vmcs12->host_ia32_perf_global_ctrl);
6896 }
6897
6898 /*
6899  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
6900  * and modify vmcs12 to make it see what it would expect to see there if
6901  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
6902  */
6903 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
6904 {
6905         struct vcpu_vmx *vmx = to_vmx(vcpu);
6906         int cpu;
6907         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6908
6909         leave_guest_mode(vcpu);
6910         prepare_vmcs12(vcpu, vmcs12);
6911
6912         cpu = get_cpu();
6913         vmx->loaded_vmcs = &vmx->vmcs01;
6914         vmx_vcpu_put(vcpu);
6915         vmx_vcpu_load(vcpu, cpu);
6916         vcpu->cpu = cpu;
6917         put_cpu();
6918
6919         /* if no vmcs02 cache requested, remove the one we used */
6920         if (VMCS02_POOL_SIZE == 0)
6921                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
6922
6923         load_vmcs12_host_state(vcpu, vmcs12);
6924
6925         /* Update TSC_OFFSET if vmx_adjust_tsc_offset() was used while L2 ran */
6926         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6927
6928         /* This is needed for same reason as it was needed in prepare_vmcs02 */
6929         vmx->host_rsp = 0;
6930
6931         /* Unpin physical memory we referred to in vmcs02 */
6932         if (vmx->nested.apic_access_page) {
6933                 nested_release_page(vmx->nested.apic_access_page);
6934                 vmx->nested.apic_access_page = 0;
6935         }
6936
6937         /*
6938          * Exiting from L2 to L1, we're now back to L1 which thinks it just
6939          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
6940          * success or failure flag accordingly.
6941          */
6942         if (unlikely(vmx->fail)) {
6943                 vmx->fail = 0;
6944                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
6945         } else
6946                 nested_vmx_succeed(vcpu);
6947 }
6948
6949 /*
6950  * L1's failure to enter L2 is a subset of a normal exit, as explained in
6951  * 23.7 "VM-entry failures during or after loading guest state" (this also
6952  * lists the acceptable exit-reason and exit-qualification parameters).
6953  * It should only be called before L2 actually succeeded to run, and when
6954  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
6955  */
6956 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
6957                         struct vmcs12 *vmcs12,
6958                         u32 reason, unsigned long qualification)
6959 {
6960         load_vmcs12_host_state(vcpu, vmcs12);
6961         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
6962         vmcs12->exit_qualification = qualification;
6963         nested_vmx_succeed(vcpu);
6964 }
6965
6966 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
6967                                struct x86_instruction_info *info,
6968                                enum x86_intercept_stage stage)
6969 {
6970         return X86EMUL_CONTINUE;
6971 }
6972
6973 static struct kvm_x86_ops vmx_x86_ops = {
6974         .cpu_has_kvm_support = cpu_has_kvm_support,
6975         .disabled_by_bios = vmx_disabled_by_bios,
6976         .hardware_setup = hardware_setup,
6977         .hardware_unsetup = hardware_unsetup,
6978         .check_processor_compatibility = vmx_check_processor_compat,
6979         .hardware_enable = hardware_enable,
6980         .hardware_disable = hardware_disable,
6981         .cpu_has_accelerated_tpr = report_flexpriority,
6982
6983         .vcpu_create = vmx_create_vcpu,
6984         .vcpu_free = vmx_free_vcpu,
6985         .vcpu_reset = vmx_vcpu_reset,
6986
6987         .prepare_guest_switch = vmx_save_host_state,
6988         .vcpu_load = vmx_vcpu_load,
6989         .vcpu_put = vmx_vcpu_put,
6990
6991         .set_guest_debug = set_guest_debug,
6992         .get_msr = vmx_get_msr,
6993         .set_msr = vmx_set_msr,
6994         .get_segment_base = vmx_get_segment_base,
6995         .get_segment = vmx_get_segment,
6996         .set_segment = vmx_set_segment,
6997         .get_cpl = vmx_get_cpl,
6998         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
6999         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7000         .decache_cr3 = vmx_decache_cr3,
7001         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7002         .set_cr0 = vmx_set_cr0,
7003         .set_cr3 = vmx_set_cr3,
7004         .set_cr4 = vmx_set_cr4,
7005         .set_efer = vmx_set_efer,
7006         .get_idt = vmx_get_idt,
7007         .set_idt = vmx_set_idt,
7008         .get_gdt = vmx_get_gdt,
7009         .set_gdt = vmx_set_gdt,
7010         .set_dr7 = vmx_set_dr7,
7011         .cache_reg = vmx_cache_reg,
7012         .get_rflags = vmx_get_rflags,
7013         .set_rflags = vmx_set_rflags,
7014         .fpu_activate = vmx_fpu_activate,
7015         .fpu_deactivate = vmx_fpu_deactivate,
7016
7017         .tlb_flush = vmx_flush_tlb,
7018
7019         .run = vmx_vcpu_run,
7020         .handle_exit = vmx_handle_exit,
7021         .skip_emulated_instruction = skip_emulated_instruction,
7022         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7023         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7024         .patch_hypercall = vmx_patch_hypercall,
7025         .set_irq = vmx_inject_irq,
7026         .set_nmi = vmx_inject_nmi,
7027         .queue_exception = vmx_queue_exception,
7028         .cancel_injection = vmx_cancel_injection,
7029         .interrupt_allowed = vmx_interrupt_allowed,
7030         .nmi_allowed = vmx_nmi_allowed,
7031         .get_nmi_mask = vmx_get_nmi_mask,
7032         .set_nmi_mask = vmx_set_nmi_mask,
7033         .enable_nmi_window = enable_nmi_window,
7034         .enable_irq_window = enable_irq_window,
7035         .update_cr8_intercept = update_cr8_intercept,
7036
7037         .set_tss_addr = vmx_set_tss_addr,
7038         .get_tdp_level = get_ept_level,
7039         .get_mt_mask = vmx_get_mt_mask,
7040
7041         .get_exit_info = vmx_get_exit_info,
7042         .exit_reasons_str = vmx_exit_reasons_str,
7043
7044         .get_lpage_level = vmx_get_lpage_level,
7045
7046         .cpuid_update = vmx_cpuid_update,
7047
7048         .rdtscp_supported = vmx_rdtscp_supported,
7049
7050         .set_supported_cpuid = vmx_set_supported_cpuid,
7051
7052         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7053
7054         .set_tsc_khz = vmx_set_tsc_khz,
7055         .write_tsc_offset = vmx_write_tsc_offset,
7056         .adjust_tsc_offset = vmx_adjust_tsc_offset,
7057         .compute_tsc_offset = vmx_compute_tsc_offset,
7058
7059         .set_tdp_cr3 = vmx_set_cr3,
7060
7061         .check_intercept = vmx_check_intercept,
7062 };
7063
7064 static int __init vmx_init(void)
7065 {
7066         int r, i;
7067
7068         rdmsrl_safe(MSR_EFER, &host_efer);
7069
7070         for (i = 0; i < NR_VMX_MSR; ++i)
7071                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7072
7073         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7074         if (!vmx_io_bitmap_a)
7075                 return -ENOMEM;
7076
7077         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7078         if (!vmx_io_bitmap_b) {
7079                 r = -ENOMEM;
7080                 goto out;
7081         }
7082
7083         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7084         if (!vmx_msr_bitmap_legacy) {
7085                 r = -ENOMEM;
7086                 goto out1;
7087         }
7088
7089         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7090         if (!vmx_msr_bitmap_longmode) {
7091                 r = -ENOMEM;
7092                 goto out2;
7093         }
7094
7095         /*
7096          * Allow direct access to the PC debug port (it is often used for I/O
7097          * delays, but the vmexits simply slow things down).
7098          */
7099         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7100         clear_bit(0x80, vmx_io_bitmap_a);
7101
7102         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7103
7104         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7105         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7106
7107         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7108
7109         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7110                      __alignof__(struct vcpu_vmx), THIS_MODULE);
7111         if (r)
7112                 goto out3;
7113
7114         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7115         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7116         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7117         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7118         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7119         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7120
7121         if (enable_ept) {
7122                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
7123                                 VMX_EPT_EXECUTABLE_MASK);
7124                 ept_set_mmio_spte_mask();
7125                 kvm_enable_tdp();
7126         } else
7127                 kvm_disable_tdp();
7128
7129         return 0;
7130
7131 out3:
7132         free_page((unsigned long)vmx_msr_bitmap_longmode);
7133 out2:
7134         free_page((unsigned long)vmx_msr_bitmap_legacy);
7135 out1:
7136         free_page((unsigned long)vmx_io_bitmap_b);
7137 out:
7138         free_page((unsigned long)vmx_io_bitmap_a);
7139         return r;
7140 }
7141
7142 static void __exit vmx_exit(void)
7143 {
7144         free_page((unsigned long)vmx_msr_bitmap_legacy);
7145         free_page((unsigned long)vmx_msr_bitmap_longmode);
7146         free_page((unsigned long)vmx_io_bitmap_b);
7147         free_page((unsigned long)vmx_io_bitmap_a);
7148
7149         kvm_exit();
7150 }
7151
7152 module_init(vmx_init)
7153 module_exit(vmx_exit)