Merge branch 'fbdev-next' of git://github.com/schandinat/linux-2.6
[pandora-kernel.git] / arch / x86 / kvm / vmx.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * This module enables machines with Intel VT-x extensions to run virtual
5  * machines without emulation or binary translation.
6  *
7  * Copyright (C) 2006 Qumranet, Inc.
8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9  *
10  * Authors:
11  *   Avi Kivity   <avi@qumranet.com>
12  *   Yaniv Kamay  <yaniv@qumranet.com>
13  *
14  * This work is licensed under the terms of the GNU GPL, version 2.  See
15  * the COPYING file in the top-level directory.
16  *
17  */
18
19 #include "irq.h"
20 #include "mmu.h"
21
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
33 #include "x86.h"
34
35 #include <asm/io.h>
36 #include <asm/desc.h>
37 #include <asm/vmx.h>
38 #include <asm/virtext.h>
39 #include <asm/mce.h>
40 #include <asm/i387.h>
41 #include <asm/xcr.h>
42
43 #include "trace.h"
44
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
46 #define __ex_clear(x, reg) \
47         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
48
49 MODULE_AUTHOR("Qumranet");
50 MODULE_LICENSE("GPL");
51
52 static int __read_mostly enable_vpid = 1;
53 module_param_named(vpid, enable_vpid, bool, 0444);
54
55 static int __read_mostly flexpriority_enabled = 1;
56 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
57
58 static int __read_mostly enable_ept = 1;
59 module_param_named(ept, enable_ept, bool, S_IRUGO);
60
61 static int __read_mostly enable_unrestricted_guest = 1;
62 module_param_named(unrestricted_guest,
63                         enable_unrestricted_guest, bool, S_IRUGO);
64
65 static int __read_mostly emulate_invalid_guest_state = 0;
66 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
67
68 static int __read_mostly vmm_exclusive = 1;
69 module_param(vmm_exclusive, bool, S_IRUGO);
70
71 static int __read_mostly yield_on_hlt = 1;
72 module_param(yield_on_hlt, bool, S_IRUGO);
73
74 /*
75  * If nested=1, nested virtualization is supported, i.e., guests may use
76  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
77  * use VMX instructions.
78  */
79 static int __read_mostly nested = 0;
80 module_param(nested, bool, S_IRUGO);
81
82 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
83         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
84 #define KVM_GUEST_CR0_MASK                                              \
85         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
86 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
87         (X86_CR0_WP | X86_CR0_NE)
88 #define KVM_VM_CR0_ALWAYS_ON                                            \
89         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
90 #define KVM_CR4_GUEST_OWNED_BITS                                      \
91         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
92          | X86_CR4_OSXMMEXCPT)
93
94 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
95 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
96
97 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
98
99 /*
100  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
101  * ple_gap:    upper bound on the amount of time between two successive
102  *             executions of PAUSE in a loop. Also indicate if ple enabled.
103  *             According to test, this time is usually smaller than 128 cycles.
104  * ple_window: upper bound on the amount of time a guest is allowed to execute
105  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
106  *             less than 2^12 cycles
107  * Time is measured based on a counter that runs at the same rate as the TSC,
108  * refer SDM volume 3b section 21.6.13 & 22.1.3.
109  */
110 #define KVM_VMX_DEFAULT_PLE_GAP    128
111 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
112 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
113 module_param(ple_gap, int, S_IRUGO);
114
115 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
116 module_param(ple_window, int, S_IRUGO);
117
118 #define NR_AUTOLOAD_MSRS 1
119 #define VMCS02_POOL_SIZE 1
120
121 struct vmcs {
122         u32 revision_id;
123         u32 abort;
124         char data[0];
125 };
126
127 /*
128  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
129  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
130  * loaded on this CPU (so we can clear them if the CPU goes down).
131  */
132 struct loaded_vmcs {
133         struct vmcs *vmcs;
134         int cpu;
135         int launched;
136         struct list_head loaded_vmcss_on_cpu_link;
137 };
138
139 struct shared_msr_entry {
140         unsigned index;
141         u64 data;
142         u64 mask;
143 };
144
145 /*
146  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
147  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
148  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
149  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
150  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
151  * More than one of these structures may exist, if L1 runs multiple L2 guests.
152  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
153  * underlying hardware which will be used to run L2.
154  * This structure is packed to ensure that its layout is identical across
155  * machines (necessary for live migration).
156  * If there are changes in this struct, VMCS12_REVISION must be changed.
157  */
158 typedef u64 natural_width;
159 struct __packed vmcs12 {
160         /* According to the Intel spec, a VMCS region must start with the
161          * following two fields. Then follow implementation-specific data.
162          */
163         u32 revision_id;
164         u32 abort;
165
166         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
167         u32 padding[7]; /* room for future expansion */
168
169         u64 io_bitmap_a;
170         u64 io_bitmap_b;
171         u64 msr_bitmap;
172         u64 vm_exit_msr_store_addr;
173         u64 vm_exit_msr_load_addr;
174         u64 vm_entry_msr_load_addr;
175         u64 tsc_offset;
176         u64 virtual_apic_page_addr;
177         u64 apic_access_addr;
178         u64 ept_pointer;
179         u64 guest_physical_address;
180         u64 vmcs_link_pointer;
181         u64 guest_ia32_debugctl;
182         u64 guest_ia32_pat;
183         u64 guest_ia32_efer;
184         u64 guest_ia32_perf_global_ctrl;
185         u64 guest_pdptr0;
186         u64 guest_pdptr1;
187         u64 guest_pdptr2;
188         u64 guest_pdptr3;
189         u64 host_ia32_pat;
190         u64 host_ia32_efer;
191         u64 host_ia32_perf_global_ctrl;
192         u64 padding64[8]; /* room for future expansion */
193         /*
194          * To allow migration of L1 (complete with its L2 guests) between
195          * machines of different natural widths (32 or 64 bit), we cannot have
196          * unsigned long fields with no explict size. We use u64 (aliased
197          * natural_width) instead. Luckily, x86 is little-endian.
198          */
199         natural_width cr0_guest_host_mask;
200         natural_width cr4_guest_host_mask;
201         natural_width cr0_read_shadow;
202         natural_width cr4_read_shadow;
203         natural_width cr3_target_value0;
204         natural_width cr3_target_value1;
205         natural_width cr3_target_value2;
206         natural_width cr3_target_value3;
207         natural_width exit_qualification;
208         natural_width guest_linear_address;
209         natural_width guest_cr0;
210         natural_width guest_cr3;
211         natural_width guest_cr4;
212         natural_width guest_es_base;
213         natural_width guest_cs_base;
214         natural_width guest_ss_base;
215         natural_width guest_ds_base;
216         natural_width guest_fs_base;
217         natural_width guest_gs_base;
218         natural_width guest_ldtr_base;
219         natural_width guest_tr_base;
220         natural_width guest_gdtr_base;
221         natural_width guest_idtr_base;
222         natural_width guest_dr7;
223         natural_width guest_rsp;
224         natural_width guest_rip;
225         natural_width guest_rflags;
226         natural_width guest_pending_dbg_exceptions;
227         natural_width guest_sysenter_esp;
228         natural_width guest_sysenter_eip;
229         natural_width host_cr0;
230         natural_width host_cr3;
231         natural_width host_cr4;
232         natural_width host_fs_base;
233         natural_width host_gs_base;
234         natural_width host_tr_base;
235         natural_width host_gdtr_base;
236         natural_width host_idtr_base;
237         natural_width host_ia32_sysenter_esp;
238         natural_width host_ia32_sysenter_eip;
239         natural_width host_rsp;
240         natural_width host_rip;
241         natural_width paddingl[8]; /* room for future expansion */
242         u32 pin_based_vm_exec_control;
243         u32 cpu_based_vm_exec_control;
244         u32 exception_bitmap;
245         u32 page_fault_error_code_mask;
246         u32 page_fault_error_code_match;
247         u32 cr3_target_count;
248         u32 vm_exit_controls;
249         u32 vm_exit_msr_store_count;
250         u32 vm_exit_msr_load_count;
251         u32 vm_entry_controls;
252         u32 vm_entry_msr_load_count;
253         u32 vm_entry_intr_info_field;
254         u32 vm_entry_exception_error_code;
255         u32 vm_entry_instruction_len;
256         u32 tpr_threshold;
257         u32 secondary_vm_exec_control;
258         u32 vm_instruction_error;
259         u32 vm_exit_reason;
260         u32 vm_exit_intr_info;
261         u32 vm_exit_intr_error_code;
262         u32 idt_vectoring_info_field;
263         u32 idt_vectoring_error_code;
264         u32 vm_exit_instruction_len;
265         u32 vmx_instruction_info;
266         u32 guest_es_limit;
267         u32 guest_cs_limit;
268         u32 guest_ss_limit;
269         u32 guest_ds_limit;
270         u32 guest_fs_limit;
271         u32 guest_gs_limit;
272         u32 guest_ldtr_limit;
273         u32 guest_tr_limit;
274         u32 guest_gdtr_limit;
275         u32 guest_idtr_limit;
276         u32 guest_es_ar_bytes;
277         u32 guest_cs_ar_bytes;
278         u32 guest_ss_ar_bytes;
279         u32 guest_ds_ar_bytes;
280         u32 guest_fs_ar_bytes;
281         u32 guest_gs_ar_bytes;
282         u32 guest_ldtr_ar_bytes;
283         u32 guest_tr_ar_bytes;
284         u32 guest_interruptibility_info;
285         u32 guest_activity_state;
286         u32 guest_sysenter_cs;
287         u32 host_ia32_sysenter_cs;
288         u32 padding32[8]; /* room for future expansion */
289         u16 virtual_processor_id;
290         u16 guest_es_selector;
291         u16 guest_cs_selector;
292         u16 guest_ss_selector;
293         u16 guest_ds_selector;
294         u16 guest_fs_selector;
295         u16 guest_gs_selector;
296         u16 guest_ldtr_selector;
297         u16 guest_tr_selector;
298         u16 host_es_selector;
299         u16 host_cs_selector;
300         u16 host_ss_selector;
301         u16 host_ds_selector;
302         u16 host_fs_selector;
303         u16 host_gs_selector;
304         u16 host_tr_selector;
305 };
306
307 /*
308  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
309  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
310  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
311  */
312 #define VMCS12_REVISION 0x11e57ed0
313
314 /*
315  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
316  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
317  * current implementation, 4K are reserved to avoid future complications.
318  */
319 #define VMCS12_SIZE 0x1000
320
321 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
322 struct vmcs02_list {
323         struct list_head list;
324         gpa_t vmptr;
325         struct loaded_vmcs vmcs02;
326 };
327
328 /*
329  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
330  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
331  */
332 struct nested_vmx {
333         /* Has the level1 guest done vmxon? */
334         bool vmxon;
335
336         /* The guest-physical address of the current VMCS L1 keeps for L2 */
337         gpa_t current_vmptr;
338         /* The host-usable pointer to the above */
339         struct page *current_vmcs12_page;
340         struct vmcs12 *current_vmcs12;
341
342         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
343         struct list_head vmcs02_pool;
344         int vmcs02_num;
345         u64 vmcs01_tsc_offset;
346         /* L2 must run next, and mustn't decide to exit to L1. */
347         bool nested_run_pending;
348         /*
349          * Guest pages referred to in vmcs02 with host-physical pointers, so
350          * we must keep them pinned while L2 runs.
351          */
352         struct page *apic_access_page;
353 };
354
355 struct vcpu_vmx {
356         struct kvm_vcpu       vcpu;
357         unsigned long         host_rsp;
358         u8                    fail;
359         u8                    cpl;
360         bool                  nmi_known_unmasked;
361         u32                   exit_intr_info;
362         u32                   idt_vectoring_info;
363         ulong                 rflags;
364         struct shared_msr_entry *guest_msrs;
365         int                   nmsrs;
366         int                   save_nmsrs;
367 #ifdef CONFIG_X86_64
368         u64                   msr_host_kernel_gs_base;
369         u64                   msr_guest_kernel_gs_base;
370 #endif
371         /*
372          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
373          * non-nested (L1) guest, it always points to vmcs01. For a nested
374          * guest (L2), it points to a different VMCS.
375          */
376         struct loaded_vmcs    vmcs01;
377         struct loaded_vmcs   *loaded_vmcs;
378         bool                  __launched; /* temporary, used in vmx_vcpu_run */
379         struct msr_autoload {
380                 unsigned nr;
381                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
382                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
383         } msr_autoload;
384         struct {
385                 int           loaded;
386                 u16           fs_sel, gs_sel, ldt_sel;
387                 int           gs_ldt_reload_needed;
388                 int           fs_reload_needed;
389         } host_state;
390         struct {
391                 int vm86_active;
392                 ulong save_rflags;
393                 struct kvm_save_segment {
394                         u16 selector;
395                         unsigned long base;
396                         u32 limit;
397                         u32 ar;
398                 } tr, es, ds, fs, gs;
399         } rmode;
400         struct {
401                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
402                 struct kvm_save_segment seg[8];
403         } segment_cache;
404         int vpid;
405         bool emulation_required;
406
407         /* Support for vnmi-less CPUs */
408         int soft_vnmi_blocked;
409         ktime_t entry_time;
410         s64 vnmi_blocked_time;
411         u32 exit_reason;
412
413         bool rdtscp_enabled;
414
415         /* Support for a guest hypervisor (nested VMX) */
416         struct nested_vmx nested;
417 };
418
419 enum segment_cache_field {
420         SEG_FIELD_SEL = 0,
421         SEG_FIELD_BASE = 1,
422         SEG_FIELD_LIMIT = 2,
423         SEG_FIELD_AR = 3,
424
425         SEG_FIELD_NR = 4
426 };
427
428 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
429 {
430         return container_of(vcpu, struct vcpu_vmx, vcpu);
431 }
432
433 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
434 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
435 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
436                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
437
438 static unsigned short vmcs_field_to_offset_table[] = {
439         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
440         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
441         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
442         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
443         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
444         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
445         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
446         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
447         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
448         FIELD(HOST_ES_SELECTOR, host_es_selector),
449         FIELD(HOST_CS_SELECTOR, host_cs_selector),
450         FIELD(HOST_SS_SELECTOR, host_ss_selector),
451         FIELD(HOST_DS_SELECTOR, host_ds_selector),
452         FIELD(HOST_FS_SELECTOR, host_fs_selector),
453         FIELD(HOST_GS_SELECTOR, host_gs_selector),
454         FIELD(HOST_TR_SELECTOR, host_tr_selector),
455         FIELD64(IO_BITMAP_A, io_bitmap_a),
456         FIELD64(IO_BITMAP_B, io_bitmap_b),
457         FIELD64(MSR_BITMAP, msr_bitmap),
458         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
459         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
460         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
461         FIELD64(TSC_OFFSET, tsc_offset),
462         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
463         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
464         FIELD64(EPT_POINTER, ept_pointer),
465         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
466         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
467         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
468         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
469         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
470         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
471         FIELD64(GUEST_PDPTR0, guest_pdptr0),
472         FIELD64(GUEST_PDPTR1, guest_pdptr1),
473         FIELD64(GUEST_PDPTR2, guest_pdptr2),
474         FIELD64(GUEST_PDPTR3, guest_pdptr3),
475         FIELD64(HOST_IA32_PAT, host_ia32_pat),
476         FIELD64(HOST_IA32_EFER, host_ia32_efer),
477         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
478         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
479         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
480         FIELD(EXCEPTION_BITMAP, exception_bitmap),
481         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
482         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
483         FIELD(CR3_TARGET_COUNT, cr3_target_count),
484         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
485         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
486         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
487         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
488         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
489         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
490         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
491         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
492         FIELD(TPR_THRESHOLD, tpr_threshold),
493         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
494         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
495         FIELD(VM_EXIT_REASON, vm_exit_reason),
496         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
497         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
498         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
499         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
500         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
501         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
502         FIELD(GUEST_ES_LIMIT, guest_es_limit),
503         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
504         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
505         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
506         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
507         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
508         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
509         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
510         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
511         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
512         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
513         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
514         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
515         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
516         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
517         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
518         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
519         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
520         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
521         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
522         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
523         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
524         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
525         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
526         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
527         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
528         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
529         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
530         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
531         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
532         FIELD(EXIT_QUALIFICATION, exit_qualification),
533         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
534         FIELD(GUEST_CR0, guest_cr0),
535         FIELD(GUEST_CR3, guest_cr3),
536         FIELD(GUEST_CR4, guest_cr4),
537         FIELD(GUEST_ES_BASE, guest_es_base),
538         FIELD(GUEST_CS_BASE, guest_cs_base),
539         FIELD(GUEST_SS_BASE, guest_ss_base),
540         FIELD(GUEST_DS_BASE, guest_ds_base),
541         FIELD(GUEST_FS_BASE, guest_fs_base),
542         FIELD(GUEST_GS_BASE, guest_gs_base),
543         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
544         FIELD(GUEST_TR_BASE, guest_tr_base),
545         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
546         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
547         FIELD(GUEST_DR7, guest_dr7),
548         FIELD(GUEST_RSP, guest_rsp),
549         FIELD(GUEST_RIP, guest_rip),
550         FIELD(GUEST_RFLAGS, guest_rflags),
551         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
552         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
553         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
554         FIELD(HOST_CR0, host_cr0),
555         FIELD(HOST_CR3, host_cr3),
556         FIELD(HOST_CR4, host_cr4),
557         FIELD(HOST_FS_BASE, host_fs_base),
558         FIELD(HOST_GS_BASE, host_gs_base),
559         FIELD(HOST_TR_BASE, host_tr_base),
560         FIELD(HOST_GDTR_BASE, host_gdtr_base),
561         FIELD(HOST_IDTR_BASE, host_idtr_base),
562         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
563         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
564         FIELD(HOST_RSP, host_rsp),
565         FIELD(HOST_RIP, host_rip),
566 };
567 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
568
569 static inline short vmcs_field_to_offset(unsigned long field)
570 {
571         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
572                 return -1;
573         return vmcs_field_to_offset_table[field];
574 }
575
576 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
577 {
578         return to_vmx(vcpu)->nested.current_vmcs12;
579 }
580
581 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
582 {
583         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
584         if (is_error_page(page)) {
585                 kvm_release_page_clean(page);
586                 return NULL;
587         }
588         return page;
589 }
590
591 static void nested_release_page(struct page *page)
592 {
593         kvm_release_page_dirty(page);
594 }
595
596 static void nested_release_page_clean(struct page *page)
597 {
598         kvm_release_page_clean(page);
599 }
600
601 static u64 construct_eptp(unsigned long root_hpa);
602 static void kvm_cpu_vmxon(u64 addr);
603 static void kvm_cpu_vmxoff(void);
604 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
605 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
606
607 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
608 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
609 /*
610  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
611  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
612  */
613 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
614 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
615
616 static unsigned long *vmx_io_bitmap_a;
617 static unsigned long *vmx_io_bitmap_b;
618 static unsigned long *vmx_msr_bitmap_legacy;
619 static unsigned long *vmx_msr_bitmap_longmode;
620
621 static bool cpu_has_load_ia32_efer;
622
623 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
624 static DEFINE_SPINLOCK(vmx_vpid_lock);
625
626 static struct vmcs_config {
627         int size;
628         int order;
629         u32 revision_id;
630         u32 pin_based_exec_ctrl;
631         u32 cpu_based_exec_ctrl;
632         u32 cpu_based_2nd_exec_ctrl;
633         u32 vmexit_ctrl;
634         u32 vmentry_ctrl;
635 } vmcs_config;
636
637 static struct vmx_capability {
638         u32 ept;
639         u32 vpid;
640 } vmx_capability;
641
642 #define VMX_SEGMENT_FIELD(seg)                                  \
643         [VCPU_SREG_##seg] = {                                   \
644                 .selector = GUEST_##seg##_SELECTOR,             \
645                 .base = GUEST_##seg##_BASE,                     \
646                 .limit = GUEST_##seg##_LIMIT,                   \
647                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
648         }
649
650 static struct kvm_vmx_segment_field {
651         unsigned selector;
652         unsigned base;
653         unsigned limit;
654         unsigned ar_bytes;
655 } kvm_vmx_segment_fields[] = {
656         VMX_SEGMENT_FIELD(CS),
657         VMX_SEGMENT_FIELD(DS),
658         VMX_SEGMENT_FIELD(ES),
659         VMX_SEGMENT_FIELD(FS),
660         VMX_SEGMENT_FIELD(GS),
661         VMX_SEGMENT_FIELD(SS),
662         VMX_SEGMENT_FIELD(TR),
663         VMX_SEGMENT_FIELD(LDTR),
664 };
665
666 static u64 host_efer;
667
668 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
669
670 /*
671  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
672  * away by decrementing the array size.
673  */
674 static const u32 vmx_msr_index[] = {
675 #ifdef CONFIG_X86_64
676         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
677 #endif
678         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
679 };
680 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
681
682 static inline bool is_page_fault(u32 intr_info)
683 {
684         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
685                              INTR_INFO_VALID_MASK)) ==
686                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
687 }
688
689 static inline bool is_no_device(u32 intr_info)
690 {
691         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
692                              INTR_INFO_VALID_MASK)) ==
693                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
694 }
695
696 static inline bool is_invalid_opcode(u32 intr_info)
697 {
698         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
699                              INTR_INFO_VALID_MASK)) ==
700                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
701 }
702
703 static inline bool is_external_interrupt(u32 intr_info)
704 {
705         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
706                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
707 }
708
709 static inline bool is_machine_check(u32 intr_info)
710 {
711         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
712                              INTR_INFO_VALID_MASK)) ==
713                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
714 }
715
716 static inline bool cpu_has_vmx_msr_bitmap(void)
717 {
718         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
719 }
720
721 static inline bool cpu_has_vmx_tpr_shadow(void)
722 {
723         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
724 }
725
726 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
727 {
728         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
729 }
730
731 static inline bool cpu_has_secondary_exec_ctrls(void)
732 {
733         return vmcs_config.cpu_based_exec_ctrl &
734                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
735 }
736
737 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
738 {
739         return vmcs_config.cpu_based_2nd_exec_ctrl &
740                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
741 }
742
743 static inline bool cpu_has_vmx_flexpriority(void)
744 {
745         return cpu_has_vmx_tpr_shadow() &&
746                 cpu_has_vmx_virtualize_apic_accesses();
747 }
748
749 static inline bool cpu_has_vmx_ept_execute_only(void)
750 {
751         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
752 }
753
754 static inline bool cpu_has_vmx_eptp_uncacheable(void)
755 {
756         return vmx_capability.ept & VMX_EPTP_UC_BIT;
757 }
758
759 static inline bool cpu_has_vmx_eptp_writeback(void)
760 {
761         return vmx_capability.ept & VMX_EPTP_WB_BIT;
762 }
763
764 static inline bool cpu_has_vmx_ept_2m_page(void)
765 {
766         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
767 }
768
769 static inline bool cpu_has_vmx_ept_1g_page(void)
770 {
771         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
772 }
773
774 static inline bool cpu_has_vmx_ept_4levels(void)
775 {
776         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
777 }
778
779 static inline bool cpu_has_vmx_invept_individual_addr(void)
780 {
781         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
782 }
783
784 static inline bool cpu_has_vmx_invept_context(void)
785 {
786         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
787 }
788
789 static inline bool cpu_has_vmx_invept_global(void)
790 {
791         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
792 }
793
794 static inline bool cpu_has_vmx_invvpid_single(void)
795 {
796         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
797 }
798
799 static inline bool cpu_has_vmx_invvpid_global(void)
800 {
801         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
802 }
803
804 static inline bool cpu_has_vmx_ept(void)
805 {
806         return vmcs_config.cpu_based_2nd_exec_ctrl &
807                 SECONDARY_EXEC_ENABLE_EPT;
808 }
809
810 static inline bool cpu_has_vmx_unrestricted_guest(void)
811 {
812         return vmcs_config.cpu_based_2nd_exec_ctrl &
813                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
814 }
815
816 static inline bool cpu_has_vmx_ple(void)
817 {
818         return vmcs_config.cpu_based_2nd_exec_ctrl &
819                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
820 }
821
822 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
823 {
824         return flexpriority_enabled && irqchip_in_kernel(kvm);
825 }
826
827 static inline bool cpu_has_vmx_vpid(void)
828 {
829         return vmcs_config.cpu_based_2nd_exec_ctrl &
830                 SECONDARY_EXEC_ENABLE_VPID;
831 }
832
833 static inline bool cpu_has_vmx_rdtscp(void)
834 {
835         return vmcs_config.cpu_based_2nd_exec_ctrl &
836                 SECONDARY_EXEC_RDTSCP;
837 }
838
839 static inline bool cpu_has_virtual_nmis(void)
840 {
841         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
842 }
843
844 static inline bool cpu_has_vmx_wbinvd_exit(void)
845 {
846         return vmcs_config.cpu_based_2nd_exec_ctrl &
847                 SECONDARY_EXEC_WBINVD_EXITING;
848 }
849
850 static inline bool report_flexpriority(void)
851 {
852         return flexpriority_enabled;
853 }
854
855 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
856 {
857         return vmcs12->cpu_based_vm_exec_control & bit;
858 }
859
860 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
861 {
862         return (vmcs12->cpu_based_vm_exec_control &
863                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
864                 (vmcs12->secondary_vm_exec_control & bit);
865 }
866
867 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
868         struct kvm_vcpu *vcpu)
869 {
870         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
871 }
872
873 static inline bool is_exception(u32 intr_info)
874 {
875         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
876                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
877 }
878
879 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
880 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
881                         struct vmcs12 *vmcs12,
882                         u32 reason, unsigned long qualification);
883
884 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
885 {
886         int i;
887
888         for (i = 0; i < vmx->nmsrs; ++i)
889                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
890                         return i;
891         return -1;
892 }
893
894 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
895 {
896     struct {
897         u64 vpid : 16;
898         u64 rsvd : 48;
899         u64 gva;
900     } operand = { vpid, 0, gva };
901
902     asm volatile (__ex(ASM_VMX_INVVPID)
903                   /* CF==1 or ZF==1 --> rc = -1 */
904                   "; ja 1f ; ud2 ; 1:"
905                   : : "a"(&operand), "c"(ext) : "cc", "memory");
906 }
907
908 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
909 {
910         struct {
911                 u64 eptp, gpa;
912         } operand = {eptp, gpa};
913
914         asm volatile (__ex(ASM_VMX_INVEPT)
915                         /* CF==1 or ZF==1 --> rc = -1 */
916                         "; ja 1f ; ud2 ; 1:\n"
917                         : : "a" (&operand), "c" (ext) : "cc", "memory");
918 }
919
920 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
921 {
922         int i;
923
924         i = __find_msr_index(vmx, msr);
925         if (i >= 0)
926                 return &vmx->guest_msrs[i];
927         return NULL;
928 }
929
930 static void vmcs_clear(struct vmcs *vmcs)
931 {
932         u64 phys_addr = __pa(vmcs);
933         u8 error;
934
935         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
936                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
937                       : "cc", "memory");
938         if (error)
939                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
940                        vmcs, phys_addr);
941 }
942
943 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
944 {
945         vmcs_clear(loaded_vmcs->vmcs);
946         loaded_vmcs->cpu = -1;
947         loaded_vmcs->launched = 0;
948 }
949
950 static void vmcs_load(struct vmcs *vmcs)
951 {
952         u64 phys_addr = __pa(vmcs);
953         u8 error;
954
955         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
956                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
957                         : "cc", "memory");
958         if (error)
959                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
960                        vmcs, phys_addr);
961 }
962
963 static void __loaded_vmcs_clear(void *arg)
964 {
965         struct loaded_vmcs *loaded_vmcs = arg;
966         int cpu = raw_smp_processor_id();
967
968         if (loaded_vmcs->cpu != cpu)
969                 return; /* vcpu migration can race with cpu offline */
970         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
971                 per_cpu(current_vmcs, cpu) = NULL;
972         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
973         loaded_vmcs_init(loaded_vmcs);
974 }
975
976 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
977 {
978         if (loaded_vmcs->cpu != -1)
979                 smp_call_function_single(
980                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
981 }
982
983 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
984 {
985         if (vmx->vpid == 0)
986                 return;
987
988         if (cpu_has_vmx_invvpid_single())
989                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
990 }
991
992 static inline void vpid_sync_vcpu_global(void)
993 {
994         if (cpu_has_vmx_invvpid_global())
995                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
996 }
997
998 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
999 {
1000         if (cpu_has_vmx_invvpid_single())
1001                 vpid_sync_vcpu_single(vmx);
1002         else
1003                 vpid_sync_vcpu_global();
1004 }
1005
1006 static inline void ept_sync_global(void)
1007 {
1008         if (cpu_has_vmx_invept_global())
1009                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1010 }
1011
1012 static inline void ept_sync_context(u64 eptp)
1013 {
1014         if (enable_ept) {
1015                 if (cpu_has_vmx_invept_context())
1016                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1017                 else
1018                         ept_sync_global();
1019         }
1020 }
1021
1022 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1023 {
1024         if (enable_ept) {
1025                 if (cpu_has_vmx_invept_individual_addr())
1026                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1027                                         eptp, gpa);
1028                 else
1029                         ept_sync_context(eptp);
1030         }
1031 }
1032
1033 static __always_inline unsigned long vmcs_readl(unsigned long field)
1034 {
1035         unsigned long value;
1036
1037         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1038                       : "=a"(value) : "d"(field) : "cc");
1039         return value;
1040 }
1041
1042 static __always_inline u16 vmcs_read16(unsigned long field)
1043 {
1044         return vmcs_readl(field);
1045 }
1046
1047 static __always_inline u32 vmcs_read32(unsigned long field)
1048 {
1049         return vmcs_readl(field);
1050 }
1051
1052 static __always_inline u64 vmcs_read64(unsigned long field)
1053 {
1054 #ifdef CONFIG_X86_64
1055         return vmcs_readl(field);
1056 #else
1057         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1058 #endif
1059 }
1060
1061 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1062 {
1063         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1064                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1065         dump_stack();
1066 }
1067
1068 static void vmcs_writel(unsigned long field, unsigned long value)
1069 {
1070         u8 error;
1071
1072         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1073                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1074         if (unlikely(error))
1075                 vmwrite_error(field, value);
1076 }
1077
1078 static void vmcs_write16(unsigned long field, u16 value)
1079 {
1080         vmcs_writel(field, value);
1081 }
1082
1083 static void vmcs_write32(unsigned long field, u32 value)
1084 {
1085         vmcs_writel(field, value);
1086 }
1087
1088 static void vmcs_write64(unsigned long field, u64 value)
1089 {
1090         vmcs_writel(field, value);
1091 #ifndef CONFIG_X86_64
1092         asm volatile ("");
1093         vmcs_writel(field+1, value >> 32);
1094 #endif
1095 }
1096
1097 static void vmcs_clear_bits(unsigned long field, u32 mask)
1098 {
1099         vmcs_writel(field, vmcs_readl(field) & ~mask);
1100 }
1101
1102 static void vmcs_set_bits(unsigned long field, u32 mask)
1103 {
1104         vmcs_writel(field, vmcs_readl(field) | mask);
1105 }
1106
1107 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1108 {
1109         vmx->segment_cache.bitmask = 0;
1110 }
1111
1112 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1113                                        unsigned field)
1114 {
1115         bool ret;
1116         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1117
1118         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1119                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1120                 vmx->segment_cache.bitmask = 0;
1121         }
1122         ret = vmx->segment_cache.bitmask & mask;
1123         vmx->segment_cache.bitmask |= mask;
1124         return ret;
1125 }
1126
1127 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1128 {
1129         u16 *p = &vmx->segment_cache.seg[seg].selector;
1130
1131         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1132                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1133         return *p;
1134 }
1135
1136 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1137 {
1138         ulong *p = &vmx->segment_cache.seg[seg].base;
1139
1140         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1141                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1142         return *p;
1143 }
1144
1145 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1146 {
1147         u32 *p = &vmx->segment_cache.seg[seg].limit;
1148
1149         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1150                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1151         return *p;
1152 }
1153
1154 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1155 {
1156         u32 *p = &vmx->segment_cache.seg[seg].ar;
1157
1158         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1159                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1160         return *p;
1161 }
1162
1163 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1164 {
1165         u32 eb;
1166
1167         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1168              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1169         if ((vcpu->guest_debug &
1170              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1171             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1172                 eb |= 1u << BP_VECTOR;
1173         if (to_vmx(vcpu)->rmode.vm86_active)
1174                 eb = ~0;
1175         if (enable_ept)
1176                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1177         if (vcpu->fpu_active)
1178                 eb &= ~(1u << NM_VECTOR);
1179
1180         /* When we are running a nested L2 guest and L1 specified for it a
1181          * certain exception bitmap, we must trap the same exceptions and pass
1182          * them to L1. When running L2, we will only handle the exceptions
1183          * specified above if L1 did not want them.
1184          */
1185         if (is_guest_mode(vcpu))
1186                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1187
1188         vmcs_write32(EXCEPTION_BITMAP, eb);
1189 }
1190
1191 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1192 {
1193         unsigned i;
1194         struct msr_autoload *m = &vmx->msr_autoload;
1195
1196         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1197                 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1198                 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1199                 return;
1200         }
1201
1202         for (i = 0; i < m->nr; ++i)
1203                 if (m->guest[i].index == msr)
1204                         break;
1205
1206         if (i == m->nr)
1207                 return;
1208         --m->nr;
1209         m->guest[i] = m->guest[m->nr];
1210         m->host[i] = m->host[m->nr];
1211         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1212         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1213 }
1214
1215 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1216                                   u64 guest_val, u64 host_val)
1217 {
1218         unsigned i;
1219         struct msr_autoload *m = &vmx->msr_autoload;
1220
1221         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1222                 vmcs_write64(GUEST_IA32_EFER, guest_val);
1223                 vmcs_write64(HOST_IA32_EFER, host_val);
1224                 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1225                 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1226                 return;
1227         }
1228
1229         for (i = 0; i < m->nr; ++i)
1230                 if (m->guest[i].index == msr)
1231                         break;
1232
1233         if (i == m->nr) {
1234                 ++m->nr;
1235                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1236                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1237         }
1238
1239         m->guest[i].index = msr;
1240         m->guest[i].value = guest_val;
1241         m->host[i].index = msr;
1242         m->host[i].value = host_val;
1243 }
1244
1245 static void reload_tss(void)
1246 {
1247         /*
1248          * VT restores TR but not its size.  Useless.
1249          */
1250         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1251         struct desc_struct *descs;
1252
1253         descs = (void *)gdt->address;
1254         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1255         load_TR_desc();
1256 }
1257
1258 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1259 {
1260         u64 guest_efer;
1261         u64 ignore_bits;
1262
1263         guest_efer = vmx->vcpu.arch.efer;
1264
1265         /*
1266          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1267          * outside long mode
1268          */
1269         ignore_bits = EFER_NX | EFER_SCE;
1270 #ifdef CONFIG_X86_64
1271         ignore_bits |= EFER_LMA | EFER_LME;
1272         /* SCE is meaningful only in long mode on Intel */
1273         if (guest_efer & EFER_LMA)
1274                 ignore_bits &= ~(u64)EFER_SCE;
1275 #endif
1276         guest_efer &= ~ignore_bits;
1277         guest_efer |= host_efer & ignore_bits;
1278         vmx->guest_msrs[efer_offset].data = guest_efer;
1279         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1280
1281         clear_atomic_switch_msr(vmx, MSR_EFER);
1282         /* On ept, can't emulate nx, and must switch nx atomically */
1283         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1284                 guest_efer = vmx->vcpu.arch.efer;
1285                 if (!(guest_efer & EFER_LMA))
1286                         guest_efer &= ~EFER_LME;
1287                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1288                 return false;
1289         }
1290
1291         return true;
1292 }
1293
1294 static unsigned long segment_base(u16 selector)
1295 {
1296         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1297         struct desc_struct *d;
1298         unsigned long table_base;
1299         unsigned long v;
1300
1301         if (!(selector & ~3))
1302                 return 0;
1303
1304         table_base = gdt->address;
1305
1306         if (selector & 4) {           /* from ldt */
1307                 u16 ldt_selector = kvm_read_ldt();
1308
1309                 if (!(ldt_selector & ~3))
1310                         return 0;
1311
1312                 table_base = segment_base(ldt_selector);
1313         }
1314         d = (struct desc_struct *)(table_base + (selector & ~7));
1315         v = get_desc_base(d);
1316 #ifdef CONFIG_X86_64
1317        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1318                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1319 #endif
1320         return v;
1321 }
1322
1323 static inline unsigned long kvm_read_tr_base(void)
1324 {
1325         u16 tr;
1326         asm("str %0" : "=g"(tr));
1327         return segment_base(tr);
1328 }
1329
1330 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1331 {
1332         struct vcpu_vmx *vmx = to_vmx(vcpu);
1333         int i;
1334
1335         if (vmx->host_state.loaded)
1336                 return;
1337
1338         vmx->host_state.loaded = 1;
1339         /*
1340          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1341          * allow segment selectors with cpl > 0 or ti == 1.
1342          */
1343         vmx->host_state.ldt_sel = kvm_read_ldt();
1344         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1345         savesegment(fs, vmx->host_state.fs_sel);
1346         if (!(vmx->host_state.fs_sel & 7)) {
1347                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1348                 vmx->host_state.fs_reload_needed = 0;
1349         } else {
1350                 vmcs_write16(HOST_FS_SELECTOR, 0);
1351                 vmx->host_state.fs_reload_needed = 1;
1352         }
1353         savesegment(gs, vmx->host_state.gs_sel);
1354         if (!(vmx->host_state.gs_sel & 7))
1355                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1356         else {
1357                 vmcs_write16(HOST_GS_SELECTOR, 0);
1358                 vmx->host_state.gs_ldt_reload_needed = 1;
1359         }
1360
1361 #ifdef CONFIG_X86_64
1362         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1363         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1364 #else
1365         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1366         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1367 #endif
1368
1369 #ifdef CONFIG_X86_64
1370         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1371         if (is_long_mode(&vmx->vcpu))
1372                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1373 #endif
1374         for (i = 0; i < vmx->save_nmsrs; ++i)
1375                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1376                                    vmx->guest_msrs[i].data,
1377                                    vmx->guest_msrs[i].mask);
1378 }
1379
1380 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1381 {
1382         if (!vmx->host_state.loaded)
1383                 return;
1384
1385         ++vmx->vcpu.stat.host_state_reload;
1386         vmx->host_state.loaded = 0;
1387 #ifdef CONFIG_X86_64
1388         if (is_long_mode(&vmx->vcpu))
1389                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1390 #endif
1391         if (vmx->host_state.gs_ldt_reload_needed) {
1392                 kvm_load_ldt(vmx->host_state.ldt_sel);
1393 #ifdef CONFIG_X86_64
1394                 load_gs_index(vmx->host_state.gs_sel);
1395 #else
1396                 loadsegment(gs, vmx->host_state.gs_sel);
1397 #endif
1398         }
1399         if (vmx->host_state.fs_reload_needed)
1400                 loadsegment(fs, vmx->host_state.fs_sel);
1401         reload_tss();
1402 #ifdef CONFIG_X86_64
1403         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1404 #endif
1405         if (current_thread_info()->status & TS_USEDFPU)
1406                 clts();
1407         load_gdt(&__get_cpu_var(host_gdt));
1408 }
1409
1410 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1411 {
1412         preempt_disable();
1413         __vmx_load_host_state(vmx);
1414         preempt_enable();
1415 }
1416
1417 /*
1418  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1419  * vcpu mutex is already taken.
1420  */
1421 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1422 {
1423         struct vcpu_vmx *vmx = to_vmx(vcpu);
1424         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1425
1426         if (!vmm_exclusive)
1427                 kvm_cpu_vmxon(phys_addr);
1428         else if (vmx->loaded_vmcs->cpu != cpu)
1429                 loaded_vmcs_clear(vmx->loaded_vmcs);
1430
1431         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1432                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1433                 vmcs_load(vmx->loaded_vmcs->vmcs);
1434         }
1435
1436         if (vmx->loaded_vmcs->cpu != cpu) {
1437                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1438                 unsigned long sysenter_esp;
1439
1440                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1441                 local_irq_disable();
1442                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1443                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1444                 local_irq_enable();
1445
1446                 /*
1447                  * Linux uses per-cpu TSS and GDT, so set these when switching
1448                  * processors.
1449                  */
1450                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1451                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1452
1453                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1454                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1455                 vmx->loaded_vmcs->cpu = cpu;
1456         }
1457 }
1458
1459 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1460 {
1461         __vmx_load_host_state(to_vmx(vcpu));
1462         if (!vmm_exclusive) {
1463                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1464                 vcpu->cpu = -1;
1465                 kvm_cpu_vmxoff();
1466         }
1467 }
1468
1469 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1470 {
1471         ulong cr0;
1472
1473         if (vcpu->fpu_active)
1474                 return;
1475         vcpu->fpu_active = 1;
1476         cr0 = vmcs_readl(GUEST_CR0);
1477         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1478         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1479         vmcs_writel(GUEST_CR0, cr0);
1480         update_exception_bitmap(vcpu);
1481         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1482         if (is_guest_mode(vcpu))
1483                 vcpu->arch.cr0_guest_owned_bits &=
1484                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1485         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1486 }
1487
1488 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1489
1490 /*
1491  * Return the cr0 value that a nested guest would read. This is a combination
1492  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1493  * its hypervisor (cr0_read_shadow).
1494  */
1495 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1496 {
1497         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1498                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1499 }
1500 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1501 {
1502         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1503                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1504 }
1505
1506 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1507 {
1508         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1509          * set this *before* calling this function.
1510          */
1511         vmx_decache_cr0_guest_bits(vcpu);
1512         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1513         update_exception_bitmap(vcpu);
1514         vcpu->arch.cr0_guest_owned_bits = 0;
1515         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1516         if (is_guest_mode(vcpu)) {
1517                 /*
1518                  * L1's specified read shadow might not contain the TS bit,
1519                  * so now that we turned on shadowing of this bit, we need to
1520                  * set this bit of the shadow. Like in nested_vmx_run we need
1521                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1522                  * up-to-date here because we just decached cr0.TS (and we'll
1523                  * only update vmcs12->guest_cr0 on nested exit).
1524                  */
1525                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1526                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1527                         (vcpu->arch.cr0 & X86_CR0_TS);
1528                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1529         } else
1530                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1531 }
1532
1533 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1534 {
1535         unsigned long rflags, save_rflags;
1536
1537         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1538                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1539                 rflags = vmcs_readl(GUEST_RFLAGS);
1540                 if (to_vmx(vcpu)->rmode.vm86_active) {
1541                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1542                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1543                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1544                 }
1545                 to_vmx(vcpu)->rflags = rflags;
1546         }
1547         return to_vmx(vcpu)->rflags;
1548 }
1549
1550 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1551 {
1552         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1553         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1554         to_vmx(vcpu)->rflags = rflags;
1555         if (to_vmx(vcpu)->rmode.vm86_active) {
1556                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1557                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1558         }
1559         vmcs_writel(GUEST_RFLAGS, rflags);
1560 }
1561
1562 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1563 {
1564         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1565         int ret = 0;
1566
1567         if (interruptibility & GUEST_INTR_STATE_STI)
1568                 ret |= KVM_X86_SHADOW_INT_STI;
1569         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1570                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1571
1572         return ret & mask;
1573 }
1574
1575 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1576 {
1577         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1578         u32 interruptibility = interruptibility_old;
1579
1580         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1581
1582         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1583                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1584         else if (mask & KVM_X86_SHADOW_INT_STI)
1585                 interruptibility |= GUEST_INTR_STATE_STI;
1586
1587         if ((interruptibility != interruptibility_old))
1588                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1589 }
1590
1591 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1592 {
1593         unsigned long rip;
1594
1595         rip = kvm_rip_read(vcpu);
1596         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1597         kvm_rip_write(vcpu, rip);
1598
1599         /* skipping an emulated instruction also counts */
1600         vmx_set_interrupt_shadow(vcpu, 0);
1601 }
1602
1603 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1604 {
1605         /* Ensure that we clear the HLT state in the VMCS.  We don't need to
1606          * explicitly skip the instruction because if the HLT state is set, then
1607          * the instruction is already executing and RIP has already been
1608          * advanced. */
1609         if (!yield_on_hlt &&
1610             vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1611                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1612 }
1613
1614 /*
1615  * KVM wants to inject page-faults which it got to the guest. This function
1616  * checks whether in a nested guest, we need to inject them to L1 or L2.
1617  * This function assumes it is called with the exit reason in vmcs02 being
1618  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1619  * is running).
1620  */
1621 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1622 {
1623         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1624
1625         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1626         if (!(vmcs12->exception_bitmap & PF_VECTOR))
1627                 return 0;
1628
1629         nested_vmx_vmexit(vcpu);
1630         return 1;
1631 }
1632
1633 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1634                                 bool has_error_code, u32 error_code,
1635                                 bool reinject)
1636 {
1637         struct vcpu_vmx *vmx = to_vmx(vcpu);
1638         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1639
1640         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1641                 nested_pf_handled(vcpu))
1642                 return;
1643
1644         if (has_error_code) {
1645                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1646                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1647         }
1648
1649         if (vmx->rmode.vm86_active) {
1650                 int inc_eip = 0;
1651                 if (kvm_exception_is_soft(nr))
1652                         inc_eip = vcpu->arch.event_exit_inst_len;
1653                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1654                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1655                 return;
1656         }
1657
1658         if (kvm_exception_is_soft(nr)) {
1659                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1660                              vmx->vcpu.arch.event_exit_inst_len);
1661                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1662         } else
1663                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1664
1665         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1666         vmx_clear_hlt(vcpu);
1667 }
1668
1669 static bool vmx_rdtscp_supported(void)
1670 {
1671         return cpu_has_vmx_rdtscp();
1672 }
1673
1674 /*
1675  * Swap MSR entry in host/guest MSR entry array.
1676  */
1677 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1678 {
1679         struct shared_msr_entry tmp;
1680
1681         tmp = vmx->guest_msrs[to];
1682         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1683         vmx->guest_msrs[from] = tmp;
1684 }
1685
1686 /*
1687  * Set up the vmcs to automatically save and restore system
1688  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1689  * mode, as fiddling with msrs is very expensive.
1690  */
1691 static void setup_msrs(struct vcpu_vmx *vmx)
1692 {
1693         int save_nmsrs, index;
1694         unsigned long *msr_bitmap;
1695
1696         vmx_load_host_state(vmx);
1697         save_nmsrs = 0;
1698 #ifdef CONFIG_X86_64
1699         if (is_long_mode(&vmx->vcpu)) {
1700                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1701                 if (index >= 0)
1702                         move_msr_up(vmx, index, save_nmsrs++);
1703                 index = __find_msr_index(vmx, MSR_LSTAR);
1704                 if (index >= 0)
1705                         move_msr_up(vmx, index, save_nmsrs++);
1706                 index = __find_msr_index(vmx, MSR_CSTAR);
1707                 if (index >= 0)
1708                         move_msr_up(vmx, index, save_nmsrs++);
1709                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1710                 if (index >= 0 && vmx->rdtscp_enabled)
1711                         move_msr_up(vmx, index, save_nmsrs++);
1712                 /*
1713                  * MSR_STAR is only needed on long mode guests, and only
1714                  * if efer.sce is enabled.
1715                  */
1716                 index = __find_msr_index(vmx, MSR_STAR);
1717                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1718                         move_msr_up(vmx, index, save_nmsrs++);
1719         }
1720 #endif
1721         index = __find_msr_index(vmx, MSR_EFER);
1722         if (index >= 0 && update_transition_efer(vmx, index))
1723                 move_msr_up(vmx, index, save_nmsrs++);
1724
1725         vmx->save_nmsrs = save_nmsrs;
1726
1727         if (cpu_has_vmx_msr_bitmap()) {
1728                 if (is_long_mode(&vmx->vcpu))
1729                         msr_bitmap = vmx_msr_bitmap_longmode;
1730                 else
1731                         msr_bitmap = vmx_msr_bitmap_legacy;
1732
1733                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1734         }
1735 }
1736
1737 /*
1738  * reads and returns guest's timestamp counter "register"
1739  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1740  */
1741 static u64 guest_read_tsc(void)
1742 {
1743         u64 host_tsc, tsc_offset;
1744
1745         rdtscll(host_tsc);
1746         tsc_offset = vmcs_read64(TSC_OFFSET);
1747         return host_tsc + tsc_offset;
1748 }
1749
1750 /*
1751  * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1752  * ioctl. In this case the call-back should update internal vmx state to make
1753  * the changes effective.
1754  */
1755 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1756 {
1757         /* Nothing to do here */
1758 }
1759
1760 /*
1761  * writes 'offset' into guest's timestamp counter offset register
1762  */
1763 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1764 {
1765         vmcs_write64(TSC_OFFSET, offset);
1766         if (is_guest_mode(vcpu))
1767                 /*
1768                  * We're here if L1 chose not to trap the TSC MSR. Since
1769                  * prepare_vmcs12() does not copy tsc_offset, we need to also
1770                  * set the vmcs12 field here.
1771                  */
1772                 get_vmcs12(vcpu)->tsc_offset = offset -
1773                         to_vmx(vcpu)->nested.vmcs01_tsc_offset;
1774 }
1775
1776 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1777 {
1778         u64 offset = vmcs_read64(TSC_OFFSET);
1779         vmcs_write64(TSC_OFFSET, offset + adjustment);
1780         if (is_guest_mode(vcpu)) {
1781                 /* Even when running L2, the adjustment needs to apply to L1 */
1782                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1783         }
1784 }
1785
1786 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1787 {
1788         return target_tsc - native_read_tsc();
1789 }
1790
1791 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1792 {
1793         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1794         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1795 }
1796
1797 /*
1798  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1799  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1800  * all guests if the "nested" module option is off, and can also be disabled
1801  * for a single guest by disabling its VMX cpuid bit.
1802  */
1803 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1804 {
1805         return nested && guest_cpuid_has_vmx(vcpu);
1806 }
1807
1808 /*
1809  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1810  * returned for the various VMX controls MSRs when nested VMX is enabled.
1811  * The same values should also be used to verify that vmcs12 control fields are
1812  * valid during nested entry from L1 to L2.
1813  * Each of these control msrs has a low and high 32-bit half: A low bit is on
1814  * if the corresponding bit in the (32-bit) control field *must* be on, and a
1815  * bit in the high half is on if the corresponding bit in the control field
1816  * may be on. See also vmx_control_verify().
1817  * TODO: allow these variables to be modified (downgraded) by module options
1818  * or other means.
1819  */
1820 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1821 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1822 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1823 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1824 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1825 static __init void nested_vmx_setup_ctls_msrs(void)
1826 {
1827         /*
1828          * Note that as a general rule, the high half of the MSRs (bits in
1829          * the control fields which may be 1) should be initialized by the
1830          * intersection of the underlying hardware's MSR (i.e., features which
1831          * can be supported) and the list of features we want to expose -
1832          * because they are known to be properly supported in our code.
1833          * Also, usually, the low half of the MSRs (bits which must be 1) can
1834          * be set to 0, meaning that L1 may turn off any of these bits. The
1835          * reason is that if one of these bits is necessary, it will appear
1836          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1837          * fields of vmcs01 and vmcs02, will turn these bits off - and
1838          * nested_vmx_exit_handled() will not pass related exits to L1.
1839          * These rules have exceptions below.
1840          */
1841
1842         /* pin-based controls */
1843         /*
1844          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1845          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1846          */
1847         nested_vmx_pinbased_ctls_low = 0x16 ;
1848         nested_vmx_pinbased_ctls_high = 0x16 |
1849                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1850                 PIN_BASED_VIRTUAL_NMIS;
1851
1852         /* exit controls */
1853         nested_vmx_exit_ctls_low = 0;
1854         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1855 #ifdef CONFIG_X86_64
1856         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1857 #else
1858         nested_vmx_exit_ctls_high = 0;
1859 #endif
1860
1861         /* entry controls */
1862         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1863                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1864         nested_vmx_entry_ctls_low = 0;
1865         nested_vmx_entry_ctls_high &=
1866                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1867
1868         /* cpu-based controls */
1869         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1870                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1871         nested_vmx_procbased_ctls_low = 0;
1872         nested_vmx_procbased_ctls_high &=
1873                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1874                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1875                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1876                 CPU_BASED_CR3_STORE_EXITING |
1877 #ifdef CONFIG_X86_64
1878                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1879 #endif
1880                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1881                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1882                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1883         /*
1884          * We can allow some features even when not supported by the
1885          * hardware. For example, L1 can specify an MSR bitmap - and we
1886          * can use it to avoid exits to L1 - even when L0 runs L2
1887          * without MSR bitmaps.
1888          */
1889         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1890
1891         /* secondary cpu-based controls */
1892         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1893                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1894         nested_vmx_secondary_ctls_low = 0;
1895         nested_vmx_secondary_ctls_high &=
1896                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1897 }
1898
1899 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1900 {
1901         /*
1902          * Bits 0 in high must be 0, and bits 1 in low must be 1.
1903          */
1904         return ((control & high) | low) == control;
1905 }
1906
1907 static inline u64 vmx_control_msr(u32 low, u32 high)
1908 {
1909         return low | ((u64)high << 32);
1910 }
1911
1912 /*
1913  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1914  * also let it use VMX-specific MSRs.
1915  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1916  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1917  * like all other MSRs).
1918  */
1919 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1920 {
1921         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1922                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
1923                 /*
1924                  * According to the spec, processors which do not support VMX
1925                  * should throw a #GP(0) when VMX capability MSRs are read.
1926                  */
1927                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
1928                 return 1;
1929         }
1930
1931         switch (msr_index) {
1932         case MSR_IA32_FEATURE_CONTROL:
1933                 *pdata = 0;
1934                 break;
1935         case MSR_IA32_VMX_BASIC:
1936                 /*
1937                  * This MSR reports some information about VMX support. We
1938                  * should return information about the VMX we emulate for the
1939                  * guest, and the VMCS structure we give it - not about the
1940                  * VMX support of the underlying hardware.
1941                  */
1942                 *pdata = VMCS12_REVISION |
1943                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
1944                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
1945                 break;
1946         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1947         case MSR_IA32_VMX_PINBASED_CTLS:
1948                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
1949                                         nested_vmx_pinbased_ctls_high);
1950                 break;
1951         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1952         case MSR_IA32_VMX_PROCBASED_CTLS:
1953                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
1954                                         nested_vmx_procbased_ctls_high);
1955                 break;
1956         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1957         case MSR_IA32_VMX_EXIT_CTLS:
1958                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
1959                                         nested_vmx_exit_ctls_high);
1960                 break;
1961         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1962         case MSR_IA32_VMX_ENTRY_CTLS:
1963                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
1964                                         nested_vmx_entry_ctls_high);
1965                 break;
1966         case MSR_IA32_VMX_MISC:
1967                 *pdata = 0;
1968                 break;
1969         /*
1970          * These MSRs specify bits which the guest must keep fixed (on or off)
1971          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
1972          * We picked the standard core2 setting.
1973          */
1974 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
1975 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
1976         case MSR_IA32_VMX_CR0_FIXED0:
1977                 *pdata = VMXON_CR0_ALWAYSON;
1978                 break;
1979         case MSR_IA32_VMX_CR0_FIXED1:
1980                 *pdata = -1ULL;
1981                 break;
1982         case MSR_IA32_VMX_CR4_FIXED0:
1983                 *pdata = VMXON_CR4_ALWAYSON;
1984                 break;
1985         case MSR_IA32_VMX_CR4_FIXED1:
1986                 *pdata = -1ULL;
1987                 break;
1988         case MSR_IA32_VMX_VMCS_ENUM:
1989                 *pdata = 0x1f;
1990                 break;
1991         case MSR_IA32_VMX_PROCBASED_CTLS2:
1992                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
1993                                         nested_vmx_secondary_ctls_high);
1994                 break;
1995         case MSR_IA32_VMX_EPT_VPID_CAP:
1996                 /* Currently, no nested ept or nested vpid */
1997                 *pdata = 0;
1998                 break;
1999         default:
2000                 return 0;
2001         }
2002
2003         return 1;
2004 }
2005
2006 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2007 {
2008         if (!nested_vmx_allowed(vcpu))
2009                 return 0;
2010
2011         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2012                 /* TODO: the right thing. */
2013                 return 1;
2014         /*
2015          * No need to treat VMX capability MSRs specially: If we don't handle
2016          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2017          */
2018         return 0;
2019 }
2020
2021 /*
2022  * Reads an msr value (of 'msr_index') into 'pdata'.
2023  * Returns 0 on success, non-0 otherwise.
2024  * Assumes vcpu_load() was already called.
2025  */
2026 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2027 {
2028         u64 data;
2029         struct shared_msr_entry *msr;
2030
2031         if (!pdata) {
2032                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2033                 return -EINVAL;
2034         }
2035
2036         switch (msr_index) {
2037 #ifdef CONFIG_X86_64
2038         case MSR_FS_BASE:
2039                 data = vmcs_readl(GUEST_FS_BASE);
2040                 break;
2041         case MSR_GS_BASE:
2042                 data = vmcs_readl(GUEST_GS_BASE);
2043                 break;
2044         case MSR_KERNEL_GS_BASE:
2045                 vmx_load_host_state(to_vmx(vcpu));
2046                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2047                 break;
2048 #endif
2049         case MSR_EFER:
2050                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2051         case MSR_IA32_TSC:
2052                 data = guest_read_tsc();
2053                 break;
2054         case MSR_IA32_SYSENTER_CS:
2055                 data = vmcs_read32(GUEST_SYSENTER_CS);
2056                 break;
2057         case MSR_IA32_SYSENTER_EIP:
2058                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2059                 break;
2060         case MSR_IA32_SYSENTER_ESP:
2061                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2062                 break;
2063         case MSR_TSC_AUX:
2064                 if (!to_vmx(vcpu)->rdtscp_enabled)
2065                         return 1;
2066                 /* Otherwise falls through */
2067         default:
2068                 vmx_load_host_state(to_vmx(vcpu));
2069                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2070                         return 0;
2071                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2072                 if (msr) {
2073                         vmx_load_host_state(to_vmx(vcpu));
2074                         data = msr->data;
2075                         break;
2076                 }
2077                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2078         }
2079
2080         *pdata = data;
2081         return 0;
2082 }
2083
2084 /*
2085  * Writes msr value into into the appropriate "register".
2086  * Returns 0 on success, non-0 otherwise.
2087  * Assumes vcpu_load() was already called.
2088  */
2089 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2090 {
2091         struct vcpu_vmx *vmx = to_vmx(vcpu);
2092         struct shared_msr_entry *msr;
2093         int ret = 0;
2094
2095         switch (msr_index) {
2096         case MSR_EFER:
2097                 vmx_load_host_state(vmx);
2098                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2099                 break;
2100 #ifdef CONFIG_X86_64
2101         case MSR_FS_BASE:
2102                 vmx_segment_cache_clear(vmx);
2103                 vmcs_writel(GUEST_FS_BASE, data);
2104                 break;
2105         case MSR_GS_BASE:
2106                 vmx_segment_cache_clear(vmx);
2107                 vmcs_writel(GUEST_GS_BASE, data);
2108                 break;
2109         case MSR_KERNEL_GS_BASE:
2110                 vmx_load_host_state(vmx);
2111                 vmx->msr_guest_kernel_gs_base = data;
2112                 break;
2113 #endif
2114         case MSR_IA32_SYSENTER_CS:
2115                 vmcs_write32(GUEST_SYSENTER_CS, data);
2116                 break;
2117         case MSR_IA32_SYSENTER_EIP:
2118                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2119                 break;
2120         case MSR_IA32_SYSENTER_ESP:
2121                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2122                 break;
2123         case MSR_IA32_TSC:
2124                 kvm_write_tsc(vcpu, data);
2125                 break;
2126         case MSR_IA32_CR_PAT:
2127                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2128                         vmcs_write64(GUEST_IA32_PAT, data);
2129                         vcpu->arch.pat = data;
2130                         break;
2131                 }
2132                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2133                 break;
2134         case MSR_TSC_AUX:
2135                 if (!vmx->rdtscp_enabled)
2136                         return 1;
2137                 /* Check reserved bit, higher 32 bits should be zero */
2138                 if ((data >> 32) != 0)
2139                         return 1;
2140                 /* Otherwise falls through */
2141         default:
2142                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2143                         break;
2144                 msr = find_msr_entry(vmx, msr_index);
2145                 if (msr) {
2146                         vmx_load_host_state(vmx);
2147                         msr->data = data;
2148                         break;
2149                 }
2150                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2151         }
2152
2153         return ret;
2154 }
2155
2156 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2157 {
2158         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2159         switch (reg) {
2160         case VCPU_REGS_RSP:
2161                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2162                 break;
2163         case VCPU_REGS_RIP:
2164                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2165                 break;
2166         case VCPU_EXREG_PDPTR:
2167                 if (enable_ept)
2168                         ept_save_pdptrs(vcpu);
2169                 break;
2170         default:
2171                 break;
2172         }
2173 }
2174
2175 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2176 {
2177         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2178                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2179         else
2180                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2181
2182         update_exception_bitmap(vcpu);
2183 }
2184
2185 static __init int cpu_has_kvm_support(void)
2186 {
2187         return cpu_has_vmx();
2188 }
2189
2190 static __init int vmx_disabled_by_bios(void)
2191 {
2192         u64 msr;
2193
2194         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2195         if (msr & FEATURE_CONTROL_LOCKED) {
2196                 /* launched w/ TXT and VMX disabled */
2197                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2198                         && tboot_enabled())
2199                         return 1;
2200                 /* launched w/o TXT and VMX only enabled w/ TXT */
2201                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2202                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2203                         && !tboot_enabled()) {
2204                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2205                                 "activate TXT before enabling KVM\n");
2206                         return 1;
2207                 }
2208                 /* launched w/o TXT and VMX disabled */
2209                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2210                         && !tboot_enabled())
2211                         return 1;
2212         }
2213
2214         return 0;
2215 }
2216
2217 static void kvm_cpu_vmxon(u64 addr)
2218 {
2219         asm volatile (ASM_VMX_VMXON_RAX
2220                         : : "a"(&addr), "m"(addr)
2221                         : "memory", "cc");
2222 }
2223
2224 static int hardware_enable(void *garbage)
2225 {
2226         int cpu = raw_smp_processor_id();
2227         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2228         u64 old, test_bits;
2229
2230         if (read_cr4() & X86_CR4_VMXE)
2231                 return -EBUSY;
2232
2233         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2234         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2235
2236         test_bits = FEATURE_CONTROL_LOCKED;
2237         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2238         if (tboot_enabled())
2239                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2240
2241         if ((old & test_bits) != test_bits) {
2242                 /* enable and lock */
2243                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2244         }
2245         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2246
2247         if (vmm_exclusive) {
2248                 kvm_cpu_vmxon(phys_addr);
2249                 ept_sync_global();
2250         }
2251
2252         store_gdt(&__get_cpu_var(host_gdt));
2253
2254         return 0;
2255 }
2256
2257 static void vmclear_local_loaded_vmcss(void)
2258 {
2259         int cpu = raw_smp_processor_id();
2260         struct loaded_vmcs *v, *n;
2261
2262         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2263                                  loaded_vmcss_on_cpu_link)
2264                 __loaded_vmcs_clear(v);
2265 }
2266
2267
2268 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2269  * tricks.
2270  */
2271 static void kvm_cpu_vmxoff(void)
2272 {
2273         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2274 }
2275
2276 static void hardware_disable(void *garbage)
2277 {
2278         if (vmm_exclusive) {
2279                 vmclear_local_loaded_vmcss();
2280                 kvm_cpu_vmxoff();
2281         }
2282         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2283 }
2284
2285 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2286                                       u32 msr, u32 *result)
2287 {
2288         u32 vmx_msr_low, vmx_msr_high;
2289         u32 ctl = ctl_min | ctl_opt;
2290
2291         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2292
2293         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2294         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2295
2296         /* Ensure minimum (required) set of control bits are supported. */
2297         if (ctl_min & ~ctl)
2298                 return -EIO;
2299
2300         *result = ctl;
2301         return 0;
2302 }
2303
2304 static __init bool allow_1_setting(u32 msr, u32 ctl)
2305 {
2306         u32 vmx_msr_low, vmx_msr_high;
2307
2308         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2309         return vmx_msr_high & ctl;
2310 }
2311
2312 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2313 {
2314         u32 vmx_msr_low, vmx_msr_high;
2315         u32 min, opt, min2, opt2;
2316         u32 _pin_based_exec_control = 0;
2317         u32 _cpu_based_exec_control = 0;
2318         u32 _cpu_based_2nd_exec_control = 0;
2319         u32 _vmexit_control = 0;
2320         u32 _vmentry_control = 0;
2321
2322         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2323         opt = PIN_BASED_VIRTUAL_NMIS;
2324         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2325                                 &_pin_based_exec_control) < 0)
2326                 return -EIO;
2327
2328         min =
2329 #ifdef CONFIG_X86_64
2330               CPU_BASED_CR8_LOAD_EXITING |
2331               CPU_BASED_CR8_STORE_EXITING |
2332 #endif
2333               CPU_BASED_CR3_LOAD_EXITING |
2334               CPU_BASED_CR3_STORE_EXITING |
2335               CPU_BASED_USE_IO_BITMAPS |
2336               CPU_BASED_MOV_DR_EXITING |
2337               CPU_BASED_USE_TSC_OFFSETING |
2338               CPU_BASED_MWAIT_EXITING |
2339               CPU_BASED_MONITOR_EXITING |
2340               CPU_BASED_INVLPG_EXITING;
2341
2342         if (yield_on_hlt)
2343                 min |= CPU_BASED_HLT_EXITING;
2344
2345         opt = CPU_BASED_TPR_SHADOW |
2346               CPU_BASED_USE_MSR_BITMAPS |
2347               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2348         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2349                                 &_cpu_based_exec_control) < 0)
2350                 return -EIO;
2351 #ifdef CONFIG_X86_64
2352         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2353                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2354                                            ~CPU_BASED_CR8_STORE_EXITING;
2355 #endif
2356         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2357                 min2 = 0;
2358                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2359                         SECONDARY_EXEC_WBINVD_EXITING |
2360                         SECONDARY_EXEC_ENABLE_VPID |
2361                         SECONDARY_EXEC_ENABLE_EPT |
2362                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2363                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2364                         SECONDARY_EXEC_RDTSCP;
2365                 if (adjust_vmx_controls(min2, opt2,
2366                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2367                                         &_cpu_based_2nd_exec_control) < 0)
2368                         return -EIO;
2369         }
2370 #ifndef CONFIG_X86_64
2371         if (!(_cpu_based_2nd_exec_control &
2372                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2373                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2374 #endif
2375         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2376                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2377                    enabled */
2378                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2379                                              CPU_BASED_CR3_STORE_EXITING |
2380                                              CPU_BASED_INVLPG_EXITING);
2381                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2382                       vmx_capability.ept, vmx_capability.vpid);
2383         }
2384
2385         min = 0;
2386 #ifdef CONFIG_X86_64
2387         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2388 #endif
2389         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2390         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2391                                 &_vmexit_control) < 0)
2392                 return -EIO;
2393
2394         min = 0;
2395         opt = VM_ENTRY_LOAD_IA32_PAT;
2396         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2397                                 &_vmentry_control) < 0)
2398                 return -EIO;
2399
2400         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2401
2402         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2403         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2404                 return -EIO;
2405
2406 #ifdef CONFIG_X86_64
2407         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2408         if (vmx_msr_high & (1u<<16))
2409                 return -EIO;
2410 #endif
2411
2412         /* Require Write-Back (WB) memory type for VMCS accesses. */
2413         if (((vmx_msr_high >> 18) & 15) != 6)
2414                 return -EIO;
2415
2416         vmcs_conf->size = vmx_msr_high & 0x1fff;
2417         vmcs_conf->order = get_order(vmcs_config.size);
2418         vmcs_conf->revision_id = vmx_msr_low;
2419
2420         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2421         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2422         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2423         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2424         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2425
2426         cpu_has_load_ia32_efer =
2427                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2428                                 VM_ENTRY_LOAD_IA32_EFER)
2429                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2430                                    VM_EXIT_LOAD_IA32_EFER);
2431
2432         return 0;
2433 }
2434
2435 static struct vmcs *alloc_vmcs_cpu(int cpu)
2436 {
2437         int node = cpu_to_node(cpu);
2438         struct page *pages;
2439         struct vmcs *vmcs;
2440
2441         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2442         if (!pages)
2443                 return NULL;
2444         vmcs = page_address(pages);
2445         memset(vmcs, 0, vmcs_config.size);
2446         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2447         return vmcs;
2448 }
2449
2450 static struct vmcs *alloc_vmcs(void)
2451 {
2452         return alloc_vmcs_cpu(raw_smp_processor_id());
2453 }
2454
2455 static void free_vmcs(struct vmcs *vmcs)
2456 {
2457         free_pages((unsigned long)vmcs, vmcs_config.order);
2458 }
2459
2460 /*
2461  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2462  */
2463 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2464 {
2465         if (!loaded_vmcs->vmcs)
2466                 return;
2467         loaded_vmcs_clear(loaded_vmcs);
2468         free_vmcs(loaded_vmcs->vmcs);
2469         loaded_vmcs->vmcs = NULL;
2470 }
2471
2472 static void free_kvm_area(void)
2473 {
2474         int cpu;
2475
2476         for_each_possible_cpu(cpu) {
2477                 free_vmcs(per_cpu(vmxarea, cpu));
2478                 per_cpu(vmxarea, cpu) = NULL;
2479         }
2480 }
2481
2482 static __init int alloc_kvm_area(void)
2483 {
2484         int cpu;
2485
2486         for_each_possible_cpu(cpu) {
2487                 struct vmcs *vmcs;
2488
2489                 vmcs = alloc_vmcs_cpu(cpu);
2490                 if (!vmcs) {
2491                         free_kvm_area();
2492                         return -ENOMEM;
2493                 }
2494
2495                 per_cpu(vmxarea, cpu) = vmcs;
2496         }
2497         return 0;
2498 }
2499
2500 static __init int hardware_setup(void)
2501 {
2502         if (setup_vmcs_config(&vmcs_config) < 0)
2503                 return -EIO;
2504
2505         if (boot_cpu_has(X86_FEATURE_NX))
2506                 kvm_enable_efer_bits(EFER_NX);
2507
2508         if (!cpu_has_vmx_vpid())
2509                 enable_vpid = 0;
2510
2511         if (!cpu_has_vmx_ept() ||
2512             !cpu_has_vmx_ept_4levels()) {
2513                 enable_ept = 0;
2514                 enable_unrestricted_guest = 0;
2515         }
2516
2517         if (!cpu_has_vmx_unrestricted_guest())
2518                 enable_unrestricted_guest = 0;
2519
2520         if (!cpu_has_vmx_flexpriority())
2521                 flexpriority_enabled = 0;
2522
2523         if (!cpu_has_vmx_tpr_shadow())
2524                 kvm_x86_ops->update_cr8_intercept = NULL;
2525
2526         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2527                 kvm_disable_largepages();
2528
2529         if (!cpu_has_vmx_ple())
2530                 ple_gap = 0;
2531
2532         if (nested)
2533                 nested_vmx_setup_ctls_msrs();
2534
2535         return alloc_kvm_area();
2536 }
2537
2538 static __exit void hardware_unsetup(void)
2539 {
2540         free_kvm_area();
2541 }
2542
2543 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2544 {
2545         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2546
2547         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2548                 vmcs_write16(sf->selector, save->selector);
2549                 vmcs_writel(sf->base, save->base);
2550                 vmcs_write32(sf->limit, save->limit);
2551                 vmcs_write32(sf->ar_bytes, save->ar);
2552         } else {
2553                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2554                         << AR_DPL_SHIFT;
2555                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2556         }
2557 }
2558
2559 static void enter_pmode(struct kvm_vcpu *vcpu)
2560 {
2561         unsigned long flags;
2562         struct vcpu_vmx *vmx = to_vmx(vcpu);
2563
2564         vmx->emulation_required = 1;
2565         vmx->rmode.vm86_active = 0;
2566
2567         vmx_segment_cache_clear(vmx);
2568
2569         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2570         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2571         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2572         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2573
2574         flags = vmcs_readl(GUEST_RFLAGS);
2575         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2576         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2577         vmcs_writel(GUEST_RFLAGS, flags);
2578
2579         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2580                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2581
2582         update_exception_bitmap(vcpu);
2583
2584         if (emulate_invalid_guest_state)
2585                 return;
2586
2587         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2588         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2589         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2590         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2591
2592         vmx_segment_cache_clear(vmx);
2593
2594         vmcs_write16(GUEST_SS_SELECTOR, 0);
2595         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2596
2597         vmcs_write16(GUEST_CS_SELECTOR,
2598                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2599         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2600 }
2601
2602 static gva_t rmode_tss_base(struct kvm *kvm)
2603 {
2604         if (!kvm->arch.tss_addr) {
2605                 struct kvm_memslots *slots;
2606                 gfn_t base_gfn;
2607
2608                 slots = kvm_memslots(kvm);
2609                 base_gfn = slots->memslots[0].base_gfn +
2610                                  kvm->memslots->memslots[0].npages - 3;
2611                 return base_gfn << PAGE_SHIFT;
2612         }
2613         return kvm->arch.tss_addr;
2614 }
2615
2616 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2617 {
2618         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2619
2620         save->selector = vmcs_read16(sf->selector);
2621         save->base = vmcs_readl(sf->base);
2622         save->limit = vmcs_read32(sf->limit);
2623         save->ar = vmcs_read32(sf->ar_bytes);
2624         vmcs_write16(sf->selector, save->base >> 4);
2625         vmcs_write32(sf->base, save->base & 0xffff0);
2626         vmcs_write32(sf->limit, 0xffff);
2627         vmcs_write32(sf->ar_bytes, 0xf3);
2628         if (save->base & 0xf)
2629                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2630                             " aligned when entering protected mode (seg=%d)",
2631                             seg);
2632 }
2633
2634 static void enter_rmode(struct kvm_vcpu *vcpu)
2635 {
2636         unsigned long flags;
2637         struct vcpu_vmx *vmx = to_vmx(vcpu);
2638
2639         if (enable_unrestricted_guest)
2640                 return;
2641
2642         vmx->emulation_required = 1;
2643         vmx->rmode.vm86_active = 1;
2644
2645         /*
2646          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2647          * vcpu. Call it here with phys address pointing 16M below 4G.
2648          */
2649         if (!vcpu->kvm->arch.tss_addr) {
2650                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2651                              "called before entering vcpu\n");
2652                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2653                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2654                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2655         }
2656
2657         vmx_segment_cache_clear(vmx);
2658
2659         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2660         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2661         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2662
2663         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2664         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2665
2666         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2667         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2668
2669         flags = vmcs_readl(GUEST_RFLAGS);
2670         vmx->rmode.save_rflags = flags;
2671
2672         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2673
2674         vmcs_writel(GUEST_RFLAGS, flags);
2675         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2676         update_exception_bitmap(vcpu);
2677
2678         if (emulate_invalid_guest_state)
2679                 goto continue_rmode;
2680
2681         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2682         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2683         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2684
2685         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
2686         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2687         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2688                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
2689         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2690
2691         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2692         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2693         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2694         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
2695
2696 continue_rmode:
2697         kvm_mmu_reset_context(vcpu);
2698 }
2699
2700 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2701 {
2702         struct vcpu_vmx *vmx = to_vmx(vcpu);
2703         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2704
2705         if (!msr)
2706                 return;
2707
2708         /*
2709          * Force kernel_gs_base reloading before EFER changes, as control
2710          * of this msr depends on is_long_mode().
2711          */
2712         vmx_load_host_state(to_vmx(vcpu));
2713         vcpu->arch.efer = efer;
2714         if (efer & EFER_LMA) {
2715                 vmcs_write32(VM_ENTRY_CONTROLS,
2716                              vmcs_read32(VM_ENTRY_CONTROLS) |
2717                              VM_ENTRY_IA32E_MODE);
2718                 msr->data = efer;
2719         } else {
2720                 vmcs_write32(VM_ENTRY_CONTROLS,
2721                              vmcs_read32(VM_ENTRY_CONTROLS) &
2722                              ~VM_ENTRY_IA32E_MODE);
2723
2724                 msr->data = efer & ~EFER_LME;
2725         }
2726         setup_msrs(vmx);
2727 }
2728
2729 #ifdef CONFIG_X86_64
2730
2731 static void enter_lmode(struct kvm_vcpu *vcpu)
2732 {
2733         u32 guest_tr_ar;
2734
2735         vmx_segment_cache_clear(to_vmx(vcpu));
2736
2737         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2738         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2739                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
2740                        __func__);
2741                 vmcs_write32(GUEST_TR_AR_BYTES,
2742                              (guest_tr_ar & ~AR_TYPE_MASK)
2743                              | AR_TYPE_BUSY_64_TSS);
2744         }
2745         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2746 }
2747
2748 static void exit_lmode(struct kvm_vcpu *vcpu)
2749 {
2750         vmcs_write32(VM_ENTRY_CONTROLS,
2751                      vmcs_read32(VM_ENTRY_CONTROLS)
2752                      & ~VM_ENTRY_IA32E_MODE);
2753         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2754 }
2755
2756 #endif
2757
2758 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2759 {
2760         vpid_sync_context(to_vmx(vcpu));
2761         if (enable_ept) {
2762                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2763                         return;
2764                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2765         }
2766 }
2767
2768 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2769 {
2770         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2771
2772         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2773         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2774 }
2775
2776 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2777 {
2778         if (enable_ept && is_paging(vcpu))
2779                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2780         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2781 }
2782
2783 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2784 {
2785         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2786
2787         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2788         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2789 }
2790
2791 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2792 {
2793         if (!test_bit(VCPU_EXREG_PDPTR,
2794                       (unsigned long *)&vcpu->arch.regs_dirty))
2795                 return;
2796
2797         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2798                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2799                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2800                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2801                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2802         }
2803 }
2804
2805 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2806 {
2807         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2808                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2809                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2810                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2811                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2812         }
2813
2814         __set_bit(VCPU_EXREG_PDPTR,
2815                   (unsigned long *)&vcpu->arch.regs_avail);
2816         __set_bit(VCPU_EXREG_PDPTR,
2817                   (unsigned long *)&vcpu->arch.regs_dirty);
2818 }
2819
2820 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2821
2822 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2823                                         unsigned long cr0,
2824                                         struct kvm_vcpu *vcpu)
2825 {
2826         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2827                 vmx_decache_cr3(vcpu);
2828         if (!(cr0 & X86_CR0_PG)) {
2829                 /* From paging/starting to nonpaging */
2830                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2831                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2832                              (CPU_BASED_CR3_LOAD_EXITING |
2833                               CPU_BASED_CR3_STORE_EXITING));
2834                 vcpu->arch.cr0 = cr0;
2835                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2836         } else if (!is_paging(vcpu)) {
2837                 /* From nonpaging to paging */
2838                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2839                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2840                              ~(CPU_BASED_CR3_LOAD_EXITING |
2841                                CPU_BASED_CR3_STORE_EXITING));
2842                 vcpu->arch.cr0 = cr0;
2843                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2844         }
2845
2846         if (!(cr0 & X86_CR0_WP))
2847                 *hw_cr0 &= ~X86_CR0_WP;
2848 }
2849
2850 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2851 {
2852         struct vcpu_vmx *vmx = to_vmx(vcpu);
2853         unsigned long hw_cr0;
2854
2855         if (enable_unrestricted_guest)
2856                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2857                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2858         else
2859                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2860
2861         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2862                 enter_pmode(vcpu);
2863
2864         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2865                 enter_rmode(vcpu);
2866
2867 #ifdef CONFIG_X86_64
2868         if (vcpu->arch.efer & EFER_LME) {
2869                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2870                         enter_lmode(vcpu);
2871                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2872                         exit_lmode(vcpu);
2873         }
2874 #endif
2875
2876         if (enable_ept)
2877                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2878
2879         if (!vcpu->fpu_active)
2880                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2881
2882         vmcs_writel(CR0_READ_SHADOW, cr0);
2883         vmcs_writel(GUEST_CR0, hw_cr0);
2884         vcpu->arch.cr0 = cr0;
2885         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2886 }
2887
2888 static u64 construct_eptp(unsigned long root_hpa)
2889 {
2890         u64 eptp;
2891
2892         /* TODO write the value reading from MSR */
2893         eptp = VMX_EPT_DEFAULT_MT |
2894                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2895         eptp |= (root_hpa & PAGE_MASK);
2896
2897         return eptp;
2898 }
2899
2900 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2901 {
2902         unsigned long guest_cr3;
2903         u64 eptp;
2904
2905         guest_cr3 = cr3;
2906         if (enable_ept) {
2907                 eptp = construct_eptp(cr3);
2908                 vmcs_write64(EPT_POINTER, eptp);
2909                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
2910                         vcpu->kvm->arch.ept_identity_map_addr;
2911                 ept_load_pdptrs(vcpu);
2912         }
2913
2914         vmx_flush_tlb(vcpu);
2915         vmcs_writel(GUEST_CR3, guest_cr3);
2916 }
2917
2918 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2919 {
2920         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
2921                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2922
2923         if (cr4 & X86_CR4_VMXE) {
2924                 /*
2925                  * To use VMXON (and later other VMX instructions), a guest
2926                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
2927                  * So basically the check on whether to allow nested VMX
2928                  * is here.
2929                  */
2930                 if (!nested_vmx_allowed(vcpu))
2931                         return 1;
2932         } else if (to_vmx(vcpu)->nested.vmxon)
2933                 return 1;
2934
2935         vcpu->arch.cr4 = cr4;
2936         if (enable_ept) {
2937                 if (!is_paging(vcpu)) {
2938                         hw_cr4 &= ~X86_CR4_PAE;
2939                         hw_cr4 |= X86_CR4_PSE;
2940                 } else if (!(cr4 & X86_CR4_PAE)) {
2941                         hw_cr4 &= ~X86_CR4_PAE;
2942                 }
2943         }
2944
2945         vmcs_writel(CR4_READ_SHADOW, cr4);
2946         vmcs_writel(GUEST_CR4, hw_cr4);
2947         return 0;
2948 }
2949
2950 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2951                             struct kvm_segment *var, int seg)
2952 {
2953         struct vcpu_vmx *vmx = to_vmx(vcpu);
2954         struct kvm_save_segment *save;
2955         u32 ar;
2956
2957         if (vmx->rmode.vm86_active
2958             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2959                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2960                 || seg == VCPU_SREG_GS)
2961             && !emulate_invalid_guest_state) {
2962                 switch (seg) {
2963                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2964                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2965                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2966                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2967                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2968                 default: BUG();
2969                 }
2970                 var->selector = save->selector;
2971                 var->base = save->base;
2972                 var->limit = save->limit;
2973                 ar = save->ar;
2974                 if (seg == VCPU_SREG_TR
2975                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
2976                         goto use_saved_rmode_seg;
2977         }
2978         var->base = vmx_read_guest_seg_base(vmx, seg);
2979         var->limit = vmx_read_guest_seg_limit(vmx, seg);
2980         var->selector = vmx_read_guest_seg_selector(vmx, seg);
2981         ar = vmx_read_guest_seg_ar(vmx, seg);
2982 use_saved_rmode_seg:
2983         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2984                 ar = 0;
2985         var->type = ar & 15;
2986         var->s = (ar >> 4) & 1;
2987         var->dpl = (ar >> 5) & 3;
2988         var->present = (ar >> 7) & 1;
2989         var->avl = (ar >> 12) & 1;
2990         var->l = (ar >> 13) & 1;
2991         var->db = (ar >> 14) & 1;
2992         var->g = (ar >> 15) & 1;
2993         var->unusable = (ar >> 16) & 1;
2994 }
2995
2996 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2997 {
2998         struct kvm_segment s;
2999
3000         if (to_vmx(vcpu)->rmode.vm86_active) {
3001                 vmx_get_segment(vcpu, &s, seg);
3002                 return s.base;
3003         }
3004         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3005 }
3006
3007 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3008 {
3009         if (!is_protmode(vcpu))
3010                 return 0;
3011
3012         if (!is_long_mode(vcpu)
3013             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3014                 return 3;
3015
3016         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3017 }
3018
3019 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3020 {
3021         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3022                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3023                 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
3024         }
3025         return to_vmx(vcpu)->cpl;
3026 }
3027
3028
3029 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3030 {
3031         u32 ar;
3032
3033         if (var->unusable)
3034                 ar = 1 << 16;
3035         else {
3036                 ar = var->type & 15;
3037                 ar |= (var->s & 1) << 4;
3038                 ar |= (var->dpl & 3) << 5;
3039                 ar |= (var->present & 1) << 7;
3040                 ar |= (var->avl & 1) << 12;
3041                 ar |= (var->l & 1) << 13;
3042                 ar |= (var->db & 1) << 14;
3043                 ar |= (var->g & 1) << 15;
3044         }
3045         if (ar == 0) /* a 0 value means unusable */
3046                 ar = AR_UNUSABLE_MASK;
3047
3048         return ar;
3049 }
3050
3051 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3052                             struct kvm_segment *var, int seg)
3053 {
3054         struct vcpu_vmx *vmx = to_vmx(vcpu);
3055         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3056         u32 ar;
3057
3058         vmx_segment_cache_clear(vmx);
3059
3060         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3061                 vmcs_write16(sf->selector, var->selector);
3062                 vmx->rmode.tr.selector = var->selector;
3063                 vmx->rmode.tr.base = var->base;
3064                 vmx->rmode.tr.limit = var->limit;
3065                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3066                 return;
3067         }
3068         vmcs_writel(sf->base, var->base);
3069         vmcs_write32(sf->limit, var->limit);
3070         vmcs_write16(sf->selector, var->selector);
3071         if (vmx->rmode.vm86_active && var->s) {
3072                 /*
3073                  * Hack real-mode segments into vm86 compatibility.
3074                  */
3075                 if (var->base == 0xffff0000 && var->selector == 0xf000)
3076                         vmcs_writel(sf->base, 0xf0000);
3077                 ar = 0xf3;
3078         } else
3079                 ar = vmx_segment_access_rights(var);
3080
3081         /*
3082          *   Fix the "Accessed" bit in AR field of segment registers for older
3083          * qemu binaries.
3084          *   IA32 arch specifies that at the time of processor reset the
3085          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3086          * is setting it to 0 in the usedland code. This causes invalid guest
3087          * state vmexit when "unrestricted guest" mode is turned on.
3088          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3089          * tree. Newer qemu binaries with that qemu fix would not need this
3090          * kvm hack.
3091          */
3092         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3093                 ar |= 0x1; /* Accessed */
3094
3095         vmcs_write32(sf->ar_bytes, ar);
3096         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3097 }
3098
3099 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3100 {
3101         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3102
3103         *db = (ar >> 14) & 1;
3104         *l = (ar >> 13) & 1;
3105 }
3106
3107 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3108 {
3109         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3110         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3111 }
3112
3113 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3114 {
3115         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3116         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3117 }
3118
3119 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3120 {
3121         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3122         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3123 }
3124
3125 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3126 {
3127         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3128         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3129 }
3130
3131 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3132 {
3133         struct kvm_segment var;
3134         u32 ar;
3135
3136         vmx_get_segment(vcpu, &var, seg);
3137         ar = vmx_segment_access_rights(&var);
3138
3139         if (var.base != (var.selector << 4))
3140                 return false;
3141         if (var.limit != 0xffff)
3142                 return false;
3143         if (ar != 0xf3)
3144                 return false;
3145
3146         return true;
3147 }
3148
3149 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3150 {
3151         struct kvm_segment cs;
3152         unsigned int cs_rpl;
3153
3154         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3155         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3156
3157         if (cs.unusable)
3158                 return false;
3159         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3160                 return false;
3161         if (!cs.s)
3162                 return false;
3163         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3164                 if (cs.dpl > cs_rpl)
3165                         return false;
3166         } else {
3167                 if (cs.dpl != cs_rpl)
3168                         return false;
3169         }
3170         if (!cs.present)
3171                 return false;
3172
3173         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3174         return true;
3175 }
3176
3177 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3178 {
3179         struct kvm_segment ss;
3180         unsigned int ss_rpl;
3181
3182         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3183         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3184
3185         if (ss.unusable)
3186                 return true;
3187         if (ss.type != 3 && ss.type != 7)
3188                 return false;
3189         if (!ss.s)
3190                 return false;
3191         if (ss.dpl != ss_rpl) /* DPL != RPL */
3192                 return false;
3193         if (!ss.present)
3194                 return false;
3195
3196         return true;
3197 }
3198
3199 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3200 {
3201         struct kvm_segment var;
3202         unsigned int rpl;
3203
3204         vmx_get_segment(vcpu, &var, seg);
3205         rpl = var.selector & SELECTOR_RPL_MASK;
3206
3207         if (var.unusable)
3208                 return true;
3209         if (!var.s)
3210                 return false;
3211         if (!var.present)
3212                 return false;
3213         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3214                 if (var.dpl < rpl) /* DPL < RPL */
3215                         return false;
3216         }
3217
3218         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3219          * rights flags
3220          */
3221         return true;
3222 }
3223
3224 static bool tr_valid(struct kvm_vcpu *vcpu)
3225 {
3226         struct kvm_segment tr;
3227
3228         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3229
3230         if (tr.unusable)
3231                 return false;
3232         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3233                 return false;
3234         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3235                 return false;
3236         if (!tr.present)
3237                 return false;
3238
3239         return true;
3240 }
3241
3242 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3243 {
3244         struct kvm_segment ldtr;
3245
3246         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3247
3248         if (ldtr.unusable)
3249                 return true;
3250         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3251                 return false;
3252         if (ldtr.type != 2)
3253                 return false;
3254         if (!ldtr.present)
3255                 return false;
3256
3257         return true;
3258 }
3259
3260 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3261 {
3262         struct kvm_segment cs, ss;
3263
3264         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3265         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3266
3267         return ((cs.selector & SELECTOR_RPL_MASK) ==
3268                  (ss.selector & SELECTOR_RPL_MASK));
3269 }
3270
3271 /*
3272  * Check if guest state is valid. Returns true if valid, false if
3273  * not.
3274  * We assume that registers are always usable
3275  */
3276 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3277 {
3278         /* real mode guest state checks */
3279         if (!is_protmode(vcpu)) {
3280                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3281                         return false;
3282                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3283                         return false;
3284                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3285                         return false;
3286                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3287                         return false;
3288                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3289                         return false;
3290                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3291                         return false;
3292         } else {
3293         /* protected mode guest state checks */
3294                 if (!cs_ss_rpl_check(vcpu))
3295                         return false;
3296                 if (!code_segment_valid(vcpu))
3297                         return false;
3298                 if (!stack_segment_valid(vcpu))
3299                         return false;
3300                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3301                         return false;
3302                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3303                         return false;
3304                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3305                         return false;
3306                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3307                         return false;
3308                 if (!tr_valid(vcpu))
3309                         return false;
3310                 if (!ldtr_valid(vcpu))
3311                         return false;
3312         }
3313         /* TODO:
3314          * - Add checks on RIP
3315          * - Add checks on RFLAGS
3316          */
3317
3318         return true;
3319 }
3320
3321 static int init_rmode_tss(struct kvm *kvm)
3322 {
3323         gfn_t fn;
3324         u16 data = 0;
3325         int r, idx, ret = 0;
3326
3327         idx = srcu_read_lock(&kvm->srcu);
3328         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3329         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3330         if (r < 0)
3331                 goto out;
3332         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3333         r = kvm_write_guest_page(kvm, fn++, &data,
3334                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3335         if (r < 0)
3336                 goto out;
3337         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3338         if (r < 0)
3339                 goto out;
3340         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3341         if (r < 0)
3342                 goto out;
3343         data = ~0;
3344         r = kvm_write_guest_page(kvm, fn, &data,