arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/ftrace_event.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include <linux/hrtimer.h>
  35 #include "kvm_cache_regs.h"
  36 #include "x86.h"
  37
  38 #include <asm/io.h>
  39 #include <asm/desc.h>
  40 #include <asm/vmx.h>
  41 #include <asm/virtext.h>
  42 #include <asm/mce.h>
  43 #include <asm/i387.h>
  44 #include <asm/xcr.h>
  45 #include <asm/perf_event.h>
  46 #include <asm/debugreg.h>
  47 #include <asm/kexec.h>
  48
  49 #include "trace.h"
  50
  51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  52 #define __ex_clear(x, reg) \
  53         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  54
  55 MODULE_AUTHOR("Qumranet");
  56 MODULE_LICENSE("GPL");
  57
  58 static const struct x86_cpu_id vmx_cpu_id[] = {
  59         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  60         {}
  61 };
  62 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  63
  64 static bool __read_mostly enable_vpid = 1;
  65 module_param_named(vpid, enable_vpid, bool, 0444);
  66
  67 static bool __read_mostly flexpriority_enabled = 1;
  68 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  69
  70 static bool __read_mostly enable_ept = 1;
  71 module_param_named(ept, enable_ept, bool, S_IRUGO);
  72
  73 static bool __read_mostly enable_unrestricted_guest = 1;
  74 module_param_named(unrestricted_guest,
  75                         enable_unrestricted_guest, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_ept_ad_bits = 1;
  78 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  79
  80 static bool __read_mostly emulate_invalid_guest_state = true;
  81 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  82
  83 static bool __read_mostly vmm_exclusive = 1;
  84 module_param(vmm_exclusive, bool, S_IRUGO);
  85
  86 static bool __read_mostly fasteoi = 1;
  87 module_param(fasteoi, bool, S_IRUGO);
  88
  89 static bool __read_mostly enable_apicv = 1;
  90 module_param(enable_apicv, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_shadow_vmcs = 1;
  93 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  94 /*
  95  * If nested=1, nested virtualization is supported, i.e., guests may use
  96  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  97  * use VMX instructions.
  98  */
  99 static bool __read_mostly nested = 0;
 100 module_param(nested, bool, S_IRUGO);
 101
 102 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 103 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 104 #define KVM_VM_CR0_ALWAYS_ON                                            \
 105         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 106 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 107         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 108          | X86_CR4_OSXMMEXCPT)
 109
 110 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 111 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 112
 113 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 114
 115 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 116
 117 /*
 118  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 119  * ple_gap:    upper bound on the amount of time between two successive
 120  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 121  *             According to test, this time is usually smaller than 128 cycles.
 122  * ple_window: upper bound on the amount of time a guest is allowed to execute
 123  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 124  *             less than 2^12 cycles
 125  * Time is measured based on a counter that runs at the same rate as the TSC,
 126  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 127  */
 128 #define KVM_VMX_DEFAULT_PLE_GAP           128
 129 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 130 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 131 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 132 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 133                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 134
 135 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 136 module_param(ple_gap, int, S_IRUGO);
 137
 138 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 139 module_param(ple_window, int, S_IRUGO);
 140
 141 /* Default doubles per-vcpu window every exit. */
 142 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 143 module_param(ple_window_grow, int, S_IRUGO);
 144
 145 /* Default resets per-vcpu window every exit to ple_window. */
 146 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 147 module_param(ple_window_shrink, int, S_IRUGO);
 148
 149 /* Default is to compute the maximum so we can never overflow. */
 150 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 151 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 152 module_param(ple_window_max, int, S_IRUGO);
 153
 154 extern const ulong vmx_return;
 155
 156 #define NR_AUTOLOAD_MSRS 8
 157 #define VMCS02_POOL_SIZE 1
 158
 159 struct vmcs {
 160         u32 revision_id;
 161         u32 abort;
 162         char data[0];
 163 };
 164
 165 /*
 166  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 167  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 168  * loaded on this CPU (so we can clear them if the CPU goes down).
 169  */
 170 struct loaded_vmcs {
 171         struct vmcs *vmcs;
 172         int cpu;
 173         int launched;
 174         struct list_head loaded_vmcss_on_cpu_link;
 175 };
 176
 177 struct shared_msr_entry {
 178         unsigned index;
 179         u64 data;
 180         u64 mask;
 181 };
 182
 183 /*
 184  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 185  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 186  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 187  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 188  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 189  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 190  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 191  * underlying hardware which will be used to run L2.
 192  * This structure is packed to ensure that its layout is identical across
 193  * machines (necessary for live migration).
 194  * If there are changes in this struct, VMCS12_REVISION must be changed.
 195  */
 196 typedef u64 natural_width;
 197 struct __packed vmcs12 {
 198         /* According to the Intel spec, a VMCS region must start with the
 199          * following two fields. Then follow implementation-specific data.
 200          */
 201         u32 revision_id;
 202         u32 abort;
 203
 204         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 205         u32 padding[7]; /* room for future expansion */
 206
 207         u64 io_bitmap_a;
 208         u64 io_bitmap_b;
 209         u64 msr_bitmap;
 210         u64 vm_exit_msr_store_addr;
 211         u64 vm_exit_msr_load_addr;
 212         u64 vm_entry_msr_load_addr;
 213         u64 tsc_offset;
 214         u64 virtual_apic_page_addr;
 215         u64 apic_access_addr;
 216         u64 ept_pointer;
 217         u64 guest_physical_address;
 218         u64 vmcs_link_pointer;
 219         u64 guest_ia32_debugctl;
 220         u64 guest_ia32_pat;
 221         u64 guest_ia32_efer;
 222         u64 guest_ia32_perf_global_ctrl;
 223         u64 guest_pdptr0;
 224         u64 guest_pdptr1;
 225         u64 guest_pdptr2;
 226         u64 guest_pdptr3;
 227         u64 guest_bndcfgs;
 228         u64 host_ia32_pat;
 229         u64 host_ia32_efer;
 230         u64 host_ia32_perf_global_ctrl;
 231         u64 padding64[8]; /* room for future expansion */
 232         /*
 233          * To allow migration of L1 (complete with its L2 guests) between
 234          * machines of different natural widths (32 or 64 bit), we cannot have
 235          * unsigned long fields with no explict size. We use u64 (aliased
 236          * natural_width) instead. Luckily, x86 is little-endian.
 237          */
 238         natural_width cr0_guest_host_mask;
 239         natural_width cr4_guest_host_mask;
 240         natural_width cr0_read_shadow;
 241         natural_width cr4_read_shadow;
 242         natural_width cr3_target_value0;
 243         natural_width cr3_target_value1;
 244         natural_width cr3_target_value2;
 245         natural_width cr3_target_value3;
 246         natural_width exit_qualification;
 247         natural_width guest_linear_address;
 248         natural_width guest_cr0;
 249         natural_width guest_cr3;
 250         natural_width guest_cr4;
 251         natural_width guest_es_base;
 252         natural_width guest_cs_base;
 253         natural_width guest_ss_base;
 254         natural_width guest_ds_base;
 255         natural_width guest_fs_base;
 256         natural_width guest_gs_base;
 257         natural_width guest_ldtr_base;
 258         natural_width guest_tr_base;
 259         natural_width guest_gdtr_base;
 260         natural_width guest_idtr_base;
 261         natural_width guest_dr7;
 262         natural_width guest_rsp;
 263         natural_width guest_rip;
 264         natural_width guest_rflags;
 265         natural_width guest_pending_dbg_exceptions;
 266         natural_width guest_sysenter_esp;
 267         natural_width guest_sysenter_eip;
 268         natural_width host_cr0;
 269         natural_width host_cr3;
 270         natural_width host_cr4;
 271         natural_width host_fs_base;
 272         natural_width host_gs_base;
 273         natural_width host_tr_base;
 274         natural_width host_gdtr_base;
 275         natural_width host_idtr_base;
 276         natural_width host_ia32_sysenter_esp;
 277         natural_width host_ia32_sysenter_eip;
 278         natural_width host_rsp;
 279         natural_width host_rip;
 280         natural_width paddingl[8]; /* room for future expansion */
 281         u32 pin_based_vm_exec_control;
 282         u32 cpu_based_vm_exec_control;
 283         u32 exception_bitmap;
 284         u32 page_fault_error_code_mask;
 285         u32 page_fault_error_code_match;
 286         u32 cr3_target_count;
 287         u32 vm_exit_controls;
 288         u32 vm_exit_msr_store_count;
 289         u32 vm_exit_msr_load_count;
 290         u32 vm_entry_controls;
 291         u32 vm_entry_msr_load_count;
 292         u32 vm_entry_intr_info_field;
 293         u32 vm_entry_exception_error_code;
 294         u32 vm_entry_instruction_len;
 295         u32 tpr_threshold;
 296         u32 secondary_vm_exec_control;
 297         u32 vm_instruction_error;
 298         u32 vm_exit_reason;
 299         u32 vm_exit_intr_info;
 300         u32 vm_exit_intr_error_code;
 301         u32 idt_vectoring_info_field;
 302         u32 idt_vectoring_error_code;
 303         u32 vm_exit_instruction_len;
 304         u32 vmx_instruction_info;
 305         u32 guest_es_limit;
 306         u32 guest_cs_limit;
 307         u32 guest_ss_limit;
 308         u32 guest_ds_limit;
 309         u32 guest_fs_limit;
 310         u32 guest_gs_limit;
 311         u32 guest_ldtr_limit;
 312         u32 guest_tr_limit;
 313         u32 guest_gdtr_limit;
 314         u32 guest_idtr_limit;
 315         u32 guest_es_ar_bytes;
 316         u32 guest_cs_ar_bytes;
 317         u32 guest_ss_ar_bytes;
 318         u32 guest_ds_ar_bytes;
 319         u32 guest_fs_ar_bytes;
 320         u32 guest_gs_ar_bytes;
 321         u32 guest_ldtr_ar_bytes;
 322         u32 guest_tr_ar_bytes;
 323         u32 guest_interruptibility_info;
 324         u32 guest_activity_state;
 325         u32 guest_sysenter_cs;
 326         u32 host_ia32_sysenter_cs;
 327         u32 vmx_preemption_timer_value;
 328         u32 padding32[7]; /* room for future expansion */
 329         u16 virtual_processor_id;
 330         u16 guest_es_selector;
 331         u16 guest_cs_selector;
 332         u16 guest_ss_selector;
 333         u16 guest_ds_selector;
 334         u16 guest_fs_selector;
 335         u16 guest_gs_selector;
 336         u16 guest_ldtr_selector;
 337         u16 guest_tr_selector;
 338         u16 host_es_selector;
 339         u16 host_cs_selector;
 340         u16 host_ss_selector;
 341         u16 host_ds_selector;
 342         u16 host_fs_selector;
 343         u16 host_gs_selector;
 344         u16 host_tr_selector;
 345 };
 346
 347 /*
 348  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 349  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 350  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 351  */
 352 #define VMCS12_REVISION 0x11e57ed0
 353
 354 /*
 355  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 356  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 357  * current implementation, 4K are reserved to avoid future complications.
 358  */
 359 #define VMCS12_SIZE 0x1000
 360
 361 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 362 struct vmcs02_list {
 363         struct list_head list;
 364         gpa_t vmptr;
 365         struct loaded_vmcs vmcs02;
 366 };
 367
 368 /*
 369  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 370  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 371  */
 372 struct nested_vmx {
 373         /* Has the level1 guest done vmxon? */
 374         bool vmxon;
 375         gpa_t vmxon_ptr;
 376
 377         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 378         gpa_t current_vmptr;
 379         /* The host-usable pointer to the above */
 380         struct page *current_vmcs12_page;
 381         struct vmcs12 *current_vmcs12;
 382         struct vmcs *current_shadow_vmcs;
 383         /*
 384          * Indicates if the shadow vmcs must be updated with the
 385          * data hold by vmcs12
 386          */
 387         bool sync_shadow_vmcs;
 388
 389         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 390         struct list_head vmcs02_pool;
 391         int vmcs02_num;
 392         u64 vmcs01_tsc_offset;
 393         /* L2 must run next, and mustn't decide to exit to L1. */
 394         bool nested_run_pending;
 395         /*
 396          * Guest pages referred to in vmcs02 with host-physical pointers, so
 397          * we must keep them pinned while L2 runs.
 398          */
 399         struct page *apic_access_page;
 400         u64 msr_ia32_feature_control;
 401
 402         struct hrtimer preemption_timer;
 403         bool preemption_timer_expired;
 404
 405         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 406         u64 vmcs01_debugctl;
 407 };
 408
 409 #define POSTED_INTR_ON  0
 410 /* Posted-Interrupt Descriptor */
 411 struct pi_desc {
 412         u32 pir[8];     /* Posted interrupt requested */
 413         u32 control;    /* bit 0 of control is outstanding notification bit */
 414         u32 rsvd[7];
 415 } __aligned(64);
 416
 417 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 418 {
 419         return test_and_set_bit(POSTED_INTR_ON,
 420                         (unsigned long *)&pi_desc->control);
 421 }
 422
 423 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 424 {
 425         return test_and_clear_bit(POSTED_INTR_ON,
 426                         (unsigned long *)&pi_desc->control);
 427 }
 428
 429 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 430 {
 431         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 432 }
 433
 434 struct vcpu_vmx {
 435         struct kvm_vcpu       vcpu;
 436         unsigned long         host_rsp;
 437         u8                    fail;
 438         bool                  nmi_known_unmasked;
 439         u32                   exit_intr_info;
 440         u32                   idt_vectoring_info;
 441         ulong                 rflags;
 442         struct shared_msr_entry *guest_msrs;
 443         int                   nmsrs;
 444         int                   save_nmsrs;
 445         unsigned long         host_idt_base;
 446 #ifdef CONFIG_X86_64
 447         u64                   msr_host_kernel_gs_base;
 448         u64                   msr_guest_kernel_gs_base;
 449 #endif
 450         u32 vm_entry_controls_shadow;
 451         u32 vm_exit_controls_shadow;
 452         /*
 453          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 454          * non-nested (L1) guest, it always points to vmcs01. For a nested
 455          * guest (L2), it points to a different VMCS.
 456          */
 457         struct loaded_vmcs    vmcs01;
 458         struct loaded_vmcs   *loaded_vmcs;
 459         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 460         struct msr_autoload {
 461                 unsigned nr;
 462                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 463                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 464         } msr_autoload;
 465         struct {
 466                 int           loaded;
 467                 u16           fs_sel, gs_sel, ldt_sel;
 468 #ifdef CONFIG_X86_64
 469                 u16           ds_sel, es_sel;
 470 #endif
 471                 int           gs_ldt_reload_needed;
 472                 int           fs_reload_needed;
 473                 u64           msr_host_bndcfgs;
 474         } host_state;
 475         struct {
 476                 int vm86_active;
 477                 ulong save_rflags;
 478                 struct kvm_segment segs[8];
 479         } rmode;
 480         struct {
 481                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 482                 struct kvm_save_segment {
 483                         u16 selector;
 484                         unsigned long base;
 485                         u32 limit;
 486                         u32 ar;
 487                 } seg[8];
 488         } segment_cache;
 489         int vpid;
 490         bool emulation_required;
 491
 492         /* Support for vnmi-less CPUs */
 493         int soft_vnmi_blocked;
 494         ktime_t entry_time;
 495         s64 vnmi_blocked_time;
 496         u32 exit_reason;
 497
 498         bool rdtscp_enabled;
 499
 500         /* Posted interrupt descriptor */
 501         struct pi_desc pi_desc;
 502
 503         /* Support for a guest hypervisor (nested VMX) */
 504         struct nested_vmx nested;
 505
 506         /* Dynamic PLE window. */
 507         int ple_window;
 508         bool ple_window_dirty;
 509 };
 510
 511 enum segment_cache_field {
 512         SEG_FIELD_SEL = 0,
 513         SEG_FIELD_BASE = 1,
 514         SEG_FIELD_LIMIT = 2,
 515         SEG_FIELD_AR = 3,
 516
 517         SEG_FIELD_NR = 4
 518 };
 519
 520 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 521 {
 522         return container_of(vcpu, struct vcpu_vmx, vcpu);
 523 }
 524
 525 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 526 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 527 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 528                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 529
 530
 531 static unsigned long shadow_read_only_fields[] = {
 532         /*
 533          * We do NOT shadow fields that are modified when L0
 534          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 535          * VMXON...) executed by L1.
 536          * For example, VM_INSTRUCTION_ERROR is read
 537          * by L1 if a vmx instruction fails (part of the error path).
 538          * Note the code assumes this logic. If for some reason
 539          * we start shadowing these fields then we need to
 540          * force a shadow sync when L0 emulates vmx instructions
 541          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 542          * by nested_vmx_failValid)
 543          */
 544         VM_EXIT_REASON,
 545         VM_EXIT_INTR_INFO,
 546         VM_EXIT_INSTRUCTION_LEN,
 547         IDT_VECTORING_INFO_FIELD,
 548         IDT_VECTORING_ERROR_CODE,
 549         VM_EXIT_INTR_ERROR_CODE,
 550         EXIT_QUALIFICATION,
 551         GUEST_LINEAR_ADDRESS,
 552         GUEST_PHYSICAL_ADDRESS
 553 };
 554 static int max_shadow_read_only_fields =
 555         ARRAY_SIZE(shadow_read_only_fields);
 556
 557 static unsigned long shadow_read_write_fields[] = {
 558         GUEST_RIP,
 559         GUEST_RSP,
 560         GUEST_CR0,
 561         GUEST_CR3,
 562         GUEST_CR4,
 563         GUEST_INTERRUPTIBILITY_INFO,
 564         GUEST_RFLAGS,
 565         GUEST_CS_SELECTOR,
 566         GUEST_CS_AR_BYTES,
 567         GUEST_CS_LIMIT,
 568         GUEST_CS_BASE,
 569         GUEST_ES_BASE,
 570         GUEST_BNDCFGS,
 571         CR0_GUEST_HOST_MASK,
 572         CR0_READ_SHADOW,
 573         CR4_READ_SHADOW,
 574         TSC_OFFSET,
 575         EXCEPTION_BITMAP,
 576         CPU_BASED_VM_EXEC_CONTROL,
 577         VM_ENTRY_EXCEPTION_ERROR_CODE,
 578         VM_ENTRY_INTR_INFO_FIELD,
 579         VM_ENTRY_INSTRUCTION_LEN,
 580         VM_ENTRY_EXCEPTION_ERROR_CODE,
 581         HOST_FS_BASE,
 582         HOST_GS_BASE,
 583         HOST_FS_SELECTOR,
 584         HOST_GS_SELECTOR
 585 };
 586 static int max_shadow_read_write_fields =
 587         ARRAY_SIZE(shadow_read_write_fields);
 588
 589 static const unsigned short vmcs_field_to_offset_table[] = {
 590         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 591         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 592         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 593         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 594         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 595         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 596         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 597         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 598         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 599         FIELD(HOST_ES_SELECTOR, host_es_selector),
 600         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 601         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 602         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 603         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 604         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 605         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 606         FIELD64(IO_BITMAP_A, io_bitmap_a),
 607         FIELD64(IO_BITMAP_B, io_bitmap_b),
 608         FIELD64(MSR_BITMAP, msr_bitmap),
 609         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 610         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 611         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 612         FIELD64(TSC_OFFSET, tsc_offset),
 613         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 614         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 615         FIELD64(EPT_POINTER, ept_pointer),
 616         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 617         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 618         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 619         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 620         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 621         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 622         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 623         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 624         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 625         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 626         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 627         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 628         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 629         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 630         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 631         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 632         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 633         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 634         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 635         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 636         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 637         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 638         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 639         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 640         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 641         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 642         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 643         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 644         FIELD(TPR_THRESHOLD, tpr_threshold),
 645         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 646         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 647         FIELD(VM_EXIT_REASON, vm_exit_reason),
 648         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 649         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 650         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 651         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 652         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 653         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 654         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 655         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 656         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 657         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 658         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 659         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 660         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 661         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 662         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 663         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 664         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 665         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 666         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 667         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 668         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 669         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 670         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 671         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 672         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 673         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 674         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 675         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 676         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 677         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 678         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 679         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 680         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 681         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 682         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 683         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 684         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 685         FIELD(EXIT_QUALIFICATION, exit_qualification),
 686         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 687         FIELD(GUEST_CR0, guest_cr0),
 688         FIELD(GUEST_CR3, guest_cr3),
 689         FIELD(GUEST_CR4, guest_cr4),
 690         FIELD(GUEST_ES_BASE, guest_es_base),
 691         FIELD(GUEST_CS_BASE, guest_cs_base),
 692         FIELD(GUEST_SS_BASE, guest_ss_base),
 693         FIELD(GUEST_DS_BASE, guest_ds_base),
 694         FIELD(GUEST_FS_BASE, guest_fs_base),
 695         FIELD(GUEST_GS_BASE, guest_gs_base),
 696         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 697         FIELD(GUEST_TR_BASE, guest_tr_base),
 698         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 699         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 700         FIELD(GUEST_DR7, guest_dr7),
 701         FIELD(GUEST_RSP, guest_rsp),
 702         FIELD(GUEST_RIP, guest_rip),
 703         FIELD(GUEST_RFLAGS, guest_rflags),
 704         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 705         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 706         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 707         FIELD(HOST_CR0, host_cr0),
 708         FIELD(HOST_CR3, host_cr3),
 709         FIELD(HOST_CR4, host_cr4),
 710         FIELD(HOST_FS_BASE, host_fs_base),
 711         FIELD(HOST_GS_BASE, host_gs_base),
 712         FIELD(HOST_TR_BASE, host_tr_base),
 713         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 714         FIELD(HOST_IDTR_BASE, host_idtr_base),
 715         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 716         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 717         FIELD(HOST_RSP, host_rsp),
 718         FIELD(HOST_RIP, host_rip),
 719 };
 720 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 721
 722 static inline short vmcs_field_to_offset(unsigned long field)
 723 {
 724         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 725                 return -1;
 726         return vmcs_field_to_offset_table[field];
 727 }
 728
 729 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 730 {
 731         return to_vmx(vcpu)->nested.current_vmcs12;
 732 }
 733
 734 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 735 {
 736         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 737         if (is_error_page(page))
 738                 return NULL;
 739
 740         return page;
 741 }
 742
 743 static void nested_release_page(struct page *page)
 744 {
 745         kvm_release_page_dirty(page);
 746 }
 747
 748 static void nested_release_page_clean(struct page *page)
 749 {
 750         kvm_release_page_clean(page);
 751 }
 752
 753 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 754 static u64 construct_eptp(unsigned long root_hpa);
 755 static void kvm_cpu_vmxon(u64 addr);
 756 static void kvm_cpu_vmxoff(void);
 757 static bool vmx_mpx_supported(void);
 758 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 759 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 760                             struct kvm_segment *var, int seg);
 761 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 762                             struct kvm_segment *var, int seg);
 763 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 764 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 765 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 766 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 767 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 768
 769 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 770 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 771 /*
 772  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 773  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 774  */
 775 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 776 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 777
 778 static unsigned long *vmx_io_bitmap_a;
 779 static unsigned long *vmx_io_bitmap_b;
 780 static unsigned long *vmx_msr_bitmap_legacy;
 781 static unsigned long *vmx_msr_bitmap_longmode;
 782 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 783 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 784 static unsigned long *vmx_vmread_bitmap;
 785 static unsigned long *vmx_vmwrite_bitmap;
 786
 787 static bool cpu_has_load_ia32_efer;
 788 static bool cpu_has_load_perf_global_ctrl;
 789
 790 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 791 static DEFINE_SPINLOCK(vmx_vpid_lock);
 792
 793 static struct vmcs_config {
 794         int size;
 795         int order;
 796         u32 revision_id;
 797         u32 pin_based_exec_ctrl;
 798         u32 cpu_based_exec_ctrl;
 799         u32 cpu_based_2nd_exec_ctrl;
 800         u32 vmexit_ctrl;
 801         u32 vmentry_ctrl;
 802 } vmcs_config;
 803
 804 static struct vmx_capability {
 805         u32 ept;
 806         u32 vpid;
 807 } vmx_capability;
 808
 809 #define VMX_SEGMENT_FIELD(seg)                                  \
 810         [VCPU_SREG_##seg] = {                                   \
 811                 .selector = GUEST_##seg##_SELECTOR,             \
 812                 .base = GUEST_##seg##_BASE,                     \
 813                 .limit = GUEST_##seg##_LIMIT,                   \
 814                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 815         }
 816
 817 static const struct kvm_vmx_segment_field {
 818         unsigned selector;
 819         unsigned base;
 820         unsigned limit;
 821         unsigned ar_bytes;
 822 } kvm_vmx_segment_fields[] = {
 823         VMX_SEGMENT_FIELD(CS),
 824         VMX_SEGMENT_FIELD(DS),
 825         VMX_SEGMENT_FIELD(ES),
 826         VMX_SEGMENT_FIELD(FS),
 827         VMX_SEGMENT_FIELD(GS),
 828         VMX_SEGMENT_FIELD(SS),
 829         VMX_SEGMENT_FIELD(TR),
 830         VMX_SEGMENT_FIELD(LDTR),
 831 };
 832
 833 static u64 host_efer;
 834
 835 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 836
 837 /*
 838  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 839  * away by decrementing the array size.
 840  */
 841 static const u32 vmx_msr_index[] = {
 842 #ifdef CONFIG_X86_64
 843         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 844 #endif
 845         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 846 };
 847
 848 static inline bool is_page_fault(u32 intr_info)
 849 {
 850         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 851                              INTR_INFO_VALID_MASK)) ==
 852                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 853 }
 854
 855 static inline bool is_no_device(u32 intr_info)
 856 {
 857         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 858                              INTR_INFO_VALID_MASK)) ==
 859                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 860 }
 861
 862 static inline bool is_invalid_opcode(u32 intr_info)
 863 {
 864         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 865                              INTR_INFO_VALID_MASK)) ==
 866                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 867 }
 868
 869 static inline bool is_external_interrupt(u32 intr_info)
 870 {
 871         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 872                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 873 }
 874
 875 static inline bool is_machine_check(u32 intr_info)
 876 {
 877         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 878                              INTR_INFO_VALID_MASK)) ==
 879                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 880 }
 881
 882 static inline bool cpu_has_vmx_msr_bitmap(void)
 883 {
 884         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 885 }
 886
 887 static inline bool cpu_has_vmx_tpr_shadow(void)
 888 {
 889         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 890 }
 891
 892 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 893 {
 894         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 895 }
 896
 897 static inline bool cpu_has_secondary_exec_ctrls(void)
 898 {
 899         return vmcs_config.cpu_based_exec_ctrl &
 900                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 901 }
 902
 903 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 904 {
 905         return vmcs_config.cpu_based_2nd_exec_ctrl &
 906                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 907 }
 908
 909 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 910 {
 911         return vmcs_config.cpu_based_2nd_exec_ctrl &
 912                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 913 }
 914
 915 static inline bool cpu_has_vmx_apic_register_virt(void)
 916 {
 917         return vmcs_config.cpu_based_2nd_exec_ctrl &
 918                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 919 }
 920
 921 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 922 {
 923         return vmcs_config.cpu_based_2nd_exec_ctrl &
 924                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 925 }
 926
 927 static inline bool cpu_has_vmx_posted_intr(void)
 928 {
 929         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
 930 }
 931
 932 static inline bool cpu_has_vmx_apicv(void)
 933 {
 934         return cpu_has_vmx_apic_register_virt() &&
 935                 cpu_has_vmx_virtual_intr_delivery() &&
 936                 cpu_has_vmx_posted_intr();
 937 }
 938
 939 static inline bool cpu_has_vmx_flexpriority(void)
 940 {
 941         return cpu_has_vmx_tpr_shadow() &&
 942                 cpu_has_vmx_virtualize_apic_accesses();
 943 }
 944
 945 static inline bool cpu_has_vmx_ept_execute_only(void)
 946 {
 947         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 948 }
 949
 950 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 951 {
 952         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 953 }
 954
 955 static inline bool cpu_has_vmx_eptp_writeback(void)
 956 {
 957         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 958 }
 959
 960 static inline bool cpu_has_vmx_ept_2m_page(void)
 961 {
 962         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 963 }
 964
 965 static inline bool cpu_has_vmx_ept_1g_page(void)
 966 {
 967         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 968 }
 969
 970 static inline bool cpu_has_vmx_ept_4levels(void)
 971 {
 972         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 973 }
 974
 975 static inline bool cpu_has_vmx_ept_ad_bits(void)
 976 {
 977         return vmx_capability.ept & VMX_EPT_AD_BIT;
 978 }
 979
 980 static inline bool cpu_has_vmx_invept_context(void)
 981 {
 982         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 983 }
 984
 985 static inline bool cpu_has_vmx_invept_global(void)
 986 {
 987         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 988 }
 989
 990 static inline bool cpu_has_vmx_invvpid_single(void)
 991 {
 992         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 993 }
 994
 995 static inline bool cpu_has_vmx_invvpid_global(void)
 996 {
 997         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 998 }
 999
1000 static inline bool cpu_has_vmx_ept(void)
1001 {
1002         return vmcs_config.cpu_based_2nd_exec_ctrl &
1003                 SECONDARY_EXEC_ENABLE_EPT;
1004 }
1005
1006 static inline bool cpu_has_vmx_unrestricted_guest(void)
1007 {
1008         return vmcs_config.cpu_based_2nd_exec_ctrl &
1009                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1010 }
1011
1012 static inline bool cpu_has_vmx_ple(void)
1013 {
1014         return vmcs_config.cpu_based_2nd_exec_ctrl &
1015                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1016 }
1017
1018 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
1019 {
1020         return flexpriority_enabled && irqchip_in_kernel(kvm);
1021 }
1022
1023 static inline bool cpu_has_vmx_vpid(void)
1024 {
1025         return vmcs_config.cpu_based_2nd_exec_ctrl &
1026                 SECONDARY_EXEC_ENABLE_VPID;
1027 }
1028
1029 static inline bool cpu_has_vmx_rdtscp(void)
1030 {
1031         return vmcs_config.cpu_based_2nd_exec_ctrl &
1032                 SECONDARY_EXEC_RDTSCP;
1033 }
1034
1035 static inline bool cpu_has_vmx_invpcid(void)
1036 {
1037         return vmcs_config.cpu_based_2nd_exec_ctrl &
1038                 SECONDARY_EXEC_ENABLE_INVPCID;
1039 }
1040
1041 static inline bool cpu_has_virtual_nmis(void)
1042 {
1043         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1044 }
1045
1046 static inline bool cpu_has_vmx_wbinvd_exit(void)
1047 {
1048         return vmcs_config.cpu_based_2nd_exec_ctrl &
1049                 SECONDARY_EXEC_WBINVD_EXITING;
1050 }
1051
1052 static inline bool cpu_has_vmx_shadow_vmcs(void)
1053 {
1054         u64 vmx_msr;
1055         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1056         /* check if the cpu supports writing r/o exit information fields */
1057         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1058                 return false;
1059
1060         return vmcs_config.cpu_based_2nd_exec_ctrl &
1061                 SECONDARY_EXEC_SHADOW_VMCS;
1062 }
1063
1064 static inline bool report_flexpriority(void)
1065 {
1066         return flexpriority_enabled;
1067 }
1068
1069 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1070 {
1071         return vmcs12->cpu_based_vm_exec_control & bit;
1072 }
1073
1074 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1075 {
1076         return (vmcs12->cpu_based_vm_exec_control &
1077                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1078                 (vmcs12->secondary_vm_exec_control & bit);
1079 }
1080
1081 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1082 {
1083         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1084 }
1085
1086 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1087 {
1088         return vmcs12->pin_based_vm_exec_control &
1089                 PIN_BASED_VMX_PREEMPTION_TIMER;
1090 }
1091
1092 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1093 {
1094         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1095 }
1096
1097 static inline bool is_exception(u32 intr_info)
1098 {
1099         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1100                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1101 }
1102
1103 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1104                               u32 exit_intr_info,
1105                               unsigned long exit_qualification);
1106 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1107                         struct vmcs12 *vmcs12,
1108                         u32 reason, unsigned long qualification);
1109
1110 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1111 {
1112         int i;
1113
1114         for (i = 0; i < vmx->nmsrs; ++i)
1115                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1116                         return i;
1117         return -1;
1118 }
1119
1120 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1121 {
1122     struct {
1123         u64 vpid : 16;
1124         u64 rsvd : 48;
1125         u64 gva;
1126     } operand = { vpid, 0, gva };
1127
1128     asm volatile (__ex(ASM_VMX_INVVPID)
1129                   /* CF==1 or ZF==1 --> rc = -1 */
1130                   "; ja 1f ; ud2 ; 1:"
1131                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1132 }
1133
1134 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1135 {
1136         struct {
1137                 u64 eptp, gpa;
1138         } operand = {eptp, gpa};
1139
1140         asm volatile (__ex(ASM_VMX_INVEPT)
1141                         /* CF==1 or ZF==1 --> rc = -1 */
1142                         "; ja 1f ; ud2 ; 1:\n"
1143                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1144 }
1145
1146 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1147 {
1148         int i;
1149
1150         i = __find_msr_index(vmx, msr);
1151         if (i >= 0)
1152                 return &vmx->guest_msrs[i];
1153         return NULL;
1154 }
1155
1156 static void vmcs_clear(struct vmcs *vmcs)
1157 {
1158         u64 phys_addr = __pa(vmcs);
1159         u8 error;
1160
1161         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1162                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1163                       : "cc", "memory");
1164         if (error)
1165                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1166                        vmcs, phys_addr);
1167 }
1168
1169 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1170 {
1171         vmcs_clear(loaded_vmcs->vmcs);
1172         loaded_vmcs->cpu = -1;
1173         loaded_vmcs->launched = 0;
1174 }
1175
1176 static void vmcs_load(struct vmcs *vmcs)
1177 {
1178         u64 phys_addr = __pa(vmcs);
1179         u8 error;
1180
1181         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1182                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1183                         : "cc", "memory");
1184         if (error)
1185                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1186                        vmcs, phys_addr);
1187 }
1188
1189 #ifdef CONFIG_KEXEC
1190 /*
1191  * This bitmap is used to indicate whether the vmclear
1192  * operation is enabled on all cpus. All disabled by
1193  * default.
1194  */
1195 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1196
1197 static inline void crash_enable_local_vmclear(int cpu)
1198 {
1199         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1200 }
1201
1202 static inline void crash_disable_local_vmclear(int cpu)
1203 {
1204         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1205 }
1206
1207 static inline int crash_local_vmclear_enabled(int cpu)
1208 {
1209         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1210 }
1211
1212 static void crash_vmclear_local_loaded_vmcss(void)
1213 {
1214         int cpu = raw_smp_processor_id();
1215         struct loaded_vmcs *v;
1216
1217         if (!crash_local_vmclear_enabled(cpu))
1218                 return;
1219
1220         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1221                             loaded_vmcss_on_cpu_link)
1222                 vmcs_clear(v->vmcs);
1223 }
1224 #else
1225 static inline void crash_enable_local_vmclear(int cpu) { }
1226 static inline void crash_disable_local_vmclear(int cpu) { }
1227 #endif /* CONFIG_KEXEC */
1228
1229 static void __loaded_vmcs_clear(void *arg)
1230 {
1231         struct loaded_vmcs *loaded_vmcs = arg;
1232         int cpu = raw_smp_processor_id();
1233
1234         if (loaded_vmcs->cpu != cpu)
1235                 return; /* vcpu migration can race with cpu offline */
1236         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1237                 per_cpu(current_vmcs, cpu) = NULL;
1238         crash_disable_local_vmclear(cpu);
1239         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1240
1241         /*
1242          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1243          * is before setting loaded_vmcs->vcpu to -1 which is done in
1244          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1245          * then adds the vmcs into percpu list before it is deleted.
1246          */
1247         smp_wmb();
1248
1249         loaded_vmcs_init(loaded_vmcs);
1250         crash_enable_local_vmclear(cpu);
1251 }
1252
1253 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1254 {
1255         int cpu = loaded_vmcs->cpu;
1256
1257         if (cpu != -1)
1258                 smp_call_function_single(cpu,
1259                          __loaded_vmcs_clear, loaded_vmcs, 1);
1260 }
1261
1262 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1263 {
1264         if (vmx->vpid == 0)
1265                 return;
1266
1267         if (cpu_has_vmx_invvpid_single())
1268                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1269 }
1270
1271 static inline void vpid_sync_vcpu_global(void)
1272 {
1273         if (cpu_has_vmx_invvpid_global())
1274                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1275 }
1276
1277 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1278 {
1279         if (cpu_has_vmx_invvpid_single())
1280                 vpid_sync_vcpu_single(vmx);
1281         else
1282                 vpid_sync_vcpu_global();
1283 }
1284
1285 static inline void ept_sync_global(void)
1286 {
1287         if (cpu_has_vmx_invept_global())
1288                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1289 }
1290
1291 static inline void ept_sync_context(u64 eptp)
1292 {
1293         if (enable_ept) {
1294                 if (cpu_has_vmx_invept_context())
1295                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1296                 else
1297                         ept_sync_global();
1298         }
1299 }
1300
1301 static __always_inline unsigned long vmcs_readl(unsigned long field)
1302 {
1303         unsigned long value;
1304
1305         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1306                       : "=a"(value) : "d"(field) : "cc");
1307         return value;
1308 }
1309
1310 static __always_inline u16 vmcs_read16(unsigned long field)
1311 {
1312         return vmcs_readl(field);
1313 }
1314
1315 static __always_inline u32 vmcs_read32(unsigned long field)
1316 {
1317         return vmcs_readl(field);
1318 }
1319
1320 static __always_inline u64 vmcs_read64(unsigned long field)
1321 {
1322 #ifdef CONFIG_X86_64
1323         return vmcs_readl(field);
1324 #else
1325         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1326 #endif
1327 }
1328
1329 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1330 {
1331         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1332                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1333         dump_stack();
1334 }
1335
1336 static void vmcs_writel(unsigned long field, unsigned long value)
1337 {
1338         u8 error;
1339
1340         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1341                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1342         if (unlikely(error))
1343                 vmwrite_error(field, value);
1344 }
1345
1346 static void vmcs_write16(unsigned long field, u16 value)
1347 {
1348         vmcs_writel(field, value);
1349 }
1350
1351 static void vmcs_write32(unsigned long field, u32 value)
1352 {
1353         vmcs_writel(field, value);
1354 }
1355
1356 static void vmcs_write64(unsigned long field, u64 value)
1357 {
1358         vmcs_writel(field, value);
1359 #ifndef CONFIG_X86_64
1360         asm volatile ("");
1361         vmcs_writel(field+1, value >> 32);
1362 #endif
1363 }
1364
1365 static void vmcs_clear_bits(unsigned long field, u32 mask)
1366 {
1367         vmcs_writel(field, vmcs_readl(field) & ~mask);
1368 }
1369
1370 static void vmcs_set_bits(unsigned long field, u32 mask)
1371 {
1372         vmcs_writel(field, vmcs_readl(field) | mask);
1373 }
1374
1375 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1376 {
1377         vmcs_write32(VM_ENTRY_CONTROLS, val);
1378         vmx->vm_entry_controls_shadow = val;
1379 }
1380
1381 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1382 {
1383         if (vmx->vm_entry_controls_shadow != val)
1384                 vm_entry_controls_init(vmx, val);
1385 }
1386
1387 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1388 {
1389         return vmx->vm_entry_controls_shadow;
1390 }
1391
1392
1393 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1394 {
1395         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1396 }
1397
1398 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1399 {
1400         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1401 }
1402
1403 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1404 {
1405         vmcs_write32(VM_EXIT_CONTROLS, val);
1406         vmx->vm_exit_controls_shadow = val;
1407 }
1408
1409 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1410 {
1411         if (vmx->vm_exit_controls_shadow != val)
1412                 vm_exit_controls_init(vmx, val);
1413 }
1414
1415 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1416 {
1417         return vmx->vm_exit_controls_shadow;
1418 }
1419
1420
1421 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1422 {
1423         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1424 }
1425
1426 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1427 {
1428         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1429 }
1430
1431 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1432 {
1433         vmx->segment_cache.bitmask = 0;
1434 }
1435
1436 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1437                                        unsigned field)
1438 {
1439         bool ret;
1440         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1441
1442         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1443                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1444                 vmx->segment_cache.bitmask = 0;
1445         }
1446         ret = vmx->segment_cache.bitmask & mask;
1447         vmx->segment_cache.bitmask |= mask;
1448         return ret;
1449 }
1450
1451 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1452 {
1453         u16 *p = &vmx->segment_cache.seg[seg].selector;
1454
1455         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1456                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1457         return *p;
1458 }
1459
1460 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1461 {
1462         ulong *p = &vmx->segment_cache.seg[seg].base;
1463
1464         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1465                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1466         return *p;
1467 }
1468
1469 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1470 {
1471         u32 *p = &vmx->segment_cache.seg[seg].limit;
1472
1473         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1474                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1475         return *p;
1476 }
1477
1478 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1479 {
1480         u32 *p = &vmx->segment_cache.seg[seg].ar;
1481
1482         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1483                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1484         return *p;
1485 }
1486
1487 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1488 {
1489         u32 eb;
1490
1491         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1492              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1493         if ((vcpu->guest_debug &
1494              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1495             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1496                 eb |= 1u << BP_VECTOR;
1497         if (to_vmx(vcpu)->rmode.vm86_active)
1498                 eb = ~0;
1499         if (enable_ept)
1500                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1501         if (vcpu->fpu_active)
1502                 eb &= ~(1u << NM_VECTOR);
1503
1504         /* When we are running a nested L2 guest and L1 specified for it a
1505          * certain exception bitmap, we must trap the same exceptions and pass
1506          * them to L1. When running L2, we will only handle the exceptions
1507          * specified above if L1 did not want them.
1508          */
1509         if (is_guest_mode(vcpu))
1510                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1511
1512         vmcs_write32(EXCEPTION_BITMAP, eb);
1513 }
1514
1515 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1516                 unsigned long entry, unsigned long exit)
1517 {
1518         vm_entry_controls_clearbit(vmx, entry);
1519         vm_exit_controls_clearbit(vmx, exit);
1520 }
1521
1522 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1523 {
1524         unsigned i;
1525         struct msr_autoload *m = &vmx->msr_autoload;
1526
1527         switch (msr) {
1528         case MSR_EFER:
1529                 if (cpu_has_load_ia32_efer) {
1530                         clear_atomic_switch_msr_special(vmx,
1531                                         VM_ENTRY_LOAD_IA32_EFER,
1532                                         VM_EXIT_LOAD_IA32_EFER);
1533                         return;
1534                 }
1535                 break;
1536         case MSR_CORE_PERF_GLOBAL_CTRL:
1537                 if (cpu_has_load_perf_global_ctrl) {
1538                         clear_atomic_switch_msr_special(vmx,
1539                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1540                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1541                         return;
1542                 }
1543                 break;
1544         }
1545
1546         for (i = 0; i < m->nr; ++i)
1547                 if (m->guest[i].index == msr)
1548                         break;
1549
1550         if (i == m->nr)
1551                 return;
1552         --m->nr;
1553         m->guest[i] = m->guest[m->nr];
1554         m->host[i] = m->host[m->nr];
1555         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1556         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1557 }
1558
1559 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1560                 unsigned long entry, unsigned long exit,
1561                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1562                 u64 guest_val, u64 host_val)
1563 {
1564         vmcs_write64(guest_val_vmcs, guest_val);
1565         vmcs_write64(host_val_vmcs, host_val);
1566         vm_entry_controls_setbit(vmx, entry);
1567         vm_exit_controls_setbit(vmx, exit);
1568 }
1569
1570 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1571                                   u64 guest_val, u64 host_val)
1572 {
1573         unsigned i;
1574         struct msr_autoload *m = &vmx->msr_autoload;
1575
1576         switch (msr) {
1577         case MSR_EFER:
1578                 if (cpu_has_load_ia32_efer) {
1579                         add_atomic_switch_msr_special(vmx,
1580                                         VM_ENTRY_LOAD_IA32_EFER,
1581                                         VM_EXIT_LOAD_IA32_EFER,
1582                                         GUEST_IA32_EFER,
1583                                         HOST_IA32_EFER,
1584                                         guest_val, host_val);
1585                         return;
1586                 }
1587                 break;
1588         case MSR_CORE_PERF_GLOBAL_CTRL:
1589                 if (cpu_has_load_perf_global_ctrl) {
1590                         add_atomic_switch_msr_special(vmx,
1591                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1592                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1593                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1594                                         HOST_IA32_PERF_GLOBAL_CTRL,
1595                                         guest_val, host_val);
1596                         return;
1597                 }
1598                 break;
1599         }
1600
1601         for (i = 0; i < m->nr; ++i)
1602                 if (m->guest[i].index == msr)
1603                         break;
1604
1605         if (i == NR_AUTOLOAD_MSRS) {
1606                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1607                                 "Can't add msr %x\n", msr);
1608                 return;
1609         } else if (i == m->nr) {
1610                 ++m->nr;
1611                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1612                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1613         }
1614
1615         m->guest[i].index = msr;
1616         m->guest[i].value = guest_val;
1617         m->host[i].index = msr;
1618         m->host[i].value = host_val;
1619 }
1620
1621 static void reload_tss(void)
1622 {
1623         /*
1624          * VT restores TR but not its size.  Useless.
1625          */
1626         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1627         struct desc_struct *descs;
1628
1629         descs = (void *)gdt->address;
1630         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1631         load_TR_desc();
1632 }
1633
1634 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1635 {
1636         u64 guest_efer;
1637         u64 ignore_bits;
1638
1639         guest_efer = vmx->vcpu.arch.efer;
1640
1641         /*
1642          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1643          * outside long mode
1644          */
1645         ignore_bits = EFER_NX | EFER_SCE;
1646 #ifdef CONFIG_X86_64
1647         ignore_bits |= EFER_LMA | EFER_LME;
1648         /* SCE is meaningful only in long mode on Intel */
1649         if (guest_efer & EFER_LMA)
1650                 ignore_bits &= ~(u64)EFER_SCE;
1651 #endif
1652         guest_efer &= ~ignore_bits;
1653         guest_efer |= host_efer & ignore_bits;
1654         vmx->guest_msrs[efer_offset].data = guest_efer;
1655         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1656
1657         clear_atomic_switch_msr(vmx, MSR_EFER);
1658         /* On ept, can't emulate nx, and must switch nx atomically */
1659         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1660                 guest_efer = vmx->vcpu.arch.efer;
1661                 if (!(guest_efer & EFER_LMA))
1662                         guest_efer &= ~EFER_LME;
1663                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1664                 return false;
1665         }
1666
1667         return true;
1668 }
1669
1670 static unsigned long segment_base(u16 selector)
1671 {
1672         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1673         struct desc_struct *d;
1674         unsigned long table_base;
1675         unsigned long v;
1676
1677         if (!(selector & ~3))
1678                 return 0;
1679
1680         table_base = gdt->address;
1681
1682         if (selector & 4) {           /* from ldt */
1683                 u16 ldt_selector = kvm_read_ldt();
1684
1685                 if (!(ldt_selector & ~3))
1686                         return 0;
1687
1688                 table_base = segment_base(ldt_selector);
1689         }
1690         d = (struct desc_struct *)(table_base + (selector & ~7));
1691         v = get_desc_base(d);
1692 #ifdef CONFIG_X86_64
1693        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1694                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1695 #endif
1696         return v;
1697 }
1698
1699 static inline unsigned long kvm_read_tr_base(void)
1700 {
1701         u16 tr;
1702         asm("str %0" : "=g"(tr));
1703         return segment_base(tr);
1704 }
1705
1706 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1707 {
1708         struct vcpu_vmx *vmx = to_vmx(vcpu);
1709         int i;
1710
1711         if (vmx->host_state.loaded)
1712                 return;
1713
1714         vmx->host_state.loaded = 1;
1715         /*
1716          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1717          * allow segment selectors with cpl > 0 or ti == 1.
1718          */
1719         vmx->host_state.ldt_sel = kvm_read_ldt();
1720         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1721         savesegment(fs, vmx->host_state.fs_sel);
1722         if (!(vmx->host_state.fs_sel & 7)) {
1723                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1724                 vmx->host_state.fs_reload_needed = 0;
1725         } else {
1726                 vmcs_write16(HOST_FS_SELECTOR, 0);
1727                 vmx->host_state.fs_reload_needed = 1;
1728         }
1729         savesegment(gs, vmx->host_state.gs_sel);
1730         if (!(vmx->host_state.gs_sel & 7))
1731                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1732         else {
1733                 vmcs_write16(HOST_GS_SELECTOR, 0);
1734                 vmx->host_state.gs_ldt_reload_needed = 1;
1735         }
1736
1737 #ifdef CONFIG_X86_64
1738         savesegment(ds, vmx->host_state.ds_sel);
1739         savesegment(es, vmx->host_state.es_sel);
1740 #endif
1741
1742 #ifdef CONFIG_X86_64
1743         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1744         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1745 #else
1746         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1747         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1748 #endif
1749
1750 #ifdef CONFIG_X86_64
1751         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1752         if (is_long_mode(&vmx->vcpu))
1753                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1754 #endif
1755         if (boot_cpu_has(X86_FEATURE_MPX))
1756                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1757         for (i = 0; i < vmx->save_nmsrs; ++i)
1758                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1759                                    vmx->guest_msrs[i].data,
1760                                    vmx->guest_msrs[i].mask);
1761 }
1762
1763 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1764 {
1765         if (!vmx->host_state.loaded)
1766                 return;
1767
1768         ++vmx->vcpu.stat.host_state_reload;
1769         vmx->host_state.loaded = 0;
1770 #ifdef CONFIG_X86_64
1771         if (is_long_mode(&vmx->vcpu))
1772                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1773 #endif
1774         if (vmx->host_state.gs_ldt_reload_needed) {
1775                 kvm_load_ldt(vmx->host_state.ldt_sel);
1776 #ifdef CONFIG_X86_64
1777                 load_gs_index(vmx->host_state.gs_sel);
1778 #else
1779                 loadsegment(gs, vmx->host_state.gs_sel);
1780 #endif
1781         }
1782         if (vmx->host_state.fs_reload_needed)
1783                 loadsegment(fs, vmx->host_state.fs_sel);
1784 #ifdef CONFIG_X86_64
1785         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1786                 loadsegment(ds, vmx->host_state.ds_sel);
1787                 loadsegment(es, vmx->host_state.es_sel);
1788         }
1789 #endif
1790         reload_tss();
1791 #ifdef CONFIG_X86_64
1792         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1793 #endif
1794         if (vmx->host_state.msr_host_bndcfgs)
1795                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1796         /*
1797          * If the FPU is not active (through the host task or
1798          * the guest vcpu), then restore the cr0.TS bit.
1799          */
1800         if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1801                 stts();
1802         load_gdt(&__get_cpu_var(host_gdt));
1803 }
1804
1805 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1806 {
1807         preempt_disable();
1808         __vmx_load_host_state(vmx);
1809         preempt_enable();
1810 }
1811
1812 /*
1813  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1814  * vcpu mutex is already taken.
1815  */
1816 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1817 {
1818         struct vcpu_vmx *vmx = to_vmx(vcpu);
1819         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1820
1821         if (!vmm_exclusive)
1822                 kvm_cpu_vmxon(phys_addr);
1823         else if (vmx->loaded_vmcs->cpu != cpu)
1824                 loaded_vmcs_clear(vmx->loaded_vmcs);
1825
1826         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1827                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1828                 vmcs_load(vmx->loaded_vmcs->vmcs);
1829         }
1830
1831         if (vmx->loaded_vmcs->cpu != cpu) {
1832                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1833                 unsigned long sysenter_esp;
1834
1835                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1836                 local_irq_disable();
1837                 crash_disable_local_vmclear(cpu);
1838
1839                 /*
1840                  * Read loaded_vmcs->cpu should be before fetching
1841                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
1842                  * See the comments in __loaded_vmcs_clear().
1843                  */
1844                 smp_rmb();
1845
1846                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1847                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1848                 crash_enable_local_vmclear(cpu);
1849                 local_irq_enable();
1850
1851                 /*
1852                  * Linux uses per-cpu TSS and GDT, so set these when switching
1853                  * processors.
1854                  */
1855                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1856                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1857
1858                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1859                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1860                 vmx->loaded_vmcs->cpu = cpu;
1861         }
1862 }
1863
1864 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1865 {
1866         __vmx_load_host_state(to_vmx(vcpu));
1867         if (!vmm_exclusive) {
1868                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1869                 vcpu->cpu = -1;
1870                 kvm_cpu_vmxoff();
1871         }
1872 }
1873
1874 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1875 {
1876         ulong cr0;
1877
1878         if (vcpu->fpu_active)
1879                 return;
1880         vcpu->fpu_active = 1;
1881         cr0 = vmcs_readl(GUEST_CR0);
1882         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1883         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1884         vmcs_writel(GUEST_CR0, cr0);
1885         update_exception_bitmap(vcpu);
1886         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1887         if (is_guest_mode(vcpu))
1888                 vcpu->arch.cr0_guest_owned_bits &=
1889                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1890         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1891 }
1892
1893 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1894
1895 /*
1896  * Return the cr0 value that a nested guest would read. This is a combination
1897  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1898  * its hypervisor (cr0_read_shadow).
1899  */
1900 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1901 {
1902         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1903                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1904 }
1905 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1906 {
1907         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1908                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1909 }
1910
1911 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1912 {
1913         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1914          * set this *before* calling this function.
1915          */
1916         vmx_decache_cr0_guest_bits(vcpu);
1917         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1918         update_exception_bitmap(vcpu);
1919         vcpu->arch.cr0_guest_owned_bits = 0;
1920         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1921         if (is_guest_mode(vcpu)) {
1922                 /*
1923                  * L1's specified read shadow might not contain the TS bit,
1924                  * so now that we turned on shadowing of this bit, we need to
1925                  * set this bit of the shadow. Like in nested_vmx_run we need
1926                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1927                  * up-to-date here because we just decached cr0.TS (and we'll
1928                  * only update vmcs12->guest_cr0 on nested exit).
1929                  */
1930                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1931                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1932                         (vcpu->arch.cr0 & X86_CR0_TS);
1933                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1934         } else
1935                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1936 }
1937
1938 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1939 {
1940         unsigned long rflags, save_rflags;
1941
1942         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1943                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1944                 rflags = vmcs_readl(GUEST_RFLAGS);
1945                 if (to_vmx(vcpu)->rmode.vm86_active) {
1946                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1947                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1948                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1949                 }
1950                 to_vmx(vcpu)->rflags = rflags;
1951         }
1952         return to_vmx(vcpu)->rflags;
1953 }
1954
1955 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1956 {
1957         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1958         to_vmx(vcpu)->rflags = rflags;
1959         if (to_vmx(vcpu)->rmode.vm86_active) {
1960                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1961                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1962         }
1963         vmcs_writel(GUEST_RFLAGS, rflags);
1964 }
1965
1966 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
1967 {
1968         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1969         int ret = 0;
1970
1971         if (interruptibility & GUEST_INTR_STATE_STI)
1972                 ret |= KVM_X86_SHADOW_INT_STI;
1973         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1974                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1975
1976         return ret;
1977 }
1978
1979 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1980 {
1981         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1982         u32 interruptibility = interruptibility_old;
1983
1984         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1985
1986         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1987                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1988         else if (mask & KVM_X86_SHADOW_INT_STI)
1989                 interruptibility |= GUEST_INTR_STATE_STI;
1990
1991         if ((interruptibility != interruptibility_old))
1992                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1993 }
1994
1995 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1996 {
1997         unsigned long rip;
1998
1999         rip = kvm_rip_read(vcpu);
2000         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2001         kvm_rip_write(vcpu, rip);
2002
2003         /* skipping an emulated instruction also counts */
2004         vmx_set_interrupt_shadow(vcpu, 0);
2005 }
2006
2007 /*
2008  * KVM wants to inject page-faults which it got to the guest. This function
2009  * checks whether in a nested guest, we need to inject them to L1 or L2.
2010  */
2011 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2012 {
2013         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2014
2015         if (!(vmcs12->exception_bitmap & (1u << nr)))
2016                 return 0;
2017
2018         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2019                           vmcs_read32(VM_EXIT_INTR_INFO),
2020                           vmcs_readl(EXIT_QUALIFICATION));
2021         return 1;
2022 }
2023
2024 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2025                                 bool has_error_code, u32 error_code,
2026                                 bool reinject)
2027 {
2028         struct vcpu_vmx *vmx = to_vmx(vcpu);
2029         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2030
2031         if (!reinject && is_guest_mode(vcpu) &&
2032             nested_vmx_check_exception(vcpu, nr))
2033                 return;
2034
2035         if (has_error_code) {
2036                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2037                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2038         }
2039
2040         if (vmx->rmode.vm86_active) {
2041                 int inc_eip = 0;
2042                 if (kvm_exception_is_soft(nr))
2043                         inc_eip = vcpu->arch.event_exit_inst_len;
2044                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2045                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2046                 return;
2047         }
2048
2049         if (kvm_exception_is_soft(nr)) {
2050                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2051                              vmx->vcpu.arch.event_exit_inst_len);
2052                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2053         } else
2054                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2055
2056         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2057 }
2058
2059 static bool vmx_rdtscp_supported(void)
2060 {
2061         return cpu_has_vmx_rdtscp();
2062 }
2063
2064 static bool vmx_invpcid_supported(void)
2065 {
2066         return cpu_has_vmx_invpcid() && enable_ept;
2067 }
2068
2069 /*
2070  * Swap MSR entry in host/guest MSR entry array.
2071  */
2072 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2073 {
2074         struct shared_msr_entry tmp;
2075
2076         tmp = vmx->guest_msrs[to];
2077         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2078         vmx->guest_msrs[from] = tmp;
2079 }
2080
2081 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2082 {
2083         unsigned long *msr_bitmap;
2084
2085         if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2086                 if (is_long_mode(vcpu))
2087                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2088                 else
2089                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2090         } else {
2091                 if (is_long_mode(vcpu))
2092                         msr_bitmap = vmx_msr_bitmap_longmode;
2093                 else
2094                         msr_bitmap = vmx_msr_bitmap_legacy;
2095         }
2096
2097         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2098 }
2099
2100 /*
2101  * Set up the vmcs to automatically save and restore system
2102  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2103  * mode, as fiddling with msrs is very expensive.
2104  */
2105 static void setup_msrs(struct vcpu_vmx *vmx)
2106 {
2107         int save_nmsrs, index;
2108
2109         save_nmsrs = 0;
2110 #ifdef CONFIG_X86_64
2111         if (is_long_mode(&vmx->vcpu)) {
2112                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2113                 if (index >= 0)
2114                         move_msr_up(vmx, index, save_nmsrs++);
2115                 index = __find_msr_index(vmx, MSR_LSTAR);
2116                 if (index >= 0)
2117                         move_msr_up(vmx, index, save_nmsrs++);
2118                 index = __find_msr_index(vmx, MSR_CSTAR);
2119                 if (index >= 0)
2120                         move_msr_up(vmx, index, save_nmsrs++);
2121                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2122                 if (index >= 0 && vmx->rdtscp_enabled)
2123                         move_msr_up(vmx, index, save_nmsrs++);
2124                 /*
2125                  * MSR_STAR is only needed on long mode guests, and only
2126                  * if efer.sce is enabled.
2127                  */
2128                 index = __find_msr_index(vmx, MSR_STAR);
2129                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2130                         move_msr_up(vmx, index, save_nmsrs++);
2131         }
2132 #endif
2133         index = __find_msr_index(vmx, MSR_EFER);
2134         if (index >= 0 && update_transition_efer(vmx, index))
2135                 move_msr_up(vmx, index, save_nmsrs++);
2136
2137         vmx->save_nmsrs = save_nmsrs;
2138
2139         if (cpu_has_vmx_msr_bitmap())
2140                 vmx_set_msr_bitmap(&vmx->vcpu);
2141 }
2142
2143 /*
2144  * reads and returns guest's timestamp counter "register"
2145  * guest_tsc = host_tsc + tsc_offset    -- 21.3
2146  */
2147 static u64 guest_read_tsc(void)
2148 {
2149         u64 host_tsc, tsc_offset;
2150
2151         rdtscll(host_tsc);
2152         tsc_offset = vmcs_read64(TSC_OFFSET);
2153         return host_tsc + tsc_offset;
2154 }
2155
2156 /*
2157  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2158  * counter, even if a nested guest (L2) is currently running.
2159  */
2160 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2161 {
2162         u64 tsc_offset;
2163
2164         tsc_offset = is_guest_mode(vcpu) ?
2165                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2166                 vmcs_read64(TSC_OFFSET);
2167         return host_tsc + tsc_offset;
2168 }
2169
2170 /*
2171  * Engage any workarounds for mis-matched TSC rates.  Currently limited to
2172  * software catchup for faster rates on slower CPUs.
2173  */
2174 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2175 {
2176         if (!scale)
2177                 return;
2178
2179         if (user_tsc_khz > tsc_khz) {
2180                 vcpu->arch.tsc_catchup = 1;
2181                 vcpu->arch.tsc_always_catchup = 1;
2182         } else
2183                 WARN(1, "user requested TSC rate below hardware speed\n");
2184 }
2185
2186 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2187 {
2188         return vmcs_read64(TSC_OFFSET);
2189 }
2190
2191 /*
2192  * writes 'offset' into guest's timestamp counter offset register
2193  */
2194 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2195 {
2196         if (is_guest_mode(vcpu)) {
2197                 /*
2198                  * We're here if L1 chose not to trap WRMSR to TSC. According
2199                  * to the spec, this should set L1's TSC; The offset that L1
2200                  * set for L2 remains unchanged, and still needs to be added
2201                  * to the newly set TSC to get L2's TSC.
2202                  */
2203                 struct vmcs12 *vmcs12;
2204                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2205                 /* recalculate vmcs02.TSC_OFFSET: */
2206                 vmcs12 = get_vmcs12(vcpu);
2207                 vmcs_write64(TSC_OFFSET, offset +
2208                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2209                          vmcs12->tsc_offset : 0));
2210         } else {
2211                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2212                                            vmcs_read64(TSC_OFFSET), offset);
2213                 vmcs_write64(TSC_OFFSET, offset);
2214         }
2215 }
2216
2217 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
2218 {
2219         u64 offset = vmcs_read64(TSC_OFFSET);
2220
2221         vmcs_write64(TSC_OFFSET, offset + adjustment);
2222         if (is_guest_mode(vcpu)) {
2223                 /* Even when running L2, the adjustment needs to apply to L1 */
2224                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2225         } else
2226                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2227                                            offset + adjustment);
2228 }
2229
2230 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2231 {
2232         return target_tsc - native_read_tsc();
2233 }
2234
2235 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2236 {
2237         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2238         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2239 }
2240
2241 /*
2242  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2243  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2244  * all guests if the "nested" module option is off, and can also be disabled
2245  * for a single guest by disabling its VMX cpuid bit.
2246  */
2247 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2248 {
2249         return nested && guest_cpuid_has_vmx(vcpu);
2250 }
2251
2252 /*
2253  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2254  * returned for the various VMX controls MSRs when nested VMX is enabled.
2255  * The same values should also be used to verify that vmcs12 control fields are
2256  * valid during nested entry from L1 to L2.
2257  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2258  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2259  * bit in the high half is on if the corresponding bit in the control field
2260  * may be on. See also vmx_control_verify().
2261  * TODO: allow these variables to be modified (downgraded) by module options
2262  * or other means.
2263  */
2264 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2265 static u32 nested_vmx_true_procbased_ctls_low;
2266 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2267 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2268 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2269 static u32 nested_vmx_true_exit_ctls_low;
2270 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2271 static u32 nested_vmx_true_entry_ctls_low;
2272 static u32 nested_vmx_misc_low, nested_vmx_misc_high;
2273 static u32 nested_vmx_ept_caps;
2274 static __init void nested_vmx_setup_ctls_msrs(void)
2275 {
2276         /*
2277          * Note that as a general rule, the high half of the MSRs (bits in
2278          * the control fields which may be 1) should be initialized by the
2279          * intersection of the underlying hardware's MSR (i.e., features which
2280          * can be supported) and the list of features we want to expose -
2281          * because they are known to be properly supported in our code.
2282          * Also, usually, the low half of the MSRs (bits which must be 1) can
2283          * be set to 0, meaning that L1 may turn off any of these bits. The
2284          * reason is that if one of these bits is necessary, it will appear
2285          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2286          * fields of vmcs01 and vmcs02, will turn these bits off - and
2287          * nested_vmx_exit_handled() will not pass related exits to L1.
2288          * These rules have exceptions below.
2289          */
2290
2291         /* pin-based controls */
2292         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2293               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
2294         nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2295         nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
2296                 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2297         nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2298                 PIN_BASED_VMX_PREEMPTION_TIMER;
2299
2300         /* exit controls */
2301         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2302                 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
2303         nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2304
2305         nested_vmx_exit_ctls_high &=
2306 #ifdef CONFIG_X86_64
2307                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2308 #endif
2309                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2310         nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2311                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2312                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2313
2314         if (vmx_mpx_supported())
2315                 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2316
2317         /* We support free control of debug control saving. */
2318         nested_vmx_true_exit_ctls_low = nested_vmx_exit_ctls_low &
2319                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2320
2321         /* entry controls */
2322         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2323                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2324         nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2325         nested_vmx_entry_ctls_high &=
2326 #ifdef CONFIG_X86_64
2327                 VM_ENTRY_IA32E_MODE |
2328 #endif
2329                 VM_ENTRY_LOAD_IA32_PAT;
2330         nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2331                                        VM_ENTRY_LOAD_IA32_EFER);
2332         if (vmx_mpx_supported())
2333                 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2334
2335         /* We support free control of debug control loading. */
2336         nested_vmx_true_entry_ctls_low = nested_vmx_entry_ctls_low &
2337                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2338
2339         /* cpu-based controls */
2340         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2341                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2342         nested_vmx_procbased_ctls_low = CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2343         nested_vmx_procbased_ctls_high &=
2344                 CPU_BASED_VIRTUAL_INTR_PENDING |
2345                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2346                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2347                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2348                 CPU_BASED_CR3_STORE_EXITING |
2349 #ifdef CONFIG_X86_64
2350                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2351 #endif
2352                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2353                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2354                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2355                 CPU_BASED_PAUSE_EXITING |
2356                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2357         /*
2358          * We can allow some features even when not supported by the
2359          * hardware. For example, L1 can specify an MSR bitmap - and we
2360          * can use it to avoid exits to L1 - even when L0 runs L2
2361          * without MSR bitmaps.
2362          */
2363         nested_vmx_procbased_ctls_high |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2364                 CPU_BASED_USE_MSR_BITMAPS;
2365
2366         /* We support free control of CR3 access interception. */
2367         nested_vmx_true_procbased_ctls_low = nested_vmx_procbased_ctls_low &
2368                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2369
2370         /* secondary cpu-based controls */
2371         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2372                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2373         nested_vmx_secondary_ctls_low = 0;
2374         nested_vmx_secondary_ctls_high &=
2375                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2376                 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2377                 SECONDARY_EXEC_WBINVD_EXITING;
2378
2379         if (enable_ept) {
2380                 /* nested EPT: emulate EPT also to L1 */
2381                 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
2382                 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2383                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2384                          VMX_EPT_INVEPT_BIT;
2385                 nested_vmx_ept_caps &= vmx_capability.ept;
2386                 /*
2387                  * For nested guests, we don't do anything specific
2388                  * for single context invalidation. Hence, only advertise
2389                  * support for global context invalidation.
2390                  */
2391                 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2392         } else
2393                 nested_vmx_ept_caps = 0;
2394
2395         /* miscellaneous data */
2396         rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
2397         nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2398         nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2399                 VMX_MISC_ACTIVITY_HLT;
2400         nested_vmx_misc_high = 0;
2401 }
2402
2403 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2404 {
2405         /*
2406          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2407          */
2408         return ((control & high) | low) == control;
2409 }
2410
2411 static inline u64 vmx_control_msr(u32 low, u32 high)
2412 {
2413         return low | ((u64)high << 32);
2414 }
2415
2416 /* Returns 0 on success, non-0 otherwise. */
2417 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2418 {
2419         switch (msr_index) {
2420         case MSR_IA32_VMX_BASIC:
2421                 /*
2422                  * This MSR reports some information about VMX support. We
2423                  * should return information about the VMX we emulate for the
2424                  * guest, and the VMCS structure we give it - not about the
2425                  * VMX support of the underlying hardware.
2426                  */
2427                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2428                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2429                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2430                 break;
2431         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2432         case MSR_IA32_VMX_PINBASED_CTLS:
2433                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2434                                         nested_vmx_pinbased_ctls_high);
2435                 break;
2436         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2437                 *pdata = vmx_control_msr(nested_vmx_true_procbased_ctls_low,
2438                                         nested_vmx_procbased_ctls_high);
2439                 break;
2440         case MSR_IA32_VMX_PROCBASED_CTLS:
2441                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2442                                         nested_vmx_procbased_ctls_high);
2443                 break;
2444         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2445                 *pdata = vmx_control_msr(nested_vmx_true_exit_ctls_low,
2446                                         nested_vmx_exit_ctls_high);
2447                 break;
2448         case MSR_IA32_VMX_EXIT_CTLS:
2449                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2450                                         nested_vmx_exit_ctls_high);
2451                 break;
2452         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2453                 *pdata = vmx_control_msr(nested_vmx_true_entry_ctls_low,
2454                                         nested_vmx_entry_ctls_high);
2455                 break;
2456         case MSR_IA32_VMX_ENTRY_CTLS:
2457                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2458                                         nested_vmx_entry_ctls_high);
2459                 break;
2460         case MSR_IA32_VMX_MISC:
2461                 *pdata = vmx_control_msr(nested_vmx_misc_low,
2462                                          nested_vmx_misc_high);
2463                 break;
2464         /*
2465          * These MSRs specify bits which the guest must keep fixed (on or off)
2466          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2467          * We picked the standard core2 setting.
2468          */
2469 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2470 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2471         case MSR_IA32_VMX_CR0_FIXED0:
2472                 *pdata = VMXON_CR0_ALWAYSON;
2473                 break;
2474         case MSR_IA32_VMX_CR0_FIXED1:
2475                 *pdata = -1ULL;
2476                 break;
2477         case MSR_IA32_VMX_CR4_FIXED0:
2478                 *pdata = VMXON_CR4_ALWAYSON;
2479                 break;
2480         case MSR_IA32_VMX_CR4_FIXED1:
2481                 *pdata = -1ULL;
2482                 break;
2483         case MSR_IA32_VMX_VMCS_ENUM:
2484                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2485                 break;
2486         case MSR_IA32_VMX_PROCBASED_CTLS2:
2487                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2488                                         nested_vmx_secondary_ctls_high);
2489                 break;
2490         case MSR_IA32_VMX_EPT_VPID_CAP:
2491                 /* Currently, no nested vpid support */
2492                 *pdata = nested_vmx_ept_caps;
2493                 break;
2494         default:
2495                 return 1;
2496         }
2497
2498         return 0;
2499 }
2500
2501 /*
2502  * Reads an msr value (of 'msr_index') into 'pdata'.
2503  * Returns 0 on success, non-0 otherwise.
2504  * Assumes vcpu_load() was already called.
2505  */
2506 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2507 {
2508         u64 data;
2509         struct shared_msr_entry *msr;
2510
2511         if (!pdata) {
2512                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2513                 return -EINVAL;
2514         }
2515
2516         switch (msr_index) {
2517 #ifdef CONFIG_X86_64
2518         case MSR_FS_BASE:
2519                 data = vmcs_readl(GUEST_FS_BASE);
2520                 break;
2521         case MSR_GS_BASE:
2522                 data = vmcs_readl(GUEST_GS_BASE);
2523                 break;
2524         case MSR_KERNEL_GS_BASE:
2525                 vmx_load_host_state(to_vmx(vcpu));
2526                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2527                 break;
2528 #endif
2529         case MSR_EFER:
2530                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2531         case MSR_IA32_TSC:
2532                 data = guest_read_tsc();
2533                 break;
2534         case MSR_IA32_SYSENTER_CS:
2535                 data = vmcs_read32(GUEST_SYSENTER_CS);
2536                 break;
2537         case MSR_IA32_SYSENTER_EIP:
2538                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2539                 break;
2540         case MSR_IA32_SYSENTER_ESP:
2541                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2542                 break;
2543         case MSR_IA32_BNDCFGS:
2544                 if (!vmx_mpx_supported())
2545                         return 1;
2546                 data = vmcs_read64(GUEST_BNDCFGS);
2547                 break;
2548         case MSR_IA32_FEATURE_CONTROL:
2549                 if (!nested_vmx_allowed(vcpu))
2550                         return 1;
2551                 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2552                 break;
2553         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2554                 if (!nested_vmx_allowed(vcpu))
2555                         return 1;
2556                 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
2557         case MSR_TSC_AUX:
2558                 if (!to_vmx(vcpu)->rdtscp_enabled)
2559                         return 1;
2560                 /* Otherwise falls through */
2561         default:
2562                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2563                 if (msr) {
2564                         data = msr->data;
2565                         break;
2566                 }
2567                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2568         }
2569
2570         *pdata = data;
2571         return 0;
2572 }
2573
2574 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2575
2576 /*
2577  * Writes msr value into into the appropriate "register".
2578  * Returns 0 on success, non-0 otherwise.
2579  * Assumes vcpu_load() was already called.
2580  */
2581 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2582 {
2583         struct vcpu_vmx *vmx = to_vmx(vcpu);
2584         struct shared_msr_entry *msr;
2585         int ret = 0;
2586         u32 msr_index = msr_info->index;
2587         u64 data = msr_info->data;
2588
2589         switch (msr_index) {
2590         case MSR_EFER:
2591                 ret = kvm_set_msr_common(vcpu, msr_info);
2592                 break;
2593 #ifdef CONFIG_X86_64
2594         case MSR_FS_BASE:
2595                 vmx_segment_cache_clear(vmx);
2596                 vmcs_writel(GUEST_FS_BASE, data);
2597                 break;
2598         case MSR_GS_BASE:
2599                 vmx_segment_cache_clear(vmx);
2600                 vmcs_writel(GUEST_GS_BASE, data);
2601                 break;
2602         case MSR_KERNEL_GS_BASE:
2603                 vmx_load_host_state(vmx);
2604                 vmx->msr_guest_kernel_gs_base = data;
2605                 break;
2606 #endif
2607         case MSR_IA32_SYSENTER_CS:
2608                 vmcs_write32(GUEST_SYSENTER_CS, data);
2609                 break;
2610         case MSR_IA32_SYSENTER_EIP:
2611                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2612                 break;
2613         case MSR_IA32_SYSENTER_ESP:
2614                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2615                 break;
2616         case MSR_IA32_BNDCFGS:
2617                 if (!vmx_mpx_supported())
2618                         return 1;
2619                 vmcs_write64(GUEST_BNDCFGS, data);
2620                 break;
2621         case MSR_IA32_TSC:
2622                 kvm_write_tsc(vcpu, msr_info);
2623                 break;
2624         case MSR_IA32_CR_PAT:
2625                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2626                         vmcs_write64(GUEST_IA32_PAT, data);
2627                         vcpu->arch.pat = data;
2628                         break;
2629                 }
2630                 ret = kvm_set_msr_common(vcpu, msr_info);
2631                 break;
2632         case MSR_IA32_TSC_ADJUST:
2633                 ret = kvm_set_msr_common(vcpu, msr_info);
2634                 break;
2635         case MSR_IA32_FEATURE_CONTROL:
2636                 if (!nested_vmx_allowed(vcpu) ||
2637                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2638                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2639                         return 1;
2640                 vmx->nested.msr_ia32_feature_control = data;
2641                 if (msr_info->host_initiated && data == 0)
2642                         vmx_leave_nested(vcpu);
2643                 break;
2644         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2645                 return 1; /* they are read-only */
2646         case MSR_TSC_AUX:
2647                 if (!vmx->rdtscp_enabled)
2648                         return 1;
2649                 /* Check reserved bit, higher 32 bits should be zero */
2650                 if ((data >> 32) != 0)
2651                         return 1;
2652                 /* Otherwise falls through */
2653         default:
2654                 msr = find_msr_entry(vmx, msr_index);
2655                 if (msr) {
2656                         msr->data = data;
2657                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2658                                 preempt_disable();
2659                                 kvm_set_shared_msr(msr->index, msr->data,
2660                                                    msr->mask);
2661                                 preempt_enable();
2662                         }
2663                         break;
2664                 }
2665                 ret = kvm_set_msr_common(vcpu, msr_info);
2666         }
2667
2668         return ret;
2669 }
2670
2671 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2672 {
2673         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2674         switch (reg) {
2675         case VCPU_REGS_RSP:
2676                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2677                 break;
2678         case VCPU_REGS_RIP:
2679                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2680                 break;
2681         case VCPU_EXREG_PDPTR:
2682                 if (enable_ept)
2683                         ept_save_pdptrs(vcpu);
2684                 break;
2685         default:
2686                 break;
2687         }
2688 }
2689
2690 static __init int cpu_has_kvm_support(void)
2691 {
2692         return cpu_has_vmx();
2693 }
2694
2695 static __init int vmx_disabled_by_bios(void)
2696 {
2697         u64 msr;
2698
2699         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2700         if (msr & FEATURE_CONTROL_LOCKED) {
2701                 /* launched w/ TXT and VMX disabled */
2702                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2703                         && tboot_enabled())
2704                         return 1;
2705                 /* launched w/o TXT and VMX only enabled w/ TXT */
2706                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2707                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2708                         && !tboot_enabled()) {
2709                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2710                                 "activate TXT before enabling KVM\n");
2711                         return 1;
2712                 }
2713                 /* launched w/o TXT and VMX disabled */
2714                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2715                         && !tboot_enabled())
2716                         return 1;
2717         }
2718
2719         return 0;
2720 }
2721
2722 static void kvm_cpu_vmxon(u64 addr)
2723 {
2724         asm volatile (ASM_VMX_VMXON_RAX
2725                         : : "a"(&addr), "m"(addr)
2726                         : "memory", "cc");
2727 }
2728
2729 static int hardware_enable(void *garbage)
2730 {
2731         int cpu = raw_smp_processor_id();
2732         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2733         u64 old, test_bits;
2734
2735         if (read_cr4() & X86_CR4_VMXE)
2736                 return -EBUSY;
2737
2738         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2739
2740         /*
2741          * Now we can enable the vmclear operation in kdump
2742          * since the loaded_vmcss_on_cpu list on this cpu
2743          * has been initialized.
2744          *
2745          * Though the cpu is not in VMX operation now, there
2746          * is no problem to enable the vmclear operation
2747          * for the loaded_vmcss_on_cpu list is empty!
2748          */
2749         crash_enable_local_vmclear(cpu);
2750
2751         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2752
2753         test_bits = FEATURE_CONTROL_LOCKED;
2754         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2755         if (tboot_enabled())
2756                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2757
2758         if ((old & test_bits) != test_bits) {
2759                 /* enable and lock */
2760                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2761         }
2762         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2763
2764         if (vmm_exclusive) {
2765                 kvm_cpu_vmxon(phys_addr);
2766                 ept_sync_global();
2767         }
2768
2769         native_store_gdt(&__get_cpu_var(host_gdt));
2770
2771         return 0;
2772 }
2773
2774 static void vmclear_local_loaded_vmcss(void)
2775 {
2776         int cpu = raw_smp_processor_id();
2777         struct loaded_vmcs *v, *n;
2778
2779         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2780                                  loaded_vmcss_on_cpu_link)
2781                 __loaded_vmcs_clear(v);
2782 }
2783
2784
2785 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2786  * tricks.
2787  */
2788 static void kvm_cpu_vmxoff(void)
2789 {
2790         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2791 }
2792
2793 static void hardware_disable(void *garbage)
2794 {
2795         if (vmm_exclusive) {
2796                 vmclear_local_loaded_vmcss();
2797                 kvm_cpu_vmxoff();
2798         }
2799         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2800 }
2801
2802 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2803                                       u32 msr, u32 *result)
2804 {
2805         u32 vmx_msr_low, vmx_msr_high;
2806         u32 ctl = ctl_min | ctl_opt;
2807
2808         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2809
2810         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2811         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2812
2813         /* Ensure minimum (required) set of control bits are supported. */
2814         if (ctl_min & ~ctl)
2815                 return -EIO;
2816
2817         *result = ctl;
2818         return 0;
2819 }
2820
2821 static __init bool allow_1_setting(u32 msr, u32 ctl)
2822 {
2823         u32 vmx_msr_low, vmx_msr_high;
2824
2825         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2826         return vmx_msr_high & ctl;
2827 }
2828
2829 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2830 {
2831         u32 vmx_msr_low, vmx_msr_high;
2832         u32 min, opt, min2, opt2;
2833         u32 _pin_based_exec_control = 0;
2834         u32 _cpu_based_exec_control = 0;
2835         u32 _cpu_based_2nd_exec_control = 0;
2836         u32 _vmexit_control = 0;
2837         u32 _vmentry_control = 0;
2838
2839         min = CPU_BASED_HLT_EXITING |
2840 #ifdef CONFIG_X86_64
2841               CPU_BASED_CR8_LOAD_EXITING |
2842               CPU_BASED_CR8_STORE_EXITING |
2843 #endif
2844               CPU_BASED_CR3_LOAD_EXITING |
2845               CPU_BASED_CR3_STORE_EXITING |
2846               CPU_BASED_USE_IO_BITMAPS |
2847               CPU_BASED_MOV_DR_EXITING |
2848               CPU_BASED_USE_TSC_OFFSETING |
2849               CPU_BASED_MWAIT_EXITING |
2850               CPU_BASED_MONITOR_EXITING |
2851               CPU_BASED_INVLPG_EXITING |
2852               CPU_BASED_RDPMC_EXITING;
2853
2854         opt = CPU_BASED_TPR_SHADOW |
2855               CPU_BASED_USE_MSR_BITMAPS |
2856               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2857         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2858                                 &_cpu_based_exec_control) < 0)
2859                 return -EIO;
2860 #ifdef CONFIG_X86_64
2861         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2862                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2863                                            ~CPU_BASED_CR8_STORE_EXITING;
2864 #endif
2865         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2866                 min2 = 0;
2867                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2868                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2869                         SECONDARY_EXEC_WBINVD_EXITING |
2870                         SECONDARY_EXEC_ENABLE_VPID |
2871                         SECONDARY_EXEC_ENABLE_EPT |
2872                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2873                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2874                         SECONDARY_EXEC_RDTSCP |
2875                         SECONDARY_EXEC_ENABLE_INVPCID |
2876                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
2877                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2878                         SECONDARY_EXEC_SHADOW_VMCS;
2879                 if (adjust_vmx_controls(min2, opt2,
2880                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2881                                         &_cpu_based_2nd_exec_control) < 0)
2882                         return -EIO;
2883         }
2884 #ifndef CONFIG_X86_64
2885         if (!(_cpu_based_2nd_exec_control &
2886                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2887                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2888 #endif
2889
2890         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2891                 _cpu_based_2nd_exec_control &= ~(
2892                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2893                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2894                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
2895
2896         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2897                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2898                    enabled */
2899                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2900                                              CPU_BASED_CR3_STORE_EXITING |
2901                                              CPU_BASED_INVLPG_EXITING);
2902                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2903                       vmx_capability.ept, vmx_capability.vpid);
2904         }
2905
2906         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
2907 #ifdef CONFIG_X86_64
2908         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2909 #endif
2910         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2911                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
2912         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2913                                 &_vmexit_control) < 0)
2914                 return -EIO;
2915
2916         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2917         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2918         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2919                                 &_pin_based_exec_control) < 0)
2920                 return -EIO;
2921
2922         if (!(_cpu_based_2nd_exec_control &
2923                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2924                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2925                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2926
2927         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
2928         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
2929         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2930                                 &_vmentry_control) < 0)
2931                 return -EIO;
2932
2933         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2934
2935         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2936         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2937                 return -EIO;
2938
2939 #ifdef CONFIG_X86_64
2940         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2941         if (vmx_msr_high & (1u<<16))
2942                 return -EIO;
2943 #endif
2944
2945         /* Require Write-Back (WB) memory type for VMCS accesses. */
2946         if (((vmx_msr_high >> 18) & 15) != 6)
2947                 return -EIO;
2948
2949         vmcs_conf->size = vmx_msr_high & 0x1fff;
2950         vmcs_conf->order = get_order(vmcs_config.size);
2951         vmcs_conf->revision_id = vmx_msr_low;
2952
2953         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2954         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2955         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2956         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2957         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2958
2959         cpu_has_load_ia32_efer =
2960                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2961                                 VM_ENTRY_LOAD_IA32_EFER)
2962                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2963                                    VM_EXIT_LOAD_IA32_EFER);
2964
2965         cpu_has_load_perf_global_ctrl =
2966                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2967                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2968                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2969                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2970
2971         /*
2972          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2973          * but due to arrata below it can't be used. Workaround is to use
2974          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2975          *
2976          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2977          *
2978          * AAK155             (model 26)
2979          * AAP115             (model 30)
2980          * AAT100             (model 37)
2981          * BC86,AAY89,BD102   (model 44)
2982          * BA97               (model 46)
2983          *
2984          */
2985         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2986                 switch (boot_cpu_data.x86_model) {
2987                 case 26:
2988                 case 30:
2989                 case 37:
2990                 case 44:
2991                 case 46:
2992                         cpu_has_load_perf_global_ctrl = false;
2993                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2994                                         "does not work properly. Using workaround\n");
2995                         break;
2996                 default:
2997                         break;
2998                 }
2999         }
3000
3001         return 0;
3002 }
3003
3004 static struct vmcs *alloc_vmcs_cpu(int cpu)
3005 {
3006         int node = cpu_to_node(cpu);
3007         struct page *pages;
3008         struct vmcs *vmcs;
3009
3010         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
3011         if (!pages)
3012                 return NULL;
3013         vmcs = page_address(pages);
3014         memset(vmcs, 0, vmcs_config.size);
3015         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3016         return vmcs;
3017 }
3018
3019 static struct vmcs *alloc_vmcs(void)
3020 {
3021         return alloc_vmcs_cpu(raw_smp_processor_id());
3022 }
3023
3024 static void free_vmcs(struct vmcs *vmcs)
3025 {
3026         free_pages((unsigned long)vmcs, vmcs_config.order);
3027 }
3028
3029 /*
3030  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3031  */
3032 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3033 {
3034         if (!loaded_vmcs->vmcs)
3035                 return;
3036         loaded_vmcs_clear(loaded_vmcs);
3037         free_vmcs(loaded_vmcs->vmcs);
3038         loaded_vmcs->vmcs = NULL;
3039 }
3040
3041 static void free_kvm_area(void)
3042 {
3043         int cpu;
3044
3045         for_each_possible_cpu(cpu) {
3046                 free_vmcs(per_cpu(vmxarea, cpu));
3047                 per_cpu(vmxarea, cpu) = NULL;
3048         }
3049 }
3050
3051 static void init_vmcs_shadow_fields(void)
3052 {
3053         int i, j;
3054
3055         /* No checks for read only fields yet */
3056
3057         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3058                 switch (shadow_read_write_fields[i]) {
3059                 case GUEST_BNDCFGS:
3060                         if (!vmx_mpx_supported())
3061                                 continue;
3062                         break;
3063                 default:
3064                         break;
3065                 }
3066
3067                 if (j < i)
3068                         shadow_read_write_fields[j] =
3069                                 shadow_read_write_fields[i];
3070                 j++;
3071         }
3072         max_shadow_read_write_fields = j;
3073
3074         /* shadowed fields guest access without vmexit */
3075         for (i = 0; i < max_shadow_read_write_fields; i++) {
3076                 clear_bit(shadow_read_write_fields[i],
3077                           vmx_vmwrite_bitmap);
3078                 clear_bit(shadow_read_write_fields[i],
3079                           vmx_vmread_bitmap);
3080         }
3081         for (i = 0; i < max_shadow_read_only_fields; i++)
3082                 clear_bit(shadow_read_only_fields[i],
3083                           vmx_vmread_bitmap);
3084 }
3085
3086 static __init int alloc_kvm_area(void)
3087 {
3088         int cpu;
3089
3090         for_each_possible_cpu(cpu) {
3091                 struct vmcs *vmcs;
3092
3093                 vmcs = alloc_vmcs_cpu(cpu);
3094                 if (!vmcs) {
3095                         free_kvm_area();
3096                         return -ENOMEM;
3097                 }
3098
3099                 per_cpu(vmxarea, cpu) = vmcs;
3100         }
3101         return 0;
3102 }
3103
3104 static __init int hardware_setup(void)
3105 {
3106         if (setup_vmcs_config(&vmcs_config) < 0)
3107                 return -EIO;
3108
3109         if (boot_cpu_has(X86_FEATURE_NX))
3110                 kvm_enable_efer_bits(EFER_NX);
3111
3112         if (!cpu_has_vmx_vpid())
3113                 enable_vpid = 0;
3114         if (!cpu_has_vmx_shadow_vmcs())
3115                 enable_shadow_vmcs = 0;
3116         if (enable_shadow_vmcs)
3117                 init_vmcs_shadow_fields();
3118
3119         if (!cpu_has_vmx_ept() ||
3120             !cpu_has_vmx_ept_4levels()) {
3121                 enable_ept = 0;
3122                 enable_unrestricted_guest = 0;
3123                 enable_ept_ad_bits = 0;
3124         }
3125
3126         if (!cpu_has_vmx_ept_ad_bits())
3127                 enable_ept_ad_bits = 0;
3128
3129         if (!cpu_has_vmx_unrestricted_guest())
3130                 enable_unrestricted_guest = 0;
3131
3132         if (!cpu_has_vmx_flexpriority())
3133                 flexpriority_enabled = 0;
3134
3135         if (!cpu_has_vmx_tpr_shadow())
3136                 kvm_x86_ops->update_cr8_intercept = NULL;
3137
3138         if (enable_ept && !cpu_has_vmx_ept_2m_page())
3139                 kvm_disable_largepages();
3140
3141         if (!cpu_has_vmx_ple())
3142                 ple_gap = 0;
3143
3144         if (!cpu_has_vmx_apicv())
3145                 enable_apicv = 0;
3146
3147         if (enable_apicv)
3148                 kvm_x86_ops->update_cr8_intercept = NULL;
3149         else {
3150                 kvm_x86_ops->hwapic_irr_update = NULL;
3151                 kvm_x86_ops->deliver_posted_interrupt = NULL;
3152                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3153         }
3154
3155         if (nested)
3156                 nested_vmx_setup_ctls_msrs();
3157
3158         return alloc_kvm_area();
3159 }
3160
3161 static __exit void hardware_unsetup(void)
3162 {
3163         free_kvm_area();
3164 }
3165
3166 static bool emulation_required(struct kvm_vcpu *vcpu)
3167 {
3168         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3169 }
3170
3171 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3172                 struct kvm_segment *save)
3173 {
3174         if (!emulate_invalid_guest_state) {
3175                 /*
3176                  * CS and SS RPL should be equal during guest entry according
3177                  * to VMX spec, but in reality it is not always so. Since vcpu
3178                  * is in the middle of the transition from real mode to
3179                  * protected mode it is safe to assume that RPL 0 is a good
3180                  * default value.
3181                  */
3182                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3183                         save->selector &= ~SELECTOR_RPL_MASK;
3184                 save->dpl = save->selector & SELECTOR_RPL_MASK;
3185                 save->s = 1;
3186         }
3187         vmx_set_segment(vcpu, save, seg);
3188 }
3189
3190 static void enter_pmode(struct kvm_vcpu *vcpu)
3191 {
3192         unsigned long flags;
3193         struct vcpu_vmx *vmx = to_vmx(vcpu);
3194
3195         /*
3196          * Update real mode segment cache. It may be not up-to-date if sement
3197          * register was written while vcpu was in a guest mode.
3198          */
3199         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3200         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3201         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3202         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3203         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3204         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3205
3206         vmx->rmode.vm86_active = 0;
3207
3208         vmx_segment_cache_clear(vmx);
3209
3210         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3211
3212         flags = vmcs_readl(GUEST_RFLAGS);
3213         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3214         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3215         vmcs_writel(GUEST_RFLAGS, flags);
3216
3217         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3218                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3219
3220         update_exception_bitmap(vcpu);
3221
3222         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3223         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3224         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3225         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3226         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3227         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3228 }
3229
3230 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3231 {
3232         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3233         struct kvm_segment var = *save;
3234
3235         var.dpl = 0x3;
3236         if (seg == VCPU_SREG_CS)
3237                 var.type = 0x3;
3238
3239         if (!emulate_invalid_guest_state) {
3240                 var.selector = var.base >> 4;
3241                 var.base = var.base & 0xffff0;
3242                 var.limit = 0xffff;
3243                 var.g = 0;
3244                 var.db = 0;
3245                 var.present = 1;
3246                 var.s = 1;
3247                 var.l = 0;
3248                 var.unusable = 0;
3249                 var.type = 0x3;
3250                 var.avl = 0;
3251                 if (save->base & 0xf)
3252                         printk_once(KERN_WARNING "kvm: segment base is not "
3253                                         "paragraph aligned when entering "
3254                                         "protected mode (seg=%d)", seg);
3255         }
3256
3257         vmcs_write16(sf->selector, var.selector);
3258         vmcs_write32(sf->base, var.base);
3259         vmcs_write32(sf->limit, var.limit);
3260         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3261 }
3262
3263 static void enter_rmode(struct kvm_vcpu *vcpu)
3264 {
3265         unsigned long flags;
3266         struct vcpu_vmx *vmx = to_vmx(vcpu);
3267
3268         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3269         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3270         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3271         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3272         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3273         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3274         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3275
3276         vmx->rmode.vm86_active = 1;
3277
3278         /*
3279          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3280          * vcpu. Warn the user that an update is overdue.
3281          */
3282         if (!vcpu->kvm->arch.tss_addr)
3283                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3284                              "called before entering vcpu\n");
3285
3286         vmx_segment_cache_clear(vmx);
3287
3288         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3289         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3290         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3291
3292         flags = vmcs_readl(GUEST_RFLAGS);
3293         vmx->rmode.save_rflags = flags;
3294
3295         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3296
3297         vmcs_writel(GUEST_RFLAGS, flags);
3298         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3299         update_exception_bitmap(vcpu);
3300
3301         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3302         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3303         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3304         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3305         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3306         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3307
3308         kvm_mmu_reset_context(vcpu);
3309 }
3310
3311 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3312 {
3313         struct vcpu_vmx *vmx = to_vmx(vcpu);
3314         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3315
3316         if (!msr)
3317                 return;
3318
3319         /*
3320          * Force kernel_gs_base reloading before EFER changes, as control
3321          * of this msr depends on is_long_mode().
3322          */
3323         vmx_load_host_state(to_vmx(vcpu));
3324         vcpu->arch.efer = efer;
3325         if (efer & EFER_LMA) {
3326                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3327                 msr->data = efer;
3328         } else {
3329                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3330
3331                 msr->data = efer & ~EFER_LME;
3332         }
3333         setup_msrs(vmx);
3334 }
3335
3336 #ifdef CONFIG_X86_64
3337
3338 static void enter_lmode(struct kvm_vcpu *vcpu)
3339 {
3340         u32 guest_tr_ar;
3341
3342         vmx_segment_cache_clear(to_vmx(vcpu));
3343
3344         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3345         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
3346                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3347                                      __func__);
3348                 vmcs_write32(GUEST_TR_AR_BYTES,
3349                              (guest_tr_ar & ~AR_TYPE_MASK)
3350                              | AR_TYPE_BUSY_64_TSS);
3351         }
3352         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3353 }
3354
3355 static void exit_lmode(struct kvm_vcpu *vcpu)
3356 {
3357         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3358         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3359 }
3360
3361 #endif
3362
3363 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3364 {
3365         vpid_sync_context(to_vmx(vcpu));
3366         if (enable_ept) {
3367                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3368                         return;
3369                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3370         }
3371 }
3372
3373 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3374 {
3375         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3376
3377         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3378         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3379 }
3380
3381 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3382 {
3383         if (enable_ept && is_paging(vcpu))
3384                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3385         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3386 }
3387
3388 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3389 {
3390         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3391
3392         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3393         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3394 }
3395
3396 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3397 {
3398         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3399
3400         if (!test_bit(VCPU_EXREG_PDPTR,
3401                       (unsigned long *)&vcpu->arch.regs_dirty))
3402                 return;
3403
3404         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3405                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3406                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3407                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3408                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3409         }
3410 }
3411
3412 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3413 {
3414         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3415
3416         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3417                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3418                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3419                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3420                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3421         }
3422
3423         __set_bit(VCPU_EXREG_PDPTR,
3424                   (unsigned long *)&vcpu->arch.regs_avail);
3425         __set_bit(VCPU_EXREG_PDPTR,
3426                   (unsigned long *)&vcpu->arch.regs_dirty);
3427 }
3428
3429 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3430
3431 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3432                                         unsigned long cr0,
3433                                         struct kvm_vcpu *vcpu)
3434 {
3435         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3436                 vmx_decache_cr3(vcpu);
3437         if (!(cr0 & X86_CR0_PG)) {
3438                 /* From paging/starting to nonpaging */
3439                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3440                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3441                              (CPU_BASED_CR3_LOAD_EXITING |
3442                               CPU_BASED_CR3_STORE_EXITING));
3443                 vcpu->arch.cr0 = cr0;
3444                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3445         } else if (!is_paging(vcpu)) {
3446                 /* From nonpaging to paging */
3447                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3448                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3449                              ~(CPU_BASED_CR3_LOAD_EXITING |
3450                                CPU_BASED_CR3_STORE_EXITING));
3451                 vcpu->arch.cr0 = cr0;
3452                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3453         }
3454
3455         if (!(cr0 & X86_CR0_WP))
3456                 *hw_cr0 &= ~X86_CR0_WP;
3457 }
3458
3459 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3460 {
3461         struct vcpu_vmx *vmx = to_vmx(vcpu);
3462         unsigned long hw_cr0;
3463
3464         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3465         if (enable_unrestricted_guest)
3466                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3467         else {
3468                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3469
3470                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3471                         enter_pmode(vcpu);
3472
3473                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3474                         enter_rmode(vcpu);
3475         }
3476
3477 #ifdef CONFIG_X86_64
3478         if (vcpu->arch.efer & EFER_LME) {
3479                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3480                         enter_lmode(vcpu);
3481                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3482                         exit_lmode(vcpu);
3483         }
3484 #endif
3485
3486         if (enable_ept)
3487                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3488
3489         if (!vcpu->fpu_active)
3490                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3491
3492         vmcs_writel(CR0_READ_SHADOW, cr0);
3493         vmcs_writel(GUEST_CR0, hw_cr0);
3494         vcpu->arch.cr0 = cr0;
3495
3496         /* depends on vcpu->arch.cr0 to be set to a new value */
3497         vmx->emulation_required = emulation_required(vcpu);
3498 }
3499
3500 static u64 construct_eptp(unsigned long root_hpa)
3501 {
3502         u64 eptp;
3503
3504         /* TODO write the value reading from MSR */
3505         eptp = VMX_EPT_DEFAULT_MT |
3506                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3507         if (enable_ept_ad_bits)
3508                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3509         eptp |= (root_hpa & PAGE_MASK);
3510
3511         return eptp;
3512 }
3513
3514 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3515 {
3516         unsigned long guest_cr3;
3517         u64 eptp;
3518
3519         guest_cr3 = cr3;
3520         if (enable_ept) {
3521                 eptp = construct_eptp(cr3);
3522                 vmcs_write64(EPT_POINTER, eptp);
3523                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3524                         guest_cr3 = kvm_read_cr3(vcpu);
3525                 else
3526                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3527                 ept_load_pdptrs(vcpu);
3528         }
3529
3530         vmx_flush_tlb(vcpu);
3531         vmcs_writel(GUEST_CR3, guest_cr3);
3532 }
3533
3534 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3535 {
3536         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3537                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3538
3539         if (cr4 & X86_CR4_VMXE) {
3540                 /*
3541                  * To use VMXON (and later other VMX instructions), a guest
3542                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3543                  * So basically the check on whether to allow nested VMX
3544                  * is here.
3545                  */
3546                 if (!nested_vmx_allowed(vcpu))
3547                         return 1;
3548         }
3549         if (to_vmx(vcpu)->nested.vmxon &&
3550             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3551                 return 1;
3552
3553         vcpu->arch.cr4 = cr4;
3554         if (enable_ept) {
3555                 if (!is_paging(vcpu)) {
3556                         hw_cr4 &= ~X86_CR4_PAE;
3557                         hw_cr4 |= X86_CR4_PSE;
3558                         /*
3559                          * SMEP/SMAP is disabled if CPU is in non-paging mode
3560                          * in hardware. However KVM always uses paging mode to
3561                          * emulate guest non-paging mode with TDP.
3562                          * To emulate this behavior, SMEP/SMAP needs to be
3563                          * manually disabled when guest switches to non-paging
3564                          * mode.
3565                          */
3566                         hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3567                 } else if (!(cr4 & X86_CR4_PAE)) {
3568                         hw_cr4 &= ~X86_CR4_PAE;
3569                 }
3570         }
3571
3572         vmcs_writel(CR4_READ_SHADOW, cr4);
3573         vmcs_writel(GUEST_CR4, hw_cr4);
3574         return 0;
3575 }
3576
3577 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3578                             struct kvm_segment *var, int seg)
3579 {
3580         struct vcpu_vmx *vmx = to_vmx(vcpu);
3581         u32 ar;
3582
3583         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3584                 *var = vmx->rmode.segs[seg];
3585                 if (seg == VCPU_SREG_TR
3586                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3587                         return;
3588                 var->base = vmx_read_guest_seg_base(vmx, seg);
3589                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3590                 return;
3591         }
3592         var->base = vmx_read_guest_seg_base(vmx, seg);
3593         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3594         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3595         ar = vmx_read_guest_seg_ar(vmx, seg);
3596         var->unusable = (ar >> 16) & 1;
3597         var->type = ar & 15;
3598         var->s = (ar >> 4) & 1;
3599         var->dpl = (ar >> 5) & 3;
3600         /*
3601          * Some userspaces do not preserve unusable property. Since usable
3602          * segment has to be present according to VMX spec we can use present
3603          * property to amend userspace bug by making unusable segment always
3604          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3605          * segment as unusable.
3606          */
3607         var->present = !var->unusable;
3608         var->avl = (ar >> 12) & 1;
3609         var->l = (ar >> 13) & 1;
3610         var->db = (ar >> 14) & 1;
3611         var->g = (ar >> 15) & 1;
3612 }
3613
3614 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3615 {
3616         struct kvm_segment s;
3617
3618         if (to_vmx(vcpu)->rmode.vm86_active) {
3619                 vmx_get_segment(vcpu, &s, seg);
3620                 return s.base;
3621         }
3622         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3623 }
3624
3625 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3626 {
3627         struct vcpu_vmx *vmx = to_vmx(vcpu);
3628
3629         if (unlikely(vmx->rmode.vm86_active))
3630                 return 0;
3631         else {
3632                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3633                 return AR_DPL(ar);
3634         }
3635 }
3636
3637 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3638 {
3639         u32 ar;
3640
3641         if (var->unusable || !var->present)
3642                 ar = 1 << 16;
3643         else {
3644                 ar = var->type & 15;
3645                 ar |= (var->s & 1) << 4;
3646                 ar |= (var->dpl & 3) << 5;
3647                 ar |= (var->present & 1) << 7;
3648                 ar |= (var->avl & 1) << 12;
3649                 ar |= (var->l & 1) << 13;
3650                 ar |= (var->db & 1) << 14;
3651                 ar |= (var->g & 1) << 15;
3652         }
3653
3654         return ar;
3655 }
3656
3657 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3658                             struct kvm_segment *var, int seg)
3659 {
3660         struct vcpu_vmx *vmx = to_vmx(vcpu);
3661         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3662
3663         vmx_segment_cache_clear(vmx);
3664
3665         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3666                 vmx->rmode.segs[seg] = *var;
3667                 if (seg == VCPU_SREG_TR)
3668                         vmcs_write16(sf->selector, var->selector);
3669                 else if (var->s)
3670                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3671                 goto out;
3672         }
3673
3674         vmcs_writel(sf->base, var->base);
3675         vmcs_write32(sf->limit, var->limit);
3676         vmcs_write16(sf->selector, var->selector);
3677
3678         /*
3679          *   Fix the "Accessed" bit in AR field of segment registers for older
3680          * qemu binaries.
3681          *   IA32 arch specifies that at the time of processor reset the
3682          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3683          * is setting it to 0 in the userland code. This causes invalid guest
3684          * state vmexit when "unrestricted guest" mode is turned on.
3685          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3686          * tree. Newer qemu binaries with that qemu fix would not need this
3687          * kvm hack.
3688          */
3689         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3690                 var->type |= 0x1; /* Accessed */
3691
3692         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3693
3694 out:
3695         vmx->emulation_required = emulation_required(vcpu);
3696 }
3697
3698 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3699 {
3700         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3701
3702         *db = (ar >> 14) & 1;
3703         *l = (ar >> 13) & 1;
3704 }
3705
3706 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3707 {
3708         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3709         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3710 }
3711
3712 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3713 {
3714         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3715         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3716 }
3717
3718 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3719 {
3720         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3721         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3722 }
3723
3724 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3725 {
3726         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3727         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3728 }
3729
3730 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3731 {
3732         struct kvm_segment var;
3733         u32 ar;
3734
3735         vmx_get_segment(vcpu, &var, seg);
3736         var.dpl = 0x3;
3737         if (seg == VCPU_SREG_CS)
3738                 var.type = 0x3;
3739         ar = vmx_segment_access_rights(&var);
3740
3741         if (var.base != (var.selector << 4))
3742                 return false;
3743         if (var.limit != 0xffff)
3744                 return false;
3745         if (ar != 0xf3)
3746                 return false;
3747
3748         return true;
3749 }
3750
3751 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3752 {
3753         struct kvm_segment cs;
3754         unsigned int cs_rpl;
3755
3756         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3757         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3758
3759         if (cs.unusable)
3760                 return false;
3761         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3762                 return false;
3763         if (!cs.s)
3764                 return false;
3765         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3766                 if (cs.dpl > cs_rpl)
3767                         return false;
3768         } else {
3769                 if (cs.dpl != cs_rpl)
3770                         return false;
3771         }
3772         if (!cs.present)
3773                 return false;
3774
3775         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3776         return true;
3777 }
3778
3779 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3780 {
3781         struct kvm_segment ss;
3782         unsigned int ss_rpl;
3783
3784         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3785         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3786
3787         if (ss.unusable)
3788                 return true;
3789         if (ss.type != 3 && ss.type != 7)
3790                 return false;
3791         if (!ss.s)
3792                 return false;
3793         if (ss.dpl != ss_rpl) /* DPL != RPL */
3794                 return false;
3795         if (!ss.present)
3796                 return false;
3797
3798         return true;
3799 }
3800
3801 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3802 {
3803         struct kvm_segment var;
3804         unsigned int rpl;
3805
3806         vmx_get_segment(vcpu, &var, seg);
3807         rpl = var.selector & SELECTOR_RPL_MASK;
3808
3809         if (var.unusable)
3810                 return true;
3811         if (!var.s)
3812                 return false;
3813         if (!var.present)
3814                 return false;
3815         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3816                 if (var.dpl < rpl) /* DPL < RPL */
3817                         return false;
3818         }
3819
3820         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3821          * rights flags
3822          */
3823         return true;
3824 }
3825
3826 static bool tr_valid(struct kvm_vcpu *vcpu)
3827 {
3828         struct kvm_segment tr;
3829
3830         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3831
3832         if (tr.unusable)
3833                 return false;
3834         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3835                 return false;
3836         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3837                 return false;
3838         if (!tr.present)
3839                 return false;
3840
3841         return true;
3842 }
3843
3844 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3845 {
3846         struct kvm_segment ldtr;
3847
3848         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3849
3850         if (ldtr.unusable)
3851                 return true;
3852         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3853                 return false;
3854         if (ldtr.type != 2)
3855                 return false;
3856         if (!ldtr.present)
3857                 return false;
3858
3859         return true;
3860 }
3861
3862 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3863 {
3864         struct kvm_segment cs, ss;
3865
3866         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3867         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3868
3869         return ((cs.selector & SELECTOR_RPL_MASK) ==
3870                  (ss.selector & SELECTOR_RPL_MASK));
3871 }
3872
3873 /*
3874  * Check if guest state is valid. Returns true if valid, false if
3875  * not.
3876  * We assume that registers are always usable
3877  */
3878 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3879 {
3880         if (enable_unrestricted_guest)
3881                 return true;
3882
3883         /* real mode guest state checks */
3884         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3885                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3886                         return false;
3887                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3888                         return false;
3889                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3890                         return false;
3891                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3892                         return false;
3893                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3894                         return false;
3895                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3896                         return false;
3897         } else {
3898         /* protected mode guest state checks */
3899                 if (!cs_ss_rpl_check(vcpu))
3900                         return false;
3901                 if (!code_segment_valid(vcpu))
3902                         return false;
3903                 if (!stack_segment_valid(vcpu))
3904                         return false;
3905                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3906                         return false;
3907                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3908                         return false;
3909                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3910                         return false;
3911                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3912                         return false;
3913                 if (!tr_valid(vcpu))
3914                         return false;
3915                 if (!ldtr_valid(vcpu))
3916                         return false;
3917         }
3918         /* TODO:
3919          * - Add checks on RIP
3920          * - Add checks on RFLAGS
3921          */
3922
3923         return true;
3924 }
3925
3926 static int init_rmode_tss(struct kvm *kvm)
3927 {
3928         gfn_t fn;
3929         u16 data = 0;
3930         int r, idx, ret = 0;
3931
3932         idx = srcu_read_lock(&kvm->srcu);
3933         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
3934         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3935         if (r < 0)
3936                 goto out;
3937         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3938         r = kvm_write_guest_page(kvm, fn++, &data,
3939                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3940         if (r < 0)
3941                 goto out;
3942         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3943         if (r < 0)
3944                 goto out;
3945         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3946         if (r < 0)
3947                 goto out;
3948         data = ~0;
3949         r = kvm_write_guest_page(kvm, fn, &data,
3950                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3951                                  sizeof(u8));
3952         if (r < 0)
3953                 goto out;
3954
3955         ret = 1;
3956 out:
3957         srcu_read_unlock(&kvm->srcu, idx);
3958         return ret;
3959 }
3960
3961 static int init_rmode_identity_map(struct kvm *kvm)
3962 {
3963         int i, idx, r, ret;
3964         pfn_t identity_map_pfn;
3965         u32 tmp;
3966
3967         if (!enable_ept)
3968                 return 1;
3969         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3970                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3971                         "haven't been allocated!\n");
3972                 return 0;
3973         }
3974         if (likely(kvm->arch.ept_identity_pagetable_done))
3975                 return 1;
3976         ret = 0;
3977         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3978         idx = srcu_read_lock(&kvm->srcu);
3979         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3980         if (r < 0)
3981                 goto out;
3982         /* Set up identity-mapping pagetable for EPT in real mode */
3983         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3984                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3985                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3986                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3987                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3988                 if (r < 0)
3989                         goto out;
3990         }
3991         kvm->arch.ept_identity_pagetable_done = true;
3992         ret = 1;
3993 out:
3994         srcu_read_unlock(&kvm->srcu, idx);
3995         return ret;
3996 }
3997
3998 static void seg_setup(int seg)
3999 {
4000         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4001         unsigned int ar;
4002
4003         vmcs_write16(sf->selector, 0);
4004         vmcs_writel(sf->base, 0);
4005         vmcs_write32(sf->limit, 0xffff);
4006         ar = 0x93;
4007         if (seg == VCPU_SREG_CS)
4008                 ar |= 0x08; /* code segment */
4009
4010         vmcs_write32(sf->ar_bytes, ar);
4011 }
4012
4013 static int alloc_apic_access_page(struct kvm *kvm)
4014 {
4015         struct page *page;
4016         struct kvm_userspace_memory_region kvm_userspace_mem;
4017         int r = 0;
4018
4019         mutex_lock(&kvm->slots_lock);
4020         if (kvm->arch.apic_access_page)
4021                 goto out;
4022         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4023         kvm_userspace_mem.flags = 0;
4024         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
4025         kvm_userspace_mem.memory_size = PAGE_SIZE;
4026         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4027         if (r)
4028                 goto out;
4029
4030         page = gfn_to_page(kvm, 0xfee00);
4031         if (is_error_page(page)) {
4032                 r = -EFAULT;
4033                 goto out;
4034         }
4035
4036         kvm->arch.apic_access_page = page;
4037 out:
4038         mutex_unlock(&kvm->slots_lock);
4039         return r;
4040 }
4041
4042 static int alloc_identity_pagetable(struct kvm *kvm)
4043 {
4044         struct page *page;
4045         struct kvm_userspace_memory_region kvm_userspace_mem;
4046         int r = 0;
4047
4048         mutex_lock(&kvm->slots_lock);
4049         if (kvm->arch.ept_identity_pagetable)
4050                 goto out;
4051         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4052         kvm_userspace_mem.flags = 0;
4053         kvm_userspace_mem.guest_phys_addr =
4054                 kvm->arch.ept_identity_map_addr;
4055         kvm_userspace_mem.memory_size = PAGE_SIZE;
4056         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
4057         if (r)
4058                 goto out;
4059
4060         page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
4061         if (is_error_page(page)) {
4062                 r = -EFAULT;
4063                 goto out;
4064         }
4065
4066         kvm->arch.ept_identity_pagetable = page;
4067 out:
4068         mutex_unlock(&kvm->slots_lock);
4069         return r;
4070 }
4071
4072 static void allocate_vpid(struct vcpu_vmx *vmx)
4073 {
4074         int vpid;
4075
4076         vmx->vpid = 0;
4077         if (!enable_vpid)
4078                 return;
4079         spin_lock(&vmx_vpid_lock);
4080         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4081         if (vpid < VMX_NR_VPIDS) {
4082                 vmx->vpid = vpid;
4083                 __set_bit(vpid, vmx_vpid_bitmap);
4084         }
4085         spin_unlock(&vmx_vpid_lock);
4086 }
4087
4088 static void free_vpid(struct vcpu_vmx *vmx)
4089 {
4090         if (!enable_vpid)
4091                 return;
4092         spin_lock(&vmx_vpid_lock);
4093         if (vmx->vpid != 0)
4094                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4095         spin_unlock(&vmx_vpid_lock);
4096 }
4097
4098 #define MSR_TYPE_R      1
4099 #define MSR_TYPE_W      2
4100 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4101                                                 u32 msr, int type)
4102 {
4103         int f = sizeof(unsigned long);
4104
4105         if (!cpu_has_vmx_msr_bitmap())
4106                 return;
4107
4108         /*
4109          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4110          * have the write-low and read-high bitmap offsets the wrong way round.
4111          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4112          */
4113         if (msr <= 0x1fff) {
4114                 if (type & MSR_TYPE_R)
4115                         /* read-low */
4116                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4117
4118                 if (type & MSR_TYPE_W)
4119                         /* write-low */
4120                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4121
4122         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4123                 msr &= 0x1fff;
4124                 if (type & MSR_TYPE_R)
4125                         /* read-high */
4126                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4127
4128                 if (type & MSR_TYPE_W)
4129                         /* write-high */
4130                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4131
4132         }
4133 }
4134
4135 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4136                                                 u32 msr, int type)
4137 {
4138         int f = sizeof(unsigned long);
4139
4140         if (!cpu_has_vmx_msr_bitmap())
4141                 return;
4142
4143         /*
4144          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4145          * have the write-low and read-high bitmap offsets the wrong way round.
4146          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4147          */
4148         if (msr <= 0x1fff) {
4149                 if (type & MSR_TYPE_R)
4150                         /* read-low */
4151                         __set_bit(msr, msr_bitmap + 0x000 / f);
4152
4153                 if (type & MSR_TYPE_W)
4154                         /* write-low */
4155                         __set_bit(msr, msr_bitmap + 0x800 / f);
4156
4157         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4158                 msr &= 0x1fff;
4159                 if (type & MSR_TYPE_R)
4160                         /* read-high */
4161                         __set_bit(msr, msr_bitmap + 0x400 / f);
4162
4163                 if (type & MSR_TYPE_W)
4164                         /* write-high */
4165                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4166
4167         }
4168 }
4169
4170 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4171 {
4172         if (!longmode_only)
4173                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4174                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4175         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4176                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4177 }
4178
4179 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4180 {
4181         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4182                         msr, MSR_TYPE_R);
4183         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4184                         msr, MSR_TYPE_R);
4185 }
4186
4187 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4188 {
4189         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4190                         msr, MSR_TYPE_R);
4191         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4192                         msr, MSR_TYPE_R);
4193 }
4194
4195 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4196 {
4197         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4198                         msr, MSR_TYPE_W);
4199         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4200                         msr, MSR_TYPE_W);
4201 }
4202
4203 static int vmx_vm_has_apicv(struct kvm *kvm)
4204 {
4205         return enable_apicv && irqchip_in_kernel(kvm);
4206 }
4207
4208 /*
4209  * Send interrupt to vcpu via posted interrupt way.
4210  * 1. If target vcpu is running(non-root mode), send posted interrupt
4211  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4212  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4213  * interrupt from PIR in next vmentry.
4214  */
4215 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4216 {
4217         struct vcpu_vmx *vmx = to_vmx(vcpu);
4218         int r;
4219
4220         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4221                 return;
4222
4223         r = pi_test_and_set_on(&vmx->pi_desc);
4224         kvm_make_request(KVM_REQ_EVENT, vcpu);
4225 #ifdef CONFIG_SMP
4226         if (!r && (vcpu->mode == IN_GUEST_MODE))
4227                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4228                                 POSTED_INTR_VECTOR);
4229         else
4230 #endif
4231                 kvm_vcpu_kick(vcpu);
4232 }
4233
4234 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4235 {
4236         struct vcpu_vmx *vmx = to_vmx(vcpu);
4237
4238         if (!pi_test_and_clear_on(&vmx->pi_desc))
4239                 return;
4240
4241         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4242 }
4243
4244 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4245 {
4246         return;
4247 }
4248
4249 /*
4250  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4251  * will not change in the lifetime of the guest.
4252  * Note that host-state that does change is set elsewhere. E.g., host-state
4253  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4254  */
4255 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4256 {
4257         u32 low32, high32;
4258         unsigned long tmpl;
4259         struct desc_ptr dt;
4260
4261         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4262         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
4263         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4264
4265         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4266 #ifdef CONFIG_X86_64
4267         /*
4268          * Load null selectors, so we can avoid reloading them in
4269          * __vmx_load_host_state(), in case userspace uses the null selectors
4270          * too (the expected case).
4271          */
4272         vmcs_write16(HOST_DS_SELECTOR, 0);
4273         vmcs_write16(HOST_ES_SELECTOR, 0);
4274 #else
4275         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4276         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4277 #endif
4278         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4279         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4280
4281         native_store_idt(&dt);
4282         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4283         vmx->host_idt_base = dt.address;
4284
4285         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4286
4287         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4288         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4289         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4290         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4291
4292         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4293                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4294                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4295         }
4296 }
4297
4298 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4299 {
4300         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4301         if (enable_ept)
4302                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4303         if (is_guest_mode(&vmx->vcpu))
4304                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4305                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4306         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4307 }
4308
4309 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4310 {
4311         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4312
4313         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4314                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4315         return pin_based_exec_ctrl;
4316 }
4317
4318 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4319 {
4320         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4321
4322         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4323                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4324
4325         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4326                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4327 #ifdef CONFIG_X86_64
4328                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4329                                 CPU_BASED_CR8_LOAD_EXITING;
4330 #endif
4331         }
4332         if (!enable_ept)
4333                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4334                                 CPU_BASED_CR3_LOAD_EXITING  |
4335                                 CPU_BASED_INVLPG_EXITING;
4336         return exec_control;
4337 }
4338
4339 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4340 {
4341         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4342         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4343                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4344         if (vmx->vpid == 0)
4345                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4346         if (!enable_ept) {
4347                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4348                 enable_unrestricted_guest = 0;
4349                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4350                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4351         }
4352         if (!enable_unrestricted_guest)
4353                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4354         if (!ple_gap)
4355                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4356         if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4357                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4358                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4359         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4360         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4361            (handle_vmptrld).
4362            We can NOT enable shadow_vmcs here because we don't have yet
4363            a current VMCS12
4364         */
4365         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4366         return exec_control;
4367 }
4368
4369 static void ept_set_mmio_spte_mask(void)
4370 {
4371         /*
4372          * EPT Misconfigurations can be generated if the value of bits 2:0
4373          * of an EPT paging-structure entry is 110b (write/execute).
4374          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4375          * spte.
4376          */
4377         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4378 }
4379
4380 /*
4381  * Sets up the vmcs for emulated real mode.
4382  */
4383 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4384 {
4385 #ifdef CONFIG_X86_64
4386         unsigned long a;
4387 #endif
4388         int i;
4389
4390         /* I/O */
4391         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4392         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4393
4394         if (enable_shadow_vmcs) {
4395                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4396                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4397         }
4398         if (cpu_has_vmx_msr_bitmap())
4399                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4400
4401         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4402
4403         /* Control */
4404         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4405
4406         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4407
4408         if (cpu_has_secondary_exec_ctrls()) {
4409                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4410                                 vmx_secondary_exec_control(vmx));
4411         }
4412
4413         if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
4414                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4415                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4416                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4417                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4418
4419                 vmcs_write16(GUEST_INTR_STATUS, 0);
4420
4421                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4422                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4423         }
4424
4425         if (ple_gap) {
4426                 vmcs_write32(PLE_GAP, ple_gap);
4427                 vmx->ple_window = ple_window;
4428                 vmx->ple_window_dirty = true;
4429         }
4430
4431         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4432         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4433         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4434
4435         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4436         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4437         vmx_set_constant_host_state(vmx);
4438 #ifdef CONFIG_X86_64
4439         rdmsrl(MSR_FS_BASE, a);
4440         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4441         rdmsrl(MSR_GS_BASE, a);
4442         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4443 #else
4444         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4445         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4446 #endif
4447
4448         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4449         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4450         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4451         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4452         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4453
4454         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4455                 u32 msr_low, msr_high;
4456                 u64 host_pat;
4457                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4458                 host_pat = msr_low | ((u64) msr_high << 32);
4459                 /* Write the default value follow host pat */
4460                 vmcs_write64(GUEST_IA32_PAT, host_pat);
4461                 /* Keep arch.pat sync with GUEST_IA32_PAT */
4462                 vmx->vcpu.arch.pat = host_pat;
4463         }
4464
4465         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4466                 u32 index = vmx_msr_index[i];
4467                 u32 data_low, data_high;
4468                 int j = vmx->nmsrs;
4469
4470                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4471                         continue;
4472                 if (wrmsr_safe(index, data_low, data_high) < 0)
4473                         continue;
4474                 vmx->guest_msrs[j].index = i;
4475                 vmx->guest_msrs[j].data = 0;
4476                 vmx->guest_msrs[j].mask = -1ull;
4477                 ++vmx->nmsrs;
4478         }
4479
4480
4481         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4482
4483         /* 22.2.1, 20.8.1 */
4484         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4485
4486         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4487         set_cr4_guest_host_mask(vmx);
4488
4489         return 0;
4490 }
4491
4492 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4493 {
4494         struct vcpu_vmx *vmx = to_vmx(vcpu);
4495         struct msr_data apic_base_msr;
4496
4497         vmx->rmode.vm86_active = 0;
4498
4499         vmx->soft_vnmi_blocked = 0;
4500
4501         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4502         kvm_set_cr8(&vmx->vcpu, 0);
4503         apic_base_msr.data = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
4504         if (kvm_vcpu_is_bsp(&vmx->vcpu))
4505                 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4506         apic_base_msr.host_initiated = true;
4507         kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
4508
4509         vmx_segment_cache_clear(vmx);
4510
4511         seg_setup(VCPU_SREG_CS);
4512         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4513         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4514
4515         seg_setup(VCPU_SREG_DS);
4516         seg_setup(VCPU_SREG_ES);
4517         seg_setup(VCPU_SREG_FS);
4518         seg_setup(VCPU_SREG_GS);
4519         seg_setup(VCPU_SREG_SS);
4520
4521         vmcs_write16(GUEST_TR_SELECTOR, 0);
4522         vmcs_writel(GUEST_TR_BASE, 0);
4523         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4524         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4525
4526         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4527         vmcs_writel(GUEST_LDTR_BASE, 0);
4528         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4529         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4530
4531         vmcs_write32(GUEST_SYSENTER_CS, 0);
4532         vmcs_writel(GUEST_SYSENTER_ESP, 0);
4533         vmcs_writel(GUEST_SYSENTER_EIP, 0);
4534
4535         vmcs_writel(GUEST_RFLAGS, 0x02);
4536         kvm_rip_write(vcpu, 0xfff0);
4537
4538         vmcs_writel(GUEST_GDTR_BASE, 0);
4539         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4540
4541         vmcs_writel(GUEST_IDTR_BASE, 0);
4542         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4543
4544         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4545         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4546         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4547
4548         /* Special registers */
4549         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4550
4551         setup_msrs(vmx);
4552
4553         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4554
4555         if (cpu_has_vmx_tpr_shadow()) {
4556                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4557                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4558                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4559                                      __pa(vmx->vcpu.arch.apic->regs));
4560                 vmcs_write32(TPR_THRESHOLD, 0);
4561         }
4562
4563         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4564                 vmcs_write64(APIC_ACCESS_ADDR,
4565                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4566
4567         if (vmx_vm_has_apicv(vcpu->kvm))
4568                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4569
4570         if (vmx->vpid != 0)
4571                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4572
4573         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4574         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4575         vmx_set_cr4(&vmx->vcpu, 0);
4576         vmx_set_efer(&vmx->vcpu, 0);
4577         vmx_fpu_activate(&vmx->vcpu);
4578         update_exception_bitmap(&vmx->vcpu);
4579
4580         vpid_sync_context(vmx);
4581 }
4582
4583 /*
4584  * In nested virtualization, check if L1 asked to exit on external interrupts.
4585  * For most existing hypervisors, this will always return true.
4586  */
4587 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4588 {
4589         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4590                 PIN_BASED_EXT_INTR_MASK;
4591 }
4592
4593 /*
4594  * In nested virtualization, check if L1 has set
4595  * VM_EXIT_ACK_INTR_ON_EXIT
4596  */
4597 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4598 {
4599         return get_vmcs12(vcpu)->vm_exit_controls &
4600                 VM_EXIT_ACK_INTR_ON_EXIT;
4601 }
4602
4603 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4604 {
4605         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4606                 PIN_BASED_NMI_EXITING;
4607 }
4608
4609 static void enable_irq_window(struct kvm_vcpu *vcpu)
4610 {
4611         u32 cpu_based_vm_exec_control;
4612
4613         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4614         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4615         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4616 }
4617
4618 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4619 {
4620         u32 cpu_based_vm_exec_control;
4621
4622         if (!cpu_has_virtual_nmis() ||
4623             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4624                 enable_irq_window(vcpu);
4625                 return;
4626         }
4627
4628         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4629         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4630         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4631 }
4632
4633 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4634 {
4635         struct vcpu_vmx *vmx = to_vmx(vcpu);
4636         uint32_t intr;
4637         int irq = vcpu->arch.interrupt.nr;
4638
4639         trace_kvm_inj_virq(irq);
4640
4641         ++vcpu->stat.irq_injections;
4642         if (vmx->rmode.vm86_active) {
4643                 int inc_eip = 0;
4644                 if (vcpu->arch.interrupt.soft)
4645                         inc_eip = vcpu->arch.event_exit_inst_len;
4646                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4647                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4648                 return;
4649         }
4650         intr = irq | INTR_INFO_VALID_MASK;
4651         if (vcpu->arch.interrupt.soft) {
4652                 intr |= INTR_TYPE_SOFT_INTR;
4653                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4654                              vmx->vcpu.arch.event_exit_inst_len);
4655         } else
4656                 intr |= INTR_TYPE_EXT_INTR;
4657         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4658 }
4659
4660 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4661 {
4662         struct vcpu_vmx *vmx = to_vmx(vcpu);
4663
4664         if (is_guest_mode(vcpu))
4665                 return;
4666
4667         if (!cpu_has_virtual_nmis()) {
4668                 /*
4669                  * Tracking the NMI-blocked state in software is built upon
4670                  * finding the next open IRQ window. This, in turn, depends on
4671                  * well-behaving guests: They have to keep IRQs disabled at
4672                  * least as long as the NMI handler runs. Otherwise we may
4673                  * cause NMI nesting, maybe breaking the guest. But as this is
4674                  * highly unlikely, we can live with the residual risk.
4675                  */
4676                 vmx->soft_vnmi_blocked = 1;
4677                 vmx->vnmi_blocked_time = 0;
4678         }
4679
4680         ++vcpu->stat.nmi_injections;
4681         vmx->nmi_known_unmasked = false;
4682         if (vmx->rmode.vm86_active) {
4683                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4684                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4685                 return;
4686         }
4687         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4688                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4689 }
4690
4691 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4692 {
4693         if (!cpu_has_virtual_nmis())
4694                 return to_vmx(vcpu)->soft_vnmi_blocked;
4695         if (to_vmx(vcpu)->nmi_known_unmasked)
4696                 return false;
4697         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4698 }
4699
4700 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4701 {
4702         struct vcpu_vmx *vmx = to_vmx(vcpu);
4703
4704         if (!cpu_has_virtual_nmis()) {
4705                 if (vmx->soft_vnmi_blocked != masked) {
4706                         vmx->soft_vnmi_blocked = masked;
4707                         vmx->vnmi_blocked_time = 0;
4708                 }
4709         } else {
4710                 vmx->nmi_known_unmasked = !masked;
4711                 if (masked)
4712                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4713                                       GUEST_INTR_STATE_NMI);
4714                 else
4715                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4716                                         GUEST_INTR_STATE_NMI);
4717         }
4718 }
4719
4720 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4721 {
4722         if (to_vmx(vcpu)->nested.nested_run_pending)
4723                 return 0;
4724
4725         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4726                 return 0;
4727
4728         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4729                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4730                    | GUEST_INTR_STATE_NMI));
4731 }
4732
4733 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4734 {
4735         return (!to_vmx(vcpu)->nested.nested_run_pending &&
4736                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4737                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4738                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4739 }
4740
4741 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4742 {
4743         int ret;
4744         struct kvm_userspace_memory_region tss_mem = {
4745                 .slot = TSS_PRIVATE_MEMSLOT,
4746                 .guest_phys_addr = addr,
4747                 .memory_size = PAGE_SIZE * 3,
4748                 .flags = 0,
4749         };
4750
4751         ret = kvm_set_memory_region(kvm, &tss_mem);
4752         if (ret)
4753                 return ret;
4754         kvm->arch.tss_addr = addr;
4755         if (!init_rmode_tss(kvm))
4756                 return  -ENOMEM;
4757
4758         return 0;
4759 }
4760
4761 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
4762 {
4763         switch (vec) {
4764         case BP_VECTOR:
4765                 /*
4766                  * Update instruction length as we may reinject the exception
4767                  * from user space while in guest debugging mode.
4768                  */
4769                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4770                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4771                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4772                         return false;
4773                 /* fall through */
4774         case DB_VECTOR:
4775                 if (vcpu->guest_debug &
4776                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4777                         return false;
4778                 /* fall through */
4779         case DE_VECTOR:
4780         case OF_VECTOR:
4781         case BR_VECTOR:
4782         case UD_VECTOR:
4783         case DF_VECTOR:
4784         case SS_VECTOR:
4785         case GP_VECTOR:
4786         case MF_VECTOR:
4787                 return true;
4788         break;
4789         }
4790         return false;
4791 }
4792
4793 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4794                                   int vec, u32 err_code)
4795 {
4796         /*
4797          * Instruction with address size override prefix opcode 0x67
4798          * Cause the #SS fault with 0 error code in VM86 mode.
4799          */
4800         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4801                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4802                         if (vcpu->arch.halt_request) {
4803                                 vcpu->arch.halt_request = 0;
4804                                 return kvm_emulate_halt(vcpu);
4805                         }
4806                         return 1;
4807                 }
4808                 return 0;
4809         }
4810
4811         /*
4812          * Forward all other exceptions that are valid in real mode.
4813          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4814          *        the required debugging infrastructure rework.
4815          */
4816         kvm_queue_exception(vcpu, vec);
4817         return 1;
4818 }
4819
4820 /*
4821  * Trigger machine check on the host. We assume all the MSRs are already set up
4822  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4823  * We pass a fake environment to the machine check handler because we want
4824  * the guest to be always treated like user space, no matter what context
4825  * it used internally.
4826  */
4827 static void kvm_machine_check(void)
4828 {
4829 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4830         struct pt_regs regs = {
4831                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4832                 .flags = X86_EFLAGS_IF,
4833         };
4834
4835         do_machine_check(&regs, 0);
4836 #endif
4837 }
4838
4839 static int handle_machine_check(struct kvm_vcpu *vcpu)
4840 {
4841         /* already handled by vcpu_run */
4842         return 1;
4843 }
4844
4845 static int handle_exception(struct kvm_vcpu *vcpu)
4846 {
4847         struct vcpu_vmx *vmx = to_vmx(vcpu);
4848         struct kvm_run *kvm_run = vcpu->run;
4849         u32 intr_info, ex_no, error_code;
4850         unsigned long cr2, rip, dr6;
4851         u32 vect_info;
4852         enum emulation_result er;
4853
4854         vect_info = vmx->idt_vectoring_info;
4855         intr_info = vmx->exit_intr_info;
4856
4857         if (is_machine_check(intr_info))
4858                 return handle_machine_check(vcpu);
4859
4860         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4861                 return 1;  /* already handled by vmx_vcpu_run() */
4862
4863         if (is_no_device(intr_info)) {
4864                 vmx_fpu_activate(vcpu);
4865                 return 1;
4866         }
4867
4868         if (is_invalid_opcode(intr_info)) {
4869                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4870                 if (er != EMULATE_DONE)
4871                         kvm_queue_exception(vcpu, UD_VECTOR);
4872                 return 1;
4873         }
4874
4875         error_code = 0;
4876         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4877                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4878
4879         /*
4880          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4881          * MMIO, it is better to report an internal error.
4882          * See the comments in vmx_handle_exit.
4883          */
4884         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4885             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4886                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4887                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4888                 vcpu->run->internal.ndata = 2;
4889                 vcpu->run->internal.data[0] = vect_info;
4890                 vcpu->run->internal.data[1] = intr_info;
4891                 return 0;
4892         }
4893
4894         if (is_page_fault(intr_info)) {
4895                 /* EPT won't cause page fault directly */
4896                 BUG_ON(enable_ept);
4897                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4898                 trace_kvm_page_fault(cr2, error_code);
4899
4900                 if (kvm_event_needs_reinjection(vcpu))
4901                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4902                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4903         }
4904
4905         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4906
4907         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4908                 return handle_rmode_exception(vcpu, ex_no, error_code);
4909
4910         switch (ex_no) {
4911         case DB_VECTOR:
4912                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4913                 if (!(vcpu->guest_debug &
4914                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4915                         vcpu->arch.dr6 &= ~15;
4916                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
4917                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
4918                                 skip_emulated_instruction(vcpu);
4919
4920                         kvm_queue_exception(vcpu, DB_VECTOR);
4921                         return 1;
4922                 }
4923                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4924                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4925                 /* fall through */
4926         case BP_VECTOR:
4927                 /*
4928                  * Update instruction length as we may reinject #BP from
4929                  * user space while in guest debugging mode. Reading it for
4930                  * #DB as well causes no harm, it is not used in that case.
4931                  */
4932                 vmx->vcpu.arch.event_exit_inst_len =
4933                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4934                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4935                 rip = kvm_rip_read(vcpu);
4936                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4937                 kvm_run->debug.arch.exception = ex_no;
4938                 break;
4939         default:
4940                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4941                 kvm_run->ex.exception = ex_no;
4942                 kvm_run->ex.error_code = error_code;
4943                 break;
4944         }
4945         return 0;
4946 }
4947
4948 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4949 {
4950         ++vcpu->stat.irq_exits;
4951         return 1;
4952 }
4953
4954 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4955 {
4956         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4957         return 0;
4958 }
4959
4960 static int handle_io(struct kvm_vcpu *vcpu)
4961 {
4962         unsigned long exit_qualification;
4963         int size, in, string;
4964         unsigned port;
4965
4966         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4967         string = (exit_qualification & 16) != 0;
4968         in = (exit_qualification & 8) != 0;
4969
4970         ++vcpu->stat.io_exits;
4971
4972         if (string || in)
4973                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4974
4975         port = exit_qualification >> 16;
4976         size = (exit_qualification & 7) + 1;
4977         skip_emulated_instruction(vcpu);
4978
4979         return kvm_fast_pio_out(vcpu, size, port);
4980 }
4981
4982 static void
4983 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4984 {
4985         /*
4986          * Patch in the VMCALL instruction:
4987          */
4988         hypercall[0] = 0x0f;
4989         hypercall[1] = 0x01;
4990         hypercall[2] = 0xc1;
4991 }
4992
4993 static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4994 {
4995         unsigned long always_on = VMXON_CR0_ALWAYSON;
4996
4997         if (nested_vmx_secondary_ctls_high &
4998                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4999             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5000                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5001         return (val & always_on) == always_on;
5002 }
5003
5004 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5005 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5006 {
5007         if (is_guest_mode(vcpu)) {
5008                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5009                 unsigned long orig_val = val;
5010
5011                 /*
5012                  * We get here when L2 changed cr0 in a way that did not change
5013                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5014                  * but did change L0 shadowed bits. So we first calculate the
5015                  * effective cr0 value that L1 would like to write into the
5016                  * hardware. It consists of the L2-owned bits from the new
5017                  * value combined with the L1-owned bits from L1's guest_cr0.
5018                  */
5019                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5020                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5021
5022                 if (!nested_cr0_valid(vmcs12, val))
5023                         return 1;
5024
5025                 if (kvm_set_cr0(vcpu, val))
5026                         return 1;
5027                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5028                 return 0;
5029         } else {
5030                 if (to_vmx(vcpu)->nested.vmxon &&
5031                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5032                         return 1;
5033                 return kvm_set_cr0(vcpu, val);
5034         }
5035 }
5036
5037 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5038 {
5039         if (is_guest_mode(vcpu)) {
5040                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5041                 unsigned long orig_val = val;
5042
5043                 /* analogously to handle_set_cr0 */
5044                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5045                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5046                 if (kvm_set_cr4(vcpu, val))
5047                         return 1;
5048                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5049                 return 0;
5050         } else
5051                 return kvm_set_cr4(vcpu, val);
5052 }
5053
5054 /* called to set cr0 as approriate for clts instruction exit. */
5055 static void handle_clts(struct kvm_vcpu *vcpu)
5056 {
5057         if (is_guest_mode(vcpu)) {
5058                 /*
5059                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5060                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5061                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5062                  */
5063                 vmcs_writel(CR0_READ_SHADOW,
5064                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5065                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5066         } else
5067                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5068 }
5069
5070 static int handle_cr(struct kvm_vcpu *vcpu)
5071 {
5072         unsigned long exit_qualification, val;
5073         int cr;
5074         int reg;
5075         int err;
5076
5077         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5078         cr = exit_qualification & 15;
5079         reg = (exit_qualification >> 8) & 15;
5080         switch ((exit_qualification >> 4) & 3) {
5081         case 0: /* mov to cr */
5082                 val = kvm_register_readl(vcpu, reg);
5083                 trace_kvm_cr_write(cr, val);
5084                 switch (cr) {
5085                 case 0:
5086                         err = handle_set_cr0(vcpu, val);
5087                         kvm_complete_insn_gp(vcpu, err);
5088                         return 1;
5089                 case 3:
5090                         err = kvm_set_cr3(vcpu, val);
5091                         kvm_complete_insn_gp(vcpu, err);
5092                         return 1;
5093                 case 4:
5094                         err = handle_set_cr4(vcpu, val);
5095                         kvm_complete_insn_gp(vcpu, err);
5096                         return 1;
5097                 case 8: {
5098                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5099                                 u8 cr8 = (u8)val;
5100                                 err = kvm_set_cr8(vcpu, cr8);
5101                                 kvm_complete_insn_gp(vcpu, err);
5102                                 if (irqchip_in_kernel(vcpu->kvm))
5103                                         return 1;
5104                                 if (cr8_prev <= cr8)
5105                                         return 1;
5106                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5107                                 return 0;
5108                         }
5109                 }
5110                 break;
5111         case 2: /* clts */
5112                 handle_clts(vcpu);
5113                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5114                 skip_emulated_instruction(vcpu);
5115                 vmx_fpu_activate(vcpu);
5116                 return 1;
5117         case 1: /*mov from cr*/
5118                 switch (cr) {
5119                 case 3:
5120                         val = kvm_read_cr3(vcpu);
5121                         kvm_register_write(vcpu, reg, val);
5122                         trace_kvm_cr_read(cr, val);
5123                         skip_emulated_instruction(vcpu);
5124                         return 1;
5125                 case 8:
5126                         val = kvm_get_cr8(vcpu);
5127                         kvm_register_write(vcpu, reg, val);
5128                         trace_kvm_cr_read(cr, val);
5129                         skip_emulated_instruction(vcpu);
5130                         return 1;
5131                 }
5132                 break;
5133         case 3: /* lmsw */
5134                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5135                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5136                 kvm_lmsw(vcpu, val);
5137
5138                 skip_emulated_instruction(vcpu);
5139                 return 1;
5140         default:
5141                 break;
5142         }
5143         vcpu->run->exit_reason = 0;
5144         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5145                (int)(exit_qualification >> 4) & 3, cr);
5146         return 0;
5147 }
5148
5149 static int handle_dr(struct kvm_vcpu *vcpu)
5150 {
5151         unsigned long exit_qualification;
5152         int dr, reg;
5153
5154         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5155         if (!kvm_require_cpl(vcpu, 0))
5156                 return 1;
5157         dr = vmcs_readl(GUEST_DR7);
5158         if (dr & DR7_GD) {
5159                 /*
5160                  * As the vm-exit takes precedence over the debug trap, we
5161                  * need to emulate the latter, either for the host or the
5162                  * guest debugging itself.
5163                  */
5164                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5165                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5166                         vcpu->run->debug.arch.dr7 = dr;
5167                         vcpu->run->debug.arch.pc =
5168                                 vmcs_readl(GUEST_CS_BASE) +
5169                                 vmcs_readl(GUEST_RIP);
5170                         vcpu->run->debug.arch.exception = DB_VECTOR;
5171                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5172                         return 0;
5173                 } else {
5174                         vcpu->arch.dr7 &= ~DR7_GD;
5175                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5176                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5177                         kvm_queue_exception(vcpu, DB_VECTOR);
5178                         return 1;
5179                 }
5180         }
5181
5182         if (vcpu->guest_debug == 0) {
5183                 u32 cpu_based_vm_exec_control;
5184
5185                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5186                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5187                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5188
5189                 /*
5190                  * No more DR vmexits; force a reload of the debug registers
5191                  * and reenter on this instruction.  The next vmexit will
5192                  * retrieve the full state of the debug registers.
5193                  */
5194                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5195                 return 1;
5196         }
5197
5198         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5199         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5200         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5201         if (exit_qualification & TYPE_MOV_FROM_DR) {
5202                 unsigned long val;
5203
5204                 if (kvm_get_dr(vcpu, dr, &val))
5205                         return 1;
5206                 kvm_register_write(vcpu, reg, val);
5207         } else
5208                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5209                         return 1;
5210
5211         skip_emulated_instruction(vcpu);
5212         return 1;
5213 }
5214
5215 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5216 {
5217         return vcpu->arch.dr6;
5218 }
5219
5220 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5221 {
5222 }
5223
5224 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5225 {
5226         u32 cpu_based_vm_exec_control;
5227
5228         get_debugreg(vcpu->arch.db[0], 0);
5229         get_debugreg(vcpu->arch.db[1], 1);
5230         get_debugreg(vcpu->arch.db[2], 2);
5231         get_debugreg(vcpu->arch.db[3], 3);
5232         get_debugreg(vcpu->arch.dr6, 6);
5233         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5234
5235         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5236
5237         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5238         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5239         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5240 }
5241
5242 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5243 {
5244         vmcs_writel(GUEST_DR7, val);
5245 }
5246
5247 static int handle_cpuid(struct kvm_vcpu *vcpu)
5248 {
5249         kvm_emulate_cpuid(vcpu);
5250         return 1;
5251 }
5252
5253 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5254 {
5255         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5256         u64 data;
5257
5258         if (vmx_get_msr(vcpu, ecx, &data)) {
5259                 trace_kvm_msr_read_ex(ecx);
5260                 kvm_inject_gp(vcpu, 0);
5261                 return 1;
5262         }
5263
5264         trace_kvm_msr_read(ecx, data);
5265
5266         /* FIXME: handling of bits 32:63 of rax, rdx */
5267         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5268         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
5269         skip_emulated_instruction(vcpu);
5270         return 1;
5271 }
5272
5273 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5274 {
5275         struct msr_data msr;
5276         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5277         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5278                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5279
5280         msr.data = data;
5281         msr.index = ecx;
5282         msr.host_initiated = false;
5283         if (vmx_set_msr(vcpu, &msr) != 0) {
5284                 trace_kvm_msr_write_ex(ecx, data);
5285                 kvm_inject_gp(vcpu, 0);
5286                 return 1;
5287         }
5288
5289         trace_kvm_msr_write(ecx, data);
5290         skip_emulated_instruction(vcpu);
5291         return 1;
5292 }
5293
5294 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5295 {
5296         kvm_make_request(KVM_REQ_EVENT, vcpu);
5297         return 1;
5298 }
5299
5300 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5301 {
5302         u32 cpu_based_vm_exec_control;
5303
5304         /* clear pending irq */
5305         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5306         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5307         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5308
5309         kvm_make_request(KVM_REQ_EVENT, vcpu);
5310
5311         ++vcpu->stat.irq_window_exits;
5312
5313         /*
5314          * If the user space waits to inject interrupts, exit as soon as
5315          * possible
5316          */
5317         if (!irqchip_in_kernel(vcpu->kvm) &&
5318             vcpu->run->request_interrupt_window &&
5319             !kvm_cpu_has_interrupt(vcpu)) {
5320                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
5321                 return 0;
5322         }
5323         return 1;
5324 }
5325
5326 static int handle_halt(struct kvm_vcpu *vcpu)
5327 {
5328         skip_emulated_instruction(vcpu);
5329         return kvm_emulate_halt(vcpu);
5330 }
5331
5332 static int handle_vmcall(struct kvm_vcpu *vcpu)
5333 {
5334         skip_emulated_instruction(vcpu);
5335         kvm_emulate_hypercall(vcpu);
5336         return 1;
5337 }
5338
5339 static int handle_invd(struct kvm_vcpu *vcpu)
5340 {
5341         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5342 }
5343
5344 static int handle_invlpg(struct kvm_vcpu *vcpu)
5345 {
5346         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5347
5348         kvm_mmu_invlpg(vcpu, exit_qualification);
5349         skip_emulated_instruction(vcpu);
5350         return 1;
5351 }
5352
5353 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5354 {
5355         int err;
5356
5357         err = kvm_rdpmc(vcpu);
5358         kvm_complete_insn_gp(vcpu, err);
5359
5360         return 1;
5361 }
5362
5363 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5364 {
5365         skip_emulated_instruction(vcpu);
5366         kvm_emulate_wbinvd(vcpu);
5367         return 1;
5368 }
5369
5370 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5371 {
5372         u64 new_bv = kvm_read_edx_eax(vcpu);
5373         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5374
5375         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5376                 skip_emulated_instruction(vcpu);
5377         return 1;
5378 }
5379
5380 static int handle_apic_access(struct kvm_vcpu *vcpu)
5381 {
5382         if (likely(fasteoi)) {
5383                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5384                 int access_type, offset;
5385
5386                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5387                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5388                 /*
5389                  * Sane guest uses MOV to write EOI, with written value
5390                  * not cared. So make a short-circuit here by avoiding
5391                  * heavy instruction emulation.
5392                  */
5393                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5394                     (offset == APIC_EOI)) {
5395                         kvm_lapic_set_eoi(vcpu);
5396                         skip_emulated_instruction(vcpu);
5397                         return 1;
5398                 }
5399         }
5400         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5401 }
5402
5403 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5404 {
5405         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5406         int vector = exit_qualification & 0xff;
5407
5408         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5409         kvm_apic_set_eoi_accelerated(vcpu, vector);
5410         return 1;
5411 }
5412
5413 static int handle_apic_write(struct kvm_vcpu *vcpu)
5414 {
5415         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5416         u32 offset = exit_qualification & 0xfff;
5417
5418         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5419         kvm_apic_write_nodecode(vcpu, offset);
5420         return 1;
5421 }
5422
5423 static int handle_task_switch(struct kvm_vcpu *vcpu)
5424 {
5425         struct vcpu_vmx *vmx = to_vmx(vcpu);
5426         unsigned long exit_qualification;
5427         bool has_error_code = false;
5428         u32 error_code = 0;
5429         u16 tss_selector;
5430         int reason, type, idt_v, idt_index;
5431
5432         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5433         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5434         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5435
5436         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5437
5438         reason = (u32)exit_qualification >> 30;
5439         if (reason == TASK_SWITCH_GATE && idt_v) {
5440                 switch (type) {
5441                 case INTR_TYPE_NMI_INTR:
5442                         vcpu->arch.nmi_injected = false;
5443                         vmx_set_nmi_mask(vcpu, true);
5444                         break;
5445                 case INTR_TYPE_EXT_INTR:
5446                 case INTR_TYPE_SOFT_INTR:
5447                         kvm_clear_interrupt_queue(vcpu);
5448                         break;
5449                 case INTR_TYPE_HARD_EXCEPTION:
5450                         if (vmx->idt_vectoring_info &
5451                             VECTORING_INFO_DELIVER_CODE_MASK) {
5452                                 has_error_code = true;
5453                                 error_code =
5454                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5455                         }
5456                         /* fall through */
5457                 case INTR_TYPE_SOFT_EXCEPTION:
5458                         kvm_clear_exception_queue(vcpu);
5459                         break;
5460                 default:
5461                         break;
5462                 }
5463         }
5464         tss_selector = exit_qualification;
5465
5466         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5467                        type != INTR_TYPE_EXT_INTR &&
5468                        type != INTR_TYPE_NMI_INTR))
5469                 skip_emulated_instruction(vcpu);
5470
5471         if (kvm_task_switch(vcpu, tss_selector,
5472                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5473                             has_error_code, error_code) == EMULATE_FAIL) {
5474                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5475                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5476                 vcpu->run->internal.ndata = 0;
5477                 return 0;
5478         }
5479
5480         /* clear all local breakpoint enable flags */
5481         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x55);
5482
5483         /*
5484          * TODO: What about debug traps on tss switch?
5485          *       Are we supposed to inject them and update dr6?
5486          */
5487
5488         return 1;
5489 }
5490
5491 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5492 {
5493         unsigned long exit_qualification;
5494         gpa_t gpa;
5495         u32 error_code;
5496         int gla_validity;
5497
5498         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5499
5500         gla_validity = (exit_qualification >> 7) & 0x3;
5501         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5502                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5503                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5504                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5505                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5506                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5507                         (long unsigned int)exit_qualification);
5508                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5509                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5510                 return 0;
5511         }
5512
5513         /*
5514          * EPT violation happened while executing iret from NMI,
5515          * "blocked by NMI" bit has to be set before next VM entry.
5516          * There are errata that may cause this bit to not be set:
5517          * AAK134, BY25.
5518          */
5519         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5520                         cpu_has_virtual_nmis() &&
5521                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5522                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5523
5524         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5525         trace_kvm_page_fault(gpa, exit_qualification);
5526
5527         /* It is a write fault? */
5528         error_code = exit_qualification & (1U << 1);
5529         /* It is a fetch fault? */
5530         error_code |= (exit_qualification & (1U << 2)) << 2;
5531         /* ept page table is present? */
5532         error_code |= (exit_qualification >> 3) & 0x1;
5533
5534         vcpu->arch.exit_qualification = exit_qualification;
5535
5536         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5537 }
5538
5539 static u64 ept_rsvd_mask(u64 spte, int level)
5540 {
5541         int i;
5542         u64 mask = 0;
5543
5544         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5545                 mask |= (1ULL << i);
5546
5547         if (level == 4)
5548                 /* bits 7:3 reserved */
5549                 mask |= 0xf8;
5550         else if (spte & (1ULL << 7))
5551                 /*
5552                  * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5553                  * level == 1 if the hypervisor is using the ignored bit 7.
5554                  */
5555                 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5556         else if (level > 1)
5557                 /* bits 6:3 reserved */
5558                 mask |= 0x78;
5559
5560         return mask;
5561 }
5562
5563 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5564                                        int level)
5565 {
5566         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5567
5568         /* 010b (write-only) */
5569         WARN_ON((spte & 0x7) == 0x2);
5570
5571         /* 110b (write/execute) */
5572         WARN_ON((spte & 0x7) == 0x6);
5573
5574         /* 100b (execute-only) and value not supported by logical processor */
5575         if (!cpu_has_vmx_ept_execute_only())
5576                 WARN_ON((spte & 0x7) == 0x4);
5577
5578         /* not 000b */
5579         if ((spte & 0x7)) {
5580                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5581
5582                 if (rsvd_bits != 0) {
5583                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5584                                          __func__, rsvd_bits);
5585                         WARN_ON(1);
5586                 }
5587
5588                 /* bits 5:3 are _not_ reserved for large page or leaf page */
5589                 if ((rsvd_bits & 0x38) == 0) {
5590                         u64 ept_mem_type = (spte & 0x38) >> 3;
5591
5592                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
5593                             ept_mem_type == 7) {
5594                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5595                                                 __func__, ept_mem_type);
5596                                 WARN_ON(1);
5597                         }
5598                 }
5599         }
5600 }
5601
5602 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5603 {
5604         u64 sptes[4];
5605         int nr_sptes, i, ret;
5606         gpa_t gpa;
5607
5608         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5609         if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5610                 skip_emulated_instruction(vcpu);
5611                 return 1;
5612         }
5613
5614         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5615         if (likely(ret == RET_MMIO_PF_EMULATE))
5616                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5617                                               EMULATE_DONE;
5618
5619         if (unlikely(ret == RET_MMIO_PF_INVALID))
5620                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5621
5622         if (unlikely(ret == RET_MMIO_PF_RETRY))
5623                 return 1;
5624
5625         /* It is the real ept misconfig */
5626         printk(KERN_ERR "EPT: Misconfiguration.\n");
5627         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5628
5629         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5630
5631         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5632                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5633
5634         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5635         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5636
5637         return 0;
5638 }
5639
5640 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5641 {
5642         u32 cpu_based_vm_exec_control;
5643
5644         /* clear pending NMI */
5645         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5646         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5647         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5648         ++vcpu->stat.nmi_window_exits;
5649         kvm_make_request(KVM_REQ_EVENT, vcpu);
5650
5651         return 1;
5652 }
5653
5654 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5655 {
5656         struct vcpu_vmx *vmx = to_vmx(vcpu);
5657         enum emulation_result err = EMULATE_DONE;
5658         int ret = 1;
5659         u32 cpu_exec_ctrl;
5660         bool intr_window_requested;
5661         unsigned count = 130;
5662
5663         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5664         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5665
5666         while (vmx->emulation_required && count-- != 0) {
5667                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5668                         return handle_interrupt_window(&vmx->vcpu);
5669
5670                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5671                         return 1;
5672
5673                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5674
5675                 if (err == EMULATE_USER_EXIT) {
5676                         ++vcpu->stat.mmio_exits;
5677                         ret = 0;
5678                         goto out;
5679                 }
5680
5681                 if (err != EMULATE_DONE) {
5682                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5683                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5684                         vcpu->run->internal.ndata = 0;
5685                         return 0;
5686                 }
5687
5688                 if (vcpu->arch.halt_request) {
5689                         vcpu->arch.halt_request = 0;
5690                         ret = kvm_emulate_halt(vcpu);
5691                         goto out;
5692                 }
5693
5694                 if (signal_pending(current))
5695                         goto out;
5696                 if (need_resched())
5697                         schedule();
5698         }
5699
5700 out:
5701         return ret;
5702 }
5703
5704 static int __grow_ple_window(int val)
5705 {
5706         if (ple_window_grow < 1)
5707                 return ple_window;
5708
5709         val = min(val, ple_window_actual_max);
5710
5711         if (ple_window_grow < ple_window)
5712                 val *= ple_window_grow;
5713         else
5714                 val += ple_window_grow;
5715
5716         return val;
5717 }
5718
5719 static int __shrink_ple_window(int val, int modifier, int minimum)
5720 {
5721         if (modifier < 1)
5722                 return ple_window;
5723
5724         if (modifier < ple_window)
5725                 val /= modifier;
5726         else
5727                 val -= modifier;
5728
5729         return max(val, minimum);
5730 }
5731
5732 static void grow_ple_window(struct kvm_vcpu *vcpu)
5733 {
5734         struct vcpu_vmx *vmx = to_vmx(vcpu);
5735         int old = vmx->ple_window;
5736
5737         vmx->ple_window = __grow_ple_window(old);
5738
5739         if (vmx->ple_window != old)
5740                 vmx->ple_window_dirty = true;
5741
5742         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
5743 }
5744
5745 static void shrink_ple_window(struct kvm_vcpu *vcpu)
5746 {
5747         struct vcpu_vmx *vmx = to_vmx(vcpu);
5748         int old = vmx->ple_window;
5749
5750         vmx->ple_window = __shrink_ple_window(old,
5751                                               ple_window_shrink, ple_window);
5752
5753         if (vmx->ple_window != old)
5754                 vmx->ple_window_dirty = true;
5755
5756         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
5757 }
5758
5759 /*
5760  * ple_window_actual_max is computed to be one grow_ple_window() below
5761  * ple_window_max. (See __grow_ple_window for the reason.)
5762  * This prevents overflows, because ple_window_max is int.
5763  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5764  * this process.
5765  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5766  */
5767 static void update_ple_window_actual_max(void)
5768 {
5769         ple_window_actual_max =
5770                         __shrink_ple_window(max(ple_window_max, ple_window),
5771                                             ple_window_grow, INT_MIN);
5772 }
5773
5774 /*
5775  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5776  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5777  */
5778 static int handle_pause(struct kvm_vcpu *vcpu)
5779 {
5780         if (ple_gap)
5781                 grow_ple_window(vcpu);
5782
5783         skip_emulated_instruction(vcpu);
5784         kvm_vcpu_on_spin(vcpu);
5785
5786         return 1;
5787 }
5788
5789 static int handle_nop(struct kvm_vcpu *vcpu)
5790 {
5791         skip_emulated_instruction(vcpu);
5792         return 1;
5793 }
5794
5795 static int handle_mwait(struct kvm_vcpu *vcpu)
5796 {
5797         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5798         return handle_nop(vcpu);
5799 }
5800
5801 static int handle_monitor(struct kvm_vcpu *vcpu)
5802 {
5803         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5804         return handle_nop(vcpu);
5805 }
5806
5807 /*
5808  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5809  * We could reuse a single VMCS for all the L2 guests, but we also want the
5810  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5811  * allows keeping them loaded on the processor, and in the future will allow
5812  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5813  * every entry if they never change.
5814  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5815  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5816  *
5817  * The following functions allocate and free a vmcs02 in this pool.
5818  */
5819
5820 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5821 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5822 {
5823         struct vmcs02_list *item;
5824         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5825                 if (item->vmptr == vmx->nested.current_vmptr) {
5826                         list_move(&item->list, &vmx->nested.vmcs02_pool);
5827                         return &item->vmcs02;
5828                 }
5829
5830         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5831                 /* Recycle the least recently used VMCS. */
5832                 item = list_entry(vmx->nested.vmcs02_pool.prev,
5833                         struct vmcs02_list, list);
5834                 item->vmptr = vmx->nested.current_vmptr;
5835                 list_move(&item->list, &vmx->nested.vmcs02_pool);
5836                 return &item->vmcs02;
5837         }
5838
5839         /* Create a new VMCS */
5840         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5841         if (!item)
5842                 return NULL;
5843         item->vmcs02.vmcs = alloc_vmcs();
5844         if (!item->vmcs02.vmcs) {
5845                 kfree(item);
5846                 return NULL;
5847         }
5848         loaded_vmcs_init(&item->vmcs02);
5849         item->vmptr = vmx->nested.current_vmptr;
5850         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5851         vmx->nested.vmcs02_num++;
5852         return &item->vmcs02;
5853 }
5854
5855 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5856 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5857 {
5858         struct vmcs02_list *item;
5859         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5860                 if (item->vmptr == vmptr) {
5861                         free_loaded_vmcs(&item->vmcs02);
5862                         list_del(&item->list);
5863                         kfree(item);
5864                         vmx->nested.vmcs02_num--;
5865                         return;
5866                 }
5867 }
5868
5869 /*
5870  * Free all VMCSs saved for this vcpu, except the one pointed by
5871  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
5872  * must be &vmx->vmcs01.
5873  */
5874 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5875 {
5876         struct vmcs02_list *item, *n;
5877
5878         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
5879         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5880                 /*
5881                  * Something will leak if the above WARN triggers.  Better than
5882                  * a use-after-free.
5883                  */
5884                 if (vmx->loaded_vmcs == &item->vmcs02)
5885                         continue;
5886
5887                 free_loaded_vmcs(&item->vmcs02);
5888                 list_del(&item->list);
5889                 kfree(item);
5890                 vmx->nested.vmcs02_num--;
5891         }
5892 }
5893
5894 /*
5895  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5896  * set the success or error code of an emulated VMX instruction, as specified
5897  * by Vol 2B, VMX Instruction Reference, "Conventions".
5898  */
5899 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5900 {
5901         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5902                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5903                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5904 }
5905
5906 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5907 {
5908         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5909                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5910                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5911                         | X86_EFLAGS_CF);
5912 }
5913
5914 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5915                                         u32 vm_instruction_error)
5916 {
5917         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5918                 /*
5919                  * failValid writes the error number to the current VMCS, which
5920                  * can't be done there isn't a current VMCS.
5921                  */
5922                 nested_vmx_failInvalid(vcpu);
5923                 return;
5924         }
5925         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5926                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5927                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5928                         | X86_EFLAGS_ZF);
5929         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5930         /*
5931          * We don't need to force a shadow sync because
5932          * VM_INSTRUCTION_ERROR is not shadowed
5933          */
5934 }
5935
5936 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
5937 {
5938         struct vcpu_vmx *vmx =
5939                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
5940
5941         vmx->nested.preemption_timer_expired = true;
5942         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5943         kvm_vcpu_kick(&vmx->vcpu);
5944
5945         return HRTIMER_NORESTART;
5946 }
5947
5948 /*
5949  * Decode the memory-address operand of a vmx instruction, as recorded on an
5950  * exit caused by such an instruction (run by a guest hypervisor).
5951  * On success, returns 0. When the operand is invalid, returns 1 and throws
5952  * #UD or #GP.
5953  */
5954 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5955                                  unsigned long exit_qualification,
5956                                  u32 vmx_instruction_info, gva_t *ret)
5957 {
5958         /*
5959          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5960          * Execution", on an exit, vmx_instruction_info holds most of the
5961          * addressing components of the operand. Only the displacement part
5962          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5963          * For how an actual address is calculated from all these components,
5964          * refer to Vol. 1, "Operand Addressing".
5965          */
5966         int  scaling = vmx_instruction_info & 3;
5967         int  addr_size = (vmx_instruction_info >> 7) & 7;
5968         bool is_reg = vmx_instruction_info & (1u << 10);
5969         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5970         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5971         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5972         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5973         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5974
5975         if (is_reg) {
5976                 kvm_queue_exception(vcpu, UD_VECTOR);
5977                 return 1;
5978         }
5979
5980         /* Addr = segment_base + offset */
5981         /* offset = base + [index * scale] + displacement */
5982         *ret = vmx_get_segment_base(vcpu, seg_reg);
5983         if (base_is_valid)
5984                 *ret += kvm_register_read(vcpu, base_reg);
5985         if (index_is_valid)
5986                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5987         *ret += exit_qualification; /* holds the displacement */
5988
5989         if (addr_size == 1) /* 32 bit */
5990                 *ret &= 0xffffffff;
5991
5992         /*
5993          * TODO: throw #GP (and return 1) in various cases that the VM*
5994          * instructions require it - e.g., offset beyond segment limit,
5995          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5996          * address, and so on. Currently these are not checked.
5997          */
5998         return 0;
5999 }
6000
6001 /*
6002  * This function performs the various checks including
6003  * - if it's 4KB aligned
6004  * - No bits beyond the physical address width are set
6005  * - Returns 0 on success or else 1
6006  * (Intel SDM Section 30.3)
6007  */
6008 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6009                                   gpa_t *vmpointer)
6010 {
6011         gva_t gva;
6012         gpa_t vmptr;
6013         struct x86_exception e;
6014         struct page *page;
6015         struct vcpu_vmx *vmx = to_vmx(vcpu);
6016         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6017
6018         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6019                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6020                 return 1;
6021
6022         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6023                                 sizeof(vmptr), &e)) {
6024                 kvm_inject_page_fault(vcpu, &e);
6025                 return 1;
6026         }
6027
6028         switch (exit_reason) {
6029         case EXIT_REASON_VMON:
6030                 /*
6031                  * SDM 3: 24.11.5
6032                  * The first 4 bytes of VMXON region contain the supported
6033                  * VMCS revision identifier
6034                  *
6035                  * Note - IA32_VMX_BASIC[48] will never be 1
6036                  * for the nested case;
6037                  * which replaces physical address width with 32
6038                  *
6039                  */
6040                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6041                         nested_vmx_failInvalid(vcpu);
6042                         skip_emulated_instruction(vcpu);
6043                         return 1;
6044                 }
6045
6046                 page = nested_get_page(vcpu, vmptr);
6047                 if (page == NULL ||
6048                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6049                         nested_vmx_failInvalid(vcpu);
6050                         kunmap(page);
6051                         skip_emulated_instruction(vcpu);
6052                         return 1;
6053                 }
6054                 kunmap(page);
6055                 vmx->nested.vmxon_ptr = vmptr;
6056                 break;
6057         case EXIT_REASON_VMCLEAR:
6058                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6059                         nested_vmx_failValid(vcpu,
6060                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6061                         skip_emulated_instruction(vcpu);
6062                         return 1;
6063                 }
6064
6065                 if (vmptr == vmx->nested.vmxon_ptr) {
6066                         nested_vmx_failValid(vcpu,
6067                                              VMXERR_VMCLEAR_VMXON_POINTER);
6068                         skip_emulated_instruction(vcpu);
6069                         return 1;
6070                 }
6071                 break;
6072         case EXIT_REASON_VMPTRLD:
6073                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6074                         nested_vmx_failValid(vcpu,
6075                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6076                         skip_emulated_instruction(vcpu);
6077                         return 1;
6078                 }
6079
6080                 if (vmptr == vmx->nested.vmxon_ptr) {
6081                         nested_vmx_failValid(vcpu,
6082                                              VMXERR_VMCLEAR_VMXON_POINTER);
6083                         skip_emulated_instruction(vcpu);
6084                         return 1;
6085                 }
6086                 break;
6087         default:
6088                 return 1; /* shouldn't happen */
6089         }
6090
6091         if (vmpointer)
6092                 *vmpointer = vmptr;
6093         return 0;
6094 }
6095
6096 /*
6097  * Emulate the VMXON instruction.
6098  * Currently, we just remember that VMX is active, and do not save or even
6099  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6100  * do not currently need to store anything in that guest-allocated memory
6101  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6102  * argument is different from the VMXON pointer (which the spec says they do).
6103  */
6104 static int handle_vmon(struct kvm_vcpu *vcpu)
6105 {
6106         struct kvm_segment cs;
6107         struct vcpu_vmx *vmx = to_vmx(vcpu);
6108         struct vmcs *shadow_vmcs;
6109         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6110                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6111
6112         /* The Intel VMX Instruction Reference lists a bunch of bits that
6113          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6114          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6115          * Otherwise, we should fail with #UD. We test these now:
6116          */
6117         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6118             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6119             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6120                 kvm_queue_exception(vcpu, UD_VECTOR);
6121                 return 1;
6122         }
6123
6124         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6125         if (is_long_mode(vcpu) && !cs.l) {
6126                 kvm_queue_exception(vcpu, UD_VECTOR);
6127                 return 1;
6128         }
6129
6130         if (vmx_get_cpl(vcpu)) {
6131                 kvm_inject_gp(vcpu, 0);
6132                 return 1;
6133         }
6134
6135         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6136                 return 1;
6137
6138         if (vmx->nested.vmxon) {
6139                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6140                 skip_emulated_instruction(vcpu);
6141                 return 1;
6142         }
6143
6144         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6145                         != VMXON_NEEDED_FEATURES) {
6146                 kvm_inject_gp(vcpu, 0);
6147                 return 1;
6148         }
6149
6150         if (enable_shadow_vmcs) {
6151                 shadow_vmcs = alloc_vmcs();
6152                 if (!shadow_vmcs)
6153                         return -ENOMEM;
6154                 /* mark vmcs as shadow */
6155                 shadow_vmcs->revision_id |= (1u << 31);
6156                 /* init shadow vmcs */
6157                 vmcs_clear(shadow_vmcs);
6158                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6159         }
6160
6161         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6162         vmx->nested.vmcs02_num = 0;
6163
6164         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6165                      HRTIMER_MODE_REL);
6166         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6167
6168         vmx->nested.vmxon = true;
6169
6170         skip_emulated_instruction(vcpu);
6171         nested_vmx_succeed(vcpu);
6172         return 1;
6173 }
6174
6175 /*
6176  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6177  * for running VMX instructions (except VMXON, whose prerequisites are
6178  * slightly different). It also specifies what exception to inject otherwise.
6179  */
6180 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6181 {
6182         struct kvm_segment cs;
6183         struct vcpu_vmx *vmx = to_vmx(vcpu);
6184
6185         if (!vmx->nested.vmxon) {
6186                 kvm_queue_exception(vcpu, UD_VECTOR);
6187                 return 0;
6188         }
6189
6190         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6191         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6192             (is_long_mode(vcpu) && !cs.l)) {
6193                 kvm_queue_exception(vcpu, UD_VECTOR);
6194                 return 0;
6195         }
6196
6197         if (vmx_get_cpl(vcpu)) {
6198                 kvm_inject_gp(vcpu, 0);
6199                 return 0;
6200         }
6201
6202         return 1;
6203 }
6204
6205 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6206 {
6207         u32 exec_control;
6208         if (vmx->nested.current_vmptr == -1ull)
6209                 return;
6210
6211         /* current_vmptr and current_vmcs12 are always set/reset together */
6212         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6213                 return;
6214
6215         if (enable_shadow_vmcs) {
6216                 /* copy to memory all shadowed fields in case
6217                    they were modified */
6218                 copy_shadow_to_vmcs12(vmx);
6219                 vmx->nested.sync_shadow_vmcs = false;
6220                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6221                 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6222                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6223                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6224         }
6225         kunmap(vmx->nested.current_vmcs12_page);
6226         nested_release_page(vmx->nested.current_vmcs12_page);
6227         vmx->nested.current_vmptr = -1ull;
6228         vmx->nested.current_vmcs12 = NULL;
6229 }
6230
6231 /*
6232  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6233  * just stops using VMX.
6234  */
6235 static void free_nested(struct vcpu_vmx *vmx)
6236 {
6237         if (!vmx->nested.vmxon)
6238                 return;
6239
6240         vmx->nested.vmxon = false;
6241         nested_release_vmcs12(vmx);
6242         if (enable_shadow_vmcs)
6243                 free_vmcs(vmx->nested.current_shadow_vmcs);
6244         /* Unpin physical memory we referred to in current vmcs02 */
6245         if (vmx->nested.apic_access_page) {
6246                 nested_release_page(vmx->nested.apic_access_page);
6247                 vmx->nested.apic_access_page = 0;
6248         }
6249
6250         nested_free_all_saved_vmcss(vmx);
6251 }
6252
6253 /* Emulate the VMXOFF instruction */
6254 static int handle_vmoff(struct kvm_vcpu *vcpu)
6255 {
6256         if (!nested_vmx_check_permission(vcpu))
6257                 return 1;
6258         free_nested(to_vmx(vcpu));
6259         skip_emulated_instruction(vcpu);
6260         nested_vmx_succeed(vcpu);
6261         return 1;
6262 }
6263
6264 /* Emulate the VMCLEAR instruction */
6265 static int handle_vmclear(struct kvm_vcpu *vcpu)
6266 {
6267         struct vcpu_vmx *vmx = to_vmx(vcpu);
6268         gpa_t vmptr;
6269         struct vmcs12 *vmcs12;
6270         struct page *page;
6271
6272         if (!nested_vmx_check_permission(vcpu))
6273                 return 1;
6274
6275         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6276                 return 1;
6277
6278         if (vmptr == vmx->nested.current_vmptr)
6279                 nested_release_vmcs12(vmx);
6280
6281         page = nested_get_page(vcpu, vmptr);
6282         if (page == NULL) {
6283                 /*
6284                  * For accurate processor emulation, VMCLEAR beyond available
6285                  * physical memory should do nothing at all. However, it is
6286                  * possible that a nested vmx bug, not a guest hypervisor bug,
6287                  * resulted in this case, so let's shut down before doing any
6288                  * more damage:
6289                  */
6290                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6291                 return 1;
6292         }
6293         vmcs12 = kmap(page);
6294         vmcs12->launch_state = 0;
6295         kunmap(page);
6296         nested_release_page(page);
6297
6298         nested_free_vmcs02(vmx, vmptr);
6299
6300         skip_emulated_instruction(vcpu);
6301         nested_vmx_succeed(vcpu);
6302         return 1;
6303 }
6304
6305 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6306
6307 /* Emulate the VMLAUNCH instruction */
6308 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6309 {
6310         return nested_vmx_run(vcpu, true);
6311 }
6312
6313 /* Emulate the VMRESUME instruction */
6314 static int handle_vmresume(struct kvm_vcpu *vcpu)
6315 {
6316
6317         return nested_vmx_run(vcpu, false);
6318 }
6319
6320 enum vmcs_field_type {
6321         VMCS_FIELD_TYPE_U16 = 0,
6322         VMCS_FIELD_TYPE_U64 = 1,
6323         VMCS_FIELD_TYPE_U32 = 2,
6324         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6325 };
6326
6327 static inline int vmcs_field_type(unsigned long field)
6328 {
6329         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6330                 return VMCS_FIELD_TYPE_U32;
6331         return (field >> 13) & 0x3 ;
6332 }
6333
6334 static inline int vmcs_field_readonly(unsigned long field)
6335 {
6336         return (((field >> 10) & 0x3) == 1);
6337 }
6338
6339 /*
6340  * Read a vmcs12 field. Since these can have varying lengths and we return
6341  * one type, we chose the biggest type (u64) and zero-extend the return value
6342  * to that size. Note that the caller, handle_vmread, might need to use only
6343  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6344  * 64-bit fields are to be returned).
6345  */
6346 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6347                                         unsigned long field, u64 *ret)
6348 {
6349         short offset = vmcs_field_to_offset(field);
6350         char *p;
6351
6352         if (offset < 0)
6353                 return 0;
6354
6355         p = ((char *)(get_vmcs12(vcpu))) + offset;
6356
6357         switch (vmcs_field_type(field)) {
6358         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6359                 *ret = *((natural_width *)p);
6360                 return 1;
6361         case VMCS_FIELD_TYPE_U16:
6362                 *ret = *((u16 *)p);
6363                 return 1;
6364         case VMCS_FIELD_TYPE_U32:
6365                 *ret = *((u32 *)p);
6366                 return 1;
6367         case VMCS_FIELD_TYPE_U64:
6368                 *ret = *((u64 *)p);
6369                 return 1;
6370         default:
6371                 return 0; /* can never happen. */
6372         }
6373 }
6374
6375
6376 static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6377                                     unsigned long field, u64 field_value){
6378         short offset = vmcs_field_to_offset(field);
6379         char *p = ((char *) get_vmcs12(vcpu)) + offset;
6380         if (offset < 0)
6381                 return false;
6382
6383         switch (vmcs_field_type(field)) {
6384         case VMCS_FIELD_TYPE_U16:
6385                 *(u16 *)p = field_value;
6386                 return true;
6387         case VMCS_FIELD_TYPE_U32:
6388                 *(u32 *)p = field_value;
6389                 return true;
6390         case VMCS_FIELD_TYPE_U64:
6391                 *(u64 *)p = field_value;
6392                 return true;
6393         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6394                 *(natural_width *)p = field_value;
6395                 return true;
6396         default:
6397                 return false; /* can never happen. */
6398         }
6399
6400 }
6401
6402 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6403 {
6404         int i;
6405         unsigned long field;
6406         u64 field_value;
6407         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6408         const unsigned long *fields = shadow_read_write_fields;
6409         const int num_fields = max_shadow_read_write_fields;
6410
6411         vmcs_load(shadow_vmcs);
6412
6413         for (i = 0; i < num_fields; i++) {
6414                 field = fields[i];
6415                 switch (vmcs_field_type(field)) {
6416                 case VMCS_FIELD_TYPE_U16:
6417                         field_value = vmcs_read16(field);
6418                         break;
6419                 case VMCS_FIELD_TYPE_U32:
6420                         field_value = vmcs_read32(field);
6421                         break;
6422                 case VMCS_FIELD_TYPE_U64:
6423                         field_value = vmcs_read64(field);
6424                         break;
6425                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6426                         field_value = vmcs_readl(field);
6427                         break;
6428                 }
6429                 vmcs12_write_any(&vmx->vcpu, field, field_value);
6430         }
6431
6432         vmcs_clear(shadow_vmcs);
6433         vmcs_load(vmx->loaded_vmcs->vmcs);
6434 }
6435
6436 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6437 {
6438         const unsigned long *fields[] = {
6439                 shadow_read_write_fields,
6440                 shadow_read_only_fields
6441         };
6442         const int max_fields[] = {
6443                 max_shadow_read_write_fields,
6444                 max_shadow_read_only_fields
6445         };
6446         int i, q;
6447         unsigned long field;
6448         u64 field_value = 0;
6449         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6450
6451         vmcs_load(shadow_vmcs);
6452
6453         for (q = 0; q < ARRAY_SIZE(fields); q++) {
6454                 for (i = 0; i < max_fields[q]; i++) {
6455                         field = fields[q][i];
6456                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
6457
6458                         switch (vmcs_field_type(field)) {
6459                         case VMCS_FIELD_TYPE_U16:
6460                                 vmcs_write16(field, (u16)field_value);
6461                                 break;
6462                         case VMCS_FIELD_TYPE_U32:
6463                                 vmcs_write32(field, (u32)field_value);
6464                                 break;
6465                         case VMCS_FIELD_TYPE_U64:
6466                                 vmcs_write64(field, (u64)field_value);
6467                                 break;
6468                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6469                                 vmcs_writel(field, (long)field_value);
6470                                 break;
6471                         }
6472                 }
6473         }
6474
6475         vmcs_clear(shadow_vmcs);
6476         vmcs_load(vmx->loaded_vmcs->vmcs);
6477 }
6478
6479 /*
6480  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6481  * used before) all generate the same failure when it is missing.
6482  */
6483 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6484 {
6485         struct vcpu_vmx *vmx = to_vmx(vcpu);
6486         if (vmx->nested.current_vmptr == -1ull) {
6487                 nested_vmx_failInvalid(vcpu);
6488                 skip_emulated_instruction(vcpu);
6489                 return 0;
6490         }
6491         return 1;
6492 }
6493
6494 static int handle_vmread(struct kvm_vcpu *vcpu)
6495 {
6496         unsigned long field;
6497         u64 field_value;
6498         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6499         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6500         gva_t gva = 0;
6501
6502         if (!nested_vmx_check_permission(vcpu) ||
6503             !nested_vmx_check_vmcs12(vcpu))
6504                 return 1;
6505
6506         /* Decode instruction info and find the field to read */
6507         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6508         /* Read the field, zero-extended to a u64 field_value */
6509         if (!vmcs12_read_any(vcpu, field, &field_value)) {
6510                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6511                 skip_emulated_instruction(vcpu);
6512                 return 1;
6513         }
6514         /*
6515          * Now copy part of this value to register or memory, as requested.
6516          * Note that the number of bits actually copied is 32 or 64 depending
6517          * on the guest's mode (32 or 64 bit), not on the given field's length.
6518          */
6519         if (vmx_instruction_info & (1u << 10)) {
6520                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6521                         field_value);
6522         } else {
6523                 if (get_vmx_mem_address(vcpu, exit_qualification,
6524                                 vmx_instruction_info, &gva))
6525                         return 1;
6526                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6527                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6528                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6529         }
6530
6531         nested_vmx_succeed(vcpu);
6532         skip_emulated_instruction(vcpu);
6533         return 1;
6534 }
6535
6536
6537 static int handle_vmwrite(struct kvm_vcpu *vcpu)
6538 {
6539         unsigned long field;
6540         gva_t gva;
6541         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6542         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6543         /* The value to write might be 32 or 64 bits, depending on L1's long
6544          * mode, and eventually we need to write that into a field of several
6545          * possible lengths. The code below first zero-extends the value to 64
6546          * bit (field_value), and then copies only the approriate number of
6547          * bits into the vmcs12 field.
6548          */
6549         u64 field_value = 0;
6550         struct x86_exception e;
6551
6552         if (!nested_vmx_check_permission(vcpu) ||
6553             !nested_vmx_check_vmcs12(vcpu))
6554                 return 1;
6555
6556         if (vmx_instruction_info & (1u << 10))
6557                 field_value = kvm_register_readl(vcpu,
6558                         (((vmx_instruction_info) >> 3) & 0xf));
6559         else {
6560                 if (get_vmx_mem_address(vcpu, exit_qualification,
6561                                 vmx_instruction_info, &gva))
6562                         return 1;
6563                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6564                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
6565                         kvm_inject_page_fault(vcpu, &e);
6566                         return 1;
6567                 }
6568         }
6569
6570
6571         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6572         if (vmcs_field_readonly(field)) {
6573                 nested_vmx_failValid(vcpu,
6574                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6575                 skip_emulated_instruction(vcpu);
6576                 return 1;
6577         }
6578
6579         if (!vmcs12_write_any(vcpu, field, field_value)) {
6580                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6581                 skip_emulated_instruction(vcpu);
6582                 return 1;
6583         }
6584
6585         nested_vmx_succeed(vcpu);
6586         skip_emulated_instruction(vcpu);
6587         return 1;
6588 }
6589
6590 /* Emulate the VMPTRLD instruction */
6591 static int handle_vmptrld(struct kvm_vcpu *vcpu)
6592 {
6593         struct vcpu_vmx *vmx = to_vmx(vcpu);
6594         gpa_t vmptr;
6595         u32 exec_control;
6596
6597         if (!nested_vmx_check_permission(vcpu))
6598                 return 1;
6599
6600         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
6601                 return 1;
6602
6603         if (vmx->nested.current_vmptr != vmptr) {
6604                 struct vmcs12 *new_vmcs12;
6605                 struct page *page;
6606                 page = nested_get_page(vcpu, vmptr);
6607                 if (page == NULL) {
6608                         nested_vmx_failInvalid(vcpu);
6609                         skip_emulated_instruction(vcpu);
6610                         return 1;
6611                 }
6612                 new_vmcs12 = kmap(page);
6613                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6614                         kunmap(page);
6615                         nested_release_page_clean(page);
6616                         nested_vmx_failValid(vcpu,
6617                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6618                         skip_emulated_instruction(vcpu);
6619                         return 1;
6620                 }
6621
6622                 nested_release_vmcs12(vmx);
6623                 vmx->nested.current_vmptr = vmptr;
6624                 vmx->nested.current_vmcs12 = new_vmcs12;
6625                 vmx->nested.current_vmcs12_page = page;
6626                 if (enable_shadow_vmcs) {
6627                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6628                         exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6629                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6630                         vmcs_write64(VMCS_LINK_POINTER,
6631                                      __pa(vmx->nested.current_shadow_vmcs));
6632                         vmx->nested.sync_shadow_vmcs = true;
6633                 }
6634         }
6635
6636         nested_vmx_succeed(vcpu);
6637         skip_emulated_instruction(vcpu);
6638         return 1;
6639 }
6640
6641 /* Emulate the VMPTRST instruction */
6642 static int handle_vmptrst(struct kvm_vcpu *vcpu)
6643 {
6644         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6645         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6646         gva_t vmcs_gva;
6647         struct x86_exception e;
6648
6649         if (!nested_vmx_check_permission(vcpu))
6650                 return 1;
6651
6652         if (get_vmx_mem_address(vcpu, exit_qualification,
6653                         vmx_instruction_info, &vmcs_gva))
6654                 return 1;
6655         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6656         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6657                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
6658                                  sizeof(u64), &e)) {
6659                 kvm_inject_page_fault(vcpu, &e);
6660                 return 1;
6661         }
6662         nested_vmx_succeed(vcpu);
6663         skip_emulated_instruction(vcpu);
6664         return 1;
6665 }
6666
6667 /* Emulate the INVEPT instruction */
6668 static int handle_invept(struct kvm_vcpu *vcpu)
6669 {
6670         u32 vmx_instruction_info, types;
6671         unsigned long type;
6672         gva_t gva;
6673         struct x86_exception e;
6674         struct {
6675                 u64 eptp, gpa;
6676         } operand;
6677
6678         if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6679             !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6680                 kvm_queue_exception(vcpu, UD_VECTOR);
6681                 return 1;
6682         }
6683
6684         if (!nested_vmx_check_permission(vcpu))
6685                 return 1;
6686
6687         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6688                 kvm_queue_exception(vcpu, UD_VECTOR);
6689                 return 1;
6690         }
6691
6692         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6693         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
6694
6695         types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6696
6697         if (!(types & (1UL << type))) {
6698                 nested_vmx_failValid(vcpu,
6699                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6700                 return 1;
6701         }
6702
6703         /* According to the Intel VMX instruction reference, the memory
6704          * operand is read even if it isn't needed (e.g., for type==global)
6705          */
6706         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6707                         vmx_instruction_info, &gva))
6708                 return 1;
6709         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6710                                 sizeof(operand), &e)) {
6711                 kvm_inject_page_fault(vcpu, &e);
6712                 return 1;
6713         }
6714
6715         switch (type) {
6716         case VMX_EPT_EXTENT_GLOBAL:
6717                 kvm_mmu_sync_roots(vcpu);
6718                 kvm_mmu_flush_tlb(vcpu);
6719                 nested_vmx_succeed(vcpu);
6720                 break;
6721         default:
6722                 /* Trap single context invalidation invept calls */
6723                 BUG_ON(1);
6724                 break;
6725         }
6726
6727         skip_emulated_instruction(vcpu);
6728         return 1;
6729 }
6730
6731 /*
6732  * The exit handlers return 1 if the exit was handled fully and guest execution
6733  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
6734  * to be done to userspace and return 0.
6735  */
6736 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6737         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
6738         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
6739         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
6740         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
6741         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
6742         [EXIT_REASON_CR_ACCESS]               = handle_cr,
6743         [EXIT_REASON_DR_ACCESS]               = handle_dr,
6744         [EXIT_REASON_CPUID]                   = handle_cpuid,
6745         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
6746         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
6747         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
6748         [EXIT_REASON_HLT]                     = handle_halt,
6749         [EXIT_REASON_INVD]                    = handle_invd,
6750         [EXIT_REASON_INVLPG]                  = handle_invlpg,
6751         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
6752         [EXIT_REASON_VMCALL]                  = handle_vmcall,
6753         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
6754         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
6755         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
6756         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
6757         [EXIT_REASON_VMREAD]                  = handle_vmread,
6758         [EXIT_REASON_VMRESUME]                = handle_vmresume,
6759         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
6760         [EXIT_REASON_VMOFF]                   = handle_vmoff,
6761         [EXIT_REASON_VMON]                    = handle_vmon,
6762         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
6763         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
6764         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
6765         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
6766         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
6767         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
6768         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
6769         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
6770         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
6771         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
6772         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
6773         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
6774         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
6775         [EXIT_REASON_INVEPT]                  = handle_invept,
6776 };
6777
6778 static const int kvm_vmx_max_exit_handlers =
6779         ARRAY_SIZE(kvm_vmx_exit_handlers);
6780
6781 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6782                                        struct vmcs12 *vmcs12)
6783 {
6784         unsigned long exit_qualification;
6785         gpa_t bitmap, last_bitmap;
6786         unsigned int port;
6787         int size;
6788         u8 b;
6789
6790         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6791                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
6792
6793         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6794
6795         port = exit_qualification >> 16;
6796         size = (exit_qualification & 7) + 1;
6797
6798         last_bitmap = (gpa_t)-1;
6799         b = -1;
6800
6801         while (size > 0) {
6802                 if (port < 0x8000)
6803                         bitmap = vmcs12->io_bitmap_a;
6804                 else if (port < 0x10000)
6805                         bitmap = vmcs12->io_bitmap_b;
6806                 else
6807                         return 1;
6808                 bitmap += (port & 0x7fff) / 8;
6809
6810                 if (last_bitmap != bitmap)
6811                         if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6812                                 return 1;
6813                 if (b & (1 << (port & 7)))
6814                         return 1;
6815
6816                 port++;
6817                 size--;
6818                 last_bitmap = bitmap;
6819         }
6820
6821         return 0;
6822 }
6823
6824 /*
6825  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6826  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6827  * disinterest in the current event (read or write a specific MSR) by using an
6828  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6829  */
6830 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6831         struct vmcs12 *vmcs12, u32 exit_reason)
6832 {
6833         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6834         gpa_t bitmap;
6835
6836         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
6837                 return 1;
6838
6839         /*
6840          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6841          * for the four combinations of read/write and low/high MSR numbers.
6842          * First we need to figure out which of the four to use:
6843          */
6844         bitmap = vmcs12->msr_bitmap;
6845         if (exit_reason == EXIT_REASON_MSR_WRITE)
6846                 bitmap += 2048;
6847         if (msr_index >= 0xc0000000) {
6848                 msr_index -= 0xc0000000;
6849                 bitmap += 1024;
6850         }
6851
6852         /* Then read the msr_index'th bit from this bitmap: */
6853         if (msr_index < 1024*8) {
6854                 unsigned char b;
6855                 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6856                         return 1;
6857                 return 1 & (b >> (msr_index & 7));
6858         } else
6859                 return 1; /* let L1 handle the wrong parameter */
6860 }
6861
6862 /*
6863  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6864  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6865  * intercept (via guest_host_mask etc.) the current event.
6866  */
6867 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6868         struct vmcs12 *vmcs12)
6869 {
6870         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6871         int cr = exit_qualification & 15;
6872         int reg = (exit_qualification >> 8) & 15;
6873         unsigned long val = kvm_register_readl(vcpu, reg);
6874
6875         switch ((exit_qualification >> 4) & 3) {
6876         case 0: /* mov to cr */
6877                 switch (cr) {
6878                 case 0:
6879                         if (vmcs12->cr0_guest_host_mask &
6880                             (val ^ vmcs12->cr0_read_shadow))
6881                                 return 1;
6882                         break;
6883                 case 3:
6884                         if ((vmcs12->cr3_target_count >= 1 &&
6885                                         vmcs12->cr3_target_value0 == val) ||
6886                                 (vmcs12->cr3_target_count >= 2 &&
6887                                         vmcs12->cr3_target_value1 == val) ||
6888                                 (vmcs12->cr3_target_count >= 3 &&
6889                                         vmcs12->cr3_target_value2 == val) ||
6890                                 (vmcs12->cr3_target_count >= 4 &&
6891                                         vmcs12->cr3_target_value3 == val))
6892                                 return 0;
6893                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6894                                 return 1;
6895                         break;
6896                 case 4:
6897                         if (vmcs12->cr4_guest_host_mask &
6898                             (vmcs12->cr4_read_shadow ^ val))
6899                                 return 1;
6900                         break;
6901                 case 8:
6902                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6903                                 return 1;
6904                         break;
6905                 }
6906                 break;
6907         case 2: /* clts */
6908                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6909                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
6910                         return 1;
6911                 break;
6912         case 1: /* mov from cr */
6913                 switch (cr) {
6914                 case 3:
6915                         if (vmcs12->cpu_based_vm_exec_control &
6916                             CPU_BASED_CR3_STORE_EXITING)
6917                                 return 1;
6918                         break;
6919                 case 8:
6920                         if (vmcs12->cpu_based_vm_exec_control &
6921                             CPU_BASED_CR8_STORE_EXITING)
6922                                 return 1;
6923                         break;
6924                 }
6925                 break;
6926         case 3: /* lmsw */
6927                 /*
6928                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6929                  * cr0. Other attempted changes are ignored, with no exit.
6930                  */
6931                 if (vmcs12->cr0_guest_host_mask & 0xe &
6932                     (val ^ vmcs12->cr0_read_shadow))
6933                         return 1;
6934                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6935                     !(vmcs12->cr0_read_shadow & 0x1) &&
6936                     (val & 0x1))
6937                         return 1;
6938                 break;
6939         }
6940         return 0;
6941 }
6942
6943 /*
6944  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6945  * should handle it ourselves in L0 (and then continue L2). Only call this
6946  * when in is_guest_mode (L2).
6947  */
6948 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6949 {
6950         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6951         struct vcpu_vmx *vmx = to_vmx(vcpu);
6952         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6953         u32 exit_reason = vmx->exit_reason;
6954
6955         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6956                                 vmcs_readl(EXIT_QUALIFICATION),
6957                                 vmx->idt_vectoring_info,
6958                                 intr_info,
6959                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6960                                 KVM_ISA_VMX);
6961
6962         if (vmx->nested.nested_run_pending)
6963                 return 0;
6964
6965         if (unlikely(vmx->fail)) {
6966                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6967                                     vmcs_read32(VM_INSTRUCTION_ERROR));
6968                 return 1;
6969         }
6970
6971         switch (exit_reason) {
6972         case EXIT_REASON_EXCEPTION_NMI:
6973                 if (!is_exception(intr_info))
6974                         return 0;
6975                 else if (is_page_fault(intr_info))
6976                         return enable_ept;
6977                 else if (is_no_device(intr_info) &&
6978                          !(vmcs12->guest_cr0 & X86_CR0_TS))
6979                         return 0;
6980                 return vmcs12->exception_bitmap &
6981                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6982         case EXIT_REASON_EXTERNAL_INTERRUPT:
6983                 return 0;
6984         case EXIT_REASON_TRIPLE_FAULT:
6985                 return 1;
6986         case EXIT_REASON_PENDING_INTERRUPT:
6987                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
6988         case EXIT_REASON_NMI_WINDOW:
6989                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
6990         case EXIT_REASON_TASK_SWITCH:
6991                 return 1;
6992         case EXIT_REASON_CPUID:
6993                 return 1;
6994         case EXIT_REASON_HLT:
6995                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6996         case EXIT_REASON_INVD:
6997                 return 1;
6998         case EXIT_REASON_INVLPG:
6999                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7000         case EXIT_REASON_RDPMC:
7001                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7002         case EXIT_REASON_RDTSC:
7003                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7004         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7005         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7006         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7007         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7008         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7009         case EXIT_REASON_INVEPT:
7010                 /*
7011                  * VMX instructions trap unconditionally. This allows L1 to
7012                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7013                  */
7014                 return 1;
7015         case EXIT_REASON_CR_ACCESS:
7016                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7017         case EXIT_REASON_DR_ACCESS:
7018                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7019         case EXIT_REASON_IO_INSTRUCTION:
7020                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7021         case EXIT_REASON_MSR_READ:
7022         case EXIT_REASON_MSR_WRITE:
7023                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7024         case EXIT_REASON_INVALID_STATE:
7025                 return 1;
7026         case EXIT_REASON_MWAIT_INSTRUCTION:
7027                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7028         case EXIT_REASON_MONITOR_INSTRUCTION:
7029                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7030         case EXIT_REASON_PAUSE_INSTRUCTION:
7031                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7032                         nested_cpu_has2(vmcs12,
7033                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7034         case EXIT_REASON_MCE_DURING_VMENTRY:
7035                 return 0;
7036         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7037                 return 1;
7038         case EXIT_REASON_APIC_ACCESS:
7039                 return nested_cpu_has2(vmcs12,
7040                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7041         case EXIT_REASON_EPT_VIOLATION:
7042                 /*
7043                  * L0 always deals with the EPT violation. If nested EPT is
7044                  * used, and the nested mmu code discovers that the address is
7045                  * missing in the guest EPT table (EPT12), the EPT violation
7046                  * will be injected with nested_ept_inject_page_fault()
7047                  */
7048                 return 0;
7049         case EXIT_REASON_EPT_MISCONFIG:
7050                 /*
7051                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7052                  * table (shadow on EPT) or a merged EPT table that L0 built
7053                  * (EPT on EPT). So any problems with the structure of the
7054                  * table is L0's fault.
7055                  */
7056                 return 0;
7057         case EXIT_REASON_WBINVD:
7058                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7059         case EXIT_REASON_XSETBV:
7060                 return 1;
7061         default:
7062                 return 1;
7063         }
7064 }
7065
7066 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7067 {
7068         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7069         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7070 }
7071
7072 /*
7073  * The guest has exited.  See if we can fix it or if we need userspace
7074  * assistance.
7075  */
7076 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
7077 {
7078         struct vcpu_vmx *vmx = to_vmx(vcpu);
7079         u32 exit_reason = vmx->exit_reason;
7080         u32 vectoring_info = vmx->idt_vectoring_info;
7081
7082         /* If guest state is invalid, start emulating */
7083         if (vmx->emulation_required)
7084                 return handle_invalid_guest_state(vcpu);
7085
7086         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
7087                 nested_vmx_vmexit(vcpu, exit_reason,
7088                                   vmcs_read32(VM_EXIT_INTR_INFO),
7089                                   vmcs_readl(EXIT_QUALIFICATION));
7090                 return 1;
7091         }
7092
7093         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7094                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7095                 vcpu->run->fail_entry.hardware_entry_failure_reason
7096                         = exit_reason;
7097                 return 0;
7098         }
7099
7100         if (unlikely(vmx->fail)) {
7101                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7102                 vcpu->run->fail_entry.hardware_entry_failure_reason
7103                         = vmcs_read32(VM_INSTRUCTION_ERROR);
7104                 return 0;
7105         }
7106
7107         /*
7108          * Note:
7109          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7110          * delivery event since it indicates guest is accessing MMIO.
7111          * The vm-exit can be triggered again after return to guest that
7112          * will cause infinite loop.
7113          */
7114         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
7115                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
7116                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
7117                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
7118                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7119                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7120                 vcpu->run->internal.ndata = 2;
7121                 vcpu->run->internal.data[0] = vectoring_info;
7122                 vcpu->run->internal.data[1] = exit_reason;
7123                 return 0;
7124         }
7125
7126         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7127             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
7128                                         get_vmcs12(vcpu))))) {
7129                 if (vmx_interrupt_allowed(vcpu)) {
7130                         vmx->soft_vnmi_blocked = 0;
7131                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
7132                            vcpu->arch.nmi_pending) {
7133                         /*
7134                          * This CPU don't support us in finding the end of an
7135                          * NMI-blocked window if the guest runs with IRQs
7136                          * disabled. So we pull the trigger after 1 s of
7137                          * futile waiting, but inform the user about this.
7138                          */
7139                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7140                                "state on VCPU %d after 1 s timeout\n",
7141                                __func__, vcpu->vcpu_id);
7142                         vmx->soft_vnmi_blocked = 0;
7143                 }
7144         }
7145
7146         if (exit_reason < kvm_vmx_max_exit_handlers
7147             && kvm_vmx_exit_handlers[exit_reason])
7148                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
7149         else {
7150                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
7151                 vcpu->run->hw.hardware_exit_reason = exit_reason;
7152         }
7153         return 0;
7154 }
7155
7156 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
7157 {
7158         if (irr == -1 || tpr < irr) {
7159                 vmcs_write32(TPR_THRESHOLD, 0);
7160                 return;
7161         }
7162
7163         vmcs_write32(TPR_THRESHOLD, irr);
7164 }
7165
7166 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7167 {
7168         u32 sec_exec_control;
7169
7170         /*
7171          * There is not point to enable virtualize x2apic without enable
7172          * apicv
7173          */
7174         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7175                                 !vmx_vm_has_apicv(vcpu->kvm))
7176                 return;
7177
7178         if (!vm_need_tpr_shadow(vcpu->kvm))
7179                 return;
7180
7181         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7182
7183         if (set) {
7184                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7185                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7186         } else {
7187                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7188                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7189         }
7190         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7191
7192         vmx_set_msr_bitmap(vcpu);
7193 }
7194
7195 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7196 {
7197         u16 status;
7198         u8 old;
7199
7200         if (!vmx_vm_has_apicv(kvm))
7201                 return;
7202
7203         if (isr == -1)
7204                 isr = 0;
7205
7206         status = vmcs_read16(GUEST_INTR_STATUS);
7207         old = status >> 8;
7208         if (isr != old) {
7209                 status &= 0xff;
7210                 status |= isr << 8;
7211                 vmcs_write16(GUEST_INTR_STATUS, status);
7212         }
7213 }
7214
7215 static void vmx_set_rvi(int vector)
7216 {
7217         u16 status;
7218         u8 old;
7219
7220         status = vmcs_read16(GUEST_INTR_STATUS);
7221         old = (u8)status & 0xff;
7222         if ((u8)vector != old) {
7223                 status &= ~0xff;
7224                 status |= (u8)vector;
7225                 vmcs_write16(GUEST_INTR_STATUS, status);
7226         }
7227 }
7228
7229 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7230 {
7231         if (max_irr == -1)
7232                 return;
7233
7234         /*
7235          * If a vmexit is needed, vmx_check_nested_events handles it.
7236          */
7237         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
7238                 return;
7239
7240         if (!is_guest_mode(vcpu)) {
7241                 vmx_set_rvi(max_irr);
7242                 return;
7243         }
7244
7245         /*
7246          * Fall back to pre-APICv interrupt injection since L2
7247          * is run without virtual interrupt delivery.
7248          */
7249         if (!kvm_event_needs_reinjection(vcpu) &&
7250             vmx_interrupt_allowed(vcpu)) {
7251                 kvm_queue_interrupt(vcpu, max_irr, false);
7252                 vmx_inject_irq(vcpu);
7253         }
7254 }
7255
7256 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7257 {
7258         if (!vmx_vm_has_apicv(vcpu->kvm))
7259                 return;
7260
7261         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7262         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7263         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7264         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7265 }
7266
7267 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
7268 {
7269         u32 exit_intr_info;
7270
7271         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7272               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7273                 return;
7274
7275         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7276         exit_intr_info = vmx->exit_intr_info;
7277
7278         /* Handle machine checks before interrupts are enabled */
7279         if (is_machine_check(exit_intr_info))
7280                 kvm_machine_check();
7281
7282         /* We need to handle NMIs before interrupts are enabled */
7283         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
7284             (exit_intr_info & INTR_INFO_VALID_MASK)) {
7285                 kvm_before_handle_nmi(&vmx->vcpu);
7286                 asm("int $2");
7287                 kvm_after_handle_nmi(&vmx->vcpu);
7288         }
7289 }
7290
7291 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7292 {
7293         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7294
7295         /*
7296          * If external interrupt exists, IF bit is set in rflags/eflags on the
7297          * interrupt stack frame, and interrupt will be enabled on a return
7298          * from interrupt handler.
7299          */
7300         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7301                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7302                 unsigned int vector;
7303                 unsigned long entry;
7304                 gate_desc *desc;
7305                 struct vcpu_vmx *vmx = to_vmx(vcpu);
7306 #ifdef CONFIG_X86_64
7307                 unsigned long tmp;
7308 #endif
7309
7310                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
7311                 desc = (gate_desc *)vmx->host_idt_base + vector;
7312                 entry = gate_offset(*desc);
7313                 asm volatile(
7314 #ifdef CONFIG_X86_64
7315                         "mov %%" _ASM_SP ", %[sp]\n\t"
7316                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7317                         "push $%c[ss]\n\t"
7318                         "push %[sp]\n\t"
7319 #endif
7320                         "pushf\n\t"
7321                         "orl $0x200, (%%" _ASM_SP ")\n\t"
7322                         __ASM_SIZE(push) " $%c[cs]\n\t"
7323                         "call *%[entry]\n\t"
7324                         :
7325 #ifdef CONFIG_X86_64
7326                         [sp]"=&r"(tmp)
7327 #endif
7328                         :
7329                         [entry]"r"(entry),
7330                         [ss]"i"(__KERNEL_DS),
7331                         [cs]"i"(__KERNEL_CS)
7332                         );
7333         } else
7334                 local_irq_enable();
7335 }
7336
7337 static bool vmx_mpx_supported(void)
7338 {
7339         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7340                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7341 }
7342
7343 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7344 {
7345         u32 exit_intr_info;
7346         bool unblock_nmi;
7347         u8 vector;
7348         bool idtv_info_valid;
7349
7350         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7351
7352         if (cpu_has_virtual_nmis()) {
7353                 if (vmx->nmi_known_unmasked)
7354                         return;
7355                 /*
7356                  * Can't use vmx->exit_intr_info since we're not sure what
7357                  * the exit reason is.
7358                  */
7359                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7360                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7361                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7362                 /*
7363                  * SDM 3: 27.7.1.2 (September 2008)
7364                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
7365                  * a guest IRET fault.
7366                  * SDM 3: 23.2.2 (September 2008)
7367                  * Bit 12 is undefined in any of the following cases:
7368                  *  If the VM exit sets the valid bit in the IDT-vectoring
7369                  *   information field.
7370                  *  If the VM exit is due to a double fault.
7371                  */
7372                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7373                     vector != DF_VECTOR && !idtv_info_valid)
7374                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7375                                       GUEST_INTR_STATE_NMI);
7376                 else
7377                         vmx->nmi_known_unmasked =
7378                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7379                                   & GUEST_INTR_STATE_NMI);
7380         } else if (unlikely(vmx->soft_vnmi_blocked))
7381                 vmx->vnmi_blocked_time +=
7382                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
7383 }
7384
7385 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
7386                                       u32 idt_vectoring_info,
7387                                       int instr_len_field,
7388                                       int error_code_field)
7389 {
7390         u8 vector;
7391         int type;
7392         bool idtv_info_valid;
7393
7394         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
7395
7396         vcpu->arch.nmi_injected = false;
7397         kvm_clear_exception_queue(vcpu);
7398         kvm_clear_interrupt_queue(vcpu);
7399
7400         if (!idtv_info_valid)
7401                 return;
7402
7403         kvm_make_request(KVM_REQ_EVENT, vcpu);
7404
7405         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7406         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
7407
7408         switch (type) {
7409         case INTR_TYPE_NMI_INTR:
7410                 vcpu->arch.nmi_injected = true;
7411                 /*
7412                  * SDM 3: 27.7.1.2 (September 2008)
7413                  * Clear bit "block by NMI" before VM entry if a NMI
7414                  * delivery faulted.
7415                  */
7416                 vmx_set_nmi_mask(vcpu, false);
7417                 break;
7418         case INTR_TYPE_SOFT_EXCEPTION:
7419                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7420                 /* fall through */
7421         case INTR_TYPE_HARD_EXCEPTION:
7422                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
7423                         u32 err = vmcs_read32(error_code_field);
7424                         kvm_requeue_exception_e(vcpu, vector, err);
7425                 } else
7426                         kvm_requeue_exception(vcpu, vector);
7427                 break;
7428         case INTR_TYPE_SOFT_INTR:
7429                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
7430                 /* fall through */
7431         case INTR_TYPE_EXT_INTR:
7432                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
7433                 break;
7434         default:
7435                 break;
7436         }
7437 }
7438
7439 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7440 {
7441         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
7442                                   VM_EXIT_INSTRUCTION_LEN,
7443                                   IDT_VECTORING_ERROR_CODE);
7444 }
7445
7446 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7447 {
7448         __vmx_complete_interrupts(vcpu,
7449                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7450                                   VM_ENTRY_INSTRUCTION_LEN,
7451                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
7452
7453         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7454 }
7455
7456 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7457 {
7458         int i, nr_msrs;
7459         struct perf_guest_switch_msr *msrs;
7460
7461         msrs = perf_guest_get_msrs(&nr_msrs);
7462
7463         if (!msrs)
7464                 return;
7465
7466         for (i = 0; i < nr_msrs; i++)
7467                 if (msrs[i].host == msrs[i].guest)
7468                         clear_atomic_switch_msr(vmx, msrs[i].msr);
7469                 else
7470                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7471                                         msrs[i].host);
7472 }
7473
7474 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
7475 {
7476         struct vcpu_vmx *vmx = to_vmx(vcpu);
7477         unsigned long debugctlmsr;
7478
7479         /* Record the guest's net vcpu time for enforced NMI injections. */
7480         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7481                 vmx->entry_time = ktime_get();
7482
7483         /* Don't enter VMX if guest state is invalid, let the exit handler
7484            start emulation until we arrive back to a valid state */
7485         if (vmx->emulation_required)
7486                 return;
7487
7488         if (vmx->ple_window_dirty) {
7489                 vmx->ple_window_dirty = false;
7490                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
7491         }
7492
7493         if (vmx->nested.sync_shadow_vmcs) {
7494                 copy_vmcs12_to_shadow(vmx);
7495                 vmx->nested.sync_shadow_vmcs = false;
7496         }
7497
7498         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7499                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7500         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7501                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7502
7503         /* When single-stepping over STI and MOV SS, we must clear the
7504          * corresponding interruptibility bits in the guest state. Otherwise
7505          * vmentry fails as it then expects bit 14 (BS) in pending debug
7506          * exceptions being set, but that's not correct for the guest debugging
7507          * case. */
7508         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7509                 vmx_set_interrupt_shadow(vcpu, 0);
7510
7511         atomic_switch_perf_msrs(vmx);
7512         debugctlmsr = get_debugctlmsr();
7513
7514         vmx->__launched = vmx->loaded_vmcs->launched;
7515         asm(
7516                 /* Store host registers */
7517                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7518                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7519                 "push %%" _ASM_CX " \n\t"
7520                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7521                 "je 1f \n\t"
7522                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
7523                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
7524                 "1: \n\t"
7525                 /* Reload cr2 if changed */
7526                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7527                 "mov %%cr2, %%" _ASM_DX " \n\t"
7528                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
7529                 "je 2f \n\t"
7530                 "mov %%" _ASM_AX", %%cr2 \n\t"
7531                 "2: \n\t"
7532                 /* Check if vmlaunch of vmresume is needed */
7533                 "cmpl $0, %c[launched](%0) \n\t"
7534                 /* Load guest registers.  Don't clobber flags. */
7535                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7536                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7537                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7538                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7539                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7540                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
7541 #ifdef CONFIG_X86_64
7542                 "mov %c[r8](%0),  %%r8  \n\t"
7543                 "mov %c[r9](%0),  %%r9  \n\t"
7544                 "mov %c[r10](%0), %%r10 \n\t"
7545                 "mov %c[r11](%0), %%r11 \n\t"
7546                 "mov %c[r12](%0), %%r12 \n\t"
7547                 "mov %c[r13](%0), %%r13 \n\t"
7548                 "mov %c[r14](%0), %%r14 \n\t"
7549                 "mov %c[r15](%0), %%r15 \n\t"
7550 #endif
7551                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
7552
7553                 /* Enter guest mode */
7554                 "jne 1f \n\t"
7555                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
7556                 "jmp 2f \n\t"
7557                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7558                 "2: "
7559                 /* Save guest registers, load host registers, keep flags */
7560                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
7561                 "pop %0 \n\t"
7562                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7563                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7564                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7565                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7566                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7567                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7568                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
7569 #ifdef CONFIG_X86_64
7570                 "mov %%r8,  %c[r8](%0) \n\t"
7571                 "mov %%r9,  %c[r9](%0) \n\t"
7572                 "mov %%r10, %c[r10](%0) \n\t"
7573                 "mov %%r11, %c[r11](%0) \n\t"
7574                 "mov %%r12, %c[r12](%0) \n\t"
7575                 "mov %%r13, %c[r13](%0) \n\t"
7576                 "mov %%r14, %c[r14](%0) \n\t"
7577                 "mov %%r15, %c[r15](%0) \n\t"
7578 #endif
7579                 "mov %%cr2, %%" _ASM_AX "   \n\t"
7580                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
7581
7582                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
7583                 "setbe %c[fail](%0) \n\t"
7584                 ".pushsection .rodata \n\t"
7585                 ".global vmx_return \n\t"
7586                 "vmx_return: " _ASM_PTR " 2b \n\t"
7587                 ".popsection"
7588               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
7589                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
7590                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
7591                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
7592                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7593                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7594                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7595                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7596                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7597                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7598                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
7599 #ifdef CONFIG_X86_64
7600                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7601                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7602                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7603                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7604                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7605                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7606                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7607                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
7608 #endif
7609                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7610                 [wordsize]"i"(sizeof(ulong))
7611               : "cc", "memory"
7612 #ifdef CONFIG_X86_64
7613                 , "rax", "rbx", "rdi", "rsi"
7614                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7615 #else
7616                 , "eax", "ebx", "edi", "esi"
7617 #endif
7618               );
7619
7620         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7621         if (debugctlmsr)
7622                 update_debugctlmsr(debugctlmsr);
7623
7624 #ifndef CONFIG_X86_64
7625         /*
7626          * The sysexit path does not restore ds/es, so we must set them to
7627          * a reasonable value ourselves.
7628          *
7629          * We can't defer this to vmx_load_host_state() since that function
7630          * may be executed in interrupt context, which saves and restore segments
7631          * around it, nullifying its effect.
7632          */
7633         loadsegment(ds, __USER_DS);
7634         loadsegment(es, __USER_DS);
7635 #endif
7636
7637         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
7638                                   | (1 << VCPU_EXREG_RFLAGS)
7639                                   | (1 << VCPU_EXREG_PDPTR)
7640                                   | (1 << VCPU_EXREG_SEGMENTS)
7641                                   | (1 << VCPU_EXREG_CR3));
7642         vcpu->arch.regs_dirty = 0;
7643
7644         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7645
7646         vmx->loaded_vmcs->launched = 1;
7647
7648         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
7649         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
7650
7651         /*
7652          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7653          * we did not inject a still-pending event to L1 now because of
7654          * nested_run_pending, we need to re-enable this bit.
7655          */
7656         if (vmx->nested.nested_run_pending)
7657                 kvm_make_request(KVM_REQ_EVENT, vcpu);
7658
7659         vmx->nested.nested_run_pending = 0;
7660
7661         vmx_complete_atomic_exit(vmx);
7662         vmx_recover_nmi_blocking(vmx);
7663         vmx_complete_interrupts(vmx);
7664 }
7665
7666 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
7667 {
7668         struct vcpu_vmx *vmx = to_vmx(vcpu);
7669         int cpu;
7670
7671         if (vmx->loaded_vmcs == &vmx->vmcs01)
7672                 return;
7673
7674         cpu = get_cpu();
7675         vmx->loaded_vmcs = &vmx->vmcs01;
7676         vmx_vcpu_put(vcpu);
7677         vmx_vcpu_load(vcpu, cpu);
7678         vcpu->cpu = cpu;
7679         put_cpu();
7680 }
7681
7682 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7683 {
7684         struct vcpu_vmx *vmx = to_vmx(vcpu);
7685
7686         free_vpid(vmx);
7687         leave_guest_mode(vcpu);
7688         vmx_load_vmcs01(vcpu);
7689         free_nested(vmx);
7690         free_loaded_vmcs(vmx->loaded_vmcs);
7691         kfree(vmx->guest_msrs);
7692         kvm_vcpu_uninit(vcpu);
7693         kmem_cache_free(kvm_vcpu_cache, vmx);
7694 }
7695
7696 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
7697 {
7698         int err;
7699         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
7700         int cpu;
7701
7702         if (!vmx)
7703                 return ERR_PTR(-ENOMEM);
7704
7705         allocate_vpid(vmx);
7706
7707         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7708         if (err)
7709                 goto free_vcpu;
7710
7711         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
7712         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
7713                      > PAGE_SIZE);
7714
7715         err = -ENOMEM;
7716         if (!vmx->guest_msrs) {
7717                 goto uninit_vcpu;
7718         }
7719
7720         vmx->loaded_vmcs = &vmx->vmcs01;
7721         vmx->loaded_vmcs->vmcs = alloc_vmcs();
7722         if (!vmx->loaded_vmcs->vmcs)
7723                 goto free_msrs;
7724         if (!vmm_exclusive)
7725                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7726         loaded_vmcs_init(vmx->loaded_vmcs);
7727         if (!vmm_exclusive)
7728                 kvm_cpu_vmxoff();
7729
7730         cpu = get_cpu();
7731         vmx_vcpu_load(&vmx->vcpu, cpu);
7732         vmx->vcpu.cpu = cpu;
7733         err = vmx_vcpu_setup(vmx);
7734         vmx_vcpu_put(&vmx->vcpu);
7735         put_cpu();
7736         if (err)
7737                 goto free_vmcs;
7738         if (vm_need_virtualize_apic_accesses(kvm)) {
7739                 err = alloc_apic_access_page(kvm);
7740                 if (err)
7741                         goto free_vmcs;
7742         }
7743
7744         if (enable_ept) {
7745                 if (!kvm->arch.ept_identity_map_addr)
7746                         kvm->arch.ept_identity_map_addr =
7747                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
7748                 err = -ENOMEM;
7749                 if (alloc_identity_pagetable(kvm) != 0)
7750                         goto free_vmcs;
7751                 if (!init_rmode_identity_map(kvm))
7752                         goto free_vmcs;
7753         }
7754
7755         vmx->nested.current_vmptr = -1ull;
7756         vmx->nested.current_vmcs12 = NULL;
7757
7758         return &vmx->vcpu;
7759
7760 free_vmcs:
7761         free_loaded_vmcs(vmx->loaded_vmcs);
7762 free_msrs:
7763         kfree(vmx->guest_msrs);
7764 uninit_vcpu:
7765         kvm_vcpu_uninit(&vmx->vcpu);
7766 free_vcpu:
7767         free_vpid(vmx);
7768         kmem_cache_free(kvm_vcpu_cache, vmx);
7769         return ERR_PTR(err);
7770 }
7771
7772 static void __init vmx_check_processor_compat(void *rtn)
7773 {
7774         struct vmcs_config vmcs_conf;
7775
7776         *(int *)rtn = 0;
7777         if (setup_vmcs_config(&vmcs_conf) < 0)
7778                 *(int *)rtn = -EIO;
7779         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7780                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7781                                 smp_processor_id());
7782                 *(int *)rtn = -EIO;
7783         }
7784 }
7785
7786 static int get_ept_level(void)
7787 {
7788         return VMX_EPT_DEFAULT_GAW + 1;
7789 }
7790
7791 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
7792 {
7793         u64 ret;
7794
7795         /* For VT-d and EPT combination
7796          * 1. MMIO: always map as UC
7797          * 2. EPT with VT-d:
7798          *   a. VT-d without snooping control feature: can't guarantee the
7799          *      result, try to trust guest.
7800          *   b. VT-d with snooping control feature: snooping control feature of
7801          *      VT-d engine can guarantee the cache correctness. Just set it
7802          *      to WB to keep consistent with host. So the same as item 3.
7803          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7804          *    consistent with host MTRR
7805          */
7806         if (is_mmio)
7807                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
7808         else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
7809                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7810                       VMX_EPT_MT_EPTE_SHIFT;
7811         else
7812                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
7813                         | VMX_EPT_IPAT_BIT;
7814
7815         return ret;
7816 }
7817
7818 static int vmx_get_lpage_level(void)
7819 {
7820         if (enable_ept && !cpu_has_vmx_ept_1g_page())
7821                 return PT_DIRECTORY_LEVEL;
7822         else
7823                 /* For shadow and EPT supported 1GB page */
7824                 return PT_PDPE_LEVEL;
7825 }
7826
7827 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7828 {
7829         struct kvm_cpuid_entry2 *best;
7830         struct vcpu_vmx *vmx = to_vmx(vcpu);
7831         u32 exec_control;
7832
7833         vmx->rdtscp_enabled = false;
7834         if (vmx_rdtscp_supported()) {
7835                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7836                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7837                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7838                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7839                                 vmx->rdtscp_enabled = true;
7840                         else {
7841                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7842                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7843                                                 exec_control);
7844                         }
7845                 }
7846         }
7847
7848         /* Exposing INVPCID only when PCID is exposed */
7849         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7850         if (vmx_invpcid_supported() &&
7851             best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
7852             guest_cpuid_has_pcid(vcpu)) {
7853                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7854                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7855                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7856                              exec_control);
7857         } else {
7858                 if (cpu_has_secondary_exec_ctrls()) {
7859                         exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7860                         exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7861                         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7862                                      exec_control);
7863                 }
7864                 if (best)
7865                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
7866         }
7867 }
7868
7869 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7870 {
7871         if (func == 1 && nested)
7872                 entry->ecx |= bit(X86_FEATURE_VMX);
7873 }
7874
7875 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7876                 struct x86_exception *fault)
7877 {
7878         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7879         u32 exit_reason;
7880
7881         if (fault->error_code & PFERR_RSVD_MASK)
7882                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
7883         else
7884                 exit_reason = EXIT_REASON_EPT_VIOLATION;
7885         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
7886         vmcs12->guest_physical_address = fault->address;
7887 }
7888
7889 /* Callbacks for nested_ept_init_mmu_context: */
7890
7891 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7892 {
7893         /* return the page table to be shadowed - in our case, EPT12 */
7894         return get_vmcs12(vcpu)->ept_pointer;
7895 }
7896
7897 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
7898 {
7899         kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
7900                         nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7901
7902         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
7903         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
7904         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7905
7906         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
7907 }
7908
7909 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7910 {
7911         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7912 }
7913
7914 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7915                 struct x86_exception *fault)
7916 {
7917         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7918
7919         WARN_ON(!is_guest_mode(vcpu));
7920
7921         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7922         if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
7923                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7924                                   vmcs_read32(VM_EXIT_INTR_INFO),
7925                                   vmcs_readl(EXIT_QUALIFICATION));
7926         else
7927                 kvm_inject_page_fault(vcpu, fault);
7928 }
7929
7930 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
7931 {
7932         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
7933         struct vcpu_vmx *vmx = to_vmx(vcpu);
7934
7935         if (vcpu->arch.virtual_tsc_khz == 0)
7936                 return;
7937
7938         /* Make sure short timeouts reliably trigger an immediate vmexit.
7939          * hrtimer_start does not guarantee this. */
7940         if (preemption_timeout <= 1) {
7941                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
7942                 return;
7943         }
7944
7945         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
7946         preemption_timeout *= 1000000;
7947         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
7948         hrtimer_start(&vmx->nested.preemption_timer,
7949                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
7950 }
7951
7952 /*
7953  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7954  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7955  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7956  * guest in a way that will both be appropriate to L1's requests, and our
7957  * needs. In addition to modifying the active vmcs (which is vmcs02), this
7958  * function also has additional necessary side-effects, like setting various
7959  * vcpu->arch fields.
7960  */
7961 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7962 {
7963         struct vcpu_vmx *vmx = to_vmx(vcpu);
7964         u32 exec_control;
7965
7966         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7967         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7968         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7969         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7970         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7971         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7972         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7973         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7974         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7975         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7976         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7977         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7978         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7979         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7980         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7981         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7982         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7983         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7984         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7985         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7986         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7987         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7988         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7989         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7990         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7991         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7992         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7993         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7994         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7995         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7996         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7997         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7998         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7999         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
8000         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
8001         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
8002
8003         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
8004                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
8005                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
8006         } else {
8007                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
8008                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
8009         }
8010         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
8011                 vmcs12->vm_entry_intr_info_field);
8012         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
8013                 vmcs12->vm_entry_exception_error_code);
8014         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
8015                 vmcs12->vm_entry_instruction_len);
8016         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
8017                 vmcs12->guest_interruptibility_info);
8018         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
8019         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
8020         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
8021                 vmcs12->guest_pending_dbg_exceptions);
8022         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
8023         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
8024
8025         vmcs_write64(VMCS_LINK_POINTER, -1ull);
8026
8027         exec_control = vmcs12->pin_based_vm_exec_control;
8028         exec_control |= vmcs_config.pin_based_exec_ctrl;
8029         exec_control &= ~(PIN_BASED_VMX_PREEMPTION_TIMER |
8030                           PIN_BASED_POSTED_INTR);
8031         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
8032
8033         vmx->nested.preemption_timer_expired = false;
8034         if (nested_cpu_has_preemption_timer(vmcs12))
8035                 vmx_start_preemption_timer(vcpu);
8036
8037         /*
8038          * Whether page-faults are trapped is determined by a combination of
8039          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
8040          * If enable_ept, L0 doesn't care about page faults and we should
8041          * set all of these to L1's desires. However, if !enable_ept, L0 does
8042          * care about (at least some) page faults, and because it is not easy
8043          * (if at all possible?) to merge L0 and L1's desires, we simply ask
8044          * to exit on each and every L2 page fault. This is done by setting
8045          * MASK=MATCH=0 and (see below) EB.PF=1.
8046          * Note that below we don't need special code to set EB.PF beyond the
8047          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
8048          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
8049          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
8050          *
8051          * A problem with this approach (when !enable_ept) is that L1 may be
8052          * injected with more page faults than it asked for. This could have
8053          * caused problems, but in practice existing hypervisors don't care.
8054          * To fix this, we will need to emulate the PFEC checking (on the L1
8055          * page tables), using walk_addr(), when injecting PFs to L1.
8056          */
8057         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
8058                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
8059         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
8060                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
8061
8062         if (cpu_has_secondary_exec_ctrls()) {
8063                 exec_control = vmx_secondary_exec_control(vmx);
8064                 if (!vmx->rdtscp_enabled)
8065                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
8066                 /* Take the following fields only from vmcs12 */
8067                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8068                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
8069                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
8070                 if (nested_cpu_has(vmcs12,
8071                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
8072                         exec_control |= vmcs12->secondary_vm_exec_control;
8073
8074                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
8075                         /*
8076                          * Translate L1 physical address to host physical
8077                          * address for vmcs02. Keep the page pinned, so this
8078                          * physical address remains valid. We keep a reference
8079                          * to it so we can release it later.
8080                          */
8081                         if (vmx->nested.apic_access_page) /* shouldn't happen */
8082                                 nested_release_page(vmx->nested.apic_access_page);
8083                         vmx->nested.apic_access_page =
8084                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
8085                         /*
8086                          * If translation failed, no matter: This feature asks
8087                          * to exit when accessing the given address, and if it
8088                          * can never be accessed, this feature won't do
8089                          * anything anyway.
8090                          */
8091                         if (!vmx->nested.apic_access_page)
8092                                 exec_control &=
8093                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8094                         else
8095                                 vmcs_write64(APIC_ACCESS_ADDR,
8096                                   page_to_phys(vmx->nested.apic_access_page));
8097                 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
8098                         exec_control |=
8099                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8100                         vmcs_write64(APIC_ACCESS_ADDR,
8101                                 page_to_phys(vcpu->kvm->arch.apic_access_page));
8102                 }
8103
8104                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
8105         }
8106
8107
8108         /*
8109          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
8110          * Some constant fields are set here by vmx_set_constant_host_state().
8111          * Other fields are different per CPU, and will be set later when
8112          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
8113          */
8114         vmx_set_constant_host_state(vmx);
8115
8116         /*
8117          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
8118          * entry, but only if the current (host) sp changed from the value
8119          * we wrote last (vmx->host_rsp). This cache is no longer relevant
8120          * if we switch vmcs, and rather than hold a separate cache per vmcs,
8121          * here we just force the write to happen on entry.
8122          */
8123         vmx->host_rsp = 0;
8124
8125         exec_control = vmx_exec_control(vmx); /* L0's desires */
8126         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
8127         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
8128         exec_control &= ~CPU_BASED_TPR_SHADOW;
8129         exec_control |= vmcs12->cpu_based_vm_exec_control;
8130         /*
8131          * Merging of IO and MSR bitmaps not currently supported.
8132          * Rather, exit every time.
8133          */
8134         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
8135         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
8136         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
8137
8138         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
8139
8140         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
8141          * bitwise-or of what L1 wants to trap for L2, and what we want to
8142          * trap. Note that CR0.TS also needs updating - we do this later.
8143          */
8144         update_exception_bitmap(vcpu);
8145         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
8146         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8147
8148         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
8149          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
8150          * bits are further modified by vmx_set_efer() below.
8151          */
8152         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8153
8154         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
8155          * emulated by vmx_set_efer(), below.
8156          */
8157         vm_entry_controls_init(vmx,
8158                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
8159                         ~VM_ENTRY_IA32E_MODE) |
8160                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
8161
8162         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
8163                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
8164                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
8165         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
8166                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
8167
8168
8169         set_cr4_guest_host_mask(vmx);
8170
8171         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
8172                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
8173
8174         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
8175                 vmcs_write64(TSC_OFFSET,
8176                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
8177         else
8178                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8179
8180         if (enable_vpid) {
8181                 /*
8182                  * Trivially support vpid by letting L2s share their parent
8183                  * L1's vpid. TODO: move to a more elaborate solution, giving
8184                  * each L2 its own vpid and exposing the vpid feature to L1.
8185                  */
8186                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
8187                 vmx_flush_tlb(vcpu);
8188         }
8189
8190         if (nested_cpu_has_ept(vmcs12)) {
8191                 kvm_mmu_unload(vcpu);
8192                 nested_ept_init_mmu_context(vcpu);
8193         }
8194
8195         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
8196                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
8197         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
8198                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8199         else
8200                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8201         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
8202         vmx_set_efer(vcpu, vcpu->arch.efer);
8203
8204         /*
8205          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
8206          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
8207          * The CR0_READ_SHADOW is what L2 should have expected to read given
8208          * the specifications by L1; It's not enough to take
8209          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8210          * have more bits than L1 expected.
8211          */
8212         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
8213         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
8214
8215         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
8216         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
8217
8218         /* shadow page tables on either EPT or shadow page tables */
8219         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
8220         kvm_mmu_reset_context(vcpu);
8221
8222         if (!enable_ept)
8223                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
8224
8225         /*
8226          * L1 may access the L2's PDPTR, so save them to construct vmcs12
8227          */
8228         if (enable_ept) {
8229                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
8230                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
8231                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
8232                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
8233         }
8234
8235         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
8236         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
8237 }
8238
8239 /*
8240  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8241  * for running an L2 nested guest.
8242  */
8243 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
8244 {
8245         struct vmcs12 *vmcs12;
8246         struct vcpu_vmx *vmx = to_vmx(vcpu);
8247         int cpu;
8248         struct loaded_vmcs *vmcs02;
8249         bool ia32e;
8250
8251         if (!nested_vmx_check_permission(vcpu) ||
8252             !nested_vmx_check_vmcs12(vcpu))
8253                 return 1;
8254
8255         skip_emulated_instruction(vcpu);
8256         vmcs12 = get_vmcs12(vcpu);
8257
8258         if (enable_shadow_vmcs)
8259                 copy_shadow_to_vmcs12(vmx);
8260
8261         /*
8262          * The nested entry process starts with enforcing various prerequisites
8263          * on vmcs12 as required by the Intel SDM, and act appropriately when
8264          * they fail: As the SDM explains, some conditions should cause the
8265          * instruction to fail, while others will cause the instruction to seem
8266          * to succeed, but return an EXIT_REASON_INVALID_STATE.
8267          * To speed up the normal (success) code path, we should avoid checking
8268          * for misconfigurations which will anyway be caught by the processor
8269          * when using the merged vmcs02.
8270          */
8271         if (vmcs12->launch_state == launch) {
8272                 nested_vmx_failValid(vcpu,
8273                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8274                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
8275                 return 1;
8276         }
8277
8278         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8279             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
8280                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8281                 return 1;
8282         }
8283
8284         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
8285                         !PAGE_ALIGNED(vmcs12->msr_bitmap)) {
8286                 /*TODO: Also verify bits beyond physical address width are 0*/
8287                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8288                 return 1;
8289         }
8290
8291         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
8292                         !PAGE_ALIGNED(vmcs12->apic_access_addr)) {
8293                 /*TODO: Also verify bits beyond physical address width are 0*/
8294                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8295                 return 1;
8296         }
8297
8298         if (vmcs12->vm_entry_msr_load_count > 0 ||
8299             vmcs12->vm_exit_msr_load_count > 0 ||
8300             vmcs12->vm_exit_msr_store_count > 0) {
8301                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8302                                     __func__);
8303                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8304                 return 1;
8305         }
8306
8307         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
8308                                 nested_vmx_true_procbased_ctls_low,
8309                                 nested_vmx_procbased_ctls_high) ||
8310             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8311               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8312             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8313               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8314             !vmx_control_verify(vmcs12->vm_exit_controls,
8315                                 nested_vmx_true_exit_ctls_low,
8316                                 nested_vmx_exit_ctls_high) ||
8317             !vmx_control_verify(vmcs12->vm_entry_controls,
8318                                 nested_vmx_true_entry_ctls_low,
8319                                 nested_vmx_entry_ctls_high))
8320         {
8321                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8322                 return 1;
8323         }
8324
8325         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8326             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8327                 nested_vmx_failValid(vcpu,
8328                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8329                 return 1;
8330         }
8331
8332         if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
8333             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8334                 nested_vmx_entry_failure(vcpu, vmcs12,
8335                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8336                 return 1;
8337         }
8338         if (vmcs12->vmcs_link_pointer != -1ull) {
8339                 nested_vmx_entry_failure(vcpu, vmcs12,
8340                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8341                 return 1;
8342         }
8343
8344         /*
8345          * If the load IA32_EFER VM-entry control is 1, the following checks
8346          * are performed on the field for the IA32_EFER MSR:
8347          * - Bits reserved in the IA32_EFER MSR must be 0.
8348          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8349          *   the IA-32e mode guest VM-exit control. It must also be identical
8350          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8351          *   CR0.PG) is 1.
8352          */
8353         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8354                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8355                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8356                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8357                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8358                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8359                         nested_vmx_entry_failure(vcpu, vmcs12,
8360                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8361                         return 1;
8362                 }
8363         }
8364
8365         /*
8366          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8367          * IA32_EFER MSR must be 0 in the field for that register. In addition,
8368          * the values of the LMA and LME bits in the field must each be that of
8369          * the host address-space size VM-exit control.
8370          */
8371         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8372                 ia32e = (vmcs12->vm_exit_controls &
8373                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8374                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8375                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8376                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8377                         nested_vmx_entry_failure(vcpu, vmcs12,
8378                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8379                         return 1;
8380                 }
8381         }
8382
8383         /*
8384          * We're finally done with prerequisite checking, and can start with
8385          * the nested entry.
8386          */
8387
8388         vmcs02 = nested_get_current_vmcs02(vmx);
8389         if (!vmcs02)
8390                 return -ENOMEM;
8391
8392         enter_guest_mode(vcpu);
8393
8394         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8395
8396         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
8397                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8398
8399         cpu = get_cpu();
8400         vmx->loaded_vmcs = vmcs02;
8401         vmx_vcpu_put(vcpu);
8402         vmx_vcpu_load(vcpu, cpu);
8403         vcpu->cpu = cpu;
8404         put_cpu();
8405
8406         vmx_segment_cache_clear(vmx);
8407
8408         vmcs12->launch_state = 1;
8409
8410         prepare_vmcs02(vcpu, vmcs12);
8411
8412         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8413                 return kvm_emulate_halt(vcpu);
8414
8415         vmx->nested.nested_run_pending = 1;
8416
8417         /*
8418          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8419          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8420          * returned as far as L1 is concerned. It will only return (and set
8421          * the success flag) when L2 exits (see nested_vmx_vmexit()).
8422          */
8423         return 1;
8424 }
8425
8426 /*
8427  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8428  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8429  * This function returns the new value we should put in vmcs12.guest_cr0.
8430  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8431  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8432  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8433  *     didn't trap the bit, because if L1 did, so would L0).
8434  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8435  *     been modified by L2, and L1 knows it. So just leave the old value of
8436  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8437  *     isn't relevant, because if L0 traps this bit it can set it to anything.
8438  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8439  *     changed these bits, and therefore they need to be updated, but L0
8440  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8441  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8442  */
8443 static inline unsigned long
8444 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8445 {
8446         return
8447         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8448         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8449         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8450                         vcpu->arch.cr0_guest_owned_bits));
8451 }
8452
8453 static inline unsigned long
8454 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8455 {
8456         return
8457         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8458         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8459         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8460                         vcpu->arch.cr4_guest_owned_bits));
8461 }
8462
8463 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8464                                        struct vmcs12 *vmcs12)
8465 {
8466         u32 idt_vectoring;
8467         unsigned int nr;
8468
8469         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
8470                 nr = vcpu->arch.exception.nr;
8471                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8472
8473                 if (kvm_exception_is_soft(nr)) {
8474                         vmcs12->vm_exit_instruction_len =
8475                                 vcpu->arch.event_exit_inst_len;
8476                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8477                 } else
8478                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8479
8480                 if (vcpu->arch.exception.has_error_code) {
8481                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8482                         vmcs12->idt_vectoring_error_code =
8483                                 vcpu->arch.exception.error_code;
8484                 }
8485
8486                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8487         } else if (vcpu->arch.nmi_injected) {
8488                 vmcs12->idt_vectoring_info_field =
8489                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8490         } else if (vcpu->arch.interrupt.pending) {
8491                 nr = vcpu->arch.interrupt.nr;
8492                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8493
8494                 if (vcpu->arch.interrupt.soft) {
8495                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
8496                         vmcs12->vm_entry_instruction_len =
8497                                 vcpu->arch.event_exit_inst_len;
8498                 } else
8499                         idt_vectoring |= INTR_TYPE_EXT_INTR;
8500
8501                 vmcs12->idt_vectoring_info_field = idt_vectoring;
8502         }
8503 }
8504
8505 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8506 {
8507         struct vcpu_vmx *vmx = to_vmx(vcpu);
8508
8509         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8510             vmx->nested.preemption_timer_expired) {
8511                 if (vmx->nested.nested_run_pending)
8512                         return -EBUSY;
8513                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8514                 return 0;
8515         }
8516
8517         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
8518                 if (vmx->nested.nested_run_pending ||
8519                     vcpu->arch.interrupt.pending)
8520                         return -EBUSY;
8521                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8522                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
8523                                   INTR_INFO_VALID_MASK, 0);
8524                 /*
8525                  * The NMI-triggered VM exit counts as injection:
8526                  * clear this one and block further NMIs.
8527                  */
8528                 vcpu->arch.nmi_pending = 0;
8529                 vmx_set_nmi_mask(vcpu, true);
8530                 return 0;
8531         }
8532
8533         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8534             nested_exit_on_intr(vcpu)) {
8535                 if (vmx->nested.nested_run_pending)
8536                         return -EBUSY;
8537                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8538         }
8539
8540         return 0;
8541 }
8542
8543 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8544 {
8545         ktime_t remaining =
8546                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8547         u64 value;
8548
8549         if (ktime_to_ns(remaining) <= 0)
8550                 return 0;
8551
8552         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8553         do_div(value, 1000000);
8554         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8555 }
8556
8557 /*
8558  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8559  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8560  * and this function updates it to reflect the changes to the guest state while
8561  * L2 was running (and perhaps made some exits which were handled directly by L0
8562  * without going back to L1), and to reflect the exit reason.
8563  * Note that we do not have to copy here all VMCS fields, just those that
8564  * could have changed by the L2 guest or the exit - i.e., the guest-state and
8565  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8566  * which already writes to vmcs12 directly.
8567  */
8568 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8569                            u32 exit_reason, u32 exit_intr_info,
8570                            unsigned long exit_qualification)
8571 {
8572         /* update guest state fields: */
8573         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8574         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8575
8576         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8577         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8578         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8579
8580         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8581         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8582         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8583         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8584         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8585         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8586         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8587         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8588         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8589         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8590         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8591         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8592         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8593         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8594         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8595         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8596         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8597         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8598         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8599         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8600         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8601         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8602         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8603         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8604         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8605         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8606         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8607         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8608         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8609         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8610         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8611         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8612         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8613         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8614         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8615         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8616
8617         vmcs12->guest_interruptibility_info =
8618                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8619         vmcs12->guest_pending_dbg_exceptions =
8620                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8621         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8622                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8623         else
8624                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
8625
8626         if (nested_cpu_has_preemption_timer(vmcs12)) {
8627                 if (vmcs12->vm_exit_controls &
8628                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8629                         vmcs12->vmx_preemption_timer_value =
8630                                 vmx_get_preemption_timer_value(vcpu);
8631                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8632         }
8633
8634         /*
8635          * In some cases (usually, nested EPT), L2 is allowed to change its
8636          * own CR3 without exiting. If it has changed it, we must keep it.
8637          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8638          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8639          *
8640          * Additionally, restore L2's PDPTR to vmcs12.
8641          */
8642         if (enable_ept) {
8643                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8644                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8645                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8646                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8647                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8648         }
8649
8650         vmcs12->vm_entry_controls =
8651                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8652                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
8653
8654         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
8655                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8656                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8657         }
8658
8659         /* TODO: These cannot have changed unless we have MSR bitmaps and
8660          * the relevant bit asks not to trap the change */
8661         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
8662                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
8663         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8664                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
8665         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8666         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8667         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8668         if (vmx_mpx_supported())
8669                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
8670
8671         /* update exit information fields: */
8672
8673         vmcs12->vm_exit_reason = exit_reason;
8674         vmcs12->exit_qualification = exit_qualification;
8675
8676         vmcs12->vm_exit_intr_info = exit_intr_info;
8677         if ((vmcs12->vm_exit_intr_info &
8678              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8679             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8680                 vmcs12->vm_exit_intr_error_code =
8681                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
8682         vmcs12->idt_vectoring_info_field = 0;
8683         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8684         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8685
8686         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8687                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8688                  * instead of reading the real value. */
8689                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
8690
8691                 /*
8692                  * Transfer the event that L0 or L1 may wanted to inject into
8693                  * L2 to IDT_VECTORING_INFO_FIELD.
8694                  */
8695                 vmcs12_save_pending_event(vcpu, vmcs12);
8696         }
8697
8698         /*
8699          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8700          * preserved above and would only end up incorrectly in L1.
8701          */
8702         vcpu->arch.nmi_injected = false;
8703         kvm_clear_exception_queue(vcpu);
8704         kvm_clear_interrupt_queue(vcpu);
8705 }
8706
8707 /*
8708  * A part of what we need to when the nested L2 guest exits and we want to
8709  * run its L1 parent, is to reset L1's guest state to the host state specified
8710  * in vmcs12.
8711  * This function is to be called not only on normal nested exit, but also on
8712  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8713  * Failures During or After Loading Guest State").
8714  * This function should be called when the active VMCS is L1's (vmcs01).
8715  */
8716 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8717                                    struct vmcs12 *vmcs12)
8718 {
8719         struct kvm_segment seg;
8720
8721         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8722                 vcpu->arch.efer = vmcs12->host_ia32_efer;
8723         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8724                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8725         else
8726                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8727         vmx_set_efer(vcpu, vcpu->arch.efer);
8728
8729         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8730         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
8731         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
8732         /*
8733          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8734          * actually changed, because it depends on the current state of
8735          * fpu_active (which may have changed).
8736          * Note that vmx_set_cr0 refers to efer set above.
8737          */
8738         vmx_set_cr0(vcpu, vmcs12->host_cr0);
8739         /*
8740          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8741          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8742          * but we also need to update cr0_guest_host_mask and exception_bitmap.
8743          */
8744         update_exception_bitmap(vcpu);
8745         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8746         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8747
8748         /*
8749          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8750          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8751          */
8752         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8753         kvm_set_cr4(vcpu, vmcs12->host_cr4);
8754
8755         nested_ept_uninit_mmu_context(vcpu);
8756
8757         kvm_set_cr3(vcpu, vmcs12->host_cr3);
8758         kvm_mmu_reset_context(vcpu);
8759
8760         if (!enable_ept)
8761                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8762
8763         if (enable_vpid) {
8764                 /*
8765                  * Trivially support vpid by letting L2s share their parent
8766                  * L1's vpid. TODO: move to a more elaborate solution, giving
8767                  * each L2 its own vpid and exposing the vpid feature to L1.
8768                  */
8769                 vmx_flush_tlb(vcpu);
8770         }
8771
8772
8773         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8774         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8775         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8776         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8777         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
8778
8779         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
8780         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
8781                 vmcs_write64(GUEST_BNDCFGS, 0);
8782
8783         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
8784                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8785                 vcpu->arch.pat = vmcs12->host_ia32_pat;
8786         }
8787         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8788                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8789                         vmcs12->host_ia32_perf_global_ctrl);
8790
8791         /* Set L1 segment info according to Intel SDM
8792             27.5.2 Loading Host Segment and Descriptor-Table Registers */
8793         seg = (struct kvm_segment) {
8794                 .base = 0,
8795                 .limit = 0xFFFFFFFF,
8796                 .selector = vmcs12->host_cs_selector,
8797                 .type = 11,
8798                 .present = 1,
8799                 .s = 1,
8800                 .g = 1
8801         };
8802         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8803                 seg.l = 1;
8804         else
8805                 seg.db = 1;
8806         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8807         seg = (struct kvm_segment) {
8808                 .base = 0,
8809                 .limit = 0xFFFFFFFF,
8810                 .type = 3,
8811                 .present = 1,
8812                 .s = 1,
8813                 .db = 1,
8814                 .g = 1
8815         };
8816         seg.selector = vmcs12->host_ds_selector;
8817         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8818         seg.selector = vmcs12->host_es_selector;
8819         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8820         seg.selector = vmcs12->host_ss_selector;
8821         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8822         seg.selector = vmcs12->host_fs_selector;
8823         seg.base = vmcs12->host_fs_base;
8824         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8825         seg.selector = vmcs12->host_gs_selector;
8826         seg.base = vmcs12->host_gs_base;
8827         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8828         seg = (struct kvm_segment) {
8829                 .base = vmcs12->host_tr_base,
8830                 .limit = 0x67,
8831                 .selector = vmcs12->host_tr_selector,
8832                 .type = 11,
8833                 .present = 1
8834         };
8835         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8836
8837         kvm_set_dr(vcpu, 7, 0x400);
8838         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
8839 }
8840
8841 /*
8842  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8843  * and modify vmcs12 to make it see what it would expect to see there if
8844  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8845  */
8846 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8847                               u32 exit_intr_info,
8848                               unsigned long exit_qualification)
8849 {
8850         struct vcpu_vmx *vmx = to_vmx(vcpu);
8851         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8852
8853         /* trying to cancel vmlaunch/vmresume is a bug */
8854         WARN_ON_ONCE(vmx->nested.nested_run_pending);
8855
8856         leave_guest_mode(vcpu);
8857         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8858                        exit_qualification);
8859
8860         vmx_load_vmcs01(vcpu);
8861
8862         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
8863             && nested_exit_intr_ack_set(vcpu)) {
8864                 int irq = kvm_cpu_get_interrupt(vcpu);
8865                 WARN_ON(irq < 0);
8866                 vmcs12->vm_exit_intr_info = irq |
8867                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
8868         }
8869
8870         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8871                                        vmcs12->exit_qualification,
8872                                        vmcs12->idt_vectoring_info_field,
8873                                        vmcs12->vm_exit_intr_info,
8874                                        vmcs12->vm_exit_intr_error_code,
8875                                        KVM_ISA_VMX);
8876
8877         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8878         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
8879         vmx_segment_cache_clear(vmx);
8880
8881         /* if no vmcs02 cache requested, remove the one we used */
8882         if (VMCS02_POOL_SIZE == 0)
8883                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8884
8885         load_vmcs12_host_state(vcpu, vmcs12);
8886
8887         /* Update TSC_OFFSET if TSC was changed while L2 ran */
8888         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8889
8890         /* This is needed for same reason as it was needed in prepare_vmcs02 */
8891         vmx->host_rsp = 0;
8892
8893         /* Unpin physical memory we referred to in vmcs02 */
8894         if (vmx->nested.apic_access_page) {
8895                 nested_release_page(vmx->nested.apic_access_page);
8896                 vmx->nested.apic_access_page = 0;
8897         }
8898
8899         /*
8900          * Exiting from L2 to L1, we're now back to L1 which thinks it just
8901          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8902          * success or failure flag accordingly.
8903          */
8904         if (unlikely(vmx->fail)) {
8905                 vmx->fail = 0;
8906                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8907         } else
8908                 nested_vmx_succeed(vcpu);
8909         if (enable_shadow_vmcs)
8910                 vmx->nested.sync_shadow_vmcs = true;
8911
8912         /* in case we halted in L2 */
8913         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8914 }
8915
8916 /*
8917  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8918  */
8919 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
8920 {
8921         if (is_guest_mode(vcpu))
8922                 nested_vmx_vmexit(vcpu, -1, 0, 0);
8923         free_nested(to_vmx(vcpu));
8924 }
8925
8926 /*
8927  * L1's failure to enter L2 is a subset of a normal exit, as explained in
8928  * 23.7 "VM-entry failures during or after loading guest state" (this also
8929  * lists the acceptable exit-reason and exit-qualification parameters).
8930  * It should only be called before L2 actually succeeded to run, and when
8931  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8932  */
8933 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8934                         struct vmcs12 *vmcs12,
8935                         u32 reason, unsigned long qualification)
8936 {
8937         load_vmcs12_host_state(vcpu, vmcs12);
8938         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8939         vmcs12->exit_qualification = qualification;
8940         nested_vmx_succeed(vcpu);
8941         if (enable_shadow_vmcs)
8942                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
8943 }
8944
8945 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8946                                struct x86_instruction_info *info,
8947                                enum x86_intercept_stage stage)
8948 {
8949         return X86EMUL_CONTINUE;
8950 }
8951
8952 void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
8953 {
8954         if (ple_gap)
8955                 shrink_ple_window(vcpu);
8956 }
8957
8958 static struct kvm_x86_ops vmx_x86_ops = {
8959         .cpu_has_kvm_support = cpu_has_kvm_support,
8960         .disabled_by_bios = vmx_disabled_by_bios,
8961         .hardware_setup = hardware_setup,
8962         .hardware_unsetup = hardware_unsetup,
8963         .check_processor_compatibility = vmx_check_processor_compat,
8964         .hardware_enable = hardware_enable,
8965         .hardware_disable = hardware_disable,
8966         .cpu_has_accelerated_tpr = report_flexpriority,
8967
8968         .vcpu_create = vmx_create_vcpu,
8969         .vcpu_free = vmx_free_vcpu,
8970         .vcpu_reset = vmx_vcpu_reset,
8971
8972         .prepare_guest_switch = vmx_save_host_state,
8973         .vcpu_load = vmx_vcpu_load,
8974         .vcpu_put = vmx_vcpu_put,
8975
8976         .update_db_bp_intercept = update_exception_bitmap,
8977         .get_msr = vmx_get_msr,
8978         .set_msr = vmx_set_msr,
8979         .get_segment_base = vmx_get_segment_base,
8980         .get_segment = vmx_get_segment,
8981         .set_segment = vmx_set_segment,
8982         .get_cpl = vmx_get_cpl,
8983         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
8984         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
8985         .decache_cr3 = vmx_decache_cr3,
8986         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
8987         .set_cr0 = vmx_set_cr0,
8988         .set_cr3 = vmx_set_cr3,
8989         .set_cr4 = vmx_set_cr4,
8990         .set_efer = vmx_set_efer,
8991         .get_idt = vmx_get_idt,
8992         .set_idt = vmx_set_idt,
8993         .get_gdt = vmx_get_gdt,
8994         .set_gdt = vmx_set_gdt,
8995         .get_dr6 = vmx_get_dr6,
8996         .set_dr6 = vmx_set_dr6,
8997         .set_dr7 = vmx_set_dr7,
8998         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
8999         .cache_reg = vmx_cache_reg,
9000         .get_rflags = vmx_get_rflags,
9001         .set_rflags = vmx_set_rflags,
9002         .fpu_deactivate = vmx_fpu_deactivate,
9003
9004         .tlb_flush = vmx_flush_tlb,
9005
9006         .run = vmx_vcpu_run,
9007         .handle_exit = vmx_handle_exit,
9008         .skip_emulated_instruction = skip_emulated_instruction,
9009         .set_interrupt_shadow = vmx_set_interrupt_shadow,
9010         .get_interrupt_shadow = vmx_get_interrupt_shadow,
9011         .patch_hypercall = vmx_patch_hypercall,
9012         .set_irq = vmx_inject_irq,
9013         .set_nmi = vmx_inject_nmi,
9014         .queue_exception = vmx_queue_exception,
9015         .cancel_injection = vmx_cancel_injection,
9016         .interrupt_allowed = vmx_interrupt_allowed,
9017         .nmi_allowed = vmx_nmi_allowed,
9018         .get_nmi_mask = vmx_get_nmi_mask,
9019         .set_nmi_mask = vmx_set_nmi_mask,
9020         .enable_nmi_window = enable_nmi_window,
9021         .enable_irq_window = enable_irq_window,
9022         .update_cr8_intercept = update_cr8_intercept,
9023         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
9024         .vm_has_apicv = vmx_vm_has_apicv,
9025         .load_eoi_exitmap = vmx_load_eoi_exitmap,
9026         .hwapic_irr_update = vmx_hwapic_irr_update,
9027         .hwapic_isr_update = vmx_hwapic_isr_update,
9028         .sync_pir_to_irr = vmx_sync_pir_to_irr,
9029         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
9030
9031         .set_tss_addr = vmx_set_tss_addr,
9032         .get_tdp_level = get_ept_level,
9033         .get_mt_mask = vmx_get_mt_mask,
9034
9035         .get_exit_info = vmx_get_exit_info,
9036
9037         .get_lpage_level = vmx_get_lpage_level,
9038
9039         .cpuid_update = vmx_cpuid_update,
9040
9041         .rdtscp_supported = vmx_rdtscp_supported,
9042         .invpcid_supported = vmx_invpcid_supported,
9043
9044         .set_supported_cpuid = vmx_set_supported_cpuid,
9045
9046         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
9047
9048         .set_tsc_khz = vmx_set_tsc_khz,
9049         .read_tsc_offset = vmx_read_tsc_offset,
9050         .write_tsc_offset = vmx_write_tsc_offset,
9051         .adjust_tsc_offset = vmx_adjust_tsc_offset,
9052         .compute_tsc_offset = vmx_compute_tsc_offset,
9053         .read_l1_tsc = vmx_read_l1_tsc,
9054
9055         .set_tdp_cr3 = vmx_set_cr3,
9056
9057         .check_intercept = vmx_check_intercept,
9058         .handle_external_intr = vmx_handle_external_intr,
9059         .mpx_supported = vmx_mpx_supported,
9060
9061         .check_nested_events = vmx_check_nested_events,
9062
9063         .sched_in = vmx_sched_in,
9064 };
9065
9066 static int __init vmx_init(void)
9067 {
9068         int r, i, msr;
9069
9070         rdmsrl_safe(MSR_EFER, &host_efer);
9071
9072         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
9073                 kvm_define_shared_msr(i, vmx_msr_index[i]);
9074
9075         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
9076         if (!vmx_io_bitmap_a)
9077                 return -ENOMEM;
9078
9079         r = -ENOMEM;
9080
9081         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
9082         if (!vmx_io_bitmap_b)
9083                 goto out;
9084
9085         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
9086         if (!vmx_msr_bitmap_legacy)
9087                 goto out1;
9088
9089         vmx_msr_bitmap_legacy_x2apic =
9090                                 (unsigned long *)__get_free_page(GFP_KERNEL);
9091         if (!vmx_msr_bitmap_legacy_x2apic)
9092                 goto out2;
9093
9094         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
9095         if (!vmx_msr_bitmap_longmode)
9096                 goto out3;
9097
9098         vmx_msr_bitmap_longmode_x2apic =
9099                                 (unsigned long *)__get_free_page(GFP_KERNEL);
9100         if (!vmx_msr_bitmap_longmode_x2apic)
9101                 goto out4;
9102         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
9103         if (!vmx_vmread_bitmap)
9104                 goto out5;
9105
9106         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
9107         if (!vmx_vmwrite_bitmap)
9108                 goto out6;
9109
9110         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
9111         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
9112
9113         /*
9114          * Allow direct access to the PC debug port (it is often used for I/O
9115          * delays, but the vmexits simply slow things down).
9116          */
9117         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
9118         clear_bit(0x80, vmx_io_bitmap_a);
9119
9120         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
9121
9122         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
9123         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
9124
9125         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
9126
9127         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
9128                      __alignof__(struct vcpu_vmx), THIS_MODULE);
9129         if (r)
9130                 goto out7;
9131
9132 #ifdef CONFIG_KEXEC
9133         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
9134                            crash_vmclear_local_loaded_vmcss);
9135 #endif
9136
9137         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
9138         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
9139         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
9140         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
9141         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
9142         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
9143         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
9144
9145         memcpy(vmx_msr_bitmap_legacy_x2apic,
9146                         vmx_msr_bitmap_legacy, PAGE_SIZE);
9147         memcpy(vmx_msr_bitmap_longmode_x2apic,
9148                         vmx_msr_bitmap_longmode, PAGE_SIZE);
9149
9150         if (enable_apicv) {
9151                 for (msr = 0x800; msr <= 0x8ff; msr++)
9152                         vmx_disable_intercept_msr_read_x2apic(msr);
9153
9154                 /* According SDM, in x2apic mode, the whole id reg is used.
9155                  * But in KVM, it only use the highest eight bits. Need to
9156                  * intercept it */
9157                 vmx_enable_intercept_msr_read_x2apic(0x802);
9158                 /* TMCCT */
9159                 vmx_enable_intercept_msr_read_x2apic(0x839);
9160                 /* TPR */
9161                 vmx_disable_intercept_msr_write_x2apic(0x808);
9162                 /* EOI */
9163                 vmx_disable_intercept_msr_write_x2apic(0x80b);
9164                 /* SELF-IPI */
9165                 vmx_disable_intercept_msr_write_x2apic(0x83f);
9166         }
9167
9168         if (enable_ept) {
9169                 kvm_mmu_set_mask_ptes(0ull,
9170                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
9171                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
9172                         0ull, VMX_EPT_EXECUTABLE_MASK);
9173                 ept_set_mmio_spte_mask();
9174                 kvm_enable_tdp();
9175         } else
9176                 kvm_disable_tdp();
9177
9178         update_ple_window_actual_max();
9179
9180         return 0;
9181
9182 out7:
9183         free_page((unsigned long)vmx_vmwrite_bitmap);
9184 out6:
9185         free_page((unsigned long)vmx_vmread_bitmap);
9186 out5:
9187         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
9188 out4:
9189         free_page((unsigned long)vmx_msr_bitmap_longmode);
9190 out3:
9191         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
9192 out2:
9193         free_page((unsigned long)vmx_msr_bitmap_legacy);
9194 out1:
9195         free_page((unsigned long)vmx_io_bitmap_b);
9196 out:
9197         free_page((unsigned long)vmx_io_bitmap_a);
9198         return r;
9199 }
9200
9201 static void __exit vmx_exit(void)
9202 {
9203         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
9204         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
9205         free_page((unsigned long)vmx_msr_bitmap_legacy);
9206         free_page((unsigned long)vmx_msr_bitmap_longmode);
9207         free_page((unsigned long)vmx_io_bitmap_b);
9208         free_page((unsigned long)vmx_io_bitmap_a);
9209         free_page((unsigned long)vmx_vmwrite_bitmap);
9210         free_page((unsigned long)vmx_vmread_bitmap);
9211
9212 #ifdef CONFIG_KEXEC
9213         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
9214         synchronize_rcu();
9215 #endif
9216
9217         kvm_exit();
9218 }
9219
9220 module_init(vmx_init)
9221 module_exit(vmx_exit)