2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
38 #include <asm/virtext.h>
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
47 MODULE_AUTHOR("Qumranet");
48 MODULE_LICENSE("GPL");
50 static int __read_mostly bypass_guest_pf = 1;
51 module_param(bypass_guest_pf, bool, S_IRUGO);
53 static int __read_mostly enable_vpid = 1;
54 module_param_named(vpid, enable_vpid, bool, 0444);
56 static int __read_mostly flexpriority_enabled = 1;
57 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
59 static int __read_mostly enable_ept = 1;
60 module_param_named(ept, enable_ept, bool, S_IRUGO);
62 static int __read_mostly enable_unrestricted_guest = 1;
63 module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
66 static int __read_mostly emulate_invalid_guest_state = 0;
67 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
69 static int __read_mostly vmm_exclusive = 1;
70 module_param(vmm_exclusive, bool, S_IRUGO);
72 static int __read_mostly yield_on_hlt = 1;
73 module_param(yield_on_hlt, bool, S_IRUGO);
75 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
76 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
77 #define KVM_GUEST_CR0_MASK \
78 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
79 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
80 (X86_CR0_WP | X86_CR0_NE)
81 #define KVM_VM_CR0_ALWAYS_ON \
82 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
83 #define KVM_CR4_GUEST_OWNED_BITS \
84 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
87 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
88 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
90 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
93 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
94 * ple_gap: upper bound on the amount of time between two successive
95 * executions of PAUSE in a loop. Also indicate if ple enabled.
96 * According to test, this time is usually smaller than 128 cycles.
97 * ple_window: upper bound on the amount of time a guest is allowed to execute
98 * in a PAUSE loop. Tests indicate that most spinlocks are held for
99 * less than 2^12 cycles
100 * Time is measured based on a counter that runs at the same rate as the TSC,
101 * refer SDM volume 3b section 21.6.13 & 22.1.3.
103 #define KVM_VMX_DEFAULT_PLE_GAP 128
104 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
105 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
106 module_param(ple_gap, int, S_IRUGO);
108 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
109 module_param(ple_window, int, S_IRUGO);
111 #define NR_AUTOLOAD_MSRS 1
119 struct shared_msr_entry {
126 struct kvm_vcpu vcpu;
127 struct list_head local_vcpus_link;
128 unsigned long host_rsp;
132 u32 idt_vectoring_info;
133 struct shared_msr_entry *guest_msrs;
137 u64 msr_host_kernel_gs_base;
138 u64 msr_guest_kernel_gs_base;
141 struct msr_autoload {
143 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
144 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
148 u16 fs_sel, gs_sel, ldt_sel;
149 int gs_ldt_reload_needed;
150 int fs_reload_needed;
155 struct kvm_save_segment {
160 } tr, es, ds, fs, gs;
163 bool emulation_required;
165 /* Support for vnmi-less CPUs */
166 int soft_vnmi_blocked;
168 s64 vnmi_blocked_time;
174 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
176 return container_of(vcpu, struct vcpu_vmx, vcpu);
179 static u64 construct_eptp(unsigned long root_hpa);
180 static void kvm_cpu_vmxon(u64 addr);
181 static void kvm_cpu_vmxoff(void);
182 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
184 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
185 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
186 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
187 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
189 static unsigned long *vmx_io_bitmap_a;
190 static unsigned long *vmx_io_bitmap_b;
191 static unsigned long *vmx_msr_bitmap_legacy;
192 static unsigned long *vmx_msr_bitmap_longmode;
194 static bool cpu_has_load_ia32_efer;
196 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
197 static DEFINE_SPINLOCK(vmx_vpid_lock);
199 static struct vmcs_config {
203 u32 pin_based_exec_ctrl;
204 u32 cpu_based_exec_ctrl;
205 u32 cpu_based_2nd_exec_ctrl;
210 static struct vmx_capability {
215 #define VMX_SEGMENT_FIELD(seg) \
216 [VCPU_SREG_##seg] = { \
217 .selector = GUEST_##seg##_SELECTOR, \
218 .base = GUEST_##seg##_BASE, \
219 .limit = GUEST_##seg##_LIMIT, \
220 .ar_bytes = GUEST_##seg##_AR_BYTES, \
223 static struct kvm_vmx_segment_field {
228 } kvm_vmx_segment_fields[] = {
229 VMX_SEGMENT_FIELD(CS),
230 VMX_SEGMENT_FIELD(DS),
231 VMX_SEGMENT_FIELD(ES),
232 VMX_SEGMENT_FIELD(FS),
233 VMX_SEGMENT_FIELD(GS),
234 VMX_SEGMENT_FIELD(SS),
235 VMX_SEGMENT_FIELD(TR),
236 VMX_SEGMENT_FIELD(LDTR),
239 static u64 host_efer;
241 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
244 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
245 * away by decrementing the array size.
247 static const u32 vmx_msr_index[] = {
249 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
251 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
253 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
255 static inline bool is_page_fault(u32 intr_info)
257 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
258 INTR_INFO_VALID_MASK)) ==
259 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
262 static inline bool is_no_device(u32 intr_info)
264 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
265 INTR_INFO_VALID_MASK)) ==
266 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
269 static inline bool is_invalid_opcode(u32 intr_info)
271 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
272 INTR_INFO_VALID_MASK)) ==
273 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
276 static inline bool is_external_interrupt(u32 intr_info)
278 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
279 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
282 static inline bool is_machine_check(u32 intr_info)
284 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
285 INTR_INFO_VALID_MASK)) ==
286 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
289 static inline bool cpu_has_vmx_msr_bitmap(void)
291 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
294 static inline bool cpu_has_vmx_tpr_shadow(void)
296 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
299 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
301 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
304 static inline bool cpu_has_secondary_exec_ctrls(void)
306 return vmcs_config.cpu_based_exec_ctrl &
307 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
310 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
312 return vmcs_config.cpu_based_2nd_exec_ctrl &
313 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
316 static inline bool cpu_has_vmx_flexpriority(void)
318 return cpu_has_vmx_tpr_shadow() &&
319 cpu_has_vmx_virtualize_apic_accesses();
322 static inline bool cpu_has_vmx_ept_execute_only(void)
324 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
327 static inline bool cpu_has_vmx_eptp_uncacheable(void)
329 return vmx_capability.ept & VMX_EPTP_UC_BIT;
332 static inline bool cpu_has_vmx_eptp_writeback(void)
334 return vmx_capability.ept & VMX_EPTP_WB_BIT;
337 static inline bool cpu_has_vmx_ept_2m_page(void)
339 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
342 static inline bool cpu_has_vmx_ept_1g_page(void)
344 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
347 static inline bool cpu_has_vmx_ept_4levels(void)
349 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
352 static inline bool cpu_has_vmx_invept_individual_addr(void)
354 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
357 static inline bool cpu_has_vmx_invept_context(void)
359 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
362 static inline bool cpu_has_vmx_invept_global(void)
364 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
367 static inline bool cpu_has_vmx_invvpid_single(void)
369 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
372 static inline bool cpu_has_vmx_invvpid_global(void)
374 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
377 static inline bool cpu_has_vmx_ept(void)
379 return vmcs_config.cpu_based_2nd_exec_ctrl &
380 SECONDARY_EXEC_ENABLE_EPT;
383 static inline bool cpu_has_vmx_unrestricted_guest(void)
385 return vmcs_config.cpu_based_2nd_exec_ctrl &
386 SECONDARY_EXEC_UNRESTRICTED_GUEST;
389 static inline bool cpu_has_vmx_ple(void)
391 return vmcs_config.cpu_based_2nd_exec_ctrl &
392 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
395 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
397 return flexpriority_enabled && irqchip_in_kernel(kvm);
400 static inline bool cpu_has_vmx_vpid(void)
402 return vmcs_config.cpu_based_2nd_exec_ctrl &
403 SECONDARY_EXEC_ENABLE_VPID;
406 static inline bool cpu_has_vmx_rdtscp(void)
408 return vmcs_config.cpu_based_2nd_exec_ctrl &
409 SECONDARY_EXEC_RDTSCP;
412 static inline bool cpu_has_virtual_nmis(void)
414 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
417 static inline bool cpu_has_vmx_wbinvd_exit(void)
419 return vmcs_config.cpu_based_2nd_exec_ctrl &
420 SECONDARY_EXEC_WBINVD_EXITING;
423 static inline bool report_flexpriority(void)
425 return flexpriority_enabled;
428 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
432 for (i = 0; i < vmx->nmsrs; ++i)
433 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
438 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
444 } operand = { vpid, 0, gva };
446 asm volatile (__ex(ASM_VMX_INVVPID)
447 /* CF==1 or ZF==1 --> rc = -1 */
449 : : "a"(&operand), "c"(ext) : "cc", "memory");
452 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
456 } operand = {eptp, gpa};
458 asm volatile (__ex(ASM_VMX_INVEPT)
459 /* CF==1 or ZF==1 --> rc = -1 */
460 "; ja 1f ; ud2 ; 1:\n"
461 : : "a" (&operand), "c" (ext) : "cc", "memory");
464 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
468 i = __find_msr_index(vmx, msr);
470 return &vmx->guest_msrs[i];
474 static void vmcs_clear(struct vmcs *vmcs)
476 u64 phys_addr = __pa(vmcs);
479 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
480 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
483 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
487 static void vmcs_load(struct vmcs *vmcs)
489 u64 phys_addr = __pa(vmcs);
492 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
493 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
496 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
500 static void __vcpu_clear(void *arg)
502 struct vcpu_vmx *vmx = arg;
503 int cpu = raw_smp_processor_id();
505 if (vmx->vcpu.cpu == cpu)
506 vmcs_clear(vmx->vmcs);
507 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
508 per_cpu(current_vmcs, cpu) = NULL;
509 list_del(&vmx->local_vcpus_link);
514 static void vcpu_clear(struct vcpu_vmx *vmx)
516 if (vmx->vcpu.cpu == -1)
518 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
521 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
526 if (cpu_has_vmx_invvpid_single())
527 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
530 static inline void vpid_sync_vcpu_global(void)
532 if (cpu_has_vmx_invvpid_global())
533 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
536 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
538 if (cpu_has_vmx_invvpid_single())
539 vpid_sync_vcpu_single(vmx);
541 vpid_sync_vcpu_global();
544 static inline void ept_sync_global(void)
546 if (cpu_has_vmx_invept_global())
547 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
550 static inline void ept_sync_context(u64 eptp)
553 if (cpu_has_vmx_invept_context())
554 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
560 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
563 if (cpu_has_vmx_invept_individual_addr())
564 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
567 ept_sync_context(eptp);
571 static unsigned long vmcs_readl(unsigned long field)
573 unsigned long value = 0;
575 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
576 : "+a"(value) : "d"(field) : "cc");
580 static u16 vmcs_read16(unsigned long field)
582 return vmcs_readl(field);
585 static u32 vmcs_read32(unsigned long field)
587 return vmcs_readl(field);
590 static u64 vmcs_read64(unsigned long field)
593 return vmcs_readl(field);
595 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
599 static noinline void vmwrite_error(unsigned long field, unsigned long value)
601 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
602 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
606 static void vmcs_writel(unsigned long field, unsigned long value)
610 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
611 : "=q"(error) : "a"(value), "d"(field) : "cc");
613 vmwrite_error(field, value);
616 static void vmcs_write16(unsigned long field, u16 value)
618 vmcs_writel(field, value);
621 static void vmcs_write32(unsigned long field, u32 value)
623 vmcs_writel(field, value);
626 static void vmcs_write64(unsigned long field, u64 value)
628 vmcs_writel(field, value);
629 #ifndef CONFIG_X86_64
631 vmcs_writel(field+1, value >> 32);
635 static void vmcs_clear_bits(unsigned long field, u32 mask)
637 vmcs_writel(field, vmcs_readl(field) & ~mask);
640 static void vmcs_set_bits(unsigned long field, u32 mask)
642 vmcs_writel(field, vmcs_readl(field) | mask);
645 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
649 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
650 (1u << NM_VECTOR) | (1u << DB_VECTOR);
651 if ((vcpu->guest_debug &
652 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
653 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
654 eb |= 1u << BP_VECTOR;
655 if (to_vmx(vcpu)->rmode.vm86_active)
658 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
659 if (vcpu->fpu_active)
660 eb &= ~(1u << NM_VECTOR);
661 vmcs_write32(EXCEPTION_BITMAP, eb);
664 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
667 struct msr_autoload *m = &vmx->msr_autoload;
669 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
670 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
671 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
675 for (i = 0; i < m->nr; ++i)
676 if (m->guest[i].index == msr)
682 m->guest[i] = m->guest[m->nr];
683 m->host[i] = m->host[m->nr];
684 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
685 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
688 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
689 u64 guest_val, u64 host_val)
692 struct msr_autoload *m = &vmx->msr_autoload;
694 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
695 vmcs_write64(GUEST_IA32_EFER, guest_val);
696 vmcs_write64(HOST_IA32_EFER, host_val);
697 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
698 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
702 for (i = 0; i < m->nr; ++i)
703 if (m->guest[i].index == msr)
708 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
709 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
712 m->guest[i].index = msr;
713 m->guest[i].value = guest_val;
714 m->host[i].index = msr;
715 m->host[i].value = host_val;
718 static void reload_tss(void)
721 * VT restores TR but not its size. Useless.
723 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
724 struct desc_struct *descs;
726 descs = (void *)gdt->address;
727 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
731 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
736 guest_efer = vmx->vcpu.arch.efer;
739 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
742 ignore_bits = EFER_NX | EFER_SCE;
744 ignore_bits |= EFER_LMA | EFER_LME;
745 /* SCE is meaningful only in long mode on Intel */
746 if (guest_efer & EFER_LMA)
747 ignore_bits &= ~(u64)EFER_SCE;
749 guest_efer &= ~ignore_bits;
750 guest_efer |= host_efer & ignore_bits;
751 vmx->guest_msrs[efer_offset].data = guest_efer;
752 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
754 clear_atomic_switch_msr(vmx, MSR_EFER);
755 /* On ept, can't emulate nx, and must switch nx atomically */
756 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
757 guest_efer = vmx->vcpu.arch.efer;
758 if (!(guest_efer & EFER_LMA))
759 guest_efer &= ~EFER_LME;
760 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
767 static unsigned long segment_base(u16 selector)
769 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
770 struct desc_struct *d;
771 unsigned long table_base;
774 if (!(selector & ~3))
777 table_base = gdt->address;
779 if (selector & 4) { /* from ldt */
780 u16 ldt_selector = kvm_read_ldt();
782 if (!(ldt_selector & ~3))
785 table_base = segment_base(ldt_selector);
787 d = (struct desc_struct *)(table_base + (selector & ~7));
788 v = get_desc_base(d);
790 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
791 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
796 static inline unsigned long kvm_read_tr_base(void)
799 asm("str %0" : "=g"(tr));
800 return segment_base(tr);
803 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
805 struct vcpu_vmx *vmx = to_vmx(vcpu);
808 if (vmx->host_state.loaded)
811 vmx->host_state.loaded = 1;
813 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
814 * allow segment selectors with cpl > 0 or ti == 1.
816 vmx->host_state.ldt_sel = kvm_read_ldt();
817 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
818 savesegment(fs, vmx->host_state.fs_sel);
819 if (!(vmx->host_state.fs_sel & 7)) {
820 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
821 vmx->host_state.fs_reload_needed = 0;
823 vmcs_write16(HOST_FS_SELECTOR, 0);
824 vmx->host_state.fs_reload_needed = 1;
826 savesegment(gs, vmx->host_state.gs_sel);
827 if (!(vmx->host_state.gs_sel & 7))
828 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
830 vmcs_write16(HOST_GS_SELECTOR, 0);
831 vmx->host_state.gs_ldt_reload_needed = 1;
835 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
836 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
838 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
839 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
843 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
844 if (is_long_mode(&vmx->vcpu))
845 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
847 for (i = 0; i < vmx->save_nmsrs; ++i)
848 kvm_set_shared_msr(vmx->guest_msrs[i].index,
849 vmx->guest_msrs[i].data,
850 vmx->guest_msrs[i].mask);
853 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
855 if (!vmx->host_state.loaded)
858 ++vmx->vcpu.stat.host_state_reload;
859 vmx->host_state.loaded = 0;
861 if (is_long_mode(&vmx->vcpu))
862 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
864 if (vmx->host_state.gs_ldt_reload_needed) {
865 kvm_load_ldt(vmx->host_state.ldt_sel);
867 load_gs_index(vmx->host_state.gs_sel);
869 loadsegment(gs, vmx->host_state.gs_sel);
872 if (vmx->host_state.fs_reload_needed)
873 loadsegment(fs, vmx->host_state.fs_sel);
876 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
878 if (current_thread_info()->status & TS_USEDFPU)
880 load_gdt(&__get_cpu_var(host_gdt));
883 static void vmx_load_host_state(struct vcpu_vmx *vmx)
886 __vmx_load_host_state(vmx);
891 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
892 * vcpu mutex is already taken.
894 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
896 struct vcpu_vmx *vmx = to_vmx(vcpu);
897 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
900 kvm_cpu_vmxon(phys_addr);
901 else if (vcpu->cpu != cpu)
904 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
905 per_cpu(current_vmcs, cpu) = vmx->vmcs;
906 vmcs_load(vmx->vmcs);
909 if (vcpu->cpu != cpu) {
910 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
911 unsigned long sysenter_esp;
913 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
915 list_add(&vmx->local_vcpus_link,
916 &per_cpu(vcpus_on_cpu, cpu));
920 * Linux uses per-cpu TSS and GDT, so set these when switching
923 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
924 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
926 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
927 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
931 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
933 __vmx_load_host_state(to_vmx(vcpu));
934 if (!vmm_exclusive) {
935 __vcpu_clear(to_vmx(vcpu));
940 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
944 if (vcpu->fpu_active)
946 vcpu->fpu_active = 1;
947 cr0 = vmcs_readl(GUEST_CR0);
948 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
949 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
950 vmcs_writel(GUEST_CR0, cr0);
951 update_exception_bitmap(vcpu);
952 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
953 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
956 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
958 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
960 vmx_decache_cr0_guest_bits(vcpu);
961 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
962 update_exception_bitmap(vcpu);
963 vcpu->arch.cr0_guest_owned_bits = 0;
964 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
965 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
968 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
970 unsigned long rflags, save_rflags;
972 rflags = vmcs_readl(GUEST_RFLAGS);
973 if (to_vmx(vcpu)->rmode.vm86_active) {
974 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
975 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
976 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
981 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
983 if (to_vmx(vcpu)->rmode.vm86_active) {
984 to_vmx(vcpu)->rmode.save_rflags = rflags;
985 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
987 vmcs_writel(GUEST_RFLAGS, rflags);
990 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
992 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
995 if (interruptibility & GUEST_INTR_STATE_STI)
996 ret |= KVM_X86_SHADOW_INT_STI;
997 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
998 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1003 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1005 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1006 u32 interruptibility = interruptibility_old;
1008 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1010 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1011 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1012 else if (mask & KVM_X86_SHADOW_INT_STI)
1013 interruptibility |= GUEST_INTR_STATE_STI;
1015 if ((interruptibility != interruptibility_old))
1016 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1019 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1023 rip = kvm_rip_read(vcpu);
1024 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1025 kvm_rip_write(vcpu, rip);
1027 /* skipping an emulated instruction also counts */
1028 vmx_set_interrupt_shadow(vcpu, 0);
1031 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1033 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1034 * explicitly skip the instruction because if the HLT state is set, then
1035 * the instruction is already executing and RIP has already been
1037 if (!yield_on_hlt &&
1038 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1039 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1042 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1043 bool has_error_code, u32 error_code,
1046 struct vcpu_vmx *vmx = to_vmx(vcpu);
1047 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1049 if (has_error_code) {
1050 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1051 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1054 if (vmx->rmode.vm86_active) {
1055 if (kvm_inject_realmode_interrupt(vcpu, nr) != EMULATE_DONE)
1056 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1060 if (kvm_exception_is_soft(nr)) {
1061 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1062 vmx->vcpu.arch.event_exit_inst_len);
1063 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1065 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1067 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1068 vmx_clear_hlt(vcpu);
1071 static bool vmx_rdtscp_supported(void)
1073 return cpu_has_vmx_rdtscp();
1077 * Swap MSR entry in host/guest MSR entry array.
1079 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1081 struct shared_msr_entry tmp;
1083 tmp = vmx->guest_msrs[to];
1084 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1085 vmx->guest_msrs[from] = tmp;
1089 * Set up the vmcs to automatically save and restore system
1090 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1091 * mode, as fiddling with msrs is very expensive.
1093 static void setup_msrs(struct vcpu_vmx *vmx)
1095 int save_nmsrs, index;
1096 unsigned long *msr_bitmap;
1098 vmx_load_host_state(vmx);
1100 #ifdef CONFIG_X86_64
1101 if (is_long_mode(&vmx->vcpu)) {
1102 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1104 move_msr_up(vmx, index, save_nmsrs++);
1105 index = __find_msr_index(vmx, MSR_LSTAR);
1107 move_msr_up(vmx, index, save_nmsrs++);
1108 index = __find_msr_index(vmx, MSR_CSTAR);
1110 move_msr_up(vmx, index, save_nmsrs++);
1111 index = __find_msr_index(vmx, MSR_TSC_AUX);
1112 if (index >= 0 && vmx->rdtscp_enabled)
1113 move_msr_up(vmx, index, save_nmsrs++);
1115 * MSR_STAR is only needed on long mode guests, and only
1116 * if efer.sce is enabled.
1118 index = __find_msr_index(vmx, MSR_STAR);
1119 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1120 move_msr_up(vmx, index, save_nmsrs++);
1123 index = __find_msr_index(vmx, MSR_EFER);
1124 if (index >= 0 && update_transition_efer(vmx, index))
1125 move_msr_up(vmx, index, save_nmsrs++);
1127 vmx->save_nmsrs = save_nmsrs;
1129 if (cpu_has_vmx_msr_bitmap()) {
1130 if (is_long_mode(&vmx->vcpu))
1131 msr_bitmap = vmx_msr_bitmap_longmode;
1133 msr_bitmap = vmx_msr_bitmap_legacy;
1135 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1140 * reads and returns guest's timestamp counter "register"
1141 * guest_tsc = host_tsc + tsc_offset -- 21.3
1143 static u64 guest_read_tsc(void)
1145 u64 host_tsc, tsc_offset;
1148 tsc_offset = vmcs_read64(TSC_OFFSET);
1149 return host_tsc + tsc_offset;
1153 * writes 'offset' into guest's timestamp counter offset register
1155 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1157 vmcs_write64(TSC_OFFSET, offset);
1160 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1162 u64 offset = vmcs_read64(TSC_OFFSET);
1163 vmcs_write64(TSC_OFFSET, offset + adjustment);
1167 * Reads an msr value (of 'msr_index') into 'pdata'.
1168 * Returns 0 on success, non-0 otherwise.
1169 * Assumes vcpu_load() was already called.
1171 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1174 struct shared_msr_entry *msr;
1177 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1181 switch (msr_index) {
1182 #ifdef CONFIG_X86_64
1184 data = vmcs_readl(GUEST_FS_BASE);
1187 data = vmcs_readl(GUEST_GS_BASE);
1189 case MSR_KERNEL_GS_BASE:
1190 vmx_load_host_state(to_vmx(vcpu));
1191 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1195 return kvm_get_msr_common(vcpu, msr_index, pdata);
1197 data = guest_read_tsc();
1199 case MSR_IA32_SYSENTER_CS:
1200 data = vmcs_read32(GUEST_SYSENTER_CS);
1202 case MSR_IA32_SYSENTER_EIP:
1203 data = vmcs_readl(GUEST_SYSENTER_EIP);
1205 case MSR_IA32_SYSENTER_ESP:
1206 data = vmcs_readl(GUEST_SYSENTER_ESP);
1209 if (!to_vmx(vcpu)->rdtscp_enabled)
1211 /* Otherwise falls through */
1213 vmx_load_host_state(to_vmx(vcpu));
1214 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1216 vmx_load_host_state(to_vmx(vcpu));
1220 return kvm_get_msr_common(vcpu, msr_index, pdata);
1228 * Writes msr value into into the appropriate "register".
1229 * Returns 0 on success, non-0 otherwise.
1230 * Assumes vcpu_load() was already called.
1232 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1234 struct vcpu_vmx *vmx = to_vmx(vcpu);
1235 struct shared_msr_entry *msr;
1238 switch (msr_index) {
1240 vmx_load_host_state(vmx);
1241 ret = kvm_set_msr_common(vcpu, msr_index, data);
1243 #ifdef CONFIG_X86_64
1245 vmcs_writel(GUEST_FS_BASE, data);
1248 vmcs_writel(GUEST_GS_BASE, data);
1250 case MSR_KERNEL_GS_BASE:
1251 vmx_load_host_state(vmx);
1252 vmx->msr_guest_kernel_gs_base = data;
1255 case MSR_IA32_SYSENTER_CS:
1256 vmcs_write32(GUEST_SYSENTER_CS, data);
1258 case MSR_IA32_SYSENTER_EIP:
1259 vmcs_writel(GUEST_SYSENTER_EIP, data);
1261 case MSR_IA32_SYSENTER_ESP:
1262 vmcs_writel(GUEST_SYSENTER_ESP, data);
1265 kvm_write_tsc(vcpu, data);
1267 case MSR_IA32_CR_PAT:
1268 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1269 vmcs_write64(GUEST_IA32_PAT, data);
1270 vcpu->arch.pat = data;
1273 ret = kvm_set_msr_common(vcpu, msr_index, data);
1276 if (!vmx->rdtscp_enabled)
1278 /* Check reserved bit, higher 32 bits should be zero */
1279 if ((data >> 32) != 0)
1281 /* Otherwise falls through */
1283 msr = find_msr_entry(vmx, msr_index);
1285 vmx_load_host_state(vmx);
1289 ret = kvm_set_msr_common(vcpu, msr_index, data);
1295 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1297 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1300 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1303 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1305 case VCPU_EXREG_PDPTR:
1307 ept_save_pdptrs(vcpu);
1314 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1316 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1317 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1319 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1321 update_exception_bitmap(vcpu);
1324 static __init int cpu_has_kvm_support(void)
1326 return cpu_has_vmx();
1329 static __init int vmx_disabled_by_bios(void)
1333 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1334 if (msr & FEATURE_CONTROL_LOCKED) {
1335 /* launched w/ TXT and VMX disabled */
1336 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1339 /* launched w/o TXT and VMX only enabled w/ TXT */
1340 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1341 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1342 && !tboot_enabled()) {
1343 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
1344 "activate TXT before enabling KVM\n");
1347 /* launched w/o TXT and VMX disabled */
1348 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1349 && !tboot_enabled())
1356 static void kvm_cpu_vmxon(u64 addr)
1358 asm volatile (ASM_VMX_VMXON_RAX
1359 : : "a"(&addr), "m"(addr)
1363 static int hardware_enable(void *garbage)
1365 int cpu = raw_smp_processor_id();
1366 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1369 if (read_cr4() & X86_CR4_VMXE)
1372 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1373 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1375 test_bits = FEATURE_CONTROL_LOCKED;
1376 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1377 if (tboot_enabled())
1378 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1380 if ((old & test_bits) != test_bits) {
1381 /* enable and lock */
1382 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1384 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1386 if (vmm_exclusive) {
1387 kvm_cpu_vmxon(phys_addr);
1391 store_gdt(&__get_cpu_var(host_gdt));
1396 static void vmclear_local_vcpus(void)
1398 int cpu = raw_smp_processor_id();
1399 struct vcpu_vmx *vmx, *n;
1401 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1407 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1410 static void kvm_cpu_vmxoff(void)
1412 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1415 static void hardware_disable(void *garbage)
1417 if (vmm_exclusive) {
1418 vmclear_local_vcpus();
1421 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1424 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1425 u32 msr, u32 *result)
1427 u32 vmx_msr_low, vmx_msr_high;
1428 u32 ctl = ctl_min | ctl_opt;
1430 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1432 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1433 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1435 /* Ensure minimum (required) set of control bits are supported. */
1443 static __init bool allow_1_setting(u32 msr, u32 ctl)
1445 u32 vmx_msr_low, vmx_msr_high;
1447 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1448 return vmx_msr_high & ctl;
1451 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1453 u32 vmx_msr_low, vmx_msr_high;
1454 u32 min, opt, min2, opt2;
1455 u32 _pin_based_exec_control = 0;
1456 u32 _cpu_based_exec_control = 0;
1457 u32 _cpu_based_2nd_exec_control = 0;
1458 u32 _vmexit_control = 0;
1459 u32 _vmentry_control = 0;
1461 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1462 opt = PIN_BASED_VIRTUAL_NMIS;
1463 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1464 &_pin_based_exec_control) < 0)
1468 #ifdef CONFIG_X86_64
1469 CPU_BASED_CR8_LOAD_EXITING |
1470 CPU_BASED_CR8_STORE_EXITING |
1472 CPU_BASED_CR3_LOAD_EXITING |
1473 CPU_BASED_CR3_STORE_EXITING |
1474 CPU_BASED_USE_IO_BITMAPS |
1475 CPU_BASED_MOV_DR_EXITING |
1476 CPU_BASED_USE_TSC_OFFSETING |
1477 CPU_BASED_MWAIT_EXITING |
1478 CPU_BASED_MONITOR_EXITING |
1479 CPU_BASED_INVLPG_EXITING;
1482 min |= CPU_BASED_HLT_EXITING;
1484 opt = CPU_BASED_TPR_SHADOW |
1485 CPU_BASED_USE_MSR_BITMAPS |
1486 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1487 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1488 &_cpu_based_exec_control) < 0)
1490 #ifdef CONFIG_X86_64
1491 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1492 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1493 ~CPU_BASED_CR8_STORE_EXITING;
1495 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1497 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1498 SECONDARY_EXEC_WBINVD_EXITING |
1499 SECONDARY_EXEC_ENABLE_VPID |
1500 SECONDARY_EXEC_ENABLE_EPT |
1501 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1502 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1503 SECONDARY_EXEC_RDTSCP;
1504 if (adjust_vmx_controls(min2, opt2,
1505 MSR_IA32_VMX_PROCBASED_CTLS2,
1506 &_cpu_based_2nd_exec_control) < 0)
1509 #ifndef CONFIG_X86_64
1510 if (!(_cpu_based_2nd_exec_control &
1511 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1512 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1514 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1515 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1517 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1518 CPU_BASED_CR3_STORE_EXITING |
1519 CPU_BASED_INVLPG_EXITING);
1520 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1521 vmx_capability.ept, vmx_capability.vpid);
1525 #ifdef CONFIG_X86_64
1526 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1528 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1529 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1530 &_vmexit_control) < 0)
1534 opt = VM_ENTRY_LOAD_IA32_PAT;
1535 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1536 &_vmentry_control) < 0)
1539 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1541 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1542 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1545 #ifdef CONFIG_X86_64
1546 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1547 if (vmx_msr_high & (1u<<16))
1551 /* Require Write-Back (WB) memory type for VMCS accesses. */
1552 if (((vmx_msr_high >> 18) & 15) != 6)
1555 vmcs_conf->size = vmx_msr_high & 0x1fff;
1556 vmcs_conf->order = get_order(vmcs_config.size);
1557 vmcs_conf->revision_id = vmx_msr_low;
1559 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1560 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1561 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1562 vmcs_conf->vmexit_ctrl = _vmexit_control;
1563 vmcs_conf->vmentry_ctrl = _vmentry_control;
1565 cpu_has_load_ia32_efer =
1566 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
1567 VM_ENTRY_LOAD_IA32_EFER)
1568 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
1569 VM_EXIT_LOAD_IA32_EFER);
1574 static struct vmcs *alloc_vmcs_cpu(int cpu)
1576 int node = cpu_to_node(cpu);
1580 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1583 vmcs = page_address(pages);
1584 memset(vmcs, 0, vmcs_config.size);
1585 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1589 static struct vmcs *alloc_vmcs(void)
1591 return alloc_vmcs_cpu(raw_smp_processor_id());
1594 static void free_vmcs(struct vmcs *vmcs)
1596 free_pages((unsigned long)vmcs, vmcs_config.order);
1599 static void free_kvm_area(void)
1603 for_each_possible_cpu(cpu) {
1604 free_vmcs(per_cpu(vmxarea, cpu));
1605 per_cpu(vmxarea, cpu) = NULL;
1609 static __init int alloc_kvm_area(void)
1613 for_each_possible_cpu(cpu) {
1616 vmcs = alloc_vmcs_cpu(cpu);
1622 per_cpu(vmxarea, cpu) = vmcs;
1627 static __init int hardware_setup(void)
1629 if (setup_vmcs_config(&vmcs_config) < 0)
1632 if (boot_cpu_has(X86_FEATURE_NX))
1633 kvm_enable_efer_bits(EFER_NX);
1635 if (!cpu_has_vmx_vpid())
1638 if (!cpu_has_vmx_ept() ||
1639 !cpu_has_vmx_ept_4levels()) {
1641 enable_unrestricted_guest = 0;
1644 if (!cpu_has_vmx_unrestricted_guest())
1645 enable_unrestricted_guest = 0;
1647 if (!cpu_has_vmx_flexpriority())
1648 flexpriority_enabled = 0;
1650 if (!cpu_has_vmx_tpr_shadow())
1651 kvm_x86_ops->update_cr8_intercept = NULL;
1653 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1654 kvm_disable_largepages();
1656 if (!cpu_has_vmx_ple())
1659 return alloc_kvm_area();
1662 static __exit void hardware_unsetup(void)
1667 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1669 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1671 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1672 vmcs_write16(sf->selector, save->selector);
1673 vmcs_writel(sf->base, save->base);
1674 vmcs_write32(sf->limit, save->limit);
1675 vmcs_write32(sf->ar_bytes, save->ar);
1677 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1679 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1683 static void enter_pmode(struct kvm_vcpu *vcpu)
1685 unsigned long flags;
1686 struct vcpu_vmx *vmx = to_vmx(vcpu);
1688 vmx->emulation_required = 1;
1689 vmx->rmode.vm86_active = 0;
1691 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
1692 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1693 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1694 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1696 flags = vmcs_readl(GUEST_RFLAGS);
1697 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1698 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1699 vmcs_writel(GUEST_RFLAGS, flags);
1701 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1702 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1704 update_exception_bitmap(vcpu);
1706 if (emulate_invalid_guest_state)
1709 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1710 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1711 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1712 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1714 vmcs_write16(GUEST_SS_SELECTOR, 0);
1715 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1717 vmcs_write16(GUEST_CS_SELECTOR,
1718 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1719 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1722 static gva_t rmode_tss_base(struct kvm *kvm)
1724 if (!kvm->arch.tss_addr) {
1725 struct kvm_memslots *slots;
1728 slots = kvm_memslots(kvm);
1729 base_gfn = slots->memslots[0].base_gfn +
1730 kvm->memslots->memslots[0].npages - 3;
1731 return base_gfn << PAGE_SHIFT;
1733 return kvm->arch.tss_addr;
1736 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1738 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1740 save->selector = vmcs_read16(sf->selector);
1741 save->base = vmcs_readl(sf->base);
1742 save->limit = vmcs_read32(sf->limit);
1743 save->ar = vmcs_read32(sf->ar_bytes);
1744 vmcs_write16(sf->selector, save->base >> 4);
1745 vmcs_write32(sf->base, save->base & 0xffff0);
1746 vmcs_write32(sf->limit, 0xffff);
1747 vmcs_write32(sf->ar_bytes, 0xf3);
1748 if (save->base & 0xf)
1749 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
1750 " aligned when entering protected mode (seg=%d)",
1754 static void enter_rmode(struct kvm_vcpu *vcpu)
1756 unsigned long flags;
1757 struct vcpu_vmx *vmx = to_vmx(vcpu);
1759 if (enable_unrestricted_guest)
1762 vmx->emulation_required = 1;
1763 vmx->rmode.vm86_active = 1;
1765 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
1766 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1767 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1769 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1770 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1772 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1773 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1775 flags = vmcs_readl(GUEST_RFLAGS);
1776 vmx->rmode.save_rflags = flags;
1778 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1780 vmcs_writel(GUEST_RFLAGS, flags);
1781 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1782 update_exception_bitmap(vcpu);
1784 if (emulate_invalid_guest_state)
1785 goto continue_rmode;
1787 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1788 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1789 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1791 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1792 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1793 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1794 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1795 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1797 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1798 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1799 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1800 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1803 kvm_mmu_reset_context(vcpu);
1806 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1808 struct vcpu_vmx *vmx = to_vmx(vcpu);
1809 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1815 * Force kernel_gs_base reloading before EFER changes, as control
1816 * of this msr depends on is_long_mode().
1818 vmx_load_host_state(to_vmx(vcpu));
1819 vcpu->arch.efer = efer;
1820 if (efer & EFER_LMA) {
1821 vmcs_write32(VM_ENTRY_CONTROLS,
1822 vmcs_read32(VM_ENTRY_CONTROLS) |
1823 VM_ENTRY_IA32E_MODE);
1826 vmcs_write32(VM_ENTRY_CONTROLS,
1827 vmcs_read32(VM_ENTRY_CONTROLS) &
1828 ~VM_ENTRY_IA32E_MODE);
1830 msr->data = efer & ~EFER_LME;
1835 #ifdef CONFIG_X86_64
1837 static void enter_lmode(struct kvm_vcpu *vcpu)
1841 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1842 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1843 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1845 vmcs_write32(GUEST_TR_AR_BYTES,
1846 (guest_tr_ar & ~AR_TYPE_MASK)
1847 | AR_TYPE_BUSY_64_TSS);
1849 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
1852 static void exit_lmode(struct kvm_vcpu *vcpu)
1854 vmcs_write32(VM_ENTRY_CONTROLS,
1855 vmcs_read32(VM_ENTRY_CONTROLS)
1856 & ~VM_ENTRY_IA32E_MODE);
1857 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
1862 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1864 vpid_sync_context(to_vmx(vcpu));
1866 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1868 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1872 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1874 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1876 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1877 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1880 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
1882 if (enable_ept && is_paging(vcpu))
1883 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1884 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
1887 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1889 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1891 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1892 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1895 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1897 if (!test_bit(VCPU_EXREG_PDPTR,
1898 (unsigned long *)&vcpu->arch.regs_dirty))
1901 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1902 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
1903 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
1904 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
1905 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1909 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1911 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1912 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1913 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1914 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1915 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1918 __set_bit(VCPU_EXREG_PDPTR,
1919 (unsigned long *)&vcpu->arch.regs_avail);
1920 __set_bit(VCPU_EXREG_PDPTR,
1921 (unsigned long *)&vcpu->arch.regs_dirty);
1924 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1926 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1928 struct kvm_vcpu *vcpu)
1930 vmx_decache_cr3(vcpu);
1931 if (!(cr0 & X86_CR0_PG)) {
1932 /* From paging/starting to nonpaging */
1933 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1934 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1935 (CPU_BASED_CR3_LOAD_EXITING |
1936 CPU_BASED_CR3_STORE_EXITING));
1937 vcpu->arch.cr0 = cr0;
1938 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1939 } else if (!is_paging(vcpu)) {
1940 /* From nonpaging to paging */
1941 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1942 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1943 ~(CPU_BASED_CR3_LOAD_EXITING |
1944 CPU_BASED_CR3_STORE_EXITING));
1945 vcpu->arch.cr0 = cr0;
1946 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1949 if (!(cr0 & X86_CR0_WP))
1950 *hw_cr0 &= ~X86_CR0_WP;
1953 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1955 struct vcpu_vmx *vmx = to_vmx(vcpu);
1956 unsigned long hw_cr0;
1958 if (enable_unrestricted_guest)
1959 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1960 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1962 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1964 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1967 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1970 #ifdef CONFIG_X86_64
1971 if (vcpu->arch.efer & EFER_LME) {
1972 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1974 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1980 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1982 if (!vcpu->fpu_active)
1983 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1985 vmcs_writel(CR0_READ_SHADOW, cr0);
1986 vmcs_writel(GUEST_CR0, hw_cr0);
1987 vcpu->arch.cr0 = cr0;
1990 static u64 construct_eptp(unsigned long root_hpa)
1994 /* TODO write the value reading from MSR */
1995 eptp = VMX_EPT_DEFAULT_MT |
1996 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1997 eptp |= (root_hpa & PAGE_MASK);
2002 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2004 unsigned long guest_cr3;
2009 eptp = construct_eptp(cr3);
2010 vmcs_write64(EPT_POINTER, eptp);
2011 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
2012 vcpu->kvm->arch.ept_identity_map_addr;
2013 ept_load_pdptrs(vcpu);
2016 vmx_flush_tlb(vcpu);
2017 vmcs_writel(GUEST_CR3, guest_cr3);
2020 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2022 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
2023 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2025 vcpu->arch.cr4 = cr4;
2027 if (!is_paging(vcpu)) {
2028 hw_cr4 &= ~X86_CR4_PAE;
2029 hw_cr4 |= X86_CR4_PSE;
2030 } else if (!(cr4 & X86_CR4_PAE)) {
2031 hw_cr4 &= ~X86_CR4_PAE;
2035 vmcs_writel(CR4_READ_SHADOW, cr4);
2036 vmcs_writel(GUEST_CR4, hw_cr4);
2039 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2040 struct kvm_segment *var, int seg)
2042 struct vcpu_vmx *vmx = to_vmx(vcpu);
2043 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2044 struct kvm_save_segment *save;
2047 if (vmx->rmode.vm86_active
2048 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2049 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2050 || seg == VCPU_SREG_GS)
2051 && !emulate_invalid_guest_state) {
2053 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2054 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2055 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2056 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2057 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2060 var->selector = save->selector;
2061 var->base = save->base;
2062 var->limit = save->limit;
2064 if (seg == VCPU_SREG_TR
2065 || var->selector == vmcs_read16(sf->selector))
2066 goto use_saved_rmode_seg;
2068 var->base = vmcs_readl(sf->base);
2069 var->limit = vmcs_read32(sf->limit);
2070 var->selector = vmcs_read16(sf->selector);
2071 ar = vmcs_read32(sf->ar_bytes);
2072 use_saved_rmode_seg:
2073 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2075 var->type = ar & 15;
2076 var->s = (ar >> 4) & 1;
2077 var->dpl = (ar >> 5) & 3;
2078 var->present = (ar >> 7) & 1;
2079 var->avl = (ar >> 12) & 1;
2080 var->l = (ar >> 13) & 1;
2081 var->db = (ar >> 14) & 1;
2082 var->g = (ar >> 15) & 1;
2083 var->unusable = (ar >> 16) & 1;
2086 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2088 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2089 struct kvm_segment s;
2091 if (to_vmx(vcpu)->rmode.vm86_active) {
2092 vmx_get_segment(vcpu, &s, seg);
2095 return vmcs_readl(sf->base);
2098 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2100 if (!is_protmode(vcpu))
2103 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2106 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2109 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2116 ar = var->type & 15;
2117 ar |= (var->s & 1) << 4;
2118 ar |= (var->dpl & 3) << 5;
2119 ar |= (var->present & 1) << 7;
2120 ar |= (var->avl & 1) << 12;
2121 ar |= (var->l & 1) << 13;
2122 ar |= (var->db & 1) << 14;
2123 ar |= (var->g & 1) << 15;
2125 if (ar == 0) /* a 0 value means unusable */
2126 ar = AR_UNUSABLE_MASK;
2131 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2132 struct kvm_segment *var, int seg)
2134 struct vcpu_vmx *vmx = to_vmx(vcpu);
2135 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2138 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2139 vmcs_write16(sf->selector, var->selector);
2140 vmx->rmode.tr.selector = var->selector;
2141 vmx->rmode.tr.base = var->base;
2142 vmx->rmode.tr.limit = var->limit;
2143 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2146 vmcs_writel(sf->base, var->base);
2147 vmcs_write32(sf->limit, var->limit);
2148 vmcs_write16(sf->selector, var->selector);
2149 if (vmx->rmode.vm86_active && var->s) {
2151 * Hack real-mode segments into vm86 compatibility.
2153 if (var->base == 0xffff0000 && var->selector == 0xf000)
2154 vmcs_writel(sf->base, 0xf0000);
2157 ar = vmx_segment_access_rights(var);
2160 * Fix the "Accessed" bit in AR field of segment registers for older
2162 * IA32 arch specifies that at the time of processor reset the
2163 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2164 * is setting it to 0 in the usedland code. This causes invalid guest
2165 * state vmexit when "unrestricted guest" mode is turned on.
2166 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2167 * tree. Newer qemu binaries with that qemu fix would not need this
2170 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2171 ar |= 0x1; /* Accessed */
2173 vmcs_write32(sf->ar_bytes, ar);
2176 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2178 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2180 *db = (ar >> 14) & 1;
2181 *l = (ar >> 13) & 1;
2184 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2186 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2187 dt->address = vmcs_readl(GUEST_IDTR_BASE);
2190 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2192 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2193 vmcs_writel(GUEST_IDTR_BASE, dt->address);
2196 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2198 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2199 dt->address = vmcs_readl(GUEST_GDTR_BASE);
2202 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2204 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2205 vmcs_writel(GUEST_GDTR_BASE, dt->address);
2208 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2210 struct kvm_segment var;
2213 vmx_get_segment(vcpu, &var, seg);
2214 ar = vmx_segment_access_rights(&var);
2216 if (var.base != (var.selector << 4))
2218 if (var.limit != 0xffff)
2226 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2228 struct kvm_segment cs;
2229 unsigned int cs_rpl;
2231 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2232 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2236 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2240 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2241 if (cs.dpl > cs_rpl)
2244 if (cs.dpl != cs_rpl)
2250 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2254 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2256 struct kvm_segment ss;
2257 unsigned int ss_rpl;
2259 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2260 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2264 if (ss.type != 3 && ss.type != 7)
2268 if (ss.dpl != ss_rpl) /* DPL != RPL */
2276 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2278 struct kvm_segment var;
2281 vmx_get_segment(vcpu, &var, seg);
2282 rpl = var.selector & SELECTOR_RPL_MASK;
2290 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2291 if (var.dpl < rpl) /* DPL < RPL */
2295 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2301 static bool tr_valid(struct kvm_vcpu *vcpu)
2303 struct kvm_segment tr;
2305 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2309 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2311 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2319 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2321 struct kvm_segment ldtr;
2323 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2327 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2337 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2339 struct kvm_segment cs, ss;
2341 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2342 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2344 return ((cs.selector & SELECTOR_RPL_MASK) ==
2345 (ss.selector & SELECTOR_RPL_MASK));
2349 * Check if guest state is valid. Returns true if valid, false if
2351 * We assume that registers are always usable
2353 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2355 /* real mode guest state checks */
2356 if (!is_protmode(vcpu)) {
2357 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2359 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2361 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2363 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2365 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2367 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2370 /* protected mode guest state checks */
2371 if (!cs_ss_rpl_check(vcpu))
2373 if (!code_segment_valid(vcpu))
2375 if (!stack_segment_valid(vcpu))
2377 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2379 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2381 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2383 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2385 if (!tr_valid(vcpu))
2387 if (!ldtr_valid(vcpu))
2391 * - Add checks on RIP
2392 * - Add checks on RFLAGS
2398 static int init_rmode_tss(struct kvm *kvm)
2400 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2405 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2408 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2409 r = kvm_write_guest_page(kvm, fn++, &data,
2410 TSS_IOPB_BASE_OFFSET, sizeof(u16));
2413 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2416 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2420 r = kvm_write_guest_page(kvm, fn, &data,
2421 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2431 static int init_rmode_identity_map(struct kvm *kvm)
2434 pfn_t identity_map_pfn;
2439 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2440 printk(KERN_ERR "EPT: identity-mapping pagetable "
2441 "haven't been allocated!\n");
2444 if (likely(kvm->arch.ept_identity_pagetable_done))
2447 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2448 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2451 /* Set up identity-mapping pagetable for EPT in real mode */
2452 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2453 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2454 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2455 r = kvm_write_guest_page(kvm, identity_map_pfn,
2456 &tmp, i * sizeof(tmp), sizeof(tmp));
2460 kvm->arch.ept_identity_pagetable_done = true;
2466 static void seg_setup(int seg)
2468 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2471 vmcs_write16(sf->selector, 0);
2472 vmcs_writel(sf->base, 0);
2473 vmcs_write32(sf->limit, 0xffff);
2474 if (enable_unrestricted_guest) {
2476 if (seg == VCPU_SREG_CS)
2477 ar |= 0x08; /* code segment */
2481 vmcs_write32(sf->ar_bytes, ar);
2484 static int alloc_apic_access_page(struct kvm *kvm)
2486 struct kvm_userspace_memory_region kvm_userspace_mem;
2489 mutex_lock(&kvm->slots_lock);
2490 if (kvm->arch.apic_access_page)
2492 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2493 kvm_userspace_mem.flags = 0;
2494 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2495 kvm_userspace_mem.memory_size = PAGE_SIZE;
2496 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2500 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2502 mutex_unlock(&kvm->slots_lock);
2506 static int alloc_identity_pagetable(struct kvm *kvm)
2508 struct kvm_userspace_memory_region kvm_userspace_mem;
2511 mutex_lock(&kvm->slots_lock);
2512 if (kvm->arch.ept_identity_pagetable)
2514 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2515 kvm_userspace_mem.flags = 0;
2516 kvm_userspace_mem.guest_phys_addr =
2517 kvm->arch.ept_identity_map_addr;
2518 kvm_userspace_mem.memory_size = PAGE_SIZE;
2519 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2523 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2524 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2526 mutex_unlock(&kvm->slots_lock);
2530 static void allocate_vpid(struct vcpu_vmx *vmx)
2537 spin_lock(&vmx_vpid_lock);
2538 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2539 if (vpid < VMX_NR_VPIDS) {
2541 __set_bit(vpid, vmx_vpid_bitmap);
2543 spin_unlock(&vmx_vpid_lock);
2546 static void free_vpid(struct vcpu_vmx *vmx)
2550 spin_lock(&vmx_vpid_lock);
2552 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2553 spin_unlock(&vmx_vpid_lock);
2556 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2558 int f = sizeof(unsigned long);
2560 if (!cpu_has_vmx_msr_bitmap())
2564 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2565 * have the write-low and read-high bitmap offsets the wrong way round.
2566 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2568 if (msr <= 0x1fff) {
2569 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2570 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2571 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2573 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2574 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2578 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2581 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2582 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2586 * Sets up the vmcs for emulated real mode.
2588 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2590 u32 host_sysenter_cs, msr_low, msr_high;
2596 unsigned long kvm_vmx_return;
2600 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2601 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2603 if (cpu_has_vmx_msr_bitmap())
2604 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2606 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2609 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2610 vmcs_config.pin_based_exec_ctrl);
2612 exec_control = vmcs_config.cpu_based_exec_ctrl;
2613 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2614 exec_control &= ~CPU_BASED_TPR_SHADOW;
2615 #ifdef CONFIG_X86_64
2616 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2617 CPU_BASED_CR8_LOAD_EXITING;
2621 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2622 CPU_BASED_CR3_LOAD_EXITING |
2623 CPU_BASED_INVLPG_EXITING;
2624 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2626 if (cpu_has_secondary_exec_ctrls()) {
2627 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2628 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2630 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2632 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2634 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2635 enable_unrestricted_guest = 0;
2637 if (!enable_unrestricted_guest)
2638 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2640 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2641 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2645 vmcs_write32(PLE_GAP, ple_gap);
2646 vmcs_write32(PLE_WINDOW, ple_window);
2649 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2650 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2651 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2653 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
2654 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2655 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2657 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2658 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2659 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2660 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
2661 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
2662 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2663 #ifdef CONFIG_X86_64
2664 rdmsrl(MSR_FS_BASE, a);
2665 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2666 rdmsrl(MSR_GS_BASE, a);
2667 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2669 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2670 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2673 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2675 native_store_idt(&dt);
2676 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
2678 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2679 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2680 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2681 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2682 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2683 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2684 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2686 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2687 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2688 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2689 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2690 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2691 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2693 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2694 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2695 host_pat = msr_low | ((u64) msr_high << 32);
2696 vmcs_write64(HOST_IA32_PAT, host_pat);
2698 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2699 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2700 host_pat = msr_low | ((u64) msr_high << 32);
2701 /* Write the default value follow host pat */
2702 vmcs_write64(GUEST_IA32_PAT, host_pat);
2703 /* Keep arch.pat sync with GUEST_IA32_PAT */
2704 vmx->vcpu.arch.pat = host_pat;
2707 for (i = 0; i < NR_VMX_MSR; ++i) {
2708 u32 index = vmx_msr_index[i];
2709 u32 data_low, data_high;
2712 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2714 if (wrmsr_safe(index, data_low, data_high) < 0)
2716 vmx->guest_msrs[j].index = i;
2717 vmx->guest_msrs[j].data = 0;
2718 vmx->guest_msrs[j].mask = -1ull;
2722 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2724 /* 22.2.1, 20.8.1 */
2725 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2727 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2728 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2730 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2731 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2733 kvm_write_tsc(&vmx->vcpu, 0);
2738 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2740 struct vcpu_vmx *vmx = to_vmx(vcpu);
2744 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2746 vmx->rmode.vm86_active = 0;
2748 vmx->soft_vnmi_blocked = 0;
2750 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2751 kvm_set_cr8(&vmx->vcpu, 0);
2752 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2753 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2754 msr |= MSR_IA32_APICBASE_BSP;
2755 kvm_set_apic_base(&vmx->vcpu, msr);
2757 ret = fx_init(&vmx->vcpu);
2761 seg_setup(VCPU_SREG_CS);
2763 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2764 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2766 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2767 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2768 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2770 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2771 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2774 seg_setup(VCPU_SREG_DS);
2775 seg_setup(VCPU_SREG_ES);
2776 seg_setup(VCPU_SREG_FS);
2777 seg_setup(VCPU_SREG_GS);
2778 seg_setup(VCPU_SREG_SS);
2780 vmcs_write16(GUEST_TR_SELECTOR, 0);
2781 vmcs_writel(GUEST_TR_BASE, 0);
2782 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2783 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2785 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2786 vmcs_writel(GUEST_LDTR_BASE, 0);
2787 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2788 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2790 vmcs_write32(GUEST_SYSENTER_CS, 0);
2791 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2792 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2794 vmcs_writel(GUEST_RFLAGS, 0x02);
2795 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2796 kvm_rip_write(vcpu, 0xfff0);
2798 kvm_rip_write(vcpu, 0);
2799 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2801 vmcs_writel(GUEST_DR7, 0x400);
2803 vmcs_writel(GUEST_GDTR_BASE, 0);
2804 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2806 vmcs_writel(GUEST_IDTR_BASE, 0);
2807 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2809 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
2810 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2811 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2813 /* Special registers */
2814 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2818 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2820 if (cpu_has_vmx_tpr_shadow()) {
2821 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2822 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2823 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2824 __pa(vmx->vcpu.arch.apic->regs));
2825 vmcs_write32(TPR_THRESHOLD, 0);
2828 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2829 vmcs_write64(APIC_ACCESS_ADDR,
2830 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2833 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2835 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2836 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2837 vmx_set_cr4(&vmx->vcpu, 0);
2838 vmx_set_efer(&vmx->vcpu, 0);
2839 vmx_fpu_activate(&vmx->vcpu);
2840 update_exception_bitmap(&vmx->vcpu);
2842 vpid_sync_context(vmx);
2846 /* HACK: Don't enable emulation on guest boot/reset */
2847 vmx->emulation_required = 0;
2853 static void enable_irq_window(struct kvm_vcpu *vcpu)
2855 u32 cpu_based_vm_exec_control;
2857 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2858 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2859 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2862 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2864 u32 cpu_based_vm_exec_control;
2866 if (!cpu_has_virtual_nmis()) {
2867 enable_irq_window(vcpu);
2871 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
2872 enable_irq_window(vcpu);
2875 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2876 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2877 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2880 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2882 struct vcpu_vmx *vmx = to_vmx(vcpu);
2884 int irq = vcpu->arch.interrupt.nr;
2886 trace_kvm_inj_virq(irq);
2888 ++vcpu->stat.irq_injections;
2889 if (vmx->rmode.vm86_active) {
2890 if (kvm_inject_realmode_interrupt(vcpu, irq) != EMULATE_DONE)
2891 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2894 intr = irq | INTR_INFO_VALID_MASK;
2895 if (vcpu->arch.interrupt.soft) {
2896 intr |= INTR_TYPE_SOFT_INTR;
2897 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2898 vmx->vcpu.arch.event_exit_inst_len);
2900 intr |= INTR_TYPE_EXT_INTR;
2901 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2902 vmx_clear_hlt(vcpu);
2905 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2907 struct vcpu_vmx *vmx = to_vmx(vcpu);
2909 if (!cpu_has_virtual_nmis()) {
2911 * Tracking the NMI-blocked state in software is built upon
2912 * finding the next open IRQ window. This, in turn, depends on
2913 * well-behaving guests: They have to keep IRQs disabled at
2914 * least as long as the NMI handler runs. Otherwise we may
2915 * cause NMI nesting, maybe breaking the guest. But as this is
2916 * highly unlikely, we can live with the residual risk.
2918 vmx->soft_vnmi_blocked = 1;
2919 vmx->vnmi_blocked_time = 0;
2922 ++vcpu->stat.nmi_injections;
2923 if (vmx->rmode.vm86_active) {
2924 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR) != EMULATE_DONE)
2925 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2928 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2929 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2930 vmx_clear_hlt(vcpu);
2933 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2935 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2938 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2939 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
2940 | GUEST_INTR_STATE_NMI));
2943 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2945 if (!cpu_has_virtual_nmis())
2946 return to_vmx(vcpu)->soft_vnmi_blocked;
2947 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
2950 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2952 struct vcpu_vmx *vmx = to_vmx(vcpu);
2954 if (!cpu_has_virtual_nmis()) {
2955 if (vmx->soft_vnmi_blocked != masked) {
2956 vmx->soft_vnmi_blocked = masked;
2957 vmx->vnmi_blocked_time = 0;
2961 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2962 GUEST_INTR_STATE_NMI);
2964 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2965 GUEST_INTR_STATE_NMI);
2969 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2971 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2972 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2973 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2976 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2979 struct kvm_userspace_memory_region tss_mem = {
2980 .slot = TSS_PRIVATE_MEMSLOT,
2981 .guest_phys_addr = addr,
2982 .memory_size = PAGE_SIZE * 3,
2986 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2989 kvm->arch.tss_addr = addr;
2990 if (!init_rmode_tss(kvm))
2996 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2997 int vec, u32 err_code)
3000 * Instruction with address size override prefix opcode 0x67
3001 * Cause the #SS fault with 0 error code in VM86 mode.
3003 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3004 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
3007 * Forward all other exceptions that are valid in real mode.
3008 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3009 * the required debugging infrastructure rework.
3013 if (vcpu->guest_debug &
3014 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
3016 kvm_queue_exception(vcpu, vec);
3020 * Update instruction length as we may reinject the exception
3021 * from user space while in guest debugging mode.
3023 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3024 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3025 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3036 kvm_queue_exception(vcpu, vec);
3043 * Trigger machine check on the host. We assume all the MSRs are already set up
3044 * by the CPU and that we still run on the same CPU as the MCE occurred on.
3045 * We pass a fake environment to the machine check handler because we want
3046 * the guest to be always treated like user space, no matter what context
3047 * it used internally.
3049 static void kvm_machine_check(void)
3051 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3052 struct pt_regs regs = {
3053 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3054 .flags = X86_EFLAGS_IF,
3057 do_machine_check(®s, 0);
3061 static int handle_machine_check(struct kvm_vcpu *vcpu)
3063 /* already handled by vcpu_run */
3067 static int handle_exception(struct kvm_vcpu *vcpu)
3069 struct vcpu_vmx *vmx = to_vmx(vcpu);
3070 struct kvm_run *kvm_run = vcpu->run;
3071 u32 intr_info, ex_no, error_code;
3072 unsigned long cr2, rip, dr6;
3074 enum emulation_result er;
3076 vect_info = vmx->idt_vectoring_info;
3077 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3079 if (is_machine_check(intr_info))
3080 return handle_machine_check(vcpu);
3082 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3083 !is_page_fault(intr_info)) {
3084 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3085 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3086 vcpu->run->internal.ndata = 2;
3087 vcpu->run->internal.data[0] = vect_info;
3088 vcpu->run->internal.data[1] = intr_info;
3092 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3093 return 1; /* already handled by vmx_vcpu_run() */
3095 if (is_no_device(intr_info)) {
3096 vmx_fpu_activate(vcpu);
3100 if (is_invalid_opcode(intr_info)) {
3101 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
3102 if (er != EMULATE_DONE)
3103 kvm_queue_exception(vcpu, UD_VECTOR);
3108 rip = kvm_rip_read(vcpu);
3109 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3110 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3111 if (is_page_fault(intr_info)) {
3112 /* EPT won't cause page fault directly */
3115 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3116 trace_kvm_page_fault(cr2, error_code);
3118 if (kvm_event_needs_reinjection(vcpu))
3119 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3120 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
3123 if (vmx->rmode.vm86_active &&
3124 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3126 if (vcpu->arch.halt_request) {
3127 vcpu->arch.halt_request = 0;
3128 return kvm_emulate_halt(vcpu);
3133 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3136 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3137 if (!(vcpu->guest_debug &
3138 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3139 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3140 kvm_queue_exception(vcpu, DB_VECTOR);
3143 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3144 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3148 * Update instruction length as we may reinject #BP from
3149 * user space while in guest debugging mode. Reading it for
3150 * #DB as well causes no harm, it is not used in that case.
3152 vmx->vcpu.arch.event_exit_inst_len =
3153 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3154 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3155 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3156 kvm_run->debug.arch.exception = ex_no;
3159 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3160 kvm_run->ex.exception = ex_no;
3161 kvm_run->ex.error_code = error_code;
3167 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3169 ++vcpu->stat.irq_exits;
3173 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3175 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3179 static int handle_io(struct kvm_vcpu *vcpu)
3181 unsigned long exit_qualification;
3182 int size, in, string;
3185 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3186 string = (exit_qualification & 16) != 0;
3187 in = (exit_qualification & 8) != 0;
3189 ++vcpu->stat.io_exits;
3192 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3194 port = exit_qualification >> 16;
3195 size = (exit_qualification & 7) + 1;
3196 skip_emulated_instruction(vcpu);
3198 return kvm_fast_pio_out(vcpu, size, port);
3202 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3205 * Patch in the VMCALL instruction:
3207 hypercall[0] = 0x0f;
3208 hypercall[1] = 0x01;
3209 hypercall[2] = 0xc1;
3212 static int handle_cr(struct kvm_vcpu *vcpu)
3214 unsigned long exit_qualification, val;
3219 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3220 cr = exit_qualification & 15;
3221 reg = (exit_qualification >> 8) & 15;
3222 switch ((exit_qualification >> 4) & 3) {
3223 case 0: /* mov to cr */
3224 val = kvm_register_read(vcpu, reg);
3225 trace_kvm_cr_write(cr, val);
3228 err = kvm_set_cr0(vcpu, val);
3229 kvm_complete_insn_gp(vcpu, err);
3232 err = kvm_set_cr3(vcpu, val);
3233 kvm_complete_insn_gp(vcpu, err);
3236 err = kvm_set_cr4(vcpu, val);
3237 kvm_complete_insn_gp(vcpu, err);
3240 u8 cr8_prev = kvm_get_cr8(vcpu);
3241 u8 cr8 = kvm_register_read(vcpu, reg);
3242 err = kvm_set_cr8(vcpu, cr8);
3243 kvm_complete_insn_gp(vcpu, err);
3244 if (irqchip_in_kernel(vcpu->kvm))
3246 if (cr8_prev <= cr8)
3248 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3254 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3255 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3256 skip_emulated_instruction(vcpu);
3257 vmx_fpu_activate(vcpu);
3259 case 1: /*mov from cr*/
3262 val = kvm_read_cr3(vcpu);
3263 kvm_register_write(vcpu, reg, val);
3264 trace_kvm_cr_read(cr, val);
3265 skip_emulated_instruction(vcpu);
3268 val = kvm_get_cr8(vcpu);
3269 kvm_register_write(vcpu, reg, val);
3270 trace_kvm_cr_read(cr, val);
3271 skip_emulated_instruction(vcpu);
3276 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3277 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3278 kvm_lmsw(vcpu, val);
3280 skip_emulated_instruction(vcpu);
3285 vcpu->run->exit_reason = 0;
3286 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3287 (int)(exit_qualification >> 4) & 3, cr);
3291 static int handle_dr(struct kvm_vcpu *vcpu)
3293 unsigned long exit_qualification;
3296 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3297 if (!kvm_require_cpl(vcpu, 0))
3299 dr = vmcs_readl(GUEST_DR7);
3302 * As the vm-exit takes precedence over the debug trap, we
3303 * need to emulate the latter, either for the host or the
3304 * guest debugging itself.
3306 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3307 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3308 vcpu->run->debug.arch.dr7 = dr;
3309 vcpu->run->debug.arch.pc =
3310 vmcs_readl(GUEST_CS_BASE) +
3311 vmcs_readl(GUEST_RIP);
3312 vcpu->run->debug.arch.exception = DB_VECTOR;
3313 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3316 vcpu->arch.dr7 &= ~DR7_GD;
3317 vcpu->arch.dr6 |= DR6_BD;
3318 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3319 kvm_queue_exception(vcpu, DB_VECTOR);
3324 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3325 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3326 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3327 if (exit_qualification & TYPE_MOV_FROM_DR) {
3329 if (!kvm_get_dr(vcpu, dr, &val))
3330 kvm_register_write(vcpu, reg, val);
3332 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3333 skip_emulated_instruction(vcpu);
3337 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3339 vmcs_writel(GUEST_DR7, val);
3342 static int handle_cpuid(struct kvm_vcpu *vcpu)
3344 kvm_emulate_cpuid(vcpu);
3348 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3350 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3353 if (vmx_get_msr(vcpu, ecx, &data)) {
3354 trace_kvm_msr_read_ex(ecx);
3355 kvm_inject_gp(vcpu, 0);
3359 trace_kvm_msr_read(ecx, data);
3361 /* FIXME: handling of bits 32:63 of rax, rdx */
3362 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3363 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3364 skip_emulated_instruction(vcpu);
3368 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3370 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3371 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3372 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3374 if (vmx_set_msr(vcpu, ecx, data) != 0) {
3375 trace_kvm_msr_write_ex(ecx, data);
3376 kvm_inject_gp(vcpu, 0);
3380 trace_kvm_msr_write(ecx, data);
3381 skip_emulated_instruction(vcpu);
3385 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3387 kvm_make_request(KVM_REQ_EVENT, vcpu);
3391 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3393 u32 cpu_based_vm_exec_control;
3395 /* clear pending irq */
3396 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3397 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3398 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3400 kvm_make_request(KVM_REQ_EVENT, vcpu);
3402 ++vcpu->stat.irq_window_exits;
3405 * If the user space waits to inject interrupts, exit as soon as
3408 if (!irqchip_in_kernel(vcpu->kvm) &&
3409 vcpu->run->request_interrupt_window &&
3410 !kvm_cpu_has_interrupt(vcpu)) {
3411 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3417 static int handle_halt(struct kvm_vcpu *vcpu)
3419 skip_emulated_instruction(vcpu);
3420 return kvm_emulate_halt(vcpu);
3423 static int handle_vmcall(struct kvm_vcpu *vcpu)
3425 skip_emulated_instruction(vcpu);
3426 kvm_emulate_hypercall(vcpu);
3430 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3432 kvm_queue_exception(vcpu, UD_VECTOR);
3436 static int handle_invd(struct kvm_vcpu *vcpu)
3438 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3441 static int handle_invlpg(struct kvm_vcpu *vcpu)
3443 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3445 kvm_mmu_invlpg(vcpu, exit_qualification);
3446 skip_emulated_instruction(vcpu);
3450 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3452 skip_emulated_instruction(vcpu);
3453 kvm_emulate_wbinvd(vcpu);
3457 static int handle_xsetbv(struct kvm_vcpu *vcpu)
3459 u64 new_bv = kvm_read_edx_eax(vcpu);
3460 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3462 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3463 skip_emulated_instruction(vcpu);
3467 static int handle_apic_access(struct kvm_vcpu *vcpu)
3469 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3472 static int handle_task_switch(struct kvm_vcpu *vcpu)
3474 struct vcpu_vmx *vmx = to_vmx(vcpu);
3475 unsigned long exit_qualification;
3476 bool has_error_code = false;
3479 int reason, type, idt_v;
3481 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3482 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3484 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3486 reason = (u32)exit_qualification >> 30;
3487 if (reason == TASK_SWITCH_GATE && idt_v) {
3489 case INTR_TYPE_NMI_INTR:
3490 vcpu->arch.nmi_injected = false;
3491 if (cpu_has_virtual_nmis())
3492 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3493 GUEST_INTR_STATE_NMI);
3495 case INTR_TYPE_EXT_INTR:
3496 case INTR_TYPE_SOFT_INTR:
3497 kvm_clear_interrupt_queue(vcpu);
3499 case INTR_TYPE_HARD_EXCEPTION:
3500 if (vmx->idt_vectoring_info &
3501 VECTORING_INFO_DELIVER_CODE_MASK) {
3502 has_error_code = true;
3504 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3507 case INTR_TYPE_SOFT_EXCEPTION:
3508 kvm_clear_exception_queue(vcpu);
3514 tss_selector = exit_qualification;
3516 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3517 type != INTR_TYPE_EXT_INTR &&
3518 type != INTR_TYPE_NMI_INTR))
3519 skip_emulated_instruction(vcpu);
3521 if (kvm_task_switch(vcpu, tss_selector, reason,
3522 has_error_code, error_code) == EMULATE_FAIL) {
3523 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3524 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3525 vcpu->run->internal.ndata = 0;
3529 /* clear all local breakpoint enable flags */
3530 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3533 * TODO: What about debug traps on tss switch?
3534 * Are we supposed to inject them and update dr6?
3540 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3542 unsigned long exit_qualification;
3546 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3548 if (exit_qualification & (1 << 6)) {
3549 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3553 gla_validity = (exit_qualification >> 7) & 0x3;
3554 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3555 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3556 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3557 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3558 vmcs_readl(GUEST_LINEAR_ADDRESS));
3559 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3560 (long unsigned int)exit_qualification);
3561 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3562 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3566 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3567 trace_kvm_page_fault(gpa, exit_qualification);
3568 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
3571 static u64 ept_rsvd_mask(u64 spte, int level)
3576 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3577 mask |= (1ULL << i);
3580 /* bits 7:3 reserved */
3582 else if (level == 2) {
3583 if (spte & (1ULL << 7))
3584 /* 2MB ref, bits 20:12 reserved */
3587 /* bits 6:3 reserved */
3594 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3597 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3599 /* 010b (write-only) */
3600 WARN_ON((spte & 0x7) == 0x2);
3602 /* 110b (write/execute) */
3603 WARN_ON((spte & 0x7) == 0x6);
3605 /* 100b (execute-only) and value not supported by logical processor */
3606 if (!cpu_has_vmx_ept_execute_only())
3607 WARN_ON((spte & 0x7) == 0x4);
3611 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3613 if (rsvd_bits != 0) {
3614 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3615 __func__, rsvd_bits);
3619 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3620 u64 ept_mem_type = (spte & 0x38) >> 3;
3622 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3623 ept_mem_type == 7) {
3624 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3625 __func__, ept_mem_type);
3632 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3638 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3640 printk(KERN_ERR "EPT: Misconfiguration.\n");
3641 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3643 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3645 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3646 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3648 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3649 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3654 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3656 u32 cpu_based_vm_exec_control;
3658 /* clear pending NMI */
3659 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3660 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3661 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3662 ++vcpu->stat.nmi_window_exits;
3663 kvm_make_request(KVM_REQ_EVENT, vcpu);
3668 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3670 struct vcpu_vmx *vmx = to_vmx(vcpu);
3671 enum emulation_result err = EMULATE_DONE;
3674 bool intr_window_requested;
3676 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3677 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
3679 while (!guest_state_valid(vcpu)) {
3680 if (intr_window_requested
3681 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
3682 return handle_interrupt_window(&vmx->vcpu);
3684 err = emulate_instruction(vcpu, 0);
3686 if (err == EMULATE_DO_MMIO) {
3691 if (err != EMULATE_DONE)
3694 if (signal_pending(current))
3700 vmx->emulation_required = 0;
3706 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3707 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3709 static int handle_pause(struct kvm_vcpu *vcpu)
3711 skip_emulated_instruction(vcpu);
3712 kvm_vcpu_on_spin(vcpu);
3717 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3719 kvm_queue_exception(vcpu, UD_VECTOR);
3724 * The exit handlers return 1 if the exit was handled fully and guest execution
3725 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3726 * to be done to userspace and return 0.
3728 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3729 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3730 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3731 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3732 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3733 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3734 [EXIT_REASON_CR_ACCESS] = handle_cr,
3735 [EXIT_REASON_DR_ACCESS] = handle_dr,
3736 [EXIT_REASON_CPUID] = handle_cpuid,
3737 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3738 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3739 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3740 [EXIT_REASON_HLT] = handle_halt,
3741 [EXIT_REASON_INVD] = handle_invd,
3742 [EXIT_REASON_INVLPG] = handle_invlpg,
3743 [EXIT_REASON_VMCALL] = handle_vmcall,
3744 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3745 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3746 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3747 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3748 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3749 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3750 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3751 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3752 [EXIT_REASON_VMON] = handle_vmx_insn,
3753 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3754 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3755 [EXIT_REASON_WBINVD] = handle_wbinvd,
3756 [EXIT_REASON_XSETBV] = handle_xsetbv,
3757 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3758 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3759 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3760 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
3761 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
3762 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3763 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
3766 static const int kvm_vmx_max_exit_handlers =
3767 ARRAY_SIZE(kvm_vmx_exit_handlers);
3769 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3771 *info1 = vmcs_readl(EXIT_QUALIFICATION);
3772 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
3776 * The guest has exited. See if we can fix it or if we need userspace
3779 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3781 struct vcpu_vmx *vmx = to_vmx(vcpu);
3782 u32 exit_reason = vmx->exit_reason;
3783 u32 vectoring_info = vmx->idt_vectoring_info;
3785 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
3787 /* If guest state is invalid, start emulating */
3788 if (vmx->emulation_required && emulate_invalid_guest_state)
3789 return handle_invalid_guest_state(vcpu);
3791 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3792 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3793 vcpu->run->fail_entry.hardware_entry_failure_reason
3798 if (unlikely(vmx->fail)) {
3799 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3800 vcpu->run->fail_entry.hardware_entry_failure_reason
3801 = vmcs_read32(VM_INSTRUCTION_ERROR);
3805 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3806 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3807 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3808 exit_reason != EXIT_REASON_TASK_SWITCH))
3809 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3810 "(0x%x) and exit reason is 0x%x\n",
3811 __func__, vectoring_info, exit_reason);
3813 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3814 if (vmx_interrupt_allowed(vcpu)) {
3815 vmx->soft_vnmi_blocked = 0;
3816 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3817 vcpu->arch.nmi_pending) {
3819 * This CPU don't support us in finding the end of an
3820 * NMI-blocked window if the guest runs with IRQs
3821 * disabled. So we pull the trigger after 1 s of
3822 * futile waiting, but inform the user about this.
3824 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3825 "state on VCPU %d after 1 s timeout\n",
3826 __func__, vcpu->vcpu_id);
3827 vmx->soft_vnmi_blocked = 0;
3831 if (exit_reason < kvm_vmx_max_exit_handlers
3832 && kvm_vmx_exit_handlers[exit_reason])
3833 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3835 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3836 vcpu->run->hw.hardware_exit_reason = exit_reason;
3841 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3843 if (irr == -1 || tpr < irr) {
3844 vmcs_write32(TPR_THRESHOLD, 0);
3848 vmcs_write32(TPR_THRESHOLD, irr);
3851 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
3853 u32 exit_intr_info = vmx->exit_intr_info;
3855 /* Handle machine checks before interrupts are enabled */
3856 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3857 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3858 && is_machine_check(exit_intr_info)))
3859 kvm_machine_check();
3861 /* We need to handle NMIs before interrupts are enabled */
3862 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3863 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3864 kvm_before_handle_nmi(&vmx->vcpu);
3866 kvm_after_handle_nmi(&vmx->vcpu);
3870 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
3872 u32 exit_intr_info = vmx->exit_intr_info;
3875 bool idtv_info_valid;
3877 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3879 if (cpu_has_virtual_nmis()) {
3880 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3881 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3883 * SDM 3: 27.7.1.2 (September 2008)
3884 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3885 * a guest IRET fault.
3886 * SDM 3: 23.2.2 (September 2008)
3887 * Bit 12 is undefined in any of the following cases:
3888 * If the VM exit sets the valid bit in the IDT-vectoring
3889 * information field.
3890 * If the VM exit is due to a double fault.
3892 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3893 vector != DF_VECTOR && !idtv_info_valid)
3894 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3895 GUEST_INTR_STATE_NMI);
3896 } else if (unlikely(vmx->soft_vnmi_blocked))
3897 vmx->vnmi_blocked_time +=
3898 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3901 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
3902 u32 idt_vectoring_info,
3903 int instr_len_field,
3904 int error_code_field)
3908 bool idtv_info_valid;
3910 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3912 vmx->vcpu.arch.nmi_injected = false;
3913 kvm_clear_exception_queue(&vmx->vcpu);
3914 kvm_clear_interrupt_queue(&vmx->vcpu);
3916 if (!idtv_info_valid)
3919 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
3921 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3922 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3925 case INTR_TYPE_NMI_INTR:
3926 vmx->vcpu.arch.nmi_injected = true;
3928 * SDM 3: 27.7.1.2 (September 2008)
3929 * Clear bit "block by NMI" before VM entry if a NMI
3932 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3933 GUEST_INTR_STATE_NMI);
3935 case INTR_TYPE_SOFT_EXCEPTION:
3936 vmx->vcpu.arch.event_exit_inst_len =
3937 vmcs_read32(instr_len_field);
3939 case INTR_TYPE_HARD_EXCEPTION:
3940 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3941 u32 err = vmcs_read32(error_code_field);
3942 kvm_queue_exception_e(&vmx->vcpu, vector, err);
3944 kvm_queue_exception(&vmx->vcpu, vector);
3946 case INTR_TYPE_SOFT_INTR:
3947 vmx->vcpu.arch.event_exit_inst_len =
3948 vmcs_read32(instr_len_field);
3950 case INTR_TYPE_EXT_INTR:
3951 kvm_queue_interrupt(&vmx->vcpu, vector,
3952 type == INTR_TYPE_SOFT_INTR);
3959 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3961 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
3962 VM_EXIT_INSTRUCTION_LEN,
3963 IDT_VECTORING_ERROR_CODE);
3966 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
3968 __vmx_complete_interrupts(to_vmx(vcpu),
3969 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
3970 VM_ENTRY_INSTRUCTION_LEN,
3971 VM_ENTRY_EXCEPTION_ERROR_CODE);
3973 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
3976 #ifdef CONFIG_X86_64
3984 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
3986 struct vcpu_vmx *vmx = to_vmx(vcpu);
3988 /* Record the guest's net vcpu time for enforced NMI injections. */
3989 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3990 vmx->entry_time = ktime_get();
3992 /* Don't enter VMX if guest state is invalid, let the exit handler
3993 start emulation until we arrive back to a valid state */
3994 if (vmx->emulation_required && emulate_invalid_guest_state)
3997 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3998 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3999 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
4000 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
4002 /* When single-stepping over STI and MOV SS, we must clear the
4003 * corresponding interruptibility bits in the guest state. Otherwise
4004 * vmentry fails as it then expects bit 14 (BS) in pending debug
4005 * exceptions being set, but that's not correct for the guest debugging
4007 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
4008 vmx_set_interrupt_shadow(vcpu, 0);
4011 /* Store host registers */
4012 "push %%"R"dx; push %%"R"bp;"
4013 "push %%"R"cx \n\t" /* placeholder for guest rcx */
4015 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
4017 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4018 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
4020 /* Reload cr2 if changed */
4021 "mov %c[cr2](%0), %%"R"ax \n\t"
4022 "mov %%cr2, %%"R"dx \n\t"
4023 "cmp %%"R"ax, %%"R"dx \n\t"
4025 "mov %%"R"ax, %%cr2 \n\t"
4027 /* Check if vmlaunch of vmresume is needed */
4028 "cmpl $0, %c[launched](%0) \n\t"
4029 /* Load guest registers. Don't clobber flags. */
4030 "mov %c[rax](%0), %%"R"ax \n\t"
4031 "mov %c[rbx](%0), %%"R"bx \n\t"
4032 "mov %c[rdx](%0), %%"R"dx \n\t"
4033 "mov %c[rsi](%0), %%"R"si \n\t"
4034 "mov %c[rdi](%0), %%"R"di \n\t"
4035 "mov %c[rbp](%0), %%"R"bp \n\t"
4036 #ifdef CONFIG_X86_64
4037 "mov %c[r8](%0), %%r8 \n\t"
4038 "mov %c[r9](%0), %%r9 \n\t"
4039 "mov %c[r10](%0), %%r10 \n\t"
4040 "mov %c[r11](%0), %%r11 \n\t"
4041 "mov %c[r12](%0), %%r12 \n\t"
4042 "mov %c[r13](%0), %%r13 \n\t"
4043 "mov %c[r14](%0), %%r14 \n\t"
4044 "mov %c[r15](%0), %%r15 \n\t"
4046 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
4048 /* Enter guest mode */
4049 "jne .Llaunched \n\t"
4050 __ex(ASM_VMX_VMLAUNCH) "\n\t"
4051 "jmp .Lkvm_vmx_return \n\t"
4052 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
4053 ".Lkvm_vmx_return: "
4054 /* Save guest registers, load host registers, keep flags */
4055 "mov %0, %c[wordsize](%%"R"sp) \n\t"
4057 "mov %%"R"ax, %c[rax](%0) \n\t"
4058 "mov %%"R"bx, %c[rbx](%0) \n\t"
4059 "pop"Q" %c[rcx](%0) \n\t"
4060 "mov %%"R"dx, %c[rdx](%0) \n\t"
4061 "mov %%"R"si, %c[rsi](%0) \n\t"
4062 "mov %%"R"di, %c[rdi](%0) \n\t"
4063 "mov %%"R"bp, %c[rbp](%0) \n\t"
4064 #ifdef CONFIG_X86_64
4065 "mov %%r8, %c[r8](%0) \n\t"
4066 "mov %%r9, %c[r9](%0) \n\t"
4067 "mov %%r10, %c[r10](%0) \n\t"
4068 "mov %%r11, %c[r11](%0) \n\t"
4069 "mov %%r12, %c[r12](%0) \n\t"
4070 "mov %%r13, %c[r13](%0) \n\t"
4071 "mov %%r14, %c[r14](%0) \n\t"
4072 "mov %%r15, %c[r15](%0) \n\t"
4074 "mov %%cr2, %%"R"ax \n\t"
4075 "mov %%"R"ax, %c[cr2](%0) \n\t"
4077 "pop %%"R"bp; pop %%"R"dx \n\t"
4078 "setbe %c[fail](%0) \n\t"
4079 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4080 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4081 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
4082 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
4083 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4084 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4085 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4086 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4087 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4088 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4089 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
4090 #ifdef CONFIG_X86_64
4091 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4092 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4093 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4094 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4095 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4096 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4097 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4098 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
4100 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
4101 [wordsize]"i"(sizeof(ulong))
4103 , R"ax", R"bx", R"di", R"si"
4104 #ifdef CONFIG_X86_64
4105 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4109 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4110 | (1 << VCPU_EXREG_PDPTR)
4111 | (1 << VCPU_EXREG_CR3));
4112 vcpu->arch.regs_dirty = 0;
4114 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4116 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
4119 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
4120 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4122 vmx_complete_atomic_exit(vmx);
4123 vmx_recover_nmi_blocking(vmx);
4124 vmx_complete_interrupts(vmx);
4130 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4132 struct vcpu_vmx *vmx = to_vmx(vcpu);
4136 free_vmcs(vmx->vmcs);
4141 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4143 struct vcpu_vmx *vmx = to_vmx(vcpu);
4146 vmx_free_vmcs(vcpu);
4147 kfree(vmx->guest_msrs);
4148 kvm_vcpu_uninit(vcpu);
4149 kmem_cache_free(kvm_vcpu_cache, vmx);
4152 static inline void vmcs_init(struct vmcs *vmcs)
4154 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4157 kvm_cpu_vmxon(phys_addr);
4165 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4168 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4172 return ERR_PTR(-ENOMEM);
4176 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4180 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4181 if (!vmx->guest_msrs) {
4186 vmx->vmcs = alloc_vmcs();
4190 vmcs_init(vmx->vmcs);
4193 vmx_vcpu_load(&vmx->vcpu, cpu);
4194 vmx->vcpu.cpu = cpu;
4195 err = vmx_vcpu_setup(vmx);
4196 vmx_vcpu_put(&vmx->vcpu);
4200 if (vm_need_virtualize_apic_accesses(kvm))
4201 if (alloc_apic_access_page(kvm) != 0)
4205 if (!kvm->arch.ept_identity_map_addr)
4206 kvm->arch.ept_identity_map_addr =
4207 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4209 if (alloc_identity_pagetable(kvm) != 0)
4211 if (!init_rmode_identity_map(kvm))
4218 free_vmcs(vmx->vmcs);
4220 kfree(vmx->guest_msrs);
4222 kvm_vcpu_uninit(&vmx->vcpu);
4225 kmem_cache_free(kvm_vcpu_cache, vmx);
4226 return ERR_PTR(err);
4229 static void __init vmx_check_processor_compat(void *rtn)
4231 struct vmcs_config vmcs_conf;
4234 if (setup_vmcs_config(&vmcs_conf) < 0)
4236 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4237 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4238 smp_processor_id());
4243 static int get_ept_level(void)
4245 return VMX_EPT_DEFAULT_GAW + 1;
4248 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4252 /* For VT-d and EPT combination
4253 * 1. MMIO: always map as UC
4255 * a. VT-d without snooping control feature: can't guarantee the
4256 * result, try to trust guest.
4257 * b. VT-d with snooping control feature: snooping control feature of
4258 * VT-d engine can guarantee the cache correctness. Just set it
4259 * to WB to keep consistent with host. So the same as item 3.
4260 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4261 * consistent with host MTRR
4264 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4265 else if (vcpu->kvm->arch.iommu_domain &&
4266 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4267 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4268 VMX_EPT_MT_EPTE_SHIFT;
4270 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4276 #define _ER(x) { EXIT_REASON_##x, #x }
4278 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4280 _ER(EXTERNAL_INTERRUPT),
4282 _ER(PENDING_INTERRUPT),
4302 _ER(IO_INSTRUCTION),
4305 _ER(MWAIT_INSTRUCTION),
4306 _ER(MONITOR_INSTRUCTION),
4307 _ER(PAUSE_INSTRUCTION),
4308 _ER(MCE_DURING_VMENTRY),
4309 _ER(TPR_BELOW_THRESHOLD),
4319 static int vmx_get_lpage_level(void)
4321 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4322 return PT_DIRECTORY_LEVEL;
4324 /* For shadow and EPT supported 1GB page */
4325 return PT_PDPE_LEVEL;
4328 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4330 struct kvm_cpuid_entry2 *best;
4331 struct vcpu_vmx *vmx = to_vmx(vcpu);
4334 vmx->rdtscp_enabled = false;
4335 if (vmx_rdtscp_supported()) {
4336 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4337 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4338 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4339 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4340 vmx->rdtscp_enabled = true;
4342 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4343 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4350 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4354 static struct kvm_x86_ops vmx_x86_ops = {
4355 .cpu_has_kvm_support = cpu_has_kvm_support,
4356 .disabled_by_bios = vmx_disabled_by_bios,
4357 .hardware_setup = hardware_setup,
4358 .hardware_unsetup = hardware_unsetup,
4359 .check_processor_compatibility = vmx_check_processor_compat,
4360 .hardware_enable = hardware_enable,
4361 .hardware_disable = hardware_disable,
4362 .cpu_has_accelerated_tpr = report_flexpriority,
4364 .vcpu_create = vmx_create_vcpu,
4365 .vcpu_free = vmx_free_vcpu,
4366 .vcpu_reset = vmx_vcpu_reset,
4368 .prepare_guest_switch = vmx_save_host_state,
4369 .vcpu_load = vmx_vcpu_load,
4370 .vcpu_put = vmx_vcpu_put,
4372 .set_guest_debug = set_guest_debug,
4373 .get_msr = vmx_get_msr,
4374 .set_msr = vmx_set_msr,
4375 .get_segment_base = vmx_get_segment_base,
4376 .get_segment = vmx_get_segment,
4377 .set_segment = vmx_set_segment,
4378 .get_cpl = vmx_get_cpl,
4379 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4380 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4381 .decache_cr3 = vmx_decache_cr3,
4382 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4383 .set_cr0 = vmx_set_cr0,
4384 .set_cr3 = vmx_set_cr3,
4385 .set_cr4 = vmx_set_cr4,
4386 .set_efer = vmx_set_efer,
4387 .get_idt = vmx_get_idt,
4388 .set_idt = vmx_set_idt,
4389 .get_gdt = vmx_get_gdt,
4390 .set_gdt = vmx_set_gdt,
4391 .set_dr7 = vmx_set_dr7,
4392 .cache_reg = vmx_cache_reg,
4393 .get_rflags = vmx_get_rflags,
4394 .set_rflags = vmx_set_rflags,
4395 .fpu_activate = vmx_fpu_activate,
4396 .fpu_deactivate = vmx_fpu_deactivate,
4398 .tlb_flush = vmx_flush_tlb,
4400 .run = vmx_vcpu_run,
4401 .handle_exit = vmx_handle_exit,
4402 .skip_emulated_instruction = skip_emulated_instruction,
4403 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4404 .get_interrupt_shadow = vmx_get_interrupt_shadow,
4405 .patch_hypercall = vmx_patch_hypercall,
4406 .set_irq = vmx_inject_irq,
4407 .set_nmi = vmx_inject_nmi,
4408 .queue_exception = vmx_queue_exception,
4409 .cancel_injection = vmx_cancel_injection,
4410 .interrupt_allowed = vmx_interrupt_allowed,
4411 .nmi_allowed = vmx_nmi_allowed,
4412 .get_nmi_mask = vmx_get_nmi_mask,
4413 .set_nmi_mask = vmx_set_nmi_mask,
4414 .enable_nmi_window = enable_nmi_window,
4415 .enable_irq_window = enable_irq_window,
4416 .update_cr8_intercept = update_cr8_intercept,
4418 .set_tss_addr = vmx_set_tss_addr,
4419 .get_tdp_level = get_ept_level,
4420 .get_mt_mask = vmx_get_mt_mask,
4422 .get_exit_info = vmx_get_exit_info,
4423 .exit_reasons_str = vmx_exit_reasons_str,
4425 .get_lpage_level = vmx_get_lpage_level,
4427 .cpuid_update = vmx_cpuid_update,
4429 .rdtscp_supported = vmx_rdtscp_supported,
4431 .set_supported_cpuid = vmx_set_supported_cpuid,
4433 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
4435 .write_tsc_offset = vmx_write_tsc_offset,
4436 .adjust_tsc_offset = vmx_adjust_tsc_offset,
4438 .set_tdp_cr3 = vmx_set_cr3,
4441 static int __init vmx_init(void)
4445 rdmsrl_safe(MSR_EFER, &host_efer);
4447 for (i = 0; i < NR_VMX_MSR; ++i)
4448 kvm_define_shared_msr(i, vmx_msr_index[i]);
4450 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4451 if (!vmx_io_bitmap_a)
4454 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4455 if (!vmx_io_bitmap_b) {
4460 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4461 if (!vmx_msr_bitmap_legacy) {
4466 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4467 if (!vmx_msr_bitmap_longmode) {
4473 * Allow direct access to the PC debug port (it is often used for I/O
4474 * delays, but the vmexits simply slow things down).
4476 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4477 clear_bit(0x80, vmx_io_bitmap_a);
4479 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4481 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4482 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4484 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4486 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4487 __alignof__(struct vcpu_vmx), THIS_MODULE);
4491 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4492 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4493 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4494 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4495 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4496 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4499 bypass_guest_pf = 0;
4500 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4501 VMX_EPT_EXECUTABLE_MASK);
4506 if (bypass_guest_pf)
4507 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4512 free_page((unsigned long)vmx_msr_bitmap_longmode);
4514 free_page((unsigned long)vmx_msr_bitmap_legacy);
4516 free_page((unsigned long)vmx_io_bitmap_b);
4518 free_page((unsigned long)vmx_io_bitmap_a);
4522 static void __exit vmx_exit(void)
4524 free_page((unsigned long)vmx_msr_bitmap_legacy);
4525 free_page((unsigned long)vmx_msr_bitmap_longmode);
4526 free_page((unsigned long)vmx_io_bitmap_b);
4527 free_page((unsigned long)vmx_io_bitmap_a);
4532 module_init(vmx_init)
4533 module_exit(vmx_exit)