arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20 #include "kvm_cache_regs.h"
  21 #include "x86.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/ftrace_event.h>
  29
  30 #include <asm/desc.h>
  31
  32 #include <asm/virtext.h>
  33 #include "trace.h"
  34
  35 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  36
  37 MODULE_AUTHOR("Qumranet");
  38 MODULE_LICENSE("GPL");
  39
  40 #define IOPM_ALLOC_ORDER 2
  41 #define MSRPM_ALLOC_ORDER 1
  42
  43 #define SEG_TYPE_LDT 2
  44 #define SEG_TYPE_BUSY_TSS16 3
  45
  46 #define SVM_FEATURE_NPT  (1 << 0)
  47 #define SVM_FEATURE_LBRV (1 << 1)
  48 #define SVM_FEATURE_SVML (1 << 2)
  49 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
  50
  51 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  52 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  53 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  54
  55 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  56
  57 static const u32 host_save_user_msrs[] = {
  58 #ifdef CONFIG_X86_64
  59         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  60         MSR_FS_BASE,
  61 #endif
  62         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  63 };
  64
  65 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  66
  67 struct kvm_vcpu;
  68
  69 struct nested_state {
  70         struct vmcb *hsave;
  71         u64 hsave_msr;
  72         u64 vmcb;
  73
  74         /* These are the merged vectors */
  75         u32 *msrpm;
  76
  77         /* gpa pointers to the real vectors */
  78         u64 vmcb_msrpm;
  79
  80         /* A VMEXIT is required but not yet emulated */
  81         bool exit_required;
  82
  83         /* cache for intercepts of the guest */
  84         u16 intercept_cr_read;
  85         u16 intercept_cr_write;
  86         u16 intercept_dr_read;
  87         u16 intercept_dr_write;
  88         u32 intercept_exceptions;
  89         u64 intercept;
  90
  91 };
  92
  93 struct vcpu_svm {
  94         struct kvm_vcpu vcpu;
  95         struct vmcb *vmcb;
  96         unsigned long vmcb_pa;
  97         struct svm_cpu_data *svm_data;
  98         uint64_t asid_generation;
  99         uint64_t sysenter_esp;
 100         uint64_t sysenter_eip;
 101
 102         u64 next_rip;
 103
 104         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 105         u64 host_gs_base;
 106
 107         u32 *msrpm;
 108
 109         struct nested_state nested;
 110
 111         bool nmi_singlestep;
 112 };
 113
 114 /* enable NPT for AMD64 and X86 with PAE */
 115 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 116 static bool npt_enabled = true;
 117 #else
 118 static bool npt_enabled = false;
 119 #endif
 120 static int npt = 1;
 121
 122 module_param(npt, int, S_IRUGO);
 123
 124 static int nested = 1;
 125 module_param(nested, int, S_IRUGO);
 126
 127 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 128 static void svm_complete_interrupts(struct vcpu_svm *svm);
 129
 130 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 131 static int nested_svm_vmexit(struct vcpu_svm *svm);
 132 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 133                                       bool has_error_code, u32 error_code);
 134
 135 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 136 {
 137         return container_of(vcpu, struct vcpu_svm, vcpu);
 138 }
 139
 140 static inline bool is_nested(struct vcpu_svm *svm)
 141 {
 142         return svm->nested.vmcb;
 143 }
 144
 145 static inline void enable_gif(struct vcpu_svm *svm)
 146 {
 147         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 148 }
 149
 150 static inline void disable_gif(struct vcpu_svm *svm)
 151 {
 152         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 153 }
 154
 155 static inline bool gif_set(struct vcpu_svm *svm)
 156 {
 157         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 158 }
 159
 160 static unsigned long iopm_base;
 161
 162 struct kvm_ldttss_desc {
 163         u16 limit0;
 164         u16 base0;
 165         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
 166         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
 167         u32 base3;
 168         u32 zero1;
 169 } __attribute__((packed));
 170
 171 struct svm_cpu_data {
 172         int cpu;
 173
 174         u64 asid_generation;
 175         u32 max_asid;
 176         u32 next_asid;
 177         struct kvm_ldttss_desc *tss_desc;
 178
 179         struct page *save_area;
 180 };
 181
 182 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 183 static uint32_t svm_features;
 184
 185 struct svm_init_data {
 186         int cpu;
 187         int r;
 188 };
 189
 190 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 191
 192 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 193 #define MSRS_RANGE_SIZE 2048
 194 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 195
 196 #define MAX_INST_SIZE 15
 197
 198 static inline u32 svm_has(u32 feat)
 199 {
 200         return svm_features & feat;
 201 }
 202
 203 static inline void clgi(void)
 204 {
 205         asm volatile (__ex(SVM_CLGI));
 206 }
 207
 208 static inline void stgi(void)
 209 {
 210         asm volatile (__ex(SVM_STGI));
 211 }
 212
 213 static inline void invlpga(unsigned long addr, u32 asid)
 214 {
 215         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 216 }
 217
 218 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 219 {
 220         to_svm(vcpu)->asid_generation--;
 221 }
 222
 223 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 224 {
 225         force_new_asid(vcpu);
 226 }
 227
 228 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 229 {
 230         if (!npt_enabled && !(efer & EFER_LMA))
 231                 efer &= ~EFER_LME;
 232
 233         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 234         vcpu->arch.shadow_efer = efer;
 235 }
 236
 237 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 238                                 bool has_error_code, u32 error_code)
 239 {
 240         struct vcpu_svm *svm = to_svm(vcpu);
 241
 242         /* If we are within a nested VM we'd better #VMEXIT and let the
 243            guest handle the exception */
 244         if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
 245                 return;
 246
 247         svm->vmcb->control.event_inj = nr
 248                 | SVM_EVTINJ_VALID
 249                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 250                 | SVM_EVTINJ_TYPE_EXEPT;
 251         svm->vmcb->control.event_inj_err = error_code;
 252 }
 253
 254 static int is_external_interrupt(u32 info)
 255 {
 256         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 257         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 258 }
 259
 260 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 261 {
 262         struct vcpu_svm *svm = to_svm(vcpu);
 263         u32 ret = 0;
 264
 265         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 266                 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
 267         return ret & mask;
 268 }
 269
 270 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 271 {
 272         struct vcpu_svm *svm = to_svm(vcpu);
 273
 274         if (mask == 0)
 275                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 276         else
 277                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 278
 279 }
 280
 281 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 282 {
 283         struct vcpu_svm *svm = to_svm(vcpu);
 284
 285         if (!svm->next_rip) {
 286                 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
 287                                 EMULATE_DONE)
 288                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 289                 return;
 290         }
 291         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 292                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 293                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 294
 295         kvm_rip_write(vcpu, svm->next_rip);
 296         svm_set_interrupt_shadow(vcpu, 0);
 297 }
 298
 299 static int has_svm(void)
 300 {
 301         const char *msg;
 302
 303         if (!cpu_has_svm(&msg)) {
 304                 printk(KERN_INFO "has_svm: %s\n", msg);
 305                 return 0;
 306         }
 307
 308         return 1;
 309 }
 310
 311 static void svm_hardware_disable(void *garbage)
 312 {
 313         cpu_svm_disable();
 314 }
 315
 316 static int svm_hardware_enable(void *garbage)
 317 {
 318
 319         struct svm_cpu_data *sd;
 320         uint64_t efer;
 321         struct descriptor_table gdt_descr;
 322         struct desc_struct *gdt;
 323         int me = raw_smp_processor_id();
 324
 325         rdmsrl(MSR_EFER, efer);
 326         if (efer & EFER_SVME)
 327                 return -EBUSY;
 328
 329         if (!has_svm()) {
 330                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 331                        me);
 332                 return -EINVAL;
 333         }
 334         sd = per_cpu(svm_data, me);
 335
 336         if (!sd) {
 337                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 338                        me);
 339                 return -EINVAL;
 340         }
 341
 342         sd->asid_generation = 1;
 343         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 344         sd->next_asid = sd->max_asid + 1;
 345
 346         kvm_get_gdt(&gdt_descr);
 347         gdt = (struct desc_struct *)gdt_descr.base;
 348         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 349
 350         wrmsrl(MSR_EFER, efer | EFER_SVME);
 351
 352         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 353
 354         return 0;
 355 }
 356
 357 static void svm_cpu_uninit(int cpu)
 358 {
 359         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 360
 361         if (!sd)
 362                 return;
 363
 364         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 365         __free_page(sd->save_area);
 366         kfree(sd);
 367 }
 368
 369 static int svm_cpu_init(int cpu)
 370 {
 371         struct svm_cpu_data *sd;
 372         int r;
 373
 374         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 375         if (!sd)
 376                 return -ENOMEM;
 377         sd->cpu = cpu;
 378         sd->save_area = alloc_page(GFP_KERNEL);
 379         r = -ENOMEM;
 380         if (!sd->save_area)
 381                 goto err_1;
 382
 383         per_cpu(svm_data, cpu) = sd;
 384
 385         return 0;
 386
 387 err_1:
 388         kfree(sd);
 389         return r;
 390
 391 }
 392
 393 static void set_msr_interception(u32 *msrpm, unsigned msr,
 394                                  int read, int write)
 395 {
 396         int i;
 397
 398         for (i = 0; i < NUM_MSR_MAPS; i++) {
 399                 if (msr >= msrpm_ranges[i] &&
 400                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 401                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 402                                           msrpm_ranges[i]) * 2;
 403
 404                         u32 *base = msrpm + (msr_offset / 32);
 405                         u32 msr_shift = msr_offset % 32;
 406                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 407                         *base = (*base & ~(0x3 << msr_shift)) |
 408                                 (mask << msr_shift);
 409                         return;
 410                 }
 411         }
 412         BUG();
 413 }
 414
 415 static void svm_vcpu_init_msrpm(u32 *msrpm)
 416 {
 417         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 418
 419 #ifdef CONFIG_X86_64
 420         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 421         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 422         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 423         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 424         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 425         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 426 #endif
 427         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 428         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 429 }
 430
 431 static void svm_enable_lbrv(struct vcpu_svm *svm)
 432 {
 433         u32 *msrpm = svm->msrpm;
 434
 435         svm->vmcb->control.lbr_ctl = 1;
 436         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 437         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 438         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 439         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 440 }
 441
 442 static void svm_disable_lbrv(struct vcpu_svm *svm)
 443 {
 444         u32 *msrpm = svm->msrpm;
 445
 446         svm->vmcb->control.lbr_ctl = 0;
 447         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 448         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 449         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 450         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 451 }
 452
 453 static __init int svm_hardware_setup(void)
 454 {
 455         int cpu;
 456         struct page *iopm_pages;
 457         void *iopm_va;
 458         int r;
 459
 460         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 461
 462         if (!iopm_pages)
 463                 return -ENOMEM;
 464
 465         iopm_va = page_address(iopm_pages);
 466         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 467         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 468
 469         if (boot_cpu_has(X86_FEATURE_NX))
 470                 kvm_enable_efer_bits(EFER_NX);
 471
 472         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 473                 kvm_enable_efer_bits(EFER_FFXSR);
 474
 475         if (nested) {
 476                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 477                 kvm_enable_efer_bits(EFER_SVME);
 478         }
 479
 480         for_each_possible_cpu(cpu) {
 481                 r = svm_cpu_init(cpu);
 482                 if (r)
 483                         goto err;
 484         }
 485
 486         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 487
 488         if (!svm_has(SVM_FEATURE_NPT))
 489                 npt_enabled = false;
 490
 491         if (npt_enabled && !npt) {
 492                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 493                 npt_enabled = false;
 494         }
 495
 496         if (npt_enabled) {
 497                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 498                 kvm_enable_tdp();
 499         } else
 500                 kvm_disable_tdp();
 501
 502         return 0;
 503
 504 err:
 505         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 506         iopm_base = 0;
 507         return r;
 508 }
 509
 510 static __exit void svm_hardware_unsetup(void)
 511 {
 512         int cpu;
 513
 514         for_each_possible_cpu(cpu)
 515                 svm_cpu_uninit(cpu);
 516
 517         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 518         iopm_base = 0;
 519 }
 520
 521 static void init_seg(struct vmcb_seg *seg)
 522 {
 523         seg->selector = 0;
 524         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 525                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 526         seg->limit = 0xffff;
 527         seg->base = 0;
 528 }
 529
 530 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 531 {
 532         seg->selector = 0;
 533         seg->attrib = SVM_SELECTOR_P_MASK | type;
 534         seg->limit = 0xffff;
 535         seg->base = 0;
 536 }
 537
 538 static void init_vmcb(struct vcpu_svm *svm)
 539 {
 540         struct vmcb_control_area *control = &svm->vmcb->control;
 541         struct vmcb_save_area *save = &svm->vmcb->save;
 542
 543         svm->vcpu.fpu_active = 1;
 544
 545         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 546                                         INTERCEPT_CR3_MASK |
 547                                         INTERCEPT_CR4_MASK;
 548
 549         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 550                                         INTERCEPT_CR3_MASK |
 551                                         INTERCEPT_CR4_MASK |
 552                                         INTERCEPT_CR8_MASK;
 553
 554         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 555                                         INTERCEPT_DR1_MASK |
 556                                         INTERCEPT_DR2_MASK |
 557                                         INTERCEPT_DR3_MASK;
 558
 559         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 560                                         INTERCEPT_DR1_MASK |
 561                                         INTERCEPT_DR2_MASK |
 562                                         INTERCEPT_DR3_MASK |
 563                                         INTERCEPT_DR5_MASK |
 564                                         INTERCEPT_DR7_MASK;
 565
 566         control->intercept_exceptions = (1 << PF_VECTOR) |
 567                                         (1 << UD_VECTOR) |
 568                                         (1 << MC_VECTOR);
 569
 570
 571         control->intercept =    (1ULL << INTERCEPT_INTR) |
 572                                 (1ULL << INTERCEPT_NMI) |
 573                                 (1ULL << INTERCEPT_SMI) |
 574                                 (1ULL << INTERCEPT_CPUID) |
 575                                 (1ULL << INTERCEPT_INVD) |
 576                                 (1ULL << INTERCEPT_HLT) |
 577                                 (1ULL << INTERCEPT_INVLPG) |
 578                                 (1ULL << INTERCEPT_INVLPGA) |
 579                                 (1ULL << INTERCEPT_IOIO_PROT) |
 580                                 (1ULL << INTERCEPT_MSR_PROT) |
 581                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 582                                 (1ULL << INTERCEPT_SHUTDOWN) |
 583                                 (1ULL << INTERCEPT_VMRUN) |
 584                                 (1ULL << INTERCEPT_VMMCALL) |
 585                                 (1ULL << INTERCEPT_VMLOAD) |
 586                                 (1ULL << INTERCEPT_VMSAVE) |
 587                                 (1ULL << INTERCEPT_STGI) |
 588                                 (1ULL << INTERCEPT_CLGI) |
 589                                 (1ULL << INTERCEPT_SKINIT) |
 590                                 (1ULL << INTERCEPT_WBINVD) |
 591                                 (1ULL << INTERCEPT_MONITOR) |
 592                                 (1ULL << INTERCEPT_MWAIT);
 593
 594         control->iopm_base_pa = iopm_base;
 595         control->msrpm_base_pa = __pa(svm->msrpm);
 596         control->tsc_offset = 0;
 597         control->int_ctl = V_INTR_MASKING_MASK;
 598
 599         init_seg(&save->es);
 600         init_seg(&save->ss);
 601         init_seg(&save->ds);
 602         init_seg(&save->fs);
 603         init_seg(&save->gs);
 604
 605         save->cs.selector = 0xf000;
 606         /* Executable/Readable Code Segment */
 607         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 608                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 609         save->cs.limit = 0xffff;
 610         /*
 611          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 612          * be consistent with it.
 613          *
 614          * Replace when we have real mode working for vmx.
 615          */
 616         save->cs.base = 0xf0000;
 617
 618         save->gdtr.limit = 0xffff;
 619         save->idtr.limit = 0xffff;
 620
 621         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 622         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 623
 624         save->efer = EFER_SVME;
 625         save->dr6 = 0xffff0ff0;
 626         save->dr7 = 0x400;
 627         save->rflags = 2;
 628         save->rip = 0x0000fff0;
 629         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 630
 631         /* This is the guest-visible cr0 value.
 632          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
 633          */
 634         svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
 635         kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
 636
 637         save->cr4 = X86_CR4_PAE;
 638         /* rdx = ?? */
 639
 640         if (npt_enabled) {
 641                 /* Setup VMCB for Nested Paging */
 642                 control->nested_ctl = 1;
 643                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 644                                         (1ULL << INTERCEPT_INVLPG));
 645                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 646                 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
 647                 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
 648                 save->g_pat = 0x0007040600070406ULL;
 649                 save->cr3 = 0;
 650                 save->cr4 = 0;
 651         }
 652         force_new_asid(&svm->vcpu);
 653
 654         svm->nested.vmcb = 0;
 655         svm->vcpu.arch.hflags = 0;
 656
 657         if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
 658                 control->pause_filter_count = 3000;
 659                 control->intercept |= (1ULL << INTERCEPT_PAUSE);
 660         }
 661
 662         enable_gif(svm);
 663 }
 664
 665 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 666 {
 667         struct vcpu_svm *svm = to_svm(vcpu);
 668
 669         init_vmcb(svm);
 670
 671         if (!kvm_vcpu_is_bsp(vcpu)) {
 672                 kvm_rip_write(vcpu, 0);
 673                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 674                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 675         }
 676         vcpu->arch.regs_avail = ~0;
 677         vcpu->arch.regs_dirty = ~0;
 678
 679         return 0;
 680 }
 681
 682 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 683 {
 684         struct vcpu_svm *svm;
 685         struct page *page;
 686         struct page *msrpm_pages;
 687         struct page *hsave_page;
 688         struct page *nested_msrpm_pages;
 689         int err;
 690
 691         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 692         if (!svm) {
 693                 err = -ENOMEM;
 694                 goto out;
 695         }
 696
 697         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 698         if (err)
 699                 goto free_svm;
 700
 701         page = alloc_page(GFP_KERNEL);
 702         if (!page) {
 703                 err = -ENOMEM;
 704                 goto uninit;
 705         }
 706
 707         err = -ENOMEM;
 708         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 709         if (!msrpm_pages)
 710                 goto uninit;
 711
 712         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 713         if (!nested_msrpm_pages)
 714                 goto uninit;
 715
 716         svm->msrpm = page_address(msrpm_pages);
 717         svm_vcpu_init_msrpm(svm->msrpm);
 718
 719         hsave_page = alloc_page(GFP_KERNEL);
 720         if (!hsave_page)
 721                 goto uninit;
 722         svm->nested.hsave = page_address(hsave_page);
 723
 724         svm->nested.msrpm = page_address(nested_msrpm_pages);
 725
 726         svm->vmcb = page_address(page);
 727         clear_page(svm->vmcb);
 728         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 729         svm->asid_generation = 0;
 730         init_vmcb(svm);
 731
 732         fx_init(&svm->vcpu);
 733         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 734         if (kvm_vcpu_is_bsp(&svm->vcpu))
 735                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 736
 737         return &svm->vcpu;
 738
 739 uninit:
 740         kvm_vcpu_uninit(&svm->vcpu);
 741 free_svm:
 742         kmem_cache_free(kvm_vcpu_cache, svm);
 743 out:
 744         return ERR_PTR(err);
 745 }
 746
 747 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 748 {
 749         struct vcpu_svm *svm = to_svm(vcpu);
 750
 751         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 752         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 753         __free_page(virt_to_page(svm->nested.hsave));
 754         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
 755         kvm_vcpu_uninit(vcpu);
 756         kmem_cache_free(kvm_vcpu_cache, svm);
 757 }
 758
 759 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 760 {
 761         struct vcpu_svm *svm = to_svm(vcpu);
 762         int i;
 763
 764         if (unlikely(cpu != vcpu->cpu)) {
 765                 u64 delta;
 766
 767                 if (check_tsc_unstable()) {
 768                         /*
 769                          * Make sure that the guest sees a monotonically
 770                          * increasing TSC.
 771                          */
 772                         delta = vcpu->arch.host_tsc - native_read_tsc();
 773                         svm->vmcb->control.tsc_offset += delta;
 774                         if (is_nested(svm))
 775                                 svm->nested.hsave->control.tsc_offset += delta;
 776                 }
 777                 vcpu->cpu = cpu;
 778                 kvm_migrate_timers(vcpu);
 779                 svm->asid_generation = 0;
 780         }
 781
 782         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 783                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 784 }
 785
 786 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 787 {
 788         struct vcpu_svm *svm = to_svm(vcpu);
 789         int i;
 790
 791         ++vcpu->stat.host_state_reload;
 792         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 793                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 794
 795         vcpu->arch.host_tsc = native_read_tsc();
 796 }
 797
 798 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 799 {
 800         return to_svm(vcpu)->vmcb->save.rflags;
 801 }
 802
 803 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 804 {
 805         to_svm(vcpu)->vmcb->save.rflags = rflags;
 806 }
 807
 808 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
 809 {
 810         switch (reg) {
 811         case VCPU_EXREG_PDPTR:
 812                 BUG_ON(!npt_enabled);
 813                 load_pdptrs(vcpu, vcpu->arch.cr3);
 814                 break;
 815         default:
 816                 BUG();
 817         }
 818 }
 819
 820 static void svm_set_vintr(struct vcpu_svm *svm)
 821 {
 822         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 823 }
 824
 825 static void svm_clear_vintr(struct vcpu_svm *svm)
 826 {
 827         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 828 }
 829
 830 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 831 {
 832         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 833
 834         switch (seg) {
 835         case VCPU_SREG_CS: return &save->cs;
 836         case VCPU_SREG_DS: return &save->ds;
 837         case VCPU_SREG_ES: return &save->es;
 838         case VCPU_SREG_FS: return &save->fs;
 839         case VCPU_SREG_GS: return &save->gs;
 840         case VCPU_SREG_SS: return &save->ss;
 841         case VCPU_SREG_TR: return &save->tr;
 842         case VCPU_SREG_LDTR: return &save->ldtr;
 843         }
 844         BUG();
 845         return NULL;
 846 }
 847
 848 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 849 {
 850         struct vmcb_seg *s = svm_seg(vcpu, seg);
 851
 852         return s->base;
 853 }
 854
 855 static void svm_get_segment(struct kvm_vcpu *vcpu,
 856                             struct kvm_segment *var, int seg)
 857 {
 858         struct vmcb_seg *s = svm_seg(vcpu, seg);
 859
 860         var->base = s->base;
 861         var->limit = s->limit;
 862         var->selector = s->selector;
 863         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 864         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 865         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 866         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 867         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 868         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 869         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 870         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 871
 872         /* AMD's VMCB does not have an explicit unusable field, so emulate it
 873          * for cross vendor migration purposes by "not present"
 874          */
 875         var->unusable = !var->present || (var->type == 0);
 876
 877         switch (seg) {
 878         case VCPU_SREG_CS:
 879                 /*
 880                  * SVM always stores 0 for the 'G' bit in the CS selector in
 881                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 882                  * Intel's VMENTRY has a check on the 'G' bit.
 883                  */
 884                 var->g = s->limit > 0xfffff;
 885                 break;
 886         case VCPU_SREG_TR:
 887                 /*
 888                  * Work around a bug where the busy flag in the tr selector
 889                  * isn't exposed
 890                  */
 891                 var->type |= 0x2;
 892                 break;
 893         case VCPU_SREG_DS:
 894         case VCPU_SREG_ES:
 895         case VCPU_SREG_FS:
 896         case VCPU_SREG_GS:
 897                 /*
 898                  * The accessed bit must always be set in the segment
 899                  * descriptor cache, although it can be cleared in the
 900                  * descriptor, the cached bit always remains at 1. Since
 901                  * Intel has a check on this, set it here to support
 902                  * cross-vendor migration.
 903                  */
 904                 if (!var->unusable)
 905                         var->type |= 0x1;
 906                 break;
 907         case VCPU_SREG_SS:
 908                 /* On AMD CPUs sometimes the DB bit in the segment
 909                  * descriptor is left as 1, although the whole segment has
 910                  * been made unusable. Clear it here to pass an Intel VMX
 911                  * entry check when cross vendor migrating.
 912                  */
 913                 if (var->unusable)
 914                         var->db = 0;
 915                 break;
 916         }
 917 }
 918
 919 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 920 {
 921         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 922
 923         return save->cpl;
 924 }
 925
 926 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 927 {
 928         struct vcpu_svm *svm = to_svm(vcpu);
 929
 930         dt->limit = svm->vmcb->save.idtr.limit;
 931         dt->base = svm->vmcb->save.idtr.base;
 932 }
 933
 934 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 935 {
 936         struct vcpu_svm *svm = to_svm(vcpu);
 937
 938         svm->vmcb->save.idtr.limit = dt->limit;
 939         svm->vmcb->save.idtr.base = dt->base ;
 940 }
 941
 942 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 943 {
 944         struct vcpu_svm *svm = to_svm(vcpu);
 945
 946         dt->limit = svm->vmcb->save.gdtr.limit;
 947         dt->base = svm->vmcb->save.gdtr.base;
 948 }
 949
 950 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 951 {
 952         struct vcpu_svm *svm = to_svm(vcpu);
 953
 954         svm->vmcb->save.gdtr.limit = dt->limit;
 955         svm->vmcb->save.gdtr.base = dt->base ;
 956 }
 957
 958 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
 959 {
 960 }
 961
 962 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 963 {
 964 }
 965
 966 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 967 {
 968         struct vcpu_svm *svm = to_svm(vcpu);
 969
 970 #ifdef CONFIG_X86_64
 971         if (vcpu->arch.shadow_efer & EFER_LME) {
 972                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 973                         vcpu->arch.shadow_efer |= EFER_LMA;
 974                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 975                 }
 976
 977                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 978                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 979                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 980                 }
 981         }
 982 #endif
 983         vcpu->arch.cr0 = cr0;
 984
 985         if (!npt_enabled)
 986                 cr0 |= X86_CR0_PG | X86_CR0_WP;
 987
 988         if (!vcpu->fpu_active)
 989                 cr0 |= X86_CR0_TS;
 990         /*
 991          * re-enable caching here because the QEMU bios
 992          * does not do it - this results in some delay at
 993          * reboot
 994          */
 995         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 996         svm->vmcb->save.cr0 = cr0;
 997 }
 998
 999 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1000 {
1001         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1002         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1003
1004         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1005                 force_new_asid(vcpu);
1006
1007         vcpu->arch.cr4 = cr4;
1008         if (!npt_enabled)
1009                 cr4 |= X86_CR4_PAE;
1010         cr4 |= host_cr4_mce;
1011         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1012 }
1013
1014 static void svm_set_segment(struct kvm_vcpu *vcpu,
1015                             struct kvm_segment *var, int seg)
1016 {
1017         struct vcpu_svm *svm = to_svm(vcpu);
1018         struct vmcb_seg *s = svm_seg(vcpu, seg);
1019
1020         s->base = var->base;
1021         s->limit = var->limit;
1022         s->selector = var->selector;
1023         if (var->unusable)
1024                 s->attrib = 0;
1025         else {
1026                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1027                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1028                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1029                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1030                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1031                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1032                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1033                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1034         }
1035         if (seg == VCPU_SREG_CS)
1036                 svm->vmcb->save.cpl
1037                         = (svm->vmcb->save.cs.attrib
1038                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1039
1040 }
1041
1042 static void update_db_intercept(struct kvm_vcpu *vcpu)
1043 {
1044         struct vcpu_svm *svm = to_svm(vcpu);
1045
1046         svm->vmcb->control.intercept_exceptions &=
1047                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1048
1049         if (svm->nmi_singlestep)
1050                 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1051
1052         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1053                 if (vcpu->guest_debug &
1054                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1055                         svm->vmcb->control.intercept_exceptions |=
1056                                 1 << DB_VECTOR;
1057                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1058                         svm->vmcb->control.intercept_exceptions |=
1059                                 1 << BP_VECTOR;
1060         } else
1061                 vcpu->guest_debug = 0;
1062 }
1063
1064 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1065 {
1066         struct vcpu_svm *svm = to_svm(vcpu);
1067
1068         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1069                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1070         else
1071                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1072
1073         update_db_intercept(vcpu);
1074 }
1075
1076 static void load_host_msrs(struct kvm_vcpu *vcpu)
1077 {
1078 #ifdef CONFIG_X86_64
1079         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1080 #endif
1081 }
1082
1083 static void save_host_msrs(struct kvm_vcpu *vcpu)
1084 {
1085 #ifdef CONFIG_X86_64
1086         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1087 #endif
1088 }
1089
1090 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1091 {
1092         if (sd->next_asid > sd->max_asid) {
1093                 ++sd->asid_generation;
1094                 sd->next_asid = 1;
1095                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1096         }
1097
1098         svm->asid_generation = sd->asid_generation;
1099         svm->vmcb->control.asid = sd->next_asid++;
1100 }
1101
1102 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1103 {
1104         struct vcpu_svm *svm = to_svm(vcpu);
1105         unsigned long val;
1106
1107         switch (dr) {
1108         case 0 ... 3:
1109                 val = vcpu->arch.db[dr];
1110                 break;
1111         case 6:
1112                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1113                         val = vcpu->arch.dr6;
1114                 else
1115                         val = svm->vmcb->save.dr6;
1116                 break;
1117         case 7:
1118                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1119                         val = vcpu->arch.dr7;
1120                 else
1121                         val = svm->vmcb->save.dr7;
1122                 break;
1123         default:
1124                 val = 0;
1125         }
1126
1127         return val;
1128 }
1129
1130 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1131                        int *exception)
1132 {
1133         struct vcpu_svm *svm = to_svm(vcpu);
1134
1135         *exception = 0;
1136
1137         switch (dr) {
1138         case 0 ... 3:
1139                 vcpu->arch.db[dr] = value;
1140                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1141                         vcpu->arch.eff_db[dr] = value;
1142                 return;
1143         case 4 ... 5:
1144                 if (vcpu->arch.cr4 & X86_CR4_DE)
1145                         *exception = UD_VECTOR;
1146                 return;
1147         case 6:
1148                 if (value & 0xffffffff00000000ULL) {
1149                         *exception = GP_VECTOR;
1150                         return;
1151                 }
1152                 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1153                 return;
1154         case 7:
1155                 if (value & 0xffffffff00000000ULL) {
1156                         *exception = GP_VECTOR;
1157                         return;
1158                 }
1159                 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1160                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1161                         svm->vmcb->save.dr7 = vcpu->arch.dr7;
1162                         vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1163                 }
1164                 return;
1165         default:
1166                 /* FIXME: Possible case? */
1167                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1168                        __func__, dr);
1169                 *exception = UD_VECTOR;
1170                 return;
1171         }
1172 }
1173
1174 static int pf_interception(struct vcpu_svm *svm)
1175 {
1176         u64 fault_address;
1177         u32 error_code;
1178
1179         fault_address  = svm->vmcb->control.exit_info_2;
1180         error_code = svm->vmcb->control.exit_info_1;
1181
1182         trace_kvm_page_fault(fault_address, error_code);
1183         if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1184                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1185         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1186 }
1187
1188 static int db_interception(struct vcpu_svm *svm)
1189 {
1190         struct kvm_run *kvm_run = svm->vcpu.run;
1191
1192         if (!(svm->vcpu.guest_debug &
1193               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1194                 !svm->nmi_singlestep) {
1195                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1196                 return 1;
1197         }
1198
1199         if (svm->nmi_singlestep) {
1200                 svm->nmi_singlestep = false;
1201                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1202                         svm->vmcb->save.rflags &=
1203                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1204                 update_db_intercept(&svm->vcpu);
1205         }
1206
1207         if (svm->vcpu.guest_debug &
1208             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1209                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1210                 kvm_run->debug.arch.pc =
1211                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1212                 kvm_run->debug.arch.exception = DB_VECTOR;
1213                 return 0;
1214         }
1215
1216         return 1;
1217 }
1218
1219 static int bp_interception(struct vcpu_svm *svm)
1220 {
1221         struct kvm_run *kvm_run = svm->vcpu.run;
1222
1223         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1224         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1225         kvm_run->debug.arch.exception = BP_VECTOR;
1226         return 0;
1227 }
1228
1229 static int ud_interception(struct vcpu_svm *svm)
1230 {
1231         int er;
1232
1233         er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1234         if (er != EMULATE_DONE)
1235                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1236         return 1;
1237 }
1238
1239 static int nm_interception(struct vcpu_svm *svm)
1240 {
1241         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1242         if (!kvm_read_cr0_bits(&svm->vcpu, X86_CR0_TS))
1243                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1244         else
1245                 svm->vmcb->save.cr0 |= X86_CR0_TS;
1246         svm->vcpu.fpu_active = 1;
1247
1248         return 1;
1249 }
1250
1251 static int mc_interception(struct vcpu_svm *svm)
1252 {
1253         /*
1254          * On an #MC intercept the MCE handler is not called automatically in
1255          * the host. So do it by hand here.
1256          */
1257         asm volatile (
1258                 "int $0x12\n");
1259         /* not sure if we ever come back to this point */
1260
1261         return 1;
1262 }
1263
1264 static int shutdown_interception(struct vcpu_svm *svm)
1265 {
1266         struct kvm_run *kvm_run = svm->vcpu.run;
1267
1268         /*
1269          * VMCB is undefined after a SHUTDOWN intercept
1270          * so reinitialize it.
1271          */
1272         clear_page(svm->vmcb);
1273         init_vmcb(svm);
1274
1275         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1276         return 0;
1277 }
1278
1279 static int io_interception(struct vcpu_svm *svm)
1280 {
1281         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1282         int size, in, string;
1283         unsigned port;
1284
1285         ++svm->vcpu.stat.io_exits;
1286
1287         svm->next_rip = svm->vmcb->control.exit_info_2;
1288
1289         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1290
1291         if (string) {
1292                 if (emulate_instruction(&svm->vcpu,
1293                                         0, 0, 0) == EMULATE_DO_MMIO)
1294                         return 0;
1295                 return 1;
1296         }
1297
1298         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1299         port = io_info >> 16;
1300         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1301
1302         skip_emulated_instruction(&svm->vcpu);
1303         return kvm_emulate_pio(&svm->vcpu, in, size, port);
1304 }
1305
1306 static int nmi_interception(struct vcpu_svm *svm)
1307 {
1308         return 1;
1309 }
1310
1311 static int intr_interception(struct vcpu_svm *svm)
1312 {
1313         ++svm->vcpu.stat.irq_exits;
1314         return 1;
1315 }
1316
1317 static int nop_on_interception(struct vcpu_svm *svm)
1318 {
1319         return 1;
1320 }
1321
1322 static int halt_interception(struct vcpu_svm *svm)
1323 {
1324         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1325         skip_emulated_instruction(&svm->vcpu);
1326         return kvm_emulate_halt(&svm->vcpu);
1327 }
1328
1329 static int vmmcall_interception(struct vcpu_svm *svm)
1330 {
1331         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1332         skip_emulated_instruction(&svm->vcpu);
1333         kvm_emulate_hypercall(&svm->vcpu);
1334         return 1;
1335 }
1336
1337 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1338 {
1339         if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1340             || !is_paging(&svm->vcpu)) {
1341                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1342                 return 1;
1343         }
1344
1345         if (svm->vmcb->save.cpl) {
1346                 kvm_inject_gp(&svm->vcpu, 0);
1347                 return 1;
1348         }
1349
1350        return 0;
1351 }
1352
1353 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1354                                       bool has_error_code, u32 error_code)
1355 {
1356         if (!is_nested(svm))
1357                 return 0;
1358
1359         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1360         svm->vmcb->control.exit_code_hi = 0;
1361         svm->vmcb->control.exit_info_1 = error_code;
1362         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1363
1364         return nested_svm_exit_handled(svm);
1365 }
1366
1367 static inline int nested_svm_intr(struct vcpu_svm *svm)
1368 {
1369         if (!is_nested(svm))
1370                 return 0;
1371
1372         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1373                 return 0;
1374
1375         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1376                 return 0;
1377
1378         svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1379
1380         if (svm->nested.intercept & 1ULL) {
1381                 /*
1382                  * The #vmexit can't be emulated here directly because this
1383                  * code path runs with irqs and preemtion disabled. A
1384                  * #vmexit emulation might sleep. Only signal request for
1385                  * the #vmexit here.
1386                  */
1387                 svm->nested.exit_required = true;
1388                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1389                 return 1;
1390         }
1391
1392         return 0;
1393 }
1394
1395 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1396 {
1397         struct page *page;
1398
1399         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1400         if (is_error_page(page))
1401                 goto error;
1402
1403         return kmap_atomic(page, idx);
1404
1405 error:
1406         kvm_release_page_clean(page);
1407         kvm_inject_gp(&svm->vcpu, 0);
1408
1409         return NULL;
1410 }
1411
1412 static void nested_svm_unmap(void *addr, enum km_type idx)
1413 {
1414         struct page *page;
1415
1416         if (!addr)
1417                 return;
1418
1419         page = kmap_atomic_to_page(addr);
1420
1421         kunmap_atomic(addr, idx);
1422         kvm_release_page_dirty(page);
1423 }
1424
1425 static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1426 {
1427         u32 param = svm->vmcb->control.exit_info_1 & 1;
1428         u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1429         bool ret = false;
1430         u32 t0, t1;
1431         u8 *msrpm;
1432
1433         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1434                 return false;
1435
1436         msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1437
1438         if (!msrpm)
1439                 goto out;
1440
1441         switch (msr) {
1442         case 0 ... 0x1fff:
1443                 t0 = (msr * 2) % 8;
1444                 t1 = msr / 8;
1445                 break;
1446         case 0xc0000000 ... 0xc0001fff:
1447                 t0 = (8192 + msr - 0xc0000000) * 2;
1448                 t1 = (t0 / 8);
1449                 t0 %= 8;
1450                 break;
1451         case 0xc0010000 ... 0xc0011fff:
1452                 t0 = (16384 + msr - 0xc0010000) * 2;
1453                 t1 = (t0 / 8);
1454                 t0 %= 8;
1455                 break;
1456         default:
1457                 ret = true;
1458                 goto out;
1459         }
1460
1461         ret = msrpm[t1] & ((1 << param) << t0);
1462
1463 out:
1464         nested_svm_unmap(msrpm, KM_USER0);
1465
1466         return ret;
1467 }
1468
1469 static int nested_svm_exit_special(struct vcpu_svm *svm)
1470 {
1471         u32 exit_code = svm->vmcb->control.exit_code;
1472
1473         switch (exit_code) {
1474         case SVM_EXIT_INTR:
1475         case SVM_EXIT_NMI:
1476                 return NESTED_EXIT_HOST;
1477                 /* For now we are always handling NPFs when using them */
1478         case SVM_EXIT_NPF:
1479                 if (npt_enabled)
1480                         return NESTED_EXIT_HOST;
1481                 break;
1482         /* When we're shadowing, trap PFs */
1483         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1484                 if (!npt_enabled)
1485                         return NESTED_EXIT_HOST;
1486                 break;
1487         default:
1488                 break;
1489         }
1490
1491         return NESTED_EXIT_CONTINUE;
1492 }
1493
1494 /*
1495  * If this function returns true, this #vmexit was already handled
1496  */
1497 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1498 {
1499         u32 exit_code = svm->vmcb->control.exit_code;
1500         int vmexit = NESTED_EXIT_HOST;
1501
1502         switch (exit_code) {
1503         case SVM_EXIT_MSR:
1504                 vmexit = nested_svm_exit_handled_msr(svm);
1505                 break;
1506         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1507                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1508                 if (svm->nested.intercept_cr_read & cr_bits)
1509                         vmexit = NESTED_EXIT_DONE;
1510                 break;
1511         }
1512         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1513                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1514                 if (svm->nested.intercept_cr_write & cr_bits)
1515                         vmexit = NESTED_EXIT_DONE;
1516                 break;
1517         }
1518         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1519                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1520                 if (svm->nested.intercept_dr_read & dr_bits)
1521                         vmexit = NESTED_EXIT_DONE;
1522                 break;
1523         }
1524         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1525                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1526                 if (svm->nested.intercept_dr_write & dr_bits)
1527                         vmexit = NESTED_EXIT_DONE;
1528                 break;
1529         }
1530         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1531                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1532                 if (svm->nested.intercept_exceptions & excp_bits)
1533                         vmexit = NESTED_EXIT_DONE;
1534                 break;
1535         }
1536         default: {
1537                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1538                 if (svm->nested.intercept & exit_bits)
1539                         vmexit = NESTED_EXIT_DONE;
1540         }
1541         }
1542
1543         if (vmexit == NESTED_EXIT_DONE) {
1544                 nested_svm_vmexit(svm);
1545         }
1546
1547         return vmexit;
1548 }
1549
1550 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1551 {
1552         struct vmcb_control_area *dst  = &dst_vmcb->control;
1553         struct vmcb_control_area *from = &from_vmcb->control;
1554
1555         dst->intercept_cr_read    = from->intercept_cr_read;
1556         dst->intercept_cr_write   = from->intercept_cr_write;
1557         dst->intercept_dr_read    = from->intercept_dr_read;
1558         dst->intercept_dr_write   = from->intercept_dr_write;
1559         dst->intercept_exceptions = from->intercept_exceptions;
1560         dst->intercept            = from->intercept;
1561         dst->iopm_base_pa         = from->iopm_base_pa;
1562         dst->msrpm_base_pa        = from->msrpm_base_pa;
1563         dst->tsc_offset           = from->tsc_offset;
1564         dst->asid                 = from->asid;
1565         dst->tlb_ctl              = from->tlb_ctl;
1566         dst->int_ctl              = from->int_ctl;
1567         dst->int_vector           = from->int_vector;
1568         dst->int_state            = from->int_state;
1569         dst->exit_code            = from->exit_code;
1570         dst->exit_code_hi         = from->exit_code_hi;
1571         dst->exit_info_1          = from->exit_info_1;
1572         dst->exit_info_2          = from->exit_info_2;
1573         dst->exit_int_info        = from->exit_int_info;
1574         dst->exit_int_info_err    = from->exit_int_info_err;
1575         dst->nested_ctl           = from->nested_ctl;
1576         dst->event_inj            = from->event_inj;
1577         dst->event_inj_err        = from->event_inj_err;
1578         dst->nested_cr3           = from->nested_cr3;
1579         dst->lbr_ctl              = from->lbr_ctl;
1580 }
1581
1582 static int nested_svm_vmexit(struct vcpu_svm *svm)
1583 {
1584         struct vmcb *nested_vmcb;
1585         struct vmcb *hsave = svm->nested.hsave;
1586         struct vmcb *vmcb = svm->vmcb;
1587
1588         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1589                                        vmcb->control.exit_info_1,
1590                                        vmcb->control.exit_info_2,
1591                                        vmcb->control.exit_int_info,
1592                                        vmcb->control.exit_int_info_err);
1593
1594         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1595         if (!nested_vmcb)
1596                 return 1;
1597
1598         /* Give the current vmcb to the guest */
1599         disable_gif(svm);
1600
1601         nested_vmcb->save.es     = vmcb->save.es;
1602         nested_vmcb->save.cs     = vmcb->save.cs;
1603         nested_vmcb->save.ss     = vmcb->save.ss;
1604         nested_vmcb->save.ds     = vmcb->save.ds;
1605         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
1606         nested_vmcb->save.idtr   = vmcb->save.idtr;
1607         if (npt_enabled)
1608                 nested_vmcb->save.cr3    = vmcb->save.cr3;
1609         nested_vmcb->save.cr2    = vmcb->save.cr2;
1610         nested_vmcb->save.rflags = vmcb->save.rflags;
1611         nested_vmcb->save.rip    = vmcb->save.rip;
1612         nested_vmcb->save.rsp    = vmcb->save.rsp;
1613         nested_vmcb->save.rax    = vmcb->save.rax;
1614         nested_vmcb->save.dr7    = vmcb->save.dr7;
1615         nested_vmcb->save.dr6    = vmcb->save.dr6;
1616         nested_vmcb->save.cpl    = vmcb->save.cpl;
1617
1618         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
1619         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
1620         nested_vmcb->control.int_state         = vmcb->control.int_state;
1621         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
1622         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
1623         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
1624         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
1625         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
1626         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1627
1628         /*
1629          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1630          * to make sure that we do not lose injected events. So check event_inj
1631          * here and copy it to exit_int_info if it is valid.
1632          * Exit_int_info and event_inj can't be both valid because the case
1633          * below only happens on a VMRUN instruction intercept which has
1634          * no valid exit_int_info set.
1635          */
1636         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1637                 struct vmcb_control_area *nc = &nested_vmcb->control;
1638
1639                 nc->exit_int_info     = vmcb->control.event_inj;
1640                 nc->exit_int_info_err = vmcb->control.event_inj_err;
1641         }
1642
1643         nested_vmcb->control.tlb_ctl           = 0;
1644         nested_vmcb->control.event_inj         = 0;
1645         nested_vmcb->control.event_inj_err     = 0;
1646
1647         /* We always set V_INTR_MASKING and remember the old value in hflags */
1648         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1649                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1650
1651         /* Restore the original control entries */
1652         copy_vmcb_control_area(vmcb, hsave);
1653
1654         kvm_clear_exception_queue(&svm->vcpu);
1655         kvm_clear_interrupt_queue(&svm->vcpu);
1656
1657         /* Restore selected save entries */
1658         svm->vmcb->save.es = hsave->save.es;
1659         svm->vmcb->save.cs = hsave->save.cs;
1660         svm->vmcb->save.ss = hsave->save.ss;
1661         svm->vmcb->save.ds = hsave->save.ds;
1662         svm->vmcb->save.gdtr = hsave->save.gdtr;
1663         svm->vmcb->save.idtr = hsave->save.idtr;
1664         svm->vmcb->save.rflags = hsave->save.rflags;
1665         svm_set_efer(&svm->vcpu, hsave->save.efer);
1666         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1667         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1668         if (npt_enabled) {
1669                 svm->vmcb->save.cr3 = hsave->save.cr3;
1670                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1671         } else {
1672                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1673         }
1674         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1675         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1676         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1677         svm->vmcb->save.dr7 = 0;
1678         svm->vmcb->save.cpl = 0;
1679         svm->vmcb->control.exit_int_info = 0;
1680
1681         /* Exit nested SVM mode */
1682         svm->nested.vmcb = 0;
1683
1684         nested_svm_unmap(nested_vmcb, KM_USER0);
1685
1686         kvm_mmu_reset_context(&svm->vcpu);
1687         kvm_mmu_load(&svm->vcpu);
1688
1689         return 0;
1690 }
1691
1692 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1693 {
1694         u32 *nested_msrpm;
1695         int i;
1696
1697         nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1698         if (!nested_msrpm)
1699                 return false;
1700
1701         for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1702                 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1703
1704         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1705
1706         nested_svm_unmap(nested_msrpm, KM_USER0);
1707
1708         return true;
1709 }
1710
1711 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1712 {
1713         struct vmcb *nested_vmcb;
1714         struct vmcb *hsave = svm->nested.hsave;
1715         struct vmcb *vmcb = svm->vmcb;
1716
1717         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1718         if (!nested_vmcb)
1719                 return false;
1720
1721         /* nested_vmcb is our indicator if nested SVM is activated */
1722         svm->nested.vmcb = svm->vmcb->save.rax;
1723
1724         trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb,
1725                                nested_vmcb->save.rip,
1726                                nested_vmcb->control.int_ctl,
1727                                nested_vmcb->control.event_inj,
1728                                nested_vmcb->control.nested_ctl);
1729
1730         /* Clear internal status */
1731         kvm_clear_exception_queue(&svm->vcpu);
1732         kvm_clear_interrupt_queue(&svm->vcpu);
1733
1734         /* Save the old vmcb, so we don't need to pick what we save, but
1735            can restore everything when a VMEXIT occurs */
1736         hsave->save.es     = vmcb->save.es;
1737         hsave->save.cs     = vmcb->save.cs;
1738         hsave->save.ss     = vmcb->save.ss;
1739         hsave->save.ds     = vmcb->save.ds;
1740         hsave->save.gdtr   = vmcb->save.gdtr;
1741         hsave->save.idtr   = vmcb->save.idtr;
1742         hsave->save.efer   = svm->vcpu.arch.shadow_efer;
1743         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
1744         hsave->save.cr4    = svm->vcpu.arch.cr4;
1745         hsave->save.rflags = vmcb->save.rflags;
1746         hsave->save.rip    = svm->next_rip;
1747         hsave->save.rsp    = vmcb->save.rsp;
1748         hsave->save.rax    = vmcb->save.rax;
1749         if (npt_enabled)
1750                 hsave->save.cr3    = vmcb->save.cr3;
1751         else
1752                 hsave->save.cr3    = svm->vcpu.arch.cr3;
1753
1754         copy_vmcb_control_area(hsave, vmcb);
1755
1756         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1757                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1758         else
1759                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1760
1761         /* Load the nested guest state */
1762         svm->vmcb->save.es = nested_vmcb->save.es;
1763         svm->vmcb->save.cs = nested_vmcb->save.cs;
1764         svm->vmcb->save.ss = nested_vmcb->save.ss;
1765         svm->vmcb->save.ds = nested_vmcb->save.ds;
1766         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1767         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1768         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1769         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1770         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1771         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1772         if (npt_enabled) {
1773                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1774                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1775         } else {
1776                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1777                 kvm_mmu_reset_context(&svm->vcpu);
1778         }
1779         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
1780         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1781         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1782         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1783         /* In case we don't even reach vcpu_run, the fields are not updated */
1784         svm->vmcb->save.rax = nested_vmcb->save.rax;
1785         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1786         svm->vmcb->save.rip = nested_vmcb->save.rip;
1787         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1788         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1789         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1790
1791         /* We don't want a nested guest to be more powerful than the guest,
1792            so all intercepts are ORed */
1793         svm->vmcb->control.intercept_cr_read |=
1794                 nested_vmcb->control.intercept_cr_read;
1795         svm->vmcb->control.intercept_cr_write |=
1796                 nested_vmcb->control.intercept_cr_write;
1797         svm->vmcb->control.intercept_dr_read |=
1798                 nested_vmcb->control.intercept_dr_read;
1799         svm->vmcb->control.intercept_dr_write |=
1800                 nested_vmcb->control.intercept_dr_write;
1801         svm->vmcb->control.intercept_exceptions |=
1802                 nested_vmcb->control.intercept_exceptions;
1803
1804         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1805
1806         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1807
1808         /* cache intercepts */
1809         svm->nested.intercept_cr_read    = nested_vmcb->control.intercept_cr_read;
1810         svm->nested.intercept_cr_write   = nested_vmcb->control.intercept_cr_write;
1811         svm->nested.intercept_dr_read    = nested_vmcb->control.intercept_dr_read;
1812         svm->nested.intercept_dr_write   = nested_vmcb->control.intercept_dr_write;
1813         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1814         svm->nested.intercept            = nested_vmcb->control.intercept;
1815
1816         force_new_asid(&svm->vcpu);
1817         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1818         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1819                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1820         else
1821                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1822
1823         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1824         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1825         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1826         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1827         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1828
1829         nested_svm_unmap(nested_vmcb, KM_USER0);
1830
1831         enable_gif(svm);
1832
1833         return true;
1834 }
1835
1836 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1837 {
1838         to_vmcb->save.fs = from_vmcb->save.fs;
1839         to_vmcb->save.gs = from_vmcb->save.gs;
1840         to_vmcb->save.tr = from_vmcb->save.tr;
1841         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1842         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1843         to_vmcb->save.star = from_vmcb->save.star;
1844         to_vmcb->save.lstar = from_vmcb->save.lstar;
1845         to_vmcb->save.cstar = from_vmcb->save.cstar;
1846         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1847         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1848         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1849         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1850 }
1851
1852 static int vmload_interception(struct vcpu_svm *svm)
1853 {
1854         struct vmcb *nested_vmcb;
1855
1856         if (nested_svm_check_permissions(svm))
1857                 return 1;
1858
1859         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1860         skip_emulated_instruction(&svm->vcpu);
1861
1862         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1863         if (!nested_vmcb)
1864                 return 1;
1865
1866         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1867         nested_svm_unmap(nested_vmcb, KM_USER0);
1868
1869         return 1;
1870 }
1871
1872 static int vmsave_interception(struct vcpu_svm *svm)
1873 {
1874         struct vmcb *nested_vmcb;
1875
1876         if (nested_svm_check_permissions(svm))
1877                 return 1;
1878
1879         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1880         skip_emulated_instruction(&svm->vcpu);
1881
1882         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1883         if (!nested_vmcb)
1884                 return 1;
1885
1886         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1887         nested_svm_unmap(nested_vmcb, KM_USER0);
1888
1889         return 1;
1890 }
1891
1892 static int vmrun_interception(struct vcpu_svm *svm)
1893 {
1894         if (nested_svm_check_permissions(svm))
1895                 return 1;
1896
1897         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1898         skip_emulated_instruction(&svm->vcpu);
1899
1900         if (!nested_svm_vmrun(svm))
1901                 return 1;
1902
1903         if (!nested_svm_vmrun_msrpm(svm))
1904                 goto failed;
1905
1906         return 1;
1907
1908 failed:
1909
1910         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
1911         svm->vmcb->control.exit_code_hi = 0;
1912         svm->vmcb->control.exit_info_1  = 0;
1913         svm->vmcb->control.exit_info_2  = 0;
1914
1915         nested_svm_vmexit(svm);
1916
1917         return 1;
1918 }
1919
1920 static int stgi_interception(struct vcpu_svm *svm)
1921 {
1922         if (nested_svm_check_permissions(svm))
1923                 return 1;
1924
1925         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1926         skip_emulated_instruction(&svm->vcpu);
1927
1928         enable_gif(svm);
1929
1930         return 1;
1931 }
1932
1933 static int clgi_interception(struct vcpu_svm *svm)
1934 {
1935         if (nested_svm_check_permissions(svm))
1936                 return 1;
1937
1938         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1939         skip_emulated_instruction(&svm->vcpu);
1940
1941         disable_gif(svm);
1942
1943         /* After a CLGI no interrupts should come */
1944         svm_clear_vintr(svm);
1945         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1946
1947         return 1;
1948 }
1949
1950 static int invlpga_interception(struct vcpu_svm *svm)
1951 {
1952         struct kvm_vcpu *vcpu = &svm->vcpu;
1953
1954         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
1955                           vcpu->arch.regs[VCPU_REGS_RAX]);
1956
1957         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1958         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1959
1960         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1961         skip_emulated_instruction(&svm->vcpu);
1962         return 1;
1963 }
1964
1965 static int skinit_interception(struct vcpu_svm *svm)
1966 {
1967         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
1968
1969         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1970         return 1;
1971 }
1972
1973 static int invalid_op_interception(struct vcpu_svm *svm)
1974 {
1975         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1976         return 1;
1977 }
1978
1979 static int task_switch_interception(struct vcpu_svm *svm)
1980 {
1981         u16 tss_selector;
1982         int reason;
1983         int int_type = svm->vmcb->control.exit_int_info &
1984                 SVM_EXITINTINFO_TYPE_MASK;
1985         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
1986         uint32_t type =
1987                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1988         uint32_t idt_v =
1989                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
1990
1991         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1992
1993         if (svm->vmcb->control.exit_info_2 &
1994             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1995                 reason = TASK_SWITCH_IRET;
1996         else if (svm->vmcb->control.exit_info_2 &
1997                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1998                 reason = TASK_SWITCH_JMP;
1999         else if (idt_v)
2000                 reason = TASK_SWITCH_GATE;
2001         else
2002                 reason = TASK_SWITCH_CALL;
2003
2004         if (reason == TASK_SWITCH_GATE) {
2005                 switch (type) {
2006                 case SVM_EXITINTINFO_TYPE_NMI:
2007                         svm->vcpu.arch.nmi_injected = false;
2008                         break;
2009                 case SVM_EXITINTINFO_TYPE_EXEPT:
2010                         kvm_clear_exception_queue(&svm->vcpu);
2011                         break;
2012                 case SVM_EXITINTINFO_TYPE_INTR:
2013                         kvm_clear_interrupt_queue(&svm->vcpu);
2014                         break;
2015                 default:
2016                         break;
2017                 }
2018         }
2019
2020         if (reason != TASK_SWITCH_GATE ||
2021             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2022             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2023              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2024                 skip_emulated_instruction(&svm->vcpu);
2025
2026         return kvm_task_switch(&svm->vcpu, tss_selector, reason);
2027 }
2028
2029 static int cpuid_interception(struct vcpu_svm *svm)
2030 {
2031         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2032         kvm_emulate_cpuid(&svm->vcpu);
2033         return 1;
2034 }
2035
2036 static int iret_interception(struct vcpu_svm *svm)
2037 {
2038         ++svm->vcpu.stat.nmi_window_exits;
2039         svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2040         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2041         return 1;
2042 }
2043
2044 static int invlpg_interception(struct vcpu_svm *svm)
2045 {
2046         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2047                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2048         return 1;
2049 }
2050
2051 static int emulate_on_interception(struct vcpu_svm *svm)
2052 {
2053         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2054                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2055         return 1;
2056 }
2057
2058 static int cr8_write_interception(struct vcpu_svm *svm)
2059 {
2060         struct kvm_run *kvm_run = svm->vcpu.run;
2061
2062         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2063         /* instruction emulation calls kvm_set_cr8() */
2064         emulate_instruction(&svm->vcpu, 0, 0, 0);
2065         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2066                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2067                 return 1;
2068         }
2069         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2070                 return 1;
2071         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2072         return 0;
2073 }
2074
2075 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2076 {
2077         struct vcpu_svm *svm = to_svm(vcpu);
2078
2079         switch (ecx) {
2080         case MSR_IA32_TSC: {
2081                 u64 tsc_offset;
2082
2083                 if (is_nested(svm))
2084                         tsc_offset = svm->nested.hsave->control.tsc_offset;
2085                 else
2086                         tsc_offset = svm->vmcb->control.tsc_offset;
2087
2088                 *data = tsc_offset + native_read_tsc();
2089                 break;
2090         }
2091         case MSR_K6_STAR:
2092                 *data = svm->vmcb->save.star;
2093                 break;
2094 #ifdef CONFIG_X86_64
2095         case MSR_LSTAR:
2096                 *data = svm->vmcb->save.lstar;
2097                 break;
2098         case MSR_CSTAR:
2099                 *data = svm->vmcb->save.cstar;
2100                 break;
2101         case MSR_KERNEL_GS_BASE:
2102                 *data = svm->vmcb->save.kernel_gs_base;
2103                 break;
2104         case MSR_SYSCALL_MASK:
2105                 *data = svm->vmcb->save.sfmask;
2106                 break;
2107 #endif
2108         case MSR_IA32_SYSENTER_CS:
2109                 *data = svm->vmcb->save.sysenter_cs;
2110                 break;
2111         case MSR_IA32_SYSENTER_EIP:
2112                 *data = svm->sysenter_eip;
2113                 break;
2114         case MSR_IA32_SYSENTER_ESP:
2115                 *data = svm->sysenter_esp;
2116                 break;
2117         /* Nobody will change the following 5 values in the VMCB so
2118            we can safely return them on rdmsr. They will always be 0
2119            until LBRV is implemented. */
2120         case MSR_IA32_DEBUGCTLMSR:
2121                 *data = svm->vmcb->save.dbgctl;
2122                 break;
2123         case MSR_IA32_LASTBRANCHFROMIP:
2124                 *data = svm->vmcb->save.br_from;
2125                 break;
2126         case MSR_IA32_LASTBRANCHTOIP:
2127                 *data = svm->vmcb->save.br_to;
2128                 break;
2129         case MSR_IA32_LASTINTFROMIP:
2130                 *data = svm->vmcb->save.last_excp_from;
2131                 break;
2132         case MSR_IA32_LASTINTTOIP:
2133                 *data = svm->vmcb->save.last_excp_to;
2134                 break;
2135         case MSR_VM_HSAVE_PA:
2136                 *data = svm->nested.hsave_msr;
2137                 break;
2138         case MSR_VM_CR:
2139                 *data = 0;
2140                 break;
2141         case MSR_IA32_UCODE_REV:
2142                 *data = 0x01000065;
2143                 break;
2144         default:
2145                 return kvm_get_msr_common(vcpu, ecx, data);
2146         }
2147         return 0;
2148 }
2149
2150 static int rdmsr_interception(struct vcpu_svm *svm)
2151 {
2152         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2153         u64 data;
2154
2155         if (svm_get_msr(&svm->vcpu, ecx, &data))
2156                 kvm_inject_gp(&svm->vcpu, 0);
2157         else {
2158                 trace_kvm_msr_read(ecx, data);
2159
2160                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2161                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2162                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2163                 skip_emulated_instruction(&svm->vcpu);
2164         }
2165         return 1;
2166 }
2167
2168 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2169 {
2170         struct vcpu_svm *svm = to_svm(vcpu);
2171
2172         switch (ecx) {
2173         case MSR_IA32_TSC: {
2174                 u64 tsc_offset = data - native_read_tsc();
2175                 u64 g_tsc_offset = 0;
2176
2177                 if (is_nested(svm)) {
2178                         g_tsc_offset = svm->vmcb->control.tsc_offset -
2179                                        svm->nested.hsave->control.tsc_offset;
2180                         svm->nested.hsave->control.tsc_offset = tsc_offset;
2181                 }
2182
2183                 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2184
2185                 break;
2186         }
2187         case MSR_K6_STAR:
2188                 svm->vmcb->save.star = data;
2189                 break;
2190 #ifdef CONFIG_X86_64
2191         case MSR_LSTAR:
2192                 svm->vmcb->save.lstar = data;
2193                 break;
2194         case MSR_CSTAR:
2195                 svm->vmcb->save.cstar = data;
2196                 break;
2197         case MSR_KERNEL_GS_BASE:
2198                 svm->vmcb->save.kernel_gs_base = data;
2199                 break;
2200         case MSR_SYSCALL_MASK:
2201                 svm->vmcb->save.sfmask = data;
2202                 break;
2203 #endif
2204         case MSR_IA32_SYSENTER_CS:
2205                 svm->vmcb->save.sysenter_cs = data;
2206                 break;
2207         case MSR_IA32_SYSENTER_EIP:
2208                 svm->sysenter_eip = data;
2209                 svm->vmcb->save.sysenter_eip = data;
2210                 break;
2211         case MSR_IA32_SYSENTER_ESP:
2212                 svm->sysenter_esp = data;
2213                 svm->vmcb->save.sysenter_esp = data;
2214                 break;
2215         case MSR_IA32_DEBUGCTLMSR:
2216                 if (!svm_has(SVM_FEATURE_LBRV)) {
2217                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2218                                         __func__, data);
2219                         break;
2220                 }
2221                 if (data & DEBUGCTL_RESERVED_BITS)
2222                         return 1;
2223
2224                 svm->vmcb->save.dbgctl = data;
2225                 if (data & (1ULL<<0))
2226                         svm_enable_lbrv(svm);
2227                 else
2228                         svm_disable_lbrv(svm);
2229                 break;
2230         case MSR_VM_HSAVE_PA:
2231                 svm->nested.hsave_msr = data;
2232                 break;
2233         case MSR_VM_CR:
2234         case MSR_VM_IGNNE:
2235                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2236                 break;
2237         default:
2238                 return kvm_set_msr_common(vcpu, ecx, data);
2239         }
2240         return 0;
2241 }
2242
2243 static int wrmsr_interception(struct vcpu_svm *svm)
2244 {
2245         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2246         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2247                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2248
2249         trace_kvm_msr_write(ecx, data);
2250
2251         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2252         if (svm_set_msr(&svm->vcpu, ecx, data))
2253                 kvm_inject_gp(&svm->vcpu, 0);
2254         else
2255                 skip_emulated_instruction(&svm->vcpu);
2256         return 1;
2257 }
2258
2259 static int msr_interception(struct vcpu_svm *svm)
2260 {
2261         if (svm->vmcb->control.exit_info_1)
2262                 return wrmsr_interception(svm);
2263         else
2264                 return rdmsr_interception(svm);
2265 }
2266
2267 static int interrupt_window_interception(struct vcpu_svm *svm)
2268 {
2269         struct kvm_run *kvm_run = svm->vcpu.run;
2270
2271         svm_clear_vintr(svm);
2272         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2273         /*
2274          * If the user space waits to inject interrupts, exit as soon as
2275          * possible
2276          */
2277         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2278             kvm_run->request_interrupt_window &&
2279             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2280                 ++svm->vcpu.stat.irq_window_exits;
2281                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2282                 return 0;
2283         }
2284
2285         return 1;
2286 }
2287
2288 static int pause_interception(struct vcpu_svm *svm)
2289 {
2290         kvm_vcpu_on_spin(&(svm->vcpu));
2291         return 1;
2292 }
2293
2294 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2295         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2296         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2297         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2298         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2299         /* for now: */
2300         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2301         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2302         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2303         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2304         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2305         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2306         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2307         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2308         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2309         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2310         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2311         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2312         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2313         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2314         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2315         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2316         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2317         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2318         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2319         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2320         [SVM_EXIT_INTR]                         = intr_interception,
2321         [SVM_EXIT_NMI]                          = nmi_interception,
2322         [SVM_EXIT_SMI]                          = nop_on_interception,
2323         [SVM_EXIT_INIT]                         = nop_on_interception,
2324         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2325         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
2326         [SVM_EXIT_CPUID]                        = cpuid_interception,
2327         [SVM_EXIT_IRET]                         = iret_interception,
2328         [SVM_EXIT_INVD]                         = emulate_on_interception,
2329         [SVM_EXIT_PAUSE]                        = pause_interception,
2330         [SVM_EXIT_HLT]                          = halt_interception,
2331         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2332         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2333         [SVM_EXIT_IOIO]                         = io_interception,
2334         [SVM_EXIT_MSR]                          = msr_interception,
2335         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2336         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2337         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2338         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2339         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2340         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2341         [SVM_EXIT_STGI]                         = stgi_interception,
2342         [SVM_EXIT_CLGI]                         = clgi_interception,
2343         [SVM_EXIT_SKINIT]                       = skinit_interception,
2344         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2345         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2346         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2347         [SVM_EXIT_NPF]                          = pf_interception,
2348 };
2349
2350 static int handle_exit(struct kvm_vcpu *vcpu)
2351 {
2352         struct vcpu_svm *svm = to_svm(vcpu);
2353         struct kvm_run *kvm_run = vcpu->run;
2354         u32 exit_code = svm->vmcb->control.exit_code;
2355
2356         trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2357
2358         if (unlikely(svm->nested.exit_required)) {
2359                 nested_svm_vmexit(svm);
2360                 svm->nested.exit_required = false;
2361
2362                 return 1;
2363         }
2364
2365         if (is_nested(svm)) {
2366                 int vmexit;
2367
2368                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2369                                         svm->vmcb->control.exit_info_1,
2370                                         svm->vmcb->control.exit_info_2,
2371                                         svm->vmcb->control.exit_int_info,
2372                                         svm->vmcb->control.exit_int_info_err);
2373
2374                 vmexit = nested_svm_exit_special(svm);
2375
2376                 if (vmexit == NESTED_EXIT_CONTINUE)
2377                         vmexit = nested_svm_exit_handled(svm);
2378
2379                 if (vmexit == NESTED_EXIT_DONE)
2380                         return 1;
2381         }
2382
2383         svm_complete_interrupts(svm);
2384
2385         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2386                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2387         if (npt_enabled)
2388                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2389
2390         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2391                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2392                 kvm_run->fail_entry.hardware_entry_failure_reason
2393                         = svm->vmcb->control.exit_code;
2394                 return 0;
2395         }
2396
2397         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2398             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2399             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2400                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2401                        "exit_code 0x%x\n",
2402                        __func__, svm->vmcb->control.exit_int_info,
2403                        exit_code);
2404
2405         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2406             || !svm_exit_handlers[exit_code]) {
2407                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2408                 kvm_run->hw.hardware_exit_reason = exit_code;
2409                 return 0;
2410         }
2411
2412         return svm_exit_handlers[exit_code](svm);
2413 }
2414
2415 static void reload_tss(struct kvm_vcpu *vcpu)
2416 {
2417         int cpu = raw_smp_processor_id();
2418
2419         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2420         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
2421         load_TR_desc();
2422 }
2423
2424 static void pre_svm_run(struct vcpu_svm *svm)
2425 {
2426         int cpu = raw_smp_processor_id();
2427
2428         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2429
2430         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2431         /* FIXME: handle wraparound of asid_generation */
2432         if (svm->asid_generation != sd->asid_generation)
2433                 new_asid(svm, sd);
2434 }
2435
2436 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2437 {
2438         struct vcpu_svm *svm = to_svm(vcpu);
2439
2440         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2441         vcpu->arch.hflags |= HF_NMI_MASK;
2442         svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2443         ++vcpu->stat.nmi_injections;
2444 }
2445
2446 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2447 {
2448         struct vmcb_control_area *control;
2449
2450         trace_kvm_inj_virq(irq);
2451
2452         ++svm->vcpu.stat.irq_injections;
2453         control = &svm->vmcb->control;
2454         control->int_vector = irq;
2455         control->int_ctl &= ~V_INTR_PRIO_MASK;
2456         control->int_ctl |= V_IRQ_MASK |
2457                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2458 }
2459
2460 static void svm_set_irq(struct kvm_vcpu *vcpu)
2461 {
2462         struct vcpu_svm *svm = to_svm(vcpu);
2463
2464         BUG_ON(!(gif_set(svm)));
2465
2466         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2467                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2468 }
2469
2470 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2471 {
2472         struct vcpu_svm *svm = to_svm(vcpu);
2473
2474         if (irr == -1)
2475                 return;
2476
2477         if (tpr >= irr)
2478                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2479 }
2480
2481 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2482 {
2483         struct vcpu_svm *svm = to_svm(vcpu);
2484         struct vmcb *vmcb = svm->vmcb;
2485         return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2486                 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2487 }
2488
2489 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2490 {
2491         struct vcpu_svm *svm = to_svm(vcpu);
2492
2493         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2494 }
2495
2496 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2497 {
2498         struct vcpu_svm *svm = to_svm(vcpu);
2499
2500         if (masked) {
2501                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2502                 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2503         } else {
2504                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2505                 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2506         }
2507 }
2508
2509 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2510 {
2511         struct vcpu_svm *svm = to_svm(vcpu);
2512         struct vmcb *vmcb = svm->vmcb;
2513         int ret;
2514
2515         if (!gif_set(svm) ||
2516              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2517                 return 0;
2518
2519         ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2520
2521         if (is_nested(svm))
2522                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2523
2524         return ret;
2525 }
2526
2527 static void enable_irq_window(struct kvm_vcpu *vcpu)
2528 {
2529         struct vcpu_svm *svm = to_svm(vcpu);
2530
2531         nested_svm_intr(svm);
2532
2533         /* In case GIF=0 we can't rely on the CPU to tell us when
2534          * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2535          * The next time we get that intercept, this function will be
2536          * called again though and we'll get the vintr intercept. */
2537         if (gif_set(svm)) {
2538                 svm_set_vintr(svm);
2539                 svm_inject_irq(svm, 0x0);
2540         }
2541 }
2542
2543 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2544 {
2545         struct vcpu_svm *svm = to_svm(vcpu);
2546
2547         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2548             == HF_NMI_MASK)
2549                 return; /* IRET will cause a vm exit */
2550
2551         /* Something prevents NMI from been injected. Single step over
2552            possible problem (IRET or exception injection or interrupt
2553            shadow) */
2554         svm->nmi_singlestep = true;
2555         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2556         update_db_intercept(vcpu);
2557 }
2558
2559 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2560 {
2561         return 0;
2562 }
2563
2564 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2565 {
2566         force_new_asid(vcpu);
2567 }
2568
2569 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2570 {
2571         if (npt_enabled)
2572                 vcpu->fpu_active = 1;
2573 }
2574
2575 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2576 {
2577         struct vcpu_svm *svm = to_svm(vcpu);
2578
2579         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2580                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2581                 kvm_set_cr8(vcpu, cr8);
2582         }
2583 }
2584
2585 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2586 {
2587         struct vcpu_svm *svm = to_svm(vcpu);
2588         u64 cr8;
2589
2590         cr8 = kvm_get_cr8(vcpu);
2591         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2592         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2593 }
2594
2595 static void svm_complete_interrupts(struct vcpu_svm *svm)
2596 {
2597         u8 vector;
2598         int type;
2599         u32 exitintinfo = svm->vmcb->control.exit_int_info;
2600
2601         if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2602                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2603
2604         svm->vcpu.arch.nmi_injected = false;
2605         kvm_clear_exception_queue(&svm->vcpu);
2606         kvm_clear_interrupt_queue(&svm->vcpu);
2607
2608         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2609                 return;
2610
2611         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2612         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2613
2614         switch (type) {
2615         case SVM_EXITINTINFO_TYPE_NMI:
2616                 svm->vcpu.arch.nmi_injected = true;
2617                 break;
2618         case SVM_EXITINTINFO_TYPE_EXEPT:
2619                 /* In case of software exception do not reinject an exception
2620                    vector, but re-execute and instruction instead */
2621                 if (is_nested(svm))
2622                         break;
2623                 if (kvm_exception_is_soft(vector))
2624                         break;
2625                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2626                         u32 err = svm->vmcb->control.exit_int_info_err;
2627                         kvm_queue_exception_e(&svm->vcpu, vector, err);
2628
2629                 } else
2630                         kvm_queue_exception(&svm->vcpu, vector);
2631                 break;
2632         case SVM_EXITINTINFO_TYPE_INTR:
2633                 kvm_queue_interrupt(&svm->vcpu, vector, false);
2634                 break;
2635         default:
2636                 break;
2637         }
2638 }
2639
2640 #ifdef CONFIG_X86_64
2641 #define R "r"
2642 #else
2643 #define R "e"
2644 #endif
2645
2646 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
2647 {
2648         struct vcpu_svm *svm = to_svm(vcpu);
2649         u16 fs_selector;
2650         u16 gs_selector;
2651         u16 ldt_selector;
2652
2653         /*
2654          * A vmexit emulation is required before the vcpu can be executed
2655          * again.
2656          */
2657         if (unlikely(svm->nested.exit_required))
2658                 return;
2659
2660         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2661         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2662         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2663
2664         pre_svm_run(svm);
2665
2666         sync_lapic_to_cr8(vcpu);
2667
2668         save_host_msrs(vcpu);
2669         fs_selector = kvm_read_fs();
2670         gs_selector = kvm_read_gs();
2671         ldt_selector = kvm_read_ldt();
2672         svm->vmcb->save.cr2 = vcpu->arch.cr2;
2673         /* required for live migration with NPT */
2674         if (npt_enabled)
2675                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2676
2677         clgi();
2678
2679         local_irq_enable();
2680
2681         asm volatile (
2682                 "push %%"R"bp; \n\t"
2683                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2684                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2685                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2686                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2687                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2688                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2689 #ifdef CONFIG_X86_64
2690                 "mov %c[r8](%[svm]),  %%r8  \n\t"
2691                 "mov %c[r9](%[svm]),  %%r9  \n\t"
2692                 "mov %c[r10](%[svm]), %%r10 \n\t"
2693                 "mov %c[r11](%[svm]), %%r11 \n\t"
2694                 "mov %c[r12](%[svm]), %%r12 \n\t"
2695                 "mov %c[r13](%[svm]), %%r13 \n\t"
2696                 "mov %c[r14](%[svm]), %%r14 \n\t"
2697                 "mov %c[r15](%[svm]), %%r15 \n\t"
2698 #endif
2699
2700                 /* Enter guest mode */
2701                 "push %%"R"ax \n\t"
2702                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2703                 __ex(SVM_VMLOAD) "\n\t"
2704                 __ex(SVM_VMRUN) "\n\t"
2705                 __ex(SVM_VMSAVE) "\n\t"
2706                 "pop %%"R"ax \n\t"
2707
2708                 /* Save guest registers, load host registers */
2709                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2710                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2711                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2712                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2713                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2714                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2715 #ifdef CONFIG_X86_64
2716                 "mov %%r8,  %c[r8](%[svm]) \n\t"
2717                 "mov %%r9,  %c[r9](%[svm]) \n\t"
2718                 "mov %%r10, %c[r10](%[svm]) \n\t"
2719                 "mov %%r11, %c[r11](%[svm]) \n\t"
2720                 "mov %%r12, %c[r12](%[svm]) \n\t"
2721                 "mov %%r13, %c[r13](%[svm]) \n\t"
2722                 "mov %%r14, %c[r14](%[svm]) \n\t"
2723                 "mov %%r15, %c[r15](%[svm]) \n\t"
2724 #endif
2725                 "pop %%"R"bp"
2726                 :
2727                 : [svm]"a"(svm),
2728                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2729                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2730                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2731                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2732                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2733                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2734                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2735 #ifdef CONFIG_X86_64
2736                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2737                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2738                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2739                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2740                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2741                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2742                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2743                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2744 #endif
2745                 : "cc", "memory"
2746                 , R"bx", R"cx", R"dx", R"si", R"di"
2747 #ifdef CONFIG_X86_64
2748                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2749 #endif
2750                 );
2751
2752         vcpu->arch.cr2 = svm->vmcb->save.cr2;
2753         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2754         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2755         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2756
2757         kvm_load_fs(fs_selector);
2758         kvm_load_gs(gs_selector);
2759         kvm_load_ldt(ldt_selector);
2760         load_host_msrs(vcpu);
2761
2762         reload_tss(vcpu);
2763
2764         local_irq_disable();
2765
2766         stgi();
2767
2768         sync_cr8_to_lapic(vcpu);
2769
2770         svm->next_rip = 0;
2771
2772         if (npt_enabled) {
2773                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2774                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2775         }
2776 }
2777
2778 #undef R
2779
2780 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2781 {
2782         struct vcpu_svm *svm = to_svm(vcpu);
2783
2784         if (npt_enabled) {
2785                 svm->vmcb->control.nested_cr3 = root;
2786                 force_new_asid(vcpu);
2787                 return;
2788         }
2789
2790         svm->vmcb->save.cr3 = root;
2791         force_new_asid(vcpu);
2792 }
2793
2794 static int is_disabled(void)
2795 {
2796         u64 vm_cr;
2797
2798         rdmsrl(MSR_VM_CR, vm_cr);
2799         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2800                 return 1;
2801
2802         return 0;
2803 }
2804
2805 static void
2806 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2807 {
2808         /*
2809          * Patch in the VMMCALL instruction:
2810          */
2811         hypercall[0] = 0x0f;
2812         hypercall[1] = 0x01;
2813         hypercall[2] = 0xd9;
2814 }
2815
2816 static void svm_check_processor_compat(void *rtn)
2817 {
2818         *(int *)rtn = 0;
2819 }
2820
2821 static bool svm_cpu_has_accelerated_tpr(void)
2822 {
2823         return false;
2824 }
2825
2826 static int get_npt_level(void)
2827 {
2828 #ifdef CONFIG_X86_64
2829         return PT64_ROOT_LEVEL;
2830 #else
2831         return PT32E_ROOT_LEVEL;
2832 #endif
2833 }
2834
2835 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2836 {
2837         return 0;
2838 }
2839
2840 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
2841 {
2842 }
2843
2844 static const struct trace_print_flags svm_exit_reasons_str[] = {
2845         { SVM_EXIT_READ_CR0,                    "read_cr0" },
2846         { SVM_EXIT_READ_CR3,                    "read_cr3" },
2847         { SVM_EXIT_READ_CR4,                    "read_cr4" },
2848         { SVM_EXIT_READ_CR8,                    "read_cr8" },
2849         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
2850         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
2851         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
2852         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
2853         { SVM_EXIT_READ_DR0,                    "read_dr0" },
2854         { SVM_EXIT_READ_DR1,                    "read_dr1" },
2855         { SVM_EXIT_READ_DR2,                    "read_dr2" },
2856         { SVM_EXIT_READ_DR3,                    "read_dr3" },
2857         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
2858         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
2859         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
2860         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
2861         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
2862         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
2863         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
2864         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
2865         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
2866         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
2867         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
2868         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
2869         { SVM_EXIT_INTR,                        "interrupt" },
2870         { SVM_EXIT_NMI,                         "nmi" },
2871         { SVM_EXIT_SMI,                         "smi" },
2872         { SVM_EXIT_INIT,                        "init" },
2873         { SVM_EXIT_VINTR,                       "vintr" },
2874         { SVM_EXIT_CPUID,                       "cpuid" },
2875         { SVM_EXIT_INVD,                        "invd" },
2876         { SVM_EXIT_HLT,                         "hlt" },
2877         { SVM_EXIT_INVLPG,                      "invlpg" },
2878         { SVM_EXIT_INVLPGA,                     "invlpga" },
2879         { SVM_EXIT_IOIO,                        "io" },
2880         { SVM_EXIT_MSR,                         "msr" },
2881         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
2882         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
2883         { SVM_EXIT_VMRUN,                       "vmrun" },
2884         { SVM_EXIT_VMMCALL,                     "hypercall" },
2885         { SVM_EXIT_VMLOAD,                      "vmload" },
2886         { SVM_EXIT_VMSAVE,                      "vmsave" },
2887         { SVM_EXIT_STGI,                        "stgi" },
2888         { SVM_EXIT_CLGI,                        "clgi" },
2889         { SVM_EXIT_SKINIT,                      "skinit" },
2890         { SVM_EXIT_WBINVD,                      "wbinvd" },
2891         { SVM_EXIT_MONITOR,                     "monitor" },
2892         { SVM_EXIT_MWAIT,                       "mwait" },
2893         { SVM_EXIT_NPF,                         "npf" },
2894         { -1, NULL }
2895 };
2896
2897 static int svm_get_lpage_level(void)
2898 {
2899         return PT_PDPE_LEVEL;
2900 }
2901
2902 static bool svm_rdtscp_supported(void)
2903 {
2904         return false;
2905 }
2906
2907 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
2908 {
2909         struct vcpu_svm *svm = to_svm(vcpu);
2910
2911         if (npt_enabled) {
2912                 /* hack: npt requires active fpu at this time */
2913                 vcpu->fpu_active = 1;
2914                 return;
2915         }
2916
2917         svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
2918         svm->vmcb->save.cr0 |= X86_CR0_TS;
2919 }
2920
2921 static struct kvm_x86_ops svm_x86_ops = {
2922         .cpu_has_kvm_support = has_svm,
2923         .disabled_by_bios = is_disabled,
2924         .hardware_setup = svm_hardware_setup,
2925         .hardware_unsetup = svm_hardware_unsetup,
2926         .check_processor_compatibility = svm_check_processor_compat,
2927         .hardware_enable = svm_hardware_enable,
2928         .hardware_disable = svm_hardware_disable,
2929         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2930
2931         .vcpu_create = svm_create_vcpu,
2932         .vcpu_free = svm_free_vcpu,
2933         .vcpu_reset = svm_vcpu_reset,
2934
2935         .prepare_guest_switch = svm_prepare_guest_switch,
2936         .vcpu_load = svm_vcpu_load,
2937         .vcpu_put = svm_vcpu_put,
2938
2939         .set_guest_debug = svm_guest_debug,
2940         .get_msr = svm_get_msr,
2941         .set_msr = svm_set_msr,
2942         .get_segment_base = svm_get_segment_base,
2943         .get_segment = svm_get_segment,
2944         .set_segment = svm_set_segment,
2945         .get_cpl = svm_get_cpl,
2946         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2947         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
2948         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2949         .set_cr0 = svm_set_cr0,
2950         .set_cr3 = svm_set_cr3,
2951         .set_cr4 = svm_set_cr4,
2952         .set_efer = svm_set_efer,
2953         .get_idt = svm_get_idt,
2954         .set_idt = svm_set_idt,
2955         .get_gdt = svm_get_gdt,
2956         .set_gdt = svm_set_gdt,
2957         .get_dr = svm_get_dr,
2958         .set_dr = svm_set_dr,
2959         .cache_reg = svm_cache_reg,
2960         .get_rflags = svm_get_rflags,
2961         .set_rflags = svm_set_rflags,
2962         .fpu_deactivate = svm_fpu_deactivate,
2963
2964         .tlb_flush = svm_flush_tlb,
2965
2966         .run = svm_vcpu_run,
2967         .handle_exit = handle_exit,
2968         .skip_emulated_instruction = skip_emulated_instruction,
2969         .set_interrupt_shadow = svm_set_interrupt_shadow,
2970         .get_interrupt_shadow = svm_get_interrupt_shadow,
2971         .patch_hypercall = svm_patch_hypercall,
2972         .set_irq = svm_set_irq,
2973         .set_nmi = svm_inject_nmi,
2974         .queue_exception = svm_queue_exception,
2975         .interrupt_allowed = svm_interrupt_allowed,
2976         .nmi_allowed = svm_nmi_allowed,
2977         .get_nmi_mask = svm_get_nmi_mask,
2978         .set_nmi_mask = svm_set_nmi_mask,
2979         .enable_nmi_window = enable_nmi_window,
2980         .enable_irq_window = enable_irq_window,
2981         .update_cr8_intercept = update_cr8_intercept,
2982
2983         .set_tss_addr = svm_set_tss_addr,
2984         .get_tdp_level = get_npt_level,
2985         .get_mt_mask = svm_get_mt_mask,
2986
2987         .exit_reasons_str = svm_exit_reasons_str,
2988         .get_lpage_level = svm_get_lpage_level,
2989
2990         .cpuid_update = svm_cpuid_update,
2991
2992         .rdtscp_supported = svm_rdtscp_supported,
2993 };
2994
2995 static int __init svm_init(void)
2996 {
2997         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2998                               THIS_MODULE);
2999 }
3000
3001 static void __exit svm_exit(void)
3002 {
3003         kvm_exit();
3004 }
3005
3006 module_init(svm_init)
3007 module_exit(svm_exit)