arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/vmalloc.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27
  28 #include <asm/desc.h>
  29
  30 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  31
  32 MODULE_AUTHOR("Qumranet");
  33 MODULE_LICENSE("GPL");
  34
  35 #define IOPM_ALLOC_ORDER 2
  36 #define MSRPM_ALLOC_ORDER 1
  37
  38 #define DB_VECTOR 1
  39 #define UD_VECTOR 6
  40 #define GP_VECTOR 13
  41
  42 #define DR7_GD_MASK (1 << 13)
  43 #define DR6_BD_MASK (1 << 13)
  44
  45 #define SEG_TYPE_LDT 2
  46 #define SEG_TYPE_BUSY_TSS16 3
  47
  48 #define SVM_FEATURE_NPT  (1 << 0)
  49 #define SVM_FEATURE_LBRV (1 << 1)
  50 #define SVM_DEATURE_SVML (1 << 2)
  51
  52 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  53
  54 /* enable NPT for AMD64 and X86 with PAE */
  55 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
  56 static bool npt_enabled = true;
  57 #else
  58 static bool npt_enabled = false;
  59 #endif
  60 static int npt = 1;
  61
  62 module_param(npt, int, S_IRUGO);
  63
  64 static void kvm_reput_irq(struct vcpu_svm *svm);
  65
  66 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  67 {
  68         return container_of(vcpu, struct vcpu_svm, vcpu);
  69 }
  70
  71 static unsigned long iopm_base;
  72
  73 struct kvm_ldttss_desc {
  74         u16 limit0;
  75         u16 base0;
  76         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  77         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  78         u32 base3;
  79         u32 zero1;
  80 } __attribute__((packed));
  81
  82 struct svm_cpu_data {
  83         int cpu;
  84
  85         u64 asid_generation;
  86         u32 max_asid;
  87         u32 next_asid;
  88         struct kvm_ldttss_desc *tss_desc;
  89
  90         struct page *save_area;
  91 };
  92
  93 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
  94 static uint32_t svm_features;
  95
  96 struct svm_init_data {
  97         int cpu;
  98         int r;
  99 };
 100
 101 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 102
 103 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 104 #define MSRS_RANGE_SIZE 2048
 105 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 106
 107 #define MAX_INST_SIZE 15
 108
 109 static inline u32 svm_has(u32 feat)
 110 {
 111         return svm_features & feat;
 112 }
 113
 114 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
 115 {
 116         int word_index = __ffs(vcpu->arch.irq_summary);
 117         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
 118         int irq = word_index * BITS_PER_LONG + bit_index;
 119
 120         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
 121         if (!vcpu->arch.irq_pending[word_index])
 122                 clear_bit(word_index, &vcpu->arch.irq_summary);
 123         return irq;
 124 }
 125
 126 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
 127 {
 128         set_bit(irq, vcpu->arch.irq_pending);
 129         set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
 130 }
 131
 132 static inline void clgi(void)
 133 {
 134         asm volatile (__ex(SVM_CLGI));
 135 }
 136
 137 static inline void stgi(void)
 138 {
 139         asm volatile (__ex(SVM_STGI));
 140 }
 141
 142 static inline void invlpga(unsigned long addr, u32 asid)
 143 {
 144         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 145 }
 146
 147 static inline unsigned long kvm_read_cr2(void)
 148 {
 149         unsigned long cr2;
 150
 151         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 152         return cr2;
 153 }
 154
 155 static inline void kvm_write_cr2(unsigned long val)
 156 {
 157         asm volatile ("mov %0, %%cr2" :: "r" (val));
 158 }
 159
 160 static inline unsigned long read_dr6(void)
 161 {
 162         unsigned long dr6;
 163
 164         asm volatile ("mov %%dr6, %0" : "=r" (dr6));
 165         return dr6;
 166 }
 167
 168 static inline void write_dr6(unsigned long val)
 169 {
 170         asm volatile ("mov %0, %%dr6" :: "r" (val));
 171 }
 172
 173 static inline unsigned long read_dr7(void)
 174 {
 175         unsigned long dr7;
 176
 177         asm volatile ("mov %%dr7, %0" : "=r" (dr7));
 178         return dr7;
 179 }
 180
 181 static inline void write_dr7(unsigned long val)
 182 {
 183         asm volatile ("mov %0, %%dr7" :: "r" (val));
 184 }
 185
 186 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 187 {
 188         to_svm(vcpu)->asid_generation--;
 189 }
 190
 191 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 192 {
 193         force_new_asid(vcpu);
 194 }
 195
 196 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 197 {
 198         if (!npt_enabled && !(efer & EFER_LMA))
 199                 efer &= ~EFER_LME;
 200
 201         to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
 202         vcpu->arch.shadow_efer = efer;
 203 }
 204
 205 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 206                                 bool has_error_code, u32 error_code)
 207 {
 208         struct vcpu_svm *svm = to_svm(vcpu);
 209
 210         svm->vmcb->control.event_inj = nr
 211                 | SVM_EVTINJ_VALID
 212                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 213                 | SVM_EVTINJ_TYPE_EXEPT;
 214         svm->vmcb->control.event_inj_err = error_code;
 215 }
 216
 217 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
 218 {
 219         struct vcpu_svm *svm = to_svm(vcpu);
 220
 221         return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
 222 }
 223
 224 static int is_external_interrupt(u32 info)
 225 {
 226         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 227         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 228 }
 229
 230 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 231 {
 232         struct vcpu_svm *svm = to_svm(vcpu);
 233
 234         if (!svm->next_rip) {
 235                 printk(KERN_DEBUG "%s: NOP\n", __func__);
 236                 return;
 237         }
 238         if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE)
 239                 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
 240                        __func__,
 241                        svm->vmcb->save.rip,
 242                        svm->next_rip);
 243
 244         vcpu->arch.rip = svm->vmcb->save.rip = svm->next_rip;
 245         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 246
 247         vcpu->arch.interrupt_window_open = 1;
 248 }
 249
 250 static int has_svm(void)
 251 {
 252         uint32_t eax, ebx, ecx, edx;
 253
 254         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 255                 printk(KERN_INFO "has_svm: not amd\n");
 256                 return 0;
 257         }
 258
 259         cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
 260         if (eax < SVM_CPUID_FUNC) {
 261                 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
 262                 return 0;
 263         }
 264
 265         cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
 266         if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
 267                 printk(KERN_DEBUG "has_svm: svm not available\n");
 268                 return 0;
 269         }
 270         return 1;
 271 }
 272
 273 static void svm_hardware_disable(void *garbage)
 274 {
 275         uint64_t efer;
 276
 277         wrmsrl(MSR_VM_HSAVE_PA, 0);
 278         rdmsrl(MSR_EFER, efer);
 279         wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
 280 }
 281
 282 static void svm_hardware_enable(void *garbage)
 283 {
 284
 285         struct svm_cpu_data *svm_data;
 286         uint64_t efer;
 287         struct desc_ptr gdt_descr;
 288         struct desc_struct *gdt;
 289         int me = raw_smp_processor_id();
 290
 291         if (!has_svm()) {
 292                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 293                 return;
 294         }
 295         svm_data = per_cpu(svm_data, me);
 296
 297         if (!svm_data) {
 298                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 299                        me);
 300                 return;
 301         }
 302
 303         svm_data->asid_generation = 1;
 304         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 305         svm_data->next_asid = svm_data->max_asid + 1;
 306
 307         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 308         gdt = (struct desc_struct *)gdt_descr.address;
 309         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 310
 311         rdmsrl(MSR_EFER, efer);
 312         wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
 313
 314         wrmsrl(MSR_VM_HSAVE_PA,
 315                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 316 }
 317
 318 static void svm_cpu_uninit(int cpu)
 319 {
 320         struct svm_cpu_data *svm_data
 321                 = per_cpu(svm_data, raw_smp_processor_id());
 322
 323         if (!svm_data)
 324                 return;
 325
 326         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 327         __free_page(svm_data->save_area);
 328         kfree(svm_data);
 329 }
 330
 331 static int svm_cpu_init(int cpu)
 332 {
 333         struct svm_cpu_data *svm_data;
 334         int r;
 335
 336         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 337         if (!svm_data)
 338                 return -ENOMEM;
 339         svm_data->cpu = cpu;
 340         svm_data->save_area = alloc_page(GFP_KERNEL);
 341         r = -ENOMEM;
 342         if (!svm_data->save_area)
 343                 goto err_1;
 344
 345         per_cpu(svm_data, cpu) = svm_data;
 346
 347         return 0;
 348
 349 err_1:
 350         kfree(svm_data);
 351         return r;
 352
 353 }
 354
 355 static void set_msr_interception(u32 *msrpm, unsigned msr,
 356                                  int read, int write)
 357 {
 358         int i;
 359
 360         for (i = 0; i < NUM_MSR_MAPS; i++) {
 361                 if (msr >= msrpm_ranges[i] &&
 362                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 363                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 364                                           msrpm_ranges[i]) * 2;
 365
 366                         u32 *base = msrpm + (msr_offset / 32);
 367                         u32 msr_shift = msr_offset % 32;
 368                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 369                         *base = (*base & ~(0x3 << msr_shift)) |
 370                                 (mask << msr_shift);
 371                         return;
 372                 }
 373         }
 374         BUG();
 375 }
 376
 377 static void svm_vcpu_init_msrpm(u32 *msrpm)
 378 {
 379         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 380
 381 #ifdef CONFIG_X86_64
 382         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 383         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 384         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 385         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 386         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 387         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 388 #endif
 389         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 390         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 391         set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
 392         set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
 393 }
 394
 395 static void svm_enable_lbrv(struct vcpu_svm *svm)
 396 {
 397         u32 *msrpm = svm->msrpm;
 398
 399         svm->vmcb->control.lbr_ctl = 1;
 400         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 401         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 402         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 403         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 404 }
 405
 406 static void svm_disable_lbrv(struct vcpu_svm *svm)
 407 {
 408         u32 *msrpm = svm->msrpm;
 409
 410         svm->vmcb->control.lbr_ctl = 0;
 411         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 412         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 413         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 414         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 415 }
 416
 417 static __init int svm_hardware_setup(void)
 418 {
 419         int cpu;
 420         struct page *iopm_pages;
 421         void *iopm_va;
 422         int r;
 423
 424         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 425
 426         if (!iopm_pages)
 427                 return -ENOMEM;
 428
 429         iopm_va = page_address(iopm_pages);
 430         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 431         clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
 432         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 433
 434         if (boot_cpu_has(X86_FEATURE_NX))
 435                 kvm_enable_efer_bits(EFER_NX);
 436
 437         for_each_online_cpu(cpu) {
 438                 r = svm_cpu_init(cpu);
 439                 if (r)
 440                         goto err;
 441         }
 442
 443         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 444
 445         if (!svm_has(SVM_FEATURE_NPT))
 446                 npt_enabled = false;
 447
 448         if (npt_enabled && !npt) {
 449                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 450                 npt_enabled = false;
 451         }
 452
 453         if (npt_enabled) {
 454                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 455                 kvm_enable_tdp();
 456         }
 457
 458         return 0;
 459
 460 err:
 461         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 462         iopm_base = 0;
 463         return r;
 464 }
 465
 466 static __exit void svm_hardware_unsetup(void)
 467 {
 468         int cpu;
 469
 470         for_each_online_cpu(cpu)
 471                 svm_cpu_uninit(cpu);
 472
 473         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 474         iopm_base = 0;
 475 }
 476
 477 static void init_seg(struct vmcb_seg *seg)
 478 {
 479         seg->selector = 0;
 480         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 481                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 482         seg->limit = 0xffff;
 483         seg->base = 0;
 484 }
 485
 486 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 487 {
 488         seg->selector = 0;
 489         seg->attrib = SVM_SELECTOR_P_MASK | type;
 490         seg->limit = 0xffff;
 491         seg->base = 0;
 492 }
 493
 494 static void init_vmcb(struct vcpu_svm *svm)
 495 {
 496         struct vmcb_control_area *control = &svm->vmcb->control;
 497         struct vmcb_save_area *save = &svm->vmcb->save;
 498
 499         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 500                                         INTERCEPT_CR3_MASK |
 501                                         INTERCEPT_CR4_MASK;
 502
 503         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 504                                         INTERCEPT_CR3_MASK |
 505                                         INTERCEPT_CR4_MASK |
 506                                         INTERCEPT_CR8_MASK;
 507
 508         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 509                                         INTERCEPT_DR1_MASK |
 510                                         INTERCEPT_DR2_MASK |
 511                                         INTERCEPT_DR3_MASK;
 512
 513         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 514                                         INTERCEPT_DR1_MASK |
 515                                         INTERCEPT_DR2_MASK |
 516                                         INTERCEPT_DR3_MASK |
 517                                         INTERCEPT_DR5_MASK |
 518                                         INTERCEPT_DR7_MASK;
 519
 520         control->intercept_exceptions = (1 << PF_VECTOR) |
 521                                         (1 << UD_VECTOR) |
 522                                         (1 << MC_VECTOR);
 523
 524
 525         control->intercept =    (1ULL << INTERCEPT_INTR) |
 526                                 (1ULL << INTERCEPT_NMI) |
 527                                 (1ULL << INTERCEPT_SMI) |
 528                                 (1ULL << INTERCEPT_CPUID) |
 529                                 (1ULL << INTERCEPT_INVD) |
 530                                 (1ULL << INTERCEPT_HLT) |
 531                                 (1ULL << INTERCEPT_INVLPGA) |
 532                                 (1ULL << INTERCEPT_IOIO_PROT) |
 533                                 (1ULL << INTERCEPT_MSR_PROT) |
 534                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 535                                 (1ULL << INTERCEPT_SHUTDOWN) |
 536                                 (1ULL << INTERCEPT_VMRUN) |
 537                                 (1ULL << INTERCEPT_VMMCALL) |
 538                                 (1ULL << INTERCEPT_VMLOAD) |
 539                                 (1ULL << INTERCEPT_VMSAVE) |
 540                                 (1ULL << INTERCEPT_STGI) |
 541                                 (1ULL << INTERCEPT_CLGI) |
 542                                 (1ULL << INTERCEPT_SKINIT) |
 543                                 (1ULL << INTERCEPT_WBINVD) |
 544                                 (1ULL << INTERCEPT_MONITOR) |
 545                                 (1ULL << INTERCEPT_MWAIT);
 546
 547         control->iopm_base_pa = iopm_base;
 548         control->msrpm_base_pa = __pa(svm->msrpm);
 549         control->tsc_offset = 0;
 550         control->int_ctl = V_INTR_MASKING_MASK;
 551
 552         init_seg(&save->es);
 553         init_seg(&save->ss);
 554         init_seg(&save->ds);
 555         init_seg(&save->fs);
 556         init_seg(&save->gs);
 557
 558         save->cs.selector = 0xf000;
 559         /* Executable/Readable Code Segment */
 560         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 561                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 562         save->cs.limit = 0xffff;
 563         /*
 564          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 565          * be consistent with it.
 566          *
 567          * Replace when we have real mode working for vmx.
 568          */
 569         save->cs.base = 0xf0000;
 570
 571         save->gdtr.limit = 0xffff;
 572         save->idtr.limit = 0xffff;
 573
 574         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 575         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 576
 577         save->efer = MSR_EFER_SVME_MASK;
 578         save->dr6 = 0xffff0ff0;
 579         save->dr7 = 0x400;
 580         save->rflags = 2;
 581         save->rip = 0x0000fff0;
 582
 583         /*
 584          * cr0 val on cpu init should be 0x60000010, we enable cpu
 585          * cache by default. the orderly way is to enable cache in bios.
 586          */
 587         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 588         save->cr4 = X86_CR4_PAE;
 589         /* rdx = ?? */
 590
 591         if (npt_enabled) {
 592                 /* Setup VMCB for Nested Paging */
 593                 control->nested_ctl = 1;
 594                 control->intercept &= ~(1ULL << INTERCEPT_TASK_SWITCH);
 595                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 596                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 597                                                 INTERCEPT_CR3_MASK);
 598                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 599                                                  INTERCEPT_CR3_MASK);
 600                 save->g_pat = 0x0007040600070406ULL;
 601                 /* enable caching because the QEMU Bios doesn't enable it */
 602                 save->cr0 = X86_CR0_ET;
 603                 save->cr3 = 0;
 604                 save->cr4 = 0;
 605         }
 606         force_new_asid(&svm->vcpu);
 607 }
 608
 609 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 610 {
 611         struct vcpu_svm *svm = to_svm(vcpu);
 612
 613         init_vmcb(svm);
 614
 615         if (vcpu->vcpu_id != 0) {
 616                 svm->vmcb->save.rip = 0;
 617                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 618                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 619         }
 620
 621         return 0;
 622 }
 623
 624 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 625 {
 626         struct vcpu_svm *svm;
 627         struct page *page;
 628         struct page *msrpm_pages;
 629         int err;
 630
 631         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 632         if (!svm) {
 633                 err = -ENOMEM;
 634                 goto out;
 635         }
 636
 637         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 638         if (err)
 639                 goto free_svm;
 640
 641         page = alloc_page(GFP_KERNEL);
 642         if (!page) {
 643                 err = -ENOMEM;
 644                 goto uninit;
 645         }
 646
 647         err = -ENOMEM;
 648         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 649         if (!msrpm_pages)
 650                 goto uninit;
 651         svm->msrpm = page_address(msrpm_pages);
 652         svm_vcpu_init_msrpm(svm->msrpm);
 653
 654         svm->vmcb = page_address(page);
 655         clear_page(svm->vmcb);
 656         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 657         svm->asid_generation = 0;
 658         memset(svm->db_regs, 0, sizeof(svm->db_regs));
 659         init_vmcb(svm);
 660
 661         fx_init(&svm->vcpu);
 662         svm->vcpu.fpu_active = 1;
 663         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 664         if (svm->vcpu.vcpu_id == 0)
 665                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 666
 667         return &svm->vcpu;
 668
 669 uninit:
 670         kvm_vcpu_uninit(&svm->vcpu);
 671 free_svm:
 672         kmem_cache_free(kvm_vcpu_cache, svm);
 673 out:
 674         return ERR_PTR(err);
 675 }
 676
 677 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 678 {
 679         struct vcpu_svm *svm = to_svm(vcpu);
 680
 681         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 682         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 683         kvm_vcpu_uninit(vcpu);
 684         kmem_cache_free(kvm_vcpu_cache, svm);
 685 }
 686
 687 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 688 {
 689         struct vcpu_svm *svm = to_svm(vcpu);
 690         int i;
 691
 692         if (unlikely(cpu != vcpu->cpu)) {
 693                 u64 tsc_this, delta;
 694
 695                 /*
 696                  * Make sure that the guest sees a monotonically
 697                  * increasing TSC.
 698                  */
 699                 rdtscll(tsc_this);
 700                 delta = vcpu->arch.host_tsc - tsc_this;
 701                 svm->vmcb->control.tsc_offset += delta;
 702                 vcpu->cpu = cpu;
 703                 kvm_migrate_timers(vcpu);
 704         }
 705
 706         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 707                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 708 }
 709
 710 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 711 {
 712         struct vcpu_svm *svm = to_svm(vcpu);
 713         int i;
 714
 715         ++vcpu->stat.host_state_reload;
 716         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 717                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 718
 719         rdtscll(vcpu->arch.host_tsc);
 720 }
 721
 722 static void svm_cache_regs(struct kvm_vcpu *vcpu)
 723 {
 724         struct vcpu_svm *svm = to_svm(vcpu);
 725
 726         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
 727         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
 728         vcpu->arch.rip = svm->vmcb->save.rip;
 729 }
 730
 731 static void svm_decache_regs(struct kvm_vcpu *vcpu)
 732 {
 733         struct vcpu_svm *svm = to_svm(vcpu);
 734         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
 735         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
 736         svm->vmcb->save.rip = vcpu->arch.rip;
 737 }
 738
 739 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 740 {
 741         return to_svm(vcpu)->vmcb->save.rflags;
 742 }
 743
 744 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 745 {
 746         to_svm(vcpu)->vmcb->save.rflags = rflags;
 747 }
 748
 749 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 750 {
 751         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 752
 753         switch (seg) {
 754         case VCPU_SREG_CS: return &save->cs;
 755         case VCPU_SREG_DS: return &save->ds;
 756         case VCPU_SREG_ES: return &save->es;
 757         case VCPU_SREG_FS: return &save->fs;
 758         case VCPU_SREG_GS: return &save->gs;
 759         case VCPU_SREG_SS: return &save->ss;
 760         case VCPU_SREG_TR: return &save->tr;
 761         case VCPU_SREG_LDTR: return &save->ldtr;
 762         }
 763         BUG();
 764         return NULL;
 765 }
 766
 767 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 768 {
 769         struct vmcb_seg *s = svm_seg(vcpu, seg);
 770
 771         return s->base;
 772 }
 773
 774 static void svm_get_segment(struct kvm_vcpu *vcpu,
 775                             struct kvm_segment *var, int seg)
 776 {
 777         struct vmcb_seg *s = svm_seg(vcpu, seg);
 778
 779         var->base = s->base;
 780         var->limit = s->limit;
 781         var->selector = s->selector;
 782         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 783         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 784         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 785         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 786         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 787         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 788         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 789         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 790         var->unusable = !var->present;
 791 }
 792
 793 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 794 {
 795         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 796
 797         return save->cpl;
 798 }
 799
 800 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 801 {
 802         struct vcpu_svm *svm = to_svm(vcpu);
 803
 804         dt->limit = svm->vmcb->save.idtr.limit;
 805         dt->base = svm->vmcb->save.idtr.base;
 806 }
 807
 808 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 809 {
 810         struct vcpu_svm *svm = to_svm(vcpu);
 811
 812         svm->vmcb->save.idtr.limit = dt->limit;
 813         svm->vmcb->save.idtr.base = dt->base ;
 814 }
 815
 816 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 817 {
 818         struct vcpu_svm *svm = to_svm(vcpu);
 819
 820         dt->limit = svm->vmcb->save.gdtr.limit;
 821         dt->base = svm->vmcb->save.gdtr.base;
 822 }
 823
 824 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 825 {
 826         struct vcpu_svm *svm = to_svm(vcpu);
 827
 828         svm->vmcb->save.gdtr.limit = dt->limit;
 829         svm->vmcb->save.gdtr.base = dt->base ;
 830 }
 831
 832 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 833 {
 834 }
 835
 836 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 837 {
 838         struct vcpu_svm *svm = to_svm(vcpu);
 839
 840 #ifdef CONFIG_X86_64
 841         if (vcpu->arch.shadow_efer & EFER_LME) {
 842                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 843                         vcpu->arch.shadow_efer |= EFER_LMA;
 844                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 845                 }
 846
 847                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 848                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 849                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 850                 }
 851         }
 852 #endif
 853         if (npt_enabled)
 854                 goto set;
 855
 856         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 857                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 858                 vcpu->fpu_active = 1;
 859         }
 860
 861         vcpu->arch.cr0 = cr0;
 862         cr0 |= X86_CR0_PG | X86_CR0_WP;
 863         if (!vcpu->fpu_active) {
 864                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 865                 cr0 |= X86_CR0_TS;
 866         }
 867 set:
 868         /*
 869          * re-enable caching here because the QEMU bios
 870          * does not do it - this results in some delay at
 871          * reboot
 872          */
 873         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 874         svm->vmcb->save.cr0 = cr0;
 875 }
 876
 877 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 878 {
 879         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
 880
 881         vcpu->arch.cr4 = cr4;
 882         if (!npt_enabled)
 883                 cr4 |= X86_CR4_PAE;
 884         cr4 |= host_cr4_mce;
 885         to_svm(vcpu)->vmcb->save.cr4 = cr4;
 886 }
 887
 888 static void svm_set_segment(struct kvm_vcpu *vcpu,
 889                             struct kvm_segment *var, int seg)
 890 {
 891         struct vcpu_svm *svm = to_svm(vcpu);
 892         struct vmcb_seg *s = svm_seg(vcpu, seg);
 893
 894         s->base = var->base;
 895         s->limit = var->limit;
 896         s->selector = var->selector;
 897         if (var->unusable)
 898                 s->attrib = 0;
 899         else {
 900                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 901                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 902                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 903                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 904                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 905                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 906                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 907                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 908         }
 909         if (seg == VCPU_SREG_CS)
 910                 svm->vmcb->save.cpl
 911                         = (svm->vmcb->save.cs.attrib
 912                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 913
 914 }
 915
 916 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 917 {
 918         return -EOPNOTSUPP;
 919 }
 920
 921 static int svm_get_irq(struct kvm_vcpu *vcpu)
 922 {
 923         struct vcpu_svm *svm = to_svm(vcpu);
 924         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 925
 926         if (is_external_interrupt(exit_int_info))
 927                 return exit_int_info & SVM_EVTINJ_VEC_MASK;
 928         return -1;
 929 }
 930
 931 static void load_host_msrs(struct kvm_vcpu *vcpu)
 932 {
 933 #ifdef CONFIG_X86_64
 934         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 935 #endif
 936 }
 937
 938 static void save_host_msrs(struct kvm_vcpu *vcpu)
 939 {
 940 #ifdef CONFIG_X86_64
 941         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 942 #endif
 943 }
 944
 945 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
 946 {
 947         if (svm_data->next_asid > svm_data->max_asid) {
 948                 ++svm_data->asid_generation;
 949                 svm_data->next_asid = 1;
 950                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
 951         }
 952
 953         svm->vcpu.cpu = svm_data->cpu;
 954         svm->asid_generation = svm_data->asid_generation;
 955         svm->vmcb->control.asid = svm_data->next_asid++;
 956 }
 957
 958 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
 959 {
 960         unsigned long val = to_svm(vcpu)->db_regs[dr];
 961         KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
 962         return val;
 963 }
 964
 965 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
 966                        int *exception)
 967 {
 968         struct vcpu_svm *svm = to_svm(vcpu);
 969
 970         *exception = 0;
 971
 972         if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
 973                 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
 974                 svm->vmcb->save.dr6 |= DR6_BD_MASK;
 975                 *exception = DB_VECTOR;
 976                 return;
 977         }
 978
 979         switch (dr) {
 980         case 0 ... 3:
 981                 svm->db_regs[dr] = value;
 982                 return;
 983         case 4 ... 5:
 984                 if (vcpu->arch.cr4 & X86_CR4_DE) {
 985                         *exception = UD_VECTOR;
 986                         return;
 987                 }
 988         case 7: {
 989                 if (value & ~((1ULL << 32) - 1)) {
 990                         *exception = GP_VECTOR;
 991                         return;
 992                 }
 993                 svm->vmcb->save.dr7 = value;
 994                 return;
 995         }
 996         default:
 997                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
 998                        __func__, dr);
 999                 *exception = UD_VECTOR;
1000                 return;
1001         }
1002 }
1003
1004 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1005 {
1006         u32 exit_int_info = svm->vmcb->control.exit_int_info;
1007         struct kvm *kvm = svm->vcpu.kvm;
1008         u64 fault_address;
1009         u32 error_code;
1010
1011         if (!irqchip_in_kernel(kvm) &&
1012                 is_external_interrupt(exit_int_info))
1013                 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
1014
1015         fault_address  = svm->vmcb->control.exit_info_2;
1016         error_code = svm->vmcb->control.exit_info_1;
1017
1018         if (!npt_enabled)
1019                 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1020                             (u32)fault_address, (u32)(fault_address >> 32),
1021                             handler);
1022         else
1023                 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1024                             (u32)fault_address, (u32)(fault_address >> 32),
1025                             handler);
1026
1027         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1028 }
1029
1030 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1031 {
1032         int er;
1033
1034         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1035         if (er != EMULATE_DONE)
1036                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1037         return 1;
1038 }
1039
1040 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1041 {
1042         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1043         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1044                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1045         svm->vcpu.fpu_active = 1;
1046
1047         return 1;
1048 }
1049
1050 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1051 {
1052         /*
1053          * On an #MC intercept the MCE handler is not called automatically in
1054          * the host. So do it by hand here.
1055          */
1056         asm volatile (
1057                 "int $0x12\n");
1058         /* not sure if we ever come back to this point */
1059
1060         return 1;
1061 }
1062
1063 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1064 {
1065         /*
1066          * VMCB is undefined after a SHUTDOWN intercept
1067          * so reinitialize it.
1068          */
1069         clear_page(svm->vmcb);
1070         init_vmcb(svm);
1071
1072         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1073         return 0;
1074 }
1075
1076 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1077 {
1078         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1079         int size, down, in, string, rep;
1080         unsigned port;
1081
1082         ++svm->vcpu.stat.io_exits;
1083
1084         svm->next_rip = svm->vmcb->control.exit_info_2;
1085
1086         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1087
1088         if (string) {
1089                 if (emulate_instruction(&svm->vcpu,
1090                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1091                         return 0;
1092                 return 1;
1093         }
1094
1095         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1096         port = io_info >> 16;
1097         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1098         rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1099         down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1100
1101         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1102 }
1103
1104 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1105 {
1106         KVMTRACE_0D(NMI, &svm->vcpu, handler);
1107         return 1;
1108 }
1109
1110 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1111 {
1112         ++svm->vcpu.stat.irq_exits;
1113         KVMTRACE_0D(INTR, &svm->vcpu, handler);
1114         return 1;
1115 }
1116
1117 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1118 {
1119         return 1;
1120 }
1121
1122 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1123 {
1124         svm->next_rip = svm->vmcb->save.rip + 1;
1125         skip_emulated_instruction(&svm->vcpu);
1126         return kvm_emulate_halt(&svm->vcpu);
1127 }
1128
1129 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1130 {
1131         svm->next_rip = svm->vmcb->save.rip + 3;
1132         skip_emulated_instruction(&svm->vcpu);
1133         kvm_emulate_hypercall(&svm->vcpu);
1134         return 1;
1135 }
1136
1137 static int invalid_op_interception(struct vcpu_svm *svm,
1138                                    struct kvm_run *kvm_run)
1139 {
1140         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1141         return 1;
1142 }
1143
1144 static int task_switch_interception(struct vcpu_svm *svm,
1145                                     struct kvm_run *kvm_run)
1146 {
1147         u16 tss_selector;
1148
1149         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1150         if (svm->vmcb->control.exit_info_2 &
1151             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1152                 return kvm_task_switch(&svm->vcpu, tss_selector,
1153                                        TASK_SWITCH_IRET);
1154         if (svm->vmcb->control.exit_info_2 &
1155             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1156                 return kvm_task_switch(&svm->vcpu, tss_selector,
1157                                        TASK_SWITCH_JMP);
1158         return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL);
1159 }
1160
1161 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1162 {
1163         svm->next_rip = svm->vmcb->save.rip + 2;
1164         kvm_emulate_cpuid(&svm->vcpu);
1165         return 1;
1166 }
1167
1168 static int emulate_on_interception(struct vcpu_svm *svm,
1169                                    struct kvm_run *kvm_run)
1170 {
1171         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1172                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1173         return 1;
1174 }
1175
1176 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1177 {
1178         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1179         if (irqchip_in_kernel(svm->vcpu.kvm))
1180                 return 1;
1181         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1182         return 0;
1183 }
1184
1185 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1186 {
1187         struct vcpu_svm *svm = to_svm(vcpu);
1188
1189         switch (ecx) {
1190         case MSR_IA32_TIME_STAMP_COUNTER: {
1191                 u64 tsc;
1192
1193                 rdtscll(tsc);
1194                 *data = svm->vmcb->control.tsc_offset + tsc;
1195                 break;
1196         }
1197         case MSR_K6_STAR:
1198                 *data = svm->vmcb->save.star;
1199                 break;
1200 #ifdef CONFIG_X86_64
1201         case MSR_LSTAR:
1202                 *data = svm->vmcb->save.lstar;
1203                 break;
1204         case MSR_CSTAR:
1205                 *data = svm->vmcb->save.cstar;
1206                 break;
1207         case MSR_KERNEL_GS_BASE:
1208                 *data = svm->vmcb->save.kernel_gs_base;
1209                 break;
1210         case MSR_SYSCALL_MASK:
1211                 *data = svm->vmcb->save.sfmask;
1212                 break;
1213 #endif
1214         case MSR_IA32_SYSENTER_CS:
1215                 *data = svm->vmcb->save.sysenter_cs;
1216                 break;
1217         case MSR_IA32_SYSENTER_EIP:
1218                 *data = svm->vmcb->save.sysenter_eip;
1219                 break;
1220         case MSR_IA32_SYSENTER_ESP:
1221                 *data = svm->vmcb->save.sysenter_esp;
1222                 break;
1223         /* Nobody will change the following 5 values in the VMCB so
1224            we can safely return them on rdmsr. They will always be 0
1225            until LBRV is implemented. */
1226         case MSR_IA32_DEBUGCTLMSR:
1227                 *data = svm->vmcb->save.dbgctl;
1228                 break;
1229         case MSR_IA32_LASTBRANCHFROMIP:
1230                 *data = svm->vmcb->save.br_from;
1231                 break;
1232         case MSR_IA32_LASTBRANCHTOIP:
1233                 *data = svm->vmcb->save.br_to;
1234                 break;
1235         case MSR_IA32_LASTINTFROMIP:
1236                 *data = svm->vmcb->save.last_excp_from;
1237                 break;
1238         case MSR_IA32_LASTINTTOIP:
1239                 *data = svm->vmcb->save.last_excp_to;
1240                 break;
1241         default:
1242                 return kvm_get_msr_common(vcpu, ecx, data);
1243         }
1244         return 0;
1245 }
1246
1247 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1248 {
1249         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1250         u64 data;
1251
1252         if (svm_get_msr(&svm->vcpu, ecx, &data))
1253                 kvm_inject_gp(&svm->vcpu, 0);
1254         else {
1255                 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
1256                             (u32)(data >> 32), handler);
1257
1258                 svm->vmcb->save.rax = data & 0xffffffff;
1259                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1260                 svm->next_rip = svm->vmcb->save.rip + 2;
1261                 skip_emulated_instruction(&svm->vcpu);
1262         }
1263         return 1;
1264 }
1265
1266 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1267 {
1268         struct vcpu_svm *svm = to_svm(vcpu);
1269
1270         switch (ecx) {
1271         case MSR_IA32_TIME_STAMP_COUNTER: {
1272                 u64 tsc;
1273
1274                 rdtscll(tsc);
1275                 svm->vmcb->control.tsc_offset = data - tsc;
1276                 break;
1277         }
1278         case MSR_K6_STAR:
1279                 svm->vmcb->save.star = data;
1280                 break;
1281 #ifdef CONFIG_X86_64
1282         case MSR_LSTAR:
1283                 svm->vmcb->save.lstar = data;
1284                 break;
1285         case MSR_CSTAR:
1286                 svm->vmcb->save.cstar = data;
1287                 break;
1288         case MSR_KERNEL_GS_BASE:
1289                 svm->vmcb->save.kernel_gs_base = data;
1290                 break;
1291         case MSR_SYSCALL_MASK:
1292                 svm->vmcb->save.sfmask = data;
1293                 break;
1294 #endif
1295         case MSR_IA32_SYSENTER_CS:
1296                 svm->vmcb->save.sysenter_cs = data;
1297                 break;
1298         case MSR_IA32_SYSENTER_EIP:
1299                 svm->vmcb->save.sysenter_eip = data;
1300                 break;
1301         case MSR_IA32_SYSENTER_ESP:
1302                 svm->vmcb->save.sysenter_esp = data;
1303                 break;
1304         case MSR_IA32_DEBUGCTLMSR:
1305                 if (!svm_has(SVM_FEATURE_LBRV)) {
1306                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
1307                                         __func__, data);
1308                         break;
1309                 }
1310                 if (data & DEBUGCTL_RESERVED_BITS)
1311                         return 1;
1312
1313                 svm->vmcb->save.dbgctl = data;
1314                 if (data & (1ULL<<0))
1315                         svm_enable_lbrv(svm);
1316                 else
1317                         svm_disable_lbrv(svm);
1318                 break;
1319         case MSR_K7_EVNTSEL0:
1320         case MSR_K7_EVNTSEL1:
1321         case MSR_K7_EVNTSEL2:
1322         case MSR_K7_EVNTSEL3:
1323         case MSR_K7_PERFCTR0:
1324         case MSR_K7_PERFCTR1:
1325         case MSR_K7_PERFCTR2:
1326         case MSR_K7_PERFCTR3:
1327                 /*
1328                  * Just discard all writes to the performance counters; this
1329                  * should keep both older linux and windows 64-bit guests
1330                  * happy
1331                  */
1332                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
1333
1334                 break;
1335         default:
1336                 return kvm_set_msr_common(vcpu, ecx, data);
1337         }
1338         return 0;
1339 }
1340
1341 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1342 {
1343         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1344         u64 data = (svm->vmcb->save.rax & -1u)
1345                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
1346
1347         KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
1348                     handler);
1349
1350         svm->next_rip = svm->vmcb->save.rip + 2;
1351         if (svm_set_msr(&svm->vcpu, ecx, data))
1352                 kvm_inject_gp(&svm->vcpu, 0);
1353         else
1354                 skip_emulated_instruction(&svm->vcpu);
1355         return 1;
1356 }
1357
1358 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1359 {
1360         if (svm->vmcb->control.exit_info_1)
1361                 return wrmsr_interception(svm, kvm_run);
1362         else
1363                 return rdmsr_interception(svm, kvm_run);
1364 }
1365
1366 static int interrupt_window_interception(struct vcpu_svm *svm,
1367                                    struct kvm_run *kvm_run)
1368 {
1369         KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
1370
1371         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1372         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1373         /*
1374          * If the user space waits to inject interrupts, exit as soon as
1375          * possible
1376          */
1377         if (kvm_run->request_interrupt_window &&
1378             !svm->vcpu.arch.irq_summary) {
1379                 ++svm->vcpu.stat.irq_window_exits;
1380                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1381                 return 0;
1382         }
1383
1384         return 1;
1385 }
1386
1387 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1388                                       struct kvm_run *kvm_run) = {
1389         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
1390         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
1391         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
1392         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
1393         /* for now: */
1394         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
1395         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
1396         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
1397         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
1398         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
1399         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
1400         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
1401         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
1402         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
1403         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
1404         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
1405         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
1406         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
1407         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
1408         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
1409         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
1410         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
1411         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
1412         [SVM_EXIT_INTR]                         = intr_interception,
1413         [SVM_EXIT_NMI]                          = nmi_interception,
1414         [SVM_EXIT_SMI]                          = nop_on_interception,
1415         [SVM_EXIT_INIT]                         = nop_on_interception,
1416         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
1417         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
1418         [SVM_EXIT_CPUID]                        = cpuid_interception,
1419         [SVM_EXIT_INVD]                         = emulate_on_interception,
1420         [SVM_EXIT_HLT]                          = halt_interception,
1421         [SVM_EXIT_INVLPG]                       = emulate_on_interception,
1422         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
1423         [SVM_EXIT_IOIO]                         = io_interception,
1424         [SVM_EXIT_MSR]                          = msr_interception,
1425         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
1426         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
1427         [SVM_EXIT_VMRUN]                        = invalid_op_interception,
1428         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
1429         [SVM_EXIT_VMLOAD]                       = invalid_op_interception,
1430         [SVM_EXIT_VMSAVE]                       = invalid_op_interception,
1431         [SVM_EXIT_STGI]                         = invalid_op_interception,
1432         [SVM_EXIT_CLGI]                         = invalid_op_interception,
1433         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
1434         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
1435         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
1436         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
1437         [SVM_EXIT_NPF]                          = pf_interception,
1438 };
1439
1440 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1441 {
1442         struct vcpu_svm *svm = to_svm(vcpu);
1443         u32 exit_code = svm->vmcb->control.exit_code;
1444
1445         KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
1446                     (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
1447
1448         if (npt_enabled) {
1449                 int mmu_reload = 0;
1450                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
1451                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
1452                         mmu_reload = 1;
1453                 }
1454                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
1455                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
1456                 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1457                         if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1458                                 kvm_inject_gp(vcpu, 0);
1459                                 return 1;
1460                         }
1461                 }
1462                 if (mmu_reload) {
1463                         kvm_mmu_reset_context(vcpu);
1464                         kvm_mmu_load(vcpu);
1465                 }
1466         }
1467
1468         kvm_reput_irq(svm);
1469
1470         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1471                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1472                 kvm_run->fail_entry.hardware_entry_failure_reason
1473                         = svm->vmcb->control.exit_code;
1474                 return 0;
1475         }
1476
1477         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1478             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
1479             exit_code != SVM_EXIT_NPF)
1480                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1481                        "exit_code 0x%x\n",
1482                        __func__, svm->vmcb->control.exit_int_info,
1483                        exit_code);
1484
1485         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1486             || !svm_exit_handlers[exit_code]) {
1487                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1488                 kvm_run->hw.hardware_exit_reason = exit_code;
1489                 return 0;
1490         }
1491
1492         return svm_exit_handlers[exit_code](svm, kvm_run);
1493 }
1494
1495 static void reload_tss(struct kvm_vcpu *vcpu)
1496 {
1497         int cpu = raw_smp_processor_id();
1498
1499         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1500         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
1501         load_TR_desc();
1502 }
1503
1504 static void pre_svm_run(struct vcpu_svm *svm)
1505 {
1506         int cpu = raw_smp_processor_id();
1507
1508         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1509
1510         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1511         if (svm->vcpu.cpu != cpu ||
1512             svm->asid_generation != svm_data->asid_generation)
1513                 new_asid(svm, svm_data);
1514 }
1515
1516
1517 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1518 {
1519         struct vmcb_control_area *control;
1520
1521         KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
1522
1523         control = &svm->vmcb->control;
1524         control->int_vector = irq;
1525         control->int_ctl &= ~V_INTR_PRIO_MASK;
1526         control->int_ctl |= V_IRQ_MASK |
1527                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1528 }
1529
1530 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1531 {
1532         struct vcpu_svm *svm = to_svm(vcpu);
1533
1534         svm_inject_irq(svm, irq);
1535 }
1536
1537 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
1538 {
1539         struct vcpu_svm *svm = to_svm(vcpu);
1540         struct vmcb *vmcb = svm->vmcb;
1541         int max_irr, tpr;
1542
1543         if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
1544                 return;
1545
1546         vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1547
1548         max_irr = kvm_lapic_find_highest_irr(vcpu);
1549         if (max_irr == -1)
1550                 return;
1551
1552         tpr = kvm_lapic_get_cr8(vcpu) << 4;
1553
1554         if (tpr >= (max_irr & 0xf0))
1555                 vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
1556 }
1557
1558 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1559 {
1560         struct vcpu_svm *svm = to_svm(vcpu);
1561         struct vmcb *vmcb = svm->vmcb;
1562         int intr_vector = -1;
1563
1564         if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1565             ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1566                 intr_vector = vmcb->control.exit_int_info &
1567                               SVM_EVTINJ_VEC_MASK;
1568                 vmcb->control.exit_int_info = 0;
1569                 svm_inject_irq(svm, intr_vector);
1570                 goto out;
1571         }
1572
1573         if (vmcb->control.int_ctl & V_IRQ_MASK)
1574                 goto out;
1575
1576         if (!kvm_cpu_has_interrupt(vcpu))
1577                 goto out;
1578
1579         if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1580             (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1581             (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1582                 /* unable to deliver irq, set pending irq */
1583                 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1584                 svm_inject_irq(svm, 0x0);
1585                 goto out;
1586         }
1587         /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1588         intr_vector = kvm_cpu_get_interrupt(vcpu);
1589         svm_inject_irq(svm, intr_vector);
1590         kvm_timer_intr_post(vcpu, intr_vector);
1591 out:
1592         update_cr8_intercept(vcpu);
1593 }
1594
1595 static void kvm_reput_irq(struct vcpu_svm *svm)
1596 {
1597         struct vmcb_control_area *control = &svm->vmcb->control;
1598
1599         if ((control->int_ctl & V_IRQ_MASK)
1600             && !irqchip_in_kernel(svm->vcpu.kvm)) {
1601                 control->int_ctl &= ~V_IRQ_MASK;
1602                 push_irq(&svm->vcpu, control->int_vector);
1603         }
1604
1605         svm->vcpu.arch.interrupt_window_open =
1606                 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1607 }
1608
1609 static void svm_do_inject_vector(struct vcpu_svm *svm)
1610 {
1611         struct kvm_vcpu *vcpu = &svm->vcpu;
1612         int word_index = __ffs(vcpu->arch.irq_summary);
1613         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1614         int irq = word_index * BITS_PER_LONG + bit_index;
1615
1616         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1617         if (!vcpu->arch.irq_pending[word_index])
1618                 clear_bit(word_index, &vcpu->arch.irq_summary);
1619         svm_inject_irq(svm, irq);
1620 }
1621
1622 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1623                                        struct kvm_run *kvm_run)
1624 {
1625         struct vcpu_svm *svm = to_svm(vcpu);
1626         struct vmcb_control_area *control = &svm->vmcb->control;
1627
1628         svm->vcpu.arch.interrupt_window_open =
1629                 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1630                  (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1631
1632         if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
1633                 /*
1634                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1635                  */
1636                 svm_do_inject_vector(svm);
1637
1638         /*
1639          * Interrupts blocked.  Wait for unblock.
1640          */
1641         if (!svm->vcpu.arch.interrupt_window_open &&
1642             (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
1643                 control->intercept |= 1ULL << INTERCEPT_VINTR;
1644          else
1645                 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1646 }
1647
1648 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
1649 {
1650         return 0;
1651 }
1652
1653 static void save_db_regs(unsigned long *db_regs)
1654 {
1655         asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1656         asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1657         asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1658         asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1659 }
1660
1661 static void load_db_regs(unsigned long *db_regs)
1662 {
1663         asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1664         asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1665         asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1666         asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1667 }
1668
1669 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1670 {
1671         force_new_asid(vcpu);
1672 }
1673
1674 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1675 {
1676 }
1677
1678 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
1679 {
1680         struct vcpu_svm *svm = to_svm(vcpu);
1681
1682         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
1683                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
1684                 kvm_lapic_set_tpr(vcpu, cr8);
1685         }
1686 }
1687
1688 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
1689 {
1690         struct vcpu_svm *svm = to_svm(vcpu);
1691         u64 cr8;
1692
1693         if (!irqchip_in_kernel(vcpu->kvm))
1694                 return;
1695
1696         cr8 = kvm_get_cr8(vcpu);
1697         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
1698         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
1699 }
1700
1701 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1702 {
1703         struct vcpu_svm *svm = to_svm(vcpu);
1704         u16 fs_selector;
1705         u16 gs_selector;
1706         u16 ldt_selector;
1707
1708         pre_svm_run(svm);
1709
1710         sync_lapic_to_cr8(vcpu);
1711
1712         save_host_msrs(vcpu);
1713         fs_selector = kvm_read_fs();
1714         gs_selector = kvm_read_gs();
1715         ldt_selector = kvm_read_ldt();
1716         svm->host_cr2 = kvm_read_cr2();
1717         svm->host_dr6 = read_dr6();
1718         svm->host_dr7 = read_dr7();
1719         svm->vmcb->save.cr2 = vcpu->arch.cr2;
1720         /* required for live migration with NPT */
1721         if (npt_enabled)
1722                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
1723
1724         if (svm->vmcb->save.dr7 & 0xff) {
1725                 write_dr7(0);
1726                 save_db_regs(svm->host_db_regs);
1727                 load_db_regs(svm->db_regs);
1728         }
1729
1730         clgi();
1731
1732         local_irq_enable();
1733
1734         asm volatile (
1735 #ifdef CONFIG_X86_64
1736                 "push %%rbp; \n\t"
1737 #else
1738                 "push %%ebp; \n\t"
1739 #endif
1740
1741 #ifdef CONFIG_X86_64
1742                 "mov %c[rbx](%[svm]), %%rbx \n\t"
1743                 "mov %c[rcx](%[svm]), %%rcx \n\t"
1744                 "mov %c[rdx](%[svm]), %%rdx \n\t"
1745                 "mov %c[rsi](%[svm]), %%rsi \n\t"
1746                 "mov %c[rdi](%[svm]), %%rdi \n\t"
1747                 "mov %c[rbp](%[svm]), %%rbp \n\t"
1748                 "mov %c[r8](%[svm]),  %%r8  \n\t"
1749                 "mov %c[r9](%[svm]),  %%r9  \n\t"
1750                 "mov %c[r10](%[svm]), %%r10 \n\t"
1751                 "mov %c[r11](%[svm]), %%r11 \n\t"
1752                 "mov %c[r12](%[svm]), %%r12 \n\t"
1753                 "mov %c[r13](%[svm]), %%r13 \n\t"
1754                 "mov %c[r14](%[svm]), %%r14 \n\t"
1755                 "mov %c[r15](%[svm]), %%r15 \n\t"
1756 #else
1757                 "mov %c[rbx](%[svm]), %%ebx \n\t"
1758                 "mov %c[rcx](%[svm]), %%ecx \n\t"
1759                 "mov %c[rdx](%[svm]), %%edx \n\t"
1760                 "mov %c[rsi](%[svm]), %%esi \n\t"
1761                 "mov %c[rdi](%[svm]), %%edi \n\t"
1762                 "mov %c[rbp](%[svm]), %%ebp \n\t"
1763 #endif
1764
1765 #ifdef CONFIG_X86_64
1766                 /* Enter guest mode */
1767                 "push %%rax \n\t"
1768                 "mov %c[vmcb](%[svm]), %%rax \n\t"
1769                 __ex(SVM_VMLOAD) "\n\t"
1770                 __ex(SVM_VMRUN) "\n\t"
1771                 __ex(SVM_VMSAVE) "\n\t"
1772                 "pop %%rax \n\t"
1773 #else
1774                 /* Enter guest mode */
1775                 "push %%eax \n\t"
1776                 "mov %c[vmcb](%[svm]), %%eax \n\t"
1777                 __ex(SVM_VMLOAD) "\n\t"
1778                 __ex(SVM_VMRUN) "\n\t"
1779                 __ex(SVM_VMSAVE) "\n\t"
1780                 "pop %%eax \n\t"
1781 #endif
1782
1783                 /* Save guest registers, load host registers */
1784 #ifdef CONFIG_X86_64
1785                 "mov %%rbx, %c[rbx](%[svm]) \n\t"
1786                 "mov %%rcx, %c[rcx](%[svm]) \n\t"
1787                 "mov %%rdx, %c[rdx](%[svm]) \n\t"
1788                 "mov %%rsi, %c[rsi](%[svm]) \n\t"
1789                 "mov %%rdi, %c[rdi](%[svm]) \n\t"
1790                 "mov %%rbp, %c[rbp](%[svm]) \n\t"
1791                 "mov %%r8,  %c[r8](%[svm]) \n\t"
1792                 "mov %%r9,  %c[r9](%[svm]) \n\t"
1793                 "mov %%r10, %c[r10](%[svm]) \n\t"
1794                 "mov %%r11, %c[r11](%[svm]) \n\t"
1795                 "mov %%r12, %c[r12](%[svm]) \n\t"
1796                 "mov %%r13, %c[r13](%[svm]) \n\t"
1797                 "mov %%r14, %c[r14](%[svm]) \n\t"
1798                 "mov %%r15, %c[r15](%[svm]) \n\t"
1799
1800                 "pop  %%rbp; \n\t"
1801 #else
1802                 "mov %%ebx, %c[rbx](%[svm]) \n\t"
1803                 "mov %%ecx, %c[rcx](%[svm]) \n\t"
1804                 "mov %%edx, %c[rdx](%[svm]) \n\t"
1805                 "mov %%esi, %c[rsi](%[svm]) \n\t"
1806                 "mov %%edi, %c[rdi](%[svm]) \n\t"
1807                 "mov %%ebp, %c[rbp](%[svm]) \n\t"
1808
1809                 "pop  %%ebp; \n\t"
1810 #endif
1811                 :
1812                 : [svm]"a"(svm),
1813                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1814                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
1815                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
1816                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
1817                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
1818                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
1819                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
1820 #ifdef CONFIG_X86_64
1821                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
1822                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
1823                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
1824                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
1825                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
1826                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
1827                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
1828                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
1829 #endif
1830                 : "cc", "memory"
1831 #ifdef CONFIG_X86_64
1832                 , "rbx", "rcx", "rdx", "rsi", "rdi"
1833                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
1834 #else
1835                 , "ebx", "ecx", "edx" , "esi", "edi"
1836 #endif
1837                 );
1838
1839         if ((svm->vmcb->save.dr7 & 0xff))
1840                 load_db_regs(svm->host_db_regs);
1841
1842         vcpu->arch.cr2 = svm->vmcb->save.cr2;
1843
1844         write_dr6(svm->host_dr6);
1845         write_dr7(svm->host_dr7);
1846         kvm_write_cr2(svm->host_cr2);
1847
1848         kvm_load_fs(fs_selector);
1849         kvm_load_gs(gs_selector);
1850         kvm_load_ldt(ldt_selector);
1851         load_host_msrs(vcpu);
1852
1853         reload_tss(vcpu);
1854
1855         local_irq_disable();
1856
1857         stgi();
1858
1859         sync_cr8_to_lapic(vcpu);
1860
1861         svm->next_rip = 0;
1862 }
1863
1864 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1865 {
1866         struct vcpu_svm *svm = to_svm(vcpu);
1867
1868         if (npt_enabled) {
1869                 svm->vmcb->control.nested_cr3 = root;
1870                 force_new_asid(vcpu);
1871                 return;
1872         }
1873
1874         svm->vmcb->save.cr3 = root;
1875         force_new_asid(vcpu);
1876
1877         if (vcpu->fpu_active) {
1878                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1879                 svm->vmcb->save.cr0 |= X86_CR0_TS;
1880                 vcpu->fpu_active = 0;
1881         }
1882 }
1883
1884 static int is_disabled(void)
1885 {
1886         u64 vm_cr;
1887
1888         rdmsrl(MSR_VM_CR, vm_cr);
1889         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1890                 return 1;
1891
1892         return 0;
1893 }
1894
1895 static void
1896 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1897 {
1898         /*
1899          * Patch in the VMMCALL instruction:
1900          */
1901         hypercall[0] = 0x0f;
1902         hypercall[1] = 0x01;
1903         hypercall[2] = 0xd9;
1904 }
1905
1906 static void svm_check_processor_compat(void *rtn)
1907 {
1908         *(int *)rtn = 0;
1909 }
1910
1911 static bool svm_cpu_has_accelerated_tpr(void)
1912 {
1913         return false;
1914 }
1915
1916 static int get_npt_level(void)
1917 {
1918 #ifdef CONFIG_X86_64
1919         return PT64_ROOT_LEVEL;
1920 #else
1921         return PT32E_ROOT_LEVEL;
1922 #endif
1923 }
1924
1925 static struct kvm_x86_ops svm_x86_ops = {
1926         .cpu_has_kvm_support = has_svm,
1927         .disabled_by_bios = is_disabled,
1928         .hardware_setup = svm_hardware_setup,
1929         .hardware_unsetup = svm_hardware_unsetup,
1930         .check_processor_compatibility = svm_check_processor_compat,
1931         .hardware_enable = svm_hardware_enable,
1932         .hardware_disable = svm_hardware_disable,
1933         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
1934
1935         .vcpu_create = svm_create_vcpu,
1936         .vcpu_free = svm_free_vcpu,
1937         .vcpu_reset = svm_vcpu_reset,
1938
1939         .prepare_guest_switch = svm_prepare_guest_switch,
1940         .vcpu_load = svm_vcpu_load,
1941         .vcpu_put = svm_vcpu_put,
1942
1943         .set_guest_debug = svm_guest_debug,
1944         .get_msr = svm_get_msr,
1945         .set_msr = svm_set_msr,
1946         .get_segment_base = svm_get_segment_base,
1947         .get_segment = svm_get_segment,
1948         .set_segment = svm_set_segment,
1949         .get_cpl = svm_get_cpl,
1950         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1951         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1952         .set_cr0 = svm_set_cr0,
1953         .set_cr3 = svm_set_cr3,
1954         .set_cr4 = svm_set_cr4,
1955         .set_efer = svm_set_efer,
1956         .get_idt = svm_get_idt,
1957         .set_idt = svm_set_idt,
1958         .get_gdt = svm_get_gdt,
1959         .set_gdt = svm_set_gdt,
1960         .get_dr = svm_get_dr,
1961         .set_dr = svm_set_dr,
1962         .cache_regs = svm_cache_regs,
1963         .decache_regs = svm_decache_regs,
1964         .get_rflags = svm_get_rflags,
1965         .set_rflags = svm_set_rflags,
1966
1967         .tlb_flush = svm_flush_tlb,
1968
1969         .run = svm_vcpu_run,
1970         .handle_exit = handle_exit,
1971         .skip_emulated_instruction = skip_emulated_instruction,
1972         .patch_hypercall = svm_patch_hypercall,
1973         .get_irq = svm_get_irq,
1974         .set_irq = svm_set_irq,
1975         .queue_exception = svm_queue_exception,
1976         .exception_injected = svm_exception_injected,
1977         .inject_pending_irq = svm_intr_assist,
1978         .inject_pending_vectors = do_interrupt_requests,
1979
1980         .set_tss_addr = svm_set_tss_addr,
1981         .get_tdp_level = get_npt_level,
1982 };
1983
1984 static int __init svm_init(void)
1985 {
1986         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
1987                               THIS_MODULE);
1988 }
1989
1990 static void __exit svm_exit(void)
1991 {
1992         kvm_exit();
1993 }
1994
1995 module_init(svm_init)
1996 module_exit(svm_exit)