arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17 #include <linux/kvm_host.h>
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22 #include "x86.h"
  23
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31
  32 #include <asm/tlbflush.h>
  33 #include <asm/desc.h>
  34 #include <asm/kvm_para.h>
  35
  36 #include <asm/virtext.h>
  37 #include "trace.h"
  38
  39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  40
  41 MODULE_AUTHOR("Qumranet");
  42 MODULE_LICENSE("GPL");
  43
  44 #define IOPM_ALLOC_ORDER 2
  45 #define MSRPM_ALLOC_ORDER 1
  46
  47 #define SEG_TYPE_LDT 2
  48 #define SEG_TYPE_BUSY_TSS16 3
  49
  50 #define SVM_FEATURE_NPT            (1 <<  0)
  51 #define SVM_FEATURE_LBRV           (1 <<  1)
  52 #define SVM_FEATURE_SVML           (1 <<  2)
  53 #define SVM_FEATURE_NRIP           (1 <<  3)
  54 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  55
  56 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  57 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  58 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  59
  60 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  61
  62 static bool erratum_383_found __read_mostly;
  63
  64 static const u32 host_save_user_msrs[] = {
  65 #ifdef CONFIG_X86_64
  66         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  67         MSR_FS_BASE,
  68 #endif
  69         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  70 };
  71
  72 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  73
  74 struct kvm_vcpu;
  75
  76 struct nested_state {
  77         struct vmcb *hsave;
  78         u64 hsave_msr;
  79         u64 vm_cr_msr;
  80         u64 vmcb;
  81
  82         /* These are the merged vectors */
  83         u32 *msrpm;
  84
  85         /* gpa pointers to the real vectors */
  86         u64 vmcb_msrpm;
  87         u64 vmcb_iopm;
  88
  89         /* A VMEXIT is required but not yet emulated */
  90         bool exit_required;
  91
  92         /*
  93          * If we vmexit during an instruction emulation we need this to restore
  94          * the l1 guest rip after the emulation
  95          */
  96         unsigned long vmexit_rip;
  97         unsigned long vmexit_rsp;
  98         unsigned long vmexit_rax;
  99
 100         /* cache for intercepts of the guest */
 101         u32 intercept_cr;
 102         u32 intercept_dr;
 103         u32 intercept_exceptions;
 104         u64 intercept;
 105
 106         /* Nested Paging related state */
 107         u64 nested_cr3;
 108 };
 109
 110 #define MSRPM_OFFSETS   16
 111 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 112
 113 struct vcpu_svm {
 114         struct kvm_vcpu vcpu;
 115         struct vmcb *vmcb;
 116         unsigned long vmcb_pa;
 117         struct svm_cpu_data *svm_data;
 118         uint64_t asid_generation;
 119         uint64_t sysenter_esp;
 120         uint64_t sysenter_eip;
 121
 122         u64 next_rip;
 123
 124         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 125         struct {
 126                 u16 fs;
 127                 u16 gs;
 128                 u16 ldt;
 129                 u64 gs_base;
 130         } host;
 131
 132         u32 *msrpm;
 133
 134         struct nested_state nested;
 135
 136         bool nmi_singlestep;
 137
 138         unsigned int3_injected;
 139         unsigned long int3_rip;
 140         u32 apf_reason;
 141 };
 142
 143 #define MSR_INVALID                     0xffffffffU
 144
 145 static struct svm_direct_access_msrs {
 146         u32 index;   /* Index of the MSR */
 147         bool always; /* True if intercept is always on */
 148 } direct_access_msrs[] = {
 149         { .index = MSR_STAR,                            .always = true  },
 150         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 151 #ifdef CONFIG_X86_64
 152         { .index = MSR_GS_BASE,                         .always = true  },
 153         { .index = MSR_FS_BASE,                         .always = true  },
 154         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 155         { .index = MSR_LSTAR,                           .always = true  },
 156         { .index = MSR_CSTAR,                           .always = true  },
 157         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 158 #endif
 159         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 160         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 161         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 162         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 163         { .index = MSR_INVALID,                         .always = false },
 164 };
 165
 166 /* enable NPT for AMD64 and X86 with PAE */
 167 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 168 static bool npt_enabled = true;
 169 #else
 170 static bool npt_enabled;
 171 #endif
 172 static int npt = 1;
 173
 174 module_param(npt, int, S_IRUGO);
 175
 176 static int nested = 1;
 177 module_param(nested, int, S_IRUGO);
 178
 179 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 180 static void svm_complete_interrupts(struct vcpu_svm *svm);
 181
 182 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 183 static int nested_svm_intercept(struct vcpu_svm *svm);
 184 static int nested_svm_vmexit(struct vcpu_svm *svm);
 185 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 186                                       bool has_error_code, u32 error_code);
 187
 188 enum {
 189         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 190                             pause filter count */
 191         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 192         VMCB_ASID,       /* ASID */
 193         VMCB_DIRTY_MAX,
 194 };
 195
 196 #define VMCB_ALWAYS_DIRTY_MASK  0U
 197
 198 static inline void mark_all_dirty(struct vmcb *vmcb)
 199 {
 200         vmcb->control.clean = 0;
 201 }
 202
 203 static inline void mark_all_clean(struct vmcb *vmcb)
 204 {
 205         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 206                                & ~VMCB_ALWAYS_DIRTY_MASK;
 207 }
 208
 209 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 210 {
 211         vmcb->control.clean &= ~(1 << bit);
 212 }
 213
 214 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 215 {
 216         return container_of(vcpu, struct vcpu_svm, vcpu);
 217 }
 218
 219 static void recalc_intercepts(struct vcpu_svm *svm)
 220 {
 221         struct vmcb_control_area *c, *h;
 222         struct nested_state *g;
 223
 224         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 225
 226         if (!is_guest_mode(&svm->vcpu))
 227                 return;
 228
 229         c = &svm->vmcb->control;
 230         h = &svm->nested.hsave->control;
 231         g = &svm->nested;
 232
 233         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 234         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 235         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 236         c->intercept = h->intercept | g->intercept;
 237 }
 238
 239 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 240 {
 241         if (is_guest_mode(&svm->vcpu))
 242                 return svm->nested.hsave;
 243         else
 244                 return svm->vmcb;
 245 }
 246
 247 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 248 {
 249         struct vmcb *vmcb = get_host_vmcb(svm);
 250
 251         vmcb->control.intercept_cr |= (1U << bit);
 252
 253         recalc_intercepts(svm);
 254 }
 255
 256 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 257 {
 258         struct vmcb *vmcb = get_host_vmcb(svm);
 259
 260         vmcb->control.intercept_cr &= ~(1U << bit);
 261
 262         recalc_intercepts(svm);
 263 }
 264
 265 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 266 {
 267         struct vmcb *vmcb = get_host_vmcb(svm);
 268
 269         return vmcb->control.intercept_cr & (1U << bit);
 270 }
 271
 272 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
 273 {
 274         struct vmcb *vmcb = get_host_vmcb(svm);
 275
 276         vmcb->control.intercept_dr |= (1U << bit);
 277
 278         recalc_intercepts(svm);
 279 }
 280
 281 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
 282 {
 283         struct vmcb *vmcb = get_host_vmcb(svm);
 284
 285         vmcb->control.intercept_dr &= ~(1U << bit);
 286
 287         recalc_intercepts(svm);
 288 }
 289
 290 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 291 {
 292         struct vmcb *vmcb = get_host_vmcb(svm);
 293
 294         vmcb->control.intercept_exceptions |= (1U << bit);
 295
 296         recalc_intercepts(svm);
 297 }
 298
 299 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 300 {
 301         struct vmcb *vmcb = get_host_vmcb(svm);
 302
 303         vmcb->control.intercept_exceptions &= ~(1U << bit);
 304
 305         recalc_intercepts(svm);
 306 }
 307
 308 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 309 {
 310         struct vmcb *vmcb = get_host_vmcb(svm);
 311
 312         vmcb->control.intercept |= (1ULL << bit);
 313
 314         recalc_intercepts(svm);
 315 }
 316
 317 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 318 {
 319         struct vmcb *vmcb = get_host_vmcb(svm);
 320
 321         vmcb->control.intercept &= ~(1ULL << bit);
 322
 323         recalc_intercepts(svm);
 324 }
 325
 326 static inline void enable_gif(struct vcpu_svm *svm)
 327 {
 328         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 329 }
 330
 331 static inline void disable_gif(struct vcpu_svm *svm)
 332 {
 333         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 334 }
 335
 336 static inline bool gif_set(struct vcpu_svm *svm)
 337 {
 338         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 339 }
 340
 341 static unsigned long iopm_base;
 342
 343 struct kvm_ldttss_desc {
 344         u16 limit0;
 345         u16 base0;
 346         unsigned base1:8, type:5, dpl:2, p:1;
 347         unsigned limit1:4, zero0:3, g:1, base2:8;
 348         u32 base3;
 349         u32 zero1;
 350 } __attribute__((packed));
 351
 352 struct svm_cpu_data {
 353         int cpu;
 354
 355         u64 asid_generation;
 356         u32 max_asid;
 357         u32 next_asid;
 358         struct kvm_ldttss_desc *tss_desc;
 359
 360         struct page *save_area;
 361 };
 362
 363 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 364 static uint32_t svm_features;
 365
 366 struct svm_init_data {
 367         int cpu;
 368         int r;
 369 };
 370
 371 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 372
 373 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 374 #define MSRS_RANGE_SIZE 2048
 375 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 376
 377 static u32 svm_msrpm_offset(u32 msr)
 378 {
 379         u32 offset;
 380         int i;
 381
 382         for (i = 0; i < NUM_MSR_MAPS; i++) {
 383                 if (msr < msrpm_ranges[i] ||
 384                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 385                         continue;
 386
 387                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 388                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 389
 390                 /* Now we have the u8 offset - but need the u32 offset */
 391                 return offset / 4;
 392         }
 393
 394         /* MSR not in any range */
 395         return MSR_INVALID;
 396 }
 397
 398 #define MAX_INST_SIZE 15
 399
 400 static inline void clgi(void)
 401 {
 402         asm volatile (__ex(SVM_CLGI));
 403 }
 404
 405 static inline void stgi(void)
 406 {
 407         asm volatile (__ex(SVM_STGI));
 408 }
 409
 410 static inline void invlpga(unsigned long addr, u32 asid)
 411 {
 412         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 413 }
 414
 415 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 416 {
 417         to_svm(vcpu)->asid_generation--;
 418 }
 419
 420 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 421 {
 422         force_new_asid(vcpu);
 423 }
 424
 425 static int get_npt_level(void)
 426 {
 427 #ifdef CONFIG_X86_64
 428         return PT64_ROOT_LEVEL;
 429 #else
 430         return PT32E_ROOT_LEVEL;
 431 #endif
 432 }
 433
 434 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 435 {
 436         vcpu->arch.efer = efer;
 437         if (!npt_enabled && !(efer & EFER_LMA))
 438                 efer &= ~EFER_LME;
 439
 440         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 441 }
 442
 443 static int is_external_interrupt(u32 info)
 444 {
 445         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 446         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 447 }
 448
 449 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 450 {
 451         struct vcpu_svm *svm = to_svm(vcpu);
 452         u32 ret = 0;
 453
 454         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 455                 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 456         return ret & mask;
 457 }
 458
 459 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 460 {
 461         struct vcpu_svm *svm = to_svm(vcpu);
 462
 463         if (mask == 0)
 464                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 465         else
 466                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 467
 468 }
 469
 470 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 471 {
 472         struct vcpu_svm *svm = to_svm(vcpu);
 473
 474         if (svm->vmcb->control.next_rip != 0)
 475                 svm->next_rip = svm->vmcb->control.next_rip;
 476
 477         if (!svm->next_rip) {
 478                 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
 479                                 EMULATE_DONE)
 480                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 481                 return;
 482         }
 483         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 484                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 485                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 486
 487         kvm_rip_write(vcpu, svm->next_rip);
 488         svm_set_interrupt_shadow(vcpu, 0);
 489 }
 490
 491 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 492                                 bool has_error_code, u32 error_code,
 493                                 bool reinject)
 494 {
 495         struct vcpu_svm *svm = to_svm(vcpu);
 496
 497         /*
 498          * If we are within a nested VM we'd better #VMEXIT and let the guest
 499          * handle the exception
 500          */
 501         if (!reinject &&
 502             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 503                 return;
 504
 505         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 506                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 507
 508                 /*
 509                  * For guest debugging where we have to reinject #BP if some
 510                  * INT3 is guest-owned:
 511                  * Emulate nRIP by moving RIP forward. Will fail if injection
 512                  * raises a fault that is not intercepted. Still better than
 513                  * failing in all cases.
 514                  */
 515                 skip_emulated_instruction(&svm->vcpu);
 516                 rip = kvm_rip_read(&svm->vcpu);
 517                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 518                 svm->int3_injected = rip - old_rip;
 519         }
 520
 521         svm->vmcb->control.event_inj = nr
 522                 | SVM_EVTINJ_VALID
 523                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 524                 | SVM_EVTINJ_TYPE_EXEPT;
 525         svm->vmcb->control.event_inj_err = error_code;
 526 }
 527
 528 static void svm_init_erratum_383(void)
 529 {
 530         u32 low, high;
 531         int err;
 532         u64 val;
 533
 534         if (!cpu_has_amd_erratum(amd_erratum_383))
 535                 return;
 536
 537         /* Use _safe variants to not break nested virtualization */
 538         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 539         if (err)
 540                 return;
 541
 542         val |= (1ULL << 47);
 543
 544         low  = lower_32_bits(val);
 545         high = upper_32_bits(val);
 546
 547         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 548
 549         erratum_383_found = true;
 550 }
 551
 552 static int has_svm(void)
 553 {
 554         const char *msg;
 555
 556         if (!cpu_has_svm(&msg)) {
 557                 printk(KERN_INFO "has_svm: %s\n", msg);
 558                 return 0;
 559         }
 560
 561         return 1;
 562 }
 563
 564 static void svm_hardware_disable(void *garbage)
 565 {
 566         cpu_svm_disable();
 567 }
 568
 569 static int svm_hardware_enable(void *garbage)
 570 {
 571
 572         struct svm_cpu_data *sd;
 573         uint64_t efer;
 574         struct desc_ptr gdt_descr;
 575         struct desc_struct *gdt;
 576         int me = raw_smp_processor_id();
 577
 578         rdmsrl(MSR_EFER, efer);
 579         if (efer & EFER_SVME)
 580                 return -EBUSY;
 581
 582         if (!has_svm()) {
 583                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 584                        me);
 585                 return -EINVAL;
 586         }
 587         sd = per_cpu(svm_data, me);
 588
 589         if (!sd) {
 590                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 591                        me);
 592                 return -EINVAL;
 593         }
 594
 595         sd->asid_generation = 1;
 596         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 597         sd->next_asid = sd->max_asid + 1;
 598
 599         native_store_gdt(&gdt_descr);
 600         gdt = (struct desc_struct *)gdt_descr.address;
 601         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 602
 603         wrmsrl(MSR_EFER, efer | EFER_SVME);
 604
 605         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 606
 607         svm_init_erratum_383();
 608
 609         return 0;
 610 }
 611
 612 static void svm_cpu_uninit(int cpu)
 613 {
 614         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 615
 616         if (!sd)
 617                 return;
 618
 619         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 620         __free_page(sd->save_area);
 621         kfree(sd);
 622 }
 623
 624 static int svm_cpu_init(int cpu)
 625 {
 626         struct svm_cpu_data *sd;
 627         int r;
 628
 629         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 630         if (!sd)
 631                 return -ENOMEM;
 632         sd->cpu = cpu;
 633         sd->save_area = alloc_page(GFP_KERNEL);
 634         r = -ENOMEM;
 635         if (!sd->save_area)
 636                 goto err_1;
 637
 638         per_cpu(svm_data, cpu) = sd;
 639
 640         return 0;
 641
 642 err_1:
 643         kfree(sd);
 644         return r;
 645
 646 }
 647
 648 static bool valid_msr_intercept(u32 index)
 649 {
 650         int i;
 651
 652         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 653                 if (direct_access_msrs[i].index == index)
 654                         return true;
 655
 656         return false;
 657 }
 658
 659 static void set_msr_interception(u32 *msrpm, unsigned msr,
 660                                  int read, int write)
 661 {
 662         u8 bit_read, bit_write;
 663         unsigned long tmp;
 664         u32 offset;
 665
 666         /*
 667          * If this warning triggers extend the direct_access_msrs list at the
 668          * beginning of the file
 669          */
 670         WARN_ON(!valid_msr_intercept(msr));
 671
 672         offset    = svm_msrpm_offset(msr);
 673         bit_read  = 2 * (msr & 0x0f);
 674         bit_write = 2 * (msr & 0x0f) + 1;
 675         tmp       = msrpm[offset];
 676
 677         BUG_ON(offset == MSR_INVALID);
 678
 679         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 680         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 681
 682         msrpm[offset] = tmp;
 683 }
 684
 685 static void svm_vcpu_init_msrpm(u32 *msrpm)
 686 {
 687         int i;
 688
 689         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 690
 691         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 692                 if (!direct_access_msrs[i].always)
 693                         continue;
 694
 695                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 696         }
 697 }
 698
 699 static void add_msr_offset(u32 offset)
 700 {
 701         int i;
 702
 703         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 704
 705                 /* Offset already in list? */
 706                 if (msrpm_offsets[i] == offset)
 707                         return;
 708
 709                 /* Slot used by another offset? */
 710                 if (msrpm_offsets[i] != MSR_INVALID)
 711                         continue;
 712
 713                 /* Add offset to list */
 714                 msrpm_offsets[i] = offset;
 715
 716                 return;
 717         }
 718
 719         /*
 720          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 721          * increase MSRPM_OFFSETS in this case.
 722          */
 723         BUG();
 724 }
 725
 726 static void init_msrpm_offsets(void)
 727 {
 728         int i;
 729
 730         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 731
 732         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 733                 u32 offset;
 734
 735                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 736                 BUG_ON(offset == MSR_INVALID);
 737
 738                 add_msr_offset(offset);
 739         }
 740 }
 741
 742 static void svm_enable_lbrv(struct vcpu_svm *svm)
 743 {
 744         u32 *msrpm = svm->msrpm;
 745
 746         svm->vmcb->control.lbr_ctl = 1;
 747         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 748         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 749         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 750         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 751 }
 752
 753 static void svm_disable_lbrv(struct vcpu_svm *svm)
 754 {
 755         u32 *msrpm = svm->msrpm;
 756
 757         svm->vmcb->control.lbr_ctl = 0;
 758         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 759         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 760         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 761         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 762 }
 763
 764 static __init int svm_hardware_setup(void)
 765 {
 766         int cpu;
 767         struct page *iopm_pages;
 768         void *iopm_va;
 769         int r;
 770
 771         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 772
 773         if (!iopm_pages)
 774                 return -ENOMEM;
 775
 776         iopm_va = page_address(iopm_pages);
 777         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 778         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 779
 780         init_msrpm_offsets();
 781
 782         if (boot_cpu_has(X86_FEATURE_NX))
 783                 kvm_enable_efer_bits(EFER_NX);
 784
 785         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 786                 kvm_enable_efer_bits(EFER_FFXSR);
 787
 788         if (nested) {
 789                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 790                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 791         }
 792
 793         for_each_possible_cpu(cpu) {
 794                 r = svm_cpu_init(cpu);
 795                 if (r)
 796                         goto err;
 797         }
 798
 799         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 800
 801         if (!boot_cpu_has(X86_FEATURE_NPT))
 802                 npt_enabled = false;
 803
 804         if (npt_enabled && !npt) {
 805                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 806                 npt_enabled = false;
 807         }
 808
 809         if (npt_enabled) {
 810                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 811                 kvm_enable_tdp();
 812         } else
 813                 kvm_disable_tdp();
 814
 815         return 0;
 816
 817 err:
 818         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 819         iopm_base = 0;
 820         return r;
 821 }
 822
 823 static __exit void svm_hardware_unsetup(void)
 824 {
 825         int cpu;
 826
 827         for_each_possible_cpu(cpu)
 828                 svm_cpu_uninit(cpu);
 829
 830         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 831         iopm_base = 0;
 832 }
 833
 834 static void init_seg(struct vmcb_seg *seg)
 835 {
 836         seg->selector = 0;
 837         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 838                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 839         seg->limit = 0xffff;
 840         seg->base = 0;
 841 }
 842
 843 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 844 {
 845         seg->selector = 0;
 846         seg->attrib = SVM_SELECTOR_P_MASK | type;
 847         seg->limit = 0xffff;
 848         seg->base = 0;
 849 }
 850
 851 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
 852 {
 853         struct vcpu_svm *svm = to_svm(vcpu);
 854         u64 g_tsc_offset = 0;
 855
 856         if (is_guest_mode(vcpu)) {
 857                 g_tsc_offset = svm->vmcb->control.tsc_offset -
 858                                svm->nested.hsave->control.tsc_offset;
 859                 svm->nested.hsave->control.tsc_offset = offset;
 860         }
 861
 862         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
 863
 864         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 865 }
 866
 867 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
 868 {
 869         struct vcpu_svm *svm = to_svm(vcpu);
 870
 871         svm->vmcb->control.tsc_offset += adjustment;
 872         if (is_guest_mode(vcpu))
 873                 svm->nested.hsave->control.tsc_offset += adjustment;
 874         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 875 }
 876
 877 static void init_vmcb(struct vcpu_svm *svm)
 878 {
 879         struct vmcb_control_area *control = &svm->vmcb->control;
 880         struct vmcb_save_area *save = &svm->vmcb->save;
 881
 882         svm->vcpu.fpu_active = 1;
 883         svm->vcpu.arch.hflags = 0;
 884
 885         set_cr_intercept(svm, INTERCEPT_CR0_READ);
 886         set_cr_intercept(svm, INTERCEPT_CR3_READ);
 887         set_cr_intercept(svm, INTERCEPT_CR4_READ);
 888         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
 889         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
 890         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
 891         set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
 892
 893         set_dr_intercept(svm, INTERCEPT_DR0_READ);
 894         set_dr_intercept(svm, INTERCEPT_DR1_READ);
 895         set_dr_intercept(svm, INTERCEPT_DR2_READ);
 896         set_dr_intercept(svm, INTERCEPT_DR3_READ);
 897         set_dr_intercept(svm, INTERCEPT_DR4_READ);
 898         set_dr_intercept(svm, INTERCEPT_DR5_READ);
 899         set_dr_intercept(svm, INTERCEPT_DR6_READ);
 900         set_dr_intercept(svm, INTERCEPT_DR7_READ);
 901
 902         set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
 903         set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
 904         set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
 905         set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
 906         set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
 907         set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
 908         set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
 909         set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
 910
 911         set_exception_intercept(svm, PF_VECTOR);
 912         set_exception_intercept(svm, UD_VECTOR);
 913         set_exception_intercept(svm, MC_VECTOR);
 914
 915         set_intercept(svm, INTERCEPT_INTR);
 916         set_intercept(svm, INTERCEPT_NMI);
 917         set_intercept(svm, INTERCEPT_SMI);
 918         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
 919         set_intercept(svm, INTERCEPT_CPUID);
 920         set_intercept(svm, INTERCEPT_INVD);
 921         set_intercept(svm, INTERCEPT_HLT);
 922         set_intercept(svm, INTERCEPT_INVLPG);
 923         set_intercept(svm, INTERCEPT_INVLPGA);
 924         set_intercept(svm, INTERCEPT_IOIO_PROT);
 925         set_intercept(svm, INTERCEPT_MSR_PROT);
 926         set_intercept(svm, INTERCEPT_TASK_SWITCH);
 927         set_intercept(svm, INTERCEPT_SHUTDOWN);
 928         set_intercept(svm, INTERCEPT_VMRUN);
 929         set_intercept(svm, INTERCEPT_VMMCALL);
 930         set_intercept(svm, INTERCEPT_VMLOAD);
 931         set_intercept(svm, INTERCEPT_VMSAVE);
 932         set_intercept(svm, INTERCEPT_STGI);
 933         set_intercept(svm, INTERCEPT_CLGI);
 934         set_intercept(svm, INTERCEPT_SKINIT);
 935         set_intercept(svm, INTERCEPT_WBINVD);
 936         set_intercept(svm, INTERCEPT_MONITOR);
 937         set_intercept(svm, INTERCEPT_MWAIT);
 938
 939         control->iopm_base_pa = iopm_base;
 940         control->msrpm_base_pa = __pa(svm->msrpm);
 941         control->int_ctl = V_INTR_MASKING_MASK;
 942
 943         init_seg(&save->es);
 944         init_seg(&save->ss);
 945         init_seg(&save->ds);
 946         init_seg(&save->fs);
 947         init_seg(&save->gs);
 948
 949         save->cs.selector = 0xf000;
 950         /* Executable/Readable Code Segment */
 951         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 952                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 953         save->cs.limit = 0xffff;
 954         /*
 955          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 956          * be consistent with it.
 957          *
 958          * Replace when we have real mode working for vmx.
 959          */
 960         save->cs.base = 0xf0000;
 961
 962         save->gdtr.limit = 0xffff;
 963         save->idtr.limit = 0xffff;
 964
 965         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 966         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 967
 968         svm_set_efer(&svm->vcpu, 0);
 969         save->dr6 = 0xffff0ff0;
 970         save->dr7 = 0x400;
 971         save->rflags = 2;
 972         save->rip = 0x0000fff0;
 973         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 974
 975         /*
 976          * This is the guest-visible cr0 value.
 977          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
 978          */
 979         svm->vcpu.arch.cr0 = 0;
 980         (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
 981
 982         save->cr4 = X86_CR4_PAE;
 983         /* rdx = ?? */
 984
 985         if (npt_enabled) {
 986                 /* Setup VMCB for Nested Paging */
 987                 control->nested_ctl = 1;
 988                 clr_intercept(svm, INTERCEPT_TASK_SWITCH);
 989                 clr_intercept(svm, INTERCEPT_INVLPG);
 990                 clr_exception_intercept(svm, PF_VECTOR);
 991                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
 992                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
 993                 save->g_pat = 0x0007040600070406ULL;
 994                 save->cr3 = 0;
 995                 save->cr4 = 0;
 996         }
 997         force_new_asid(&svm->vcpu);
 998
 999         svm->nested.vmcb = 0;
1000         svm->vcpu.arch.hflags = 0;
1001
1002         if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1003                 control->pause_filter_count = 3000;
1004                 set_intercept(svm, INTERCEPT_PAUSE);
1005         }
1006
1007         mark_all_dirty(svm->vmcb);
1008
1009         enable_gif(svm);
1010 }
1011
1012 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
1013 {
1014         struct vcpu_svm *svm = to_svm(vcpu);
1015
1016         init_vmcb(svm);
1017
1018         if (!kvm_vcpu_is_bsp(vcpu)) {
1019                 kvm_rip_write(vcpu, 0);
1020                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1021                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
1022         }
1023         vcpu->arch.regs_avail = ~0;
1024         vcpu->arch.regs_dirty = ~0;
1025
1026         return 0;
1027 }
1028
1029 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1030 {
1031         struct vcpu_svm *svm;
1032         struct page *page;
1033         struct page *msrpm_pages;
1034         struct page *hsave_page;
1035         struct page *nested_msrpm_pages;
1036         int err;
1037
1038         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1039         if (!svm) {
1040                 err = -ENOMEM;
1041                 goto out;
1042         }
1043
1044         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1045         if (err)
1046                 goto free_svm;
1047
1048         err = -ENOMEM;
1049         page = alloc_page(GFP_KERNEL);
1050         if (!page)
1051                 goto uninit;
1052
1053         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1054         if (!msrpm_pages)
1055                 goto free_page1;
1056
1057         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1058         if (!nested_msrpm_pages)
1059                 goto free_page2;
1060
1061         hsave_page = alloc_page(GFP_KERNEL);
1062         if (!hsave_page)
1063                 goto free_page3;
1064
1065         svm->nested.hsave = page_address(hsave_page);
1066
1067         svm->msrpm = page_address(msrpm_pages);
1068         svm_vcpu_init_msrpm(svm->msrpm);
1069
1070         svm->nested.msrpm = page_address(nested_msrpm_pages);
1071         svm_vcpu_init_msrpm(svm->nested.msrpm);
1072
1073         svm->vmcb = page_address(page);
1074         clear_page(svm->vmcb);
1075         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1076         svm->asid_generation = 0;
1077         init_vmcb(svm);
1078         kvm_write_tsc(&svm->vcpu, 0);
1079
1080         err = fx_init(&svm->vcpu);
1081         if (err)
1082                 goto free_page4;
1083
1084         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1085         if (kvm_vcpu_is_bsp(&svm->vcpu))
1086                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1087
1088         return &svm->vcpu;
1089
1090 free_page4:
1091         __free_page(hsave_page);
1092 free_page3:
1093         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1094 free_page2:
1095         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1096 free_page1:
1097         __free_page(page);
1098 uninit:
1099         kvm_vcpu_uninit(&svm->vcpu);
1100 free_svm:
1101         kmem_cache_free(kvm_vcpu_cache, svm);
1102 out:
1103         return ERR_PTR(err);
1104 }
1105
1106 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1107 {
1108         struct vcpu_svm *svm = to_svm(vcpu);
1109
1110         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1111         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1112         __free_page(virt_to_page(svm->nested.hsave));
1113         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1114         kvm_vcpu_uninit(vcpu);
1115         kmem_cache_free(kvm_vcpu_cache, svm);
1116 }
1117
1118 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1119 {
1120         struct vcpu_svm *svm = to_svm(vcpu);
1121         int i;
1122
1123         if (unlikely(cpu != vcpu->cpu)) {
1124                 svm->asid_generation = 0;
1125                 mark_all_dirty(svm->vmcb);
1126         }
1127
1128 #ifdef CONFIG_X86_64
1129         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1130 #endif
1131         savesegment(fs, svm->host.fs);
1132         savesegment(gs, svm->host.gs);
1133         svm->host.ldt = kvm_read_ldt();
1134
1135         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1136                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1137 }
1138
1139 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1140 {
1141         struct vcpu_svm *svm = to_svm(vcpu);
1142         int i;
1143
1144         ++vcpu->stat.host_state_reload;
1145         kvm_load_ldt(svm->host.ldt);
1146 #ifdef CONFIG_X86_64
1147         loadsegment(fs, svm->host.fs);
1148         load_gs_index(svm->host.gs);
1149         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1150 #else
1151         loadsegment(gs, svm->host.gs);
1152 #endif
1153         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1154                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1155 }
1156
1157 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1158 {
1159         return to_svm(vcpu)->vmcb->save.rflags;
1160 }
1161
1162 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1163 {
1164         to_svm(vcpu)->vmcb->save.rflags = rflags;
1165 }
1166
1167 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1168 {
1169         switch (reg) {
1170         case VCPU_EXREG_PDPTR:
1171                 BUG_ON(!npt_enabled);
1172                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
1173                 break;
1174         default:
1175                 BUG();
1176         }
1177 }
1178
1179 static void svm_set_vintr(struct vcpu_svm *svm)
1180 {
1181         set_intercept(svm, INTERCEPT_VINTR);
1182 }
1183
1184 static void svm_clear_vintr(struct vcpu_svm *svm)
1185 {
1186         clr_intercept(svm, INTERCEPT_VINTR);
1187 }
1188
1189 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1190 {
1191         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1192
1193         switch (seg) {
1194         case VCPU_SREG_CS: return &save->cs;
1195         case VCPU_SREG_DS: return &save->ds;
1196         case VCPU_SREG_ES: return &save->es;
1197         case VCPU_SREG_FS: return &save->fs;
1198         case VCPU_SREG_GS: return &save->gs;
1199         case VCPU_SREG_SS: return &save->ss;
1200         case VCPU_SREG_TR: return &save->tr;
1201         case VCPU_SREG_LDTR: return &save->ldtr;
1202         }
1203         BUG();
1204         return NULL;
1205 }
1206
1207 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1208 {
1209         struct vmcb_seg *s = svm_seg(vcpu, seg);
1210
1211         return s->base;
1212 }
1213
1214 static void svm_get_segment(struct kvm_vcpu *vcpu,
1215                             struct kvm_segment *var, int seg)
1216 {
1217         struct vmcb_seg *s = svm_seg(vcpu, seg);
1218
1219         var->base = s->base;
1220         var->limit = s->limit;
1221         var->selector = s->selector;
1222         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1223         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1224         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1225         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1226         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1227         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1228         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1229         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1230
1231         /*
1232          * AMD's VMCB does not have an explicit unusable field, so emulate it
1233          * for cross vendor migration purposes by "not present"
1234          */
1235         var->unusable = !var->present || (var->type == 0);
1236
1237         switch (seg) {
1238         case VCPU_SREG_CS:
1239                 /*
1240                  * SVM always stores 0 for the 'G' bit in the CS selector in
1241                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1242                  * Intel's VMENTRY has a check on the 'G' bit.
1243                  */
1244                 var->g = s->limit > 0xfffff;
1245                 break;
1246         case VCPU_SREG_TR:
1247                 /*
1248                  * Work around a bug where the busy flag in the tr selector
1249                  * isn't exposed
1250                  */
1251                 var->type |= 0x2;
1252                 break;
1253         case VCPU_SREG_DS:
1254         case VCPU_SREG_ES:
1255         case VCPU_SREG_FS:
1256         case VCPU_SREG_GS:
1257                 /*
1258                  * The accessed bit must always be set in the segment
1259                  * descriptor cache, although it can be cleared in the
1260                  * descriptor, the cached bit always remains at 1. Since
1261                  * Intel has a check on this, set it here to support
1262                  * cross-vendor migration.
1263                  */
1264                 if (!var->unusable)
1265                         var->type |= 0x1;
1266                 break;
1267         case VCPU_SREG_SS:
1268                 /*
1269                  * On AMD CPUs sometimes the DB bit in the segment
1270                  * descriptor is left as 1, although the whole segment has
1271                  * been made unusable. Clear it here to pass an Intel VMX
1272                  * entry check when cross vendor migrating.
1273                  */
1274                 if (var->unusable)
1275                         var->db = 0;
1276                 break;
1277         }
1278 }
1279
1280 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1281 {
1282         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1283
1284         return save->cpl;
1285 }
1286
1287 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1288 {
1289         struct vcpu_svm *svm = to_svm(vcpu);
1290
1291         dt->size = svm->vmcb->save.idtr.limit;
1292         dt->address = svm->vmcb->save.idtr.base;
1293 }
1294
1295 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1296 {
1297         struct vcpu_svm *svm = to_svm(vcpu);
1298
1299         svm->vmcb->save.idtr.limit = dt->size;
1300         svm->vmcb->save.idtr.base = dt->address ;
1301 }
1302
1303 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1304 {
1305         struct vcpu_svm *svm = to_svm(vcpu);
1306
1307         dt->size = svm->vmcb->save.gdtr.limit;
1308         dt->address = svm->vmcb->save.gdtr.base;
1309 }
1310
1311 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1312 {
1313         struct vcpu_svm *svm = to_svm(vcpu);
1314
1315         svm->vmcb->save.gdtr.limit = dt->size;
1316         svm->vmcb->save.gdtr.base = dt->address ;
1317 }
1318
1319 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1320 {
1321 }
1322
1323 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1324 {
1325 }
1326
1327 static void update_cr0_intercept(struct vcpu_svm *svm)
1328 {
1329         ulong gcr0 = svm->vcpu.arch.cr0;
1330         u64 *hcr0 = &svm->vmcb->save.cr0;
1331
1332         if (!svm->vcpu.fpu_active)
1333                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1334         else
1335                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1336                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1337
1338
1339         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1340                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1341                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1342         } else {
1343                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1344                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1345         }
1346 }
1347
1348 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1349 {
1350         struct vcpu_svm *svm = to_svm(vcpu);
1351
1352         if (is_guest_mode(vcpu)) {
1353                 /*
1354                  * We are here because we run in nested mode, the host kvm
1355                  * intercepts cr0 writes but the l1 hypervisor does not.
1356                  * But the L1 hypervisor may intercept selective cr0 writes.
1357                  * This needs to be checked here.
1358                  */
1359                 unsigned long old, new;
1360
1361                 /* Remove bits that would trigger a real cr0 write intercept */
1362                 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1363                 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1364
1365                 if (old == new) {
1366                         /* cr0 write with ts and mp unchanged */
1367                         svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1368                         if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1369                                 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1370                                 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1371                                 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
1372                                 return;
1373                         }
1374                 }
1375         }
1376
1377 #ifdef CONFIG_X86_64
1378         if (vcpu->arch.efer & EFER_LME) {
1379                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1380                         vcpu->arch.efer |= EFER_LMA;
1381                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1382                 }
1383
1384                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1385                         vcpu->arch.efer &= ~EFER_LMA;
1386                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1387                 }
1388         }
1389 #endif
1390         vcpu->arch.cr0 = cr0;
1391
1392         if (!npt_enabled)
1393                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1394
1395         if (!vcpu->fpu_active)
1396                 cr0 |= X86_CR0_TS;
1397         /*
1398          * re-enable caching here because the QEMU bios
1399          * does not do it - this results in some delay at
1400          * reboot
1401          */
1402         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1403         svm->vmcb->save.cr0 = cr0;
1404         update_cr0_intercept(svm);
1405 }
1406
1407 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1408 {
1409         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1410         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1411
1412         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1413                 force_new_asid(vcpu);
1414
1415         vcpu->arch.cr4 = cr4;
1416         if (!npt_enabled)
1417                 cr4 |= X86_CR4_PAE;
1418         cr4 |= host_cr4_mce;
1419         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1420 }
1421
1422 static void svm_set_segment(struct kvm_vcpu *vcpu,
1423                             struct kvm_segment *var, int seg)
1424 {
1425         struct vcpu_svm *svm = to_svm(vcpu);
1426         struct vmcb_seg *s = svm_seg(vcpu, seg);
1427
1428         s->base = var->base;
1429         s->limit = var->limit;
1430         s->selector = var->selector;
1431         if (var->unusable)
1432                 s->attrib = 0;
1433         else {
1434                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1435                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1436                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1437                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1438                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1439                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1440                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1441                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1442         }
1443         if (seg == VCPU_SREG_CS)
1444                 svm->vmcb->save.cpl
1445                         = (svm->vmcb->save.cs.attrib
1446                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1447
1448 }
1449
1450 static void update_db_intercept(struct kvm_vcpu *vcpu)
1451 {
1452         struct vcpu_svm *svm = to_svm(vcpu);
1453
1454         clr_exception_intercept(svm, DB_VECTOR);
1455         clr_exception_intercept(svm, BP_VECTOR);
1456
1457         if (svm->nmi_singlestep)
1458                 set_exception_intercept(svm, DB_VECTOR);
1459
1460         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1461                 if (vcpu->guest_debug &
1462                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1463                         set_exception_intercept(svm, DB_VECTOR);
1464                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1465                         set_exception_intercept(svm, BP_VECTOR);
1466         } else
1467                 vcpu->guest_debug = 0;
1468 }
1469
1470 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1471 {
1472         struct vcpu_svm *svm = to_svm(vcpu);
1473
1474         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1475                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1476         else
1477                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1478
1479         update_db_intercept(vcpu);
1480 }
1481
1482 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1483 {
1484         if (sd->next_asid > sd->max_asid) {
1485                 ++sd->asid_generation;
1486                 sd->next_asid = 1;
1487                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1488         }
1489
1490         svm->asid_generation = sd->asid_generation;
1491         svm->vmcb->control.asid = sd->next_asid++;
1492
1493         mark_dirty(svm->vmcb, VMCB_ASID);
1494 }
1495
1496 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1497 {
1498         struct vcpu_svm *svm = to_svm(vcpu);
1499
1500         svm->vmcb->save.dr7 = value;
1501 }
1502
1503 static int pf_interception(struct vcpu_svm *svm)
1504 {
1505         u64 fault_address = svm->vmcb->control.exit_info_2;
1506         u32 error_code;
1507         int r = 1;
1508
1509         switch (svm->apf_reason) {
1510         default:
1511                 error_code = svm->vmcb->control.exit_info_1;
1512
1513                 trace_kvm_page_fault(fault_address, error_code);
1514                 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1515                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1516                 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1517                 break;
1518         case KVM_PV_REASON_PAGE_NOT_PRESENT:
1519                 svm->apf_reason = 0;
1520                 local_irq_disable();
1521                 kvm_async_pf_task_wait(fault_address);
1522                 local_irq_enable();
1523                 break;
1524         case KVM_PV_REASON_PAGE_READY:
1525                 svm->apf_reason = 0;
1526                 local_irq_disable();
1527                 kvm_async_pf_task_wake(fault_address);
1528                 local_irq_enable();
1529                 break;
1530         }
1531         return r;
1532 }
1533
1534 static int db_interception(struct vcpu_svm *svm)
1535 {
1536         struct kvm_run *kvm_run = svm->vcpu.run;
1537
1538         if (!(svm->vcpu.guest_debug &
1539               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1540                 !svm->nmi_singlestep) {
1541                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1542                 return 1;
1543         }
1544
1545         if (svm->nmi_singlestep) {
1546                 svm->nmi_singlestep = false;
1547                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1548                         svm->vmcb->save.rflags &=
1549                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1550                 update_db_intercept(&svm->vcpu);
1551         }
1552
1553         if (svm->vcpu.guest_debug &
1554             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1555                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1556                 kvm_run->debug.arch.pc =
1557                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1558                 kvm_run->debug.arch.exception = DB_VECTOR;
1559                 return 0;
1560         }
1561
1562         return 1;
1563 }
1564
1565 static int bp_interception(struct vcpu_svm *svm)
1566 {
1567         struct kvm_run *kvm_run = svm->vcpu.run;
1568
1569         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1570         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1571         kvm_run->debug.arch.exception = BP_VECTOR;
1572         return 0;
1573 }
1574
1575 static int ud_interception(struct vcpu_svm *svm)
1576 {
1577         int er;
1578
1579         er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1580         if (er != EMULATE_DONE)
1581                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1582         return 1;
1583 }
1584
1585 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1586 {
1587         struct vcpu_svm *svm = to_svm(vcpu);
1588
1589         clr_exception_intercept(svm, NM_VECTOR);
1590
1591         svm->vcpu.fpu_active = 1;
1592         update_cr0_intercept(svm);
1593 }
1594
1595 static int nm_interception(struct vcpu_svm *svm)
1596 {
1597         svm_fpu_activate(&svm->vcpu);
1598         return 1;
1599 }
1600
1601 static bool is_erratum_383(void)
1602 {
1603         int err, i;
1604         u64 value;
1605
1606         if (!erratum_383_found)
1607                 return false;
1608
1609         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1610         if (err)
1611                 return false;
1612
1613         /* Bit 62 may or may not be set for this mce */
1614         value &= ~(1ULL << 62);
1615
1616         if (value != 0xb600000000010015ULL)
1617                 return false;
1618
1619         /* Clear MCi_STATUS registers */
1620         for (i = 0; i < 6; ++i)
1621                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1622
1623         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1624         if (!err) {
1625                 u32 low, high;
1626
1627                 value &= ~(1ULL << 2);
1628                 low    = lower_32_bits(value);
1629                 high   = upper_32_bits(value);
1630
1631                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1632         }
1633
1634         /* Flush tlb to evict multi-match entries */
1635         __flush_tlb_all();
1636
1637         return true;
1638 }
1639
1640 static void svm_handle_mce(struct vcpu_svm *svm)
1641 {
1642         if (is_erratum_383()) {
1643                 /*
1644                  * Erratum 383 triggered. Guest state is corrupt so kill the
1645                  * guest.
1646                  */
1647                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1648
1649                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1650
1651                 return;
1652         }
1653
1654         /*
1655          * On an #MC intercept the MCE handler is not called automatically in
1656          * the host. So do it by hand here.
1657          */
1658         asm volatile (
1659                 "int $0x12\n");
1660         /* not sure if we ever come back to this point */
1661
1662         return;
1663 }
1664
1665 static int mc_interception(struct vcpu_svm *svm)
1666 {
1667         return 1;
1668 }
1669
1670 static int shutdown_interception(struct vcpu_svm *svm)
1671 {
1672         struct kvm_run *kvm_run = svm->vcpu.run;
1673
1674         /*
1675          * VMCB is undefined after a SHUTDOWN intercept
1676          * so reinitialize it.
1677          */
1678         clear_page(svm->vmcb);
1679         init_vmcb(svm);
1680
1681         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1682         return 0;
1683 }
1684
1685 static int io_interception(struct vcpu_svm *svm)
1686 {
1687         struct kvm_vcpu *vcpu = &svm->vcpu;
1688         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1689         int size, in, string;
1690         unsigned port;
1691
1692         ++svm->vcpu.stat.io_exits;
1693         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1694         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1695         if (string || in)
1696                 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
1697
1698         port = io_info >> 16;
1699         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1700         svm->next_rip = svm->vmcb->control.exit_info_2;
1701         skip_emulated_instruction(&svm->vcpu);
1702
1703         return kvm_fast_pio_out(vcpu, size, port);
1704 }
1705
1706 static int nmi_interception(struct vcpu_svm *svm)
1707 {
1708         return 1;
1709 }
1710
1711 static int intr_interception(struct vcpu_svm *svm)
1712 {
1713         ++svm->vcpu.stat.irq_exits;
1714         return 1;
1715 }
1716
1717 static int nop_on_interception(struct vcpu_svm *svm)
1718 {
1719         return 1;
1720 }
1721
1722 static int halt_interception(struct vcpu_svm *svm)
1723 {
1724         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1725         skip_emulated_instruction(&svm->vcpu);
1726         return kvm_emulate_halt(&svm->vcpu);
1727 }
1728
1729 static int vmmcall_interception(struct vcpu_svm *svm)
1730 {
1731         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1732         skip_emulated_instruction(&svm->vcpu);
1733         kvm_emulate_hypercall(&svm->vcpu);
1734         return 1;
1735 }
1736
1737 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1738 {
1739         struct vcpu_svm *svm = to_svm(vcpu);
1740
1741         return svm->nested.nested_cr3;
1742 }
1743
1744 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1745                                    unsigned long root)
1746 {
1747         struct vcpu_svm *svm = to_svm(vcpu);
1748
1749         svm->vmcb->control.nested_cr3 = root;
1750         force_new_asid(vcpu);
1751 }
1752
1753 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1754                                        struct x86_exception *fault)
1755 {
1756         struct vcpu_svm *svm = to_svm(vcpu);
1757
1758         svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1759         svm->vmcb->control.exit_code_hi = 0;
1760         svm->vmcb->control.exit_info_1 = fault->error_code;
1761         svm->vmcb->control.exit_info_2 = fault->address;
1762
1763         nested_svm_vmexit(svm);
1764 }
1765
1766 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1767 {
1768         int r;
1769
1770         r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1771
1772         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
1773         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
1774         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1775         vcpu->arch.mmu.shadow_root_level = get_npt_level();
1776         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
1777
1778         return r;
1779 }
1780
1781 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1782 {
1783         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1784 }
1785
1786 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1787 {
1788         if (!(svm->vcpu.arch.efer & EFER_SVME)
1789             || !is_paging(&svm->vcpu)) {
1790                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1791                 return 1;
1792         }
1793
1794         if (svm->vmcb->save.cpl) {
1795                 kvm_inject_gp(&svm->vcpu, 0);
1796                 return 1;
1797         }
1798
1799        return 0;
1800 }
1801
1802 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1803                                       bool has_error_code, u32 error_code)
1804 {
1805         int vmexit;
1806
1807         if (!is_guest_mode(&svm->vcpu))
1808                 return 0;
1809
1810         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1811         svm->vmcb->control.exit_code_hi = 0;
1812         svm->vmcb->control.exit_info_1 = error_code;
1813         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1814
1815         vmexit = nested_svm_intercept(svm);
1816         if (vmexit == NESTED_EXIT_DONE)
1817                 svm->nested.exit_required = true;
1818
1819         return vmexit;
1820 }
1821
1822 /* This function returns true if it is save to enable the irq window */
1823 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1824 {
1825         if (!is_guest_mode(&svm->vcpu))
1826                 return true;
1827
1828         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1829                 return true;
1830
1831         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1832                 return false;
1833
1834         /*
1835          * if vmexit was already requested (by intercepted exception
1836          * for instance) do not overwrite it with "external interrupt"
1837          * vmexit.
1838          */
1839         if (svm->nested.exit_required)
1840                 return false;
1841
1842         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
1843         svm->vmcb->control.exit_info_1 = 0;
1844         svm->vmcb->control.exit_info_2 = 0;
1845
1846         if (svm->nested.intercept & 1ULL) {
1847                 /*
1848                  * The #vmexit can't be emulated here directly because this
1849                  * code path runs with irqs and preemtion disabled. A
1850                  * #vmexit emulation might sleep. Only signal request for
1851                  * the #vmexit here.
1852                  */
1853                 svm->nested.exit_required = true;
1854                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1855                 return false;
1856         }
1857
1858         return true;
1859 }
1860
1861 /* This function returns true if it is save to enable the nmi window */
1862 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1863 {
1864         if (!is_guest_mode(&svm->vcpu))
1865                 return true;
1866
1867         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1868                 return true;
1869
1870         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1871         svm->nested.exit_required = true;
1872
1873         return false;
1874 }
1875
1876 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1877 {
1878         struct page *page;
1879
1880         might_sleep();
1881
1882         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1883         if (is_error_page(page))
1884                 goto error;
1885
1886         *_page = page;
1887
1888         return kmap(page);
1889
1890 error:
1891         kvm_release_page_clean(page);
1892         kvm_inject_gp(&svm->vcpu, 0);
1893
1894         return NULL;
1895 }
1896
1897 static void nested_svm_unmap(struct page *page)
1898 {
1899         kunmap(page);
1900         kvm_release_page_dirty(page);
1901 }
1902
1903 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1904 {
1905         unsigned port;
1906         u8 val, bit;
1907         u64 gpa;
1908
1909         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1910                 return NESTED_EXIT_HOST;
1911
1912         port = svm->vmcb->control.exit_info_1 >> 16;
1913         gpa  = svm->nested.vmcb_iopm + (port / 8);
1914         bit  = port % 8;
1915         val  = 0;
1916
1917         if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1918                 val &= (1 << bit);
1919
1920         return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1921 }
1922
1923 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1924 {
1925         u32 offset, msr, value;
1926         int write, mask;
1927
1928         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1929                 return NESTED_EXIT_HOST;
1930
1931         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1932         offset = svm_msrpm_offset(msr);
1933         write  = svm->vmcb->control.exit_info_1 & 1;
1934         mask   = 1 << ((2 * (msr & 0xf)) + write);
1935
1936         if (offset == MSR_INVALID)
1937                 return NESTED_EXIT_DONE;
1938
1939         /* Offset is in 32 bit units but need in 8 bit units */
1940         offset *= 4;
1941
1942         if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1943                 return NESTED_EXIT_DONE;
1944
1945         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1946 }
1947
1948 static int nested_svm_exit_special(struct vcpu_svm *svm)
1949 {
1950         u32 exit_code = svm->vmcb->control.exit_code;
1951
1952         switch (exit_code) {
1953         case SVM_EXIT_INTR:
1954         case SVM_EXIT_NMI:
1955         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1956                 return NESTED_EXIT_HOST;
1957         case SVM_EXIT_NPF:
1958                 /* For now we are always handling NPFs when using them */
1959                 if (npt_enabled)
1960                         return NESTED_EXIT_HOST;
1961                 break;
1962         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1963                 /* When we're shadowing, trap PFs, but not async PF */
1964                 if (!npt_enabled && svm->apf_reason == 0)
1965                         return NESTED_EXIT_HOST;
1966                 break;
1967         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1968                 nm_interception(svm);
1969                 break;
1970         default:
1971                 break;
1972         }
1973
1974         return NESTED_EXIT_CONTINUE;
1975 }
1976
1977 /*
1978  * If this function returns true, this #vmexit was already handled
1979  */
1980 static int nested_svm_intercept(struct vcpu_svm *svm)
1981 {
1982         u32 exit_code = svm->vmcb->control.exit_code;
1983         int vmexit = NESTED_EXIT_HOST;
1984
1985         switch (exit_code) {
1986         case SVM_EXIT_MSR:
1987                 vmexit = nested_svm_exit_handled_msr(svm);
1988                 break;
1989         case SVM_EXIT_IOIO:
1990                 vmexit = nested_svm_intercept_ioio(svm);
1991                 break;
1992         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
1993                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
1994                 if (svm->nested.intercept_cr & bit)
1995                         vmexit = NESTED_EXIT_DONE;
1996                 break;
1997         }
1998         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
1999                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2000                 if (svm->nested.intercept_dr & bit)
2001                         vmexit = NESTED_EXIT_DONE;
2002                 break;
2003         }
2004         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2005                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2006                 if (svm->nested.intercept_exceptions & excp_bits)
2007                         vmexit = NESTED_EXIT_DONE;
2008                 /* async page fault always cause vmexit */
2009                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2010                          svm->apf_reason != 0)
2011                         vmexit = NESTED_EXIT_DONE;
2012                 break;
2013         }
2014         case SVM_EXIT_ERR: {
2015                 vmexit = NESTED_EXIT_DONE;
2016                 break;
2017         }
2018         default: {
2019                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2020                 if (svm->nested.intercept & exit_bits)
2021                         vmexit = NESTED_EXIT_DONE;
2022         }
2023         }
2024
2025         return vmexit;
2026 }
2027
2028 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2029 {
2030         int vmexit;
2031
2032         vmexit = nested_svm_intercept(svm);
2033
2034         if (vmexit == NESTED_EXIT_DONE)
2035                 nested_svm_vmexit(svm);
2036
2037         return vmexit;
2038 }
2039
2040 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2041 {
2042         struct vmcb_control_area *dst  = &dst_vmcb->control;
2043         struct vmcb_control_area *from = &from_vmcb->control;
2044
2045         dst->intercept_cr         = from->intercept_cr;
2046         dst->intercept_dr         = from->intercept_dr;
2047         dst->intercept_exceptions = from->intercept_exceptions;
2048         dst->intercept            = from->intercept;
2049         dst->iopm_base_pa         = from->iopm_base_pa;
2050         dst->msrpm_base_pa        = from->msrpm_base_pa;
2051         dst->tsc_offset           = from->tsc_offset;
2052         dst->asid                 = from->asid;
2053         dst->tlb_ctl              = from->tlb_ctl;
2054         dst->int_ctl              = from->int_ctl;
2055         dst->int_vector           = from->int_vector;
2056         dst->int_state            = from->int_state;
2057         dst->exit_code            = from->exit_code;
2058         dst->exit_code_hi         = from->exit_code_hi;
2059         dst->exit_info_1          = from->exit_info_1;
2060         dst->exit_info_2          = from->exit_info_2;
2061         dst->exit_int_info        = from->exit_int_info;
2062         dst->exit_int_info_err    = from->exit_int_info_err;
2063         dst->nested_ctl           = from->nested_ctl;
2064         dst->event_inj            = from->event_inj;
2065         dst->event_inj_err        = from->event_inj_err;
2066         dst->nested_cr3           = from->nested_cr3;
2067         dst->lbr_ctl              = from->lbr_ctl;
2068 }
2069
2070 static int nested_svm_vmexit(struct vcpu_svm *svm)
2071 {
2072         struct vmcb *nested_vmcb;
2073         struct vmcb *hsave = svm->nested.hsave;
2074         struct vmcb *vmcb = svm->vmcb;
2075         struct page *page;
2076
2077         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2078                                        vmcb->control.exit_info_1,
2079                                        vmcb->control.exit_info_2,
2080                                        vmcb->control.exit_int_info,
2081                                        vmcb->control.exit_int_info_err);
2082
2083         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2084         if (!nested_vmcb)
2085                 return 1;
2086
2087         /* Exit Guest-Mode */
2088         leave_guest_mode(&svm->vcpu);
2089         svm->nested.vmcb = 0;
2090
2091         /* Give the current vmcb to the guest */
2092         disable_gif(svm);
2093
2094         nested_vmcb->save.es     = vmcb->save.es;
2095         nested_vmcb->save.cs     = vmcb->save.cs;
2096         nested_vmcb->save.ss     = vmcb->save.ss;
2097         nested_vmcb->save.ds     = vmcb->save.ds;
2098         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
2099         nested_vmcb->save.idtr   = vmcb->save.idtr;
2100         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
2101         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
2102         nested_vmcb->save.cr3    = svm->vcpu.arch.cr3;
2103         nested_vmcb->save.cr2    = vmcb->save.cr2;
2104         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
2105         nested_vmcb->save.rflags = vmcb->save.rflags;
2106         nested_vmcb->save.rip    = vmcb->save.rip;
2107         nested_vmcb->save.rsp    = vmcb->save.rsp;
2108         nested_vmcb->save.rax    = vmcb->save.rax;
2109         nested_vmcb->save.dr7    = vmcb->save.dr7;
2110         nested_vmcb->save.dr6    = vmcb->save.dr6;
2111         nested_vmcb->save.cpl    = vmcb->save.cpl;
2112
2113         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
2114         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
2115         nested_vmcb->control.int_state         = vmcb->control.int_state;
2116         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
2117         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
2118         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
2119         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
2120         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
2121         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2122         nested_vmcb->control.next_rip          = vmcb->control.next_rip;
2123
2124         /*
2125          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2126          * to make sure that we do not lose injected events. So check event_inj
2127          * here and copy it to exit_int_info if it is valid.
2128          * Exit_int_info and event_inj can't be both valid because the case
2129          * below only happens on a VMRUN instruction intercept which has
2130          * no valid exit_int_info set.
2131          */
2132         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2133                 struct vmcb_control_area *nc = &nested_vmcb->control;
2134
2135                 nc->exit_int_info     = vmcb->control.event_inj;
2136                 nc->exit_int_info_err = vmcb->control.event_inj_err;
2137         }
2138
2139         nested_vmcb->control.tlb_ctl           = 0;
2140         nested_vmcb->control.event_inj         = 0;
2141         nested_vmcb->control.event_inj_err     = 0;
2142
2143         /* We always set V_INTR_MASKING and remember the old value in hflags */
2144         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2145                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2146
2147         /* Restore the original control entries */
2148         copy_vmcb_control_area(vmcb, hsave);
2149
2150         kvm_clear_exception_queue(&svm->vcpu);
2151         kvm_clear_interrupt_queue(&svm->vcpu);
2152
2153         svm->nested.nested_cr3 = 0;
2154
2155         /* Restore selected save entries */
2156         svm->vmcb->save.es = hsave->save.es;
2157         svm->vmcb->save.cs = hsave->save.cs;
2158         svm->vmcb->save.ss = hsave->save.ss;
2159         svm->vmcb->save.ds = hsave->save.ds;
2160         svm->vmcb->save.gdtr = hsave->save.gdtr;
2161         svm->vmcb->save.idtr = hsave->save.idtr;
2162         svm->vmcb->save.rflags = hsave->save.rflags;
2163         svm_set_efer(&svm->vcpu, hsave->save.efer);
2164         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2165         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2166         if (npt_enabled) {
2167                 svm->vmcb->save.cr3 = hsave->save.cr3;
2168                 svm->vcpu.arch.cr3 = hsave->save.cr3;
2169         } else {
2170                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2171         }
2172         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2173         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2174         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2175         svm->vmcb->save.dr7 = 0;
2176         svm->vmcb->save.cpl = 0;
2177         svm->vmcb->control.exit_int_info = 0;
2178
2179         mark_all_dirty(svm->vmcb);
2180
2181         nested_svm_unmap(page);
2182
2183         nested_svm_uninit_mmu_context(&svm->vcpu);
2184         kvm_mmu_reset_context(&svm->vcpu);
2185         kvm_mmu_load(&svm->vcpu);
2186
2187         return 0;
2188 }
2189
2190 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2191 {
2192         /*
2193          * This function merges the msr permission bitmaps of kvm and the
2194          * nested vmcb. It is omptimized in that it only merges the parts where
2195          * the kvm msr permission bitmap may contain zero bits
2196          */
2197         int i;
2198
2199         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2200                 return true;
2201
2202         for (i = 0; i < MSRPM_OFFSETS; i++) {
2203                 u32 value, p;
2204                 u64 offset;
2205
2206                 if (msrpm_offsets[i] == 0xffffffff)
2207                         break;
2208
2209                 p      = msrpm_offsets[i];
2210                 offset = svm->nested.vmcb_msrpm + (p * 4);
2211
2212                 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2213                         return false;
2214
2215                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2216         }
2217
2218         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2219
2220         return true;
2221 }
2222
2223 static bool nested_vmcb_checks(struct vmcb *vmcb)
2224 {
2225         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2226                 return false;
2227
2228         if (vmcb->control.asid == 0)
2229                 return false;
2230
2231         if (vmcb->control.nested_ctl && !npt_enabled)
2232                 return false;
2233
2234         return true;
2235 }
2236
2237 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2238 {
2239         struct vmcb *nested_vmcb;
2240         struct vmcb *hsave = svm->nested.hsave;
2241         struct vmcb *vmcb = svm->vmcb;
2242         struct page *page;
2243         u64 vmcb_gpa;
2244
2245         vmcb_gpa = svm->vmcb->save.rax;
2246
2247         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2248         if (!nested_vmcb)
2249                 return false;
2250
2251         if (!nested_vmcb_checks(nested_vmcb)) {
2252                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
2253                 nested_vmcb->control.exit_code_hi = 0;
2254                 nested_vmcb->control.exit_info_1  = 0;
2255                 nested_vmcb->control.exit_info_2  = 0;
2256
2257                 nested_svm_unmap(page);
2258
2259                 return false;
2260         }
2261
2262         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2263                                nested_vmcb->save.rip,
2264                                nested_vmcb->control.int_ctl,
2265                                nested_vmcb->control.event_inj,
2266                                nested_vmcb->control.nested_ctl);
2267
2268         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2269                                     nested_vmcb->control.intercept_cr >> 16,
2270                                     nested_vmcb->control.intercept_exceptions,
2271                                     nested_vmcb->control.intercept);
2272
2273         /* Clear internal status */
2274         kvm_clear_exception_queue(&svm->vcpu);
2275         kvm_clear_interrupt_queue(&svm->vcpu);
2276
2277         /*
2278          * Save the old vmcb, so we don't need to pick what we save, but can
2279          * restore everything when a VMEXIT occurs
2280          */
2281         hsave->save.es     = vmcb->save.es;
2282         hsave->save.cs     = vmcb->save.cs;
2283         hsave->save.ss     = vmcb->save.ss;
2284         hsave->save.ds     = vmcb->save.ds;
2285         hsave->save.gdtr   = vmcb->save.gdtr;
2286         hsave->save.idtr   = vmcb->save.idtr;
2287         hsave->save.efer   = svm->vcpu.arch.efer;
2288         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2289         hsave->save.cr4    = svm->vcpu.arch.cr4;
2290         hsave->save.rflags = vmcb->save.rflags;
2291         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
2292         hsave->save.rsp    = vmcb->save.rsp;
2293         hsave->save.rax    = vmcb->save.rax;
2294         if (npt_enabled)
2295                 hsave->save.cr3    = vmcb->save.cr3;
2296         else
2297                 hsave->save.cr3    = svm->vcpu.arch.cr3;
2298
2299         copy_vmcb_control_area(hsave, vmcb);
2300
2301         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2302                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2303         else
2304                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2305
2306         if (nested_vmcb->control.nested_ctl) {
2307                 kvm_mmu_unload(&svm->vcpu);
2308                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2309                 nested_svm_init_mmu_context(&svm->vcpu);
2310         }
2311
2312         /* Load the nested guest state */
2313         svm->vmcb->save.es = nested_vmcb->save.es;
2314         svm->vmcb->save.cs = nested_vmcb->save.cs;
2315         svm->vmcb->save.ss = nested_vmcb->save.ss;
2316         svm->vmcb->save.ds = nested_vmcb->save.ds;
2317         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2318         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2319         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2320         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2321         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2322         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2323         if (npt_enabled) {
2324                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2325                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2326         } else
2327                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2328
2329         /* Guest paging mode is active - reset mmu */
2330         kvm_mmu_reset_context(&svm->vcpu);
2331
2332         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2333         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2334         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2335         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2336
2337         /* In case we don't even reach vcpu_run, the fields are not updated */
2338         svm->vmcb->save.rax = nested_vmcb->save.rax;
2339         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2340         svm->vmcb->save.rip = nested_vmcb->save.rip;
2341         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2342         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2343         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2344
2345         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2346         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2347
2348         /* cache intercepts */
2349         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
2350         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
2351         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2352         svm->nested.intercept            = nested_vmcb->control.intercept;
2353
2354         force_new_asid(&svm->vcpu);
2355         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2356         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2357                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2358         else
2359                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2360
2361         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2362                 /* We only want the cr8 intercept bits of the guest */
2363                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2364                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2365         }
2366
2367         /* We don't want to see VMMCALLs from a nested guest */
2368         clr_intercept(svm, INTERCEPT_VMMCALL);
2369
2370         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2371         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2372         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2373         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2374         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2375         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2376
2377         nested_svm_unmap(page);
2378
2379         /* Enter Guest-Mode */
2380         enter_guest_mode(&svm->vcpu);
2381
2382         /*
2383          * Merge guest and host intercepts - must be called  with vcpu in
2384          * guest-mode to take affect here
2385          */
2386         recalc_intercepts(svm);
2387
2388         svm->nested.vmcb = vmcb_gpa;
2389
2390         enable_gif(svm);
2391
2392         mark_all_dirty(svm->vmcb);
2393
2394         return true;
2395 }
2396
2397 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2398 {
2399         to_vmcb->save.fs = from_vmcb->save.fs;
2400         to_vmcb->save.gs = from_vmcb->save.gs;
2401         to_vmcb->save.tr = from_vmcb->save.tr;
2402         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2403         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2404         to_vmcb->save.star = from_vmcb->save.star;
2405         to_vmcb->save.lstar = from_vmcb->save.lstar;
2406         to_vmcb->save.cstar = from_vmcb->save.cstar;
2407         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2408         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2409         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2410         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2411 }
2412
2413 static int vmload_interception(struct vcpu_svm *svm)
2414 {
2415         struct vmcb *nested_vmcb;
2416         struct page *page;
2417
2418         if (nested_svm_check_permissions(svm))
2419                 return 1;
2420
2421         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2422         skip_emulated_instruction(&svm->vcpu);
2423
2424         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2425         if (!nested_vmcb)
2426                 return 1;
2427
2428         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2429         nested_svm_unmap(page);
2430
2431         return 1;
2432 }
2433
2434 static int vmsave_interception(struct vcpu_svm *svm)
2435 {
2436         struct vmcb *nested_vmcb;
2437         struct page *page;
2438
2439         if (nested_svm_check_permissions(svm))
2440                 return 1;
2441
2442         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2443         skip_emulated_instruction(&svm->vcpu);
2444
2445         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2446         if (!nested_vmcb)
2447                 return 1;
2448
2449         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2450         nested_svm_unmap(page);
2451
2452         return 1;
2453 }
2454
2455 static int vmrun_interception(struct vcpu_svm *svm)
2456 {
2457         if (nested_svm_check_permissions(svm))
2458                 return 1;
2459
2460         /* Save rip after vmrun instruction */
2461         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2462
2463         if (!nested_svm_vmrun(svm))
2464                 return 1;
2465
2466         if (!nested_svm_vmrun_msrpm(svm))
2467                 goto failed;
2468
2469         return 1;
2470
2471 failed:
2472
2473         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
2474         svm->vmcb->control.exit_code_hi = 0;
2475         svm->vmcb->control.exit_info_1  = 0;
2476         svm->vmcb->control.exit_info_2  = 0;
2477
2478         nested_svm_vmexit(svm);
2479
2480         return 1;
2481 }
2482
2483 static int stgi_interception(struct vcpu_svm *svm)
2484 {
2485         if (nested_svm_check_permissions(svm))
2486                 return 1;
2487
2488         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2489         skip_emulated_instruction(&svm->vcpu);
2490         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2491
2492         enable_gif(svm);
2493
2494         return 1;
2495 }
2496
2497 static int clgi_interception(struct vcpu_svm *svm)
2498 {
2499         if (nested_svm_check_permissions(svm))
2500                 return 1;
2501
2502         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2503         skip_emulated_instruction(&svm->vcpu);
2504
2505         disable_gif(svm);
2506
2507         /* After a CLGI no interrupts should come */
2508         svm_clear_vintr(svm);
2509         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2510
2511         return 1;
2512 }
2513
2514 static int invlpga_interception(struct vcpu_svm *svm)
2515 {
2516         struct kvm_vcpu *vcpu = &svm->vcpu;
2517
2518         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2519                           vcpu->arch.regs[VCPU_REGS_RAX]);
2520
2521         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2522         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2523
2524         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2525         skip_emulated_instruction(&svm->vcpu);
2526         return 1;
2527 }
2528
2529 static int skinit_interception(struct vcpu_svm *svm)
2530 {
2531         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2532
2533         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2534         return 1;
2535 }
2536
2537 static int invalid_op_interception(struct vcpu_svm *svm)
2538 {
2539         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2540         return 1;
2541 }
2542
2543 static int task_switch_interception(struct vcpu_svm *svm)
2544 {
2545         u16 tss_selector;
2546         int reason;
2547         int int_type = svm->vmcb->control.exit_int_info &
2548                 SVM_EXITINTINFO_TYPE_MASK;
2549         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2550         uint32_t type =
2551                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2552         uint32_t idt_v =
2553                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2554         bool has_error_code = false;
2555         u32 error_code = 0;
2556
2557         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2558
2559         if (svm->vmcb->control.exit_info_2 &
2560             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2561                 reason = TASK_SWITCH_IRET;
2562         else if (svm->vmcb->control.exit_info_2 &
2563                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2564                 reason = TASK_SWITCH_JMP;
2565         else if (idt_v)
2566                 reason = TASK_SWITCH_GATE;
2567         else
2568                 reason = TASK_SWITCH_CALL;
2569
2570         if (reason == TASK_SWITCH_GATE) {
2571                 switch (type) {
2572                 case SVM_EXITINTINFO_TYPE_NMI:
2573                         svm->vcpu.arch.nmi_injected = false;
2574                         break;
2575                 case SVM_EXITINTINFO_TYPE_EXEPT:
2576                         if (svm->vmcb->control.exit_info_2 &
2577                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2578                                 has_error_code = true;
2579                                 error_code =
2580                                         (u32)svm->vmcb->control.exit_info_2;
2581                         }
2582                         kvm_clear_exception_queue(&svm->vcpu);
2583                         break;
2584                 case SVM_EXITINTINFO_TYPE_INTR:
2585                         kvm_clear_interrupt_queue(&svm->vcpu);
2586                         break;
2587                 default:
2588                         break;
2589                 }
2590         }
2591
2592         if (reason != TASK_SWITCH_GATE ||
2593             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2594             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2595              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2596                 skip_emulated_instruction(&svm->vcpu);
2597
2598         if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2599                                 has_error_code, error_code) == EMULATE_FAIL) {
2600                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2601                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2602                 svm->vcpu.run->internal.ndata = 0;
2603                 return 0;
2604         }
2605         return 1;
2606 }
2607
2608 static int cpuid_interception(struct vcpu_svm *svm)
2609 {
2610         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2611         kvm_emulate_cpuid(&svm->vcpu);
2612         return 1;
2613 }
2614
2615 static int iret_interception(struct vcpu_svm *svm)
2616 {
2617         ++svm->vcpu.stat.nmi_window_exits;
2618         clr_intercept(svm, INTERCEPT_IRET);
2619         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2620         return 1;
2621 }
2622
2623 static int invlpg_interception(struct vcpu_svm *svm)
2624 {
2625         return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2626 }
2627
2628 static int emulate_on_interception(struct vcpu_svm *svm)
2629 {
2630         return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2631 }
2632
2633 static int cr0_write_interception(struct vcpu_svm *svm)
2634 {
2635         struct kvm_vcpu *vcpu = &svm->vcpu;
2636         int r;
2637
2638         r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2639
2640         if (svm->nested.vmexit_rip) {
2641                 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2642                 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2643                 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2644                 svm->nested.vmexit_rip = 0;
2645         }
2646
2647         return r == EMULATE_DONE;
2648 }
2649
2650 static int cr8_write_interception(struct vcpu_svm *svm)
2651 {
2652         struct kvm_run *kvm_run = svm->vcpu.run;
2653
2654         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2655         /* instruction emulation calls kvm_set_cr8() */
2656         emulate_instruction(&svm->vcpu, 0, 0, 0);
2657         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2658                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2659                 return 1;
2660         }
2661         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2662                 return 1;
2663         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2664         return 0;
2665 }
2666
2667 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2668 {
2669         struct vcpu_svm *svm = to_svm(vcpu);
2670
2671         switch (ecx) {
2672         case MSR_IA32_TSC: {
2673                 struct vmcb *vmcb = get_host_vmcb(svm);
2674
2675                 *data = vmcb->control.tsc_offset + native_read_tsc();
2676                 break;
2677         }
2678         case MSR_STAR:
2679                 *data = svm->vmcb->save.star;
2680                 break;
2681 #ifdef CONFIG_X86_64
2682         case MSR_LSTAR:
2683                 *data = svm->vmcb->save.lstar;
2684                 break;
2685         case MSR_CSTAR:
2686                 *data = svm->vmcb->save.cstar;
2687                 break;
2688         case MSR_KERNEL_GS_BASE:
2689                 *data = svm->vmcb->save.kernel_gs_base;
2690                 break;
2691         case MSR_SYSCALL_MASK:
2692                 *data = svm->vmcb->save.sfmask;
2693                 break;
2694 #endif
2695         case MSR_IA32_SYSENTER_CS:
2696                 *data = svm->vmcb->save.sysenter_cs;
2697                 break;
2698         case MSR_IA32_SYSENTER_EIP:
2699                 *data = svm->sysenter_eip;
2700                 break;
2701         case MSR_IA32_SYSENTER_ESP:
2702                 *data = svm->sysenter_esp;
2703                 break;
2704         /*
2705          * Nobody will change the following 5 values in the VMCB so we can
2706          * safely return them on rdmsr. They will always be 0 until LBRV is
2707          * implemented.
2708          */
2709         case MSR_IA32_DEBUGCTLMSR:
2710                 *data = svm->vmcb->save.dbgctl;
2711                 break;
2712         case MSR_IA32_LASTBRANCHFROMIP:
2713                 *data = svm->vmcb->save.br_from;
2714                 break;
2715         case MSR_IA32_LASTBRANCHTOIP:
2716                 *data = svm->vmcb->save.br_to;
2717                 break;
2718         case MSR_IA32_LASTINTFROMIP:
2719                 *data = svm->vmcb->save.last_excp_from;
2720                 break;
2721         case MSR_IA32_LASTINTTOIP:
2722                 *data = svm->vmcb->save.last_excp_to;
2723                 break;
2724         case MSR_VM_HSAVE_PA:
2725                 *data = svm->nested.hsave_msr;
2726                 break;
2727         case MSR_VM_CR:
2728                 *data = svm->nested.vm_cr_msr;
2729                 break;
2730         case MSR_IA32_UCODE_REV:
2731                 *data = 0x01000065;
2732                 break;
2733         default:
2734                 return kvm_get_msr_common(vcpu, ecx, data);
2735         }
2736         return 0;
2737 }
2738
2739 static int rdmsr_interception(struct vcpu_svm *svm)
2740 {
2741         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2742         u64 data;
2743
2744         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2745                 trace_kvm_msr_read_ex(ecx);
2746                 kvm_inject_gp(&svm->vcpu, 0);
2747         } else {
2748                 trace_kvm_msr_read(ecx, data);
2749
2750                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2751                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2752                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2753                 skip_emulated_instruction(&svm->vcpu);
2754         }
2755         return 1;
2756 }
2757
2758 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2759 {
2760         struct vcpu_svm *svm = to_svm(vcpu);
2761         int svm_dis, chg_mask;
2762
2763         if (data & ~SVM_VM_CR_VALID_MASK)
2764                 return 1;
2765
2766         chg_mask = SVM_VM_CR_VALID_MASK;
2767
2768         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2769                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2770
2771         svm->nested.vm_cr_msr &= ~chg_mask;
2772         svm->nested.vm_cr_msr |= (data & chg_mask);
2773
2774         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2775
2776         /* check for svm_disable while efer.svme is set */
2777         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2778                 return 1;
2779
2780         return 0;
2781 }
2782
2783 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2784 {
2785         struct vcpu_svm *svm = to_svm(vcpu);
2786
2787         switch (ecx) {
2788         case MSR_IA32_TSC:
2789                 kvm_write_tsc(vcpu, data);
2790                 break;
2791         case MSR_STAR:
2792                 svm->vmcb->save.star = data;
2793                 break;
2794 #ifdef CONFIG_X86_64
2795         case MSR_LSTAR:
2796                 svm->vmcb->save.lstar = data;
2797                 break;
2798         case MSR_CSTAR:
2799                 svm->vmcb->save.cstar = data;
2800                 break;
2801         case MSR_KERNEL_GS_BASE:
2802                 svm->vmcb->save.kernel_gs_base = data;
2803                 break;
2804         case MSR_SYSCALL_MASK:
2805                 svm->vmcb->save.sfmask = data;
2806                 break;
2807 #endif
2808         case MSR_IA32_SYSENTER_CS:
2809                 svm->vmcb->save.sysenter_cs = data;
2810                 break;
2811         case MSR_IA32_SYSENTER_EIP:
2812                 svm->sysenter_eip = data;
2813                 svm->vmcb->save.sysenter_eip = data;
2814                 break;
2815         case MSR_IA32_SYSENTER_ESP:
2816                 svm->sysenter_esp = data;
2817                 svm->vmcb->save.sysenter_esp = data;
2818                 break;
2819         case MSR_IA32_DEBUGCTLMSR:
2820                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2821                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2822                                         __func__, data);
2823                         break;
2824                 }
2825                 if (data & DEBUGCTL_RESERVED_BITS)
2826                         return 1;
2827
2828                 svm->vmcb->save.dbgctl = data;
2829                 if (data & (1ULL<<0))
2830                         svm_enable_lbrv(svm);
2831                 else
2832                         svm_disable_lbrv(svm);
2833                 break;
2834         case MSR_VM_HSAVE_PA:
2835                 svm->nested.hsave_msr = data;
2836                 break;
2837         case MSR_VM_CR:
2838                 return svm_set_vm_cr(vcpu, data);
2839         case MSR_VM_IGNNE:
2840                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2841                 break;
2842         default:
2843                 return kvm_set_msr_common(vcpu, ecx, data);
2844         }
2845         return 0;
2846 }
2847
2848 static int wrmsr_interception(struct vcpu_svm *svm)
2849 {
2850         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2851         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2852                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2853
2854
2855         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2856         if (svm_set_msr(&svm->vcpu, ecx, data)) {
2857                 trace_kvm_msr_write_ex(ecx, data);
2858                 kvm_inject_gp(&svm->vcpu, 0);
2859         } else {
2860                 trace_kvm_msr_write(ecx, data);
2861                 skip_emulated_instruction(&svm->vcpu);
2862         }
2863         return 1;
2864 }
2865
2866 static int msr_interception(struct vcpu_svm *svm)
2867 {
2868         if (svm->vmcb->control.exit_info_1)
2869                 return wrmsr_interception(svm);
2870         else
2871                 return rdmsr_interception(svm);
2872 }
2873
2874 static int interrupt_window_interception(struct vcpu_svm *svm)
2875 {
2876         struct kvm_run *kvm_run = svm->vcpu.run;
2877
2878         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2879         svm_clear_vintr(svm);
2880         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2881         /*
2882          * If the user space waits to inject interrupts, exit as soon as
2883          * possible
2884          */
2885         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2886             kvm_run->request_interrupt_window &&
2887             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2888                 ++svm->vcpu.stat.irq_window_exits;
2889                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2890                 return 0;
2891         }
2892
2893         return 1;
2894 }
2895
2896 static int pause_interception(struct vcpu_svm *svm)
2897 {
2898         kvm_vcpu_on_spin(&(svm->vcpu));
2899         return 1;
2900 }
2901
2902 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2903         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2904         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2905         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2906         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2907         [SVM_EXIT_CR0_SEL_WRITE]                = emulate_on_interception,
2908         [SVM_EXIT_WRITE_CR0]                    = cr0_write_interception,
2909         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2910         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2911         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2912         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2913         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2914         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2915         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2916         [SVM_EXIT_READ_DR4]                     = emulate_on_interception,
2917         [SVM_EXIT_READ_DR5]                     = emulate_on_interception,
2918         [SVM_EXIT_READ_DR6]                     = emulate_on_interception,
2919         [SVM_EXIT_READ_DR7]                     = emulate_on_interception,
2920         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2921         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2922         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2923         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2924         [SVM_EXIT_WRITE_DR4]                    = emulate_on_interception,
2925         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2926         [SVM_EXIT_WRITE_DR6]                    = emulate_on_interception,
2927         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2928         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2929         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2930         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2931         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2932         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2933         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2934         [SVM_EXIT_INTR]                         = intr_interception,
2935         [SVM_EXIT_NMI]                          = nmi_interception,
2936         [SVM_EXIT_SMI]                          = nop_on_interception,
2937         [SVM_EXIT_INIT]                         = nop_on_interception,
2938         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2939         [SVM_EXIT_CPUID]                        = cpuid_interception,
2940         [SVM_EXIT_IRET]                         = iret_interception,
2941         [SVM_EXIT_INVD]                         = emulate_on_interception,
2942         [SVM_EXIT_PAUSE]                        = pause_interception,
2943         [SVM_EXIT_HLT]                          = halt_interception,
2944         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2945         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2946         [SVM_EXIT_IOIO]                         = io_interception,
2947         [SVM_EXIT_MSR]                          = msr_interception,
2948         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2949         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2950         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2951         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2952         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2953         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2954         [SVM_EXIT_STGI]                         = stgi_interception,
2955         [SVM_EXIT_CLGI]                         = clgi_interception,
2956         [SVM_EXIT_SKINIT]                       = skinit_interception,
2957         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2958         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2959         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2960         [SVM_EXIT_NPF]                          = pf_interception,
2961 };
2962
2963 void dump_vmcb(struct kvm_vcpu *vcpu)
2964 {
2965         struct vcpu_svm *svm = to_svm(vcpu);
2966         struct vmcb_control_area *control = &svm->vmcb->control;
2967         struct vmcb_save_area *save = &svm->vmcb->save;
2968
2969         pr_err("VMCB Control Area:\n");
2970         pr_err("cr_read:            %04x\n", control->intercept_cr & 0xffff);
2971         pr_err("cr_write:           %04x\n", control->intercept_cr >> 16);
2972         pr_err("dr_read:            %04x\n", control->intercept_dr & 0xffff);
2973         pr_err("dr_write:           %04x\n", control->intercept_dr >> 16);
2974         pr_err("exceptions:         %08x\n", control->intercept_exceptions);
2975         pr_err("intercepts:         %016llx\n", control->intercept);
2976         pr_err("pause filter count: %d\n", control->pause_filter_count);
2977         pr_err("iopm_base_pa:       %016llx\n", control->iopm_base_pa);
2978         pr_err("msrpm_base_pa:      %016llx\n", control->msrpm_base_pa);
2979         pr_err("tsc_offset:         %016llx\n", control->tsc_offset);
2980         pr_err("asid:               %d\n", control->asid);
2981         pr_err("tlb_ctl:            %d\n", control->tlb_ctl);
2982         pr_err("int_ctl:            %08x\n", control->int_ctl);
2983         pr_err("int_vector:         %08x\n", control->int_vector);
2984         pr_err("int_state:          %08x\n", control->int_state);
2985         pr_err("exit_code:          %08x\n", control->exit_code);
2986         pr_err("exit_info1:         %016llx\n", control->exit_info_1);
2987         pr_err("exit_info2:         %016llx\n", control->exit_info_2);
2988         pr_err("exit_int_info:      %08x\n", control->exit_int_info);
2989         pr_err("exit_int_info_err:  %08x\n", control->exit_int_info_err);
2990         pr_err("nested_ctl:         %lld\n", control->nested_ctl);
2991         pr_err("nested_cr3:         %016llx\n", control->nested_cr3);
2992         pr_err("event_inj:          %08x\n", control->event_inj);
2993         pr_err("event_inj_err:      %08x\n", control->event_inj_err);
2994         pr_err("lbr_ctl:            %lld\n", control->lbr_ctl);
2995         pr_err("next_rip:           %016llx\n", control->next_rip);
2996         pr_err("VMCB State Save Area:\n");
2997         pr_err("es:   s: %04x a: %04x l: %08x b: %016llx\n",
2998                 save->es.selector, save->es.attrib,
2999                 save->es.limit, save->es.base);
3000         pr_err("cs:   s: %04x a: %04x l: %08x b: %016llx\n",
3001                 save->cs.selector, save->cs.attrib,
3002                 save->cs.limit, save->cs.base);
3003         pr_err("ss:   s: %04x a: %04x l: %08x b: %016llx\n",
3004                 save->ss.selector, save->ss.attrib,
3005                 save->ss.limit, save->ss.base);
3006         pr_err("ds:   s: %04x a: %04x l: %08x b: %016llx\n",
3007                 save->ds.selector, save->ds.attrib,
3008                 save->ds.limit, save->ds.base);
3009         pr_err("fs:   s: %04x a: %04x l: %08x b: %016llx\n",
3010                 save->fs.selector, save->fs.attrib,
3011                 save->fs.limit, save->fs.base);
3012         pr_err("gs:   s: %04x a: %04x l: %08x b: %016llx\n",
3013                 save->gs.selector, save->gs.attrib,
3014                 save->gs.limit, save->gs.base);
3015         pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
3016                 save->gdtr.selector, save->gdtr.attrib,
3017                 save->gdtr.limit, save->gdtr.base);
3018         pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
3019                 save->ldtr.selector, save->ldtr.attrib,
3020                 save->ldtr.limit, save->ldtr.base);
3021         pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
3022                 save->idtr.selector, save->idtr.attrib,
3023                 save->idtr.limit, save->idtr.base);
3024         pr_err("tr:   s: %04x a: %04x l: %08x b: %016llx\n",
3025                 save->tr.selector, save->tr.attrib,
3026                 save->tr.limit, save->tr.base);
3027         pr_err("cpl:            %d                efer:         %016llx\n",
3028                 save->cpl, save->efer);
3029         pr_err("cr0:            %016llx cr2:          %016llx\n",
3030                 save->cr0, save->cr2);
3031         pr_err("cr3:            %016llx cr4:          %016llx\n",
3032                 save->cr3, save->cr4);
3033         pr_err("dr6:            %016llx dr7:          %016llx\n",
3034                 save->dr6, save->dr7);
3035         pr_err("rip:            %016llx rflags:       %016llx\n",
3036                 save->rip, save->rflags);
3037         pr_err("rsp:            %016llx rax:          %016llx\n",
3038                 save->rsp, save->rax);
3039         pr_err("star:           %016llx lstar:        %016llx\n",
3040                 save->star, save->lstar);
3041         pr_err("cstar:          %016llx sfmask:       %016llx\n",
3042                 save->cstar, save->sfmask);
3043         pr_err("kernel_gs_base: %016llx sysenter_cs:  %016llx\n",
3044                 save->kernel_gs_base, save->sysenter_cs);
3045         pr_err("sysenter_esp:   %016llx sysenter_eip: %016llx\n",
3046                 save->sysenter_esp, save->sysenter_eip);
3047         pr_err("gpat:           %016llx dbgctl:       %016llx\n",
3048                 save->g_pat, save->dbgctl);
3049         pr_err("br_from:        %016llx br_to:        %016llx\n",
3050                 save->br_from, save->br_to);
3051         pr_err("excp_from:      %016llx excp_to:      %016llx\n",
3052                 save->last_excp_from, save->last_excp_to);
3053
3054 }
3055
3056 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3057 {
3058         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3059
3060         *info1 = control->exit_info_1;
3061         *info2 = control->exit_info_2;
3062 }
3063
3064 static int handle_exit(struct kvm_vcpu *vcpu)
3065 {
3066         struct vcpu_svm *svm = to_svm(vcpu);
3067         struct kvm_run *kvm_run = vcpu->run;
3068         u32 exit_code = svm->vmcb->control.exit_code;
3069
3070         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3071
3072         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3073                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3074         if (npt_enabled)
3075                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3076
3077         if (unlikely(svm->nested.exit_required)) {
3078                 nested_svm_vmexit(svm);
3079                 svm->nested.exit_required = false;
3080
3081                 return 1;
3082         }
3083
3084         if (is_guest_mode(vcpu)) {
3085                 int vmexit;
3086
3087                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3088                                         svm->vmcb->control.exit_info_1,
3089                                         svm->vmcb->control.exit_info_2,
3090                                         svm->vmcb->control.exit_int_info,
3091                                         svm->vmcb->control.exit_int_info_err);
3092
3093                 vmexit = nested_svm_exit_special(svm);
3094
3095                 if (vmexit == NESTED_EXIT_CONTINUE)
3096                         vmexit = nested_svm_exit_handled(svm);
3097
3098                 if (vmexit == NESTED_EXIT_DONE)
3099                         return 1;
3100         }
3101
3102         svm_complete_interrupts(svm);
3103
3104         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3105                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3106                 kvm_run->fail_entry.hardware_entry_failure_reason
3107                         = svm->vmcb->control.exit_code;
3108                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3109                 dump_vmcb(vcpu);
3110                 return 0;
3111         }
3112
3113         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3114             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3115             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3116             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3117                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3118                        "exit_code 0x%x\n",
3119                        __func__, svm->vmcb->control.exit_int_info,
3120                        exit_code);
3121
3122         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3123             || !svm_exit_handlers[exit_code]) {
3124                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3125                 kvm_run->hw.hardware_exit_reason = exit_code;
3126                 return 0;
3127         }
3128
3129         return svm_exit_handlers[exit_code](svm);
3130 }
3131
3132 static void reload_tss(struct kvm_vcpu *vcpu)
3133 {
3134         int cpu = raw_smp_processor_id();
3135
3136         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3137         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3138         load_TR_desc();
3139 }
3140
3141 static void pre_svm_run(struct vcpu_svm *svm)
3142 {
3143         int cpu = raw_smp_processor_id();
3144
3145         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3146
3147         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3148         /* FIXME: handle wraparound of asid_generation */
3149         if (svm->asid_generation != sd->asid_generation)
3150                 new_asid(svm, sd);
3151 }
3152
3153 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3154 {
3155         struct vcpu_svm *svm = to_svm(vcpu);
3156
3157         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3158         vcpu->arch.hflags |= HF_NMI_MASK;
3159         set_intercept(svm, INTERCEPT_IRET);
3160         ++vcpu->stat.nmi_injections;
3161 }
3162
3163 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3164 {
3165         struct vmcb_control_area *control;
3166
3167         control = &svm->vmcb->control;
3168         control->int_vector = irq;
3169         control->int_ctl &= ~V_INTR_PRIO_MASK;
3170         control->int_ctl |= V_IRQ_MASK |
3171                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3172 }
3173
3174 static void svm_set_irq(struct kvm_vcpu *vcpu)
3175 {
3176         struct vcpu_svm *svm = to_svm(vcpu);
3177
3178         BUG_ON(!(gif_set(svm)));
3179
3180         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3181         ++vcpu->stat.irq_injections;
3182
3183         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3184                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3185 }
3186
3187 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3188 {
3189         struct vcpu_svm *svm = to_svm(vcpu);
3190
3191         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3192                 return;
3193
3194         if (irr == -1)
3195                 return;
3196
3197         if (tpr >= irr)
3198                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3199 }
3200
3201 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3202 {
3203         struct vcpu_svm *svm = to_svm(vcpu);
3204         struct vmcb *vmcb = svm->vmcb;
3205         int ret;
3206         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3207               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3208         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3209
3210         return ret;
3211 }
3212
3213 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3214 {
3215         struct vcpu_svm *svm = to_svm(vcpu);
3216
3217         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3218 }
3219
3220 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3221 {
3222         struct vcpu_svm *svm = to_svm(vcpu);
3223
3224         if (masked) {
3225                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3226                 set_intercept(svm, INTERCEPT_IRET);
3227         } else {
3228                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3229                 clr_intercept(svm, INTERCEPT_IRET);
3230         }
3231 }
3232
3233 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3234 {
3235         struct vcpu_svm *svm = to_svm(vcpu);
3236         struct vmcb *vmcb = svm->vmcb;
3237         int ret;
3238
3239         if (!gif_set(svm) ||
3240              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3241                 return 0;
3242
3243         ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3244
3245         if (is_guest_mode(vcpu))
3246                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3247
3248         return ret;
3249 }
3250
3251 static void enable_irq_window(struct kvm_vcpu *vcpu)
3252 {
3253         struct vcpu_svm *svm = to_svm(vcpu);
3254
3255         /*
3256          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3257          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3258          * get that intercept, this function will be called again though and
3259          * we'll get the vintr intercept.
3260          */
3261         if (gif_set(svm) && nested_svm_intr(svm)) {
3262                 svm_set_vintr(svm);
3263                 svm_inject_irq(svm, 0x0);
3264         }
3265 }
3266
3267 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3268 {
3269         struct vcpu_svm *svm = to_svm(vcpu);
3270
3271         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3272             == HF_NMI_MASK)
3273                 return; /* IRET will cause a vm exit */
3274
3275         /*
3276          * Something prevents NMI from been injected. Single step over possible
3277          * problem (IRET or exception injection or interrupt shadow)
3278          */
3279         svm->nmi_singlestep = true;
3280         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3281         update_db_intercept(vcpu);
3282 }
3283
3284 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3285 {
3286         return 0;
3287 }
3288
3289 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3290 {
3291         force_new_asid(vcpu);
3292 }
3293
3294 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3295 {
3296 }
3297
3298 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3299 {
3300         struct vcpu_svm *svm = to_svm(vcpu);
3301
3302         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3303                 return;
3304
3305         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3306                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3307                 kvm_set_cr8(vcpu, cr8);
3308         }
3309 }
3310
3311 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3312 {
3313         struct vcpu_svm *svm = to_svm(vcpu);
3314         u64 cr8;
3315
3316         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3317                 return;
3318
3319         cr8 = kvm_get_cr8(vcpu);
3320         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3321         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3322 }
3323
3324 static void svm_complete_interrupts(struct vcpu_svm *svm)
3325 {
3326         u8 vector;
3327         int type;
3328         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3329         unsigned int3_injected = svm->int3_injected;
3330
3331         svm->int3_injected = 0;
3332
3333         if (svm->vcpu.arch.hflags & HF_IRET_MASK) {
3334                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3335                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3336         }
3337
3338         svm->vcpu.arch.nmi_injected = false;
3339         kvm_clear_exception_queue(&svm->vcpu);
3340         kvm_clear_interrupt_queue(&svm->vcpu);
3341
3342         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3343                 return;
3344
3345         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3346
3347         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3348         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3349
3350         switch (type) {
3351         case SVM_EXITINTINFO_TYPE_NMI:
3352                 svm->vcpu.arch.nmi_injected = true;
3353                 break;
3354         case SVM_EXITINTINFO_TYPE_EXEPT:
3355                 /*
3356                  * In case of software exceptions, do not reinject the vector,
3357                  * but re-execute the instruction instead. Rewind RIP first
3358                  * if we emulated INT3 before.
3359                  */
3360                 if (kvm_exception_is_soft(vector)) {
3361                         if (vector == BP_VECTOR && int3_injected &&
3362                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3363                                 kvm_rip_write(&svm->vcpu,
3364                                               kvm_rip_read(&svm->vcpu) -
3365                                               int3_injected);
3366                         break;
3367                 }
3368                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3369                         u32 err = svm->vmcb->control.exit_int_info_err;
3370                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3371
3372                 } else
3373                         kvm_requeue_exception(&svm->vcpu, vector);
3374                 break;
3375         case SVM_EXITINTINFO_TYPE_INTR:
3376                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3377                 break;
3378         default:
3379                 break;
3380         }
3381 }
3382
3383 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3384 {
3385         struct vcpu_svm *svm = to_svm(vcpu);
3386         struct vmcb_control_area *control = &svm->vmcb->control;
3387
3388         control->exit_int_info = control->event_inj;
3389         control->exit_int_info_err = control->event_inj_err;
3390         control->event_inj = 0;
3391         svm_complete_interrupts(svm);
3392 }
3393
3394 #ifdef CONFIG_X86_64
3395 #define R "r"
3396 #else
3397 #define R "e"
3398 #endif
3399
3400 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3401 {
3402         struct vcpu_svm *svm = to_svm(vcpu);
3403
3404         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3405         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3406         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3407
3408         /*
3409          * A vmexit emulation is required before the vcpu can be executed
3410          * again.
3411          */
3412         if (unlikely(svm->nested.exit_required))
3413                 return;
3414
3415         pre_svm_run(svm);
3416
3417         sync_lapic_to_cr8(vcpu);
3418
3419         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3420
3421         clgi();
3422
3423         local_irq_enable();
3424
3425         asm volatile (
3426                 "push %%"R"bp; \n\t"
3427                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3428                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3429                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3430                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3431                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3432                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3433 #ifdef CONFIG_X86_64
3434                 "mov %c[r8](%[svm]),  %%r8  \n\t"
3435                 "mov %c[r9](%[svm]),  %%r9  \n\t"
3436                 "mov %c[r10](%[svm]), %%r10 \n\t"
3437                 "mov %c[r11](%[svm]), %%r11 \n\t"
3438                 "mov %c[r12](%[svm]), %%r12 \n\t"
3439                 "mov %c[r13](%[svm]), %%r13 \n\t"
3440                 "mov %c[r14](%[svm]), %%r14 \n\t"
3441                 "mov %c[r15](%[svm]), %%r15 \n\t"
3442 #endif
3443
3444                 /* Enter guest mode */
3445                 "push %%"R"ax \n\t"
3446                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3447                 __ex(SVM_VMLOAD) "\n\t"
3448                 __ex(SVM_VMRUN) "\n\t"
3449                 __ex(SVM_VMSAVE) "\n\t"
3450                 "pop %%"R"ax \n\t"
3451
3452                 /* Save guest registers, load host registers */
3453                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3454                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3455                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3456                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3457                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3458                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3459 #ifdef CONFIG_X86_64
3460                 "mov %%r8,  %c[r8](%[svm]) \n\t"
3461                 "mov %%r9,  %c[r9](%[svm]) \n\t"
3462                 "mov %%r10, %c[r10](%[svm]) \n\t"
3463                 "mov %%r11, %c[r11](%[svm]) \n\t"
3464                 "mov %%r12, %c[r12](%[svm]) \n\t"
3465                 "mov %%r13, %c[r13](%[svm]) \n\t"
3466                 "mov %%r14, %c[r14](%[svm]) \n\t"
3467                 "mov %%r15, %c[r15](%[svm]) \n\t"
3468 #endif
3469                 "pop %%"R"bp"
3470                 :
3471                 : [svm]"a"(svm),
3472                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3473                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3474                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3475                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3476                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3477                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3478                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3479 #ifdef CONFIG_X86_64
3480                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3481                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3482                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3483                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3484                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3485                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3486                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3487                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3488 #endif
3489                 : "cc", "memory"
3490                 , R"bx", R"cx", R"dx", R"si", R"di"
3491 #ifdef CONFIG_X86_64
3492                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3493 #endif
3494                 );
3495
3496 #ifdef CONFIG_X86_64
3497         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3498 #else
3499         loadsegment(fs, svm->host.fs);
3500 #endif
3501
3502         reload_tss(vcpu);
3503
3504         local_irq_disable();
3505
3506         stgi();
3507
3508         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3509         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3510         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3511         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3512
3513         sync_cr8_to_lapic(vcpu);
3514
3515         svm->next_rip = 0;
3516
3517         /* if exit due to PF check for async PF */
3518         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3519                 svm->apf_reason = kvm_read_and_reset_pf_reason();
3520
3521         if (npt_enabled) {
3522                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3523                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3524         }
3525
3526         /*
3527          * We need to handle MC intercepts here before the vcpu has a chance to
3528          * change the physical cpu
3529          */
3530         if (unlikely(svm->vmcb->control.exit_code ==
3531                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3532                 svm_handle_mce(svm);
3533
3534         mark_all_clean(svm->vmcb);
3535 }
3536
3537 #undef R
3538
3539 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3540 {
3541         struct vcpu_svm *svm = to_svm(vcpu);
3542
3543         svm->vmcb->save.cr3 = root;
3544         force_new_asid(vcpu);
3545 }
3546
3547 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3548 {
3549         struct vcpu_svm *svm = to_svm(vcpu);
3550
3551         svm->vmcb->control.nested_cr3 = root;
3552
3553         /* Also sync guest cr3 here in case we live migrate */
3554         svm->vmcb->save.cr3 = vcpu->arch.cr3;
3555
3556         force_new_asid(vcpu);
3557 }
3558
3559 static int is_disabled(void)
3560 {
3561         u64 vm_cr;
3562
3563         rdmsrl(MSR_VM_CR, vm_cr);
3564         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3565                 return 1;
3566
3567         return 0;
3568 }
3569
3570 static void
3571 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3572 {
3573         /*
3574          * Patch in the VMMCALL instruction:
3575          */
3576         hypercall[0] = 0x0f;
3577         hypercall[1] = 0x01;
3578         hypercall[2] = 0xd9;
3579 }
3580
3581 static void svm_check_processor_compat(void *rtn)
3582 {
3583         *(int *)rtn = 0;
3584 }
3585
3586 static bool svm_cpu_has_accelerated_tpr(void)
3587 {
3588         return false;
3589 }
3590
3591 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3592 {
3593         return 0;
3594 }
3595
3596 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3597 {
3598 }
3599
3600 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3601 {
3602         switch (func) {
3603         case 0x00000001:
3604                 /* Mask out xsave bit as long as it is not supported by SVM */
3605                 entry->ecx &= ~(bit(X86_FEATURE_XSAVE));
3606                 break;
3607         case 0x80000001:
3608                 if (nested)
3609                         entry->ecx |= (1 << 2); /* Set SVM bit */
3610                 break;
3611         case 0x8000000A:
3612                 entry->eax = 1; /* SVM revision 1 */
3613                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3614                                    ASID emulation to nested SVM */
3615                 entry->ecx = 0; /* Reserved */
3616                 entry->edx = 0; /* Per default do not support any
3617                                    additional features */
3618
3619                 /* Support next_rip if host supports it */
3620                 if (boot_cpu_has(X86_FEATURE_NRIPS))
3621                         entry->edx |= SVM_FEATURE_NRIP;
3622
3623                 /* Support NPT for the guest if enabled */
3624                 if (npt_enabled)
3625                         entry->edx |= SVM_FEATURE_NPT;
3626
3627                 break;
3628         }
3629 }
3630
3631 static const struct trace_print_flags svm_exit_reasons_str[] = {
3632         { SVM_EXIT_READ_CR0,                    "read_cr0" },
3633         { SVM_EXIT_READ_CR3,                    "read_cr3" },
3634         { SVM_EXIT_READ_CR4,                    "read_cr4" },
3635         { SVM_EXIT_READ_CR8,                    "read_cr8" },
3636         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
3637         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
3638         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
3639         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
3640         { SVM_EXIT_READ_DR0,                    "read_dr0" },
3641         { SVM_EXIT_READ_DR1,                    "read_dr1" },
3642         { SVM_EXIT_READ_DR2,                    "read_dr2" },
3643         { SVM_EXIT_READ_DR3,                    "read_dr3" },
3644         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
3645         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
3646         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
3647         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
3648         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
3649         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
3650         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
3651         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
3652         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
3653         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
3654         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
3655         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
3656         { SVM_EXIT_INTR,                        "interrupt" },
3657         { SVM_EXIT_NMI,                         "nmi" },
3658         { SVM_EXIT_SMI,                         "smi" },
3659         { SVM_EXIT_INIT,                        "init" },
3660         { SVM_EXIT_VINTR,                       "vintr" },
3661         { SVM_EXIT_CPUID,                       "cpuid" },
3662         { SVM_EXIT_INVD,                        "invd" },
3663         { SVM_EXIT_HLT,                         "hlt" },
3664         { SVM_EXIT_INVLPG,                      "invlpg" },
3665         { SVM_EXIT_INVLPGA,                     "invlpga" },
3666         { SVM_EXIT_IOIO,                        "io" },
3667         { SVM_EXIT_MSR,                         "msr" },
3668         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
3669         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
3670         { SVM_EXIT_VMRUN,                       "vmrun" },
3671         { SVM_EXIT_VMMCALL,                     "hypercall" },
3672         { SVM_EXIT_VMLOAD,                      "vmload" },
3673         { SVM_EXIT_VMSAVE,                      "vmsave" },
3674         { SVM_EXIT_STGI,                        "stgi" },
3675         { SVM_EXIT_CLGI,                        "clgi" },
3676         { SVM_EXIT_SKINIT,                      "skinit" },
3677         { SVM_EXIT_WBINVD,                      "wbinvd" },
3678         { SVM_EXIT_MONITOR,                     "monitor" },
3679         { SVM_EXIT_MWAIT,                       "mwait" },
3680         { SVM_EXIT_NPF,                         "npf" },
3681         { -1, NULL }
3682 };
3683
3684 static int svm_get_lpage_level(void)
3685 {
3686         return PT_PDPE_LEVEL;
3687 }
3688
3689 static bool svm_rdtscp_supported(void)
3690 {
3691         return false;
3692 }
3693
3694 static bool svm_has_wbinvd_exit(void)
3695 {
3696         return true;
3697 }
3698
3699 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3700 {
3701         struct vcpu_svm *svm = to_svm(vcpu);
3702
3703         set_exception_intercept(svm, NM_VECTOR);
3704         update_cr0_intercept(svm);
3705 }
3706
3707 static struct kvm_x86_ops svm_x86_ops = {
3708         .cpu_has_kvm_support = has_svm,
3709         .disabled_by_bios = is_disabled,
3710         .hardware_setup = svm_hardware_setup,
3711         .hardware_unsetup = svm_hardware_unsetup,
3712         .check_processor_compatibility = svm_check_processor_compat,
3713         .hardware_enable = svm_hardware_enable,
3714         .hardware_disable = svm_hardware_disable,
3715         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3716
3717         .vcpu_create = svm_create_vcpu,
3718         .vcpu_free = svm_free_vcpu,
3719         .vcpu_reset = svm_vcpu_reset,
3720
3721         .prepare_guest_switch = svm_prepare_guest_switch,
3722         .vcpu_load = svm_vcpu_load,
3723         .vcpu_put = svm_vcpu_put,
3724
3725         .set_guest_debug = svm_guest_debug,
3726         .get_msr = svm_get_msr,
3727         .set_msr = svm_set_msr,
3728         .get_segment_base = svm_get_segment_base,
3729         .get_segment = svm_get_segment,
3730         .set_segment = svm_set_segment,
3731         .get_cpl = svm_get_cpl,
3732         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3733         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3734         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3735         .set_cr0 = svm_set_cr0,
3736         .set_cr3 = svm_set_cr3,
3737         .set_cr4 = svm_set_cr4,
3738         .set_efer = svm_set_efer,
3739         .get_idt = svm_get_idt,
3740         .set_idt = svm_set_idt,
3741         .get_gdt = svm_get_gdt,
3742         .set_gdt = svm_set_gdt,
3743         .set_dr7 = svm_set_dr7,
3744         .cache_reg = svm_cache_reg,
3745         .get_rflags = svm_get_rflags,
3746         .set_rflags = svm_set_rflags,
3747         .fpu_activate = svm_fpu_activate,
3748         .fpu_deactivate = svm_fpu_deactivate,
3749
3750         .tlb_flush = svm_flush_tlb,
3751
3752         .run = svm_vcpu_run,
3753         .handle_exit = handle_exit,
3754         .skip_emulated_instruction = skip_emulated_instruction,
3755         .set_interrupt_shadow = svm_set_interrupt_shadow,
3756         .get_interrupt_shadow = svm_get_interrupt_shadow,
3757         .patch_hypercall = svm_patch_hypercall,
3758         .set_irq = svm_set_irq,
3759         .set_nmi = svm_inject_nmi,
3760         .queue_exception = svm_queue_exception,
3761         .cancel_injection = svm_cancel_injection,
3762         .interrupt_allowed = svm_interrupt_allowed,
3763         .nmi_allowed = svm_nmi_allowed,
3764         .get_nmi_mask = svm_get_nmi_mask,
3765         .set_nmi_mask = svm_set_nmi_mask,
3766         .enable_nmi_window = enable_nmi_window,
3767         .enable_irq_window = enable_irq_window,
3768         .update_cr8_intercept = update_cr8_intercept,
3769
3770         .set_tss_addr = svm_set_tss_addr,
3771         .get_tdp_level = get_npt_level,
3772         .get_mt_mask = svm_get_mt_mask,
3773
3774         .get_exit_info = svm_get_exit_info,
3775         .exit_reasons_str = svm_exit_reasons_str,
3776
3777         .get_lpage_level = svm_get_lpage_level,
3778
3779         .cpuid_update = svm_cpuid_update,
3780
3781         .rdtscp_supported = svm_rdtscp_supported,
3782
3783         .set_supported_cpuid = svm_set_supported_cpuid,
3784
3785         .has_wbinvd_exit = svm_has_wbinvd_exit,
3786
3787         .write_tsc_offset = svm_write_tsc_offset,
3788         .adjust_tsc_offset = svm_adjust_tsc_offset,
3789
3790         .set_tdp_cr3 = set_tdp_cr3,
3791 };
3792
3793 static int __init svm_init(void)
3794 {
3795         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3796                         __alignof__(struct vcpu_svm), THIS_MODULE);
3797 }
3798
3799 static void __exit svm_exit(void)
3800 {
3801         kvm_exit();
3802 }
3803
3804 module_init(svm_init)
3805 module_exit(svm_exit)