arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17 #include <linux/kvm_host.h>
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22 #include "x86.h"
  23
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31
  32 #include <asm/perf_event.h>
  33 #include <asm/tlbflush.h>
  34 #include <asm/desc.h>
  35 #include <asm/kvm_para.h>
  36
  37 #include <asm/virtext.h>
  38 #include "trace.h"
  39
  40 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  41
  42 MODULE_AUTHOR("Qumranet");
  43 MODULE_LICENSE("GPL");
  44
  45 #define IOPM_ALLOC_ORDER 2
  46 #define MSRPM_ALLOC_ORDER 1
  47
  48 #define SEG_TYPE_LDT 2
  49 #define SEG_TYPE_BUSY_TSS16 3
  50
  51 #define SVM_FEATURE_NPT            (1 <<  0)
  52 #define SVM_FEATURE_LBRV           (1 <<  1)
  53 #define SVM_FEATURE_SVML           (1 <<  2)
  54 #define SVM_FEATURE_NRIP           (1 <<  3)
  55 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  56 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  57 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  58 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  59 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  60
  61 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  62 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  63 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  64
  65 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  66
  67 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  68 #define TSC_RATIO_MIN           0x0000000000000001ULL
  69 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  70
  71 static bool erratum_383_found __read_mostly;
  72
  73 static const u32 host_save_user_msrs[] = {
  74 #ifdef CONFIG_X86_64
  75         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  76         MSR_FS_BASE,
  77 #endif
  78         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  79 };
  80
  81 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  82
  83 struct kvm_vcpu;
  84
  85 struct nested_state {
  86         struct vmcb *hsave;
  87         u64 hsave_msr;
  88         u64 vm_cr_msr;
  89         u64 vmcb;
  90
  91         /* These are the merged vectors */
  92         u32 *msrpm;
  93
  94         /* gpa pointers to the real vectors */
  95         u64 vmcb_msrpm;
  96         u64 vmcb_iopm;
  97
  98         /* A VMEXIT is required but not yet emulated */
  99         bool exit_required;
 100
 101         /* cache for intercepts of the guest */
 102         u32 intercept_cr;
 103         u32 intercept_dr;
 104         u32 intercept_exceptions;
 105         u64 intercept;
 106
 107         /* Nested Paging related state */
 108         u64 nested_cr3;
 109 };
 110
 111 #define MSRPM_OFFSETS   16
 112 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 113
 114 struct vcpu_svm {
 115         struct kvm_vcpu vcpu;
 116         struct vmcb *vmcb;
 117         unsigned long vmcb_pa;
 118         struct svm_cpu_data *svm_data;
 119         uint64_t asid_generation;
 120         uint64_t sysenter_esp;
 121         uint64_t sysenter_eip;
 122
 123         u64 next_rip;
 124
 125         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 126         struct {
 127                 u16 fs;
 128                 u16 gs;
 129                 u16 ldt;
 130                 u64 gs_base;
 131         } host;
 132
 133         u32 *msrpm;
 134
 135         ulong nmi_iret_rip;
 136
 137         struct nested_state nested;
 138
 139         bool nmi_singlestep;
 140
 141         unsigned int3_injected;
 142         unsigned long int3_rip;
 143         u32 apf_reason;
 144
 145         u64  tsc_ratio;
 146 };
 147
 148 static DEFINE_PER_CPU(u64, current_tsc_ratio);
 149 #define TSC_RATIO_DEFAULT       0x0100000000ULL
 150
 151 #define MSR_INVALID                     0xffffffffU
 152
 153 static struct svm_direct_access_msrs {
 154         u32 index;   /* Index of the MSR */
 155         bool always; /* True if intercept is always on */
 156 } direct_access_msrs[] = {
 157         { .index = MSR_STAR,                            .always = true  },
 158         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 159 #ifdef CONFIG_X86_64
 160         { .index = MSR_GS_BASE,                         .always = true  },
 161         { .index = MSR_FS_BASE,                         .always = true  },
 162         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 163         { .index = MSR_LSTAR,                           .always = true  },
 164         { .index = MSR_CSTAR,                           .always = true  },
 165         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 166 #endif
 167         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 168         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 169         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 170         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 171         { .index = MSR_INVALID,                         .always = false },
 172 };
 173
 174 /* enable NPT for AMD64 and X86 with PAE */
 175 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 176 static bool npt_enabled = true;
 177 #else
 178 static bool npt_enabled;
 179 #endif
 180 static int npt = 1;
 181
 182 module_param(npt, int, S_IRUGO);
 183
 184 static int nested = 1;
 185 module_param(nested, int, S_IRUGO);
 186
 187 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 188 static void svm_complete_interrupts(struct vcpu_svm *svm);
 189
 190 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 191 static int nested_svm_intercept(struct vcpu_svm *svm);
 192 static int nested_svm_vmexit(struct vcpu_svm *svm);
 193 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 194                                       bool has_error_code, u32 error_code);
 195 static u64 __scale_tsc(u64 ratio, u64 tsc);
 196
 197 enum {
 198         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
 199                             pause filter count */
 200         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
 201         VMCB_ASID,       /* ASID */
 202         VMCB_INTR,       /* int_ctl, int_vector */
 203         VMCB_NPT,        /* npt_en, nCR3, gPAT */
 204         VMCB_CR,         /* CR0, CR3, CR4, EFER */
 205         VMCB_DR,         /* DR6, DR7 */
 206         VMCB_DT,         /* GDT, IDT */
 207         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
 208         VMCB_CR2,        /* CR2 only */
 209         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
 210         VMCB_DIRTY_MAX,
 211 };
 212
 213 /* TPR and CR2 are always written before VMRUN */
 214 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
 215
 216 static inline void mark_all_dirty(struct vmcb *vmcb)
 217 {
 218         vmcb->control.clean = 0;
 219 }
 220
 221 static inline void mark_all_clean(struct vmcb *vmcb)
 222 {
 223         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 224                                & ~VMCB_ALWAYS_DIRTY_MASK;
 225 }
 226
 227 static inline void mark_dirty(struct vmcb *vmcb, int bit)
 228 {
 229         vmcb->control.clean &= ~(1 << bit);
 230 }
 231
 232 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 233 {
 234         return container_of(vcpu, struct vcpu_svm, vcpu);
 235 }
 236
 237 static void recalc_intercepts(struct vcpu_svm *svm)
 238 {
 239         struct vmcb_control_area *c, *h;
 240         struct nested_state *g;
 241
 242         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 243
 244         if (!is_guest_mode(&svm->vcpu))
 245                 return;
 246
 247         c = &svm->vmcb->control;
 248         h = &svm->nested.hsave->control;
 249         g = &svm->nested;
 250
 251         c->intercept_cr = h->intercept_cr | g->intercept_cr;
 252         c->intercept_dr = h->intercept_dr | g->intercept_dr;
 253         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
 254         c->intercept = h->intercept | g->intercept;
 255 }
 256
 257 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
 258 {
 259         if (is_guest_mode(&svm->vcpu))
 260                 return svm->nested.hsave;
 261         else
 262                 return svm->vmcb;
 263 }
 264
 265 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
 266 {
 267         struct vmcb *vmcb = get_host_vmcb(svm);
 268
 269         vmcb->control.intercept_cr |= (1U << bit);
 270
 271         recalc_intercepts(svm);
 272 }
 273
 274 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
 275 {
 276         struct vmcb *vmcb = get_host_vmcb(svm);
 277
 278         vmcb->control.intercept_cr &= ~(1U << bit);
 279
 280         recalc_intercepts(svm);
 281 }
 282
 283 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
 284 {
 285         struct vmcb *vmcb = get_host_vmcb(svm);
 286
 287         return vmcb->control.intercept_cr & (1U << bit);
 288 }
 289
 290 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
 291 {
 292         struct vmcb *vmcb = get_host_vmcb(svm);
 293
 294         vmcb->control.intercept_dr |= (1U << bit);
 295
 296         recalc_intercepts(svm);
 297 }
 298
 299 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
 300 {
 301         struct vmcb *vmcb = get_host_vmcb(svm);
 302
 303         vmcb->control.intercept_dr &= ~(1U << bit);
 304
 305         recalc_intercepts(svm);
 306 }
 307
 308 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
 309 {
 310         struct vmcb *vmcb = get_host_vmcb(svm);
 311
 312         vmcb->control.intercept_exceptions |= (1U << bit);
 313
 314         recalc_intercepts(svm);
 315 }
 316
 317 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
 318 {
 319         struct vmcb *vmcb = get_host_vmcb(svm);
 320
 321         vmcb->control.intercept_exceptions &= ~(1U << bit);
 322
 323         recalc_intercepts(svm);
 324 }
 325
 326 static inline void set_intercept(struct vcpu_svm *svm, int bit)
 327 {
 328         struct vmcb *vmcb = get_host_vmcb(svm);
 329
 330         vmcb->control.intercept |= (1ULL << bit);
 331
 332         recalc_intercepts(svm);
 333 }
 334
 335 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
 336 {
 337         struct vmcb *vmcb = get_host_vmcb(svm);
 338
 339         vmcb->control.intercept &= ~(1ULL << bit);
 340
 341         recalc_intercepts(svm);
 342 }
 343
 344 static inline void enable_gif(struct vcpu_svm *svm)
 345 {
 346         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 347 }
 348
 349 static inline void disable_gif(struct vcpu_svm *svm)
 350 {
 351         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 352 }
 353
 354 static inline bool gif_set(struct vcpu_svm *svm)
 355 {
 356         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 357 }
 358
 359 static unsigned long iopm_base;
 360
 361 struct kvm_ldttss_desc {
 362         u16 limit0;
 363         u16 base0;
 364         unsigned base1:8, type:5, dpl:2, p:1;
 365         unsigned limit1:4, zero0:3, g:1, base2:8;
 366         u32 base3;
 367         u32 zero1;
 368 } __attribute__((packed));
 369
 370 struct svm_cpu_data {
 371         int cpu;
 372
 373         u64 asid_generation;
 374         u32 max_asid;
 375         u32 next_asid;
 376         struct kvm_ldttss_desc *tss_desc;
 377
 378         struct page *save_area;
 379 };
 380
 381 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 382
 383 struct svm_init_data {
 384         int cpu;
 385         int r;
 386 };
 387
 388 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 389
 390 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 391 #define MSRS_RANGE_SIZE 2048
 392 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 393
 394 static u32 svm_msrpm_offset(u32 msr)
 395 {
 396         u32 offset;
 397         int i;
 398
 399         for (i = 0; i < NUM_MSR_MAPS; i++) {
 400                 if (msr < msrpm_ranges[i] ||
 401                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 402                         continue;
 403
 404                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 405                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 406
 407                 /* Now we have the u8 offset - but need the u32 offset */
 408                 return offset / 4;
 409         }
 410
 411         /* MSR not in any range */
 412         return MSR_INVALID;
 413 }
 414
 415 #define MAX_INST_SIZE 15
 416
 417 static inline void clgi(void)
 418 {
 419         asm volatile (__ex(SVM_CLGI));
 420 }
 421
 422 static inline void stgi(void)
 423 {
 424         asm volatile (__ex(SVM_STGI));
 425 }
 426
 427 static inline void invlpga(unsigned long addr, u32 asid)
 428 {
 429         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 430 }
 431
 432 static int get_npt_level(void)
 433 {
 434 #ifdef CONFIG_X86_64
 435         return PT64_ROOT_LEVEL;
 436 #else
 437         return PT32E_ROOT_LEVEL;
 438 #endif
 439 }
 440
 441 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 442 {
 443         vcpu->arch.efer = efer;
 444         if (!npt_enabled && !(efer & EFER_LMA))
 445                 efer &= ~EFER_LME;
 446
 447         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 448         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 449 }
 450
 451 static int is_external_interrupt(u32 info)
 452 {
 453         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 454         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 455 }
 456
 457 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 458 {
 459         struct vcpu_svm *svm = to_svm(vcpu);
 460         u32 ret = 0;
 461
 462         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 463                 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 464         return ret & mask;
 465 }
 466
 467 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 468 {
 469         struct vcpu_svm *svm = to_svm(vcpu);
 470
 471         if (mask == 0)
 472                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 473         else
 474                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 475
 476 }
 477
 478 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 479 {
 480         struct vcpu_svm *svm = to_svm(vcpu);
 481
 482         if (svm->vmcb->control.next_rip != 0)
 483                 svm->next_rip = svm->vmcb->control.next_rip;
 484
 485         if (!svm->next_rip) {
 486                 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
 487                                 EMULATE_DONE)
 488                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 489                 return;
 490         }
 491         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 492                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 493                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 494
 495         kvm_rip_write(vcpu, svm->next_rip);
 496         svm_set_interrupt_shadow(vcpu, 0);
 497 }
 498
 499 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 500                                 bool has_error_code, u32 error_code,
 501                                 bool reinject)
 502 {
 503         struct vcpu_svm *svm = to_svm(vcpu);
 504
 505         /*
 506          * If we are within a nested VM we'd better #VMEXIT and let the guest
 507          * handle the exception
 508          */
 509         if (!reinject &&
 510             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 511                 return;
 512
 513         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 514                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 515
 516                 /*
 517                  * For guest debugging where we have to reinject #BP if some
 518                  * INT3 is guest-owned:
 519                  * Emulate nRIP by moving RIP forward. Will fail if injection
 520                  * raises a fault that is not intercepted. Still better than
 521                  * failing in all cases.
 522                  */
 523                 skip_emulated_instruction(&svm->vcpu);
 524                 rip = kvm_rip_read(&svm->vcpu);
 525                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 526                 svm->int3_injected = rip - old_rip;
 527         }
 528
 529         svm->vmcb->control.event_inj = nr
 530                 | SVM_EVTINJ_VALID
 531                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 532                 | SVM_EVTINJ_TYPE_EXEPT;
 533         svm->vmcb->control.event_inj_err = error_code;
 534 }
 535
 536 static void svm_init_erratum_383(void)
 537 {
 538         u32 low, high;
 539         int err;
 540         u64 val;
 541
 542         if (!cpu_has_amd_erratum(amd_erratum_383))
 543                 return;
 544
 545         /* Use _safe variants to not break nested virtualization */
 546         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 547         if (err)
 548                 return;
 549
 550         val |= (1ULL << 47);
 551
 552         low  = lower_32_bits(val);
 553         high = upper_32_bits(val);
 554
 555         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 556
 557         erratum_383_found = true;
 558 }
 559
 560 static int has_svm(void)
 561 {
 562         const char *msg;
 563
 564         if (!cpu_has_svm(&msg)) {
 565                 printk(KERN_INFO "has_svm: %s\n", msg);
 566                 return 0;
 567         }
 568
 569         return 1;
 570 }
 571
 572 static void svm_hardware_disable(void *garbage)
 573 {
 574         /* Make sure we clean up behind us */
 575         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 576                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 577
 578         cpu_svm_disable();
 579
 580         amd_pmu_disable_virt();
 581 }
 582
 583 static int svm_hardware_enable(void *garbage)
 584 {
 585
 586         struct svm_cpu_data *sd;
 587         uint64_t efer;
 588         struct desc_ptr gdt_descr;
 589         struct desc_struct *gdt;
 590         int me = raw_smp_processor_id();
 591
 592         rdmsrl(MSR_EFER, efer);
 593         if (efer & EFER_SVME)
 594                 return -EBUSY;
 595
 596         if (!has_svm()) {
 597                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 598                        me);
 599                 return -EINVAL;
 600         }
 601         sd = per_cpu(svm_data, me);
 602
 603         if (!sd) {
 604                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 605                        me);
 606                 return -EINVAL;
 607         }
 608
 609         sd->asid_generation = 1;
 610         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 611         sd->next_asid = sd->max_asid + 1;
 612
 613         native_store_gdt(&gdt_descr);
 614         gdt = (struct desc_struct *)gdt_descr.address;
 615         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 616
 617         wrmsrl(MSR_EFER, efer | EFER_SVME);
 618
 619         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 620
 621         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 622                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 623                 __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT;
 624         }
 625
 626         svm_init_erratum_383();
 627
 628         amd_pmu_enable_virt();
 629
 630         return 0;
 631 }
 632
 633 static void svm_cpu_uninit(int cpu)
 634 {
 635         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 636
 637         if (!sd)
 638                 return;
 639
 640         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 641         __free_page(sd->save_area);
 642         kfree(sd);
 643 }
 644
 645 static int svm_cpu_init(int cpu)
 646 {
 647         struct svm_cpu_data *sd;
 648         int r;
 649
 650         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 651         if (!sd)
 652                 return -ENOMEM;
 653         sd->cpu = cpu;
 654         sd->save_area = alloc_page(GFP_KERNEL);
 655         r = -ENOMEM;
 656         if (!sd->save_area)
 657                 goto err_1;
 658
 659         per_cpu(svm_data, cpu) = sd;
 660
 661         return 0;
 662
 663 err_1:
 664         kfree(sd);
 665         return r;
 666
 667 }
 668
 669 static bool valid_msr_intercept(u32 index)
 670 {
 671         int i;
 672
 673         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 674                 if (direct_access_msrs[i].index == index)
 675                         return true;
 676
 677         return false;
 678 }
 679
 680 static void set_msr_interception(u32 *msrpm, unsigned msr,
 681                                  int read, int write)
 682 {
 683         u8 bit_read, bit_write;
 684         unsigned long tmp;
 685         u32 offset;
 686
 687         /*
 688          * If this warning triggers extend the direct_access_msrs list at the
 689          * beginning of the file
 690          */
 691         WARN_ON(!valid_msr_intercept(msr));
 692
 693         offset    = svm_msrpm_offset(msr);
 694         bit_read  = 2 * (msr & 0x0f);
 695         bit_write = 2 * (msr & 0x0f) + 1;
 696         tmp       = msrpm[offset];
 697
 698         BUG_ON(offset == MSR_INVALID);
 699
 700         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 701         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 702
 703         msrpm[offset] = tmp;
 704 }
 705
 706 static void svm_vcpu_init_msrpm(u32 *msrpm)
 707 {
 708         int i;
 709
 710         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 711
 712         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 713                 if (!direct_access_msrs[i].always)
 714                         continue;
 715
 716                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 717         }
 718 }
 719
 720 static void add_msr_offset(u32 offset)
 721 {
 722         int i;
 723
 724         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 725
 726                 /* Offset already in list? */
 727                 if (msrpm_offsets[i] == offset)
 728                         return;
 729
 730                 /* Slot used by another offset? */
 731                 if (msrpm_offsets[i] != MSR_INVALID)
 732                         continue;
 733
 734                 /* Add offset to list */
 735                 msrpm_offsets[i] = offset;
 736
 737                 return;
 738         }
 739
 740         /*
 741          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 742          * increase MSRPM_OFFSETS in this case.
 743          */
 744         BUG();
 745 }
 746
 747 static void init_msrpm_offsets(void)
 748 {
 749         int i;
 750
 751         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 752
 753         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 754                 u32 offset;
 755
 756                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 757                 BUG_ON(offset == MSR_INVALID);
 758
 759                 add_msr_offset(offset);
 760         }
 761 }
 762
 763 static void svm_enable_lbrv(struct vcpu_svm *svm)
 764 {
 765         u32 *msrpm = svm->msrpm;
 766
 767         svm->vmcb->control.lbr_ctl = 1;
 768         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 769         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 770         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 771         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 772 }
 773
 774 static void svm_disable_lbrv(struct vcpu_svm *svm)
 775 {
 776         u32 *msrpm = svm->msrpm;
 777
 778         svm->vmcb->control.lbr_ctl = 0;
 779         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 780         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 781         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 782         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 783 }
 784
 785 static __init int svm_hardware_setup(void)
 786 {
 787         int cpu;
 788         struct page *iopm_pages;
 789         void *iopm_va;
 790         int r;
 791
 792         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 793
 794         if (!iopm_pages)
 795                 return -ENOMEM;
 796
 797         iopm_va = page_address(iopm_pages);
 798         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 799         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 800
 801         init_msrpm_offsets();
 802
 803         if (boot_cpu_has(X86_FEATURE_NX))
 804                 kvm_enable_efer_bits(EFER_NX);
 805
 806         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 807                 kvm_enable_efer_bits(EFER_FFXSR);
 808
 809         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 810                 u64 max;
 811
 812                 kvm_has_tsc_control = true;
 813
 814                 /*
 815                  * Make sure the user can only configure tsc_khz values that
 816                  * fit into a signed integer.
 817                  * A min value is not calculated needed because it will always
 818                  * be 1 on all machines and a value of 0 is used to disable
 819                  * tsc-scaling for the vcpu.
 820                  */
 821                 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
 822
 823                 kvm_max_guest_tsc_khz = max;
 824         }
 825
 826         if (nested) {
 827                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 828                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 829         }
 830
 831         for_each_possible_cpu(cpu) {
 832                 r = svm_cpu_init(cpu);
 833                 if (r)
 834                         goto err;
 835         }
 836
 837         if (!boot_cpu_has(X86_FEATURE_NPT))
 838                 npt_enabled = false;
 839
 840         if (npt_enabled && !npt) {
 841                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 842                 npt_enabled = false;
 843         }
 844
 845         if (npt_enabled) {
 846                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 847                 kvm_enable_tdp();
 848         } else
 849                 kvm_disable_tdp();
 850
 851         return 0;
 852
 853 err:
 854         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 855         iopm_base = 0;
 856         return r;
 857 }
 858
 859 static __exit void svm_hardware_unsetup(void)
 860 {
 861         int cpu;
 862
 863         for_each_possible_cpu(cpu)
 864                 svm_cpu_uninit(cpu);
 865
 866         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 867         iopm_base = 0;
 868 }
 869
 870 static void init_seg(struct vmcb_seg *seg)
 871 {
 872         seg->selector = 0;
 873         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 874                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 875         seg->limit = 0xffff;
 876         seg->base = 0;
 877 }
 878
 879 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 880 {
 881         seg->selector = 0;
 882         seg->attrib = SVM_SELECTOR_P_MASK | type;
 883         seg->limit = 0xffff;
 884         seg->base = 0;
 885 }
 886
 887 static u64 __scale_tsc(u64 ratio, u64 tsc)
 888 {
 889         u64 mult, frac, _tsc;
 890
 891         mult  = ratio >> 32;
 892         frac  = ratio & ((1ULL << 32) - 1);
 893
 894         _tsc  = tsc;
 895         _tsc *= mult;
 896         _tsc += (tsc >> 32) * frac;
 897         _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
 898
 899         return _tsc;
 900 }
 901
 902 static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
 903 {
 904         struct vcpu_svm *svm = to_svm(vcpu);
 905         u64 _tsc = tsc;
 906
 907         if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
 908                 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
 909
 910         return _tsc;
 911 }
 912
 913 static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
 914 {
 915         struct vcpu_svm *svm = to_svm(vcpu);
 916         u64 ratio;
 917         u64 khz;
 918
 919         /* TSC scaling supported? */
 920         if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR))
 921                 return;
 922
 923         /* TSC-Scaling disabled or guest TSC same frequency as host TSC? */
 924         if (user_tsc_khz == 0) {
 925                 vcpu->arch.virtual_tsc_khz = 0;
 926                 svm->tsc_ratio = TSC_RATIO_DEFAULT;
 927                 return;
 928         }
 929
 930         khz = user_tsc_khz;
 931
 932         /* TSC scaling required  - calculate ratio */
 933         ratio = khz << 32;
 934         do_div(ratio, tsc_khz);
 935
 936         if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
 937                 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
 938                                 user_tsc_khz);
 939                 return;
 940         }
 941         vcpu->arch.virtual_tsc_khz = user_tsc_khz;
 942         svm->tsc_ratio             = ratio;
 943 }
 944
 945 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
 946 {
 947         struct vcpu_svm *svm = to_svm(vcpu);
 948         u64 g_tsc_offset = 0;
 949
 950         if (is_guest_mode(vcpu)) {
 951                 g_tsc_offset = svm->vmcb->control.tsc_offset -
 952                                svm->nested.hsave->control.tsc_offset;
 953                 svm->nested.hsave->control.tsc_offset = offset;
 954         }
 955
 956         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
 957
 958         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 959 }
 960
 961 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
 962 {
 963         struct vcpu_svm *svm = to_svm(vcpu);
 964
 965         svm->vmcb->control.tsc_offset += adjustment;
 966         if (is_guest_mode(vcpu))
 967                 svm->nested.hsave->control.tsc_offset += adjustment;
 968         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 969 }
 970
 971 static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
 972 {
 973         u64 tsc;
 974
 975         tsc = svm_scale_tsc(vcpu, native_read_tsc());
 976
 977         return target_tsc - tsc;
 978 }
 979
 980 static void init_vmcb(struct vcpu_svm *svm)
 981 {
 982         struct vmcb_control_area *control = &svm->vmcb->control;
 983         struct vmcb_save_area *save = &svm->vmcb->save;
 984
 985         svm->vcpu.fpu_active = 1;
 986         svm->vcpu.arch.hflags = 0;
 987
 988         set_cr_intercept(svm, INTERCEPT_CR0_READ);
 989         set_cr_intercept(svm, INTERCEPT_CR3_READ);
 990         set_cr_intercept(svm, INTERCEPT_CR4_READ);
 991         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
 992         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
 993         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
 994         set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
 995
 996         set_dr_intercept(svm, INTERCEPT_DR0_READ);
 997         set_dr_intercept(svm, INTERCEPT_DR1_READ);
 998         set_dr_intercept(svm, INTERCEPT_DR2_READ);
 999         set_dr_intercept(svm, INTERCEPT_DR3_READ);
1000         set_dr_intercept(svm, INTERCEPT_DR4_READ);
1001         set_dr_intercept(svm, INTERCEPT_DR5_READ);
1002         set_dr_intercept(svm, INTERCEPT_DR6_READ);
1003         set_dr_intercept(svm, INTERCEPT_DR7_READ);
1004
1005         set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
1006         set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
1007         set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
1008         set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
1009         set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
1010         set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
1011         set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
1012         set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
1013
1014         set_exception_intercept(svm, PF_VECTOR);
1015         set_exception_intercept(svm, UD_VECTOR);
1016         set_exception_intercept(svm, MC_VECTOR);
1017
1018         set_intercept(svm, INTERCEPT_INTR);
1019         set_intercept(svm, INTERCEPT_NMI);
1020         set_intercept(svm, INTERCEPT_SMI);
1021         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1022         set_intercept(svm, INTERCEPT_CPUID);
1023         set_intercept(svm, INTERCEPT_INVD);
1024         set_intercept(svm, INTERCEPT_HLT);
1025         set_intercept(svm, INTERCEPT_INVLPG);
1026         set_intercept(svm, INTERCEPT_INVLPGA);
1027         set_intercept(svm, INTERCEPT_IOIO_PROT);
1028         set_intercept(svm, INTERCEPT_MSR_PROT);
1029         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1030         set_intercept(svm, INTERCEPT_SHUTDOWN);
1031         set_intercept(svm, INTERCEPT_VMRUN);
1032         set_intercept(svm, INTERCEPT_VMMCALL);
1033         set_intercept(svm, INTERCEPT_VMLOAD);
1034         set_intercept(svm, INTERCEPT_VMSAVE);
1035         set_intercept(svm, INTERCEPT_STGI);
1036         set_intercept(svm, INTERCEPT_CLGI);
1037         set_intercept(svm, INTERCEPT_SKINIT);
1038         set_intercept(svm, INTERCEPT_WBINVD);
1039         set_intercept(svm, INTERCEPT_MONITOR);
1040         set_intercept(svm, INTERCEPT_MWAIT);
1041         set_intercept(svm, INTERCEPT_XSETBV);
1042
1043         control->iopm_base_pa = iopm_base;
1044         control->msrpm_base_pa = __pa(svm->msrpm);
1045         control->int_ctl = V_INTR_MASKING_MASK;
1046
1047         init_seg(&save->es);
1048         init_seg(&save->ss);
1049         init_seg(&save->ds);
1050         init_seg(&save->fs);
1051         init_seg(&save->gs);
1052
1053         save->cs.selector = 0xf000;
1054         /* Executable/Readable Code Segment */
1055         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1056                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1057         save->cs.limit = 0xffff;
1058         /*
1059          * cs.base should really be 0xffff0000, but vmx can't handle that, so
1060          * be consistent with it.
1061          *
1062          * Replace when we have real mode working for vmx.
1063          */
1064         save->cs.base = 0xf0000;
1065
1066         save->gdtr.limit = 0xffff;
1067         save->idtr.limit = 0xffff;
1068
1069         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1070         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1071
1072         svm_set_efer(&svm->vcpu, 0);
1073         save->dr6 = 0xffff0ff0;
1074         save->dr7 = 0x400;
1075         kvm_set_rflags(&svm->vcpu, 2);
1076         save->rip = 0x0000fff0;
1077         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1078
1079         /*
1080          * This is the guest-visible cr0 value.
1081          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1082          */
1083         svm->vcpu.arch.cr0 = 0;
1084         (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1085
1086         save->cr4 = X86_CR4_PAE;
1087         /* rdx = ?? */
1088
1089         if (npt_enabled) {
1090                 /* Setup VMCB for Nested Paging */
1091                 control->nested_ctl = 1;
1092                 clr_intercept(svm, INTERCEPT_INVLPG);
1093                 clr_exception_intercept(svm, PF_VECTOR);
1094                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1095                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1096                 save->g_pat = 0x0007040600070406ULL;
1097                 save->cr3 = 0;
1098                 save->cr4 = 0;
1099         }
1100         svm->asid_generation = 0;
1101
1102         svm->nested.vmcb = 0;
1103         svm->vcpu.arch.hflags = 0;
1104
1105         if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1106                 control->pause_filter_count = 3000;
1107                 set_intercept(svm, INTERCEPT_PAUSE);
1108         }
1109
1110         mark_all_dirty(svm->vmcb);
1111
1112         enable_gif(svm);
1113 }
1114
1115 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
1116 {
1117         struct vcpu_svm *svm = to_svm(vcpu);
1118
1119         init_vmcb(svm);
1120
1121         if (!kvm_vcpu_is_bsp(vcpu)) {
1122                 kvm_rip_write(vcpu, 0);
1123                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1124                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
1125         }
1126         vcpu->arch.regs_avail = ~0;
1127         vcpu->arch.regs_dirty = ~0;
1128
1129         return 0;
1130 }
1131
1132 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1133 {
1134         struct vcpu_svm *svm;
1135         struct page *page;
1136         struct page *msrpm_pages;
1137         struct page *hsave_page;
1138         struct page *nested_msrpm_pages;
1139         int err;
1140
1141         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1142         if (!svm) {
1143                 err = -ENOMEM;
1144                 goto out;
1145         }
1146
1147         svm->tsc_ratio = TSC_RATIO_DEFAULT;
1148
1149         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1150         if (err)
1151                 goto free_svm;
1152
1153         err = -ENOMEM;
1154         page = alloc_page(GFP_KERNEL);
1155         if (!page)
1156                 goto uninit;
1157
1158         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1159         if (!msrpm_pages)
1160                 goto free_page1;
1161
1162         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1163         if (!nested_msrpm_pages)
1164                 goto free_page2;
1165
1166         hsave_page = alloc_page(GFP_KERNEL);
1167         if (!hsave_page)
1168                 goto free_page3;
1169
1170         svm->nested.hsave = page_address(hsave_page);
1171
1172         svm->msrpm = page_address(msrpm_pages);
1173         svm_vcpu_init_msrpm(svm->msrpm);
1174
1175         svm->nested.msrpm = page_address(nested_msrpm_pages);
1176         svm_vcpu_init_msrpm(svm->nested.msrpm);
1177
1178         svm->vmcb = page_address(page);
1179         clear_page(svm->vmcb);
1180         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1181         svm->asid_generation = 0;
1182         init_vmcb(svm);
1183         kvm_write_tsc(&svm->vcpu, 0);
1184
1185         err = fx_init(&svm->vcpu);
1186         if (err)
1187                 goto free_page4;
1188
1189         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1190         if (kvm_vcpu_is_bsp(&svm->vcpu))
1191                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1192
1193         return &svm->vcpu;
1194
1195 free_page4:
1196         __free_page(hsave_page);
1197 free_page3:
1198         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1199 free_page2:
1200         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1201 free_page1:
1202         __free_page(page);
1203 uninit:
1204         kvm_vcpu_uninit(&svm->vcpu);
1205 free_svm:
1206         kmem_cache_free(kvm_vcpu_cache, svm);
1207 out:
1208         return ERR_PTR(err);
1209 }
1210
1211 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1212 {
1213         struct vcpu_svm *svm = to_svm(vcpu);
1214
1215         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1216         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1217         __free_page(virt_to_page(svm->nested.hsave));
1218         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1219         kvm_vcpu_uninit(vcpu);
1220         kmem_cache_free(kvm_vcpu_cache, svm);
1221 }
1222
1223 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1224 {
1225         struct vcpu_svm *svm = to_svm(vcpu);
1226         int i;
1227
1228         if (unlikely(cpu != vcpu->cpu)) {
1229                 svm->asid_generation = 0;
1230                 mark_all_dirty(svm->vmcb);
1231         }
1232
1233 #ifdef CONFIG_X86_64
1234         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1235 #endif
1236         savesegment(fs, svm->host.fs);
1237         savesegment(gs, svm->host.gs);
1238         svm->host.ldt = kvm_read_ldt();
1239
1240         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1241                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1242
1243         if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1244             svm->tsc_ratio != __get_cpu_var(current_tsc_ratio)) {
1245                 __get_cpu_var(current_tsc_ratio) = svm->tsc_ratio;
1246                 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1247         }
1248 }
1249
1250 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1251 {
1252         struct vcpu_svm *svm = to_svm(vcpu);
1253         int i;
1254
1255         ++vcpu->stat.host_state_reload;
1256         kvm_load_ldt(svm->host.ldt);
1257 #ifdef CONFIG_X86_64
1258         loadsegment(fs, svm->host.fs);
1259         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1260         load_gs_index(svm->host.gs);
1261 #else
1262 #ifdef CONFIG_X86_32_LAZY_GS
1263         loadsegment(gs, svm->host.gs);
1264 #endif
1265 #endif
1266         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1267                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1268 }
1269
1270 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1271 {
1272         return to_svm(vcpu)->vmcb->save.rflags;
1273 }
1274
1275 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1276 {
1277         to_svm(vcpu)->vmcb->save.rflags = rflags;
1278 }
1279
1280 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1281 {
1282         switch (reg) {
1283         case VCPU_EXREG_PDPTR:
1284                 BUG_ON(!npt_enabled);
1285                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1286                 break;
1287         default:
1288                 BUG();
1289         }
1290 }
1291
1292 static void svm_set_vintr(struct vcpu_svm *svm)
1293 {
1294         set_intercept(svm, INTERCEPT_VINTR);
1295 }
1296
1297 static void svm_clear_vintr(struct vcpu_svm *svm)
1298 {
1299         clr_intercept(svm, INTERCEPT_VINTR);
1300 }
1301
1302 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1303 {
1304         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1305
1306         switch (seg) {
1307         case VCPU_SREG_CS: return &save->cs;
1308         case VCPU_SREG_DS: return &save->ds;
1309         case VCPU_SREG_ES: return &save->es;
1310         case VCPU_SREG_FS: return &save->fs;
1311         case VCPU_SREG_GS: return &save->gs;
1312         case VCPU_SREG_SS: return &save->ss;
1313         case VCPU_SREG_TR: return &save->tr;
1314         case VCPU_SREG_LDTR: return &save->ldtr;
1315         }
1316         BUG();
1317         return NULL;
1318 }
1319
1320 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1321 {
1322         struct vmcb_seg *s = svm_seg(vcpu, seg);
1323
1324         return s->base;
1325 }
1326
1327 static void svm_get_segment(struct kvm_vcpu *vcpu,
1328                             struct kvm_segment *var, int seg)
1329 {
1330         struct vmcb_seg *s = svm_seg(vcpu, seg);
1331
1332         var->base = s->base;
1333         var->limit = s->limit;
1334         var->selector = s->selector;
1335         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1336         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1337         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1338         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1339         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1340         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1341         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1342         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1343
1344         /*
1345          * AMD's VMCB does not have an explicit unusable field, so emulate it
1346          * for cross vendor migration purposes by "not present"
1347          */
1348         var->unusable = !var->present || (var->type == 0);
1349
1350         switch (seg) {
1351         case VCPU_SREG_CS:
1352                 /*
1353                  * SVM always stores 0 for the 'G' bit in the CS selector in
1354                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1355                  * Intel's VMENTRY has a check on the 'G' bit.
1356                  */
1357                 var->g = s->limit > 0xfffff;
1358                 break;
1359         case VCPU_SREG_TR:
1360                 /*
1361                  * Work around a bug where the busy flag in the tr selector
1362                  * isn't exposed
1363                  */
1364                 var->type |= 0x2;
1365                 break;
1366         case VCPU_SREG_DS:
1367         case VCPU_SREG_ES:
1368         case VCPU_SREG_FS:
1369         case VCPU_SREG_GS:
1370                 /*
1371                  * The accessed bit must always be set in the segment
1372                  * descriptor cache, although it can be cleared in the
1373                  * descriptor, the cached bit always remains at 1. Since
1374                  * Intel has a check on this, set it here to support
1375                  * cross-vendor migration.
1376                  */
1377                 if (!var->unusable)
1378                         var->type |= 0x1;
1379                 break;
1380         case VCPU_SREG_SS:
1381                 /*
1382                  * On AMD CPUs sometimes the DB bit in the segment
1383                  * descriptor is left as 1, although the whole segment has
1384                  * been made unusable. Clear it here to pass an Intel VMX
1385                  * entry check when cross vendor migrating.
1386                  */
1387                 if (var->unusable)
1388                         var->db = 0;
1389                 break;
1390         }
1391 }
1392
1393 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1394 {
1395         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1396
1397         return save->cpl;
1398 }
1399
1400 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1401 {
1402         struct vcpu_svm *svm = to_svm(vcpu);
1403
1404         dt->size = svm->vmcb->save.idtr.limit;
1405         dt->address = svm->vmcb->save.idtr.base;
1406 }
1407
1408 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1409 {
1410         struct vcpu_svm *svm = to_svm(vcpu);
1411
1412         svm->vmcb->save.idtr.limit = dt->size;
1413         svm->vmcb->save.idtr.base = dt->address ;
1414         mark_dirty(svm->vmcb, VMCB_DT);
1415 }
1416
1417 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1418 {
1419         struct vcpu_svm *svm = to_svm(vcpu);
1420
1421         dt->size = svm->vmcb->save.gdtr.limit;
1422         dt->address = svm->vmcb->save.gdtr.base;
1423 }
1424
1425 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1426 {
1427         struct vcpu_svm *svm = to_svm(vcpu);
1428
1429         svm->vmcb->save.gdtr.limit = dt->size;
1430         svm->vmcb->save.gdtr.base = dt->address ;
1431         mark_dirty(svm->vmcb, VMCB_DT);
1432 }
1433
1434 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1435 {
1436 }
1437
1438 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1439 {
1440 }
1441
1442 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1443 {
1444 }
1445
1446 static void update_cr0_intercept(struct vcpu_svm *svm)
1447 {
1448         ulong gcr0 = svm->vcpu.arch.cr0;
1449         u64 *hcr0 = &svm->vmcb->save.cr0;
1450
1451         if (!svm->vcpu.fpu_active)
1452                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1453         else
1454                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1455                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1456
1457         mark_dirty(svm->vmcb, VMCB_CR);
1458
1459         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1460                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1461                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1462         } else {
1463                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1464                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1465         }
1466 }
1467
1468 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1469 {
1470         struct vcpu_svm *svm = to_svm(vcpu);
1471
1472 #ifdef CONFIG_X86_64
1473         if (vcpu->arch.efer & EFER_LME) {
1474                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1475                         vcpu->arch.efer |= EFER_LMA;
1476                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1477                 }
1478
1479                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1480                         vcpu->arch.efer &= ~EFER_LMA;
1481                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1482                 }
1483         }
1484 #endif
1485         vcpu->arch.cr0 = cr0;
1486
1487         if (!npt_enabled)
1488                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1489
1490         if (!vcpu->fpu_active)
1491                 cr0 |= X86_CR0_TS;
1492         /*
1493          * re-enable caching here because the QEMU bios
1494          * does not do it - this results in some delay at
1495          * reboot
1496          */
1497         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1498         svm->vmcb->save.cr0 = cr0;
1499         mark_dirty(svm->vmcb, VMCB_CR);
1500         update_cr0_intercept(svm);
1501 }
1502
1503 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1504 {
1505         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1506         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1507
1508         if (cr4 & X86_CR4_VMXE)
1509                 return 1;
1510
1511         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1512                 svm_flush_tlb(vcpu);
1513
1514         vcpu->arch.cr4 = cr4;
1515         if (!npt_enabled)
1516                 cr4 |= X86_CR4_PAE;
1517         cr4 |= host_cr4_mce;
1518         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1519         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1520         return 0;
1521 }
1522
1523 static void svm_set_segment(struct kvm_vcpu *vcpu,
1524                             struct kvm_segment *var, int seg)
1525 {
1526         struct vcpu_svm *svm = to_svm(vcpu);
1527         struct vmcb_seg *s = svm_seg(vcpu, seg);
1528
1529         s->base = var->base;
1530         s->limit = var->limit;
1531         s->selector = var->selector;
1532         if (var->unusable)
1533                 s->attrib = 0;
1534         else {
1535                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1536                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1537                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1538                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1539                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1540                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1541                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1542                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1543         }
1544         if (seg == VCPU_SREG_CS)
1545                 svm->vmcb->save.cpl
1546                         = (svm->vmcb->save.cs.attrib
1547                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1548
1549         mark_dirty(svm->vmcb, VMCB_SEG);
1550 }
1551
1552 static void update_db_intercept(struct kvm_vcpu *vcpu)
1553 {
1554         struct vcpu_svm *svm = to_svm(vcpu);
1555
1556         clr_exception_intercept(svm, DB_VECTOR);
1557         clr_exception_intercept(svm, BP_VECTOR);
1558
1559         if (svm->nmi_singlestep)
1560                 set_exception_intercept(svm, DB_VECTOR);
1561
1562         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1563                 if (vcpu->guest_debug &
1564                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1565                         set_exception_intercept(svm, DB_VECTOR);
1566                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1567                         set_exception_intercept(svm, BP_VECTOR);
1568         } else
1569                 vcpu->guest_debug = 0;
1570 }
1571
1572 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1573 {
1574         struct vcpu_svm *svm = to_svm(vcpu);
1575
1576         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1577                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1578         else
1579                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1580
1581         mark_dirty(svm->vmcb, VMCB_DR);
1582
1583         update_db_intercept(vcpu);
1584 }
1585
1586 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1587 {
1588         if (sd->next_asid > sd->max_asid) {
1589                 ++sd->asid_generation;
1590                 sd->next_asid = 1;
1591                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1592         }
1593
1594         svm->asid_generation = sd->asid_generation;
1595         svm->vmcb->control.asid = sd->next_asid++;
1596
1597         mark_dirty(svm->vmcb, VMCB_ASID);
1598 }
1599
1600 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1601 {
1602         struct vcpu_svm *svm = to_svm(vcpu);
1603
1604         svm->vmcb->save.dr7 = value;
1605         mark_dirty(svm->vmcb, VMCB_DR);
1606 }
1607
1608 static int pf_interception(struct vcpu_svm *svm)
1609 {
1610         u64 fault_address = svm->vmcb->control.exit_info_2;
1611         u32 error_code;
1612         int r = 1;
1613
1614         switch (svm->apf_reason) {
1615         default:
1616                 error_code = svm->vmcb->control.exit_info_1;
1617
1618                 trace_kvm_page_fault(fault_address, error_code);
1619                 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1620                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1621                 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1622                         svm->vmcb->control.insn_bytes,
1623                         svm->vmcb->control.insn_len);
1624                 break;
1625         case KVM_PV_REASON_PAGE_NOT_PRESENT:
1626                 svm->apf_reason = 0;
1627                 local_irq_disable();
1628                 kvm_async_pf_task_wait(fault_address);
1629                 local_irq_enable();
1630                 break;
1631         case KVM_PV_REASON_PAGE_READY:
1632                 svm->apf_reason = 0;
1633                 local_irq_disable();
1634                 kvm_async_pf_task_wake(fault_address);
1635                 local_irq_enable();
1636                 break;
1637         }
1638         return r;
1639 }
1640
1641 static int db_interception(struct vcpu_svm *svm)
1642 {
1643         struct kvm_run *kvm_run = svm->vcpu.run;
1644
1645         if (!(svm->vcpu.guest_debug &
1646               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1647                 !svm->nmi_singlestep) {
1648                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1649                 return 1;
1650         }
1651
1652         if (svm->nmi_singlestep) {
1653                 svm->nmi_singlestep = false;
1654                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1655                         svm->vmcb->save.rflags &=
1656                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1657                 update_db_intercept(&svm->vcpu);
1658         }
1659
1660         if (svm->vcpu.guest_debug &
1661             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1662                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1663                 kvm_run->debug.arch.pc =
1664                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1665                 kvm_run->debug.arch.exception = DB_VECTOR;
1666                 return 0;
1667         }
1668
1669         return 1;
1670 }
1671
1672 static int bp_interception(struct vcpu_svm *svm)
1673 {
1674         struct kvm_run *kvm_run = svm->vcpu.run;
1675
1676         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1677         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1678         kvm_run->debug.arch.exception = BP_VECTOR;
1679         return 0;
1680 }
1681
1682 static int ud_interception(struct vcpu_svm *svm)
1683 {
1684         int er;
1685
1686         er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1687         if (er != EMULATE_DONE)
1688                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1689         return 1;
1690 }
1691
1692 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1693 {
1694         struct vcpu_svm *svm = to_svm(vcpu);
1695
1696         clr_exception_intercept(svm, NM_VECTOR);
1697
1698         svm->vcpu.fpu_active = 1;
1699         update_cr0_intercept(svm);
1700 }
1701
1702 static int nm_interception(struct vcpu_svm *svm)
1703 {
1704         svm_fpu_activate(&svm->vcpu);
1705         return 1;
1706 }
1707
1708 static bool is_erratum_383(void)
1709 {
1710         int err, i;
1711         u64 value;
1712
1713         if (!erratum_383_found)
1714                 return false;
1715
1716         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1717         if (err)
1718                 return false;
1719
1720         /* Bit 62 may or may not be set for this mce */
1721         value &= ~(1ULL << 62);
1722
1723         if (value != 0xb600000000010015ULL)
1724                 return false;
1725
1726         /* Clear MCi_STATUS registers */
1727         for (i = 0; i < 6; ++i)
1728                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1729
1730         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1731         if (!err) {
1732                 u32 low, high;
1733
1734                 value &= ~(1ULL << 2);
1735                 low    = lower_32_bits(value);
1736                 high   = upper_32_bits(value);
1737
1738                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1739         }
1740
1741         /* Flush tlb to evict multi-match entries */
1742         __flush_tlb_all();
1743
1744         return true;
1745 }
1746
1747 static void svm_handle_mce(struct vcpu_svm *svm)
1748 {
1749         if (is_erratum_383()) {
1750                 /*
1751                  * Erratum 383 triggered. Guest state is corrupt so kill the
1752                  * guest.
1753                  */
1754                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1755
1756                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1757
1758                 return;
1759         }
1760
1761         /*
1762          * On an #MC intercept the MCE handler is not called automatically in
1763          * the host. So do it by hand here.
1764          */
1765         asm volatile (
1766                 "int $0x12\n");
1767         /* not sure if we ever come back to this point */
1768
1769         return;
1770 }
1771
1772 static int mc_interception(struct vcpu_svm *svm)
1773 {
1774         return 1;
1775 }
1776
1777 static int shutdown_interception(struct vcpu_svm *svm)
1778 {
1779         struct kvm_run *kvm_run = svm->vcpu.run;
1780
1781         /*
1782          * VMCB is undefined after a SHUTDOWN intercept
1783          * so reinitialize it.
1784          */
1785         clear_page(svm->vmcb);
1786         init_vmcb(svm);
1787
1788         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1789         return 0;
1790 }
1791
1792 static int io_interception(struct vcpu_svm *svm)
1793 {
1794         struct kvm_vcpu *vcpu = &svm->vcpu;
1795         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1796         int size, in, string;
1797         unsigned port;
1798
1799         ++svm->vcpu.stat.io_exits;
1800         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1801         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1802         if (string || in)
1803                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1804
1805         port = io_info >> 16;
1806         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1807         svm->next_rip = svm->vmcb->control.exit_info_2;
1808         skip_emulated_instruction(&svm->vcpu);
1809
1810         return kvm_fast_pio_out(vcpu, size, port);
1811 }
1812
1813 static int nmi_interception(struct vcpu_svm *svm)
1814 {
1815         return 1;
1816 }
1817
1818 static int intr_interception(struct vcpu_svm *svm)
1819 {
1820         ++svm->vcpu.stat.irq_exits;
1821         return 1;
1822 }
1823
1824 static int nop_on_interception(struct vcpu_svm *svm)
1825 {
1826         return 1;
1827 }
1828
1829 static int halt_interception(struct vcpu_svm *svm)
1830 {
1831         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1832         skip_emulated_instruction(&svm->vcpu);
1833         return kvm_emulate_halt(&svm->vcpu);
1834 }
1835
1836 static int vmmcall_interception(struct vcpu_svm *svm)
1837 {
1838         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1839         skip_emulated_instruction(&svm->vcpu);
1840         kvm_emulate_hypercall(&svm->vcpu);
1841         return 1;
1842 }
1843
1844 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1845 {
1846         struct vcpu_svm *svm = to_svm(vcpu);
1847
1848         return svm->nested.nested_cr3;
1849 }
1850
1851 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
1852 {
1853         struct vcpu_svm *svm = to_svm(vcpu);
1854         u64 cr3 = svm->nested.nested_cr3;
1855         u64 pdpte;
1856         int ret;
1857
1858         ret = kvm_read_guest_page(vcpu->kvm, gpa_to_gfn(cr3), &pdpte,
1859                                   offset_in_page(cr3) + index * 8, 8);
1860         if (ret)
1861                 return 0;
1862         return pdpte;
1863 }
1864
1865 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1866                                    unsigned long root)
1867 {
1868         struct vcpu_svm *svm = to_svm(vcpu);
1869
1870         svm->vmcb->control.nested_cr3 = root;
1871         mark_dirty(svm->vmcb, VMCB_NPT);
1872         svm_flush_tlb(vcpu);
1873 }
1874
1875 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1876                                        struct x86_exception *fault)
1877 {
1878         struct vcpu_svm *svm = to_svm(vcpu);
1879
1880         svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1881         svm->vmcb->control.exit_code_hi = 0;
1882         svm->vmcb->control.exit_info_1 = fault->error_code;
1883         svm->vmcb->control.exit_info_2 = fault->address;
1884
1885         nested_svm_vmexit(svm);
1886 }
1887
1888 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1889 {
1890         int r;
1891
1892         r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1893
1894         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
1895         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
1896         vcpu->arch.mmu.get_pdptr         = nested_svm_get_tdp_pdptr;
1897         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1898         vcpu->arch.mmu.shadow_root_level = get_npt_level();
1899         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
1900
1901         return r;
1902 }
1903
1904 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1905 {
1906         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1907 }
1908
1909 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1910 {
1911         if (!(svm->vcpu.arch.efer & EFER_SVME)
1912             || !is_paging(&svm->vcpu)) {
1913                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1914                 return 1;
1915         }
1916
1917         if (svm->vmcb->save.cpl) {
1918                 kvm_inject_gp(&svm->vcpu, 0);
1919                 return 1;
1920         }
1921
1922        return 0;
1923 }
1924
1925 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1926                                       bool has_error_code, u32 error_code)
1927 {
1928         int vmexit;
1929
1930         if (!is_guest_mode(&svm->vcpu))
1931                 return 0;
1932
1933         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1934         svm->vmcb->control.exit_code_hi = 0;
1935         svm->vmcb->control.exit_info_1 = error_code;
1936         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1937
1938         vmexit = nested_svm_intercept(svm);
1939         if (vmexit == NESTED_EXIT_DONE)
1940                 svm->nested.exit_required = true;
1941
1942         return vmexit;
1943 }
1944
1945 /* This function returns true if it is save to enable the irq window */
1946 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1947 {
1948         if (!is_guest_mode(&svm->vcpu))
1949                 return true;
1950
1951         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1952                 return true;
1953
1954         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1955                 return false;
1956
1957         /*
1958          * if vmexit was already requested (by intercepted exception
1959          * for instance) do not overwrite it with "external interrupt"
1960          * vmexit.
1961          */
1962         if (svm->nested.exit_required)
1963                 return false;
1964
1965         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
1966         svm->vmcb->control.exit_info_1 = 0;
1967         svm->vmcb->control.exit_info_2 = 0;
1968
1969         if (svm->nested.intercept & 1ULL) {
1970                 /*
1971                  * The #vmexit can't be emulated here directly because this
1972                  * code path runs with irqs and preemtion disabled. A
1973                  * #vmexit emulation might sleep. Only signal request for
1974                  * the #vmexit here.
1975                  */
1976                 svm->nested.exit_required = true;
1977                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1978                 return false;
1979         }
1980
1981         return true;
1982 }
1983
1984 /* This function returns true if it is save to enable the nmi window */
1985 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1986 {
1987         if (!is_guest_mode(&svm->vcpu))
1988                 return true;
1989
1990         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1991                 return true;
1992
1993         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1994         svm->nested.exit_required = true;
1995
1996         return false;
1997 }
1998
1999 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2000 {
2001         struct page *page;
2002
2003         might_sleep();
2004
2005         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
2006         if (is_error_page(page))
2007                 goto error;
2008
2009         *_page = page;
2010
2011         return kmap(page);
2012
2013 error:
2014         kvm_release_page_clean(page);
2015         kvm_inject_gp(&svm->vcpu, 0);
2016
2017         return NULL;
2018 }
2019
2020 static void nested_svm_unmap(struct page *page)
2021 {
2022         kunmap(page);
2023         kvm_release_page_dirty(page);
2024 }
2025
2026 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2027 {
2028         unsigned port;
2029         u8 val, bit;
2030         u64 gpa;
2031
2032         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2033                 return NESTED_EXIT_HOST;
2034
2035         port = svm->vmcb->control.exit_info_1 >> 16;
2036         gpa  = svm->nested.vmcb_iopm + (port / 8);
2037         bit  = port % 8;
2038         val  = 0;
2039
2040         if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
2041                 val &= (1 << bit);
2042
2043         return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2044 }
2045
2046 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2047 {
2048         u32 offset, msr, value;
2049         int write, mask;
2050
2051         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2052                 return NESTED_EXIT_HOST;
2053
2054         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2055         offset = svm_msrpm_offset(msr);
2056         write  = svm->vmcb->control.exit_info_1 & 1;
2057         mask   = 1 << ((2 * (msr & 0xf)) + write);
2058
2059         if (offset == MSR_INVALID)
2060                 return NESTED_EXIT_DONE;
2061
2062         /* Offset is in 32 bit units but need in 8 bit units */
2063         offset *= 4;
2064
2065         if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
2066                 return NESTED_EXIT_DONE;
2067
2068         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2069 }
2070
2071 static int nested_svm_exit_special(struct vcpu_svm *svm)
2072 {
2073         u32 exit_code = svm->vmcb->control.exit_code;
2074
2075         switch (exit_code) {
2076         case SVM_EXIT_INTR:
2077         case SVM_EXIT_NMI:
2078         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2079                 return NESTED_EXIT_HOST;
2080         case SVM_EXIT_NPF:
2081                 /* For now we are always handling NPFs when using them */
2082                 if (npt_enabled)
2083                         return NESTED_EXIT_HOST;
2084                 break;
2085         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2086                 /* When we're shadowing, trap PFs, but not async PF */
2087                 if (!npt_enabled && svm->apf_reason == 0)
2088                         return NESTED_EXIT_HOST;
2089                 break;
2090         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2091                 nm_interception(svm);
2092                 break;
2093         default:
2094                 break;
2095         }
2096
2097         return NESTED_EXIT_CONTINUE;
2098 }
2099
2100 /*
2101  * If this function returns true, this #vmexit was already handled
2102  */
2103 static int nested_svm_intercept(struct vcpu_svm *svm)
2104 {
2105         u32 exit_code = svm->vmcb->control.exit_code;
2106         int vmexit = NESTED_EXIT_HOST;
2107
2108         switch (exit_code) {
2109         case SVM_EXIT_MSR:
2110                 vmexit = nested_svm_exit_handled_msr(svm);
2111                 break;
2112         case SVM_EXIT_IOIO:
2113                 vmexit = nested_svm_intercept_ioio(svm);
2114                 break;
2115         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2116                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2117                 if (svm->nested.intercept_cr & bit)
2118                         vmexit = NESTED_EXIT_DONE;
2119                 break;
2120         }
2121         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2122                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2123                 if (svm->nested.intercept_dr & bit)
2124                         vmexit = NESTED_EXIT_DONE;
2125                 break;
2126         }
2127         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2128                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2129                 if (svm->nested.intercept_exceptions & excp_bits)
2130                         vmexit = NESTED_EXIT_DONE;
2131                 /* async page fault always cause vmexit */
2132                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2133                          svm->apf_reason != 0)
2134                         vmexit = NESTED_EXIT_DONE;
2135                 break;
2136         }
2137         case SVM_EXIT_ERR: {
2138                 vmexit = NESTED_EXIT_DONE;
2139                 break;
2140         }
2141         default: {
2142                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2143                 if (svm->nested.intercept & exit_bits)
2144                         vmexit = NESTED_EXIT_DONE;
2145         }
2146         }
2147
2148         return vmexit;
2149 }
2150
2151 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2152 {
2153         int vmexit;
2154
2155         vmexit = nested_svm_intercept(svm);
2156
2157         if (vmexit == NESTED_EXIT_DONE)
2158                 nested_svm_vmexit(svm);
2159
2160         return vmexit;
2161 }
2162
2163 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2164 {
2165         struct vmcb_control_area *dst  = &dst_vmcb->control;
2166         struct vmcb_control_area *from = &from_vmcb->control;
2167
2168         dst->intercept_cr         = from->intercept_cr;
2169         dst->intercept_dr         = from->intercept_dr;
2170         dst->intercept_exceptions = from->intercept_exceptions;
2171         dst->intercept            = from->intercept;
2172         dst->iopm_base_pa         = from->iopm_base_pa;
2173         dst->msrpm_base_pa        = from->msrpm_base_pa;
2174         dst->tsc_offset           = from->tsc_offset;
2175         dst->asid                 = from->asid;
2176         dst->tlb_ctl              = from->tlb_ctl;
2177         dst->int_ctl              = from->int_ctl;
2178         dst->int_vector           = from->int_vector;
2179         dst->int_state            = from->int_state;
2180         dst->exit_code            = from->exit_code;
2181         dst->exit_code_hi         = from->exit_code_hi;
2182         dst->exit_info_1          = from->exit_info_1;
2183         dst->exit_info_2          = from->exit_info_2;
2184         dst->exit_int_info        = from->exit_int_info;
2185         dst->exit_int_info_err    = from->exit_int_info_err;
2186         dst->nested_ctl           = from->nested_ctl;
2187         dst->event_inj            = from->event_inj;
2188         dst->event_inj_err        = from->event_inj_err;
2189         dst->nested_cr3           = from->nested_cr3;
2190         dst->lbr_ctl              = from->lbr_ctl;
2191 }
2192
2193 static int nested_svm_vmexit(struct vcpu_svm *svm)
2194 {
2195         struct vmcb *nested_vmcb;
2196         struct vmcb *hsave = svm->nested.hsave;
2197         struct vmcb *vmcb = svm->vmcb;
2198         struct page *page;
2199
2200         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2201                                        vmcb->control.exit_info_1,
2202                                        vmcb->control.exit_info_2,
2203                                        vmcb->control.exit_int_info,
2204                                        vmcb->control.exit_int_info_err,
2205                                        KVM_ISA_SVM);
2206
2207         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2208         if (!nested_vmcb)
2209                 return 1;
2210
2211         /* Exit Guest-Mode */
2212         leave_guest_mode(&svm->vcpu);
2213         svm->nested.vmcb = 0;
2214
2215         /* Give the current vmcb to the guest */
2216         disable_gif(svm);
2217
2218         nested_vmcb->save.es     = vmcb->save.es;
2219         nested_vmcb->save.cs     = vmcb->save.cs;
2220         nested_vmcb->save.ss     = vmcb->save.ss;
2221         nested_vmcb->save.ds     = vmcb->save.ds;
2222         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
2223         nested_vmcb->save.idtr   = vmcb->save.idtr;
2224         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
2225         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
2226         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
2227         nested_vmcb->save.cr2    = vmcb->save.cr2;
2228         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
2229         nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2230         nested_vmcb->save.rip    = vmcb->save.rip;
2231         nested_vmcb->save.rsp    = vmcb->save.rsp;
2232         nested_vmcb->save.rax    = vmcb->save.rax;
2233         nested_vmcb->save.dr7    = vmcb->save.dr7;
2234         nested_vmcb->save.dr6    = vmcb->save.dr6;
2235         nested_vmcb->save.cpl    = vmcb->save.cpl;
2236
2237         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
2238         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
2239         nested_vmcb->control.int_state         = vmcb->control.int_state;
2240         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
2241         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
2242         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
2243         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
2244         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
2245         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2246         nested_vmcb->control.next_rip          = vmcb->control.next_rip;
2247
2248         /*
2249          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2250          * to make sure that we do not lose injected events. So check event_inj
2251          * here and copy it to exit_int_info if it is valid.
2252          * Exit_int_info and event_inj can't be both valid because the case
2253          * below only happens on a VMRUN instruction intercept which has
2254          * no valid exit_int_info set.
2255          */
2256         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2257                 struct vmcb_control_area *nc = &nested_vmcb->control;
2258
2259                 nc->exit_int_info     = vmcb->control.event_inj;
2260                 nc->exit_int_info_err = vmcb->control.event_inj_err;
2261         }
2262
2263         nested_vmcb->control.tlb_ctl           = 0;
2264         nested_vmcb->control.event_inj         = 0;
2265         nested_vmcb->control.event_inj_err     = 0;
2266
2267         /* We always set V_INTR_MASKING and remember the old value in hflags */
2268         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2269                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2270
2271         /* Restore the original control entries */
2272         copy_vmcb_control_area(vmcb, hsave);
2273
2274         kvm_clear_exception_queue(&svm->vcpu);
2275         kvm_clear_interrupt_queue(&svm->vcpu);
2276
2277         svm->nested.nested_cr3 = 0;
2278
2279         /* Restore selected save entries */
2280         svm->vmcb->save.es = hsave->save.es;
2281         svm->vmcb->save.cs = hsave->save.cs;
2282         svm->vmcb->save.ss = hsave->save.ss;
2283         svm->vmcb->save.ds = hsave->save.ds;
2284         svm->vmcb->save.gdtr = hsave->save.gdtr;
2285         svm->vmcb->save.idtr = hsave->save.idtr;
2286         kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2287         svm_set_efer(&svm->vcpu, hsave->save.efer);
2288         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2289         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2290         if (npt_enabled) {
2291                 svm->vmcb->save.cr3 = hsave->save.cr3;
2292                 svm->vcpu.arch.cr3 = hsave->save.cr3;
2293         } else {
2294                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2295         }
2296         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2297         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2298         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2299         svm->vmcb->save.dr7 = 0;
2300         svm->vmcb->save.cpl = 0;
2301         svm->vmcb->control.exit_int_info = 0;
2302
2303         mark_all_dirty(svm->vmcb);
2304
2305         nested_svm_unmap(page);
2306
2307         nested_svm_uninit_mmu_context(&svm->vcpu);
2308         kvm_mmu_reset_context(&svm->vcpu);
2309         kvm_mmu_load(&svm->vcpu);
2310
2311         return 0;
2312 }
2313
2314 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2315 {
2316         /*
2317          * This function merges the msr permission bitmaps of kvm and the
2318          * nested vmcb. It is omptimized in that it only merges the parts where
2319          * the kvm msr permission bitmap may contain zero bits
2320          */
2321         int i;
2322
2323         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2324                 return true;
2325
2326         for (i = 0; i < MSRPM_OFFSETS; i++) {
2327                 u32 value, p;
2328                 u64 offset;
2329
2330                 if (msrpm_offsets[i] == 0xffffffff)
2331                         break;
2332
2333                 p      = msrpm_offsets[i];
2334                 offset = svm->nested.vmcb_msrpm + (p * 4);
2335
2336                 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2337                         return false;
2338
2339                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2340         }
2341
2342         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2343
2344         return true;
2345 }
2346
2347 static bool nested_vmcb_checks(struct vmcb *vmcb)
2348 {
2349         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2350                 return false;
2351
2352         if (vmcb->control.asid == 0)
2353                 return false;
2354
2355         if (vmcb->control.nested_ctl && !npt_enabled)
2356                 return false;
2357
2358         return true;
2359 }
2360
2361 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2362 {
2363         struct vmcb *nested_vmcb;
2364         struct vmcb *hsave = svm->nested.hsave;
2365         struct vmcb *vmcb = svm->vmcb;
2366         struct page *page;
2367         u64 vmcb_gpa;
2368
2369         vmcb_gpa = svm->vmcb->save.rax;
2370
2371         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2372         if (!nested_vmcb)
2373                 return false;
2374
2375         if (!nested_vmcb_checks(nested_vmcb)) {
2376                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
2377                 nested_vmcb->control.exit_code_hi = 0;
2378                 nested_vmcb->control.exit_info_1  = 0;
2379                 nested_vmcb->control.exit_info_2  = 0;
2380
2381                 nested_svm_unmap(page);
2382
2383                 return false;
2384         }
2385
2386         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2387                                nested_vmcb->save.rip,
2388                                nested_vmcb->control.int_ctl,
2389                                nested_vmcb->control.event_inj,
2390                                nested_vmcb->control.nested_ctl);
2391
2392         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2393                                     nested_vmcb->control.intercept_cr >> 16,
2394                                     nested_vmcb->control.intercept_exceptions,
2395                                     nested_vmcb->control.intercept);
2396
2397         /* Clear internal status */
2398         kvm_clear_exception_queue(&svm->vcpu);
2399         kvm_clear_interrupt_queue(&svm->vcpu);
2400
2401         /*
2402          * Save the old vmcb, so we don't need to pick what we save, but can
2403          * restore everything when a VMEXIT occurs
2404          */
2405         hsave->save.es     = vmcb->save.es;
2406         hsave->save.cs     = vmcb->save.cs;
2407         hsave->save.ss     = vmcb->save.ss;
2408         hsave->save.ds     = vmcb->save.ds;
2409         hsave->save.gdtr   = vmcb->save.gdtr;
2410         hsave->save.idtr   = vmcb->save.idtr;
2411         hsave->save.efer   = svm->vcpu.arch.efer;
2412         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2413         hsave->save.cr4    = svm->vcpu.arch.cr4;
2414         hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2415         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
2416         hsave->save.rsp    = vmcb->save.rsp;
2417         hsave->save.rax    = vmcb->save.rax;
2418         if (npt_enabled)
2419                 hsave->save.cr3    = vmcb->save.cr3;
2420         else
2421                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
2422
2423         copy_vmcb_control_area(hsave, vmcb);
2424
2425         if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2426                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2427         else
2428                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2429
2430         if (nested_vmcb->control.nested_ctl) {
2431                 kvm_mmu_unload(&svm->vcpu);
2432                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2433                 nested_svm_init_mmu_context(&svm->vcpu);
2434         }
2435
2436         /* Load the nested guest state */
2437         svm->vmcb->save.es = nested_vmcb->save.es;
2438         svm->vmcb->save.cs = nested_vmcb->save.cs;
2439         svm->vmcb->save.ss = nested_vmcb->save.ss;
2440         svm->vmcb->save.ds = nested_vmcb->save.ds;
2441         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2442         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2443         kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2444         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2445         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2446         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2447         if (npt_enabled) {
2448                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2449                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2450         } else
2451                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2452
2453         /* Guest paging mode is active - reset mmu */
2454         kvm_mmu_reset_context(&svm->vcpu);
2455
2456         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2457         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2458         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2459         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2460
2461         /* In case we don't even reach vcpu_run, the fields are not updated */
2462         svm->vmcb->save.rax = nested_vmcb->save.rax;
2463         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2464         svm->vmcb->save.rip = nested_vmcb->save.rip;
2465         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2466         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2467         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2468
2469         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2470         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2471
2472         /* cache intercepts */
2473         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
2474         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
2475         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2476         svm->nested.intercept            = nested_vmcb->control.intercept;
2477
2478         svm_flush_tlb(&svm->vcpu);
2479         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2480         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2481                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2482         else
2483                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2484
2485         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2486                 /* We only want the cr8 intercept bits of the guest */
2487                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2488                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2489         }
2490
2491         /* We don't want to see VMMCALLs from a nested guest */
2492         clr_intercept(svm, INTERCEPT_VMMCALL);
2493
2494         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2495         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2496         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2497         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2498         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2499         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2500
2501         nested_svm_unmap(page);
2502
2503         /* Enter Guest-Mode */
2504         enter_guest_mode(&svm->vcpu);
2505
2506         /*
2507          * Merge guest and host intercepts - must be called  with vcpu in
2508          * guest-mode to take affect here
2509          */
2510         recalc_intercepts(svm);
2511
2512         svm->nested.vmcb = vmcb_gpa;
2513
2514         enable_gif(svm);
2515
2516         mark_all_dirty(svm->vmcb);
2517
2518         return true;
2519 }
2520
2521 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2522 {
2523         to_vmcb->save.fs = from_vmcb->save.fs;
2524         to_vmcb->save.gs = from_vmcb->save.gs;
2525         to_vmcb->save.tr = from_vmcb->save.tr;
2526         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2527         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2528         to_vmcb->save.star = from_vmcb->save.star;
2529         to_vmcb->save.lstar = from_vmcb->save.lstar;
2530         to_vmcb->save.cstar = from_vmcb->save.cstar;
2531         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2532         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2533         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2534         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2535 }
2536
2537 static int vmload_interception(struct vcpu_svm *svm)
2538 {
2539         struct vmcb *nested_vmcb;
2540         struct page *page;
2541
2542         if (nested_svm_check_permissions(svm))
2543                 return 1;
2544
2545         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2546         if (!nested_vmcb)
2547                 return 1;
2548
2549         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2550         skip_emulated_instruction(&svm->vcpu);
2551
2552         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2553         nested_svm_unmap(page);
2554
2555         return 1;
2556 }
2557
2558 static int vmsave_interception(struct vcpu_svm *svm)
2559 {
2560         struct vmcb *nested_vmcb;
2561         struct page *page;
2562
2563         if (nested_svm_check_permissions(svm))
2564                 return 1;
2565
2566         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2567         if (!nested_vmcb)
2568                 return 1;
2569
2570         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2571         skip_emulated_instruction(&svm->vcpu);
2572
2573         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2574         nested_svm_unmap(page);
2575
2576         return 1;
2577 }
2578
2579 static int vmrun_interception(struct vcpu_svm *svm)
2580 {
2581         if (nested_svm_check_permissions(svm))
2582                 return 1;
2583
2584         /* Save rip after vmrun instruction */
2585         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2586
2587         if (!nested_svm_vmrun(svm))
2588                 return 1;
2589
2590         if (!nested_svm_vmrun_msrpm(svm))
2591                 goto failed;
2592
2593         return 1;
2594
2595 failed:
2596
2597         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
2598         svm->vmcb->control.exit_code_hi = 0;
2599         svm->vmcb->control.exit_info_1  = 0;
2600         svm->vmcb->control.exit_info_2  = 0;
2601
2602         nested_svm_vmexit(svm);
2603
2604         return 1;
2605 }
2606
2607 static int stgi_interception(struct vcpu_svm *svm)
2608 {
2609         if (nested_svm_check_permissions(svm))
2610                 return 1;
2611
2612         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2613         skip_emulated_instruction(&svm->vcpu);
2614         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2615
2616         enable_gif(svm);
2617
2618         return 1;
2619 }
2620
2621 static int clgi_interception(struct vcpu_svm *svm)
2622 {
2623         if (nested_svm_check_permissions(svm))
2624                 return 1;
2625
2626         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2627         skip_emulated_instruction(&svm->vcpu);
2628
2629         disable_gif(svm);
2630
2631         /* After a CLGI no interrupts should come */
2632         svm_clear_vintr(svm);
2633         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2634
2635         mark_dirty(svm->vmcb, VMCB_INTR);
2636
2637         return 1;
2638 }
2639
2640 static int invlpga_interception(struct vcpu_svm *svm)
2641 {
2642         struct kvm_vcpu *vcpu = &svm->vcpu;
2643
2644         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2645                           vcpu->arch.regs[VCPU_REGS_RAX]);
2646
2647         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2648         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2649
2650         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2651         skip_emulated_instruction(&svm->vcpu);
2652         return 1;
2653 }
2654
2655 static int skinit_interception(struct vcpu_svm *svm)
2656 {
2657         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2658
2659         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2660         return 1;
2661 }
2662
2663 static int xsetbv_interception(struct vcpu_svm *svm)
2664 {
2665         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2666         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2667
2668         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2669                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2670                 skip_emulated_instruction(&svm->vcpu);
2671         }
2672
2673         return 1;
2674 }
2675
2676 static int invalid_op_interception(struct vcpu_svm *svm)
2677 {
2678         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2679         return 1;
2680 }
2681
2682 static int task_switch_interception(struct vcpu_svm *svm)
2683 {
2684         u16 tss_selector;
2685         int reason;
2686         int int_type = svm->vmcb->control.exit_int_info &
2687                 SVM_EXITINTINFO_TYPE_MASK;
2688         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2689         uint32_t type =
2690                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2691         uint32_t idt_v =
2692                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2693         bool has_error_code = false;
2694         u32 error_code = 0;
2695
2696         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2697
2698         if (svm->vmcb->control.exit_info_2 &
2699             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2700                 reason = TASK_SWITCH_IRET;
2701         else if (svm->vmcb->control.exit_info_2 &
2702                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2703                 reason = TASK_SWITCH_JMP;
2704         else if (idt_v)
2705                 reason = TASK_SWITCH_GATE;
2706         else
2707                 reason = TASK_SWITCH_CALL;
2708
2709         if (reason == TASK_SWITCH_GATE) {
2710                 switch (type) {
2711                 case SVM_EXITINTINFO_TYPE_NMI:
2712                         svm->vcpu.arch.nmi_injected = false;
2713                         break;
2714                 case SVM_EXITINTINFO_TYPE_EXEPT:
2715                         if (svm->vmcb->control.exit_info_2 &
2716                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2717                                 has_error_code = true;
2718                                 error_code =
2719                                         (u32)svm->vmcb->control.exit_info_2;
2720                         }
2721                         kvm_clear_exception_queue(&svm->vcpu);
2722                         break;
2723                 case SVM_EXITINTINFO_TYPE_INTR:
2724                         kvm_clear_interrupt_queue(&svm->vcpu);
2725                         break;
2726                 default:
2727                         break;
2728                 }
2729         }
2730
2731         if (reason != TASK_SWITCH_GATE ||
2732             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2733             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2734              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2735                 skip_emulated_instruction(&svm->vcpu);
2736
2737         if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2738                                 has_error_code, error_code) == EMULATE_FAIL) {
2739                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2740                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2741                 svm->vcpu.run->internal.ndata = 0;
2742                 return 0;
2743         }
2744         return 1;
2745 }
2746
2747 static int cpuid_interception(struct vcpu_svm *svm)
2748 {
2749         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2750         kvm_emulate_cpuid(&svm->vcpu);
2751         return 1;
2752 }
2753
2754 static int iret_interception(struct vcpu_svm *svm)
2755 {
2756         ++svm->vcpu.stat.nmi_window_exits;
2757         clr_intercept(svm, INTERCEPT_IRET);
2758         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2759         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2760         return 1;
2761 }
2762
2763 static int invlpg_interception(struct vcpu_svm *svm)
2764 {
2765         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2766                 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2767
2768         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2769         skip_emulated_instruction(&svm->vcpu);
2770         return 1;
2771 }
2772
2773 static int emulate_on_interception(struct vcpu_svm *svm)
2774 {
2775         return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2776 }
2777
2778 bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val)
2779 {
2780         unsigned long cr0 = svm->vcpu.arch.cr0;
2781         bool ret = false;
2782         u64 intercept;
2783
2784         intercept = svm->nested.intercept;
2785
2786         if (!is_guest_mode(&svm->vcpu) ||
2787             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2788                 return false;
2789
2790         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2791         val &= ~SVM_CR0_SELECTIVE_MASK;
2792
2793         if (cr0 ^ val) {
2794                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2795                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2796         }
2797
2798         return ret;
2799 }
2800
2801 #define CR_VALID (1ULL << 63)
2802
2803 static int cr_interception(struct vcpu_svm *svm)
2804 {
2805         int reg, cr;
2806         unsigned long val;
2807         int err;
2808
2809         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2810                 return emulate_on_interception(svm);
2811
2812         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2813                 return emulate_on_interception(svm);
2814
2815         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2816         cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2817
2818         err = 0;
2819         if (cr >= 16) { /* mov to cr */
2820                 cr -= 16;
2821                 val = kvm_register_read(&svm->vcpu, reg);
2822                 switch (cr) {
2823                 case 0:
2824                         if (!check_selective_cr0_intercepted(svm, val))
2825                                 err = kvm_set_cr0(&svm->vcpu, val);
2826                         else
2827                                 return 1;
2828
2829                         break;
2830                 case 3:
2831                         err = kvm_set_cr3(&svm->vcpu, val);
2832                         break;
2833                 case 4:
2834                         err = kvm_set_cr4(&svm->vcpu, val);
2835                         break;
2836                 case 8:
2837                         err = kvm_set_cr8(&svm->vcpu, val);
2838                         break;
2839                 default:
2840                         WARN(1, "unhandled write to CR%d", cr);
2841                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2842                         return 1;
2843                 }
2844         } else { /* mov from cr */
2845                 switch (cr) {
2846                 case 0:
2847                         val = kvm_read_cr0(&svm->vcpu);
2848                         break;
2849                 case 2:
2850                         val = svm->vcpu.arch.cr2;
2851                         break;
2852                 case 3:
2853                         val = kvm_read_cr3(&svm->vcpu);
2854                         break;
2855                 case 4:
2856                         val = kvm_read_cr4(&svm->vcpu);
2857                         break;
2858                 case 8:
2859                         val = kvm_get_cr8(&svm->vcpu);
2860                         break;
2861                 default:
2862                         WARN(1, "unhandled read from CR%d", cr);
2863                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2864                         return 1;
2865                 }
2866                 kvm_register_write(&svm->vcpu, reg, val);
2867         }
2868         kvm_complete_insn_gp(&svm->vcpu, err);
2869
2870         return 1;
2871 }
2872
2873 static int dr_interception(struct vcpu_svm *svm)
2874 {
2875         int reg, dr;
2876         unsigned long val;
2877         int err;
2878
2879         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2880                 return emulate_on_interception(svm);
2881
2882         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2883         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2884
2885         if (dr >= 16) { /* mov to DRn */
2886                 val = kvm_register_read(&svm->vcpu, reg);
2887                 kvm_set_dr(&svm->vcpu, dr - 16, val);
2888         } else {
2889                 err = kvm_get_dr(&svm->vcpu, dr, &val);
2890                 if (!err)
2891                         kvm_register_write(&svm->vcpu, reg, val);
2892         }
2893
2894         skip_emulated_instruction(&svm->vcpu);
2895
2896         return 1;
2897 }
2898
2899 static int cr8_write_interception(struct vcpu_svm *svm)
2900 {
2901         struct kvm_run *kvm_run = svm->vcpu.run;
2902         int r;
2903
2904         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2905         /* instruction emulation calls kvm_set_cr8() */
2906         r = cr_interception(svm);
2907         if (irqchip_in_kernel(svm->vcpu.kvm))
2908                 return r;
2909         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2910                 return r;
2911         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2912         return 0;
2913 }
2914
2915 u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu)
2916 {
2917         struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
2918         return vmcb->control.tsc_offset +
2919                 svm_scale_tsc(vcpu, native_read_tsc());
2920 }
2921
2922 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2923 {
2924         struct vcpu_svm *svm = to_svm(vcpu);
2925
2926         switch (ecx) {
2927         case MSR_IA32_TSC: {
2928                 *data = svm->vmcb->control.tsc_offset +
2929                         svm_scale_tsc(vcpu, native_read_tsc());
2930
2931                 break;
2932         }
2933         case MSR_STAR:
2934                 *data = svm->vmcb->save.star;
2935                 break;
2936 #ifdef CONFIG_X86_64
2937         case MSR_LSTAR:
2938                 *data = svm->vmcb->save.lstar;
2939                 break;
2940         case MSR_CSTAR:
2941                 *data = svm->vmcb->save.cstar;
2942                 break;
2943         case MSR_KERNEL_GS_BASE:
2944                 *data = svm->vmcb->save.kernel_gs_base;
2945                 break;
2946         case MSR_SYSCALL_MASK:
2947                 *data = svm->vmcb->save.sfmask;
2948                 break;
2949 #endif
2950         case MSR_IA32_SYSENTER_CS:
2951                 *data = svm->vmcb->save.sysenter_cs;
2952                 break;
2953         case MSR_IA32_SYSENTER_EIP:
2954                 *data = svm->sysenter_eip;
2955                 break;
2956         case MSR_IA32_SYSENTER_ESP:
2957                 *data = svm->sysenter_esp;
2958                 break;
2959         /*
2960          * Nobody will change the following 5 values in the VMCB so we can
2961          * safely return them on rdmsr. They will always be 0 until LBRV is
2962          * implemented.
2963          */
2964         case MSR_IA32_DEBUGCTLMSR:
2965                 *data = svm->vmcb->save.dbgctl;
2966                 break;
2967         case MSR_IA32_LASTBRANCHFROMIP:
2968                 *data = svm->vmcb->save.br_from;
2969                 break;
2970         case MSR_IA32_LASTBRANCHTOIP:
2971                 *data = svm->vmcb->save.br_to;
2972                 break;
2973         case MSR_IA32_LASTINTFROMIP:
2974                 *data = svm->vmcb->save.last_excp_from;
2975                 break;
2976         case MSR_IA32_LASTINTTOIP:
2977                 *data = svm->vmcb->save.last_excp_to;
2978                 break;
2979         case MSR_VM_HSAVE_PA:
2980                 *data = svm->nested.hsave_msr;
2981                 break;
2982         case MSR_VM_CR:
2983                 *data = svm->nested.vm_cr_msr;
2984                 break;
2985         case MSR_IA32_UCODE_REV:
2986                 *data = 0x01000065;
2987                 break;
2988         default:
2989                 return kvm_get_msr_common(vcpu, ecx, data);
2990         }
2991         return 0;
2992 }
2993
2994 static int rdmsr_interception(struct vcpu_svm *svm)
2995 {
2996         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2997         u64 data;
2998
2999         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
3000                 trace_kvm_msr_read_ex(ecx);
3001                 kvm_inject_gp(&svm->vcpu, 0);
3002         } else {
3003                 trace_kvm_msr_read(ecx, data);
3004
3005                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
3006                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
3007                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3008                 skip_emulated_instruction(&svm->vcpu);
3009         }
3010         return 1;
3011 }
3012
3013 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3014 {
3015         struct vcpu_svm *svm = to_svm(vcpu);
3016         int svm_dis, chg_mask;
3017
3018         if (data & ~SVM_VM_CR_VALID_MASK)
3019                 return 1;
3020
3021         chg_mask = SVM_VM_CR_VALID_MASK;
3022
3023         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3024                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3025
3026         svm->nested.vm_cr_msr &= ~chg_mask;
3027         svm->nested.vm_cr_msr |= (data & chg_mask);
3028
3029         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3030
3031         /* check for svm_disable while efer.svme is set */
3032         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3033                 return 1;
3034
3035         return 0;
3036 }
3037
3038 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
3039 {
3040         struct vcpu_svm *svm = to_svm(vcpu);
3041
3042         switch (ecx) {
3043         case MSR_IA32_TSC:
3044                 kvm_write_tsc(vcpu, data);
3045                 break;
3046         case MSR_STAR:
3047                 svm->vmcb->save.star = data;
3048                 break;
3049 #ifdef CONFIG_X86_64
3050         case MSR_LSTAR:
3051                 svm->vmcb->save.lstar = data;
3052                 break;
3053         case MSR_CSTAR:
3054                 svm->vmcb->save.cstar = data;
3055                 break;
3056         case MSR_KERNEL_GS_BASE:
3057                 svm->vmcb->save.kernel_gs_base = data;
3058                 break;
3059         case MSR_SYSCALL_MASK:
3060                 svm->vmcb->save.sfmask = data;
3061                 break;
3062 #endif
3063         case MSR_IA32_SYSENTER_CS:
3064                 svm->vmcb->save.sysenter_cs = data;
3065                 break;
3066         case MSR_IA32_SYSENTER_EIP:
3067                 svm->sysenter_eip = data;
3068                 svm->vmcb->save.sysenter_eip = data;
3069                 break;
3070         case MSR_IA32_SYSENTER_ESP:
3071                 svm->sysenter_esp = data;
3072                 svm->vmcb->save.sysenter_esp = data;
3073                 break;
3074         case MSR_IA32_DEBUGCTLMSR:
3075                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3076                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3077                                         __func__, data);
3078                         break;
3079                 }
3080                 if (data & DEBUGCTL_RESERVED_BITS)
3081                         return 1;
3082
3083                 svm->vmcb->save.dbgctl = data;
3084                 mark_dirty(svm->vmcb, VMCB_LBR);
3085                 if (data & (1ULL<<0))
3086                         svm_enable_lbrv(svm);
3087                 else
3088                         svm_disable_lbrv(svm);
3089                 break;
3090         case MSR_VM_HSAVE_PA:
3091                 svm->nested.hsave_msr = data;
3092                 break;
3093         case MSR_VM_CR:
3094                 return svm_set_vm_cr(vcpu, data);
3095         case MSR_VM_IGNNE:
3096                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3097                 break;
3098         default:
3099                 return kvm_set_msr_common(vcpu, ecx, data);
3100         }
3101         return 0;
3102 }
3103
3104 static int wrmsr_interception(struct vcpu_svm *svm)
3105 {
3106         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3107         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
3108                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3109
3110
3111         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3112         if (kvm_set_msr(&svm->vcpu, ecx, data)) {
3113                 trace_kvm_msr_write_ex(ecx, data);
3114                 kvm_inject_gp(&svm->vcpu, 0);
3115         } else {
3116                 trace_kvm_msr_write(ecx, data);
3117                 skip_emulated_instruction(&svm->vcpu);
3118         }
3119         return 1;
3120 }
3121
3122 static int msr_interception(struct vcpu_svm *svm)
3123 {
3124         if (svm->vmcb->control.exit_info_1)
3125                 return wrmsr_interception(svm);
3126         else
3127                 return rdmsr_interception(svm);
3128 }
3129
3130 static int interrupt_window_interception(struct vcpu_svm *svm)
3131 {
3132         struct kvm_run *kvm_run = svm->vcpu.run;
3133
3134         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3135         svm_clear_vintr(svm);
3136         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3137         mark_dirty(svm->vmcb, VMCB_INTR);
3138         /*
3139          * If the user space waits to inject interrupts, exit as soon as
3140          * possible
3141          */
3142         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3143             kvm_run->request_interrupt_window &&
3144             !kvm_cpu_has_interrupt(&svm->vcpu)) {
3145                 ++svm->vcpu.stat.irq_window_exits;
3146                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3147                 return 0;
3148         }
3149
3150         return 1;
3151 }
3152
3153 static int pause_interception(struct vcpu_svm *svm)
3154 {
3155         kvm_vcpu_on_spin(&(svm->vcpu));
3156         return 1;
3157 }
3158
3159 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
3160         [SVM_EXIT_READ_CR0]                     = cr_interception,
3161         [SVM_EXIT_READ_CR3]                     = cr_interception,
3162         [SVM_EXIT_READ_CR4]                     = cr_interception,
3163         [SVM_EXIT_READ_CR8]                     = cr_interception,
3164         [SVM_EXIT_CR0_SEL_WRITE]                = emulate_on_interception,
3165         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
3166         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
3167         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
3168         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
3169         [SVM_EXIT_READ_DR0]                     = dr_interception,
3170         [SVM_EXIT_READ_DR1]                     = dr_interception,
3171         [SVM_EXIT_READ_DR2]                     = dr_interception,
3172         [SVM_EXIT_READ_DR3]                     = dr_interception,
3173         [SVM_EXIT_READ_DR4]                     = dr_interception,
3174         [SVM_EXIT_READ_DR5]                     = dr_interception,
3175         [SVM_EXIT_READ_DR6]                     = dr_interception,
3176         [SVM_EXIT_READ_DR7]                     = dr_interception,
3177         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
3178         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
3179         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
3180         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
3181         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
3182         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
3183         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
3184         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
3185         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
3186         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
3187         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
3188         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
3189         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
3190         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
3191         [SVM_EXIT_INTR]                         = intr_interception,
3192         [SVM_EXIT_NMI]                          = nmi_interception,
3193         [SVM_EXIT_SMI]                          = nop_on_interception,
3194         [SVM_EXIT_INIT]                         = nop_on_interception,
3195         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
3196         [SVM_EXIT_CPUID]                        = cpuid_interception,
3197         [SVM_EXIT_IRET]                         = iret_interception,
3198         [SVM_EXIT_INVD]                         = emulate_on_interception,
3199         [SVM_EXIT_PAUSE]                        = pause_interception,
3200         [SVM_EXIT_HLT]                          = halt_interception,
3201         [SVM_EXIT_INVLPG]                       = invlpg_interception,
3202         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
3203         [SVM_EXIT_IOIO]                         = io_interception,
3204         [SVM_EXIT_MSR]                          = msr_interception,
3205         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
3206         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
3207         [SVM_EXIT_VMRUN]                        = vmrun_interception,
3208         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
3209         [SVM_EXIT_VMLOAD]                       = vmload_interception,
3210         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
3211         [SVM_EXIT_STGI]                         = stgi_interception,
3212         [SVM_EXIT_CLGI]                         = clgi_interception,
3213         [SVM_EXIT_SKINIT]                       = skinit_interception,
3214         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
3215         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
3216         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
3217         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
3218         [SVM_EXIT_NPF]                          = pf_interception,
3219 };
3220
3221 static void dump_vmcb(struct kvm_vcpu *vcpu)
3222 {
3223         struct vcpu_svm *svm = to_svm(vcpu);
3224         struct vmcb_control_area *control = &svm->vmcb->control;
3225         struct vmcb_save_area *save = &svm->vmcb->save;
3226
3227         pr_err("VMCB Control Area:\n");
3228         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3229         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3230         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3231         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3232         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3233         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3234         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3235         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3236         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3237         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3238         pr_err("%-20s%d\n", "asid:", control->asid);
3239         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3240         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3241         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3242         pr_err("%-20s%08x\n", "int_state:", control->int_state);
3243         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3244         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3245         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3246         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3247         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3248         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3249         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3250         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3251         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3252         pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3253         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3254         pr_err("VMCB State Save Area:\n");
3255         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3256                "es:",
3257                save->es.selector, save->es.attrib,
3258                save->es.limit, save->es.base);
3259         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3260                "cs:",
3261                save->cs.selector, save->cs.attrib,
3262                save->cs.limit, save->cs.base);
3263         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3264                "ss:",
3265                save->ss.selector, save->ss.attrib,
3266                save->ss.limit, save->ss.base);
3267         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3268                "ds:",
3269                save->ds.selector, save->ds.attrib,
3270                save->ds.limit, save->ds.base);
3271         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3272                "fs:",
3273                save->fs.selector, save->fs.attrib,
3274                save->fs.limit, save->fs.base);
3275         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3276                "gs:",
3277                save->gs.selector, save->gs.attrib,
3278                save->gs.limit, save->gs.base);
3279         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3280                "gdtr:",
3281                save->gdtr.selector, save->gdtr.attrib,
3282                save->gdtr.limit, save->gdtr.base);
3283         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3284                "ldtr:",
3285                save->ldtr.selector, save->ldtr.attrib,
3286                save->ldtr.limit, save->ldtr.base);
3287         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3288                "idtr:",
3289                save->idtr.selector, save->idtr.attrib,
3290                save->idtr.limit, save->idtr.base);
3291         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3292                "tr:",
3293                save->tr.selector, save->tr.attrib,
3294                save->tr.limit, save->tr.base);
3295         pr_err("cpl:            %d                efer:         %016llx\n",
3296                 save->cpl, save->efer);
3297         pr_err("%-15s %016llx %-13s %016llx\n",
3298                "cr0:", save->cr0, "cr2:", save->cr2);
3299         pr_err("%-15s %016llx %-13s %016llx\n",
3300                "cr3:", save->cr3, "cr4:", save->cr4);
3301         pr_err("%-15s %016llx %-13s %016llx\n",
3302                "dr6:", save->dr6, "dr7:", save->dr7);
3303         pr_err("%-15s %016llx %-13s %016llx\n",
3304                "rip:", save->rip, "rflags:", save->rflags);
3305         pr_err("%-15s %016llx %-13s %016llx\n",
3306                "rsp:", save->rsp, "rax:", save->rax);
3307         pr_err("%-15s %016llx %-13s %016llx\n",
3308                "star:", save->star, "lstar:", save->lstar);
3309         pr_err("%-15s %016llx %-13s %016llx\n",
3310                "cstar:", save->cstar, "sfmask:", save->sfmask);
3311         pr_err("%-15s %016llx %-13s %016llx\n",
3312                "kernel_gs_base:", save->kernel_gs_base,
3313                "sysenter_cs:", save->sysenter_cs);
3314         pr_err("%-15s %016llx %-13s %016llx\n",
3315                "sysenter_esp:", save->sysenter_esp,
3316                "sysenter_eip:", save->sysenter_eip);
3317         pr_err("%-15s %016llx %-13s %016llx\n",
3318                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3319         pr_err("%-15s %016llx %-13s %016llx\n",
3320                "br_from:", save->br_from, "br_to:", save->br_to);
3321         pr_err("%-15s %016llx %-13s %016llx\n",
3322                "excp_from:", save->last_excp_from,
3323                "excp_to:", save->last_excp_to);
3324 }
3325
3326 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3327 {
3328         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3329
3330         *info1 = control->exit_info_1;
3331         *info2 = control->exit_info_2;
3332 }
3333
3334 static int handle_exit(struct kvm_vcpu *vcpu)
3335 {
3336         struct vcpu_svm *svm = to_svm(vcpu);
3337         struct kvm_run *kvm_run = vcpu->run;
3338         u32 exit_code = svm->vmcb->control.exit_code;
3339
3340         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3341                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3342         if (npt_enabled)
3343                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3344
3345         if (unlikely(svm->nested.exit_required)) {
3346                 nested_svm_vmexit(svm);
3347                 svm->nested.exit_required = false;
3348
3349                 return 1;
3350         }
3351
3352         if (is_guest_mode(vcpu)) {
3353                 int vmexit;
3354
3355                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3356                                         svm->vmcb->control.exit_info_1,
3357                                         svm->vmcb->control.exit_info_2,
3358                                         svm->vmcb->control.exit_int_info,
3359                                         svm->vmcb->control.exit_int_info_err,
3360                                         KVM_ISA_SVM);
3361
3362                 vmexit = nested_svm_exit_special(svm);
3363
3364                 if (vmexit == NESTED_EXIT_CONTINUE)
3365                         vmexit = nested_svm_exit_handled(svm);
3366
3367                 if (vmexit == NESTED_EXIT_DONE)
3368                         return 1;
3369         }
3370
3371         svm_complete_interrupts(svm);
3372
3373         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3374                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3375                 kvm_run->fail_entry.hardware_entry_failure_reason
3376                         = svm->vmcb->control.exit_code;
3377                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3378                 dump_vmcb(vcpu);
3379                 return 0;
3380         }
3381
3382         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3383             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3384             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3385             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3386                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3387                        "exit_code 0x%x\n",
3388                        __func__, svm->vmcb->control.exit_int_info,
3389                        exit_code);
3390
3391         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3392             || !svm_exit_handlers[exit_code]) {
3393                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3394                 kvm_run->hw.hardware_exit_reason = exit_code;
3395                 return 0;
3396         }
3397
3398         return svm_exit_handlers[exit_code](svm);
3399 }
3400
3401 static void reload_tss(struct kvm_vcpu *vcpu)
3402 {
3403         int cpu = raw_smp_processor_id();
3404
3405         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3406         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3407         load_TR_desc();
3408 }
3409
3410 static void pre_svm_run(struct vcpu_svm *svm)
3411 {
3412         int cpu = raw_smp_processor_id();
3413
3414         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3415
3416         /* FIXME: handle wraparound of asid_generation */
3417         if (svm->asid_generation != sd->asid_generation)
3418                 new_asid(svm, sd);
3419 }
3420
3421 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3422 {
3423         struct vcpu_svm *svm = to_svm(vcpu);
3424
3425         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3426         vcpu->arch.hflags |= HF_NMI_MASK;
3427         set_intercept(svm, INTERCEPT_IRET);
3428         ++vcpu->stat.nmi_injections;
3429 }
3430
3431 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3432 {
3433         struct vmcb_control_area *control;
3434
3435         control = &svm->vmcb->control;
3436         control->int_vector = irq;
3437         control->int_ctl &= ~V_INTR_PRIO_MASK;
3438         control->int_ctl |= V_IRQ_MASK |
3439                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3440         mark_dirty(svm->vmcb, VMCB_INTR);
3441 }
3442
3443 static void svm_set_irq(struct kvm_vcpu *vcpu)
3444 {
3445         struct vcpu_svm *svm = to_svm(vcpu);
3446
3447         BUG_ON(!(gif_set(svm)));
3448
3449         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3450         ++vcpu->stat.irq_injections;
3451
3452         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3453                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3454 }
3455
3456 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3457 {
3458         struct vcpu_svm *svm = to_svm(vcpu);
3459
3460         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3461                 return;
3462
3463         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3464
3465         if (irr == -1)
3466                 return;
3467
3468         if (tpr >= irr)
3469                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3470 }
3471
3472 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3473 {
3474         struct vcpu_svm *svm = to_svm(vcpu);
3475         struct vmcb *vmcb = svm->vmcb;
3476         int ret;
3477         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3478               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3479         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3480
3481         return ret;
3482 }
3483
3484 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3485 {
3486         struct vcpu_svm *svm = to_svm(vcpu);
3487
3488         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3489 }
3490
3491 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3492 {
3493         struct vcpu_svm *svm = to_svm(vcpu);
3494
3495         if (masked) {
3496                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3497                 set_intercept(svm, INTERCEPT_IRET);
3498         } else {
3499                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3500                 clr_intercept(svm, INTERCEPT_IRET);
3501         }
3502 }
3503
3504 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3505 {
3506         struct vcpu_svm *svm = to_svm(vcpu);
3507         struct vmcb *vmcb = svm->vmcb;
3508         int ret;
3509
3510         if (!gif_set(svm) ||
3511              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3512                 return 0;
3513
3514         ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3515
3516         if (is_guest_mode(vcpu))
3517                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3518
3519         return ret;
3520 }
3521
3522 static void enable_irq_window(struct kvm_vcpu *vcpu)
3523 {
3524         struct vcpu_svm *svm = to_svm(vcpu);
3525
3526         /*
3527          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3528          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3529          * get that intercept, this function will be called again though and
3530          * we'll get the vintr intercept.
3531          */
3532         if (gif_set(svm) && nested_svm_intr(svm)) {
3533                 svm_set_vintr(svm);
3534                 svm_inject_irq(svm, 0x0);
3535         }
3536 }
3537
3538 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3539 {
3540         struct vcpu_svm *svm = to_svm(vcpu);
3541
3542         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3543             == HF_NMI_MASK)
3544                 return; /* IRET will cause a vm exit */
3545
3546         /*
3547          * Something prevents NMI from been injected. Single step over possible
3548          * problem (IRET or exception injection or interrupt shadow)
3549          */
3550         svm->nmi_singlestep = true;
3551         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3552         update_db_intercept(vcpu);
3553 }
3554
3555 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3556 {
3557         return 0;
3558 }
3559
3560 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3561 {
3562         struct vcpu_svm *svm = to_svm(vcpu);
3563
3564         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3565                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3566         else
3567                 svm->asid_generation--;
3568 }
3569
3570 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3571 {
3572 }
3573
3574 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3575 {
3576         struct vcpu_svm *svm = to_svm(vcpu);
3577
3578         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3579                 return;
3580
3581         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3582                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3583                 kvm_set_cr8(vcpu, cr8);
3584         }
3585 }
3586
3587 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3588 {
3589         struct vcpu_svm *svm = to_svm(vcpu);
3590         u64 cr8;
3591
3592         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3593                 return;
3594
3595         cr8 = kvm_get_cr8(vcpu);
3596         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3597         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3598 }
3599
3600 static void svm_complete_interrupts(struct vcpu_svm *svm)
3601 {
3602         u8 vector;
3603         int type;
3604         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3605         unsigned int3_injected = svm->int3_injected;
3606
3607         svm->int3_injected = 0;
3608
3609         /*
3610          * If we've made progress since setting HF_IRET_MASK, we've
3611          * executed an IRET and can allow NMI injection.
3612          */
3613         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3614             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3615                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3616                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3617         }
3618
3619         svm->vcpu.arch.nmi_injected = false;
3620         kvm_clear_exception_queue(&svm->vcpu);
3621         kvm_clear_interrupt_queue(&svm->vcpu);
3622
3623         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3624                 return;
3625
3626         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3627
3628         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3629         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3630
3631         switch (type) {
3632         case SVM_EXITINTINFO_TYPE_NMI:
3633                 svm->vcpu.arch.nmi_injected = true;
3634                 break;
3635         case SVM_EXITINTINFO_TYPE_EXEPT:
3636                 /*
3637                  * In case of software exceptions, do not reinject the vector,
3638                  * but re-execute the instruction instead. Rewind RIP first
3639                  * if we emulated INT3 before.
3640                  */
3641                 if (kvm_exception_is_soft(vector)) {
3642                         if (vector == BP_VECTOR && int3_injected &&
3643                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3644                                 kvm_rip_write(&svm->vcpu,
3645                                               kvm_rip_read(&svm->vcpu) -
3646                                               int3_injected);
3647                         break;
3648                 }
3649                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3650                         u32 err = svm->vmcb->control.exit_int_info_err;
3651                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3652
3653                 } else
3654                         kvm_requeue_exception(&svm->vcpu, vector);
3655                 break;
3656         case SVM_EXITINTINFO_TYPE_INTR:
3657                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3658                 break;
3659         default:
3660                 break;
3661         }
3662 }
3663
3664 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3665 {
3666         struct vcpu_svm *svm = to_svm(vcpu);
3667         struct vmcb_control_area *control = &svm->vmcb->control;
3668
3669         control->exit_int_info = control->event_inj;
3670         control->exit_int_info_err = control->event_inj_err;
3671         control->event_inj = 0;
3672         svm_complete_interrupts(svm);
3673 }
3674
3675 #ifdef CONFIG_X86_64
3676 #define R "r"
3677 #else
3678 #define R "e"
3679 #endif
3680
3681 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3682 {
3683         struct vcpu_svm *svm = to_svm(vcpu);
3684
3685         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3686         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3687         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3688
3689         /*
3690          * A vmexit emulation is required before the vcpu can be executed
3691          * again.
3692          */
3693         if (unlikely(svm->nested.exit_required))
3694                 return;
3695
3696         pre_svm_run(svm);
3697
3698         sync_lapic_to_cr8(vcpu);
3699
3700         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3701
3702         clgi();
3703
3704         local_irq_enable();
3705
3706         asm volatile (
3707                 "push %%"R"bp; \n\t"
3708                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3709                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3710                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3711                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3712                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3713                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3714 #ifdef CONFIG_X86_64
3715                 "mov %c[r8](%[svm]),  %%r8  \n\t"
3716                 "mov %c[r9](%[svm]),  %%r9  \n\t"
3717                 "mov %c[r10](%[svm]), %%r10 \n\t"
3718                 "mov %c[r11](%[svm]), %%r11 \n\t"
3719                 "mov %c[r12](%[svm]), %%r12 \n\t"
3720                 "mov %c[r13](%[svm]), %%r13 \n\t"
3721                 "mov %c[r14](%[svm]), %%r14 \n\t"
3722                 "mov %c[r15](%[svm]), %%r15 \n\t"
3723 #endif
3724
3725                 /* Enter guest mode */
3726                 "push %%"R"ax \n\t"
3727                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3728                 __ex(SVM_VMLOAD) "\n\t"
3729                 __ex(SVM_VMRUN) "\n\t"
3730                 __ex(SVM_VMSAVE) "\n\t"
3731                 "pop %%"R"ax \n\t"
3732
3733                 /* Save guest registers, load host registers */
3734                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3735                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3736                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3737                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3738                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3739                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3740 #ifdef CONFIG_X86_64
3741                 "mov %%r8,  %c[r8](%[svm]) \n\t"
3742                 "mov %%r9,  %c[r9](%[svm]) \n\t"
3743                 "mov %%r10, %c[r10](%[svm]) \n\t"
3744                 "mov %%r11, %c[r11](%[svm]) \n\t"
3745                 "mov %%r12, %c[r12](%[svm]) \n\t"
3746                 "mov %%r13, %c[r13](%[svm]) \n\t"
3747                 "mov %%r14, %c[r14](%[svm]) \n\t"
3748                 "mov %%r15, %c[r15](%[svm]) \n\t"
3749 #endif
3750                 "pop %%"R"bp"
3751                 :
3752                 : [svm]"a"(svm),
3753                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3754                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3755                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3756                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3757                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3758                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3759                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3760 #ifdef CONFIG_X86_64
3761                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3762                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3763                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3764                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3765                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3766                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3767                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3768                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3769 #endif
3770                 : "cc", "memory"
3771                 , R"bx", R"cx", R"dx", R"si", R"di"
3772 #ifdef CONFIG_X86_64
3773                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3774 #endif
3775                 );
3776
3777 #ifdef CONFIG_X86_64
3778         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3779 #else
3780         loadsegment(fs, svm->host.fs);
3781 #ifndef CONFIG_X86_32_LAZY_GS
3782         loadsegment(gs, svm->host.gs);
3783 #endif
3784 #endif
3785
3786         reload_tss(vcpu);
3787
3788         local_irq_disable();
3789
3790         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3791         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3792         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3793         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3794
3795         trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
3796
3797         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3798                 kvm_before_handle_nmi(&svm->vcpu);
3799
3800         stgi();
3801
3802         /* Any pending NMI will happen here */
3803
3804         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3805                 kvm_after_handle_nmi(&svm->vcpu);
3806
3807         sync_cr8_to_lapic(vcpu);
3808
3809         svm->next_rip = 0;
3810
3811         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3812
3813         /* if exit due to PF check for async PF */
3814         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3815                 svm->apf_reason = kvm_read_and_reset_pf_reason();
3816
3817         if (npt_enabled) {
3818                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3819                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3820         }
3821
3822         /*
3823          * We need to handle MC intercepts here before the vcpu has a chance to
3824          * change the physical cpu
3825          */
3826         if (unlikely(svm->vmcb->control.exit_code ==
3827                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3828                 svm_handle_mce(svm);
3829
3830         mark_all_clean(svm->vmcb);
3831 }
3832
3833 #undef R
3834
3835 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3836 {
3837         struct vcpu_svm *svm = to_svm(vcpu);
3838
3839         svm->vmcb->save.cr3 = root;
3840         mark_dirty(svm->vmcb, VMCB_CR);
3841         svm_flush_tlb(vcpu);
3842 }
3843
3844 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3845 {
3846         struct vcpu_svm *svm = to_svm(vcpu);
3847
3848         svm->vmcb->control.nested_cr3 = root;
3849         mark_dirty(svm->vmcb, VMCB_NPT);
3850
3851         /* Also sync guest cr3 here in case we live migrate */
3852         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
3853         mark_dirty(svm->vmcb, VMCB_CR);
3854
3855         svm_flush_tlb(vcpu);
3856 }
3857
3858 static int is_disabled(void)
3859 {
3860         u64 vm_cr;
3861
3862         rdmsrl(MSR_VM_CR, vm_cr);
3863         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3864                 return 1;
3865
3866         return 0;
3867 }
3868
3869 static void
3870 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3871 {
3872         /*
3873          * Patch in the VMMCALL instruction:
3874          */
3875         hypercall[0] = 0x0f;
3876         hypercall[1] = 0x01;
3877         hypercall[2] = 0xd9;
3878 }
3879
3880 static void svm_check_processor_compat(void *rtn)
3881 {
3882         *(int *)rtn = 0;
3883 }
3884
3885 static bool svm_cpu_has_accelerated_tpr(void)
3886 {
3887         return false;
3888 }
3889
3890 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3891 {
3892         return 0;
3893 }
3894
3895 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3896 {
3897 }
3898
3899 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3900 {
3901         switch (func) {
3902         case 0x80000001:
3903                 if (nested)
3904                         entry->ecx |= (1 << 2); /* Set SVM bit */
3905                 break;
3906         case 0x8000000A:
3907                 entry->eax = 1; /* SVM revision 1 */
3908                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3909                                    ASID emulation to nested SVM */
3910                 entry->ecx = 0; /* Reserved */
3911                 entry->edx = 0; /* Per default do not support any
3912                                    additional features */
3913
3914                 /* Support next_rip if host supports it */
3915                 if (boot_cpu_has(X86_FEATURE_NRIPS))
3916                         entry->edx |= SVM_FEATURE_NRIP;
3917
3918                 /* Support NPT for the guest if enabled */
3919                 if (npt_enabled)
3920                         entry->edx |= SVM_FEATURE_NPT;
3921
3922                 break;
3923         }
3924 }
3925
3926 static int svm_get_lpage_level(void)
3927 {
3928         return PT_PDPE_LEVEL;
3929 }
3930
3931 static bool svm_rdtscp_supported(void)
3932 {
3933         return false;
3934 }
3935
3936 static bool svm_has_wbinvd_exit(void)
3937 {
3938         return true;
3939 }
3940
3941 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3942 {
3943         struct vcpu_svm *svm = to_svm(vcpu);
3944
3945         set_exception_intercept(svm, NM_VECTOR);
3946         update_cr0_intercept(svm);
3947 }
3948
3949 #define PRE_EX(exit)  { .exit_code = (exit), \
3950                         .stage = X86_ICPT_PRE_EXCEPT, }
3951 #define POST_EX(exit) { .exit_code = (exit), \
3952                         .stage = X86_ICPT_POST_EXCEPT, }
3953 #define POST_MEM(exit) { .exit_code = (exit), \
3954                         .stage = X86_ICPT_POST_MEMACCESS, }
3955
3956 static struct __x86_intercept {
3957         u32 exit_code;
3958         enum x86_intercept_stage stage;
3959 } x86_intercept_map[] = {
3960         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
3961         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
3962         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
3963         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
3964         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
3965         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
3966         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
3967         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
3968         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
3969         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
3970         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
3971         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
3972         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
3973         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
3974         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
3975         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
3976         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
3977         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
3978         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
3979         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
3980         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
3981         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
3982         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
3983         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
3984         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
3985         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
3986         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
3987         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
3988         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
3989         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
3990         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
3991         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
3992         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
3993         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
3994         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
3995         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
3996         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
3997         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
3998         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
3999         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
4000         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
4001         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
4002         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
4003         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
4004         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
4005         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
4006 };
4007
4008 #undef PRE_EX
4009 #undef POST_EX
4010 #undef POST_MEM
4011
4012 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4013                                struct x86_instruction_info *info,
4014                                enum x86_intercept_stage stage)
4015 {
4016         struct vcpu_svm *svm = to_svm(vcpu);
4017         int vmexit, ret = X86EMUL_CONTINUE;
4018         struct __x86_intercept icpt_info;
4019         struct vmcb *vmcb = svm->vmcb;
4020
4021         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4022                 goto out;
4023
4024         icpt_info = x86_intercept_map[info->intercept];
4025
4026         if (stage != icpt_info.stage)
4027                 goto out;
4028
4029         switch (icpt_info.exit_code) {
4030         case SVM_EXIT_READ_CR0:
4031                 if (info->intercept == x86_intercept_cr_read)
4032                         icpt_info.exit_code += info->modrm_reg;
4033                 break;
4034         case SVM_EXIT_WRITE_CR0: {
4035                 unsigned long cr0, val;
4036                 u64 intercept;
4037
4038                 if (info->intercept == x86_intercept_cr_write)
4039                         icpt_info.exit_code += info->modrm_reg;
4040
4041                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0)
4042                         break;
4043
4044                 intercept = svm->nested.intercept;
4045
4046                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4047                         break;
4048
4049                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4050                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
4051
4052                 if (info->intercept == x86_intercept_lmsw) {
4053                         cr0 &= 0xfUL;
4054                         val &= 0xfUL;
4055                         /* lmsw can't clear PE - catch this here */
4056                         if (cr0 & X86_CR0_PE)
4057                                 val |= X86_CR0_PE;
4058                 }
4059
4060                 if (cr0 ^ val)
4061                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4062
4063                 break;
4064         }
4065         case SVM_EXIT_READ_DR0:
4066         case SVM_EXIT_WRITE_DR0:
4067                 icpt_info.exit_code += info->modrm_reg;
4068                 break;
4069         case SVM_EXIT_MSR:
4070                 if (info->intercept == x86_intercept_wrmsr)
4071                         vmcb->control.exit_info_1 = 1;
4072                 else
4073                         vmcb->control.exit_info_1 = 0;
4074                 break;
4075         case SVM_EXIT_PAUSE:
4076                 /*
4077                  * We get this for NOP only, but pause
4078                  * is rep not, check this here
4079                  */
4080                 if (info->rep_prefix != REPE_PREFIX)
4081                         goto out;
4082         case SVM_EXIT_IOIO: {
4083                 u64 exit_info;
4084                 u32 bytes;
4085
4086                 exit_info = (vcpu->arch.regs[VCPU_REGS_RDX] & 0xffff) << 16;
4087
4088                 if (info->intercept == x86_intercept_in ||
4089                     info->intercept == x86_intercept_ins) {
4090                         exit_info |= SVM_IOIO_TYPE_MASK;
4091                         bytes = info->src_bytes;
4092                 } else {
4093                         bytes = info->dst_bytes;
4094                 }
4095
4096                 if (info->intercept == x86_intercept_outs ||
4097                     info->intercept == x86_intercept_ins)
4098                         exit_info |= SVM_IOIO_STR_MASK;
4099
4100                 if (info->rep_prefix)
4101                         exit_info |= SVM_IOIO_REP_MASK;
4102
4103                 bytes = min(bytes, 4u);
4104
4105                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4106
4107                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4108
4109                 vmcb->control.exit_info_1 = exit_info;
4110                 vmcb->control.exit_info_2 = info->next_rip;
4111
4112                 break;
4113         }
4114         default:
4115                 break;
4116         }
4117
4118         vmcb->control.next_rip  = info->next_rip;
4119         vmcb->control.exit_code = icpt_info.exit_code;
4120         vmexit = nested_svm_exit_handled(svm);
4121
4122         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4123                                            : X86EMUL_CONTINUE;
4124
4125 out:
4126         return ret;
4127 }
4128
4129 static struct kvm_x86_ops svm_x86_ops = {
4130         .cpu_has_kvm_support = has_svm,
4131         .disabled_by_bios = is_disabled,
4132         .hardware_setup = svm_hardware_setup,
4133         .hardware_unsetup = svm_hardware_unsetup,
4134         .check_processor_compatibility = svm_check_processor_compat,
4135         .hardware_enable = svm_hardware_enable,
4136         .hardware_disable = svm_hardware_disable,
4137         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4138
4139         .vcpu_create = svm_create_vcpu,
4140         .vcpu_free = svm_free_vcpu,
4141         .vcpu_reset = svm_vcpu_reset,
4142
4143         .prepare_guest_switch = svm_prepare_guest_switch,
4144         .vcpu_load = svm_vcpu_load,
4145         .vcpu_put = svm_vcpu_put,
4146
4147         .set_guest_debug = svm_guest_debug,
4148         .get_msr = svm_get_msr,
4149         .set_msr = svm_set_msr,
4150         .get_segment_base = svm_get_segment_base,
4151         .get_segment = svm_get_segment,
4152         .set_segment = svm_set_segment,
4153         .get_cpl = svm_get_cpl,
4154         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4155         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4156         .decache_cr3 = svm_decache_cr3,
4157         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4158         .set_cr0 = svm_set_cr0,
4159         .set_cr3 = svm_set_cr3,
4160         .set_cr4 = svm_set_cr4,
4161         .set_efer = svm_set_efer,
4162         .get_idt = svm_get_idt,
4163         .set_idt = svm_set_idt,
4164         .get_gdt = svm_get_gdt,
4165         .set_gdt = svm_set_gdt,
4166         .set_dr7 = svm_set_dr7,
4167         .cache_reg = svm_cache_reg,
4168         .get_rflags = svm_get_rflags,
4169         .set_rflags = svm_set_rflags,
4170         .fpu_activate = svm_fpu_activate,
4171         .fpu_deactivate = svm_fpu_deactivate,
4172
4173         .tlb_flush = svm_flush_tlb,
4174
4175         .run = svm_vcpu_run,
4176         .handle_exit = handle_exit,
4177         .skip_emulated_instruction = skip_emulated_instruction,
4178         .set_interrupt_shadow = svm_set_interrupt_shadow,
4179         .get_interrupt_shadow = svm_get_interrupt_shadow,
4180         .patch_hypercall = svm_patch_hypercall,
4181         .set_irq = svm_set_irq,
4182         .set_nmi = svm_inject_nmi,
4183         .queue_exception = svm_queue_exception,
4184         .cancel_injection = svm_cancel_injection,
4185         .interrupt_allowed = svm_interrupt_allowed,
4186         .nmi_allowed = svm_nmi_allowed,
4187         .get_nmi_mask = svm_get_nmi_mask,
4188         .set_nmi_mask = svm_set_nmi_mask,
4189         .enable_nmi_window = enable_nmi_window,
4190         .enable_irq_window = enable_irq_window,
4191         .update_cr8_intercept = update_cr8_intercept,
4192
4193         .set_tss_addr = svm_set_tss_addr,
4194         .get_tdp_level = get_npt_level,
4195         .get_mt_mask = svm_get_mt_mask,
4196
4197         .get_exit_info = svm_get_exit_info,
4198
4199         .get_lpage_level = svm_get_lpage_level,
4200
4201         .cpuid_update = svm_cpuid_update,
4202
4203         .rdtscp_supported = svm_rdtscp_supported,
4204
4205         .set_supported_cpuid = svm_set_supported_cpuid,
4206
4207         .has_wbinvd_exit = svm_has_wbinvd_exit,
4208
4209         .set_tsc_khz = svm_set_tsc_khz,
4210         .write_tsc_offset = svm_write_tsc_offset,
4211         .adjust_tsc_offset = svm_adjust_tsc_offset,
4212         .compute_tsc_offset = svm_compute_tsc_offset,
4213         .read_l1_tsc = svm_read_l1_tsc,
4214
4215         .set_tdp_cr3 = set_tdp_cr3,
4216
4217         .check_intercept = svm_check_intercept,
4218 };
4219
4220 static int __init svm_init(void)
4221 {
4222         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4223                         __alignof__(struct vcpu_svm), THIS_MODULE);
4224 }
4225
4226 static void __exit svm_exit(void)
4227 {
4228         kvm_exit();
4229 }
4230
4231 module_init(svm_init)
4232 module_exit(svm_exit)