arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20 #include "kvm_cache_regs.h"
  21 #include "x86.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/ftrace_event.h>
  29
  30 #include <asm/desc.h>
  31
  32 #include <asm/virtext.h>
  33 #include "trace.h"
  34
  35 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  36
  37 MODULE_AUTHOR("Qumranet");
  38 MODULE_LICENSE("GPL");
  39
  40 #define IOPM_ALLOC_ORDER 2
  41 #define MSRPM_ALLOC_ORDER 1
  42
  43 #define SEG_TYPE_LDT 2
  44 #define SEG_TYPE_BUSY_TSS16 3
  45
  46 #define SVM_FEATURE_NPT  (1 << 0)
  47 #define SVM_FEATURE_LBRV (1 << 1)
  48 #define SVM_FEATURE_SVML (1 << 2)
  49
  50 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  51
  52 /* Turn on to get debugging output*/
  53 /* #define NESTED_DEBUG */
  54
  55 #ifdef NESTED_DEBUG
  56 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
  57 #else
  58 #define nsvm_printk(fmt, args...) do {} while(0)
  59 #endif
  60
  61 static const u32 host_save_user_msrs[] = {
  62 #ifdef CONFIG_X86_64
  63         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  64         MSR_FS_BASE,
  65 #endif
  66         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  67 };
  68
  69 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  70
  71 struct kvm_vcpu;
  72
  73 struct vcpu_svm {
  74         struct kvm_vcpu vcpu;
  75         struct vmcb *vmcb;
  76         unsigned long vmcb_pa;
  77         struct svm_cpu_data *svm_data;
  78         uint64_t asid_generation;
  79         uint64_t sysenter_esp;
  80         uint64_t sysenter_eip;
  81
  82         u64 next_rip;
  83
  84         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
  85         u64 host_gs_base;
  86
  87         u32 *msrpm;
  88         struct vmcb *hsave;
  89         u64 hsave_msr;
  90
  91         u64 nested_vmcb;
  92
  93         /* These are the merged vectors */
  94         u32 *nested_msrpm;
  95
  96         /* gpa pointers to the real vectors */
  97         u64 nested_vmcb_msrpm;
  98 };
  99
 100 /* enable NPT for AMD64 and X86 with PAE */
 101 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 102 static bool npt_enabled = true;
 103 #else
 104 static bool npt_enabled = false;
 105 #endif
 106 static int npt = 1;
 107
 108 module_param(npt, int, S_IRUGO);
 109
 110 static int nested = 0;
 111 module_param(nested, int, S_IRUGO);
 112
 113 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 114
 115 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
 116 static int nested_svm_vmexit(struct vcpu_svm *svm);
 117 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
 118                              void *arg2, void *opaque);
 119 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 120                                       bool has_error_code, u32 error_code);
 121
 122 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 123 {
 124         return container_of(vcpu, struct vcpu_svm, vcpu);
 125 }
 126
 127 static inline bool is_nested(struct vcpu_svm *svm)
 128 {
 129         return svm->nested_vmcb;
 130 }
 131
 132 static inline void enable_gif(struct vcpu_svm *svm)
 133 {
 134         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 135 }
 136
 137 static inline void disable_gif(struct vcpu_svm *svm)
 138 {
 139         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 140 }
 141
 142 static inline bool gif_set(struct vcpu_svm *svm)
 143 {
 144         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 145 }
 146
 147 static unsigned long iopm_base;
 148
 149 struct kvm_ldttss_desc {
 150         u16 limit0;
 151         u16 base0;
 152         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
 153         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
 154         u32 base3;
 155         u32 zero1;
 156 } __attribute__((packed));
 157
 158 struct svm_cpu_data {
 159         int cpu;
 160
 161         u64 asid_generation;
 162         u32 max_asid;
 163         u32 next_asid;
 164         struct kvm_ldttss_desc *tss_desc;
 165
 166         struct page *save_area;
 167 };
 168
 169 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 170 static uint32_t svm_features;
 171
 172 struct svm_init_data {
 173         int cpu;
 174         int r;
 175 };
 176
 177 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 178
 179 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 180 #define MSRS_RANGE_SIZE 2048
 181 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 182
 183 #define MAX_INST_SIZE 15
 184
 185 static inline u32 svm_has(u32 feat)
 186 {
 187         return svm_features & feat;
 188 }
 189
 190 static inline void clgi(void)
 191 {
 192         asm volatile (__ex(SVM_CLGI));
 193 }
 194
 195 static inline void stgi(void)
 196 {
 197         asm volatile (__ex(SVM_STGI));
 198 }
 199
 200 static inline void invlpga(unsigned long addr, u32 asid)
 201 {
 202         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 203 }
 204
 205 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 206 {
 207         to_svm(vcpu)->asid_generation--;
 208 }
 209
 210 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 211 {
 212         force_new_asid(vcpu);
 213 }
 214
 215 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 216 {
 217         if (!npt_enabled && !(efer & EFER_LMA))
 218                 efer &= ~EFER_LME;
 219
 220         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 221         vcpu->arch.shadow_efer = efer;
 222 }
 223
 224 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 225                                 bool has_error_code, u32 error_code)
 226 {
 227         struct vcpu_svm *svm = to_svm(vcpu);
 228
 229         /* If we are within a nested VM we'd better #VMEXIT and let the
 230            guest handle the exception */
 231         if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
 232                 return;
 233
 234         svm->vmcb->control.event_inj = nr
 235                 | SVM_EVTINJ_VALID
 236                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 237                 | SVM_EVTINJ_TYPE_EXEPT;
 238         svm->vmcb->control.event_inj_err = error_code;
 239 }
 240
 241 static int is_external_interrupt(u32 info)
 242 {
 243         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 244         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 245 }
 246
 247 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 248 {
 249         struct vcpu_svm *svm = to_svm(vcpu);
 250         u32 ret = 0;
 251
 252         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 253                 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
 254         return ret & mask;
 255 }
 256
 257 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 258 {
 259         struct vcpu_svm *svm = to_svm(vcpu);
 260
 261         if (mask == 0)
 262                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 263         else
 264                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 265
 266 }
 267
 268 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 269 {
 270         struct vcpu_svm *svm = to_svm(vcpu);
 271
 272         if (!svm->next_rip) {
 273                 if (emulate_instruction(vcpu, vcpu->run, 0, 0, EMULTYPE_SKIP) !=
 274                                 EMULATE_DONE)
 275                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 276                 return;
 277         }
 278         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 279                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 280                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 281
 282         kvm_rip_write(vcpu, svm->next_rip);
 283         svm_set_interrupt_shadow(vcpu, 0);
 284 }
 285
 286 static int has_svm(void)
 287 {
 288         const char *msg;
 289
 290         if (!cpu_has_svm(&msg)) {
 291                 printk(KERN_INFO "has_svm: %s\n", msg);
 292                 return 0;
 293         }
 294
 295         return 1;
 296 }
 297
 298 static void svm_hardware_disable(void *garbage)
 299 {
 300         cpu_svm_disable();
 301 }
 302
 303 static void svm_hardware_enable(void *garbage)
 304 {
 305
 306         struct svm_cpu_data *svm_data;
 307         uint64_t efer;
 308         struct descriptor_table gdt_descr;
 309         struct desc_struct *gdt;
 310         int me = raw_smp_processor_id();
 311
 312         if (!has_svm()) {
 313                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 314                 return;
 315         }
 316         svm_data = per_cpu(svm_data, me);
 317
 318         if (!svm_data) {
 319                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 320                        me);
 321                 return;
 322         }
 323
 324         svm_data->asid_generation = 1;
 325         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 326         svm_data->next_asid = svm_data->max_asid + 1;
 327
 328         kvm_get_gdt(&gdt_descr);
 329         gdt = (struct desc_struct *)gdt_descr.base;
 330         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 331
 332         rdmsrl(MSR_EFER, efer);
 333         wrmsrl(MSR_EFER, efer | EFER_SVME);
 334
 335         wrmsrl(MSR_VM_HSAVE_PA,
 336                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 337 }
 338
 339 static void svm_cpu_uninit(int cpu)
 340 {
 341         struct svm_cpu_data *svm_data
 342                 = per_cpu(svm_data, raw_smp_processor_id());
 343
 344         if (!svm_data)
 345                 return;
 346
 347         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 348         __free_page(svm_data->save_area);
 349         kfree(svm_data);
 350 }
 351
 352 static int svm_cpu_init(int cpu)
 353 {
 354         struct svm_cpu_data *svm_data;
 355         int r;
 356
 357         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 358         if (!svm_data)
 359                 return -ENOMEM;
 360         svm_data->cpu = cpu;
 361         svm_data->save_area = alloc_page(GFP_KERNEL);
 362         r = -ENOMEM;
 363         if (!svm_data->save_area)
 364                 goto err_1;
 365
 366         per_cpu(svm_data, cpu) = svm_data;
 367
 368         return 0;
 369
 370 err_1:
 371         kfree(svm_data);
 372         return r;
 373
 374 }
 375
 376 static void set_msr_interception(u32 *msrpm, unsigned msr,
 377                                  int read, int write)
 378 {
 379         int i;
 380
 381         for (i = 0; i < NUM_MSR_MAPS; i++) {
 382                 if (msr >= msrpm_ranges[i] &&
 383                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 384                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 385                                           msrpm_ranges[i]) * 2;
 386
 387                         u32 *base = msrpm + (msr_offset / 32);
 388                         u32 msr_shift = msr_offset % 32;
 389                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 390                         *base = (*base & ~(0x3 << msr_shift)) |
 391                                 (mask << msr_shift);
 392                         return;
 393                 }
 394         }
 395         BUG();
 396 }
 397
 398 static void svm_vcpu_init_msrpm(u32 *msrpm)
 399 {
 400         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 401
 402 #ifdef CONFIG_X86_64
 403         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 404         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 405         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 406         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 407         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 408         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 409 #endif
 410         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 411         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 412 }
 413
 414 static void svm_enable_lbrv(struct vcpu_svm *svm)
 415 {
 416         u32 *msrpm = svm->msrpm;
 417
 418         svm->vmcb->control.lbr_ctl = 1;
 419         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 420         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 421         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 422         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 423 }
 424
 425 static void svm_disable_lbrv(struct vcpu_svm *svm)
 426 {
 427         u32 *msrpm = svm->msrpm;
 428
 429         svm->vmcb->control.lbr_ctl = 0;
 430         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 431         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 432         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 433         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 434 }
 435
 436 static __init int svm_hardware_setup(void)
 437 {
 438         int cpu;
 439         struct page *iopm_pages;
 440         void *iopm_va;
 441         int r;
 442
 443         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 444
 445         if (!iopm_pages)
 446                 return -ENOMEM;
 447
 448         iopm_va = page_address(iopm_pages);
 449         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 450         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 451
 452         if (boot_cpu_has(X86_FEATURE_NX))
 453                 kvm_enable_efer_bits(EFER_NX);
 454
 455         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 456                 kvm_enable_efer_bits(EFER_FFXSR);
 457
 458         if (nested) {
 459                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 460                 kvm_enable_efer_bits(EFER_SVME);
 461         }
 462
 463         for_each_online_cpu(cpu) {
 464                 r = svm_cpu_init(cpu);
 465                 if (r)
 466                         goto err;
 467         }
 468
 469         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 470
 471         if (!svm_has(SVM_FEATURE_NPT))
 472                 npt_enabled = false;
 473
 474         if (npt_enabled && !npt) {
 475                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 476                 npt_enabled = false;
 477         }
 478
 479         if (npt_enabled) {
 480                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 481                 kvm_enable_tdp();
 482         } else
 483                 kvm_disable_tdp();
 484
 485         return 0;
 486
 487 err:
 488         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 489         iopm_base = 0;
 490         return r;
 491 }
 492
 493 static __exit void svm_hardware_unsetup(void)
 494 {
 495         int cpu;
 496
 497         for_each_online_cpu(cpu)
 498                 svm_cpu_uninit(cpu);
 499
 500         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 501         iopm_base = 0;
 502 }
 503
 504 static void init_seg(struct vmcb_seg *seg)
 505 {
 506         seg->selector = 0;
 507         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 508                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 509         seg->limit = 0xffff;
 510         seg->base = 0;
 511 }
 512
 513 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 514 {
 515         seg->selector = 0;
 516         seg->attrib = SVM_SELECTOR_P_MASK | type;
 517         seg->limit = 0xffff;
 518         seg->base = 0;
 519 }
 520
 521 static void init_vmcb(struct vcpu_svm *svm)
 522 {
 523         struct vmcb_control_area *control = &svm->vmcb->control;
 524         struct vmcb_save_area *save = &svm->vmcb->save;
 525
 526         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 527                                         INTERCEPT_CR3_MASK |
 528                                         INTERCEPT_CR4_MASK;
 529
 530         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 531                                         INTERCEPT_CR3_MASK |
 532                                         INTERCEPT_CR4_MASK |
 533                                         INTERCEPT_CR8_MASK;
 534
 535         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 536                                         INTERCEPT_DR1_MASK |
 537                                         INTERCEPT_DR2_MASK |
 538                                         INTERCEPT_DR3_MASK;
 539
 540         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 541                                         INTERCEPT_DR1_MASK |
 542                                         INTERCEPT_DR2_MASK |
 543                                         INTERCEPT_DR3_MASK |
 544                                         INTERCEPT_DR5_MASK |
 545                                         INTERCEPT_DR7_MASK;
 546
 547         control->intercept_exceptions = (1 << PF_VECTOR) |
 548                                         (1 << UD_VECTOR) |
 549                                         (1 << MC_VECTOR);
 550
 551
 552         control->intercept =    (1ULL << INTERCEPT_INTR) |
 553                                 (1ULL << INTERCEPT_NMI) |
 554                                 (1ULL << INTERCEPT_SMI) |
 555                                 (1ULL << INTERCEPT_CPUID) |
 556                                 (1ULL << INTERCEPT_INVD) |
 557                                 (1ULL << INTERCEPT_HLT) |
 558                                 (1ULL << INTERCEPT_INVLPG) |
 559                                 (1ULL << INTERCEPT_INVLPGA) |
 560                                 (1ULL << INTERCEPT_IOIO_PROT) |
 561                                 (1ULL << INTERCEPT_MSR_PROT) |
 562                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 563                                 (1ULL << INTERCEPT_SHUTDOWN) |
 564                                 (1ULL << INTERCEPT_VMRUN) |
 565                                 (1ULL << INTERCEPT_VMMCALL) |
 566                                 (1ULL << INTERCEPT_VMLOAD) |
 567                                 (1ULL << INTERCEPT_VMSAVE) |
 568                                 (1ULL << INTERCEPT_STGI) |
 569                                 (1ULL << INTERCEPT_CLGI) |
 570                                 (1ULL << INTERCEPT_SKINIT) |
 571                                 (1ULL << INTERCEPT_WBINVD) |
 572                                 (1ULL << INTERCEPT_MONITOR) |
 573                                 (1ULL << INTERCEPT_MWAIT);
 574
 575         control->iopm_base_pa = iopm_base;
 576         control->msrpm_base_pa = __pa(svm->msrpm);
 577         control->tsc_offset = 0;
 578         control->int_ctl = V_INTR_MASKING_MASK;
 579
 580         init_seg(&save->es);
 581         init_seg(&save->ss);
 582         init_seg(&save->ds);
 583         init_seg(&save->fs);
 584         init_seg(&save->gs);
 585
 586         save->cs.selector = 0xf000;
 587         /* Executable/Readable Code Segment */
 588         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 589                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 590         save->cs.limit = 0xffff;
 591         /*
 592          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 593          * be consistent with it.
 594          *
 595          * Replace when we have real mode working for vmx.
 596          */
 597         save->cs.base = 0xf0000;
 598
 599         save->gdtr.limit = 0xffff;
 600         save->idtr.limit = 0xffff;
 601
 602         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 603         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 604
 605         save->efer = EFER_SVME;
 606         save->dr6 = 0xffff0ff0;
 607         save->dr7 = 0x400;
 608         save->rflags = 2;
 609         save->rip = 0x0000fff0;
 610         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 611
 612         /*
 613          * cr0 val on cpu init should be 0x60000010, we enable cpu
 614          * cache by default. the orderly way is to enable cache in bios.
 615          */
 616         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 617         save->cr4 = X86_CR4_PAE;
 618         /* rdx = ?? */
 619
 620         if (npt_enabled) {
 621                 /* Setup VMCB for Nested Paging */
 622                 control->nested_ctl = 1;
 623                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 624                                         (1ULL << INTERCEPT_INVLPG));
 625                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 626                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 627                                                 INTERCEPT_CR3_MASK);
 628                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 629                                                  INTERCEPT_CR3_MASK);
 630                 save->g_pat = 0x0007040600070406ULL;
 631                 /* enable caching because the QEMU Bios doesn't enable it */
 632                 save->cr0 = X86_CR0_ET;
 633                 save->cr3 = 0;
 634                 save->cr4 = 0;
 635         }
 636         force_new_asid(&svm->vcpu);
 637
 638         svm->nested_vmcb = 0;
 639         svm->vcpu.arch.hflags = 0;
 640
 641         enable_gif(svm);
 642 }
 643
 644 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 645 {
 646         struct vcpu_svm *svm = to_svm(vcpu);
 647
 648         init_vmcb(svm);
 649
 650         if (!kvm_vcpu_is_bsp(vcpu)) {
 651                 kvm_rip_write(vcpu, 0);
 652                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 653                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 654         }
 655         vcpu->arch.regs_avail = ~0;
 656         vcpu->arch.regs_dirty = ~0;
 657
 658         return 0;
 659 }
 660
 661 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 662 {
 663         struct vcpu_svm *svm;
 664         struct page *page;
 665         struct page *msrpm_pages;
 666         struct page *hsave_page;
 667         struct page *nested_msrpm_pages;
 668         int err;
 669
 670         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 671         if (!svm) {
 672                 err = -ENOMEM;
 673                 goto out;
 674         }
 675
 676         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 677         if (err)
 678                 goto free_svm;
 679
 680         page = alloc_page(GFP_KERNEL);
 681         if (!page) {
 682                 err = -ENOMEM;
 683                 goto uninit;
 684         }
 685
 686         err = -ENOMEM;
 687         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 688         if (!msrpm_pages)
 689                 goto uninit;
 690
 691         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 692         if (!nested_msrpm_pages)
 693                 goto uninit;
 694
 695         svm->msrpm = page_address(msrpm_pages);
 696         svm_vcpu_init_msrpm(svm->msrpm);
 697
 698         hsave_page = alloc_page(GFP_KERNEL);
 699         if (!hsave_page)
 700                 goto uninit;
 701         svm->hsave = page_address(hsave_page);
 702
 703         svm->nested_msrpm = page_address(nested_msrpm_pages);
 704
 705         svm->vmcb = page_address(page);
 706         clear_page(svm->vmcb);
 707         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 708         svm->asid_generation = 0;
 709         init_vmcb(svm);
 710
 711         fx_init(&svm->vcpu);
 712         svm->vcpu.fpu_active = 1;
 713         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 714         if (kvm_vcpu_is_bsp(&svm->vcpu))
 715                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 716
 717         return &svm->vcpu;
 718
 719 uninit:
 720         kvm_vcpu_uninit(&svm->vcpu);
 721 free_svm:
 722         kmem_cache_free(kvm_vcpu_cache, svm);
 723 out:
 724         return ERR_PTR(err);
 725 }
 726
 727 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 728 {
 729         struct vcpu_svm *svm = to_svm(vcpu);
 730
 731         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 732         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 733         __free_page(virt_to_page(svm->hsave));
 734         __free_pages(virt_to_page(svm->nested_msrpm), MSRPM_ALLOC_ORDER);
 735         kvm_vcpu_uninit(vcpu);
 736         kmem_cache_free(kvm_vcpu_cache, svm);
 737 }
 738
 739 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 740 {
 741         struct vcpu_svm *svm = to_svm(vcpu);
 742         int i;
 743
 744         if (unlikely(cpu != vcpu->cpu)) {
 745                 u64 tsc_this, delta;
 746
 747                 /*
 748                  * Make sure that the guest sees a monotonically
 749                  * increasing TSC.
 750                  */
 751                 rdtscll(tsc_this);
 752                 delta = vcpu->arch.host_tsc - tsc_this;
 753                 svm->vmcb->control.tsc_offset += delta;
 754                 vcpu->cpu = cpu;
 755                 kvm_migrate_timers(vcpu);
 756                 svm->asid_generation = 0;
 757         }
 758
 759         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 760                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 761 }
 762
 763 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 764 {
 765         struct vcpu_svm *svm = to_svm(vcpu);
 766         int i;
 767
 768         ++vcpu->stat.host_state_reload;
 769         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 770                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 771
 772         rdtscll(vcpu->arch.host_tsc);
 773 }
 774
 775 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 776 {
 777         return to_svm(vcpu)->vmcb->save.rflags;
 778 }
 779
 780 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 781 {
 782         to_svm(vcpu)->vmcb->save.rflags = rflags;
 783 }
 784
 785 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
 786 {
 787         switch (reg) {
 788         case VCPU_EXREG_PDPTR:
 789                 BUG_ON(!npt_enabled);
 790                 load_pdptrs(vcpu, vcpu->arch.cr3);
 791                 break;
 792         default:
 793                 BUG();
 794         }
 795 }
 796
 797 static void svm_set_vintr(struct vcpu_svm *svm)
 798 {
 799         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 800 }
 801
 802 static void svm_clear_vintr(struct vcpu_svm *svm)
 803 {
 804         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 805 }
 806
 807 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 808 {
 809         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 810
 811         switch (seg) {
 812         case VCPU_SREG_CS: return &save->cs;
 813         case VCPU_SREG_DS: return &save->ds;
 814         case VCPU_SREG_ES: return &save->es;
 815         case VCPU_SREG_FS: return &save->fs;
 816         case VCPU_SREG_GS: return &save->gs;
 817         case VCPU_SREG_SS: return &save->ss;
 818         case VCPU_SREG_TR: return &save->tr;
 819         case VCPU_SREG_LDTR: return &save->ldtr;
 820         }
 821         BUG();
 822         return NULL;
 823 }
 824
 825 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 826 {
 827         struct vmcb_seg *s = svm_seg(vcpu, seg);
 828
 829         return s->base;
 830 }
 831
 832 static void svm_get_segment(struct kvm_vcpu *vcpu,
 833                             struct kvm_segment *var, int seg)
 834 {
 835         struct vmcb_seg *s = svm_seg(vcpu, seg);
 836
 837         var->base = s->base;
 838         var->limit = s->limit;
 839         var->selector = s->selector;
 840         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 841         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 842         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 843         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 844         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 845         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 846         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 847         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 848
 849         /* AMD's VMCB does not have an explicit unusable field, so emulate it
 850          * for cross vendor migration purposes by "not present"
 851          */
 852         var->unusable = !var->present || (var->type == 0);
 853
 854         switch (seg) {
 855         case VCPU_SREG_CS:
 856                 /*
 857                  * SVM always stores 0 for the 'G' bit in the CS selector in
 858                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 859                  * Intel's VMENTRY has a check on the 'G' bit.
 860                  */
 861                 var->g = s->limit > 0xfffff;
 862                 break;
 863         case VCPU_SREG_TR:
 864                 /*
 865                  * Work around a bug where the busy flag in the tr selector
 866                  * isn't exposed
 867                  */
 868                 var->type |= 0x2;
 869                 break;
 870         case VCPU_SREG_DS:
 871         case VCPU_SREG_ES:
 872         case VCPU_SREG_FS:
 873         case VCPU_SREG_GS:
 874                 /*
 875                  * The accessed bit must always be set in the segment
 876                  * descriptor cache, although it can be cleared in the
 877                  * descriptor, the cached bit always remains at 1. Since
 878                  * Intel has a check on this, set it here to support
 879                  * cross-vendor migration.
 880                  */
 881                 if (!var->unusable)
 882                         var->type |= 0x1;
 883                 break;
 884         case VCPU_SREG_SS:
 885                 /* On AMD CPUs sometimes the DB bit in the segment
 886                  * descriptor is left as 1, although the whole segment has
 887                  * been made unusable. Clear it here to pass an Intel VMX
 888                  * entry check when cross vendor migrating.
 889                  */
 890                 if (var->unusable)
 891                         var->db = 0;
 892                 break;
 893         }
 894 }
 895
 896 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 897 {
 898         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 899
 900         return save->cpl;
 901 }
 902
 903 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 904 {
 905         struct vcpu_svm *svm = to_svm(vcpu);
 906
 907         dt->limit = svm->vmcb->save.idtr.limit;
 908         dt->base = svm->vmcb->save.idtr.base;
 909 }
 910
 911 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 912 {
 913         struct vcpu_svm *svm = to_svm(vcpu);
 914
 915         svm->vmcb->save.idtr.limit = dt->limit;
 916         svm->vmcb->save.idtr.base = dt->base ;
 917 }
 918
 919 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 920 {
 921         struct vcpu_svm *svm = to_svm(vcpu);
 922
 923         dt->limit = svm->vmcb->save.gdtr.limit;
 924         dt->base = svm->vmcb->save.gdtr.base;
 925 }
 926
 927 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 928 {
 929         struct vcpu_svm *svm = to_svm(vcpu);
 930
 931         svm->vmcb->save.gdtr.limit = dt->limit;
 932         svm->vmcb->save.gdtr.base = dt->base ;
 933 }
 934
 935 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 936 {
 937 }
 938
 939 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 940 {
 941         struct vcpu_svm *svm = to_svm(vcpu);
 942
 943 #ifdef CONFIG_X86_64
 944         if (vcpu->arch.shadow_efer & EFER_LME) {
 945                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 946                         vcpu->arch.shadow_efer |= EFER_LMA;
 947                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 948                 }
 949
 950                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 951                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 952                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 953                 }
 954         }
 955 #endif
 956         if (npt_enabled)
 957                 goto set;
 958
 959         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 960                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 961                 vcpu->fpu_active = 1;
 962         }
 963
 964         vcpu->arch.cr0 = cr0;
 965         cr0 |= X86_CR0_PG | X86_CR0_WP;
 966         if (!vcpu->fpu_active) {
 967                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 968                 cr0 |= X86_CR0_TS;
 969         }
 970 set:
 971         /*
 972          * re-enable caching here because the QEMU bios
 973          * does not do it - this results in some delay at
 974          * reboot
 975          */
 976         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 977         svm->vmcb->save.cr0 = cr0;
 978 }
 979
 980 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 981 {
 982         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
 983         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
 984
 985         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
 986                 force_new_asid(vcpu);
 987
 988         vcpu->arch.cr4 = cr4;
 989         if (!npt_enabled)
 990                 cr4 |= X86_CR4_PAE;
 991         cr4 |= host_cr4_mce;
 992         to_svm(vcpu)->vmcb->save.cr4 = cr4;
 993 }
 994
 995 static void svm_set_segment(struct kvm_vcpu *vcpu,
 996                             struct kvm_segment *var, int seg)
 997 {
 998         struct vcpu_svm *svm = to_svm(vcpu);
 999         struct vmcb_seg *s = svm_seg(vcpu, seg);
1000
1001         s->base = var->base;
1002         s->limit = var->limit;
1003         s->selector = var->selector;
1004         if (var->unusable)
1005                 s->attrib = 0;
1006         else {
1007                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1008                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1009                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1010                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1011                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1012                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1013                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1014                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1015         }
1016         if (seg == VCPU_SREG_CS)
1017                 svm->vmcb->save.cpl
1018                         = (svm->vmcb->save.cs.attrib
1019                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1020
1021 }
1022
1023 static void update_db_intercept(struct kvm_vcpu *vcpu)
1024 {
1025         struct vcpu_svm *svm = to_svm(vcpu);
1026
1027         svm->vmcb->control.intercept_exceptions &=
1028                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1029
1030         if (vcpu->arch.singlestep)
1031                 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1032
1033         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1034                 if (vcpu->guest_debug &
1035                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1036                         svm->vmcb->control.intercept_exceptions |=
1037                                 1 << DB_VECTOR;
1038                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1039                         svm->vmcb->control.intercept_exceptions |=
1040                                 1 << BP_VECTOR;
1041         } else
1042                 vcpu->guest_debug = 0;
1043 }
1044
1045 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1046 {
1047         int old_debug = vcpu->guest_debug;
1048         struct vcpu_svm *svm = to_svm(vcpu);
1049
1050         vcpu->guest_debug = dbg->control;
1051
1052         update_db_intercept(vcpu);
1053
1054         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1055                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1056         else
1057                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1058
1059         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1060                 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1061         else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1062                 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1063
1064         return 0;
1065 }
1066
1067 static void load_host_msrs(struct kvm_vcpu *vcpu)
1068 {
1069 #ifdef CONFIG_X86_64
1070         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1071 #endif
1072 }
1073
1074 static void save_host_msrs(struct kvm_vcpu *vcpu)
1075 {
1076 #ifdef CONFIG_X86_64
1077         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1078 #endif
1079 }
1080
1081 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
1082 {
1083         if (svm_data->next_asid > svm_data->max_asid) {
1084                 ++svm_data->asid_generation;
1085                 svm_data->next_asid = 1;
1086                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1087         }
1088
1089         svm->asid_generation = svm_data->asid_generation;
1090         svm->vmcb->control.asid = svm_data->next_asid++;
1091 }
1092
1093 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1094 {
1095         struct vcpu_svm *svm = to_svm(vcpu);
1096         unsigned long val;
1097
1098         switch (dr) {
1099         case 0 ... 3:
1100                 val = vcpu->arch.db[dr];
1101                 break;
1102         case 6:
1103                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1104                         val = vcpu->arch.dr6;
1105                 else
1106                         val = svm->vmcb->save.dr6;
1107                 break;
1108         case 7:
1109                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1110                         val = vcpu->arch.dr7;
1111                 else
1112                         val = svm->vmcb->save.dr7;
1113                 break;
1114         default:
1115                 val = 0;
1116         }
1117
1118         return val;
1119 }
1120
1121 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1122                        int *exception)
1123 {
1124         struct vcpu_svm *svm = to_svm(vcpu);
1125
1126         *exception = 0;
1127
1128         switch (dr) {
1129         case 0 ... 3:
1130                 vcpu->arch.db[dr] = value;
1131                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1132                         vcpu->arch.eff_db[dr] = value;
1133                 return;
1134         case 4 ... 5:
1135                 if (vcpu->arch.cr4 & X86_CR4_DE)
1136                         *exception = UD_VECTOR;
1137                 return;
1138         case 6:
1139                 if (value & 0xffffffff00000000ULL) {
1140                         *exception = GP_VECTOR;
1141                         return;
1142                 }
1143                 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1144                 return;
1145         case 7:
1146                 if (value & 0xffffffff00000000ULL) {
1147                         *exception = GP_VECTOR;
1148                         return;
1149                 }
1150                 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1151                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1152                         svm->vmcb->save.dr7 = vcpu->arch.dr7;
1153                         vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1154                 }
1155                 return;
1156         default:
1157                 /* FIXME: Possible case? */
1158                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1159                        __func__, dr);
1160                 *exception = UD_VECTOR;
1161                 return;
1162         }
1163 }
1164
1165 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1166 {
1167         u64 fault_address;
1168         u32 error_code;
1169
1170         fault_address  = svm->vmcb->control.exit_info_2;
1171         error_code = svm->vmcb->control.exit_info_1;
1172
1173         trace_kvm_page_fault(fault_address, error_code);
1174         /*
1175          * FIXME: Tis shouldn't be necessary here, but there is a flush
1176          * missing in the MMU code. Until we find this bug, flush the
1177          * complete TLB here on an NPF
1178          */
1179         if (npt_enabled)
1180                 svm_flush_tlb(&svm->vcpu);
1181         else {
1182                 if (kvm_event_needs_reinjection(&svm->vcpu))
1183                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1184         }
1185         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1186 }
1187
1188 static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1189 {
1190         if (!(svm->vcpu.guest_debug &
1191               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1192                 !svm->vcpu.arch.singlestep) {
1193                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1194                 return 1;
1195         }
1196
1197         if (svm->vcpu.arch.singlestep) {
1198                 svm->vcpu.arch.singlestep = false;
1199                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1200                         svm->vmcb->save.rflags &=
1201                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1202                 update_db_intercept(&svm->vcpu);
1203         }
1204
1205         if (svm->vcpu.guest_debug &
1206             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1207                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1208                 kvm_run->debug.arch.pc =
1209                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1210                 kvm_run->debug.arch.exception = DB_VECTOR;
1211                 return 0;
1212         }
1213
1214         return 1;
1215 }
1216
1217 static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1218 {
1219         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1220         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1221         kvm_run->debug.arch.exception = BP_VECTOR;
1222         return 0;
1223 }
1224
1225 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1226 {
1227         int er;
1228
1229         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1230         if (er != EMULATE_DONE)
1231                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1232         return 1;
1233 }
1234
1235 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1236 {
1237         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1238         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1239                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1240         svm->vcpu.fpu_active = 1;
1241
1242         return 1;
1243 }
1244
1245 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1246 {
1247         /*
1248          * On an #MC intercept the MCE handler is not called automatically in
1249          * the host. So do it by hand here.
1250          */
1251         asm volatile (
1252                 "int $0x12\n");
1253         /* not sure if we ever come back to this point */
1254
1255         return 1;
1256 }
1257
1258 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1259 {
1260         /*
1261          * VMCB is undefined after a SHUTDOWN intercept
1262          * so reinitialize it.
1263          */
1264         clear_page(svm->vmcb);
1265         init_vmcb(svm);
1266
1267         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1268         return 0;
1269 }
1270
1271 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1272 {
1273         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1274         int size, in, string;
1275         unsigned port;
1276
1277         ++svm->vcpu.stat.io_exits;
1278
1279         svm->next_rip = svm->vmcb->control.exit_info_2;
1280
1281         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1282
1283         if (string) {
1284                 if (emulate_instruction(&svm->vcpu,
1285                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1286                         return 0;
1287                 return 1;
1288         }
1289
1290         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1291         port = io_info >> 16;
1292         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1293
1294         skip_emulated_instruction(&svm->vcpu);
1295         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1296 }
1297
1298 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1299 {
1300         return 1;
1301 }
1302
1303 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1304 {
1305         ++svm->vcpu.stat.irq_exits;
1306         return 1;
1307 }
1308
1309 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1310 {
1311         return 1;
1312 }
1313
1314 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1315 {
1316         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1317         skip_emulated_instruction(&svm->vcpu);
1318         return kvm_emulate_halt(&svm->vcpu);
1319 }
1320
1321 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1322 {
1323         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1324         skip_emulated_instruction(&svm->vcpu);
1325         kvm_emulate_hypercall(&svm->vcpu);
1326         return 1;
1327 }
1328
1329 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1330 {
1331         if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1332             || !is_paging(&svm->vcpu)) {
1333                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1334                 return 1;
1335         }
1336
1337         if (svm->vmcb->save.cpl) {
1338                 kvm_inject_gp(&svm->vcpu, 0);
1339                 return 1;
1340         }
1341
1342        return 0;
1343 }
1344
1345 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1346                                       bool has_error_code, u32 error_code)
1347 {
1348         if (is_nested(svm)) {
1349                 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1350                 svm->vmcb->control.exit_code_hi = 0;
1351                 svm->vmcb->control.exit_info_1 = error_code;
1352                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1353                 if (nested_svm_exit_handled(svm, false)) {
1354                         nsvm_printk("VMexit -> EXCP 0x%x\n", nr);
1355
1356                         nested_svm_vmexit(svm);
1357                         return 1;
1358                 }
1359         }
1360
1361         return 0;
1362 }
1363
1364 static inline int nested_svm_intr(struct vcpu_svm *svm)
1365 {
1366         if (is_nested(svm)) {
1367                 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1368                         return 0;
1369
1370                 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1371                         return 0;
1372
1373                 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1374
1375                 if (nested_svm_exit_handled(svm, false)) {
1376                         nsvm_printk("VMexit -> INTR\n");
1377                         nested_svm_vmexit(svm);
1378                         return 1;
1379                 }
1380         }
1381
1382         return 0;
1383 }
1384
1385 static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1386 {
1387         struct page *page;
1388
1389         down_read(&current->mm->mmap_sem);
1390         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1391         up_read(&current->mm->mmap_sem);
1392
1393         if (is_error_page(page)) {
1394                 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1395                        __func__, gpa);
1396                 kvm_release_page_clean(page);
1397                 kvm_inject_gp(&svm->vcpu, 0);
1398                 return NULL;
1399         }
1400         return page;
1401 }
1402
1403 static int nested_svm_do(struct vcpu_svm *svm,
1404                          u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1405                          int (*handler)(struct vcpu_svm *svm,
1406                                         void *arg1,
1407                                         void *arg2,
1408                                         void *opaque))
1409 {
1410         struct page *arg1_page;
1411         struct page *arg2_page = NULL;
1412         void *arg1;
1413         void *arg2 = NULL;
1414         int retval;
1415
1416         arg1_page = nested_svm_get_page(svm, arg1_gpa);
1417         if(arg1_page == NULL)
1418                 return 1;
1419
1420         if (arg2_gpa) {
1421                 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1422                 if(arg2_page == NULL) {
1423                         kvm_release_page_clean(arg1_page);
1424                         return 1;
1425                 }
1426         }
1427
1428         arg1 = kmap_atomic(arg1_page, KM_USER0);
1429         if (arg2_gpa)
1430                 arg2 = kmap_atomic(arg2_page, KM_USER1);
1431
1432         retval = handler(svm, arg1, arg2, opaque);
1433
1434         kunmap_atomic(arg1, KM_USER0);
1435         if (arg2_gpa)
1436                 kunmap_atomic(arg2, KM_USER1);
1437
1438         kvm_release_page_dirty(arg1_page);
1439         if (arg2_gpa)
1440                 kvm_release_page_dirty(arg2_page);
1441
1442         return retval;
1443 }
1444
1445 static int nested_svm_exit_handled_real(struct vcpu_svm *svm,
1446                                         void *arg1,
1447                                         void *arg2,
1448                                         void *opaque)
1449 {
1450         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1451         bool kvm_overrides = *(bool *)opaque;
1452         u32 exit_code = svm->vmcb->control.exit_code;
1453
1454         if (kvm_overrides) {
1455                 switch (exit_code) {
1456                 case SVM_EXIT_INTR:
1457                 case SVM_EXIT_NMI:
1458                         return 0;
1459                 /* For now we are always handling NPFs when using them */
1460                 case SVM_EXIT_NPF:
1461                         if (npt_enabled)
1462                                 return 0;
1463                         break;
1464                 /* When we're shadowing, trap PFs */
1465                 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1466                         if (!npt_enabled)
1467                                 return 0;
1468                         break;
1469                 default:
1470                         break;
1471                 }
1472         }
1473
1474         switch (exit_code) {
1475         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1476                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1477                 if (nested_vmcb->control.intercept_cr_read & cr_bits)
1478                         return 1;
1479                 break;
1480         }
1481         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1482                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1483                 if (nested_vmcb->control.intercept_cr_write & cr_bits)
1484                         return 1;
1485                 break;
1486         }
1487         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1488                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1489                 if (nested_vmcb->control.intercept_dr_read & dr_bits)
1490                         return 1;
1491                 break;
1492         }
1493         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1494                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1495                 if (nested_vmcb->control.intercept_dr_write & dr_bits)
1496                         return 1;
1497                 break;
1498         }
1499         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1500                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1501                 if (nested_vmcb->control.intercept_exceptions & excp_bits)
1502                         return 1;
1503                 break;
1504         }
1505         default: {
1506                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1507                 nsvm_printk("exit code: 0x%x\n", exit_code);
1508                 if (nested_vmcb->control.intercept & exit_bits)
1509                         return 1;
1510         }
1511         }
1512
1513         return 0;
1514 }
1515
1516 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm,
1517                                        void *arg1, void *arg2,
1518                                        void *opaque)
1519 {
1520         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1521         u8 *msrpm = (u8 *)arg2;
1522         u32 t0, t1;
1523         u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1524         u32 param = svm->vmcb->control.exit_info_1 & 1;
1525
1526         if (!(nested_vmcb->control.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1527                 return 0;
1528
1529         switch(msr) {
1530         case 0 ... 0x1fff:
1531                 t0 = (msr * 2) % 8;
1532                 t1 = msr / 8;
1533                 break;
1534         case 0xc0000000 ... 0xc0001fff:
1535                 t0 = (8192 + msr - 0xc0000000) * 2;
1536                 t1 = (t0 / 8);
1537                 t0 %= 8;
1538                 break;
1539         case 0xc0010000 ... 0xc0011fff:
1540                 t0 = (16384 + msr - 0xc0010000) * 2;
1541                 t1 = (t0 / 8);
1542                 t0 %= 8;
1543                 break;
1544         default:
1545                 return 1;
1546                 break;
1547         }
1548         if (msrpm[t1] & ((1 << param) << t0))
1549                 return 1;
1550
1551         return 0;
1552 }
1553
1554 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
1555 {
1556         bool k = kvm_override;
1557
1558         switch (svm->vmcb->control.exit_code) {
1559         case SVM_EXIT_MSR:
1560                 return nested_svm_do(svm, svm->nested_vmcb,
1561                                      svm->nested_vmcb_msrpm, NULL,
1562                                      nested_svm_exit_handled_msr);
1563         default: break;
1564         }
1565
1566         return nested_svm_do(svm, svm->nested_vmcb, 0, &k,
1567                              nested_svm_exit_handled_real);
1568 }
1569
1570 static int nested_svm_vmexit_real(struct vcpu_svm *svm, void *arg1,
1571                                   void *arg2, void *opaque)
1572 {
1573         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1574         struct vmcb *hsave = svm->hsave;
1575         struct vmcb *vmcb = svm->vmcb;
1576
1577         /* Give the current vmcb to the guest */
1578         disable_gif(svm);
1579
1580         nested_vmcb->save.es     = vmcb->save.es;
1581         nested_vmcb->save.cs     = vmcb->save.cs;
1582         nested_vmcb->save.ss     = vmcb->save.ss;
1583         nested_vmcb->save.ds     = vmcb->save.ds;
1584         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
1585         nested_vmcb->save.idtr   = vmcb->save.idtr;
1586         if (npt_enabled)
1587                 nested_vmcb->save.cr3    = vmcb->save.cr3;
1588         nested_vmcb->save.cr2    = vmcb->save.cr2;
1589         nested_vmcb->save.rflags = vmcb->save.rflags;
1590         nested_vmcb->save.rip    = vmcb->save.rip;
1591         nested_vmcb->save.rsp    = vmcb->save.rsp;
1592         nested_vmcb->save.rax    = vmcb->save.rax;
1593         nested_vmcb->save.dr7    = vmcb->save.dr7;
1594         nested_vmcb->save.dr6    = vmcb->save.dr6;
1595         nested_vmcb->save.cpl    = vmcb->save.cpl;
1596
1597         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
1598         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
1599         nested_vmcb->control.int_state         = vmcb->control.int_state;
1600         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
1601         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
1602         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
1603         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
1604         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
1605         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1606         nested_vmcb->control.tlb_ctl           = 0;
1607         nested_vmcb->control.event_inj         = 0;
1608         nested_vmcb->control.event_inj_err     = 0;
1609
1610         /* We always set V_INTR_MASKING and remember the old value in hflags */
1611         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1612                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1613
1614         /* Restore the original control entries */
1615         svm->vmcb->control = hsave->control;
1616
1617         /* Kill any pending exceptions */
1618         if (svm->vcpu.arch.exception.pending == true)
1619                 nsvm_printk("WARNING: Pending Exception\n");
1620
1621         kvm_clear_exception_queue(&svm->vcpu);
1622         kvm_clear_interrupt_queue(&svm->vcpu);
1623
1624         /* Restore selected save entries */
1625         svm->vmcb->save.es = hsave->save.es;
1626         svm->vmcb->save.cs = hsave->save.cs;
1627         svm->vmcb->save.ss = hsave->save.ss;
1628         svm->vmcb->save.ds = hsave->save.ds;
1629         svm->vmcb->save.gdtr = hsave->save.gdtr;
1630         svm->vmcb->save.idtr = hsave->save.idtr;
1631         svm->vmcb->save.rflags = hsave->save.rflags;
1632         svm_set_efer(&svm->vcpu, hsave->save.efer);
1633         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1634         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1635         if (npt_enabled) {
1636                 svm->vmcb->save.cr3 = hsave->save.cr3;
1637                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1638         } else {
1639                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1640         }
1641         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1642         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1643         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1644         svm->vmcb->save.dr7 = 0;
1645         svm->vmcb->save.cpl = 0;
1646         svm->vmcb->control.exit_int_info = 0;
1647
1648         /* Exit nested SVM mode */
1649         svm->nested_vmcb = 0;
1650
1651         return 0;
1652 }
1653
1654 static int nested_svm_vmexit(struct vcpu_svm *svm)
1655 {
1656         nsvm_printk("VMexit\n");
1657         if (nested_svm_do(svm, svm->nested_vmcb, 0,
1658                           NULL, nested_svm_vmexit_real))
1659                 return 1;
1660
1661         kvm_mmu_reset_context(&svm->vcpu);
1662         kvm_mmu_load(&svm->vcpu);
1663
1664         return 0;
1665 }
1666
1667 static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1668                                   void *arg2, void *opaque)
1669 {
1670         int i;
1671         u32 *nested_msrpm = (u32*)arg1;
1672         for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1673                 svm->nested_msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1674         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested_msrpm);
1675
1676         return 0;
1677 }
1678
1679 static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1680                             void *arg2, void *opaque)
1681 {
1682         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1683         struct vmcb *hsave = svm->hsave;
1684
1685         /* nested_vmcb is our indicator if nested SVM is activated */
1686         svm->nested_vmcb = svm->vmcb->save.rax;
1687
1688         /* Clear internal status */
1689         kvm_clear_exception_queue(&svm->vcpu);
1690         kvm_clear_interrupt_queue(&svm->vcpu);
1691
1692         /* Save the old vmcb, so we don't need to pick what we save, but
1693            can restore everything when a VMEXIT occurs */
1694         memcpy(hsave, svm->vmcb, sizeof(struct vmcb));
1695         /* We need to remember the original CR3 in the SPT case */
1696         if (!npt_enabled)
1697                 hsave->save.cr3 = svm->vcpu.arch.cr3;
1698         hsave->save.cr4 = svm->vcpu.arch.cr4;
1699         hsave->save.rip = svm->next_rip;
1700
1701         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1702                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1703         else
1704                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1705
1706         /* Load the nested guest state */
1707         svm->vmcb->save.es = nested_vmcb->save.es;
1708         svm->vmcb->save.cs = nested_vmcb->save.cs;
1709         svm->vmcb->save.ss = nested_vmcb->save.ss;
1710         svm->vmcb->save.ds = nested_vmcb->save.ds;
1711         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1712         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1713         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1714         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1715         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1716         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1717         if (npt_enabled) {
1718                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1719                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1720         } else {
1721                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1722                 kvm_mmu_reset_context(&svm->vcpu);
1723         }
1724         svm->vmcb->save.cr2 = nested_vmcb->save.cr2;
1725         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1726         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1727         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1728         /* In case we don't even reach vcpu_run, the fields are not updated */
1729         svm->vmcb->save.rax = nested_vmcb->save.rax;
1730         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1731         svm->vmcb->save.rip = nested_vmcb->save.rip;
1732         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1733         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1734         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1735
1736         /* We don't want a nested guest to be more powerful than the guest,
1737            so all intercepts are ORed */
1738         svm->vmcb->control.intercept_cr_read |=
1739                 nested_vmcb->control.intercept_cr_read;
1740         svm->vmcb->control.intercept_cr_write |=
1741                 nested_vmcb->control.intercept_cr_write;
1742         svm->vmcb->control.intercept_dr_read |=
1743                 nested_vmcb->control.intercept_dr_read;
1744         svm->vmcb->control.intercept_dr_write |=
1745                 nested_vmcb->control.intercept_dr_write;
1746         svm->vmcb->control.intercept_exceptions |=
1747                 nested_vmcb->control.intercept_exceptions;
1748
1749         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1750
1751         svm->nested_vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1752
1753         force_new_asid(&svm->vcpu);
1754         svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1755         svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1756         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1757         if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1758                 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1759                                 nested_vmcb->control.int_ctl);
1760         }
1761         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1762                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1763         else
1764                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1765
1766         nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1767                         nested_vmcb->control.exit_int_info,
1768                         nested_vmcb->control.int_state);
1769
1770         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1771         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1772         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1773         if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1774                 nsvm_printk("Injecting Event: 0x%x\n",
1775                                 nested_vmcb->control.event_inj);
1776         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1777         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1778
1779         enable_gif(svm);
1780
1781         return 0;
1782 }
1783
1784 static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1785 {
1786         to_vmcb->save.fs = from_vmcb->save.fs;
1787         to_vmcb->save.gs = from_vmcb->save.gs;
1788         to_vmcb->save.tr = from_vmcb->save.tr;
1789         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1790         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1791         to_vmcb->save.star = from_vmcb->save.star;
1792         to_vmcb->save.lstar = from_vmcb->save.lstar;
1793         to_vmcb->save.cstar = from_vmcb->save.cstar;
1794         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1795         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1796         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1797         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1798
1799         return 1;
1800 }
1801
1802 static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1803                              void *arg2, void *opaque)
1804 {
1805         return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1806 }
1807
1808 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1809                              void *arg2, void *opaque)
1810 {
1811         return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1812 }
1813
1814 static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1815 {
1816         if (nested_svm_check_permissions(svm))
1817                 return 1;
1818
1819         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1820         skip_emulated_instruction(&svm->vcpu);
1821
1822         nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1823
1824         return 1;
1825 }
1826
1827 static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1828 {
1829         if (nested_svm_check_permissions(svm))
1830                 return 1;
1831
1832         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1833         skip_emulated_instruction(&svm->vcpu);
1834
1835         nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1836
1837         return 1;
1838 }
1839
1840 static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1841 {
1842         nsvm_printk("VMrun\n");
1843         if (nested_svm_check_permissions(svm))
1844                 return 1;
1845
1846         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1847         skip_emulated_instruction(&svm->vcpu);
1848
1849         if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1850                           NULL, nested_svm_vmrun))
1851                 return 1;
1852
1853         if (nested_svm_do(svm, svm->nested_vmcb_msrpm, 0,
1854                       NULL, nested_svm_vmrun_msrpm))
1855                 return 1;
1856
1857         return 1;
1858 }
1859
1860 static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1861 {
1862         if (nested_svm_check_permissions(svm))
1863                 return 1;
1864
1865         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1866         skip_emulated_instruction(&svm->vcpu);
1867
1868         enable_gif(svm);
1869
1870         return 1;
1871 }
1872
1873 static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1874 {
1875         if (nested_svm_check_permissions(svm))
1876                 return 1;
1877
1878         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1879         skip_emulated_instruction(&svm->vcpu);
1880
1881         disable_gif(svm);
1882
1883         /* After a CLGI no interrupts should come */
1884         svm_clear_vintr(svm);
1885         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1886
1887         return 1;
1888 }
1889
1890 static int invlpga_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1891 {
1892         struct kvm_vcpu *vcpu = &svm->vcpu;
1893         nsvm_printk("INVLPGA\n");
1894
1895         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1896         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1897
1898         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1899         skip_emulated_instruction(&svm->vcpu);
1900         return 1;
1901 }
1902
1903 static int invalid_op_interception(struct vcpu_svm *svm,
1904                                    struct kvm_run *kvm_run)
1905 {
1906         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1907         return 1;
1908 }
1909
1910 static int task_switch_interception(struct vcpu_svm *svm,
1911                                     struct kvm_run *kvm_run)
1912 {
1913         u16 tss_selector;
1914         int reason;
1915         int int_type = svm->vmcb->control.exit_int_info &
1916                 SVM_EXITINTINFO_TYPE_MASK;
1917         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
1918         uint32_t type =
1919                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1920         uint32_t idt_v =
1921                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
1922
1923         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1924
1925         if (svm->vmcb->control.exit_info_2 &
1926             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1927                 reason = TASK_SWITCH_IRET;
1928         else if (svm->vmcb->control.exit_info_2 &
1929                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1930                 reason = TASK_SWITCH_JMP;
1931         else if (idt_v)
1932                 reason = TASK_SWITCH_GATE;
1933         else
1934                 reason = TASK_SWITCH_CALL;
1935
1936         if (reason == TASK_SWITCH_GATE) {
1937                 switch (type) {
1938                 case SVM_EXITINTINFO_TYPE_NMI:
1939                         svm->vcpu.arch.nmi_injected = false;
1940                         break;
1941                 case SVM_EXITINTINFO_TYPE_EXEPT:
1942                         kvm_clear_exception_queue(&svm->vcpu);
1943                         break;
1944                 case SVM_EXITINTINFO_TYPE_INTR:
1945                         kvm_clear_interrupt_queue(&svm->vcpu);
1946                         break;
1947                 default:
1948                         break;
1949                 }
1950         }
1951
1952         if (reason != TASK_SWITCH_GATE ||
1953             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
1954             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
1955              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
1956                 skip_emulated_instruction(&svm->vcpu);
1957
1958         return kvm_task_switch(&svm->vcpu, tss_selector, reason);
1959 }
1960
1961 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1962 {
1963         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1964         kvm_emulate_cpuid(&svm->vcpu);
1965         return 1;
1966 }
1967
1968 static int iret_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1969 {
1970         ++svm->vcpu.stat.nmi_window_exits;
1971         svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
1972         svm->vcpu.arch.hflags |= HF_IRET_MASK;
1973         return 1;
1974 }
1975
1976 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1977 {
1978         if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1979                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1980         return 1;
1981 }
1982
1983 static int emulate_on_interception(struct vcpu_svm *svm,
1984                                    struct kvm_run *kvm_run)
1985 {
1986         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1987                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1988         return 1;
1989 }
1990
1991 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1992 {
1993         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
1994         /* instruction emulation calls kvm_set_cr8() */
1995         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1996         if (irqchip_in_kernel(svm->vcpu.kvm)) {
1997                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1998                 return 1;
1999         }
2000         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2001                 return 1;
2002         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2003         return 0;
2004 }
2005
2006 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2007 {
2008         struct vcpu_svm *svm = to_svm(vcpu);
2009
2010         switch (ecx) {
2011         case MSR_IA32_TSC: {
2012                 u64 tsc;
2013
2014                 rdtscll(tsc);
2015                 *data = svm->vmcb->control.tsc_offset + tsc;
2016                 break;
2017         }
2018         case MSR_K6_STAR:
2019                 *data = svm->vmcb->save.star;
2020                 break;
2021 #ifdef CONFIG_X86_64
2022         case MSR_LSTAR:
2023                 *data = svm->vmcb->save.lstar;
2024                 break;
2025         case MSR_CSTAR:
2026                 *data = svm->vmcb->save.cstar;
2027                 break;
2028         case MSR_KERNEL_GS_BASE:
2029                 *data = svm->vmcb->save.kernel_gs_base;
2030                 break;
2031         case MSR_SYSCALL_MASK:
2032                 *data = svm->vmcb->save.sfmask;
2033                 break;
2034 #endif
2035         case MSR_IA32_SYSENTER_CS:
2036                 *data = svm->vmcb->save.sysenter_cs;
2037                 break;
2038         case MSR_IA32_SYSENTER_EIP:
2039                 *data = svm->sysenter_eip;
2040                 break;
2041         case MSR_IA32_SYSENTER_ESP:
2042                 *data = svm->sysenter_esp;
2043                 break;
2044         /* Nobody will change the following 5 values in the VMCB so
2045            we can safely return them on rdmsr. They will always be 0
2046            until LBRV is implemented. */
2047         case MSR_IA32_DEBUGCTLMSR:
2048                 *data = svm->vmcb->save.dbgctl;
2049                 break;
2050         case MSR_IA32_LASTBRANCHFROMIP:
2051                 *data = svm->vmcb->save.br_from;
2052                 break;
2053         case MSR_IA32_LASTBRANCHTOIP:
2054                 *data = svm->vmcb->save.br_to;
2055                 break;
2056         case MSR_IA32_LASTINTFROMIP:
2057                 *data = svm->vmcb->save.last_excp_from;
2058                 break;
2059         case MSR_IA32_LASTINTTOIP:
2060                 *data = svm->vmcb->save.last_excp_to;
2061                 break;
2062         case MSR_VM_HSAVE_PA:
2063                 *data = svm->hsave_msr;
2064                 break;
2065         case MSR_VM_CR:
2066                 *data = 0;
2067                 break;
2068         case MSR_IA32_UCODE_REV:
2069                 *data = 0x01000065;
2070                 break;
2071         default:
2072                 return kvm_get_msr_common(vcpu, ecx, data);
2073         }
2074         return 0;
2075 }
2076
2077 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2078 {
2079         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2080         u64 data;
2081
2082         if (svm_get_msr(&svm->vcpu, ecx, &data))
2083                 kvm_inject_gp(&svm->vcpu, 0);
2084         else {
2085                 trace_kvm_msr_read(ecx, data);
2086
2087                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2088                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2089                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2090                 skip_emulated_instruction(&svm->vcpu);
2091         }
2092         return 1;
2093 }
2094
2095 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2096 {
2097         struct vcpu_svm *svm = to_svm(vcpu);
2098
2099         switch (ecx) {
2100         case MSR_IA32_TSC: {
2101                 u64 tsc;
2102
2103                 rdtscll(tsc);
2104                 svm->vmcb->control.tsc_offset = data - tsc;
2105                 break;
2106         }
2107         case MSR_K6_STAR:
2108                 svm->vmcb->save.star = data;
2109                 break;
2110 #ifdef CONFIG_X86_64
2111         case MSR_LSTAR:
2112                 svm->vmcb->save.lstar = data;
2113                 break;
2114         case MSR_CSTAR:
2115                 svm->vmcb->save.cstar = data;
2116                 break;
2117         case MSR_KERNEL_GS_BASE:
2118                 svm->vmcb->save.kernel_gs_base = data;
2119                 break;
2120         case MSR_SYSCALL_MASK:
2121                 svm->vmcb->save.sfmask = data;
2122                 break;
2123 #endif
2124         case MSR_IA32_SYSENTER_CS:
2125                 svm->vmcb->save.sysenter_cs = data;
2126                 break;
2127         case MSR_IA32_SYSENTER_EIP:
2128                 svm->sysenter_eip = data;
2129                 svm->vmcb->save.sysenter_eip = data;
2130                 break;
2131         case MSR_IA32_SYSENTER_ESP:
2132                 svm->sysenter_esp = data;
2133                 svm->vmcb->save.sysenter_esp = data;
2134                 break;
2135         case MSR_IA32_DEBUGCTLMSR:
2136                 if (!svm_has(SVM_FEATURE_LBRV)) {
2137                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2138                                         __func__, data);
2139                         break;
2140                 }
2141                 if (data & DEBUGCTL_RESERVED_BITS)
2142                         return 1;
2143
2144                 svm->vmcb->save.dbgctl = data;
2145                 if (data & (1ULL<<0))
2146                         svm_enable_lbrv(svm);
2147                 else
2148                         svm_disable_lbrv(svm);
2149                 break;
2150         case MSR_VM_HSAVE_PA:
2151                 svm->hsave_msr = data;
2152                 break;
2153         case MSR_VM_CR:
2154         case MSR_VM_IGNNE:
2155                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2156                 break;
2157         default:
2158                 return kvm_set_msr_common(vcpu, ecx, data);
2159         }
2160         return 0;
2161 }
2162
2163 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2164 {
2165         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2166         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2167                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2168
2169         trace_kvm_msr_write(ecx, data);
2170
2171         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2172         if (svm_set_msr(&svm->vcpu, ecx, data))
2173                 kvm_inject_gp(&svm->vcpu, 0);
2174         else
2175                 skip_emulated_instruction(&svm->vcpu);
2176         return 1;
2177 }
2178
2179 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2180 {
2181         if (svm->vmcb->control.exit_info_1)
2182                 return wrmsr_interception(svm, kvm_run);
2183         else
2184                 return rdmsr_interception(svm, kvm_run);
2185 }
2186
2187 static int interrupt_window_interception(struct vcpu_svm *svm,
2188                                    struct kvm_run *kvm_run)
2189 {
2190         svm_clear_vintr(svm);
2191         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2192         /*
2193          * If the user space waits to inject interrupts, exit as soon as
2194          * possible
2195          */
2196         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2197             kvm_run->request_interrupt_window &&
2198             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2199                 ++svm->vcpu.stat.irq_window_exits;
2200                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2201                 return 0;
2202         }
2203
2204         return 1;
2205 }
2206
2207 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
2208                                       struct kvm_run *kvm_run) = {
2209         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2210         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2211         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2212         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2213         /* for now: */
2214         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2215         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2216         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2217         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2218         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2219         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2220         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2221         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2222         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2223         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2224         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2225         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2226         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2227         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2228         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2229         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2230         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2231         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2232         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2233         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2234         [SVM_EXIT_INTR]                         = intr_interception,
2235         [SVM_EXIT_NMI]                          = nmi_interception,
2236         [SVM_EXIT_SMI]                          = nop_on_interception,
2237         [SVM_EXIT_INIT]                         = nop_on_interception,
2238         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2239         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
2240         [SVM_EXIT_CPUID]                        = cpuid_interception,
2241         [SVM_EXIT_IRET]                         = iret_interception,
2242         [SVM_EXIT_INVD]                         = emulate_on_interception,
2243         [SVM_EXIT_HLT]                          = halt_interception,
2244         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2245         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2246         [SVM_EXIT_IOIO]                         = io_interception,
2247         [SVM_EXIT_MSR]                          = msr_interception,
2248         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2249         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2250         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2251         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2252         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2253         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2254         [SVM_EXIT_STGI]                         = stgi_interception,
2255         [SVM_EXIT_CLGI]                         = clgi_interception,
2256         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
2257         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2258         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2259         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2260         [SVM_EXIT_NPF]                          = pf_interception,
2261 };
2262
2263 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2264 {
2265         struct vcpu_svm *svm = to_svm(vcpu);
2266         u32 exit_code = svm->vmcb->control.exit_code;
2267
2268         trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2269
2270         if (is_nested(svm)) {
2271                 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2272                             exit_code, svm->vmcb->control.exit_info_1,
2273                             svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2274                 if (nested_svm_exit_handled(svm, true)) {
2275                         nested_svm_vmexit(svm);
2276                         nsvm_printk("-> #VMEXIT\n");
2277                         return 1;
2278                 }
2279         }
2280
2281         if (npt_enabled) {
2282                 int mmu_reload = 0;
2283                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2284                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2285                         mmu_reload = 1;
2286                 }
2287                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2288                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2289                 if (mmu_reload) {
2290                         kvm_mmu_reset_context(vcpu);
2291                         kvm_mmu_load(vcpu);
2292                 }
2293         }
2294
2295
2296         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2297                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2298                 kvm_run->fail_entry.hardware_entry_failure_reason
2299                         = svm->vmcb->control.exit_code;
2300                 return 0;
2301         }
2302
2303         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2304             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2305             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2306                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2307                        "exit_code 0x%x\n",
2308                        __func__, svm->vmcb->control.exit_int_info,
2309                        exit_code);
2310
2311         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2312             || !svm_exit_handlers[exit_code]) {
2313                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2314                 kvm_run->hw.hardware_exit_reason = exit_code;
2315                 return 0;
2316         }
2317
2318         return svm_exit_handlers[exit_code](svm, kvm_run);
2319 }
2320
2321 static void reload_tss(struct kvm_vcpu *vcpu)
2322 {
2323         int cpu = raw_smp_processor_id();
2324
2325         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2326         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
2327         load_TR_desc();
2328 }
2329
2330 static void pre_svm_run(struct vcpu_svm *svm)
2331 {
2332         int cpu = raw_smp_processor_id();
2333
2334         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2335
2336         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2337         /* FIXME: handle wraparound of asid_generation */
2338         if (svm->asid_generation != svm_data->asid_generation)
2339                 new_asid(svm, svm_data);
2340 }
2341
2342 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2343 {
2344         struct vcpu_svm *svm = to_svm(vcpu);
2345
2346         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2347         vcpu->arch.hflags |= HF_NMI_MASK;
2348         svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2349         ++vcpu->stat.nmi_injections;
2350 }
2351
2352 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2353 {
2354         struct vmcb_control_area *control;
2355
2356         trace_kvm_inj_virq(irq);
2357
2358         ++svm->vcpu.stat.irq_injections;
2359         control = &svm->vmcb->control;
2360         control->int_vector = irq;
2361         control->int_ctl &= ~V_INTR_PRIO_MASK;
2362         control->int_ctl |= V_IRQ_MASK |
2363                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2364 }
2365
2366 static void svm_set_irq(struct kvm_vcpu *vcpu)
2367 {
2368         struct vcpu_svm *svm = to_svm(vcpu);
2369
2370         BUG_ON(!(gif_set(svm)));
2371
2372         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2373                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2374 }
2375
2376 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2377 {
2378         struct vcpu_svm *svm = to_svm(vcpu);
2379
2380         if (irr == -1)
2381                 return;
2382
2383         if (tpr >= irr)
2384                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2385 }
2386
2387 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2388 {
2389         struct vcpu_svm *svm = to_svm(vcpu);
2390         struct vmcb *vmcb = svm->vmcb;
2391         return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2392                 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2393 }
2394
2395 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2396 {
2397         struct vcpu_svm *svm = to_svm(vcpu);
2398         struct vmcb *vmcb = svm->vmcb;
2399         return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2400                 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2401                 gif_set(svm) &&
2402                 !is_nested(svm);
2403 }
2404
2405 static void enable_irq_window(struct kvm_vcpu *vcpu)
2406 {
2407         struct vcpu_svm *svm = to_svm(vcpu);
2408         nsvm_printk("Trying to open IRQ window\n");
2409
2410         nested_svm_intr(svm);
2411
2412         /* In case GIF=0 we can't rely on the CPU to tell us when
2413          * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2414          * The next time we get that intercept, this function will be
2415          * called again though and we'll get the vintr intercept. */
2416         if (gif_set(svm)) {
2417                 svm_set_vintr(svm);
2418                 svm_inject_irq(svm, 0x0);
2419         }
2420 }
2421
2422 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2423 {
2424         struct vcpu_svm *svm = to_svm(vcpu);
2425
2426         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2427             == HF_NMI_MASK)
2428                 return; /* IRET will cause a vm exit */
2429
2430         /* Something prevents NMI from been injected. Single step over
2431            possible problem (IRET or exception injection or interrupt
2432            shadow) */
2433         vcpu->arch.singlestep = true;
2434         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2435         update_db_intercept(vcpu);
2436 }
2437
2438 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2439 {
2440         return 0;
2441 }
2442
2443 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2444 {
2445         force_new_asid(vcpu);
2446 }
2447
2448 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2449 {
2450 }
2451
2452 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2453 {
2454         struct vcpu_svm *svm = to_svm(vcpu);
2455
2456         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2457                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2458                 kvm_set_cr8(vcpu, cr8);
2459         }
2460 }
2461
2462 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2463 {
2464         struct vcpu_svm *svm = to_svm(vcpu);
2465         u64 cr8;
2466
2467         cr8 = kvm_get_cr8(vcpu);
2468         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2469         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2470 }
2471
2472 static void svm_complete_interrupts(struct vcpu_svm *svm)
2473 {
2474         u8 vector;
2475         int type;
2476         u32 exitintinfo = svm->vmcb->control.exit_int_info;
2477
2478         if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2479                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2480
2481         svm->vcpu.arch.nmi_injected = false;
2482         kvm_clear_exception_queue(&svm->vcpu);
2483         kvm_clear_interrupt_queue(&svm->vcpu);
2484
2485         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2486                 return;
2487
2488         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2489         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2490
2491         switch (type) {
2492         case SVM_EXITINTINFO_TYPE_NMI:
2493                 svm->vcpu.arch.nmi_injected = true;
2494                 break;
2495         case SVM_EXITINTINFO_TYPE_EXEPT:
2496                 /* In case of software exception do not reinject an exception
2497                    vector, but re-execute and instruction instead */
2498                 if (is_nested(svm))
2499                         break;
2500                 if (kvm_exception_is_soft(vector))
2501                         break;
2502                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2503                         u32 err = svm->vmcb->control.exit_int_info_err;
2504                         kvm_queue_exception_e(&svm->vcpu, vector, err);
2505
2506                 } else
2507                         kvm_queue_exception(&svm->vcpu, vector);
2508                 break;
2509         case SVM_EXITINTINFO_TYPE_INTR:
2510                 kvm_queue_interrupt(&svm->vcpu, vector, false);
2511                 break;
2512         default:
2513                 break;
2514         }
2515 }
2516
2517 #ifdef CONFIG_X86_64
2518 #define R "r"
2519 #else
2520 #define R "e"
2521 #endif
2522
2523 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2524 {
2525         struct vcpu_svm *svm = to_svm(vcpu);
2526         u16 fs_selector;
2527         u16 gs_selector;
2528         u16 ldt_selector;
2529
2530         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2531         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2532         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2533
2534         pre_svm_run(svm);
2535
2536         sync_lapic_to_cr8(vcpu);
2537
2538         save_host_msrs(vcpu);
2539         fs_selector = kvm_read_fs();
2540         gs_selector = kvm_read_gs();
2541         ldt_selector = kvm_read_ldt();
2542         if (!is_nested(svm))
2543                 svm->vmcb->save.cr2 = vcpu->arch.cr2;
2544         /* required for live migration with NPT */
2545         if (npt_enabled)
2546                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2547
2548         clgi();
2549
2550         local_irq_enable();
2551
2552         asm volatile (
2553                 "push %%"R"bp; \n\t"
2554                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2555                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2556                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2557                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2558                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2559                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2560 #ifdef CONFIG_X86_64
2561                 "mov %c[r8](%[svm]),  %%r8  \n\t"
2562                 "mov %c[r9](%[svm]),  %%r9  \n\t"
2563                 "mov %c[r10](%[svm]), %%r10 \n\t"
2564                 "mov %c[r11](%[svm]), %%r11 \n\t"
2565                 "mov %c[r12](%[svm]), %%r12 \n\t"
2566                 "mov %c[r13](%[svm]), %%r13 \n\t"
2567                 "mov %c[r14](%[svm]), %%r14 \n\t"
2568                 "mov %c[r15](%[svm]), %%r15 \n\t"
2569 #endif
2570
2571                 /* Enter guest mode */
2572                 "push %%"R"ax \n\t"
2573                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2574                 __ex(SVM_VMLOAD) "\n\t"
2575                 __ex(SVM_VMRUN) "\n\t"
2576                 __ex(SVM_VMSAVE) "\n\t"
2577                 "pop %%"R"ax \n\t"
2578
2579                 /* Save guest registers, load host registers */
2580                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2581                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2582                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2583                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2584                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2585                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2586 #ifdef CONFIG_X86_64
2587                 "mov %%r8,  %c[r8](%[svm]) \n\t"
2588                 "mov %%r9,  %c[r9](%[svm]) \n\t"
2589                 "mov %%r10, %c[r10](%[svm]) \n\t"
2590                 "mov %%r11, %c[r11](%[svm]) \n\t"
2591                 "mov %%r12, %c[r12](%[svm]) \n\t"
2592                 "mov %%r13, %c[r13](%[svm]) \n\t"
2593                 "mov %%r14, %c[r14](%[svm]) \n\t"
2594                 "mov %%r15, %c[r15](%[svm]) \n\t"
2595 #endif
2596                 "pop %%"R"bp"
2597                 :
2598                 : [svm]"a"(svm),
2599                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2600                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2601                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2602                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2603                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2604                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2605                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2606 #ifdef CONFIG_X86_64
2607                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2608                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2609                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2610                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2611                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2612                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2613                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2614                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2615 #endif
2616                 : "cc", "memory"
2617                 , R"bx", R"cx", R"dx", R"si", R"di"
2618 #ifdef CONFIG_X86_64
2619                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2620 #endif
2621                 );
2622
2623         vcpu->arch.cr2 = svm->vmcb->save.cr2;
2624         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2625         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2626         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2627
2628         kvm_load_fs(fs_selector);
2629         kvm_load_gs(gs_selector);
2630         kvm_load_ldt(ldt_selector);
2631         load_host_msrs(vcpu);
2632
2633         reload_tss(vcpu);
2634
2635         local_irq_disable();
2636
2637         stgi();
2638
2639         sync_cr8_to_lapic(vcpu);
2640
2641         svm->next_rip = 0;
2642
2643         if (npt_enabled) {
2644                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2645                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2646         }
2647
2648         svm_complete_interrupts(svm);
2649 }
2650
2651 #undef R
2652
2653 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2654 {
2655         struct vcpu_svm *svm = to_svm(vcpu);
2656
2657         if (npt_enabled) {
2658                 svm->vmcb->control.nested_cr3 = root;
2659                 force_new_asid(vcpu);
2660                 return;
2661         }
2662
2663         svm->vmcb->save.cr3 = root;
2664         force_new_asid(vcpu);
2665
2666         if (vcpu->fpu_active) {
2667                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2668                 svm->vmcb->save.cr0 |= X86_CR0_TS;
2669                 vcpu->fpu_active = 0;
2670         }
2671 }
2672
2673 static int is_disabled(void)
2674 {
2675         u64 vm_cr;
2676
2677         rdmsrl(MSR_VM_CR, vm_cr);
2678         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2679                 return 1;
2680
2681         return 0;
2682 }
2683
2684 static void
2685 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2686 {
2687         /*
2688          * Patch in the VMMCALL instruction:
2689          */
2690         hypercall[0] = 0x0f;
2691         hypercall[1] = 0x01;
2692         hypercall[2] = 0xd9;
2693 }
2694
2695 static void svm_check_processor_compat(void *rtn)
2696 {
2697         *(int *)rtn = 0;
2698 }
2699
2700 static bool svm_cpu_has_accelerated_tpr(void)
2701 {
2702         return false;
2703 }
2704
2705 static int get_npt_level(void)
2706 {
2707 #ifdef CONFIG_X86_64
2708         return PT64_ROOT_LEVEL;
2709 #else
2710         return PT32E_ROOT_LEVEL;
2711 #endif
2712 }
2713
2714 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2715 {
2716         return 0;
2717 }
2718
2719 static const struct trace_print_flags svm_exit_reasons_str[] = {
2720         { SVM_EXIT_READ_CR0,                    "read_cr0" },
2721         { SVM_EXIT_READ_CR3,                    "read_cr3" },
2722         { SVM_EXIT_READ_CR4,                    "read_cr4" },
2723         { SVM_EXIT_READ_CR8,                    "read_cr8" },
2724         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
2725         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
2726         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
2727         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
2728         { SVM_EXIT_READ_DR0,                    "read_dr0" },
2729         { SVM_EXIT_READ_DR1,                    "read_dr1" },
2730         { SVM_EXIT_READ_DR2,                    "read_dr2" },
2731         { SVM_EXIT_READ_DR3,                    "read_dr3" },
2732         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
2733         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
2734         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
2735         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
2736         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
2737         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
2738         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
2739         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
2740         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
2741         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
2742         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
2743         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
2744         { SVM_EXIT_INTR,                        "interrupt" },
2745         { SVM_EXIT_NMI,                         "nmi" },
2746         { SVM_EXIT_SMI,                         "smi" },
2747         { SVM_EXIT_INIT,                        "init" },
2748         { SVM_EXIT_VINTR,                       "vintr" },
2749         { SVM_EXIT_CPUID,                       "cpuid" },
2750         { SVM_EXIT_INVD,                        "invd" },
2751         { SVM_EXIT_HLT,                         "hlt" },
2752         { SVM_EXIT_INVLPG,                      "invlpg" },
2753         { SVM_EXIT_INVLPGA,                     "invlpga" },
2754         { SVM_EXIT_IOIO,                        "io" },
2755         { SVM_EXIT_MSR,                         "msr" },
2756         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
2757         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
2758         { SVM_EXIT_VMRUN,                       "vmrun" },
2759         { SVM_EXIT_VMMCALL,                     "hypercall" },
2760         { SVM_EXIT_VMLOAD,                      "vmload" },
2761         { SVM_EXIT_VMSAVE,                      "vmsave" },
2762         { SVM_EXIT_STGI,                        "stgi" },
2763         { SVM_EXIT_CLGI,                        "clgi" },
2764         { SVM_EXIT_SKINIT,                      "skinit" },
2765         { SVM_EXIT_WBINVD,                      "wbinvd" },
2766         { SVM_EXIT_MONITOR,                     "monitor" },
2767         { SVM_EXIT_MWAIT,                       "mwait" },
2768         { SVM_EXIT_NPF,                         "npf" },
2769         { -1, NULL }
2770 };
2771
2772 static bool svm_gb_page_enable(void)
2773 {
2774         return true;
2775 }
2776
2777 static struct kvm_x86_ops svm_x86_ops = {
2778         .cpu_has_kvm_support = has_svm,
2779         .disabled_by_bios = is_disabled,
2780         .hardware_setup = svm_hardware_setup,
2781         .hardware_unsetup = svm_hardware_unsetup,
2782         .check_processor_compatibility = svm_check_processor_compat,
2783         .hardware_enable = svm_hardware_enable,
2784         .hardware_disable = svm_hardware_disable,
2785         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2786
2787         .vcpu_create = svm_create_vcpu,
2788         .vcpu_free = svm_free_vcpu,
2789         .vcpu_reset = svm_vcpu_reset,
2790
2791         .prepare_guest_switch = svm_prepare_guest_switch,
2792         .vcpu_load = svm_vcpu_load,
2793         .vcpu_put = svm_vcpu_put,
2794
2795         .set_guest_debug = svm_guest_debug,
2796         .get_msr = svm_get_msr,
2797         .set_msr = svm_set_msr,
2798         .get_segment_base = svm_get_segment_base,
2799         .get_segment = svm_get_segment,
2800         .set_segment = svm_set_segment,
2801         .get_cpl = svm_get_cpl,
2802         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2803         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2804         .set_cr0 = svm_set_cr0,
2805         .set_cr3 = svm_set_cr3,
2806         .set_cr4 = svm_set_cr4,
2807         .set_efer = svm_set_efer,
2808         .get_idt = svm_get_idt,
2809         .set_idt = svm_set_idt,
2810         .get_gdt = svm_get_gdt,
2811         .set_gdt = svm_set_gdt,
2812         .get_dr = svm_get_dr,
2813         .set_dr = svm_set_dr,
2814         .cache_reg = svm_cache_reg,
2815         .get_rflags = svm_get_rflags,
2816         .set_rflags = svm_set_rflags,
2817
2818         .tlb_flush = svm_flush_tlb,
2819
2820         .run = svm_vcpu_run,
2821         .handle_exit = handle_exit,
2822         .skip_emulated_instruction = skip_emulated_instruction,
2823         .set_interrupt_shadow = svm_set_interrupt_shadow,
2824         .get_interrupt_shadow = svm_get_interrupt_shadow,
2825         .patch_hypercall = svm_patch_hypercall,
2826         .set_irq = svm_set_irq,
2827         .set_nmi = svm_inject_nmi,
2828         .queue_exception = svm_queue_exception,
2829         .interrupt_allowed = svm_interrupt_allowed,
2830         .nmi_allowed = svm_nmi_allowed,
2831         .enable_nmi_window = enable_nmi_window,
2832         .enable_irq_window = enable_irq_window,
2833         .update_cr8_intercept = update_cr8_intercept,
2834
2835         .set_tss_addr = svm_set_tss_addr,
2836         .get_tdp_level = get_npt_level,
2837         .get_mt_mask = svm_get_mt_mask,
2838
2839         .exit_reasons_str = svm_exit_reasons_str,
2840         .gb_page_enable = svm_gb_page_enable,
2841 };
2842
2843 static int __init svm_init(void)
2844 {
2845         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2846                               THIS_MODULE);
2847 }
2848
2849 static void __exit svm_exit(void)
2850 {
2851         kvm_exit();
2852 }
2853
2854 module_init(svm_init)
2855 module_exit(svm_exit)