arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   8  *
   9  * Authors:
  10  *   Yaniv Kamay  <yaniv@qumranet.com>
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17 #include <linux/kvm_host.h>
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22 #include "x86.h"
  23
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31
  32 #include <asm/tlbflush.h>
  33 #include <asm/desc.h>
  34 #include <asm/kvm_para.h>
  35
  36 #include <asm/virtext.h>
  37 #include "trace.h"
  38
  39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  40
  41 MODULE_AUTHOR("Qumranet");
  42 MODULE_LICENSE("GPL");
  43
  44 #define IOPM_ALLOC_ORDER 2
  45 #define MSRPM_ALLOC_ORDER 1
  46
  47 #define SEG_TYPE_LDT 2
  48 #define SEG_TYPE_BUSY_TSS16 3
  49
  50 #define SVM_FEATURE_NPT            (1 <<  0)
  51 #define SVM_FEATURE_LBRV           (1 <<  1)
  52 #define SVM_FEATURE_SVML           (1 <<  2)
  53 #define SVM_FEATURE_NRIP           (1 <<  3)
  54 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  55
  56 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  57 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  58 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  59
  60 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  61
  62 static bool erratum_383_found __read_mostly;
  63
  64 static const u32 host_save_user_msrs[] = {
  65 #ifdef CONFIG_X86_64
  66         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  67         MSR_FS_BASE,
  68 #endif
  69         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  70 };
  71
  72 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  73
  74 struct kvm_vcpu;
  75
  76 struct nested_state {
  77         struct vmcb *hsave;
  78         u64 hsave_msr;
  79         u64 vm_cr_msr;
  80         u64 vmcb;
  81
  82         /* These are the merged vectors */
  83         u32 *msrpm;
  84
  85         /* gpa pointers to the real vectors */
  86         u64 vmcb_msrpm;
  87         u64 vmcb_iopm;
  88
  89         /* A VMEXIT is required but not yet emulated */
  90         bool exit_required;
  91
  92         /*
  93          * If we vmexit during an instruction emulation we need this to restore
  94          * the l1 guest rip after the emulation
  95          */
  96         unsigned long vmexit_rip;
  97         unsigned long vmexit_rsp;
  98         unsigned long vmexit_rax;
  99
 100         /* cache for intercepts of the guest */
 101         u16 intercept_cr_read;
 102         u16 intercept_cr_write;
 103         u16 intercept_dr_read;
 104         u16 intercept_dr_write;
 105         u32 intercept_exceptions;
 106         u64 intercept;
 107
 108         /* Nested Paging related state */
 109         u64 nested_cr3;
 110 };
 111
 112 #define MSRPM_OFFSETS   16
 113 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
 114
 115 struct vcpu_svm {
 116         struct kvm_vcpu vcpu;
 117         struct vmcb *vmcb;
 118         unsigned long vmcb_pa;
 119         struct svm_cpu_data *svm_data;
 120         uint64_t asid_generation;
 121         uint64_t sysenter_esp;
 122         uint64_t sysenter_eip;
 123
 124         u64 next_rip;
 125
 126         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 127         struct {
 128                 u16 fs;
 129                 u16 gs;
 130                 u16 ldt;
 131                 u64 gs_base;
 132         } host;
 133
 134         u32 *msrpm;
 135
 136         struct nested_state nested;
 137
 138         bool nmi_singlestep;
 139
 140         unsigned int3_injected;
 141         unsigned long int3_rip;
 142         u32 apf_reason;
 143 };
 144
 145 #define MSR_INVALID                     0xffffffffU
 146
 147 static struct svm_direct_access_msrs {
 148         u32 index;   /* Index of the MSR */
 149         bool always; /* True if intercept is always on */
 150 } direct_access_msrs[] = {
 151         { .index = MSR_STAR,                            .always = true  },
 152         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 153 #ifdef CONFIG_X86_64
 154         { .index = MSR_GS_BASE,                         .always = true  },
 155         { .index = MSR_FS_BASE,                         .always = true  },
 156         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 157         { .index = MSR_LSTAR,                           .always = true  },
 158         { .index = MSR_CSTAR,                           .always = true  },
 159         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 160 #endif
 161         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 162         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 163         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 164         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 165         { .index = MSR_INVALID,                         .always = false },
 166 };
 167
 168 /* enable NPT for AMD64 and X86 with PAE */
 169 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 170 static bool npt_enabled = true;
 171 #else
 172 static bool npt_enabled;
 173 #endif
 174 static int npt = 1;
 175
 176 module_param(npt, int, S_IRUGO);
 177
 178 static int nested = 1;
 179 module_param(nested, int, S_IRUGO);
 180
 181 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 182 static void svm_complete_interrupts(struct vcpu_svm *svm);
 183
 184 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 185 static int nested_svm_intercept(struct vcpu_svm *svm);
 186 static int nested_svm_vmexit(struct vcpu_svm *svm);
 187 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 188                                       bool has_error_code, u32 error_code);
 189
 190 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 191 {
 192         return container_of(vcpu, struct vcpu_svm, vcpu);
 193 }
 194
 195 static inline bool is_nested(struct vcpu_svm *svm)
 196 {
 197         return svm->nested.vmcb;
 198 }
 199
 200 static inline void enable_gif(struct vcpu_svm *svm)
 201 {
 202         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 203 }
 204
 205 static inline void disable_gif(struct vcpu_svm *svm)
 206 {
 207         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 208 }
 209
 210 static inline bool gif_set(struct vcpu_svm *svm)
 211 {
 212         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 213 }
 214
 215 static unsigned long iopm_base;
 216
 217 struct kvm_ldttss_desc {
 218         u16 limit0;
 219         u16 base0;
 220         unsigned base1:8, type:5, dpl:2, p:1;
 221         unsigned limit1:4, zero0:3, g:1, base2:8;
 222         u32 base3;
 223         u32 zero1;
 224 } __attribute__((packed));
 225
 226 struct svm_cpu_data {
 227         int cpu;
 228
 229         u64 asid_generation;
 230         u32 max_asid;
 231         u32 next_asid;
 232         struct kvm_ldttss_desc *tss_desc;
 233
 234         struct page *save_area;
 235 };
 236
 237 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 238 static uint32_t svm_features;
 239
 240 struct svm_init_data {
 241         int cpu;
 242         int r;
 243 };
 244
 245 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 246
 247 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 248 #define MSRS_RANGE_SIZE 2048
 249 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 250
 251 static u32 svm_msrpm_offset(u32 msr)
 252 {
 253         u32 offset;
 254         int i;
 255
 256         for (i = 0; i < NUM_MSR_MAPS; i++) {
 257                 if (msr < msrpm_ranges[i] ||
 258                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 259                         continue;
 260
 261                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 262                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 263
 264                 /* Now we have the u8 offset - but need the u32 offset */
 265                 return offset / 4;
 266         }
 267
 268         /* MSR not in any range */
 269         return MSR_INVALID;
 270 }
 271
 272 #define MAX_INST_SIZE 15
 273
 274 static inline void clgi(void)
 275 {
 276         asm volatile (__ex(SVM_CLGI));
 277 }
 278
 279 static inline void stgi(void)
 280 {
 281         asm volatile (__ex(SVM_STGI));
 282 }
 283
 284 static inline void invlpga(unsigned long addr, u32 asid)
 285 {
 286         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 287 }
 288
 289 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 290 {
 291         to_svm(vcpu)->asid_generation--;
 292 }
 293
 294 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 295 {
 296         force_new_asid(vcpu);
 297 }
 298
 299 static int get_npt_level(void)
 300 {
 301 #ifdef CONFIG_X86_64
 302         return PT64_ROOT_LEVEL;
 303 #else
 304         return PT32E_ROOT_LEVEL;
 305 #endif
 306 }
 307
 308 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 309 {
 310         vcpu->arch.efer = efer;
 311         if (!npt_enabled && !(efer & EFER_LMA))
 312                 efer &= ~EFER_LME;
 313
 314         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 315 }
 316
 317 static int is_external_interrupt(u32 info)
 318 {
 319         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 320         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 321 }
 322
 323 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 324 {
 325         struct vcpu_svm *svm = to_svm(vcpu);
 326         u32 ret = 0;
 327
 328         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 329                 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 330         return ret & mask;
 331 }
 332
 333 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 334 {
 335         struct vcpu_svm *svm = to_svm(vcpu);
 336
 337         if (mask == 0)
 338                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 339         else
 340                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 341
 342 }
 343
 344 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 345 {
 346         struct vcpu_svm *svm = to_svm(vcpu);
 347
 348         if (svm->vmcb->control.next_rip != 0)
 349                 svm->next_rip = svm->vmcb->control.next_rip;
 350
 351         if (!svm->next_rip) {
 352                 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
 353                                 EMULATE_DONE)
 354                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 355                 return;
 356         }
 357         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 358                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 359                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 360
 361         kvm_rip_write(vcpu, svm->next_rip);
 362         svm_set_interrupt_shadow(vcpu, 0);
 363 }
 364
 365 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 366                                 bool has_error_code, u32 error_code,
 367                                 bool reinject)
 368 {
 369         struct vcpu_svm *svm = to_svm(vcpu);
 370
 371         /*
 372          * If we are within a nested VM we'd better #VMEXIT and let the guest
 373          * handle the exception
 374          */
 375         if (!reinject &&
 376             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 377                 return;
 378
 379         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
 380                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 381
 382                 /*
 383                  * For guest debugging where we have to reinject #BP if some
 384                  * INT3 is guest-owned:
 385                  * Emulate nRIP by moving RIP forward. Will fail if injection
 386                  * raises a fault that is not intercepted. Still better than
 387                  * failing in all cases.
 388                  */
 389                 skip_emulated_instruction(&svm->vcpu);
 390                 rip = kvm_rip_read(&svm->vcpu);
 391                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 392                 svm->int3_injected = rip - old_rip;
 393         }
 394
 395         svm->vmcb->control.event_inj = nr
 396                 | SVM_EVTINJ_VALID
 397                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 398                 | SVM_EVTINJ_TYPE_EXEPT;
 399         svm->vmcb->control.event_inj_err = error_code;
 400 }
 401
 402 static void svm_init_erratum_383(void)
 403 {
 404         u32 low, high;
 405         int err;
 406         u64 val;
 407
 408         if (!cpu_has_amd_erratum(amd_erratum_383))
 409                 return;
 410
 411         /* Use _safe variants to not break nested virtualization */
 412         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 413         if (err)
 414                 return;
 415
 416         val |= (1ULL << 47);
 417
 418         low  = lower_32_bits(val);
 419         high = upper_32_bits(val);
 420
 421         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 422
 423         erratum_383_found = true;
 424 }
 425
 426 static int has_svm(void)
 427 {
 428         const char *msg;
 429
 430         if (!cpu_has_svm(&msg)) {
 431                 printk(KERN_INFO "has_svm: %s\n", msg);
 432                 return 0;
 433         }
 434
 435         return 1;
 436 }
 437
 438 static void svm_hardware_disable(void *garbage)
 439 {
 440         cpu_svm_disable();
 441 }
 442
 443 static int svm_hardware_enable(void *garbage)
 444 {
 445
 446         struct svm_cpu_data *sd;
 447         uint64_t efer;
 448         struct desc_ptr gdt_descr;
 449         struct desc_struct *gdt;
 450         int me = raw_smp_processor_id();
 451
 452         rdmsrl(MSR_EFER, efer);
 453         if (efer & EFER_SVME)
 454                 return -EBUSY;
 455
 456         if (!has_svm()) {
 457                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 458                        me);
 459                 return -EINVAL;
 460         }
 461         sd = per_cpu(svm_data, me);
 462
 463         if (!sd) {
 464                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 465                        me);
 466                 return -EINVAL;
 467         }
 468
 469         sd->asid_generation = 1;
 470         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 471         sd->next_asid = sd->max_asid + 1;
 472
 473         native_store_gdt(&gdt_descr);
 474         gdt = (struct desc_struct *)gdt_descr.address;
 475         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 476
 477         wrmsrl(MSR_EFER, efer | EFER_SVME);
 478
 479         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 480
 481         svm_init_erratum_383();
 482
 483         return 0;
 484 }
 485
 486 static void svm_cpu_uninit(int cpu)
 487 {
 488         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 489
 490         if (!sd)
 491                 return;
 492
 493         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 494         __free_page(sd->save_area);
 495         kfree(sd);
 496 }
 497
 498 static int svm_cpu_init(int cpu)
 499 {
 500         struct svm_cpu_data *sd;
 501         int r;
 502
 503         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 504         if (!sd)
 505                 return -ENOMEM;
 506         sd->cpu = cpu;
 507         sd->save_area = alloc_page(GFP_KERNEL);
 508         r = -ENOMEM;
 509         if (!sd->save_area)
 510                 goto err_1;
 511
 512         per_cpu(svm_data, cpu) = sd;
 513
 514         return 0;
 515
 516 err_1:
 517         kfree(sd);
 518         return r;
 519
 520 }
 521
 522 static bool valid_msr_intercept(u32 index)
 523 {
 524         int i;
 525
 526         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 527                 if (direct_access_msrs[i].index == index)
 528                         return true;
 529
 530         return false;
 531 }
 532
 533 static void set_msr_interception(u32 *msrpm, unsigned msr,
 534                                  int read, int write)
 535 {
 536         u8 bit_read, bit_write;
 537         unsigned long tmp;
 538         u32 offset;
 539
 540         /*
 541          * If this warning triggers extend the direct_access_msrs list at the
 542          * beginning of the file
 543          */
 544         WARN_ON(!valid_msr_intercept(msr));
 545
 546         offset    = svm_msrpm_offset(msr);
 547         bit_read  = 2 * (msr & 0x0f);
 548         bit_write = 2 * (msr & 0x0f) + 1;
 549         tmp       = msrpm[offset];
 550
 551         BUG_ON(offset == MSR_INVALID);
 552
 553         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 554         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 555
 556         msrpm[offset] = tmp;
 557 }
 558
 559 static void svm_vcpu_init_msrpm(u32 *msrpm)
 560 {
 561         int i;
 562
 563         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 564
 565         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 566                 if (!direct_access_msrs[i].always)
 567                         continue;
 568
 569                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 570         }
 571 }
 572
 573 static void add_msr_offset(u32 offset)
 574 {
 575         int i;
 576
 577         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 578
 579                 /* Offset already in list? */
 580                 if (msrpm_offsets[i] == offset)
 581                         return;
 582
 583                 /* Slot used by another offset? */
 584                 if (msrpm_offsets[i] != MSR_INVALID)
 585                         continue;
 586
 587                 /* Add offset to list */
 588                 msrpm_offsets[i] = offset;
 589
 590                 return;
 591         }
 592
 593         /*
 594          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 595          * increase MSRPM_OFFSETS in this case.
 596          */
 597         BUG();
 598 }
 599
 600 static void init_msrpm_offsets(void)
 601 {
 602         int i;
 603
 604         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 605
 606         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 607                 u32 offset;
 608
 609                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 610                 BUG_ON(offset == MSR_INVALID);
 611
 612                 add_msr_offset(offset);
 613         }
 614 }
 615
 616 static void svm_enable_lbrv(struct vcpu_svm *svm)
 617 {
 618         u32 *msrpm = svm->msrpm;
 619
 620         svm->vmcb->control.lbr_ctl = 1;
 621         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 622         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 623         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 624         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 625 }
 626
 627 static void svm_disable_lbrv(struct vcpu_svm *svm)
 628 {
 629         u32 *msrpm = svm->msrpm;
 630
 631         svm->vmcb->control.lbr_ctl = 0;
 632         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 633         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 634         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 635         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 636 }
 637
 638 static __init int svm_hardware_setup(void)
 639 {
 640         int cpu;
 641         struct page *iopm_pages;
 642         void *iopm_va;
 643         int r;
 644
 645         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 646
 647         if (!iopm_pages)
 648                 return -ENOMEM;
 649
 650         iopm_va = page_address(iopm_pages);
 651         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 652         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 653
 654         init_msrpm_offsets();
 655
 656         if (boot_cpu_has(X86_FEATURE_NX))
 657                 kvm_enable_efer_bits(EFER_NX);
 658
 659         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 660                 kvm_enable_efer_bits(EFER_FFXSR);
 661
 662         if (nested) {
 663                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 664                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 665         }
 666
 667         for_each_possible_cpu(cpu) {
 668                 r = svm_cpu_init(cpu);
 669                 if (r)
 670                         goto err;
 671         }
 672
 673         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 674
 675         if (!boot_cpu_has(X86_FEATURE_NPT))
 676                 npt_enabled = false;
 677
 678         if (npt_enabled && !npt) {
 679                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 680                 npt_enabled = false;
 681         }
 682
 683         if (npt_enabled) {
 684                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 685                 kvm_enable_tdp();
 686         } else
 687                 kvm_disable_tdp();
 688
 689         return 0;
 690
 691 err:
 692         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 693         iopm_base = 0;
 694         return r;
 695 }
 696
 697 static __exit void svm_hardware_unsetup(void)
 698 {
 699         int cpu;
 700
 701         for_each_possible_cpu(cpu)
 702                 svm_cpu_uninit(cpu);
 703
 704         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 705         iopm_base = 0;
 706 }
 707
 708 static void init_seg(struct vmcb_seg *seg)
 709 {
 710         seg->selector = 0;
 711         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 712                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 713         seg->limit = 0xffff;
 714         seg->base = 0;
 715 }
 716
 717 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 718 {
 719         seg->selector = 0;
 720         seg->attrib = SVM_SELECTOR_P_MASK | type;
 721         seg->limit = 0xffff;
 722         seg->base = 0;
 723 }
 724
 725 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
 726 {
 727         struct vcpu_svm *svm = to_svm(vcpu);
 728         u64 g_tsc_offset = 0;
 729
 730         if (is_nested(svm)) {
 731                 g_tsc_offset = svm->vmcb->control.tsc_offset -
 732                                svm->nested.hsave->control.tsc_offset;
 733                 svm->nested.hsave->control.tsc_offset = offset;
 734         }
 735
 736         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
 737 }
 738
 739 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
 740 {
 741         struct vcpu_svm *svm = to_svm(vcpu);
 742
 743         svm->vmcb->control.tsc_offset += adjustment;
 744         if (is_nested(svm))
 745                 svm->nested.hsave->control.tsc_offset += adjustment;
 746 }
 747
 748 static void init_vmcb(struct vcpu_svm *svm)
 749 {
 750         struct vmcb_control_area *control = &svm->vmcb->control;
 751         struct vmcb_save_area *save = &svm->vmcb->save;
 752
 753         svm->vcpu.fpu_active = 1;
 754
 755         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 756                                         INTERCEPT_CR3_MASK |
 757                                         INTERCEPT_CR4_MASK;
 758
 759         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 760                                         INTERCEPT_CR3_MASK |
 761                                         INTERCEPT_CR4_MASK |
 762                                         INTERCEPT_CR8_MASK;
 763
 764         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 765                                         INTERCEPT_DR1_MASK |
 766                                         INTERCEPT_DR2_MASK |
 767                                         INTERCEPT_DR3_MASK |
 768                                         INTERCEPT_DR4_MASK |
 769                                         INTERCEPT_DR5_MASK |
 770                                         INTERCEPT_DR6_MASK |
 771                                         INTERCEPT_DR7_MASK;
 772
 773         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 774                                         INTERCEPT_DR1_MASK |
 775                                         INTERCEPT_DR2_MASK |
 776                                         INTERCEPT_DR3_MASK |
 777                                         INTERCEPT_DR4_MASK |
 778                                         INTERCEPT_DR5_MASK |
 779                                         INTERCEPT_DR6_MASK |
 780                                         INTERCEPT_DR7_MASK;
 781
 782         control->intercept_exceptions = (1 << PF_VECTOR) |
 783                                         (1 << UD_VECTOR) |
 784                                         (1 << MC_VECTOR);
 785
 786
 787         control->intercept =    (1ULL << INTERCEPT_INTR) |
 788                                 (1ULL << INTERCEPT_NMI) |
 789                                 (1ULL << INTERCEPT_SMI) |
 790                                 (1ULL << INTERCEPT_SELECTIVE_CR0) |
 791                                 (1ULL << INTERCEPT_CPUID) |
 792                                 (1ULL << INTERCEPT_INVD) |
 793                                 (1ULL << INTERCEPT_HLT) |
 794                                 (1ULL << INTERCEPT_INVLPG) |
 795                                 (1ULL << INTERCEPT_INVLPGA) |
 796                                 (1ULL << INTERCEPT_IOIO_PROT) |
 797                                 (1ULL << INTERCEPT_MSR_PROT) |
 798                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 799                                 (1ULL << INTERCEPT_SHUTDOWN) |
 800                                 (1ULL << INTERCEPT_VMRUN) |
 801                                 (1ULL << INTERCEPT_VMMCALL) |
 802                                 (1ULL << INTERCEPT_VMLOAD) |
 803                                 (1ULL << INTERCEPT_VMSAVE) |
 804                                 (1ULL << INTERCEPT_STGI) |
 805                                 (1ULL << INTERCEPT_CLGI) |
 806                                 (1ULL << INTERCEPT_SKINIT) |
 807                                 (1ULL << INTERCEPT_WBINVD) |
 808                                 (1ULL << INTERCEPT_MONITOR) |
 809                                 (1ULL << INTERCEPT_MWAIT);
 810
 811         control->iopm_base_pa = iopm_base;
 812         control->msrpm_base_pa = __pa(svm->msrpm);
 813         control->int_ctl = V_INTR_MASKING_MASK;
 814
 815         init_seg(&save->es);
 816         init_seg(&save->ss);
 817         init_seg(&save->ds);
 818         init_seg(&save->fs);
 819         init_seg(&save->gs);
 820
 821         save->cs.selector = 0xf000;
 822         /* Executable/Readable Code Segment */
 823         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 824                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 825         save->cs.limit = 0xffff;
 826         /*
 827          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 828          * be consistent with it.
 829          *
 830          * Replace when we have real mode working for vmx.
 831          */
 832         save->cs.base = 0xf0000;
 833
 834         save->gdtr.limit = 0xffff;
 835         save->idtr.limit = 0xffff;
 836
 837         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 838         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 839
 840         svm_set_efer(&svm->vcpu, 0);
 841         save->dr6 = 0xffff0ff0;
 842         save->dr7 = 0x400;
 843         save->rflags = 2;
 844         save->rip = 0x0000fff0;
 845         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 846
 847         /*
 848          * This is the guest-visible cr0 value.
 849          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
 850          */
 851         svm->vcpu.arch.cr0 = 0;
 852         (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
 853
 854         save->cr4 = X86_CR4_PAE;
 855         /* rdx = ?? */
 856
 857         if (npt_enabled) {
 858                 /* Setup VMCB for Nested Paging */
 859                 control->nested_ctl = 1;
 860                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 861                                         (1ULL << INTERCEPT_INVLPG));
 862                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 863                 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
 864                 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
 865                 save->g_pat = 0x0007040600070406ULL;
 866                 save->cr3 = 0;
 867                 save->cr4 = 0;
 868         }
 869         force_new_asid(&svm->vcpu);
 870
 871         svm->nested.vmcb = 0;
 872         svm->vcpu.arch.hflags = 0;
 873
 874         if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
 875                 control->pause_filter_count = 3000;
 876                 control->intercept |= (1ULL << INTERCEPT_PAUSE);
 877         }
 878
 879         enable_gif(svm);
 880 }
 881
 882 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 883 {
 884         struct vcpu_svm *svm = to_svm(vcpu);
 885
 886         init_vmcb(svm);
 887
 888         if (!kvm_vcpu_is_bsp(vcpu)) {
 889                 kvm_rip_write(vcpu, 0);
 890                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 891                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 892         }
 893         vcpu->arch.regs_avail = ~0;
 894         vcpu->arch.regs_dirty = ~0;
 895
 896         return 0;
 897 }
 898
 899 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 900 {
 901         struct vcpu_svm *svm;
 902         struct page *page;
 903         struct page *msrpm_pages;
 904         struct page *hsave_page;
 905         struct page *nested_msrpm_pages;
 906         int err;
 907
 908         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 909         if (!svm) {
 910                 err = -ENOMEM;
 911                 goto out;
 912         }
 913
 914         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 915         if (err)
 916                 goto free_svm;
 917
 918         err = -ENOMEM;
 919         page = alloc_page(GFP_KERNEL);
 920         if (!page)
 921                 goto uninit;
 922
 923         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 924         if (!msrpm_pages)
 925                 goto free_page1;
 926
 927         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 928         if (!nested_msrpm_pages)
 929                 goto free_page2;
 930
 931         hsave_page = alloc_page(GFP_KERNEL);
 932         if (!hsave_page)
 933                 goto free_page3;
 934
 935         svm->nested.hsave = page_address(hsave_page);
 936
 937         svm->msrpm = page_address(msrpm_pages);
 938         svm_vcpu_init_msrpm(svm->msrpm);
 939
 940         svm->nested.msrpm = page_address(nested_msrpm_pages);
 941         svm_vcpu_init_msrpm(svm->nested.msrpm);
 942
 943         svm->vmcb = page_address(page);
 944         clear_page(svm->vmcb);
 945         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 946         svm->asid_generation = 0;
 947         init_vmcb(svm);
 948         kvm_write_tsc(&svm->vcpu, 0);
 949
 950         err = fx_init(&svm->vcpu);
 951         if (err)
 952                 goto free_page4;
 953
 954         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 955         if (kvm_vcpu_is_bsp(&svm->vcpu))
 956                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 957
 958         return &svm->vcpu;
 959
 960 free_page4:
 961         __free_page(hsave_page);
 962 free_page3:
 963         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
 964 free_page2:
 965         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
 966 free_page1:
 967         __free_page(page);
 968 uninit:
 969         kvm_vcpu_uninit(&svm->vcpu);
 970 free_svm:
 971         kmem_cache_free(kvm_vcpu_cache, svm);
 972 out:
 973         return ERR_PTR(err);
 974 }
 975
 976 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 977 {
 978         struct vcpu_svm *svm = to_svm(vcpu);
 979
 980         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 981         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 982         __free_page(virt_to_page(svm->nested.hsave));
 983         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
 984         kvm_vcpu_uninit(vcpu);
 985         kmem_cache_free(kvm_vcpu_cache, svm);
 986 }
 987
 988 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 989 {
 990         struct vcpu_svm *svm = to_svm(vcpu);
 991         int i;
 992
 993         if (unlikely(cpu != vcpu->cpu)) {
 994                 svm->asid_generation = 0;
 995         }
 996
 997 #ifdef CONFIG_X86_64
 998         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
 999 #endif
1000         savesegment(fs, svm->host.fs);
1001         savesegment(gs, svm->host.gs);
1002         svm->host.ldt = kvm_read_ldt();
1003
1004         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1005                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1006 }
1007
1008 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1009 {
1010         struct vcpu_svm *svm = to_svm(vcpu);
1011         int i;
1012
1013         ++vcpu->stat.host_state_reload;
1014         kvm_load_ldt(svm->host.ldt);
1015 #ifdef CONFIG_X86_64
1016         loadsegment(fs, svm->host.fs);
1017         load_gs_index(svm->host.gs);
1018         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1019 #else
1020         loadsegment(gs, svm->host.gs);
1021 #endif
1022         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1023                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1024 }
1025
1026 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1027 {
1028         return to_svm(vcpu)->vmcb->save.rflags;
1029 }
1030
1031 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1032 {
1033         to_svm(vcpu)->vmcb->save.rflags = rflags;
1034 }
1035
1036 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1037 {
1038         switch (reg) {
1039         case VCPU_EXREG_PDPTR:
1040                 BUG_ON(!npt_enabled);
1041                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
1042                 break;
1043         default:
1044                 BUG();
1045         }
1046 }
1047
1048 static void svm_set_vintr(struct vcpu_svm *svm)
1049 {
1050         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
1051 }
1052
1053 static void svm_clear_vintr(struct vcpu_svm *svm)
1054 {
1055         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1056 }
1057
1058 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1059 {
1060         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1061
1062         switch (seg) {
1063         case VCPU_SREG_CS: return &save->cs;
1064         case VCPU_SREG_DS: return &save->ds;
1065         case VCPU_SREG_ES: return &save->es;
1066         case VCPU_SREG_FS: return &save->fs;
1067         case VCPU_SREG_GS: return &save->gs;
1068         case VCPU_SREG_SS: return &save->ss;
1069         case VCPU_SREG_TR: return &save->tr;
1070         case VCPU_SREG_LDTR: return &save->ldtr;
1071         }
1072         BUG();
1073         return NULL;
1074 }
1075
1076 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1077 {
1078         struct vmcb_seg *s = svm_seg(vcpu, seg);
1079
1080         return s->base;
1081 }
1082
1083 static void svm_get_segment(struct kvm_vcpu *vcpu,
1084                             struct kvm_segment *var, int seg)
1085 {
1086         struct vmcb_seg *s = svm_seg(vcpu, seg);
1087
1088         var->base = s->base;
1089         var->limit = s->limit;
1090         var->selector = s->selector;
1091         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1092         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1093         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1094         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1095         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1096         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1097         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1098         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1099
1100         /*
1101          * AMD's VMCB does not have an explicit unusable field, so emulate it
1102          * for cross vendor migration purposes by "not present"
1103          */
1104         var->unusable = !var->present || (var->type == 0);
1105
1106         switch (seg) {
1107         case VCPU_SREG_CS:
1108                 /*
1109                  * SVM always stores 0 for the 'G' bit in the CS selector in
1110                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1111                  * Intel's VMENTRY has a check on the 'G' bit.
1112                  */
1113                 var->g = s->limit > 0xfffff;
1114                 break;
1115         case VCPU_SREG_TR:
1116                 /*
1117                  * Work around a bug where the busy flag in the tr selector
1118                  * isn't exposed
1119                  */
1120                 var->type |= 0x2;
1121                 break;
1122         case VCPU_SREG_DS:
1123         case VCPU_SREG_ES:
1124         case VCPU_SREG_FS:
1125         case VCPU_SREG_GS:
1126                 /*
1127                  * The accessed bit must always be set in the segment
1128                  * descriptor cache, although it can be cleared in the
1129                  * descriptor, the cached bit always remains at 1. Since
1130                  * Intel has a check on this, set it here to support
1131                  * cross-vendor migration.
1132                  */
1133                 if (!var->unusable)
1134                         var->type |= 0x1;
1135                 break;
1136         case VCPU_SREG_SS:
1137                 /*
1138                  * On AMD CPUs sometimes the DB bit in the segment
1139                  * descriptor is left as 1, although the whole segment has
1140                  * been made unusable. Clear it here to pass an Intel VMX
1141                  * entry check when cross vendor migrating.
1142                  */
1143                 if (var->unusable)
1144                         var->db = 0;
1145                 break;
1146         }
1147 }
1148
1149 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1150 {
1151         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1152
1153         return save->cpl;
1154 }
1155
1156 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1157 {
1158         struct vcpu_svm *svm = to_svm(vcpu);
1159
1160         dt->size = svm->vmcb->save.idtr.limit;
1161         dt->address = svm->vmcb->save.idtr.base;
1162 }
1163
1164 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1165 {
1166         struct vcpu_svm *svm = to_svm(vcpu);
1167
1168         svm->vmcb->save.idtr.limit = dt->size;
1169         svm->vmcb->save.idtr.base = dt->address ;
1170 }
1171
1172 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1173 {
1174         struct vcpu_svm *svm = to_svm(vcpu);
1175
1176         dt->size = svm->vmcb->save.gdtr.limit;
1177         dt->address = svm->vmcb->save.gdtr.base;
1178 }
1179
1180 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1181 {
1182         struct vcpu_svm *svm = to_svm(vcpu);
1183
1184         svm->vmcb->save.gdtr.limit = dt->size;
1185         svm->vmcb->save.gdtr.base = dt->address ;
1186 }
1187
1188 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1189 {
1190 }
1191
1192 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1193 {
1194 }
1195
1196 static void update_cr0_intercept(struct vcpu_svm *svm)
1197 {
1198         struct vmcb *vmcb = svm->vmcb;
1199         ulong gcr0 = svm->vcpu.arch.cr0;
1200         u64 *hcr0 = &svm->vmcb->save.cr0;
1201
1202         if (!svm->vcpu.fpu_active)
1203                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1204         else
1205                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1206                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1207
1208
1209         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1210                 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1211                 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1212                 if (is_nested(svm)) {
1213                         struct vmcb *hsave = svm->nested.hsave;
1214
1215                         hsave->control.intercept_cr_read  &= ~INTERCEPT_CR0_MASK;
1216                         hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1217                         vmcb->control.intercept_cr_read  |= svm->nested.intercept_cr_read;
1218                         vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1219                 }
1220         } else {
1221                 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1222                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1223                 if (is_nested(svm)) {
1224                         struct vmcb *hsave = svm->nested.hsave;
1225
1226                         hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1227                         hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1228                 }
1229         }
1230 }
1231
1232 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1233 {
1234         struct vcpu_svm *svm = to_svm(vcpu);
1235
1236         if (is_nested(svm)) {
1237                 /*
1238                  * We are here because we run in nested mode, the host kvm
1239                  * intercepts cr0 writes but the l1 hypervisor does not.
1240                  * But the L1 hypervisor may intercept selective cr0 writes.
1241                  * This needs to be checked here.
1242                  */
1243                 unsigned long old, new;
1244
1245                 /* Remove bits that would trigger a real cr0 write intercept */
1246                 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1247                 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1248
1249                 if (old == new) {
1250                         /* cr0 write with ts and mp unchanged */
1251                         svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1252                         if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1253                                 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1254                                 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1255                                 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
1256                                 return;
1257                         }
1258                 }
1259         }
1260
1261 #ifdef CONFIG_X86_64
1262         if (vcpu->arch.efer & EFER_LME) {
1263                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1264                         vcpu->arch.efer |= EFER_LMA;
1265                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1266                 }
1267
1268                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1269                         vcpu->arch.efer &= ~EFER_LMA;
1270                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1271                 }
1272         }
1273 #endif
1274         vcpu->arch.cr0 = cr0;
1275
1276         if (!npt_enabled)
1277                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1278
1279         if (!vcpu->fpu_active)
1280                 cr0 |= X86_CR0_TS;
1281         /*
1282          * re-enable caching here because the QEMU bios
1283          * does not do it - this results in some delay at
1284          * reboot
1285          */
1286         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1287         svm->vmcb->save.cr0 = cr0;
1288         update_cr0_intercept(svm);
1289 }
1290
1291 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1292 {
1293         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1294         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1295
1296         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1297                 force_new_asid(vcpu);
1298
1299         vcpu->arch.cr4 = cr4;
1300         if (!npt_enabled)
1301                 cr4 |= X86_CR4_PAE;
1302         cr4 |= host_cr4_mce;
1303         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1304 }
1305
1306 static void svm_set_segment(struct kvm_vcpu *vcpu,
1307                             struct kvm_segment *var, int seg)
1308 {
1309         struct vcpu_svm *svm = to_svm(vcpu);
1310         struct vmcb_seg *s = svm_seg(vcpu, seg);
1311
1312         s->base = var->base;
1313         s->limit = var->limit;
1314         s->selector = var->selector;
1315         if (var->unusable)
1316                 s->attrib = 0;
1317         else {
1318                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1319                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1320                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1321                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1322                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1323                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1324                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1325                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1326         }
1327         if (seg == VCPU_SREG_CS)
1328                 svm->vmcb->save.cpl
1329                         = (svm->vmcb->save.cs.attrib
1330                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1331
1332 }
1333
1334 static void update_db_intercept(struct kvm_vcpu *vcpu)
1335 {
1336         struct vcpu_svm *svm = to_svm(vcpu);
1337
1338         svm->vmcb->control.intercept_exceptions &=
1339                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1340
1341         if (svm->nmi_singlestep)
1342                 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1343
1344         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1345                 if (vcpu->guest_debug &
1346                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1347                         svm->vmcb->control.intercept_exceptions |=
1348                                 1 << DB_VECTOR;
1349                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1350                         svm->vmcb->control.intercept_exceptions |=
1351                                 1 << BP_VECTOR;
1352         } else
1353                 vcpu->guest_debug = 0;
1354 }
1355
1356 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1357 {
1358         struct vcpu_svm *svm = to_svm(vcpu);
1359
1360         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1361                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1362         else
1363                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1364
1365         update_db_intercept(vcpu);
1366 }
1367
1368 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1369 {
1370         if (sd->next_asid > sd->max_asid) {
1371                 ++sd->asid_generation;
1372                 sd->next_asid = 1;
1373                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1374         }
1375
1376         svm->asid_generation = sd->asid_generation;
1377         svm->vmcb->control.asid = sd->next_asid++;
1378 }
1379
1380 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1381 {
1382         struct vcpu_svm *svm = to_svm(vcpu);
1383
1384         svm->vmcb->save.dr7 = value;
1385 }
1386
1387 static int pf_interception(struct vcpu_svm *svm)
1388 {
1389         u64 fault_address = svm->vmcb->control.exit_info_2;
1390         u32 error_code;
1391         int r = 1;
1392
1393         switch (svm->apf_reason) {
1394         default:
1395                 error_code = svm->vmcb->control.exit_info_1;
1396
1397                 trace_kvm_page_fault(fault_address, error_code);
1398                 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1399                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1400                 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1401                 break;
1402         case KVM_PV_REASON_PAGE_NOT_PRESENT:
1403                 svm->apf_reason = 0;
1404                 local_irq_disable();
1405                 kvm_async_pf_task_wait(fault_address);
1406                 local_irq_enable();
1407                 break;
1408         case KVM_PV_REASON_PAGE_READY:
1409                 svm->apf_reason = 0;
1410                 local_irq_disable();
1411                 kvm_async_pf_task_wake(fault_address);
1412                 local_irq_enable();
1413                 break;
1414         }
1415         return r;
1416 }
1417
1418 static int db_interception(struct vcpu_svm *svm)
1419 {
1420         struct kvm_run *kvm_run = svm->vcpu.run;
1421
1422         if (!(svm->vcpu.guest_debug &
1423               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1424                 !svm->nmi_singlestep) {
1425                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1426                 return 1;
1427         }
1428
1429         if (svm->nmi_singlestep) {
1430                 svm->nmi_singlestep = false;
1431                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1432                         svm->vmcb->save.rflags &=
1433                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1434                 update_db_intercept(&svm->vcpu);
1435         }
1436
1437         if (svm->vcpu.guest_debug &
1438             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1439                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1440                 kvm_run->debug.arch.pc =
1441                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1442                 kvm_run->debug.arch.exception = DB_VECTOR;
1443                 return 0;
1444         }
1445
1446         return 1;
1447 }
1448
1449 static int bp_interception(struct vcpu_svm *svm)
1450 {
1451         struct kvm_run *kvm_run = svm->vcpu.run;
1452
1453         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1454         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1455         kvm_run->debug.arch.exception = BP_VECTOR;
1456         return 0;
1457 }
1458
1459 static int ud_interception(struct vcpu_svm *svm)
1460 {
1461         int er;
1462
1463         er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1464         if (er != EMULATE_DONE)
1465                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1466         return 1;
1467 }
1468
1469 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1470 {
1471         struct vcpu_svm *svm = to_svm(vcpu);
1472         u32 excp;
1473
1474         if (is_nested(svm)) {
1475                 u32 h_excp, n_excp;
1476
1477                 h_excp  = svm->nested.hsave->control.intercept_exceptions;
1478                 n_excp  = svm->nested.intercept_exceptions;
1479                 h_excp &= ~(1 << NM_VECTOR);
1480                 excp    = h_excp | n_excp;
1481         } else {
1482                 excp  = svm->vmcb->control.intercept_exceptions;
1483                 excp &= ~(1 << NM_VECTOR);
1484         }
1485
1486         svm->vmcb->control.intercept_exceptions = excp;
1487
1488         svm->vcpu.fpu_active = 1;
1489         update_cr0_intercept(svm);
1490 }
1491
1492 static int nm_interception(struct vcpu_svm *svm)
1493 {
1494         svm_fpu_activate(&svm->vcpu);
1495         return 1;
1496 }
1497
1498 static bool is_erratum_383(void)
1499 {
1500         int err, i;
1501         u64 value;
1502
1503         if (!erratum_383_found)
1504                 return false;
1505
1506         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1507         if (err)
1508                 return false;
1509
1510         /* Bit 62 may or may not be set for this mce */
1511         value &= ~(1ULL << 62);
1512
1513         if (value != 0xb600000000010015ULL)
1514                 return false;
1515
1516         /* Clear MCi_STATUS registers */
1517         for (i = 0; i < 6; ++i)
1518                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1519
1520         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1521         if (!err) {
1522                 u32 low, high;
1523
1524                 value &= ~(1ULL << 2);
1525                 low    = lower_32_bits(value);
1526                 high   = upper_32_bits(value);
1527
1528                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1529         }
1530
1531         /* Flush tlb to evict multi-match entries */
1532         __flush_tlb_all();
1533
1534         return true;
1535 }
1536
1537 static void svm_handle_mce(struct vcpu_svm *svm)
1538 {
1539         if (is_erratum_383()) {
1540                 /*
1541                  * Erratum 383 triggered. Guest state is corrupt so kill the
1542                  * guest.
1543                  */
1544                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1545
1546                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1547
1548                 return;
1549         }
1550
1551         /*
1552          * On an #MC intercept the MCE handler is not called automatically in
1553          * the host. So do it by hand here.
1554          */
1555         asm volatile (
1556                 "int $0x12\n");
1557         /* not sure if we ever come back to this point */
1558
1559         return;
1560 }
1561
1562 static int mc_interception(struct vcpu_svm *svm)
1563 {
1564         return 1;
1565 }
1566
1567 static int shutdown_interception(struct vcpu_svm *svm)
1568 {
1569         struct kvm_run *kvm_run = svm->vcpu.run;
1570
1571         /*
1572          * VMCB is undefined after a SHUTDOWN intercept
1573          * so reinitialize it.
1574          */
1575         clear_page(svm->vmcb);
1576         init_vmcb(svm);
1577
1578         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1579         return 0;
1580 }
1581
1582 static int io_interception(struct vcpu_svm *svm)
1583 {
1584         struct kvm_vcpu *vcpu = &svm->vcpu;
1585         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1586         int size, in, string;
1587         unsigned port;
1588
1589         ++svm->vcpu.stat.io_exits;
1590         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1591         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1592         if (string || in)
1593                 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
1594
1595         port = io_info >> 16;
1596         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1597         svm->next_rip = svm->vmcb->control.exit_info_2;
1598         skip_emulated_instruction(&svm->vcpu);
1599
1600         return kvm_fast_pio_out(vcpu, size, port);
1601 }
1602
1603 static int nmi_interception(struct vcpu_svm *svm)
1604 {
1605         return 1;
1606 }
1607
1608 static int intr_interception(struct vcpu_svm *svm)
1609 {
1610         ++svm->vcpu.stat.irq_exits;
1611         return 1;
1612 }
1613
1614 static int nop_on_interception(struct vcpu_svm *svm)
1615 {
1616         return 1;
1617 }
1618
1619 static int halt_interception(struct vcpu_svm *svm)
1620 {
1621         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1622         skip_emulated_instruction(&svm->vcpu);
1623         return kvm_emulate_halt(&svm->vcpu);
1624 }
1625
1626 static int vmmcall_interception(struct vcpu_svm *svm)
1627 {
1628         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1629         skip_emulated_instruction(&svm->vcpu);
1630         kvm_emulate_hypercall(&svm->vcpu);
1631         return 1;
1632 }
1633
1634 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1635 {
1636         struct vcpu_svm *svm = to_svm(vcpu);
1637
1638         return svm->nested.nested_cr3;
1639 }
1640
1641 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1642                                    unsigned long root)
1643 {
1644         struct vcpu_svm *svm = to_svm(vcpu);
1645
1646         svm->vmcb->control.nested_cr3 = root;
1647         force_new_asid(vcpu);
1648 }
1649
1650 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu)
1651 {
1652         struct vcpu_svm *svm = to_svm(vcpu);
1653
1654         svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1655         svm->vmcb->control.exit_code_hi = 0;
1656         svm->vmcb->control.exit_info_1 = vcpu->arch.fault.error_code;
1657         svm->vmcb->control.exit_info_2 = vcpu->arch.fault.address;
1658
1659         nested_svm_vmexit(svm);
1660 }
1661
1662 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1663 {
1664         int r;
1665
1666         r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1667
1668         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
1669         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
1670         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1671         vcpu->arch.mmu.shadow_root_level = get_npt_level();
1672         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
1673
1674         return r;
1675 }
1676
1677 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1678 {
1679         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1680 }
1681
1682 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1683 {
1684         if (!(svm->vcpu.arch.efer & EFER_SVME)
1685             || !is_paging(&svm->vcpu)) {
1686                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1687                 return 1;
1688         }
1689
1690         if (svm->vmcb->save.cpl) {
1691                 kvm_inject_gp(&svm->vcpu, 0);
1692                 return 1;
1693         }
1694
1695        return 0;
1696 }
1697
1698 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1699                                       bool has_error_code, u32 error_code)
1700 {
1701         int vmexit;
1702
1703         if (!is_nested(svm))
1704                 return 0;
1705
1706         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1707         svm->vmcb->control.exit_code_hi = 0;
1708         svm->vmcb->control.exit_info_1 = error_code;
1709         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1710
1711         vmexit = nested_svm_intercept(svm);
1712         if (vmexit == NESTED_EXIT_DONE)
1713                 svm->nested.exit_required = true;
1714
1715         return vmexit;
1716 }
1717
1718 /* This function returns true if it is save to enable the irq window */
1719 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1720 {
1721         if (!is_nested(svm))
1722                 return true;
1723
1724         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1725                 return true;
1726
1727         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1728                 return false;
1729
1730         /*
1731          * if vmexit was already requested (by intercepted exception
1732          * for instance) do not overwrite it with "external interrupt"
1733          * vmexit.
1734          */
1735         if (svm->nested.exit_required)
1736                 return false;
1737
1738         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
1739         svm->vmcb->control.exit_info_1 = 0;
1740         svm->vmcb->control.exit_info_2 = 0;
1741
1742         if (svm->nested.intercept & 1ULL) {
1743                 /*
1744                  * The #vmexit can't be emulated here directly because this
1745                  * code path runs with irqs and preemtion disabled. A
1746                  * #vmexit emulation might sleep. Only signal request for
1747                  * the #vmexit here.
1748                  */
1749                 svm->nested.exit_required = true;
1750                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1751                 return false;
1752         }
1753
1754         return true;
1755 }
1756
1757 /* This function returns true if it is save to enable the nmi window */
1758 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1759 {
1760         if (!is_nested(svm))
1761                 return true;
1762
1763         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1764                 return true;
1765
1766         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1767         svm->nested.exit_required = true;
1768
1769         return false;
1770 }
1771
1772 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1773 {
1774         struct page *page;
1775
1776         might_sleep();
1777
1778         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1779         if (is_error_page(page))
1780                 goto error;
1781
1782         *_page = page;
1783
1784         return kmap(page);
1785
1786 error:
1787         kvm_release_page_clean(page);
1788         kvm_inject_gp(&svm->vcpu, 0);
1789
1790         return NULL;
1791 }
1792
1793 static void nested_svm_unmap(struct page *page)
1794 {
1795         kunmap(page);
1796         kvm_release_page_dirty(page);
1797 }
1798
1799 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1800 {
1801         unsigned port;
1802         u8 val, bit;
1803         u64 gpa;
1804
1805         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1806                 return NESTED_EXIT_HOST;
1807
1808         port = svm->vmcb->control.exit_info_1 >> 16;
1809         gpa  = svm->nested.vmcb_iopm + (port / 8);
1810         bit  = port % 8;
1811         val  = 0;
1812
1813         if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1814                 val &= (1 << bit);
1815
1816         return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1817 }
1818
1819 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1820 {
1821         u32 offset, msr, value;
1822         int write, mask;
1823
1824         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1825                 return NESTED_EXIT_HOST;
1826
1827         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1828         offset = svm_msrpm_offset(msr);
1829         write  = svm->vmcb->control.exit_info_1 & 1;
1830         mask   = 1 << ((2 * (msr & 0xf)) + write);
1831
1832         if (offset == MSR_INVALID)
1833                 return NESTED_EXIT_DONE;
1834
1835         /* Offset is in 32 bit units but need in 8 bit units */
1836         offset *= 4;
1837
1838         if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1839                 return NESTED_EXIT_DONE;
1840
1841         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1842 }
1843
1844 static int nested_svm_exit_special(struct vcpu_svm *svm)
1845 {
1846         u32 exit_code = svm->vmcb->control.exit_code;
1847
1848         switch (exit_code) {
1849         case SVM_EXIT_INTR:
1850         case SVM_EXIT_NMI:
1851         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1852                 return NESTED_EXIT_HOST;
1853         case SVM_EXIT_NPF:
1854                 /* For now we are always handling NPFs when using them */
1855                 if (npt_enabled)
1856                         return NESTED_EXIT_HOST;
1857                 break;
1858         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1859                 /* When we're shadowing, trap PFs, but not async PF */
1860                 if (!npt_enabled && svm->apf_reason == 0)
1861                         return NESTED_EXIT_HOST;
1862                 break;
1863         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1864                 nm_interception(svm);
1865                 break;
1866         default:
1867                 break;
1868         }
1869
1870         return NESTED_EXIT_CONTINUE;
1871 }
1872
1873 /*
1874  * If this function returns true, this #vmexit was already handled
1875  */
1876 static int nested_svm_intercept(struct vcpu_svm *svm)
1877 {
1878         u32 exit_code = svm->vmcb->control.exit_code;
1879         int vmexit = NESTED_EXIT_HOST;
1880
1881         switch (exit_code) {
1882         case SVM_EXIT_MSR:
1883                 vmexit = nested_svm_exit_handled_msr(svm);
1884                 break;
1885         case SVM_EXIT_IOIO:
1886                 vmexit = nested_svm_intercept_ioio(svm);
1887                 break;
1888         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1889                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1890                 if (svm->nested.intercept_cr_read & cr_bits)
1891                         vmexit = NESTED_EXIT_DONE;
1892                 break;
1893         }
1894         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1895                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1896                 if (svm->nested.intercept_cr_write & cr_bits)
1897                         vmexit = NESTED_EXIT_DONE;
1898                 break;
1899         }
1900         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1901                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1902                 if (svm->nested.intercept_dr_read & dr_bits)
1903                         vmexit = NESTED_EXIT_DONE;
1904                 break;
1905         }
1906         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1907                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1908                 if (svm->nested.intercept_dr_write & dr_bits)
1909                         vmexit = NESTED_EXIT_DONE;
1910                 break;
1911         }
1912         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1913                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1914                 if (svm->nested.intercept_exceptions & excp_bits)
1915                         vmexit = NESTED_EXIT_DONE;
1916                 /* async page fault always cause vmexit */
1917                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
1918                          svm->apf_reason != 0)
1919                         vmexit = NESTED_EXIT_DONE;
1920                 break;
1921         }
1922         case SVM_EXIT_ERR: {
1923                 vmexit = NESTED_EXIT_DONE;
1924                 break;
1925         }
1926         default: {
1927                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1928                 if (svm->nested.intercept & exit_bits)
1929                         vmexit = NESTED_EXIT_DONE;
1930         }
1931         }
1932
1933         return vmexit;
1934 }
1935
1936 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1937 {
1938         int vmexit;
1939
1940         vmexit = nested_svm_intercept(svm);
1941
1942         if (vmexit == NESTED_EXIT_DONE)
1943                 nested_svm_vmexit(svm);
1944
1945         return vmexit;
1946 }
1947
1948 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1949 {
1950         struct vmcb_control_area *dst  = &dst_vmcb->control;
1951         struct vmcb_control_area *from = &from_vmcb->control;
1952
1953         dst->intercept_cr_read    = from->intercept_cr_read;
1954         dst->intercept_cr_write   = from->intercept_cr_write;
1955         dst->intercept_dr_read    = from->intercept_dr_read;
1956         dst->intercept_dr_write   = from->intercept_dr_write;
1957         dst->intercept_exceptions = from->intercept_exceptions;
1958         dst->intercept            = from->intercept;
1959         dst->iopm_base_pa         = from->iopm_base_pa;
1960         dst->msrpm_base_pa        = from->msrpm_base_pa;
1961         dst->tsc_offset           = from->tsc_offset;
1962         dst->asid                 = from->asid;
1963         dst->tlb_ctl              = from->tlb_ctl;
1964         dst->int_ctl              = from->int_ctl;
1965         dst->int_vector           = from->int_vector;
1966         dst->int_state            = from->int_state;
1967         dst->exit_code            = from->exit_code;
1968         dst->exit_code_hi         = from->exit_code_hi;
1969         dst->exit_info_1          = from->exit_info_1;
1970         dst->exit_info_2          = from->exit_info_2;
1971         dst->exit_int_info        = from->exit_int_info;
1972         dst->exit_int_info_err    = from->exit_int_info_err;
1973         dst->nested_ctl           = from->nested_ctl;
1974         dst->event_inj            = from->event_inj;
1975         dst->event_inj_err        = from->event_inj_err;
1976         dst->nested_cr3           = from->nested_cr3;
1977         dst->lbr_ctl              = from->lbr_ctl;
1978 }
1979
1980 static int nested_svm_vmexit(struct vcpu_svm *svm)
1981 {
1982         struct vmcb *nested_vmcb;
1983         struct vmcb *hsave = svm->nested.hsave;
1984         struct vmcb *vmcb = svm->vmcb;
1985         struct page *page;
1986
1987         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1988                                        vmcb->control.exit_info_1,
1989                                        vmcb->control.exit_info_2,
1990                                        vmcb->control.exit_int_info,
1991                                        vmcb->control.exit_int_info_err);
1992
1993         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
1994         if (!nested_vmcb)
1995                 return 1;
1996
1997         /* Exit nested SVM mode */
1998         svm->nested.vmcb = 0;
1999
2000         /* Give the current vmcb to the guest */
2001         disable_gif(svm);
2002
2003         nested_vmcb->save.es     = vmcb->save.es;
2004         nested_vmcb->save.cs     = vmcb->save.cs;
2005         nested_vmcb->save.ss     = vmcb->save.ss;
2006         nested_vmcb->save.ds     = vmcb->save.ds;
2007         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
2008         nested_vmcb->save.idtr   = vmcb->save.idtr;
2009         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
2010         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
2011         nested_vmcb->save.cr3    = svm->vcpu.arch.cr3;
2012         nested_vmcb->save.cr2    = vmcb->save.cr2;
2013         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
2014         nested_vmcb->save.rflags = vmcb->save.rflags;
2015         nested_vmcb->save.rip    = vmcb->save.rip;
2016         nested_vmcb->save.rsp    = vmcb->save.rsp;
2017         nested_vmcb->save.rax    = vmcb->save.rax;
2018         nested_vmcb->save.dr7    = vmcb->save.dr7;
2019         nested_vmcb->save.dr6    = vmcb->save.dr6;
2020         nested_vmcb->save.cpl    = vmcb->save.cpl;
2021
2022         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
2023         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
2024         nested_vmcb->control.int_state         = vmcb->control.int_state;
2025         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
2026         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
2027         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
2028         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
2029         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
2030         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2031         nested_vmcb->control.next_rip          = vmcb->control.next_rip;
2032
2033         /*
2034          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2035          * to make sure that we do not lose injected events. So check event_inj
2036          * here and copy it to exit_int_info if it is valid.
2037          * Exit_int_info and event_inj can't be both valid because the case
2038          * below only happens on a VMRUN instruction intercept which has
2039          * no valid exit_int_info set.
2040          */
2041         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2042                 struct vmcb_control_area *nc = &nested_vmcb->control;
2043
2044                 nc->exit_int_info     = vmcb->control.event_inj;
2045                 nc->exit_int_info_err = vmcb->control.event_inj_err;
2046         }
2047
2048         nested_vmcb->control.tlb_ctl           = 0;
2049         nested_vmcb->control.event_inj         = 0;
2050         nested_vmcb->control.event_inj_err     = 0;
2051
2052         /* We always set V_INTR_MASKING and remember the old value in hflags */
2053         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2054                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2055
2056         /* Restore the original control entries */
2057         copy_vmcb_control_area(vmcb, hsave);
2058
2059         kvm_clear_exception_queue(&svm->vcpu);
2060         kvm_clear_interrupt_queue(&svm->vcpu);
2061
2062         svm->nested.nested_cr3 = 0;
2063
2064         /* Restore selected save entries */
2065         svm->vmcb->save.es = hsave->save.es;
2066         svm->vmcb->save.cs = hsave->save.cs;
2067         svm->vmcb->save.ss = hsave->save.ss;
2068         svm->vmcb->save.ds = hsave->save.ds;
2069         svm->vmcb->save.gdtr = hsave->save.gdtr;
2070         svm->vmcb->save.idtr = hsave->save.idtr;
2071         svm->vmcb->save.rflags = hsave->save.rflags;
2072         svm_set_efer(&svm->vcpu, hsave->save.efer);
2073         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2074         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2075         if (npt_enabled) {
2076                 svm->vmcb->save.cr3 = hsave->save.cr3;
2077                 svm->vcpu.arch.cr3 = hsave->save.cr3;
2078         } else {
2079                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2080         }
2081         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2082         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2083         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2084         svm->vmcb->save.dr7 = 0;
2085         svm->vmcb->save.cpl = 0;
2086         svm->vmcb->control.exit_int_info = 0;
2087
2088         nested_svm_unmap(page);
2089
2090         nested_svm_uninit_mmu_context(&svm->vcpu);
2091         kvm_mmu_reset_context(&svm->vcpu);
2092         kvm_mmu_load(&svm->vcpu);
2093
2094         return 0;
2095 }
2096
2097 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2098 {
2099         /*
2100          * This function merges the msr permission bitmaps of kvm and the
2101          * nested vmcb. It is omptimized in that it only merges the parts where
2102          * the kvm msr permission bitmap may contain zero bits
2103          */
2104         int i;
2105
2106         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2107                 return true;
2108
2109         for (i = 0; i < MSRPM_OFFSETS; i++) {
2110                 u32 value, p;
2111                 u64 offset;
2112
2113                 if (msrpm_offsets[i] == 0xffffffff)
2114                         break;
2115
2116                 p      = msrpm_offsets[i];
2117                 offset = svm->nested.vmcb_msrpm + (p * 4);
2118
2119                 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2120                         return false;
2121
2122                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2123         }
2124
2125         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2126
2127         return true;
2128 }
2129
2130 static bool nested_vmcb_checks(struct vmcb *vmcb)
2131 {
2132         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2133                 return false;
2134
2135         if (vmcb->control.asid == 0)
2136                 return false;
2137
2138         if (vmcb->control.nested_ctl && !npt_enabled)
2139                 return false;
2140
2141         return true;
2142 }
2143
2144 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2145 {
2146         struct vmcb *nested_vmcb;
2147         struct vmcb *hsave = svm->nested.hsave;
2148         struct vmcb *vmcb = svm->vmcb;
2149         struct page *page;
2150         u64 vmcb_gpa;
2151
2152         vmcb_gpa = svm->vmcb->save.rax;
2153
2154         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2155         if (!nested_vmcb)
2156                 return false;
2157
2158         if (!nested_vmcb_checks(nested_vmcb)) {
2159                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
2160                 nested_vmcb->control.exit_code_hi = 0;
2161                 nested_vmcb->control.exit_info_1  = 0;
2162                 nested_vmcb->control.exit_info_2  = 0;
2163
2164                 nested_svm_unmap(page);
2165
2166                 return false;
2167         }
2168
2169         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2170                                nested_vmcb->save.rip,
2171                                nested_vmcb->control.int_ctl,
2172                                nested_vmcb->control.event_inj,
2173                                nested_vmcb->control.nested_ctl);
2174
2175         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
2176                                     nested_vmcb->control.intercept_cr_write,
2177                                     nested_vmcb->control.intercept_exceptions,
2178                                     nested_vmcb->control.intercept);
2179
2180         /* Clear internal status */
2181         kvm_clear_exception_queue(&svm->vcpu);
2182         kvm_clear_interrupt_queue(&svm->vcpu);
2183
2184         /*
2185          * Save the old vmcb, so we don't need to pick what we save, but can
2186          * restore everything when a VMEXIT occurs
2187          */
2188         hsave->save.es     = vmcb->save.es;
2189         hsave->save.cs     = vmcb->save.cs;
2190         hsave->save.ss     = vmcb->save.ss;
2191         hsave->save.ds     = vmcb->save.ds;
2192         hsave->save.gdtr   = vmcb->save.gdtr;
2193         hsave->save.idtr   = vmcb->save.idtr;
2194         hsave->save.efer   = svm->vcpu.arch.efer;
2195         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2196         hsave->save.cr4    = svm->vcpu.arch.cr4;
2197         hsave->save.rflags = vmcb->save.rflags;
2198         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
2199         hsave->save.rsp    = vmcb->save.rsp;
2200         hsave->save.rax    = vmcb->save.rax;
2201         if (npt_enabled)
2202                 hsave->save.cr3    = vmcb->save.cr3;
2203         else
2204                 hsave->save.cr3    = svm->vcpu.arch.cr3;
2205
2206         copy_vmcb_control_area(hsave, vmcb);
2207
2208         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2209                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2210         else
2211                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2212
2213         if (nested_vmcb->control.nested_ctl) {
2214                 kvm_mmu_unload(&svm->vcpu);
2215                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2216                 nested_svm_init_mmu_context(&svm->vcpu);
2217         }
2218
2219         /* Load the nested guest state */
2220         svm->vmcb->save.es = nested_vmcb->save.es;
2221         svm->vmcb->save.cs = nested_vmcb->save.cs;
2222         svm->vmcb->save.ss = nested_vmcb->save.ss;
2223         svm->vmcb->save.ds = nested_vmcb->save.ds;
2224         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2225         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2226         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2227         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2228         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2229         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2230         if (npt_enabled) {
2231                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2232                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2233         } else
2234                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2235
2236         /* Guest paging mode is active - reset mmu */
2237         kvm_mmu_reset_context(&svm->vcpu);
2238
2239         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2240         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2241         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2242         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2243
2244         /* In case we don't even reach vcpu_run, the fields are not updated */
2245         svm->vmcb->save.rax = nested_vmcb->save.rax;
2246         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2247         svm->vmcb->save.rip = nested_vmcb->save.rip;
2248         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2249         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2250         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2251
2252         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2253         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2254
2255         /* cache intercepts */
2256         svm->nested.intercept_cr_read    = nested_vmcb->control.intercept_cr_read;
2257         svm->nested.intercept_cr_write   = nested_vmcb->control.intercept_cr_write;
2258         svm->nested.intercept_dr_read    = nested_vmcb->control.intercept_dr_read;
2259         svm->nested.intercept_dr_write   = nested_vmcb->control.intercept_dr_write;
2260         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2261         svm->nested.intercept            = nested_vmcb->control.intercept;
2262
2263         force_new_asid(&svm->vcpu);
2264         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2265         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2266                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2267         else
2268                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2269
2270         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2271                 /* We only want the cr8 intercept bits of the guest */
2272                 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2273                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2274         }
2275
2276         /* We don't want to see VMMCALLs from a nested guest */
2277         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2278
2279         /*
2280          * We don't want a nested guest to be more powerful than the guest, so
2281          * all intercepts are ORed
2282          */
2283         svm->vmcb->control.intercept_cr_read |=
2284                 nested_vmcb->control.intercept_cr_read;
2285         svm->vmcb->control.intercept_cr_write |=
2286                 nested_vmcb->control.intercept_cr_write;
2287         svm->vmcb->control.intercept_dr_read |=
2288                 nested_vmcb->control.intercept_dr_read;
2289         svm->vmcb->control.intercept_dr_write |=
2290                 nested_vmcb->control.intercept_dr_write;
2291         svm->vmcb->control.intercept_exceptions |=
2292                 nested_vmcb->control.intercept_exceptions;
2293
2294         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2295
2296         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2297         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2298         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2299         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2300         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2301         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2302
2303         nested_svm_unmap(page);
2304
2305         /* nested_vmcb is our indicator if nested SVM is activated */
2306         svm->nested.vmcb = vmcb_gpa;
2307
2308         enable_gif(svm);
2309
2310         return true;
2311 }
2312
2313 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2314 {
2315         to_vmcb->save.fs = from_vmcb->save.fs;
2316         to_vmcb->save.gs = from_vmcb->save.gs;
2317         to_vmcb->save.tr = from_vmcb->save.tr;
2318         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2319         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2320         to_vmcb->save.star = from_vmcb->save.star;
2321         to_vmcb->save.lstar = from_vmcb->save.lstar;
2322         to_vmcb->save.cstar = from_vmcb->save.cstar;
2323         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2324         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2325         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2326         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2327 }
2328
2329 static int vmload_interception(struct vcpu_svm *svm)
2330 {
2331         struct vmcb *nested_vmcb;
2332         struct page *page;
2333
2334         if (nested_svm_check_permissions(svm))
2335                 return 1;
2336
2337         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2338         skip_emulated_instruction(&svm->vcpu);
2339
2340         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2341         if (!nested_vmcb)
2342                 return 1;
2343
2344         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2345         nested_svm_unmap(page);
2346
2347         return 1;
2348 }
2349
2350 static int vmsave_interception(struct vcpu_svm *svm)
2351 {
2352         struct vmcb *nested_vmcb;
2353         struct page *page;
2354
2355         if (nested_svm_check_permissions(svm))
2356                 return 1;
2357
2358         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2359         skip_emulated_instruction(&svm->vcpu);
2360
2361         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2362         if (!nested_vmcb)
2363                 return 1;
2364
2365         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2366         nested_svm_unmap(page);
2367
2368         return 1;
2369 }
2370
2371 static int vmrun_interception(struct vcpu_svm *svm)
2372 {
2373         if (nested_svm_check_permissions(svm))
2374                 return 1;
2375
2376         /* Save rip after vmrun instruction */
2377         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2378
2379         if (!nested_svm_vmrun(svm))
2380                 return 1;
2381
2382         if (!nested_svm_vmrun_msrpm(svm))
2383                 goto failed;
2384
2385         return 1;
2386
2387 failed:
2388
2389         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
2390         svm->vmcb->control.exit_code_hi = 0;
2391         svm->vmcb->control.exit_info_1  = 0;
2392         svm->vmcb->control.exit_info_2  = 0;
2393
2394         nested_svm_vmexit(svm);
2395
2396         return 1;
2397 }
2398
2399 static int stgi_interception(struct vcpu_svm *svm)
2400 {
2401         if (nested_svm_check_permissions(svm))
2402                 return 1;
2403
2404         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2405         skip_emulated_instruction(&svm->vcpu);
2406         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2407
2408         enable_gif(svm);
2409
2410         return 1;
2411 }
2412
2413 static int clgi_interception(struct vcpu_svm *svm)
2414 {
2415         if (nested_svm_check_permissions(svm))
2416                 return 1;
2417
2418         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2419         skip_emulated_instruction(&svm->vcpu);
2420
2421         disable_gif(svm);
2422
2423         /* After a CLGI no interrupts should come */
2424         svm_clear_vintr(svm);
2425         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2426
2427         return 1;
2428 }
2429
2430 static int invlpga_interception(struct vcpu_svm *svm)
2431 {
2432         struct kvm_vcpu *vcpu = &svm->vcpu;
2433
2434         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2435                           vcpu->arch.regs[VCPU_REGS_RAX]);
2436
2437         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2438         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2439
2440         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2441         skip_emulated_instruction(&svm->vcpu);
2442         return 1;
2443 }
2444
2445 static int skinit_interception(struct vcpu_svm *svm)
2446 {
2447         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2448
2449         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2450         return 1;
2451 }
2452
2453 static int invalid_op_interception(struct vcpu_svm *svm)
2454 {
2455         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2456         return 1;
2457 }
2458
2459 static int task_switch_interception(struct vcpu_svm *svm)
2460 {
2461         u16 tss_selector;
2462         int reason;
2463         int int_type = svm->vmcb->control.exit_int_info &
2464                 SVM_EXITINTINFO_TYPE_MASK;
2465         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2466         uint32_t type =
2467                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2468         uint32_t idt_v =
2469                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2470         bool has_error_code = false;
2471         u32 error_code = 0;
2472
2473         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2474
2475         if (svm->vmcb->control.exit_info_2 &
2476             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2477                 reason = TASK_SWITCH_IRET;
2478         else if (svm->vmcb->control.exit_info_2 &
2479                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2480                 reason = TASK_SWITCH_JMP;
2481         else if (idt_v)
2482                 reason = TASK_SWITCH_GATE;
2483         else
2484                 reason = TASK_SWITCH_CALL;
2485
2486         if (reason == TASK_SWITCH_GATE) {
2487                 switch (type) {
2488                 case SVM_EXITINTINFO_TYPE_NMI:
2489                         svm->vcpu.arch.nmi_injected = false;
2490                         break;
2491                 case SVM_EXITINTINFO_TYPE_EXEPT:
2492                         if (svm->vmcb->control.exit_info_2 &
2493                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2494                                 has_error_code = true;
2495                                 error_code =
2496                                         (u32)svm->vmcb->control.exit_info_2;
2497                         }
2498                         kvm_clear_exception_queue(&svm->vcpu);
2499                         break;
2500                 case SVM_EXITINTINFO_TYPE_INTR:
2501                         kvm_clear_interrupt_queue(&svm->vcpu);
2502                         break;
2503                 default:
2504                         break;
2505                 }
2506         }
2507
2508         if (reason != TASK_SWITCH_GATE ||
2509             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2510             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2511              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2512                 skip_emulated_instruction(&svm->vcpu);
2513
2514         if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2515                                 has_error_code, error_code) == EMULATE_FAIL) {
2516                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2517                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2518                 svm->vcpu.run->internal.ndata = 0;
2519                 return 0;
2520         }
2521         return 1;
2522 }
2523
2524 static int cpuid_interception(struct vcpu_svm *svm)
2525 {
2526         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2527         kvm_emulate_cpuid(&svm->vcpu);
2528         return 1;
2529 }
2530
2531 static int iret_interception(struct vcpu_svm *svm)
2532 {
2533         ++svm->vcpu.stat.nmi_window_exits;
2534         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
2535         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2536         return 1;
2537 }
2538
2539 static int invlpg_interception(struct vcpu_svm *svm)
2540 {
2541         return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2542 }
2543
2544 static int emulate_on_interception(struct vcpu_svm *svm)
2545 {
2546         return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2547 }
2548
2549 static int cr0_write_interception(struct vcpu_svm *svm)
2550 {
2551         struct kvm_vcpu *vcpu = &svm->vcpu;
2552         int r;
2553
2554         r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2555
2556         if (svm->nested.vmexit_rip) {
2557                 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2558                 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2559                 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2560                 svm->nested.vmexit_rip = 0;
2561         }
2562
2563         return r == EMULATE_DONE;
2564 }
2565
2566 static int cr8_write_interception(struct vcpu_svm *svm)
2567 {
2568         struct kvm_run *kvm_run = svm->vcpu.run;
2569
2570         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2571         /* instruction emulation calls kvm_set_cr8() */
2572         emulate_instruction(&svm->vcpu, 0, 0, 0);
2573         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2574                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2575                 return 1;
2576         }
2577         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2578                 return 1;
2579         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2580         return 0;
2581 }
2582
2583 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2584 {
2585         struct vcpu_svm *svm = to_svm(vcpu);
2586
2587         switch (ecx) {
2588         case MSR_IA32_TSC: {
2589                 u64 tsc_offset;
2590
2591                 if (is_nested(svm))
2592                         tsc_offset = svm->nested.hsave->control.tsc_offset;
2593                 else
2594                         tsc_offset = svm->vmcb->control.tsc_offset;
2595
2596                 *data = tsc_offset + native_read_tsc();
2597                 break;
2598         }
2599         case MSR_STAR:
2600                 *data = svm->vmcb->save.star;
2601                 break;
2602 #ifdef CONFIG_X86_64
2603         case MSR_LSTAR:
2604                 *data = svm->vmcb->save.lstar;
2605                 break;
2606         case MSR_CSTAR:
2607                 *data = svm->vmcb->save.cstar;
2608                 break;
2609         case MSR_KERNEL_GS_BASE:
2610                 *data = svm->vmcb->save.kernel_gs_base;
2611                 break;
2612         case MSR_SYSCALL_MASK:
2613                 *data = svm->vmcb->save.sfmask;
2614                 break;
2615 #endif
2616         case MSR_IA32_SYSENTER_CS:
2617                 *data = svm->vmcb->save.sysenter_cs;
2618                 break;
2619         case MSR_IA32_SYSENTER_EIP:
2620                 *data = svm->sysenter_eip;
2621                 break;
2622         case MSR_IA32_SYSENTER_ESP:
2623                 *data = svm->sysenter_esp;
2624                 break;
2625         /*
2626          * Nobody will change the following 5 values in the VMCB so we can
2627          * safely return them on rdmsr. They will always be 0 until LBRV is
2628          * implemented.
2629          */
2630         case MSR_IA32_DEBUGCTLMSR:
2631                 *data = svm->vmcb->save.dbgctl;
2632                 break;
2633         case MSR_IA32_LASTBRANCHFROMIP:
2634                 *data = svm->vmcb->save.br_from;
2635                 break;
2636         case MSR_IA32_LASTBRANCHTOIP:
2637                 *data = svm->vmcb->save.br_to;
2638                 break;
2639         case MSR_IA32_LASTINTFROMIP:
2640                 *data = svm->vmcb->save.last_excp_from;
2641                 break;
2642         case MSR_IA32_LASTINTTOIP:
2643                 *data = svm->vmcb->save.last_excp_to;
2644                 break;
2645         case MSR_VM_HSAVE_PA:
2646                 *data = svm->nested.hsave_msr;
2647                 break;
2648         case MSR_VM_CR:
2649                 *data = svm->nested.vm_cr_msr;
2650                 break;
2651         case MSR_IA32_UCODE_REV:
2652                 *data = 0x01000065;
2653                 break;
2654         default:
2655                 return kvm_get_msr_common(vcpu, ecx, data);
2656         }
2657         return 0;
2658 }
2659
2660 static int rdmsr_interception(struct vcpu_svm *svm)
2661 {
2662         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2663         u64 data;
2664
2665         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2666                 trace_kvm_msr_read_ex(ecx);
2667                 kvm_inject_gp(&svm->vcpu, 0);
2668         } else {
2669                 trace_kvm_msr_read(ecx, data);
2670
2671                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2672                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2673                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2674                 skip_emulated_instruction(&svm->vcpu);
2675         }
2676         return 1;
2677 }
2678
2679 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2680 {
2681         struct vcpu_svm *svm = to_svm(vcpu);
2682         int svm_dis, chg_mask;
2683
2684         if (data & ~SVM_VM_CR_VALID_MASK)
2685                 return 1;
2686
2687         chg_mask = SVM_VM_CR_VALID_MASK;
2688
2689         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2690                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2691
2692         svm->nested.vm_cr_msr &= ~chg_mask;
2693         svm->nested.vm_cr_msr |= (data & chg_mask);
2694
2695         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2696
2697         /* check for svm_disable while efer.svme is set */
2698         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2699                 return 1;
2700
2701         return 0;
2702 }
2703
2704 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2705 {
2706         struct vcpu_svm *svm = to_svm(vcpu);
2707
2708         switch (ecx) {
2709         case MSR_IA32_TSC:
2710                 kvm_write_tsc(vcpu, data);
2711                 break;
2712         case MSR_STAR:
2713                 svm->vmcb->save.star = data;
2714                 break;
2715 #ifdef CONFIG_X86_64
2716         case MSR_LSTAR:
2717                 svm->vmcb->save.lstar = data;
2718                 break;
2719         case MSR_CSTAR:
2720                 svm->vmcb->save.cstar = data;
2721                 break;
2722         case MSR_KERNEL_GS_BASE:
2723                 svm->vmcb->save.kernel_gs_base = data;
2724                 break;
2725         case MSR_SYSCALL_MASK:
2726                 svm->vmcb->save.sfmask = data;
2727                 break;
2728 #endif
2729         case MSR_IA32_SYSENTER_CS:
2730                 svm->vmcb->save.sysenter_cs = data;
2731                 break;
2732         case MSR_IA32_SYSENTER_EIP:
2733                 svm->sysenter_eip = data;
2734                 svm->vmcb->save.sysenter_eip = data;
2735                 break;
2736         case MSR_IA32_SYSENTER_ESP:
2737                 svm->sysenter_esp = data;
2738                 svm->vmcb->save.sysenter_esp = data;
2739                 break;
2740         case MSR_IA32_DEBUGCTLMSR:
2741                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2742                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2743                                         __func__, data);
2744                         break;
2745                 }
2746                 if (data & DEBUGCTL_RESERVED_BITS)
2747                         return 1;
2748
2749                 svm->vmcb->save.dbgctl = data;
2750                 if (data & (1ULL<<0))
2751                         svm_enable_lbrv(svm);
2752                 else
2753                         svm_disable_lbrv(svm);
2754                 break;
2755         case MSR_VM_HSAVE_PA:
2756                 svm->nested.hsave_msr = data;
2757                 break;
2758         case MSR_VM_CR:
2759                 return svm_set_vm_cr(vcpu, data);
2760         case MSR_VM_IGNNE:
2761                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2762                 break;
2763         default:
2764                 return kvm_set_msr_common(vcpu, ecx, data);
2765         }
2766         return 0;
2767 }
2768
2769 static int wrmsr_interception(struct vcpu_svm *svm)
2770 {
2771         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2772         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2773                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2774
2775
2776         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2777         if (svm_set_msr(&svm->vcpu, ecx, data)) {
2778                 trace_kvm_msr_write_ex(ecx, data);
2779                 kvm_inject_gp(&svm->vcpu, 0);
2780         } else {
2781                 trace_kvm_msr_write(ecx, data);
2782                 skip_emulated_instruction(&svm->vcpu);
2783         }
2784         return 1;
2785 }
2786
2787 static int msr_interception(struct vcpu_svm *svm)
2788 {
2789         if (svm->vmcb->control.exit_info_1)
2790                 return wrmsr_interception(svm);
2791         else
2792                 return rdmsr_interception(svm);
2793 }
2794
2795 static int interrupt_window_interception(struct vcpu_svm *svm)
2796 {
2797         struct kvm_run *kvm_run = svm->vcpu.run;
2798
2799         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2800         svm_clear_vintr(svm);
2801         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2802         /*
2803          * If the user space waits to inject interrupts, exit as soon as
2804          * possible
2805          */
2806         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2807             kvm_run->request_interrupt_window &&
2808             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2809                 ++svm->vcpu.stat.irq_window_exits;
2810                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2811                 return 0;
2812         }
2813
2814         return 1;
2815 }
2816
2817 static int pause_interception(struct vcpu_svm *svm)
2818 {
2819         kvm_vcpu_on_spin(&(svm->vcpu));
2820         return 1;
2821 }
2822
2823 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2824         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2825         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2826         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2827         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2828         [SVM_EXIT_CR0_SEL_WRITE]                = emulate_on_interception,
2829         [SVM_EXIT_WRITE_CR0]                    = cr0_write_interception,
2830         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2831         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2832         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2833         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2834         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2835         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2836         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2837         [SVM_EXIT_READ_DR4]                     = emulate_on_interception,
2838         [SVM_EXIT_READ_DR5]                     = emulate_on_interception,
2839         [SVM_EXIT_READ_DR6]                     = emulate_on_interception,
2840         [SVM_EXIT_READ_DR7]                     = emulate_on_interception,
2841         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2842         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2843         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2844         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2845         [SVM_EXIT_WRITE_DR4]                    = emulate_on_interception,
2846         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2847         [SVM_EXIT_WRITE_DR6]                    = emulate_on_interception,
2848         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2849         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2850         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2851         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2852         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2853         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2854         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2855         [SVM_EXIT_INTR]                         = intr_interception,
2856         [SVM_EXIT_NMI]                          = nmi_interception,
2857         [SVM_EXIT_SMI]                          = nop_on_interception,
2858         [SVM_EXIT_INIT]                         = nop_on_interception,
2859         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2860         [SVM_EXIT_CPUID]                        = cpuid_interception,
2861         [SVM_EXIT_IRET]                         = iret_interception,
2862         [SVM_EXIT_INVD]                         = emulate_on_interception,
2863         [SVM_EXIT_PAUSE]                        = pause_interception,
2864         [SVM_EXIT_HLT]                          = halt_interception,
2865         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2866         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2867         [SVM_EXIT_IOIO]                         = io_interception,
2868         [SVM_EXIT_MSR]                          = msr_interception,
2869         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2870         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2871         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2872         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2873         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2874         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2875         [SVM_EXIT_STGI]                         = stgi_interception,
2876         [SVM_EXIT_CLGI]                         = clgi_interception,
2877         [SVM_EXIT_SKINIT]                       = skinit_interception,
2878         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2879         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2880         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2881         [SVM_EXIT_NPF]                          = pf_interception,
2882 };
2883
2884 void dump_vmcb(struct kvm_vcpu *vcpu)
2885 {
2886         struct vcpu_svm *svm = to_svm(vcpu);
2887         struct vmcb_control_area *control = &svm->vmcb->control;
2888         struct vmcb_save_area *save = &svm->vmcb->save;
2889
2890         pr_err("VMCB Control Area:\n");
2891         pr_err("cr_read:            %04x\n", control->intercept_cr_read);
2892         pr_err("cr_write:           %04x\n", control->intercept_cr_write);
2893         pr_err("dr_read:            %04x\n", control->intercept_dr_read);
2894         pr_err("dr_write:           %04x\n", control->intercept_dr_write);
2895         pr_err("exceptions:         %08x\n", control->intercept_exceptions);
2896         pr_err("intercepts:         %016llx\n", control->intercept);
2897         pr_err("pause filter count: %d\n", control->pause_filter_count);
2898         pr_err("iopm_base_pa:       %016llx\n", control->iopm_base_pa);
2899         pr_err("msrpm_base_pa:      %016llx\n", control->msrpm_base_pa);
2900         pr_err("tsc_offset:         %016llx\n", control->tsc_offset);
2901         pr_err("asid:               %d\n", control->asid);
2902         pr_err("tlb_ctl:            %d\n", control->tlb_ctl);
2903         pr_err("int_ctl:            %08x\n", control->int_ctl);
2904         pr_err("int_vector:         %08x\n", control->int_vector);
2905         pr_err("int_state:          %08x\n", control->int_state);
2906         pr_err("exit_code:          %08x\n", control->exit_code);
2907         pr_err("exit_info1:         %016llx\n", control->exit_info_1);
2908         pr_err("exit_info2:         %016llx\n", control->exit_info_2);
2909         pr_err("exit_int_info:      %08x\n", control->exit_int_info);
2910         pr_err("exit_int_info_err:  %08x\n", control->exit_int_info_err);
2911         pr_err("nested_ctl:         %lld\n", control->nested_ctl);
2912         pr_err("nested_cr3:         %016llx\n", control->nested_cr3);
2913         pr_err("event_inj:          %08x\n", control->event_inj);
2914         pr_err("event_inj_err:      %08x\n", control->event_inj_err);
2915         pr_err("lbr_ctl:            %lld\n", control->lbr_ctl);
2916         pr_err("next_rip:           %016llx\n", control->next_rip);
2917         pr_err("VMCB State Save Area:\n");
2918         pr_err("es:   s: %04x a: %04x l: %08x b: %016llx\n",
2919                 save->es.selector, save->es.attrib,
2920                 save->es.limit, save->es.base);
2921         pr_err("cs:   s: %04x a: %04x l: %08x b: %016llx\n",
2922                 save->cs.selector, save->cs.attrib,
2923                 save->cs.limit, save->cs.base);
2924         pr_err("ss:   s: %04x a: %04x l: %08x b: %016llx\n",
2925                 save->ss.selector, save->ss.attrib,
2926                 save->ss.limit, save->ss.base);
2927         pr_err("ds:   s: %04x a: %04x l: %08x b: %016llx\n",
2928                 save->ds.selector, save->ds.attrib,
2929                 save->ds.limit, save->ds.base);
2930         pr_err("fs:   s: %04x a: %04x l: %08x b: %016llx\n",
2931                 save->fs.selector, save->fs.attrib,
2932                 save->fs.limit, save->fs.base);
2933         pr_err("gs:   s: %04x a: %04x l: %08x b: %016llx\n",
2934                 save->gs.selector, save->gs.attrib,
2935                 save->gs.limit, save->gs.base);
2936         pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
2937                 save->gdtr.selector, save->gdtr.attrib,
2938                 save->gdtr.limit, save->gdtr.base);
2939         pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
2940                 save->ldtr.selector, save->ldtr.attrib,
2941                 save->ldtr.limit, save->ldtr.base);
2942         pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
2943                 save->idtr.selector, save->idtr.attrib,
2944                 save->idtr.limit, save->idtr.base);
2945         pr_err("tr:   s: %04x a: %04x l: %08x b: %016llx\n",
2946                 save->tr.selector, save->tr.attrib,
2947                 save->tr.limit, save->tr.base);
2948         pr_err("cpl:            %d                efer:         %016llx\n",
2949                 save->cpl, save->efer);
2950         pr_err("cr0:            %016llx cr2:          %016llx\n",
2951                 save->cr0, save->cr2);
2952         pr_err("cr3:            %016llx cr4:          %016llx\n",
2953                 save->cr3, save->cr4);
2954         pr_err("dr6:            %016llx dr7:          %016llx\n",
2955                 save->dr6, save->dr7);
2956         pr_err("rip:            %016llx rflags:       %016llx\n",
2957                 save->rip, save->rflags);
2958         pr_err("rsp:            %016llx rax:          %016llx\n",
2959                 save->rsp, save->rax);
2960         pr_err("star:           %016llx lstar:        %016llx\n",
2961                 save->star, save->lstar);
2962         pr_err("cstar:          %016llx sfmask:       %016llx\n",
2963                 save->cstar, save->sfmask);
2964         pr_err("kernel_gs_base: %016llx sysenter_cs:  %016llx\n",
2965                 save->kernel_gs_base, save->sysenter_cs);
2966         pr_err("sysenter_esp:   %016llx sysenter_eip: %016llx\n",
2967                 save->sysenter_esp, save->sysenter_eip);
2968         pr_err("gpat:           %016llx dbgctl:       %016llx\n",
2969                 save->g_pat, save->dbgctl);
2970         pr_err("br_from:        %016llx br_to:        %016llx\n",
2971                 save->br_from, save->br_to);
2972         pr_err("excp_from:      %016llx excp_to:      %016llx\n",
2973                 save->last_excp_from, save->last_excp_to);
2974
2975 }
2976
2977 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
2978 {
2979         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
2980
2981         *info1 = control->exit_info_1;
2982         *info2 = control->exit_info_2;
2983 }
2984
2985 static int handle_exit(struct kvm_vcpu *vcpu)
2986 {
2987         struct vcpu_svm *svm = to_svm(vcpu);
2988         struct kvm_run *kvm_run = vcpu->run;
2989         u32 exit_code = svm->vmcb->control.exit_code;
2990
2991         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
2992
2993         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2994                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2995         if (npt_enabled)
2996                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2997
2998         if (unlikely(svm->nested.exit_required)) {
2999                 nested_svm_vmexit(svm);
3000                 svm->nested.exit_required = false;
3001
3002                 return 1;
3003         }
3004
3005         if (is_nested(svm)) {
3006                 int vmexit;
3007
3008                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3009                                         svm->vmcb->control.exit_info_1,
3010                                         svm->vmcb->control.exit_info_2,
3011                                         svm->vmcb->control.exit_int_info,
3012                                         svm->vmcb->control.exit_int_info_err);
3013
3014                 vmexit = nested_svm_exit_special(svm);
3015
3016                 if (vmexit == NESTED_EXIT_CONTINUE)
3017                         vmexit = nested_svm_exit_handled(svm);
3018
3019                 if (vmexit == NESTED_EXIT_DONE)
3020                         return 1;
3021         }
3022
3023         svm_complete_interrupts(svm);
3024
3025         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3026                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3027                 kvm_run->fail_entry.hardware_entry_failure_reason
3028                         = svm->vmcb->control.exit_code;
3029                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3030                 dump_vmcb(vcpu);
3031                 return 0;
3032         }
3033
3034         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3035             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3036             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3037             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3038                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3039                        "exit_code 0x%x\n",
3040                        __func__, svm->vmcb->control.exit_int_info,
3041                        exit_code);
3042
3043         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3044             || !svm_exit_handlers[exit_code]) {
3045                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3046                 kvm_run->hw.hardware_exit_reason = exit_code;
3047                 return 0;
3048         }
3049
3050         return svm_exit_handlers[exit_code](svm);
3051 }
3052
3053 static void reload_tss(struct kvm_vcpu *vcpu)
3054 {
3055         int cpu = raw_smp_processor_id();
3056
3057         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3058         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3059         load_TR_desc();
3060 }
3061
3062 static void pre_svm_run(struct vcpu_svm *svm)
3063 {
3064         int cpu = raw_smp_processor_id();
3065
3066         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3067
3068         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3069         /* FIXME: handle wraparound of asid_generation */
3070         if (svm->asid_generation != sd->asid_generation)
3071                 new_asid(svm, sd);
3072 }
3073
3074 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3075 {
3076         struct vcpu_svm *svm = to_svm(vcpu);
3077
3078         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3079         vcpu->arch.hflags |= HF_NMI_MASK;
3080         svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3081         ++vcpu->stat.nmi_injections;
3082 }
3083
3084 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3085 {
3086         struct vmcb_control_area *control;
3087
3088         control = &svm->vmcb->control;
3089         control->int_vector = irq;
3090         control->int_ctl &= ~V_INTR_PRIO_MASK;
3091         control->int_ctl |= V_IRQ_MASK |
3092                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3093 }
3094
3095 static void svm_set_irq(struct kvm_vcpu *vcpu)
3096 {
3097         struct vcpu_svm *svm = to_svm(vcpu);
3098
3099         BUG_ON(!(gif_set(svm)));
3100
3101         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3102         ++vcpu->stat.irq_injections;
3103
3104         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3105                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3106 }
3107
3108 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3109 {
3110         struct vcpu_svm *svm = to_svm(vcpu);
3111
3112         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3113                 return;
3114
3115         if (irr == -1)
3116                 return;
3117
3118         if (tpr >= irr)
3119                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
3120 }
3121
3122 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3123 {
3124         struct vcpu_svm *svm = to_svm(vcpu);
3125         struct vmcb *vmcb = svm->vmcb;
3126         int ret;
3127         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3128               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3129         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3130
3131         return ret;
3132 }
3133
3134 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3135 {
3136         struct vcpu_svm *svm = to_svm(vcpu);
3137
3138         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3139 }
3140
3141 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3142 {
3143         struct vcpu_svm *svm = to_svm(vcpu);
3144
3145         if (masked) {
3146                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3147                 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3148         } else {
3149                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3150                 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
3151         }
3152 }
3153
3154 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3155 {
3156         struct vcpu_svm *svm = to_svm(vcpu);
3157         struct vmcb *vmcb = svm->vmcb;
3158         int ret;
3159
3160         if (!gif_set(svm) ||
3161              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3162                 return 0;
3163
3164         ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3165
3166         if (is_nested(svm))
3167                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3168
3169         return ret;
3170 }
3171
3172 static void enable_irq_window(struct kvm_vcpu *vcpu)
3173 {
3174         struct vcpu_svm *svm = to_svm(vcpu);
3175
3176         /*
3177          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3178          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3179          * get that intercept, this function will be called again though and
3180          * we'll get the vintr intercept.
3181          */
3182         if (gif_set(svm) && nested_svm_intr(svm)) {
3183                 svm_set_vintr(svm);
3184                 svm_inject_irq(svm, 0x0);
3185         }
3186 }
3187
3188 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3189 {
3190         struct vcpu_svm *svm = to_svm(vcpu);
3191
3192         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3193             == HF_NMI_MASK)
3194                 return; /* IRET will cause a vm exit */
3195
3196         /*
3197          * Something prevents NMI from been injected. Single step over possible
3198          * problem (IRET or exception injection or interrupt shadow)
3199          */
3200         svm->nmi_singlestep = true;
3201         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3202         update_db_intercept(vcpu);
3203 }
3204
3205 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3206 {
3207         return 0;
3208 }
3209
3210 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3211 {
3212         force_new_asid(vcpu);
3213 }
3214
3215 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3216 {
3217 }
3218
3219 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3220 {
3221         struct vcpu_svm *svm = to_svm(vcpu);
3222
3223         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3224                 return;
3225
3226         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
3227                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3228                 kvm_set_cr8(vcpu, cr8);
3229         }
3230 }
3231
3232 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3233 {
3234         struct vcpu_svm *svm = to_svm(vcpu);
3235         u64 cr8;
3236
3237         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3238                 return;
3239
3240         cr8 = kvm_get_cr8(vcpu);
3241         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3242         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3243 }
3244
3245 static void svm_complete_interrupts(struct vcpu_svm *svm)
3246 {
3247         u8 vector;
3248         int type;
3249         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3250         unsigned int3_injected = svm->int3_injected;
3251
3252         svm->int3_injected = 0;
3253
3254         if (svm->vcpu.arch.hflags & HF_IRET_MASK) {
3255                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3256                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3257         }
3258
3259         svm->vcpu.arch.nmi_injected = false;
3260         kvm_clear_exception_queue(&svm->vcpu);
3261         kvm_clear_interrupt_queue(&svm->vcpu);
3262
3263         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3264                 return;
3265
3266         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3267
3268         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3269         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3270
3271         switch (type) {
3272         case SVM_EXITINTINFO_TYPE_NMI:
3273                 svm->vcpu.arch.nmi_injected = true;
3274                 break;
3275         case SVM_EXITINTINFO_TYPE_EXEPT:
3276                 /*
3277                  * In case of software exceptions, do not reinject the vector,
3278                  * but re-execute the instruction instead. Rewind RIP first
3279                  * if we emulated INT3 before.
3280                  */
3281                 if (kvm_exception_is_soft(vector)) {
3282                         if (vector == BP_VECTOR && int3_injected &&
3283                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3284                                 kvm_rip_write(&svm->vcpu,
3285                                               kvm_rip_read(&svm->vcpu) -
3286                                               int3_injected);
3287                         break;
3288                 }
3289                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3290                         u32 err = svm->vmcb->control.exit_int_info_err;
3291                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3292
3293                 } else
3294                         kvm_requeue_exception(&svm->vcpu, vector);
3295                 break;
3296         case SVM_EXITINTINFO_TYPE_INTR:
3297                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3298                 break;
3299         default:
3300                 break;
3301         }
3302 }
3303
3304 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3305 {
3306         struct vcpu_svm *svm = to_svm(vcpu);
3307         struct vmcb_control_area *control = &svm->vmcb->control;
3308
3309         control->exit_int_info = control->event_inj;
3310         control->exit_int_info_err = control->event_inj_err;
3311         control->event_inj = 0;
3312         svm_complete_interrupts(svm);
3313 }
3314
3315 #ifdef CONFIG_X86_64
3316 #define R "r"
3317 #else
3318 #define R "e"
3319 #endif
3320
3321 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3322 {
3323         struct vcpu_svm *svm = to_svm(vcpu);
3324
3325         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3326         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3327         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3328
3329         /*
3330          * A vmexit emulation is required before the vcpu can be executed
3331          * again.
3332          */
3333         if (unlikely(svm->nested.exit_required))
3334                 return;
3335
3336         pre_svm_run(svm);
3337
3338         sync_lapic_to_cr8(vcpu);
3339
3340         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3341
3342         clgi();
3343
3344         local_irq_enable();
3345
3346         asm volatile (
3347                 "push %%"R"bp; \n\t"
3348                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3349                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3350                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3351                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3352                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3353                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3354 #ifdef CONFIG_X86_64
3355                 "mov %c[r8](%[svm]),  %%r8  \n\t"
3356                 "mov %c[r9](%[svm]),  %%r9  \n\t"
3357                 "mov %c[r10](%[svm]), %%r10 \n\t"
3358                 "mov %c[r11](%[svm]), %%r11 \n\t"
3359                 "mov %c[r12](%[svm]), %%r12 \n\t"
3360                 "mov %c[r13](%[svm]), %%r13 \n\t"
3361                 "mov %c[r14](%[svm]), %%r14 \n\t"
3362                 "mov %c[r15](%[svm]), %%r15 \n\t"
3363 #endif
3364
3365                 /* Enter guest mode */
3366                 "push %%"R"ax \n\t"
3367                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3368                 __ex(SVM_VMLOAD) "\n\t"
3369                 __ex(SVM_VMRUN) "\n\t"
3370                 __ex(SVM_VMSAVE) "\n\t"
3371                 "pop %%"R"ax \n\t"
3372
3373                 /* Save guest registers, load host registers */
3374                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3375                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3376                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3377                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3378                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3379                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3380 #ifdef CONFIG_X86_64
3381                 "mov %%r8,  %c[r8](%[svm]) \n\t"
3382                 "mov %%r9,  %c[r9](%[svm]) \n\t"
3383                 "mov %%r10, %c[r10](%[svm]) \n\t"
3384                 "mov %%r11, %c[r11](%[svm]) \n\t"
3385                 "mov %%r12, %c[r12](%[svm]) \n\t"
3386                 "mov %%r13, %c[r13](%[svm]) \n\t"
3387                 "mov %%r14, %c[r14](%[svm]) \n\t"
3388                 "mov %%r15, %c[r15](%[svm]) \n\t"
3389 #endif
3390                 "pop %%"R"bp"
3391                 :
3392                 : [svm]"a"(svm),
3393                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3394                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3395                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3396                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3397                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3398                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3399                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3400 #ifdef CONFIG_X86_64
3401                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3402                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3403                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3404                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3405                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3406                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3407                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3408                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3409 #endif
3410                 : "cc", "memory"
3411                 , R"bx", R"cx", R"dx", R"si", R"di"
3412 #ifdef CONFIG_X86_64
3413                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3414 #endif
3415                 );
3416
3417 #ifdef CONFIG_X86_64
3418         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3419 #else
3420         loadsegment(fs, svm->host.fs);
3421 #endif
3422
3423         reload_tss(vcpu);
3424
3425         local_irq_disable();
3426
3427         stgi();
3428
3429         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3430         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3431         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3432         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3433
3434         sync_cr8_to_lapic(vcpu);
3435
3436         svm->next_rip = 0;
3437
3438         /* if exit due to PF check for async PF */
3439         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3440                 svm->apf_reason = kvm_read_and_reset_pf_reason();
3441
3442         if (npt_enabled) {
3443                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3444                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3445         }
3446
3447         /*
3448          * We need to handle MC intercepts here before the vcpu has a chance to
3449          * change the physical cpu
3450          */
3451         if (unlikely(svm->vmcb->control.exit_code ==
3452                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3453                 svm_handle_mce(svm);
3454 }
3455
3456 #undef R
3457
3458 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3459 {
3460         struct vcpu_svm *svm = to_svm(vcpu);
3461
3462         svm->vmcb->save.cr3 = root;
3463         force_new_asid(vcpu);
3464 }
3465
3466 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3467 {
3468         struct vcpu_svm *svm = to_svm(vcpu);
3469
3470         svm->vmcb->control.nested_cr3 = root;
3471
3472         /* Also sync guest cr3 here in case we live migrate */
3473         svm->vmcb->save.cr3 = vcpu->arch.cr3;
3474
3475         force_new_asid(vcpu);
3476 }
3477
3478 static int is_disabled(void)
3479 {
3480         u64 vm_cr;
3481
3482         rdmsrl(MSR_VM_CR, vm_cr);
3483         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3484                 return 1;
3485
3486         return 0;
3487 }
3488
3489 static void
3490 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3491 {
3492         /*
3493          * Patch in the VMMCALL instruction:
3494          */
3495         hypercall[0] = 0x0f;
3496         hypercall[1] = 0x01;
3497         hypercall[2] = 0xd9;
3498 }
3499
3500 static void svm_check_processor_compat(void *rtn)
3501 {
3502         *(int *)rtn = 0;
3503 }
3504
3505 static bool svm_cpu_has_accelerated_tpr(void)
3506 {
3507         return false;
3508 }
3509
3510 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3511 {
3512         return 0;
3513 }
3514
3515 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3516 {
3517 }
3518
3519 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3520 {
3521         switch (func) {
3522         case 0x00000001:
3523                 /* Mask out xsave bit as long as it is not supported by SVM */
3524                 entry->ecx &= ~(bit(X86_FEATURE_XSAVE));
3525                 break;
3526         case 0x80000001:
3527                 if (nested)
3528                         entry->ecx |= (1 << 2); /* Set SVM bit */
3529                 break;
3530         case 0x8000000A:
3531                 entry->eax = 1; /* SVM revision 1 */
3532                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3533                                    ASID emulation to nested SVM */
3534                 entry->ecx = 0; /* Reserved */
3535                 entry->edx = 0; /* Per default do not support any
3536                                    additional features */
3537
3538                 /* Support next_rip if host supports it */
3539                 if (boot_cpu_has(X86_FEATURE_NRIPS))
3540                         entry->edx |= SVM_FEATURE_NRIP;
3541
3542                 /* Support NPT for the guest if enabled */
3543                 if (npt_enabled)
3544                         entry->edx |= SVM_FEATURE_NPT;
3545
3546                 break;
3547         }
3548 }
3549
3550 static const struct trace_print_flags svm_exit_reasons_str[] = {
3551         { SVM_EXIT_READ_CR0,                    "read_cr0" },
3552         { SVM_EXIT_READ_CR3,                    "read_cr3" },
3553         { SVM_EXIT_READ_CR4,                    "read_cr4" },
3554         { SVM_EXIT_READ_CR8,                    "read_cr8" },
3555         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
3556         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
3557         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
3558         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
3559         { SVM_EXIT_READ_DR0,                    "read_dr0" },
3560         { SVM_EXIT_READ_DR1,                    "read_dr1" },
3561         { SVM_EXIT_READ_DR2,                    "read_dr2" },
3562         { SVM_EXIT_READ_DR3,                    "read_dr3" },
3563         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
3564         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
3565         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
3566         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
3567         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
3568         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
3569         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
3570         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
3571         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
3572         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
3573         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
3574         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
3575         { SVM_EXIT_INTR,                        "interrupt" },
3576         { SVM_EXIT_NMI,                         "nmi" },
3577         { SVM_EXIT_SMI,                         "smi" },
3578         { SVM_EXIT_INIT,                        "init" },
3579         { SVM_EXIT_VINTR,                       "vintr" },
3580         { SVM_EXIT_CPUID,                       "cpuid" },
3581         { SVM_EXIT_INVD,                        "invd" },
3582         { SVM_EXIT_HLT,                         "hlt" },
3583         { SVM_EXIT_INVLPG,                      "invlpg" },
3584         { SVM_EXIT_INVLPGA,                     "invlpga" },
3585         { SVM_EXIT_IOIO,                        "io" },
3586         { SVM_EXIT_MSR,                         "msr" },
3587         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
3588         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
3589         { SVM_EXIT_VMRUN,                       "vmrun" },
3590         { SVM_EXIT_VMMCALL,                     "hypercall" },
3591         { SVM_EXIT_VMLOAD,                      "vmload" },
3592         { SVM_EXIT_VMSAVE,                      "vmsave" },
3593         { SVM_EXIT_STGI,                        "stgi" },
3594         { SVM_EXIT_CLGI,                        "clgi" },
3595         { SVM_EXIT_SKINIT,                      "skinit" },
3596         { SVM_EXIT_WBINVD,                      "wbinvd" },
3597         { SVM_EXIT_MONITOR,                     "monitor" },
3598         { SVM_EXIT_MWAIT,                       "mwait" },
3599         { SVM_EXIT_NPF,                         "npf" },
3600         { -1, NULL }
3601 };
3602
3603 static int svm_get_lpage_level(void)
3604 {
3605         return PT_PDPE_LEVEL;
3606 }
3607
3608 static bool svm_rdtscp_supported(void)
3609 {
3610         return false;
3611 }
3612
3613 static bool svm_has_wbinvd_exit(void)
3614 {
3615         return true;
3616 }
3617
3618 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3619 {
3620         struct vcpu_svm *svm = to_svm(vcpu);
3621
3622         svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
3623         if (is_nested(svm))
3624                 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3625         update_cr0_intercept(svm);
3626 }
3627
3628 static struct kvm_x86_ops svm_x86_ops = {
3629         .cpu_has_kvm_support = has_svm,
3630         .disabled_by_bios = is_disabled,
3631         .hardware_setup = svm_hardware_setup,
3632         .hardware_unsetup = svm_hardware_unsetup,
3633         .check_processor_compatibility = svm_check_processor_compat,
3634         .hardware_enable = svm_hardware_enable,
3635         .hardware_disable = svm_hardware_disable,
3636         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3637
3638         .vcpu_create = svm_create_vcpu,
3639         .vcpu_free = svm_free_vcpu,
3640         .vcpu_reset = svm_vcpu_reset,
3641
3642         .prepare_guest_switch = svm_prepare_guest_switch,
3643         .vcpu_load = svm_vcpu_load,
3644         .vcpu_put = svm_vcpu_put,
3645
3646         .set_guest_debug = svm_guest_debug,
3647         .get_msr = svm_get_msr,
3648         .set_msr = svm_set_msr,
3649         .get_segment_base = svm_get_segment_base,
3650         .get_segment = svm_get_segment,
3651         .set_segment = svm_set_segment,
3652         .get_cpl = svm_get_cpl,
3653         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3654         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3655         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3656         .set_cr0 = svm_set_cr0,
3657         .set_cr3 = svm_set_cr3,
3658         .set_cr4 = svm_set_cr4,
3659         .set_efer = svm_set_efer,
3660         .get_idt = svm_get_idt,
3661         .set_idt = svm_set_idt,
3662         .get_gdt = svm_get_gdt,
3663         .set_gdt = svm_set_gdt,
3664         .set_dr7 = svm_set_dr7,
3665         .cache_reg = svm_cache_reg,
3666         .get_rflags = svm_get_rflags,
3667         .set_rflags = svm_set_rflags,
3668         .fpu_activate = svm_fpu_activate,
3669         .fpu_deactivate = svm_fpu_deactivate,
3670
3671         .tlb_flush = svm_flush_tlb,
3672
3673         .run = svm_vcpu_run,
3674         .handle_exit = handle_exit,
3675         .skip_emulated_instruction = skip_emulated_instruction,
3676         .set_interrupt_shadow = svm_set_interrupt_shadow,
3677         .get_interrupt_shadow = svm_get_interrupt_shadow,
3678         .patch_hypercall = svm_patch_hypercall,
3679         .set_irq = svm_set_irq,
3680         .set_nmi = svm_inject_nmi,
3681         .queue_exception = svm_queue_exception,
3682         .cancel_injection = svm_cancel_injection,
3683         .interrupt_allowed = svm_interrupt_allowed,
3684         .nmi_allowed = svm_nmi_allowed,
3685         .get_nmi_mask = svm_get_nmi_mask,
3686         .set_nmi_mask = svm_set_nmi_mask,
3687         .enable_nmi_window = enable_nmi_window,
3688         .enable_irq_window = enable_irq_window,
3689         .update_cr8_intercept = update_cr8_intercept,
3690
3691         .set_tss_addr = svm_set_tss_addr,
3692         .get_tdp_level = get_npt_level,
3693         .get_mt_mask = svm_get_mt_mask,
3694
3695         .get_exit_info = svm_get_exit_info,
3696         .exit_reasons_str = svm_exit_reasons_str,
3697
3698         .get_lpage_level = svm_get_lpage_level,
3699
3700         .cpuid_update = svm_cpuid_update,
3701
3702         .rdtscp_supported = svm_rdtscp_supported,
3703
3704         .set_supported_cpuid = svm_set_supported_cpuid,
3705
3706         .has_wbinvd_exit = svm_has_wbinvd_exit,
3707
3708         .write_tsc_offset = svm_write_tsc_offset,
3709         .adjust_tsc_offset = svm_adjust_tsc_offset,
3710
3711         .set_tdp_cr3 = set_tdp_cr3,
3712 };
3713
3714 static int __init svm_init(void)
3715 {
3716         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3717                         __alignof__(struct vcpu_svm), THIS_MODULE);
3718 }
3719
3720 static void __exit svm_exit(void)
3721 {
3722         kvm_exit();
3723 }
3724
3725 module_init(svm_init)
3726 module_exit(svm_exit)