2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affilates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
27 #define pt_element_t u64
28 #define guest_walker guest_walker64
29 #define FNAME(name) paging##64_##name
30 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
31 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
32 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
33 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
34 #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
35 #define PT_LEVEL_BITS PT64_LEVEL_BITS
37 #define PT_MAX_FULL_LEVELS 4
38 #define CMPXCHG cmpxchg
40 #define CMPXCHG cmpxchg64
41 #define PT_MAX_FULL_LEVELS 2
44 #define pt_element_t u32
45 #define guest_walker guest_walker32
46 #define FNAME(name) paging##32_##name
47 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
48 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
49 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
50 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
51 #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
52 #define PT_LEVEL_BITS PT32_LEVEL_BITS
53 #define PT_MAX_FULL_LEVELS 2
54 #define CMPXCHG cmpxchg
56 #error Invalid PTTYPE value
59 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
60 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
63 * The guest_walker structure emulates the behavior of the hardware page
68 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
69 pt_element_t ptes[PT_MAX_FULL_LEVELS];
70 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
71 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
78 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
80 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
83 static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
84 gfn_t table_gfn, unsigned index,
85 pt_element_t orig_pte, pt_element_t new_pte)
91 page = gfn_to_page(kvm, table_gfn);
93 table = kmap_atomic(page, KM_USER0);
94 ret = CMPXCHG(&table[index], orig_pte, new_pte);
95 kunmap_atomic(table, KM_USER0);
97 kvm_release_page_dirty(page);
99 return (ret != orig_pte);
102 static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
106 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
109 access &= ~(gpte >> PT64_NX_SHIFT);
115 * Fetch a guest pte for a guest virtual address
117 static int FNAME(walk_addr)(struct guest_walker *walker,
118 struct kvm_vcpu *vcpu, gva_t addr,
119 int write_fault, int user_fault, int fetch_fault)
123 unsigned index, pt_access, uninitialized_var(pte_access);
125 bool eperm, present, rsvd_fault;
127 trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault,
131 eperm = rsvd_fault = false;
132 walker->level = vcpu->arch.mmu.root_level;
133 pte = vcpu->arch.mmu.get_cr3(vcpu);
135 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
136 pte = kvm_pdptr_read(vcpu, (addr >> 30) & 3);
137 trace_kvm_mmu_paging_element(pte, walker->level);
138 if (!is_present_gpte(pte)) {
145 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
146 (vcpu->arch.mmu.get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0);
151 index = PT_INDEX(addr, walker->level);
153 table_gfn = gpte_to_gfn(pte);
154 pte_gpa = gfn_to_gpa(table_gfn);
155 pte_gpa += index * sizeof(pt_element_t);
156 walker->table_gfn[walker->level - 1] = table_gfn;
157 walker->pte_gpa[walker->level - 1] = pte_gpa;
159 if (kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte))) {
164 trace_kvm_mmu_paging_element(pte, walker->level);
166 if (!is_present_gpte(pte)) {
171 if (is_rsvd_bits_set(&vcpu->arch.mmu, pte, walker->level)) {
176 if (write_fault && !is_writable_pte(pte))
177 if (user_fault || is_write_protection(vcpu))
180 if (user_fault && !(pte & PT_USER_MASK))
184 if (fetch_fault && (pte & PT64_NX_MASK))
188 if (!eperm && !rsvd_fault && !(pte & PT_ACCESSED_MASK)) {
189 trace_kvm_mmu_set_accessed_bit(table_gfn, index,
191 if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
192 index, pte, pte|PT_ACCESSED_MASK))
194 mark_page_dirty(vcpu->kvm, table_gfn);
195 pte |= PT_ACCESSED_MASK;
198 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
200 walker->ptes[walker->level - 1] = pte;
202 if ((walker->level == PT_PAGE_TABLE_LEVEL) ||
203 ((walker->level == PT_DIRECTORY_LEVEL) &&
205 (PTTYPE == 64 || is_pse(vcpu))) ||
206 ((walker->level == PT_PDPE_LEVEL) &&
208 vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL)) {
209 int lvl = walker->level;
211 walker->gfn = gpte_to_gfn_lvl(pte, lvl);
212 walker->gfn += (addr & PT_LVL_OFFSET_MASK(lvl))
216 walker->level == PT_DIRECTORY_LEVEL &&
218 walker->gfn += pse36_gfn_delta(pte);
223 pt_access = pte_access;
227 if (!present || eperm || rsvd_fault)
230 if (write_fault && !is_dirty_gpte(pte)) {
233 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
234 ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
238 mark_page_dirty(vcpu->kvm, table_gfn);
239 pte |= PT_DIRTY_MASK;
240 walker->ptes[walker->level - 1] = pte;
243 walker->pt_access = pt_access;
244 walker->pte_access = pte_access;
245 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
246 __func__, (u64)pte, pte_access, pt_access);
250 walker->error_code = 0;
252 walker->error_code |= PFERR_PRESENT_MASK;
254 walker->error_code |= PFERR_WRITE_MASK;
256 walker->error_code |= PFERR_USER_MASK;
257 if (fetch_fault && is_nx(vcpu))
258 walker->error_code |= PFERR_FETCH_MASK;
260 walker->error_code |= PFERR_RSVD_MASK;
261 trace_kvm_mmu_walker_error(walker->error_code);
265 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
266 u64 *spte, const void *pte)
273 gpte = *(const pt_element_t *)pte;
274 if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
275 if (!is_present_gpte(gpte)) {
277 new_spte = shadow_trap_nonpresent_pte;
279 new_spte = shadow_notrap_nonpresent_pte;
280 __set_spte(spte, new_spte);
284 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
285 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
286 if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
288 pfn = vcpu->arch.update_pte.pfn;
289 if (is_error_pfn(pfn))
291 if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
295 * we call mmu_set_spte() with reset_host_protection = true beacuse that
296 * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1).
298 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
299 is_dirty_gpte(gpte), NULL, PT_PAGE_TABLE_LEVEL,
300 gpte_to_gfn(gpte), pfn, true, true);
303 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
304 struct guest_walker *gw, int level)
306 pt_element_t curr_pte;
307 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
311 if (level == PT_PAGE_TABLE_LEVEL) {
312 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
313 base_gpa = pte_gpa & ~mask;
314 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
316 r = kvm_read_guest_atomic(vcpu->kvm, base_gpa,
317 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
318 curr_pte = gw->prefetch_ptes[index];
320 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa,
321 &curr_pte, sizeof(curr_pte));
323 return r || curr_pte != gw->ptes[level - 1];
326 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
329 struct kvm_mmu_page *sp;
330 struct kvm_mmu *mmu = &vcpu->arch.mmu;
331 pt_element_t *gptep = gw->prefetch_ptes;
335 sp = page_header(__pa(sptep));
337 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
341 return __direct_pte_prefetch(vcpu, sp, sptep);
343 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
346 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
356 if (*spte != shadow_trap_nonpresent_pte)
361 if (!is_present_gpte(gpte) ||
362 is_rsvd_bits_set(mmu, gpte, PT_PAGE_TABLE_LEVEL)) {
364 __set_spte(spte, shadow_notrap_nonpresent_pte);
368 if (!(gpte & PT_ACCESSED_MASK))
371 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
372 gfn = gpte_to_gfn(gpte);
373 dirty = is_dirty_gpte(gpte);
374 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
375 (pte_access & ACC_WRITE_MASK) && dirty);
376 if (is_error_pfn(pfn)) {
377 kvm_release_pfn_clean(pfn);
381 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
382 dirty, NULL, PT_PAGE_TABLE_LEVEL, gfn,
388 * Fetch a shadow pte for a specific level in the paging hierarchy.
390 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
391 struct guest_walker *gw,
392 int user_fault, int write_fault, int hlevel,
393 int *ptwrite, pfn_t pfn)
395 unsigned access = gw->pt_access;
396 struct kvm_mmu_page *sp = NULL;
397 bool dirty = is_dirty_gpte(gw->ptes[gw->level - 1]);
399 unsigned direct_access;
400 struct kvm_shadow_walk_iterator it;
402 if (!is_present_gpte(gw->ptes[gw->level - 1]))
405 direct_access = gw->pt_access & gw->pte_access;
407 direct_access &= ~ACC_WRITE_MASK;
409 top_level = vcpu->arch.mmu.root_level;
410 if (top_level == PT32E_ROOT_LEVEL)
411 top_level = PT32_ROOT_LEVEL;
413 * Verify that the top-level gpte is still there. Since the page
414 * is a root page, it is either write protected (and cannot be
415 * changed from now on) or it is invalid (in which case, we don't
416 * really care if it changes underneath us after this point).
418 if (FNAME(gpte_changed)(vcpu, gw, top_level))
419 goto out_gpte_changed;
421 for (shadow_walk_init(&it, vcpu, addr);
422 shadow_walk_okay(&it) && it.level > gw->level;
423 shadow_walk_next(&it)) {
426 drop_large_spte(vcpu, it.sptep);
429 if (!is_shadow_present_pte(*it.sptep)) {
430 table_gfn = gw->table_gfn[it.level - 2];
431 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
432 false, access, it.sptep);
436 * Verify that the gpte in the page we've just write
437 * protected is still there.
439 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
440 goto out_gpte_changed;
443 link_shadow_page(it.sptep, sp);
447 shadow_walk_okay(&it) && it.level > hlevel;
448 shadow_walk_next(&it)) {
451 validate_direct_spte(vcpu, it.sptep, direct_access);
453 drop_large_spte(vcpu, it.sptep);
455 if (is_shadow_present_pte(*it.sptep))
458 direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
460 sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1,
461 true, direct_access, it.sptep);
462 link_shadow_page(it.sptep, sp);
465 mmu_set_spte(vcpu, it.sptep, access, gw->pte_access & access,
466 user_fault, write_fault, dirty, ptwrite, it.level,
467 gw->gfn, pfn, false, true);
468 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
474 kvm_mmu_put_page(sp, it.sptep);
475 kvm_release_pfn_clean(pfn);
480 * Page fault handler. There are several causes for a page fault:
481 * - there is no shadow pte for the guest pte
482 * - write access through a shadow pte marked read only so that we can set
484 * - write access to a shadow pte marked read only so we can update the page
485 * dirty bitmap, when userspace requests it
486 * - mmio access; in this case we will never install a present shadow pte
487 * - normal guest page fault due to the guest pte marked not present, not
488 * writable, or not executable
490 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
491 * a negative value on error.
493 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
496 int write_fault = error_code & PFERR_WRITE_MASK;
497 int user_fault = error_code & PFERR_USER_MASK;
498 int fetch_fault = error_code & PFERR_FETCH_MASK;
499 struct guest_walker walker;
504 int level = PT_PAGE_TABLE_LEVEL;
505 unsigned long mmu_seq;
507 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
509 r = mmu_topup_memory_caches(vcpu);
514 * Look up the guest pte for the faulting address.
516 r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
520 * The page is not mapped by the guest. Let the guest handle it.
523 pgprintk("%s: guest page fault\n", __func__);
524 inject_page_fault(vcpu, addr, walker.error_code);
525 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
529 if (walker.level >= PT_DIRECTORY_LEVEL) {
530 level = min(walker.level, mapping_level(vcpu, walker.gfn));
531 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
534 mmu_seq = vcpu->kvm->mmu_notifier_seq;
536 pfn = gfn_to_pfn(vcpu->kvm, walker.gfn);
539 if (is_error_pfn(pfn))
540 return kvm_handle_bad_page(vcpu->kvm, walker.gfn, pfn);
542 spin_lock(&vcpu->kvm->mmu_lock);
543 if (mmu_notifier_retry(vcpu, mmu_seq))
546 trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
547 kvm_mmu_free_some_pages(vcpu);
548 sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
549 level, &write_pt, pfn);
551 pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
552 sptep, *sptep, write_pt);
555 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
557 ++vcpu->stat.pf_fixed;
558 trace_kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
559 spin_unlock(&vcpu->kvm->mmu_lock);
564 spin_unlock(&vcpu->kvm->mmu_lock);
565 kvm_release_pfn_clean(pfn);
569 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
571 struct kvm_shadow_walk_iterator iterator;
572 struct kvm_mmu_page *sp;
578 spin_lock(&vcpu->kvm->mmu_lock);
580 for_each_shadow_entry(vcpu, gva, iterator) {
581 level = iterator.level;
582 sptep = iterator.sptep;
584 sp = page_header(__pa(sptep));
585 if (is_last_spte(*sptep, level)) {
592 (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level;
593 offset = sp->role.quadrant << shift;
595 pte_gpa = (sp->gfn << PAGE_SHIFT) + offset;
596 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
598 if (is_shadow_present_pte(*sptep)) {
599 if (is_large_pte(*sptep))
600 --vcpu->kvm->stat.lpages;
601 drop_spte(vcpu->kvm, sptep,
602 shadow_trap_nonpresent_pte);
605 __set_spte(sptep, shadow_trap_nonpresent_pte);
609 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
614 kvm_flush_remote_tlbs(vcpu->kvm);
616 atomic_inc(&vcpu->kvm->arch.invlpg_counter);
618 spin_unlock(&vcpu->kvm->mmu_lock);
623 if (mmu_topup_memory_caches(vcpu))
625 kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0);
628 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
631 struct guest_walker walker;
632 gpa_t gpa = UNMAPPED_GVA;
635 r = FNAME(walk_addr)(&walker, vcpu, vaddr,
636 !!(access & PFERR_WRITE_MASK),
637 !!(access & PFERR_USER_MASK),
638 !!(access & PFERR_FETCH_MASK));
641 gpa = gfn_to_gpa(walker.gfn);
642 gpa |= vaddr & ~PAGE_MASK;
644 *error = walker.error_code;
649 static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
650 struct kvm_mmu_page *sp)
653 pt_element_t pt[256 / sizeof(pt_element_t)];
657 || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
658 nonpaging_prefetch_page(vcpu, sp);
662 pte_gpa = gfn_to_gpa(sp->gfn);
664 offset = sp->role.quadrant << PT64_LEVEL_BITS;
665 pte_gpa += offset * sizeof(pt_element_t);
668 for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
669 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
670 pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
671 for (j = 0; j < ARRAY_SIZE(pt); ++j)
672 if (r || is_present_gpte(pt[j]))
673 sp->spt[i+j] = shadow_trap_nonpresent_pte;
675 sp->spt[i+j] = shadow_notrap_nonpresent_pte;
680 * Using the cached information from sp->gfns is safe because:
681 * - The spte has a reference to the struct page, so the pfn for a given gfn
682 * can't change unless all sptes pointing to it are nuked first.
684 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
687 int i, offset, nr_present;
688 bool reset_host_protection;
691 offset = nr_present = 0;
693 /* direct kvm_mmu_page can not be unsync. */
694 BUG_ON(sp->role.direct);
697 offset = sp->role.quadrant << PT64_LEVEL_BITS;
699 first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
701 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
707 if (!is_shadow_present_pte(sp->spt[i]))
710 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
712 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
713 sizeof(pt_element_t)))
716 gfn = gpte_to_gfn(gpte);
717 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)
718 || gfn != sp->gfns[i] || !is_present_gpte(gpte)
719 || !(gpte & PT_ACCESSED_MASK)) {
722 if (is_present_gpte(gpte) || !clear_unsync)
723 nonpresent = shadow_trap_nonpresent_pte;
725 nonpresent = shadow_notrap_nonpresent_pte;
726 drop_spte(vcpu->kvm, &sp->spt[i], nonpresent);
731 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
732 if (!(sp->spt[i] & SPTE_HOST_WRITEABLE)) {
733 pte_access &= ~ACC_WRITE_MASK;
734 reset_host_protection = 0;
736 reset_host_protection = 1;
738 set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
739 is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn,
740 spte_to_pfn(sp->spt[i]), true, false,
741 reset_host_protection);
750 #undef PT_BASE_ADDR_MASK
753 #undef PT_LVL_ADDR_MASK
754 #undef PT_LVL_OFFSET_MASK
756 #undef PT_MAX_FULL_LEVELS
758 #undef gpte_to_gfn_lvl