arch/x86/kvm/i8259.c

   1 /*
   2  * 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2007 Intel Corporation
   6  * Copyright 2009 Red Hat, Inc. and/or its affilates.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  * Authors:
  26  *   Yaozu (Eddie) Dong <Eddie.dong@intel.com>
  27  *   Port from Qemu.
  28  */
  29 #include <linux/mm.h>
  30 #include <linux/slab.h>
  31 #include <linux/bitops.h>
  32 #include "irq.h"
  33
  34 #include <linux/kvm_host.h>
  35 #include "trace.h"
  36
  37 static void pic_irq_request(struct kvm *kvm, int level);
  38
  39 static void pic_lock(struct kvm_pic *s)
  40         __acquires(&s->lock)
  41 {
  42         raw_spin_lock(&s->lock);
  43 }
  44
  45 static void pic_unlock(struct kvm_pic *s)
  46         __releases(&s->lock)
  47 {
  48         bool wakeup = s->wakeup_needed;
  49         struct kvm_vcpu *vcpu;
  50
  51         s->wakeup_needed = false;
  52
  53         raw_spin_unlock(&s->lock);
  54
  55         if (wakeup) {
  56                 vcpu = s->kvm->bsp_vcpu;
  57                 if (vcpu)
  58                         kvm_vcpu_kick(vcpu);
  59         }
  60 }
  61
  62 static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
  63 {
  64         s->isr &= ~(1 << irq);
  65         s->isr_ack |= (1 << irq);
  66         if (s != &s->pics_state->pics[0])
  67                 irq += 8;
  68         /*
  69          * We are dropping lock while calling ack notifiers since ack
  70          * notifier callbacks for assigned devices call into PIC recursively.
  71          * Other interrupt may be delivered to PIC while lock is dropped but
  72          * it should be safe since PIC state is already updated at this stage.
  73          */
  74         pic_unlock(s->pics_state);
  75         kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq);
  76         pic_lock(s->pics_state);
  77 }
  78
  79 void kvm_pic_clear_isr_ack(struct kvm *kvm)
  80 {
  81         struct kvm_pic *s = pic_irqchip(kvm);
  82
  83         pic_lock(s);
  84         s->pics[0].isr_ack = 0xff;
  85         s->pics[1].isr_ack = 0xff;
  86         pic_unlock(s);
  87 }
  88
  89 /*
  90  * set irq level. If an edge is detected, then the IRR is set to 1
  91  */
  92 static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
  93 {
  94         int mask, ret = 1;
  95         mask = 1 << irq;
  96         if (s->elcr & mask)     /* level triggered */
  97                 if (level) {
  98                         ret = !(s->irr & mask);
  99                         s->irr |= mask;
 100                         s->last_irr |= mask;
 101                 } else {
 102                         s->irr &= ~mask;
 103                         s->last_irr &= ~mask;
 104                 }
 105         else    /* edge triggered */
 106                 if (level) {
 107                         if ((s->last_irr & mask) == 0) {
 108                                 ret = !(s->irr & mask);
 109                                 s->irr |= mask;
 110                         }
 111                         s->last_irr |= mask;
 112                 } else
 113                         s->last_irr &= ~mask;
 114
 115         return (s->imr & mask) ? -1 : ret;
 116 }
 117
 118 /*
 119  * return the highest priority found in mask (highest = smallest
 120  * number). Return 8 if no irq
 121  */
 122 static inline int get_priority(struct kvm_kpic_state *s, int mask)
 123 {
 124         int priority;
 125         if (mask == 0)
 126                 return 8;
 127         priority = 0;
 128         while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
 129                 priority++;
 130         return priority;
 131 }
 132
 133 /*
 134  * return the pic wanted interrupt. return -1 if none
 135  */
 136 static int pic_get_irq(struct kvm_kpic_state *s)
 137 {
 138         int mask, cur_priority, priority;
 139
 140         mask = s->irr & ~s->imr;
 141         priority = get_priority(s, mask);
 142         if (priority == 8)
 143                 return -1;
 144         /*
 145          * compute current priority. If special fully nested mode on the
 146          * master, the IRQ coming from the slave is not taken into account
 147          * for the priority computation.
 148          */
 149         mask = s->isr;
 150         if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
 151                 mask &= ~(1 << 2);
 152         cur_priority = get_priority(s, mask);
 153         if (priority < cur_priority)
 154                 /*
 155                  * higher priority found: an irq should be generated
 156                  */
 157                 return (priority + s->priority_add) & 7;
 158         else
 159                 return -1;
 160 }
 161
 162 /*
 163  * raise irq to CPU if necessary. must be called every time the active
 164  * irq may change
 165  */
 166 static void pic_update_irq(struct kvm_pic *s)
 167 {
 168         int irq2, irq;
 169
 170         irq2 = pic_get_irq(&s->pics[1]);
 171         if (irq2 >= 0) {
 172                 /*
 173                  * if irq request by slave pic, signal master PIC
 174                  */
 175                 pic_set_irq1(&s->pics[0], 2, 1);
 176                 pic_set_irq1(&s->pics[0], 2, 0);
 177         }
 178         irq = pic_get_irq(&s->pics[0]);
 179         pic_irq_request(s->kvm, irq >= 0);
 180 }
 181
 182 void kvm_pic_update_irq(struct kvm_pic *s)
 183 {
 184         pic_lock(s);
 185         pic_update_irq(s);
 186         pic_unlock(s);
 187 }
 188
 189 int kvm_pic_set_irq(void *opaque, int irq, int level)
 190 {
 191         struct kvm_pic *s = opaque;
 192         int ret = -1;
 193
 194         pic_lock(s);
 195         if (irq >= 0 && irq < PIC_NUM_PINS) {
 196                 ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
 197                 pic_update_irq(s);
 198                 trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
 199                                       s->pics[irq >> 3].imr, ret == 0);
 200         }
 201         pic_unlock(s);
 202
 203         return ret;
 204 }
 205
 206 /*
 207  * acknowledge interrupt 'irq'
 208  */
 209 static inline void pic_intack(struct kvm_kpic_state *s, int irq)
 210 {
 211         s->isr |= 1 << irq;
 212         /*
 213          * We don't clear a level sensitive interrupt here
 214          */
 215         if (!(s->elcr & (1 << irq)))
 216                 s->irr &= ~(1 << irq);
 217
 218         if (s->auto_eoi) {
 219                 if (s->rotate_on_auto_eoi)
 220                         s->priority_add = (irq + 1) & 7;
 221                 pic_clear_isr(s, irq);
 222         }
 223
 224 }
 225
 226 int kvm_pic_read_irq(struct kvm *kvm)
 227 {
 228         int irq, irq2, intno;
 229         struct kvm_pic *s = pic_irqchip(kvm);
 230
 231         pic_lock(s);
 232         irq = pic_get_irq(&s->pics[0]);
 233         if (irq >= 0) {
 234                 pic_intack(&s->pics[0], irq);
 235                 if (irq == 2) {
 236                         irq2 = pic_get_irq(&s->pics[1]);
 237                         if (irq2 >= 0)
 238                                 pic_intack(&s->pics[1], irq2);
 239                         else
 240                                 /*
 241                                  * spurious IRQ on slave controller
 242                                  */
 243                                 irq2 = 7;
 244                         intno = s->pics[1].irq_base + irq2;
 245                         irq = irq2 + 8;
 246                 } else
 247                         intno = s->pics[0].irq_base + irq;
 248         } else {
 249                 /*
 250                  * spurious IRQ on host controller
 251                  */
 252                 irq = 7;
 253                 intno = s->pics[0].irq_base + irq;
 254         }
 255         pic_update_irq(s);
 256         pic_unlock(s);
 257
 258         return intno;
 259 }
 260
 261 void kvm_pic_reset(struct kvm_kpic_state *s)
 262 {
 263         int irq;
 264         struct kvm_vcpu *vcpu0 = s->pics_state->kvm->bsp_vcpu;
 265         u8 irr = s->irr, isr = s->imr;
 266
 267         s->last_irr = 0;
 268         s->irr = 0;
 269         s->imr = 0;
 270         s->isr = 0;
 271         s->isr_ack = 0xff;
 272         s->priority_add = 0;
 273         s->irq_base = 0;
 274         s->read_reg_select = 0;
 275         s->poll = 0;
 276         s->special_mask = 0;
 277         s->init_state = 0;
 278         s->auto_eoi = 0;
 279         s->rotate_on_auto_eoi = 0;
 280         s->special_fully_nested_mode = 0;
 281         s->init4 = 0;
 282
 283         for (irq = 0; irq < PIC_NUM_PINS/2; irq++) {
 284                 if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0))
 285                         if (irr & (1 << irq) || isr & (1 << irq)) {
 286                                 pic_clear_isr(s, irq);
 287                         }
 288         }
 289 }
 290
 291 static void pic_ioport_write(void *opaque, u32 addr, u32 val)
 292 {
 293         struct kvm_kpic_state *s = opaque;
 294         int priority, cmd, irq;
 295
 296         addr &= 1;
 297         if (addr == 0) {
 298                 if (val & 0x10) {
 299                         kvm_pic_reset(s);       /* init */
 300                         /*
 301                          * deassert a pending interrupt
 302                          */
 303                         pic_irq_request(s->pics_state->kvm, 0);
 304                         s->init_state = 1;
 305                         s->init4 = val & 1;
 306                         if (val & 0x02)
 307                                 printk(KERN_ERR "single mode not supported");
 308                         if (val & 0x08)
 309                                 printk(KERN_ERR
 310                                        "level sensitive irq not supported");
 311                 } else if (val & 0x08) {
 312                         if (val & 0x04)
 313                                 s->poll = 1;
 314                         if (val & 0x02)
 315                                 s->read_reg_select = val & 1;
 316                         if (val & 0x40)
 317                                 s->special_mask = (val >> 5) & 1;
 318                 } else {
 319                         cmd = val >> 5;
 320                         switch (cmd) {
 321                         case 0:
 322                         case 4:
 323                                 s->rotate_on_auto_eoi = cmd >> 2;
 324                                 break;
 325                         case 1: /* end of interrupt */
 326                         case 5:
 327                                 priority = get_priority(s, s->isr);
 328                                 if (priority != 8) {
 329                                         irq = (priority + s->priority_add) & 7;
 330                                         if (cmd == 5)
 331                                                 s->priority_add = (irq + 1) & 7;
 332                                         pic_clear_isr(s, irq);
 333                                         pic_update_irq(s->pics_state);
 334                                 }
 335                                 break;
 336                         case 3:
 337                                 irq = val & 7;
 338                                 pic_clear_isr(s, irq);
 339                                 pic_update_irq(s->pics_state);
 340                                 break;
 341                         case 6:
 342                                 s->priority_add = (val + 1) & 7;
 343                                 pic_update_irq(s->pics_state);
 344                                 break;
 345                         case 7:
 346                                 irq = val & 7;
 347                                 s->priority_add = (irq + 1) & 7;
 348                                 pic_clear_isr(s, irq);
 349                                 pic_update_irq(s->pics_state);
 350                                 break;
 351                         default:
 352                                 break;  /* no operation */
 353                         }
 354                 }
 355         } else
 356                 switch (s->init_state) {
 357                 case 0:         /* normal mode */
 358                         s->imr = val;
 359                         pic_update_irq(s->pics_state);
 360                         break;
 361                 case 1:
 362                         s->irq_base = val & 0xf8;
 363                         s->init_state = 2;
 364                         break;
 365                 case 2:
 366                         if (s->init4)
 367                                 s->init_state = 3;
 368                         else
 369                                 s->init_state = 0;
 370                         break;
 371                 case 3:
 372                         s->special_fully_nested_mode = (val >> 4) & 1;
 373                         s->auto_eoi = (val >> 1) & 1;
 374                         s->init_state = 0;
 375                         break;
 376                 }
 377 }
 378
 379 static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
 380 {
 381         int ret;
 382
 383         ret = pic_get_irq(s);
 384         if (ret >= 0) {
 385                 if (addr1 >> 7) {
 386                         s->pics_state->pics[0].isr &= ~(1 << 2);
 387                         s->pics_state->pics[0].irr &= ~(1 << 2);
 388                 }
 389                 s->irr &= ~(1 << ret);
 390                 pic_clear_isr(s, ret);
 391                 if (addr1 >> 7 || ret != 2)
 392                         pic_update_irq(s->pics_state);
 393         } else {
 394                 ret = 0x07;
 395                 pic_update_irq(s->pics_state);
 396         }
 397
 398         return ret;
 399 }
 400
 401 static u32 pic_ioport_read(void *opaque, u32 addr1)
 402 {
 403         struct kvm_kpic_state *s = opaque;
 404         unsigned int addr;
 405         int ret;
 406
 407         addr = addr1;
 408         addr &= 1;
 409         if (s->poll) {
 410                 ret = pic_poll_read(s, addr1);
 411                 s->poll = 0;
 412         } else
 413                 if (addr == 0)
 414                         if (s->read_reg_select)
 415                                 ret = s->isr;
 416                         else
 417                                 ret = s->irr;
 418                 else
 419                         ret = s->imr;
 420         return ret;
 421 }
 422
 423 static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
 424 {
 425         struct kvm_kpic_state *s = opaque;
 426         s->elcr = val & s->elcr_mask;
 427 }
 428
 429 static u32 elcr_ioport_read(void *opaque, u32 addr1)
 430 {
 431         struct kvm_kpic_state *s = opaque;
 432         return s->elcr;
 433 }
 434
 435 static int picdev_in_range(gpa_t addr)
 436 {
 437         switch (addr) {
 438         case 0x20:
 439         case 0x21:
 440         case 0xa0:
 441         case 0xa1:
 442         case 0x4d0:
 443         case 0x4d1:
 444                 return 1;
 445         default:
 446                 return 0;
 447         }
 448 }
 449
 450 static inline struct kvm_pic *to_pic(struct kvm_io_device *dev)
 451 {
 452         return container_of(dev, struct kvm_pic, dev);
 453 }
 454
 455 static int picdev_write(struct kvm_io_device *this,
 456                          gpa_t addr, int len, const void *val)
 457 {
 458         struct kvm_pic *s = to_pic(this);
 459         unsigned char data = *(unsigned char *)val;
 460         if (!picdev_in_range(addr))
 461                 return -EOPNOTSUPP;
 462
 463         if (len != 1) {
 464                 if (printk_ratelimit())
 465                         printk(KERN_ERR "PIC: non byte write\n");
 466                 return 0;
 467         }
 468         pic_lock(s);
 469         switch (addr) {
 470         case 0x20:
 471         case 0x21:
 472         case 0xa0:
 473         case 0xa1:
 474                 pic_ioport_write(&s->pics[addr >> 7], addr, data);
 475                 break;
 476         case 0x4d0:
 477         case 0x4d1:
 478                 elcr_ioport_write(&s->pics[addr & 1], addr, data);
 479                 break;
 480         }
 481         pic_unlock(s);
 482         return 0;
 483 }
 484
 485 static int picdev_read(struct kvm_io_device *this,
 486                        gpa_t addr, int len, void *val)
 487 {
 488         struct kvm_pic *s = to_pic(this);
 489         unsigned char data = 0;
 490         if (!picdev_in_range(addr))
 491                 return -EOPNOTSUPP;
 492
 493         if (len != 1) {
 494                 if (printk_ratelimit())
 495                         printk(KERN_ERR "PIC: non byte read\n");
 496                 return 0;
 497         }
 498         pic_lock(s);
 499         switch (addr) {
 500         case 0x20:
 501         case 0x21:
 502         case 0xa0:
 503         case 0xa1:
 504                 data = pic_ioport_read(&s->pics[addr >> 7], addr);
 505                 break;
 506         case 0x4d0:
 507         case 0x4d1:
 508                 data = elcr_ioport_read(&s->pics[addr & 1], addr);
 509                 break;
 510         }
 511         *(unsigned char *)val = data;
 512         pic_unlock(s);
 513         return 0;
 514 }
 515
 516 /*
 517  * callback when PIC0 irq status changed
 518  */
 519 static void pic_irq_request(struct kvm *kvm, int level)
 520 {
 521         struct kvm_vcpu *vcpu = kvm->bsp_vcpu;
 522         struct kvm_pic *s = pic_irqchip(kvm);
 523         int irq = pic_get_irq(&s->pics[0]);
 524
 525         s->output = level;
 526         if (vcpu && level && (s->pics[0].isr_ack & (1 << irq))) {
 527                 s->pics[0].isr_ack &= ~(1 << irq);
 528                 s->wakeup_needed = true;
 529         }
 530 }
 531
 532 static const struct kvm_io_device_ops picdev_ops = {
 533         .read     = picdev_read,
 534         .write    = picdev_write,
 535 };
 536
 537 struct kvm_pic *kvm_create_pic(struct kvm *kvm)
 538 {
 539         struct kvm_pic *s;
 540         int ret;
 541
 542         s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
 543         if (!s)
 544                 return NULL;
 545         raw_spin_lock_init(&s->lock);
 546         s->kvm = kvm;
 547         s->pics[0].elcr_mask = 0xf8;
 548         s->pics[1].elcr_mask = 0xde;
 549         s->pics[0].pics_state = s;
 550         s->pics[1].pics_state = s;
 551
 552         /*
 553          * Initialize PIO device
 554          */
 555         kvm_iodevice_init(&s->dev, &picdev_ops);
 556         mutex_lock(&kvm->slots_lock);
 557         ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, &s->dev);
 558         mutex_unlock(&kvm->slots_lock);
 559         if (ret < 0) {
 560                 kfree(s);
 561                 return NULL;
 562         }
 563
 564         return s;
 565 }
 566
 567 void kvm_destroy_pic(struct kvm *kvm)
 568 {
 569         struct kvm_pic *vpic = kvm->arch.vpic;
 570
 571         if (vpic) {
 572                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev);
 573                 kvm->arch.vpic = NULL;
 574                 kfree(vpic);
 575         }
 576 }