2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
37 #include <acpi/acpi_bus.h>
39 #include <linux/bootmem.h>
45 #include <asm/proto.h>
49 #include <asm/msidef.h>
50 #include <asm/hypertransport.h>
53 #include <mach_apic.h>
58 unsigned move_cleanup_count;
60 u8 move_in_progress : 1;
63 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
64 struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
65 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
66 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
67 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
68 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
69 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
70 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
71 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
72 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
73 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
74 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
75 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
76 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
77 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
78 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
79 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
80 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
83 static int assign_irq_vector(int irq, cpumask_t mask);
85 #define __apicdebuginit __init
87 int sis_apic_bug; /* not actually supported, dummy for compile */
89 static int no_timer_check;
91 static int disable_timer_pin_1 __initdata;
93 int timer_through_8259 __initdata;
95 /* Where if anywhere is the i8259 connect in external int mode */
96 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
98 static DEFINE_SPINLOCK(ioapic_lock);
99 DEFINE_SPINLOCK(vector_lock);
102 * # of IRQ routing registers
104 int nr_ioapic_registers[MAX_IO_APICS];
106 /* I/O APIC entries */
107 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
110 /* MP IRQ source entries */
111 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
113 /* # of MP IRQ source entries */
117 * Rough estimation of how many shared IRQs there are, can
118 * be changed anytime.
120 #define MAX_PLUS_SHARED_IRQS NR_IRQS
121 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
124 * This is performance-critical, we want to do it O(1)
126 * the indexing order of this array favors 1:1 mappings
127 * between pins and IRQs.
130 static struct irq_pin_list {
131 short apic, pin, next;
132 } irq_2_pin[PIN_MAP_SIZE];
136 unsigned int unused[3];
140 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
142 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
143 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
146 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
148 struct io_apic __iomem *io_apic = io_apic_base(apic);
149 writel(reg, &io_apic->index);
150 return readl(&io_apic->data);
153 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
155 struct io_apic __iomem *io_apic = io_apic_base(apic);
156 writel(reg, &io_apic->index);
157 writel(value, &io_apic->data);
161 * Re-write a value: to be used for read-modify-write
162 * cycles where the read already set up the index register.
164 static inline void io_apic_modify(unsigned int apic, unsigned int value)
166 struct io_apic __iomem *io_apic = io_apic_base(apic);
167 writel(value, &io_apic->data);
170 static bool io_apic_level_ack_pending(unsigned int irq)
172 struct irq_pin_list *entry;
175 spin_lock_irqsave(&ioapic_lock, flags);
176 entry = irq_2_pin + irq;
184 reg = io_apic_read(entry->apic, 0x10 + pin*2);
185 /* Is the remote IRR bit set? */
186 if ((reg >> 14) & 1) {
187 spin_unlock_irqrestore(&ioapic_lock, flags);
192 entry = irq_2_pin + entry->next;
194 spin_unlock_irqrestore(&ioapic_lock, flags);
200 * Synchronize the IO-APIC and the CPU by doing
201 * a dummy read from the IO-APIC
203 static inline void io_apic_sync(unsigned int apic)
205 struct io_apic __iomem *io_apic = io_apic_base(apic);
206 readl(&io_apic->data);
209 #define __DO_ACTION(R, ACTION, FINAL) \
213 struct irq_pin_list *entry = irq_2_pin + irq; \
215 BUG_ON(irq >= NR_IRQS); \
221 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
223 io_apic_modify(entry->apic, reg); \
227 entry = irq_2_pin + entry->next; \
232 struct { u32 w1, w2; };
233 struct IO_APIC_route_entry entry;
236 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
238 union entry_union eu;
240 spin_lock_irqsave(&ioapic_lock, flags);
241 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
242 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
243 spin_unlock_irqrestore(&ioapic_lock, flags);
248 * When we write a new IO APIC routing entry, we need to write the high
249 * word first! If the mask bit in the low word is clear, we will enable
250 * the interrupt, and we need to make sure the entry is fully populated
251 * before that happens.
254 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
256 union entry_union eu;
258 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
259 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
262 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
265 spin_lock_irqsave(&ioapic_lock, flags);
266 __ioapic_write_entry(apic, pin, e);
267 spin_unlock_irqrestore(&ioapic_lock, flags);
271 * When we mask an IO APIC routing entry, we need to write the low
272 * word first, in order to set the mask bit before we change the
275 static void ioapic_mask_entry(int apic, int pin)
278 union entry_union eu = { .entry.mask = 1 };
280 spin_lock_irqsave(&ioapic_lock, flags);
281 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
282 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
283 spin_unlock_irqrestore(&ioapic_lock, flags);
287 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
290 struct irq_pin_list *entry = irq_2_pin + irq;
292 BUG_ON(irq >= NR_IRQS);
299 io_apic_write(apic, 0x11 + pin*2, dest);
300 reg = io_apic_read(apic, 0x10 + pin*2);
303 io_apic_modify(apic, reg);
306 entry = irq_2_pin + entry->next;
310 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
312 struct irq_cfg *cfg = irq_cfg + irq;
317 cpus_and(tmp, mask, cpu_online_map);
321 if (assign_irq_vector(irq, mask))
324 cpus_and(tmp, cfg->domain, mask);
325 dest = cpu_mask_to_apicid(tmp);
328 * Only the high 8 bits are valid.
330 dest = SET_APIC_LOGICAL_ID(dest);
332 spin_lock_irqsave(&ioapic_lock, flags);
333 __target_IO_APIC_irq(irq, dest, cfg->vector);
334 irq_desc[irq].affinity = mask;
335 spin_unlock_irqrestore(&ioapic_lock, flags);
340 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
341 * shared ISA-space IRQs, so we have to support them. We are super
342 * fast in the common case, and fast for shared ISA-space IRQs.
344 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
346 static int first_free_entry = NR_IRQS;
347 struct irq_pin_list *entry = irq_2_pin + irq;
349 BUG_ON(irq >= NR_IRQS);
351 entry = irq_2_pin + entry->next;
353 if (entry->pin != -1) {
354 entry->next = first_free_entry;
355 entry = irq_2_pin + entry->next;
356 if (++first_free_entry >= PIN_MAP_SIZE)
357 panic("io_apic.c: ran out of irq_2_pin entries!");
364 #define DO_ACTION(name,R,ACTION, FINAL) \
366 static void name##_IO_APIC_irq (unsigned int irq) \
367 __DO_ACTION(R, ACTION, FINAL)
369 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
371 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
374 static void mask_IO_APIC_irq (unsigned int irq)
378 spin_lock_irqsave(&ioapic_lock, flags);
379 __mask_IO_APIC_irq(irq);
380 spin_unlock_irqrestore(&ioapic_lock, flags);
383 static void unmask_IO_APIC_irq (unsigned int irq)
387 spin_lock_irqsave(&ioapic_lock, flags);
388 __unmask_IO_APIC_irq(irq);
389 spin_unlock_irqrestore(&ioapic_lock, flags);
392 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
394 struct IO_APIC_route_entry entry;
396 /* Check delivery_mode to be sure we're not clearing an SMI pin */
397 entry = ioapic_read_entry(apic, pin);
398 if (entry.delivery_mode == dest_SMI)
401 * Disable it in the IO-APIC irq-routing table:
403 ioapic_mask_entry(apic, pin);
406 static void clear_IO_APIC (void)
410 for (apic = 0; apic < nr_ioapics; apic++)
411 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
412 clear_IO_APIC_pin(apic, pin);
415 int skip_ioapic_setup;
418 static int __init parse_noapic(char *str)
420 disable_ioapic_setup();
423 early_param("noapic", parse_noapic);
425 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
426 static int __init disable_timer_pin_setup(char *arg)
428 disable_timer_pin_1 = 1;
431 __setup("disable_timer_pin_1", disable_timer_pin_setup);
435 * Find the IRQ entry number of a certain pin.
437 static int find_irq_entry(int apic, int pin, int type)
441 for (i = 0; i < mp_irq_entries; i++)
442 if (mp_irqs[i].mpc_irqtype == type &&
443 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
444 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
445 mp_irqs[i].mpc_dstirq == pin)
452 * Find the pin to which IRQ[irq] (ISA) is connected
454 static int __init find_isa_irq_pin(int irq, int type)
458 for (i = 0; i < mp_irq_entries; i++) {
459 int lbus = mp_irqs[i].mpc_srcbus;
461 if (test_bit(lbus, mp_bus_not_pci) &&
462 (mp_irqs[i].mpc_irqtype == type) &&
463 (mp_irqs[i].mpc_srcbusirq == irq))
465 return mp_irqs[i].mpc_dstirq;
470 static int __init find_isa_irq_apic(int irq, int type)
474 for (i = 0; i < mp_irq_entries; i++) {
475 int lbus = mp_irqs[i].mpc_srcbus;
477 if (test_bit(lbus, mp_bus_not_pci) &&
478 (mp_irqs[i].mpc_irqtype == type) &&
479 (mp_irqs[i].mpc_srcbusirq == irq))
482 if (i < mp_irq_entries) {
484 for(apic = 0; apic < nr_ioapics; apic++) {
485 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
494 * Find a specific PCI IRQ entry.
495 * Not an __init, possibly needed by modules
497 static int pin_2_irq(int idx, int apic, int pin);
499 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
501 int apic, i, best_guess = -1;
503 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
505 if (mp_bus_id_to_pci_bus[bus] == -1) {
506 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
509 for (i = 0; i < mp_irq_entries; i++) {
510 int lbus = mp_irqs[i].mpc_srcbus;
512 for (apic = 0; apic < nr_ioapics; apic++)
513 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
514 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
517 if (!test_bit(lbus, mp_bus_not_pci) &&
518 !mp_irqs[i].mpc_irqtype &&
520 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
521 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
523 if (!(apic || IO_APIC_IRQ(irq)))
526 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
529 * Use the first all-but-pin matching entry as a
530 * best-guess fuzzy result for broken mptables.
536 BUG_ON(best_guess >= NR_IRQS);
540 /* ISA interrupts are always polarity zero edge triggered,
541 * when listed as conforming in the MP table. */
543 #define default_ISA_trigger(idx) (0)
544 #define default_ISA_polarity(idx) (0)
546 /* PCI interrupts are always polarity one level triggered,
547 * when listed as conforming in the MP table. */
549 #define default_PCI_trigger(idx) (1)
550 #define default_PCI_polarity(idx) (1)
552 static int MPBIOS_polarity(int idx)
554 int bus = mp_irqs[idx].mpc_srcbus;
558 * Determine IRQ line polarity (high active or low active):
560 switch (mp_irqs[idx].mpc_irqflag & 3)
562 case 0: /* conforms, ie. bus-type dependent polarity */
563 if (test_bit(bus, mp_bus_not_pci))
564 polarity = default_ISA_polarity(idx);
566 polarity = default_PCI_polarity(idx);
568 case 1: /* high active */
573 case 2: /* reserved */
575 printk(KERN_WARNING "broken BIOS!!\n");
579 case 3: /* low active */
584 default: /* invalid */
586 printk(KERN_WARNING "broken BIOS!!\n");
594 static int MPBIOS_trigger(int idx)
596 int bus = mp_irqs[idx].mpc_srcbus;
600 * Determine IRQ trigger mode (edge or level sensitive):
602 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
604 case 0: /* conforms, ie. bus-type dependent */
605 if (test_bit(bus, mp_bus_not_pci))
606 trigger = default_ISA_trigger(idx);
608 trigger = default_PCI_trigger(idx);
615 case 2: /* reserved */
617 printk(KERN_WARNING "broken BIOS!!\n");
626 default: /* invalid */
628 printk(KERN_WARNING "broken BIOS!!\n");
636 static inline int irq_polarity(int idx)
638 return MPBIOS_polarity(idx);
641 static inline int irq_trigger(int idx)
643 return MPBIOS_trigger(idx);
646 static int pin_2_irq(int idx, int apic, int pin)
649 int bus = mp_irqs[idx].mpc_srcbus;
652 * Debugging check, we are in big trouble if this message pops up!
654 if (mp_irqs[idx].mpc_dstirq != pin)
655 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
657 if (test_bit(bus, mp_bus_not_pci)) {
658 irq = mp_irqs[idx].mpc_srcbusirq;
661 * PCI IRQs are mapped in order
665 irq += nr_ioapic_registers[i++];
668 BUG_ON(irq >= NR_IRQS);
672 static int __assign_irq_vector(int irq, cpumask_t mask)
675 * NOTE! The local APIC isn't very good at handling
676 * multiple interrupts at the same interrupt level.
677 * As the interrupt level is determined by taking the
678 * vector number and shifting that right by 4, we
679 * want to spread these out a bit so that they don't
680 * all fall in the same interrupt level.
682 * Also, we've got to be careful not to trash gate
683 * 0x80, because int 0x80 is hm, kind of importantish. ;)
685 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
686 unsigned int old_vector;
690 BUG_ON((unsigned)irq >= NR_IRQS);
693 /* Only try and allocate irqs on cpus that are present */
694 cpus_and(mask, mask, cpu_online_map);
696 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
699 old_vector = cfg->vector;
702 cpus_and(tmp, cfg->domain, mask);
703 if (!cpus_empty(tmp))
707 for_each_cpu_mask(cpu, mask) {
708 cpumask_t domain, new_mask;
712 domain = vector_allocation_domain(cpu);
713 cpus_and(new_mask, domain, cpu_online_map);
715 vector = current_vector;
716 offset = current_offset;
719 if (vector >= FIRST_SYSTEM_VECTOR) {
720 /* If we run out of vectors on large boxen, must share them. */
721 offset = (offset + 1) % 8;
722 vector = FIRST_DEVICE_VECTOR + offset;
724 if (unlikely(current_vector == vector))
726 if (vector == IA32_SYSCALL_VECTOR)
728 for_each_cpu_mask(new_cpu, new_mask)
729 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
732 current_vector = vector;
733 current_offset = offset;
735 cfg->move_in_progress = 1;
736 cfg->old_domain = cfg->domain;
738 for_each_cpu_mask(new_cpu, new_mask)
739 per_cpu(vector_irq, new_cpu)[vector] = irq;
740 cfg->vector = vector;
741 cfg->domain = domain;
747 static int assign_irq_vector(int irq, cpumask_t mask)
752 spin_lock_irqsave(&vector_lock, flags);
753 err = __assign_irq_vector(irq, mask);
754 spin_unlock_irqrestore(&vector_lock, flags);
758 static void __clear_irq_vector(int irq)
764 BUG_ON((unsigned)irq >= NR_IRQS);
766 BUG_ON(!cfg->vector);
768 vector = cfg->vector;
769 cpus_and(mask, cfg->domain, cpu_online_map);
770 for_each_cpu_mask(cpu, mask)
771 per_cpu(vector_irq, cpu)[vector] = -1;
774 cpus_clear(cfg->domain);
777 void __setup_vector_irq(int cpu)
779 /* Initialize vector_irq on a new cpu */
780 /* This function must be called with vector_lock held */
783 /* Mark the inuse vectors */
784 for (irq = 0; irq < NR_IRQS; ++irq) {
785 if (!cpu_isset(cpu, irq_cfg[irq].domain))
787 vector = irq_cfg[irq].vector;
788 per_cpu(vector_irq, cpu)[vector] = irq;
790 /* Mark the free vectors */
791 for (vector = 0; vector < NR_VECTORS; ++vector) {
792 irq = per_cpu(vector_irq, cpu)[vector];
795 if (!cpu_isset(cpu, irq_cfg[irq].domain))
796 per_cpu(vector_irq, cpu)[vector] = -1;
801 static struct irq_chip ioapic_chip;
803 static void ioapic_register_intr(int irq, unsigned long trigger)
806 irq_desc[irq].status |= IRQ_LEVEL;
807 set_irq_chip_and_handler_name(irq, &ioapic_chip,
808 handle_fasteoi_irq, "fasteoi");
810 irq_desc[irq].status &= ~IRQ_LEVEL;
811 set_irq_chip_and_handler_name(irq, &ioapic_chip,
812 handle_edge_irq, "edge");
816 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
817 int trigger, int polarity)
819 struct irq_cfg *cfg = irq_cfg + irq;
820 struct IO_APIC_route_entry entry;
823 if (!IO_APIC_IRQ(irq))
827 if (assign_irq_vector(irq, mask))
830 cpus_and(mask, cfg->domain, mask);
832 apic_printk(APIC_VERBOSE,KERN_DEBUG
833 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
834 "IRQ %d Mode:%i Active:%i)\n",
835 apic, mp_ioapics[apic].mpc_apicid, pin, cfg->vector,
836 irq, trigger, polarity);
839 * add it to the IO-APIC irq-routing table:
841 memset(&entry,0,sizeof(entry));
843 entry.delivery_mode = INT_DELIVERY_MODE;
844 entry.dest_mode = INT_DEST_MODE;
845 entry.dest = cpu_mask_to_apicid(mask);
846 entry.mask = 0; /* enable IRQ */
847 entry.trigger = trigger;
848 entry.polarity = polarity;
849 entry.vector = cfg->vector;
851 /* Mask level triggered irqs.
852 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
857 ioapic_register_intr(irq, trigger);
859 disable_8259A_irq(irq);
861 ioapic_write_entry(apic, pin, entry);
864 static void __init setup_IO_APIC_irqs(void)
866 int apic, pin, idx, irq, first_notcon = 1;
868 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
870 for (apic = 0; apic < nr_ioapics; apic++) {
871 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
873 idx = find_irq_entry(apic,pin,mp_INT);
876 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
879 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
883 apic_printk(APIC_VERBOSE, " not connected.\n");
887 irq = pin_2_irq(idx, apic, pin);
888 add_pin_to_irq(irq, apic, pin);
890 setup_IO_APIC_irq(apic, pin, irq,
891 irq_trigger(idx), irq_polarity(idx));
896 apic_printk(APIC_VERBOSE, " not connected.\n");
900 * Set up the timer pin, possibly with the 8259A-master behind.
902 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
905 struct IO_APIC_route_entry entry;
907 memset(&entry, 0, sizeof(entry));
910 * We use logical delivery to get the timer IRQ
913 entry.dest_mode = INT_DEST_MODE;
914 entry.mask = 0; /* unmask IRQ now */
915 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
916 entry.delivery_mode = INT_DELIVERY_MODE;
919 entry.vector = vector;
922 * The timer IRQ doesn't have to know that behind the
923 * scene we may have a 8259A-master in AEOI mode ...
925 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
928 * Add it to the IO-APIC irq-routing table:
930 ioapic_write_entry(apic, pin, entry);
933 void __apicdebuginit print_IO_APIC(void)
936 union IO_APIC_reg_00 reg_00;
937 union IO_APIC_reg_01 reg_01;
938 union IO_APIC_reg_02 reg_02;
941 if (apic_verbosity == APIC_QUIET)
944 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
945 for (i = 0; i < nr_ioapics; i++)
946 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
947 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
950 * We are a bit conservative about what we expect. We have to
951 * know about every hardware change ASAP.
953 printk(KERN_INFO "testing the IO APIC.......................\n");
955 for (apic = 0; apic < nr_ioapics; apic++) {
957 spin_lock_irqsave(&ioapic_lock, flags);
958 reg_00.raw = io_apic_read(apic, 0);
959 reg_01.raw = io_apic_read(apic, 1);
960 if (reg_01.bits.version >= 0x10)
961 reg_02.raw = io_apic_read(apic, 2);
962 spin_unlock_irqrestore(&ioapic_lock, flags);
965 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
966 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
967 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
969 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
970 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
972 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
973 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
975 if (reg_01.bits.version >= 0x10) {
976 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
977 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
980 printk(KERN_DEBUG ".... IRQ redirection table:\n");
982 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
983 " Stat Dmod Deli Vect: \n");
985 for (i = 0; i <= reg_01.bits.entries; i++) {
986 struct IO_APIC_route_entry entry;
988 entry = ioapic_read_entry(apic, i);
990 printk(KERN_DEBUG " %02x %03X ",
995 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1000 entry.delivery_status,
1002 entry.delivery_mode,
1007 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1008 for (i = 0; i < NR_IRQS; i++) {
1009 struct irq_pin_list *entry = irq_2_pin + i;
1012 printk(KERN_DEBUG "IRQ%d ", i);
1014 printk("-> %d:%d", entry->apic, entry->pin);
1017 entry = irq_2_pin + entry->next;
1022 printk(KERN_INFO ".................................... done.\n");
1029 static __apicdebuginit void print_APIC_bitfield (int base)
1034 if (apic_verbosity == APIC_QUIET)
1037 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1038 for (i = 0; i < 8; i++) {
1039 v = apic_read(base + i*0x10);
1040 for (j = 0; j < 32; j++) {
1050 void __apicdebuginit print_local_APIC(void * dummy)
1052 unsigned int v, ver, maxlvt;
1054 if (apic_verbosity == APIC_QUIET)
1057 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1058 smp_processor_id(), hard_smp_processor_id());
1059 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(read_apic_id()));
1060 v = apic_read(APIC_LVR);
1061 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1062 ver = GET_APIC_VERSION(v);
1063 maxlvt = lapic_get_maxlvt();
1065 v = apic_read(APIC_TASKPRI);
1066 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1068 v = apic_read(APIC_ARBPRI);
1069 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1070 v & APIC_ARBPRI_MASK);
1071 v = apic_read(APIC_PROCPRI);
1072 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1074 v = apic_read(APIC_EOI);
1075 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1076 v = apic_read(APIC_RRR);
1077 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1078 v = apic_read(APIC_LDR);
1079 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1080 v = apic_read(APIC_DFR);
1081 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1082 v = apic_read(APIC_SPIV);
1083 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1085 printk(KERN_DEBUG "... APIC ISR field:\n");
1086 print_APIC_bitfield(APIC_ISR);
1087 printk(KERN_DEBUG "... APIC TMR field:\n");
1088 print_APIC_bitfield(APIC_TMR);
1089 printk(KERN_DEBUG "... APIC IRR field:\n");
1090 print_APIC_bitfield(APIC_IRR);
1092 v = apic_read(APIC_ESR);
1093 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1095 v = apic_read(APIC_ICR);
1096 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1097 v = apic_read(APIC_ICR2);
1098 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1100 v = apic_read(APIC_LVTT);
1101 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1103 if (maxlvt > 3) { /* PC is LVT#4. */
1104 v = apic_read(APIC_LVTPC);
1105 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1107 v = apic_read(APIC_LVT0);
1108 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1109 v = apic_read(APIC_LVT1);
1110 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1112 if (maxlvt > 2) { /* ERR is LVT#3. */
1113 v = apic_read(APIC_LVTERR);
1114 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1117 v = apic_read(APIC_TMICT);
1118 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1119 v = apic_read(APIC_TMCCT);
1120 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1121 v = apic_read(APIC_TDCR);
1122 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1126 void print_all_local_APICs (void)
1128 on_each_cpu(print_local_APIC, NULL, 1, 1);
1131 void __apicdebuginit print_PIC(void)
1134 unsigned long flags;
1136 if (apic_verbosity == APIC_QUIET)
1139 printk(KERN_DEBUG "\nprinting PIC contents\n");
1141 spin_lock_irqsave(&i8259A_lock, flags);
1143 v = inb(0xa1) << 8 | inb(0x21);
1144 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1146 v = inb(0xa0) << 8 | inb(0x20);
1147 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1151 v = inb(0xa0) << 8 | inb(0x20);
1155 spin_unlock_irqrestore(&i8259A_lock, flags);
1157 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1159 v = inb(0x4d1) << 8 | inb(0x4d0);
1160 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1165 void __init enable_IO_APIC(void)
1167 union IO_APIC_reg_01 reg_01;
1168 int i8259_apic, i8259_pin;
1170 unsigned long flags;
1172 for (i = 0; i < PIN_MAP_SIZE; i++) {
1173 irq_2_pin[i].pin = -1;
1174 irq_2_pin[i].next = 0;
1178 * The number of IO-APIC IRQ registers (== #pins):
1180 for (apic = 0; apic < nr_ioapics; apic++) {
1181 spin_lock_irqsave(&ioapic_lock, flags);
1182 reg_01.raw = io_apic_read(apic, 1);
1183 spin_unlock_irqrestore(&ioapic_lock, flags);
1184 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1186 for(apic = 0; apic < nr_ioapics; apic++) {
1188 /* See if any of the pins is in ExtINT mode */
1189 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1190 struct IO_APIC_route_entry entry;
1191 entry = ioapic_read_entry(apic, pin);
1193 /* If the interrupt line is enabled and in ExtInt mode
1194 * I have found the pin where the i8259 is connected.
1196 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1197 ioapic_i8259.apic = apic;
1198 ioapic_i8259.pin = pin;
1204 /* Look to see what if the MP table has reported the ExtINT */
1205 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1206 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1207 /* Trust the MP table if nothing is setup in the hardware */
1208 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1209 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1210 ioapic_i8259.pin = i8259_pin;
1211 ioapic_i8259.apic = i8259_apic;
1213 /* Complain if the MP table and the hardware disagree */
1214 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1215 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1217 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1221 * Do not trust the IO-APIC being empty at bootup
1227 * Not an __init, needed by the reboot code
1229 void disable_IO_APIC(void)
1232 * Clear the IO-APIC before rebooting:
1237 * If the i8259 is routed through an IOAPIC
1238 * Put that IOAPIC in virtual wire mode
1239 * so legacy interrupts can be delivered.
1241 if (ioapic_i8259.pin != -1) {
1242 struct IO_APIC_route_entry entry;
1244 memset(&entry, 0, sizeof(entry));
1245 entry.mask = 0; /* Enabled */
1246 entry.trigger = 0; /* Edge */
1248 entry.polarity = 0; /* High */
1249 entry.delivery_status = 0;
1250 entry.dest_mode = 0; /* Physical */
1251 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1253 entry.dest = GET_APIC_ID(read_apic_id());
1256 * Add it to the IO-APIC irq-routing table:
1258 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1261 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1265 * There is a nasty bug in some older SMP boards, their mptable lies
1266 * about the timer IRQ. We do the following to work around the situation:
1268 * - timer IRQ defaults to IO-APIC IRQ
1269 * - if this function detects that timer IRQs are defunct, then we fall
1270 * back to ISA timer IRQs
1272 static int __init timer_irq_works(void)
1274 unsigned long t1 = jiffies;
1275 unsigned long flags;
1277 local_save_flags(flags);
1279 /* Let ten ticks pass... */
1280 mdelay((10 * 1000) / HZ);
1281 local_irq_restore(flags);
1284 * Expect a few ticks at least, to be sure some possible
1285 * glue logic does not lock up after one or two first
1286 * ticks in a non-ExtINT mode. Also the local APIC
1287 * might have cached one ExtINT interrupt. Finally, at
1288 * least one tick may be lost due to delays.
1292 if (time_after(jiffies, t1 + 4))
1298 * In the SMP+IOAPIC case it might happen that there are an unspecified
1299 * number of pending IRQ events unhandled. These cases are very rare,
1300 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1301 * better to do it this way as thus we do not have to be aware of
1302 * 'pending' interrupts in the IRQ path, except at this point.
1305 * Edge triggered needs to resend any interrupt
1306 * that was delayed but this is now handled in the device
1311 * Starting up a edge-triggered IO-APIC interrupt is
1312 * nasty - we need to make sure that we get the edge.
1313 * If it is already asserted for some reason, we need
1314 * return 1 to indicate that is was pending.
1316 * This is not complete - we should be able to fake
1317 * an edge even if it isn't on the 8259A...
1320 static unsigned int startup_ioapic_irq(unsigned int irq)
1322 int was_pending = 0;
1323 unsigned long flags;
1325 spin_lock_irqsave(&ioapic_lock, flags);
1327 disable_8259A_irq(irq);
1328 if (i8259A_irq_pending(irq))
1331 __unmask_IO_APIC_irq(irq);
1332 spin_unlock_irqrestore(&ioapic_lock, flags);
1337 static int ioapic_retrigger_irq(unsigned int irq)
1339 struct irq_cfg *cfg = &irq_cfg[irq];
1341 unsigned long flags;
1343 spin_lock_irqsave(&vector_lock, flags);
1344 mask = cpumask_of_cpu(first_cpu(cfg->domain));
1345 send_IPI_mask(mask, cfg->vector);
1346 spin_unlock_irqrestore(&vector_lock, flags);
1352 * Level and edge triggered IO-APIC interrupts need different handling,
1353 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1354 * handled with the level-triggered descriptor, but that one has slightly
1355 * more overhead. Level-triggered interrupts cannot be handled with the
1356 * edge-triggered handler, without risking IRQ storms and other ugly
1361 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1363 unsigned vector, me;
1368 me = smp_processor_id();
1369 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1371 struct irq_desc *desc;
1372 struct irq_cfg *cfg;
1373 irq = __get_cpu_var(vector_irq)[vector];
1377 desc = irq_desc + irq;
1378 cfg = irq_cfg + irq;
1379 spin_lock(&desc->lock);
1380 if (!cfg->move_cleanup_count)
1383 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1386 __get_cpu_var(vector_irq)[vector] = -1;
1387 cfg->move_cleanup_count--;
1389 spin_unlock(&desc->lock);
1395 static void irq_complete_move(unsigned int irq)
1397 struct irq_cfg *cfg = irq_cfg + irq;
1398 unsigned vector, me;
1400 if (likely(!cfg->move_in_progress))
1403 vector = ~get_irq_regs()->orig_ax;
1404 me = smp_processor_id();
1405 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1406 cpumask_t cleanup_mask;
1408 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1409 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1410 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1411 cfg->move_in_progress = 0;
1415 static inline void irq_complete_move(unsigned int irq) {}
1418 static void ack_apic_edge(unsigned int irq)
1420 irq_complete_move(irq);
1421 move_native_irq(irq);
1425 static void ack_apic_level(unsigned int irq)
1427 int do_unmask_irq = 0;
1429 irq_complete_move(irq);
1430 #ifdef CONFIG_GENERIC_PENDING_IRQ
1431 /* If we are moving the irq we need to mask it */
1432 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1434 mask_IO_APIC_irq(irq);
1439 * We must acknowledge the irq before we move it or the acknowledge will
1440 * not propagate properly.
1444 /* Now we can move and renable the irq */
1445 if (unlikely(do_unmask_irq)) {
1446 /* Only migrate the irq if the ack has been received.
1448 * On rare occasions the broadcast level triggered ack gets
1449 * delayed going to ioapics, and if we reprogram the
1450 * vector while Remote IRR is still set the irq will never
1453 * To prevent this scenario we read the Remote IRR bit
1454 * of the ioapic. This has two effects.
1455 * - On any sane system the read of the ioapic will
1456 * flush writes (and acks) going to the ioapic from
1458 * - We get to see if the ACK has actually been delivered.
1460 * Based on failed experiments of reprogramming the
1461 * ioapic entry from outside of irq context starting
1462 * with masking the ioapic entry and then polling until
1463 * Remote IRR was clear before reprogramming the
1464 * ioapic I don't trust the Remote IRR bit to be
1465 * completey accurate.
1467 * However there appears to be no other way to plug
1468 * this race, so if the Remote IRR bit is not
1469 * accurate and is causing problems then it is a hardware bug
1470 * and you can go talk to the chipset vendor about it.
1472 if (!io_apic_level_ack_pending(irq))
1473 move_masked_irq(irq);
1474 unmask_IO_APIC_irq(irq);
1478 static struct irq_chip ioapic_chip __read_mostly = {
1480 .startup = startup_ioapic_irq,
1481 .mask = mask_IO_APIC_irq,
1482 .unmask = unmask_IO_APIC_irq,
1483 .ack = ack_apic_edge,
1484 .eoi = ack_apic_level,
1486 .set_affinity = set_ioapic_affinity_irq,
1488 .retrigger = ioapic_retrigger_irq,
1491 static inline void init_IO_APIC_traps(void)
1496 * NOTE! The local APIC isn't very good at handling
1497 * multiple interrupts at the same interrupt level.
1498 * As the interrupt level is determined by taking the
1499 * vector number and shifting that right by 4, we
1500 * want to spread these out a bit so that they don't
1501 * all fall in the same interrupt level.
1503 * Also, we've got to be careful not to trash gate
1504 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1506 for (irq = 0; irq < NR_IRQS ; irq++) {
1507 if (IO_APIC_IRQ(irq) && !irq_cfg[irq].vector) {
1509 * Hmm.. We don't have an entry for this,
1510 * so default to an old-fashioned 8259
1511 * interrupt if we can..
1514 make_8259A_irq(irq);
1516 /* Strange. Oh, well.. */
1517 irq_desc[irq].chip = &no_irq_chip;
1522 static void enable_lapic_irq (unsigned int irq)
1526 v = apic_read(APIC_LVT0);
1527 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1530 static void disable_lapic_irq (unsigned int irq)
1534 v = apic_read(APIC_LVT0);
1535 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1538 static void ack_lapic_irq (unsigned int irq)
1543 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1545 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1546 .name = "local-APIC",
1547 .typename = "local-APIC-edge",
1548 .startup = NULL, /* startup_irq() not used for IRQ0 */
1549 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1550 .enable = enable_lapic_irq,
1551 .disable = disable_lapic_irq,
1552 .ack = ack_lapic_irq,
1553 .end = end_lapic_irq,
1556 static void __init setup_nmi(void)
1559 * Dirty trick to enable the NMI watchdog ...
1560 * We put the 8259A master into AEOI mode and
1561 * unmask on all local APICs LVT0 as NMI.
1563 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1564 * is from Maciej W. Rozycki - so we do not have to EOI from
1565 * the NMI handler or the timer interrupt.
1567 printk(KERN_INFO "activating NMI Watchdog ...");
1569 enable_NMI_through_LVT0();
1575 * This looks a bit hackish but it's about the only one way of sending
1576 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1577 * not support the ExtINT mode, unfortunately. We need to send these
1578 * cycles as some i82489DX-based boards have glue logic that keeps the
1579 * 8259A interrupt line asserted until INTA. --macro
1581 static inline void __init unlock_ExtINT_logic(void)
1584 struct IO_APIC_route_entry entry0, entry1;
1585 unsigned char save_control, save_freq_select;
1587 pin = find_isa_irq_pin(8, mp_INT);
1588 apic = find_isa_irq_apic(8, mp_INT);
1592 entry0 = ioapic_read_entry(apic, pin);
1594 clear_IO_APIC_pin(apic, pin);
1596 memset(&entry1, 0, sizeof(entry1));
1598 entry1.dest_mode = 0; /* physical delivery */
1599 entry1.mask = 0; /* unmask IRQ now */
1600 entry1.dest = hard_smp_processor_id();
1601 entry1.delivery_mode = dest_ExtINT;
1602 entry1.polarity = entry0.polarity;
1606 ioapic_write_entry(apic, pin, entry1);
1608 save_control = CMOS_READ(RTC_CONTROL);
1609 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1610 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1612 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1617 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1621 CMOS_WRITE(save_control, RTC_CONTROL);
1622 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1623 clear_IO_APIC_pin(apic, pin);
1625 ioapic_write_entry(apic, pin, entry0);
1629 * This code may look a bit paranoid, but it's supposed to cooperate with
1630 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1631 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1632 * fanatically on his truly buggy board.
1634 * FIXME: really need to revamp this for modern platforms only.
1636 static inline void __init check_timer(void)
1638 struct irq_cfg *cfg = irq_cfg + 0;
1639 int apic1, pin1, apic2, pin2;
1640 unsigned long flags;
1642 local_irq_save(flags);
1645 * get/set the timer IRQ vector:
1647 disable_8259A_irq(0);
1648 assign_irq_vector(0, TARGET_CPUS);
1651 * As IRQ0 is to be enabled in the 8259A, the virtual
1652 * wire has to be disabled in the local APIC.
1654 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1657 pin1 = find_isa_irq_pin(0, mp_INT);
1658 apic1 = find_isa_irq_apic(0, mp_INT);
1659 pin2 = ioapic_i8259.pin;
1660 apic2 = ioapic_i8259.apic;
1662 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1663 cfg->vector, apic1, pin1, apic2, pin2);
1667 * Ok, does IRQ0 through the IOAPIC work?
1669 unmask_IO_APIC_irq(0);
1670 if (!no_timer_check && timer_irq_works()) {
1671 nmi_watchdog_default();
1672 if (nmi_watchdog == NMI_IO_APIC) {
1674 enable_8259A_irq(0);
1676 if (disable_timer_pin_1 > 0)
1677 clear_IO_APIC_pin(0, pin1);
1680 clear_IO_APIC_pin(apic1, pin1);
1681 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1682 "connected to IO-APIC\n");
1685 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1686 "through the 8259A ... ");
1688 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1691 * legacy devices should be connected to IO APIC #0
1693 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
1694 enable_8259A_irq(0);
1695 if (timer_irq_works()) {
1696 apic_printk(APIC_VERBOSE," works.\n");
1697 timer_through_8259 = 1;
1698 nmi_watchdog_default();
1699 if (nmi_watchdog == NMI_IO_APIC) {
1700 disable_8259A_irq(0);
1702 enable_8259A_irq(0);
1707 * Cleanup, just in case ...
1709 disable_8259A_irq(0);
1710 clear_IO_APIC_pin(apic2, pin2);
1712 apic_printk(APIC_VERBOSE," failed.\n");
1714 if (nmi_watchdog == NMI_IO_APIC) {
1715 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1719 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1721 irq_desc[0].chip = &lapic_irq_type;
1722 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1723 enable_8259A_irq(0);
1725 if (timer_irq_works()) {
1726 apic_printk(APIC_VERBOSE," works.\n");
1729 disable_8259A_irq(0);
1730 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1731 apic_printk(APIC_VERBOSE," failed.\n");
1733 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1737 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1739 unlock_ExtINT_logic();
1741 if (timer_irq_works()) {
1742 apic_printk(APIC_VERBOSE," works.\n");
1745 apic_printk(APIC_VERBOSE," failed :(.\n");
1746 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1748 local_irq_restore(flags);
1751 static int __init notimercheck(char *s)
1756 __setup("no_timer_check", notimercheck);
1760 * IRQs that are handled by the PIC in the MPS IOAPIC case.
1761 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1762 * Linux doesn't really care, as it's not actually used
1763 * for any interrupt handling anyway.
1765 #define PIC_IRQS (1<<2)
1767 void __init setup_IO_APIC(void)
1771 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
1775 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1777 io_apic_irqs = ~PIC_IRQS;
1779 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1782 setup_IO_APIC_irqs();
1783 init_IO_APIC_traps();
1789 struct sysfs_ioapic_data {
1790 struct sys_device dev;
1791 struct IO_APIC_route_entry entry[0];
1793 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1795 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1797 struct IO_APIC_route_entry *entry;
1798 struct sysfs_ioapic_data *data;
1801 data = container_of(dev, struct sysfs_ioapic_data, dev);
1802 entry = data->entry;
1803 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1804 *entry = ioapic_read_entry(dev->id, i);
1809 static int ioapic_resume(struct sys_device *dev)
1811 struct IO_APIC_route_entry *entry;
1812 struct sysfs_ioapic_data *data;
1813 unsigned long flags;
1814 union IO_APIC_reg_00 reg_00;
1817 data = container_of(dev, struct sysfs_ioapic_data, dev);
1818 entry = data->entry;
1820 spin_lock_irqsave(&ioapic_lock, flags);
1821 reg_00.raw = io_apic_read(dev->id, 0);
1822 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1823 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1824 io_apic_write(dev->id, 0, reg_00.raw);
1826 spin_unlock_irqrestore(&ioapic_lock, flags);
1827 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1828 ioapic_write_entry(dev->id, i, entry[i]);
1833 static struct sysdev_class ioapic_sysdev_class = {
1835 .suspend = ioapic_suspend,
1836 .resume = ioapic_resume,
1839 static int __init ioapic_init_sysfs(void)
1841 struct sys_device * dev;
1844 error = sysdev_class_register(&ioapic_sysdev_class);
1848 for (i = 0; i < nr_ioapics; i++ ) {
1849 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1850 * sizeof(struct IO_APIC_route_entry);
1851 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1852 if (!mp_ioapic_data[i]) {
1853 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1856 dev = &mp_ioapic_data[i]->dev;
1858 dev->cls = &ioapic_sysdev_class;
1859 error = sysdev_register(dev);
1861 kfree(mp_ioapic_data[i]);
1862 mp_ioapic_data[i] = NULL;
1863 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1871 device_initcall(ioapic_init_sysfs);
1874 * Dynamic irq allocate and deallocation
1876 int create_irq(void)
1878 /* Allocate an unused irq */
1881 unsigned long flags;
1884 spin_lock_irqsave(&vector_lock, flags);
1885 for (new = (NR_IRQS - 1); new >= 0; new--) {
1886 if (platform_legacy_irq(new))
1888 if (irq_cfg[new].vector != 0)
1890 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
1894 spin_unlock_irqrestore(&vector_lock, flags);
1897 dynamic_irq_init(irq);
1902 void destroy_irq(unsigned int irq)
1904 unsigned long flags;
1906 dynamic_irq_cleanup(irq);
1908 spin_lock_irqsave(&vector_lock, flags);
1909 __clear_irq_vector(irq);
1910 spin_unlock_irqrestore(&vector_lock, flags);
1914 * MSI message composition
1916 #ifdef CONFIG_PCI_MSI
1917 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1919 struct irq_cfg *cfg = irq_cfg + irq;
1925 err = assign_irq_vector(irq, tmp);
1927 cpus_and(tmp, cfg->domain, tmp);
1928 dest = cpu_mask_to_apicid(tmp);
1930 msg->address_hi = MSI_ADDR_BASE_HI;
1933 ((INT_DEST_MODE == 0) ?
1934 MSI_ADDR_DEST_MODE_PHYSICAL:
1935 MSI_ADDR_DEST_MODE_LOGICAL) |
1936 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1937 MSI_ADDR_REDIRECTION_CPU:
1938 MSI_ADDR_REDIRECTION_LOWPRI) |
1939 MSI_ADDR_DEST_ID(dest);
1942 MSI_DATA_TRIGGER_EDGE |
1943 MSI_DATA_LEVEL_ASSERT |
1944 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1945 MSI_DATA_DELIVERY_FIXED:
1946 MSI_DATA_DELIVERY_LOWPRI) |
1947 MSI_DATA_VECTOR(cfg->vector);
1953 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1955 struct irq_cfg *cfg = irq_cfg + irq;
1960 cpus_and(tmp, mask, cpu_online_map);
1961 if (cpus_empty(tmp))
1964 if (assign_irq_vector(irq, mask))
1967 cpus_and(tmp, cfg->domain, mask);
1968 dest = cpu_mask_to_apicid(tmp);
1970 read_msi_msg(irq, &msg);
1972 msg.data &= ~MSI_DATA_VECTOR_MASK;
1973 msg.data |= MSI_DATA_VECTOR(cfg->vector);
1974 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1975 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1977 write_msi_msg(irq, &msg);
1978 irq_desc[irq].affinity = mask;
1980 #endif /* CONFIG_SMP */
1983 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1984 * which implement the MSI or MSI-X Capability Structure.
1986 static struct irq_chip msi_chip = {
1988 .unmask = unmask_msi_irq,
1989 .mask = mask_msi_irq,
1990 .ack = ack_apic_edge,
1992 .set_affinity = set_msi_irq_affinity,
1994 .retrigger = ioapic_retrigger_irq,
1997 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2005 ret = msi_compose_msg(dev, irq, &msg);
2011 set_irq_msi(irq, desc);
2012 write_msi_msg(irq, &msg);
2014 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2019 void arch_teardown_msi_irq(unsigned int irq)
2026 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2028 struct irq_cfg *cfg = irq_cfg + irq;
2033 cpus_and(tmp, mask, cpu_online_map);
2034 if (cpus_empty(tmp))
2037 if (assign_irq_vector(irq, mask))
2040 cpus_and(tmp, cfg->domain, mask);
2041 dest = cpu_mask_to_apicid(tmp);
2043 dmar_msi_read(irq, &msg);
2045 msg.data &= ~MSI_DATA_VECTOR_MASK;
2046 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2047 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2048 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2050 dmar_msi_write(irq, &msg);
2051 irq_desc[irq].affinity = mask;
2053 #endif /* CONFIG_SMP */
2055 struct irq_chip dmar_msi_type = {
2057 .unmask = dmar_msi_unmask,
2058 .mask = dmar_msi_mask,
2059 .ack = ack_apic_edge,
2061 .set_affinity = dmar_msi_set_affinity,
2063 .retrigger = ioapic_retrigger_irq,
2066 int arch_setup_dmar_msi(unsigned int irq)
2071 ret = msi_compose_msg(NULL, irq, &msg);
2074 dmar_msi_write(irq, &msg);
2075 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2081 #endif /* CONFIG_PCI_MSI */
2083 * Hypertransport interrupt support
2085 #ifdef CONFIG_HT_IRQ
2089 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2091 struct ht_irq_msg msg;
2092 fetch_ht_irq_msg(irq, &msg);
2094 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2095 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2097 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2098 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2100 write_ht_irq_msg(irq, &msg);
2103 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2105 struct irq_cfg *cfg = irq_cfg + irq;
2109 cpus_and(tmp, mask, cpu_online_map);
2110 if (cpus_empty(tmp))
2113 if (assign_irq_vector(irq, mask))
2116 cpus_and(tmp, cfg->domain, mask);
2117 dest = cpu_mask_to_apicid(tmp);
2119 target_ht_irq(irq, dest, cfg->vector);
2120 irq_desc[irq].affinity = mask;
2124 static struct irq_chip ht_irq_chip = {
2126 .mask = mask_ht_irq,
2127 .unmask = unmask_ht_irq,
2128 .ack = ack_apic_edge,
2130 .set_affinity = set_ht_irq_affinity,
2132 .retrigger = ioapic_retrigger_irq,
2135 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2137 struct irq_cfg *cfg = irq_cfg + irq;
2142 err = assign_irq_vector(irq, tmp);
2144 struct ht_irq_msg msg;
2147 cpus_and(tmp, cfg->domain, tmp);
2148 dest = cpu_mask_to_apicid(tmp);
2150 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2154 HT_IRQ_LOW_DEST_ID(dest) |
2155 HT_IRQ_LOW_VECTOR(cfg->vector) |
2156 ((INT_DEST_MODE == 0) ?
2157 HT_IRQ_LOW_DM_PHYSICAL :
2158 HT_IRQ_LOW_DM_LOGICAL) |
2159 HT_IRQ_LOW_RQEOI_EDGE |
2160 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2161 HT_IRQ_LOW_MT_FIXED :
2162 HT_IRQ_LOW_MT_ARBITRATED) |
2163 HT_IRQ_LOW_IRQ_MASKED;
2165 write_ht_irq_msg(irq, &msg);
2167 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2168 handle_edge_irq, "edge");
2172 #endif /* CONFIG_HT_IRQ */
2174 /* --------------------------------------------------------------------------
2175 ACPI-based IOAPIC Configuration
2176 -------------------------------------------------------------------------- */
2180 #define IO_APIC_MAX_ID 0xFE
2182 int __init io_apic_get_redir_entries (int ioapic)
2184 union IO_APIC_reg_01 reg_01;
2185 unsigned long flags;
2187 spin_lock_irqsave(&ioapic_lock, flags);
2188 reg_01.raw = io_apic_read(ioapic, 1);
2189 spin_unlock_irqrestore(&ioapic_lock, flags);
2191 return reg_01.bits.entries;
2195 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2197 if (!IO_APIC_IRQ(irq)) {
2198 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2204 * IRQs < 16 are already in the irq_2_pin[] map
2207 add_pin_to_irq(irq, ioapic, pin);
2209 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2215 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2219 if (skip_ioapic_setup)
2222 for (i = 0; i < mp_irq_entries; i++)
2223 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2224 mp_irqs[i].mpc_srcbusirq == bus_irq)
2226 if (i >= mp_irq_entries)
2229 *trigger = irq_trigger(i);
2230 *polarity = irq_polarity(i);
2234 #endif /* CONFIG_ACPI */
2237 * This function currently is only a helper for the i386 smp boot process where
2238 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2239 * so mask in all cases should simply be TARGET_CPUS
2242 void __init setup_ioapic_dest(void)
2244 int pin, ioapic, irq, irq_entry;
2246 if (skip_ioapic_setup == 1)
2249 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2250 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2251 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2252 if (irq_entry == -1)
2254 irq = pin_2_irq(irq_entry, ioapic, pin);
2256 /* setup_IO_APIC_irqs could fail to get vector for some device
2257 * when you have too many devices, because at that time only boot
2260 if (!irq_cfg[irq].vector)
2261 setup_IO_APIC_irq(ioapic, pin, irq,
2262 irq_trigger(irq_entry),
2263 irq_polarity(irq_entry));
2265 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2272 #define IOAPIC_RESOURCE_NAME_SIZE 11
2274 static struct resource *ioapic_resources;
2276 static struct resource * __init ioapic_setup_resources(void)
2279 struct resource *res;
2283 if (nr_ioapics <= 0)
2286 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2289 mem = alloc_bootmem(n);
2293 mem += sizeof(struct resource) * nr_ioapics;
2295 for (i = 0; i < nr_ioapics; i++) {
2297 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2298 sprintf(mem, "IOAPIC %u", i);
2299 mem += IOAPIC_RESOURCE_NAME_SIZE;
2303 ioapic_resources = res;
2308 void __init ioapic_init_mappings(void)
2310 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2311 struct resource *ioapic_res;
2314 ioapic_res = ioapic_setup_resources();
2315 for (i = 0; i < nr_ioapics; i++) {
2316 if (smp_found_config) {
2317 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
2319 ioapic_phys = (unsigned long)
2320 alloc_bootmem_pages(PAGE_SIZE);
2321 ioapic_phys = __pa(ioapic_phys);
2323 set_fixmap_nocache(idx, ioapic_phys);
2324 apic_printk(APIC_VERBOSE,
2325 "mapped IOAPIC to %016lx (%016lx)\n",
2326 __fix_to_virt(idx), ioapic_phys);
2329 if (ioapic_res != NULL) {
2330 ioapic_res->start = ioapic_phys;
2331 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
2337 static int __init ioapic_insert_resources(void)
2340 struct resource *r = ioapic_resources;
2344 "IO APIC resources could be not be allocated.\n");
2348 for (i = 0; i < nr_ioapics; i++) {
2349 insert_resource(&iomem_resource, r);
2356 /* Insert the IO APIC resources after PCI initialization has occured to handle
2357 * IO APICS that are mapped in on a BAR in PCI space. */
2358 late_initcall(ioapic_insert_resources);