arch/x86/kernel/genx2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/threads.h>
  13 #include <linux/cpu.h>
  14 #include <linux/cpumask.h>
  15 #include <linux/string.h>
  16 #include <linux/ctype.h>
  17 #include <linux/init.h>
  18 #include <linux/sched.h>
  19 #include <linux/bootmem.h>
  20 #include <linux/module.h>
  21 #include <linux/hardirq.h>
  22 #include <linux/timer.h>
  23 #include <linux/proc_fs.h>
  24 #include <asm/current.h>
  25 #include <asm/smp.h>
  26 #include <asm/ipi.h>
  27 #include <asm/genapic.h>
  28 #include <asm/pgtable.h>
  29 #include <asm/uv/uv_mmrs.h>
  30 #include <asm/uv/uv_hub.h>
  31 #include <asm/uv/bios.h>
  32
  33 DEFINE_PER_CPU(int, x2apic_extra_bits);
  34
  35 static enum uv_system_type uv_system_type;
  36
  37 static int uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
  38 {
  39         if (!strcmp(oem_id, "SGI")) {
  40                 if (!strcmp(oem_table_id, "UVL"))
  41                         uv_system_type = UV_LEGACY_APIC;
  42                 else if (!strcmp(oem_table_id, "UVX"))
  43                         uv_system_type = UV_X2APIC;
  44                 else if (!strcmp(oem_table_id, "UVH")) {
  45                         uv_system_type = UV_NON_UNIQUE_APIC;
  46                         return 1;
  47                 }
  48         }
  49         return 0;
  50 }
  51
  52 enum uv_system_type get_uv_system_type(void)
  53 {
  54         return uv_system_type;
  55 }
  56
  57 int is_uv_system(void)
  58 {
  59         return uv_system_type != UV_NONE;
  60 }
  61 EXPORT_SYMBOL_GPL(is_uv_system);
  62
  63 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
  64 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
  65
  66 struct uv_blade_info *uv_blade_info;
  67 EXPORT_SYMBOL_GPL(uv_blade_info);
  68
  69 short *uv_node_to_blade;
  70 EXPORT_SYMBOL_GPL(uv_node_to_blade);
  71
  72 short *uv_cpu_to_blade;
  73 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
  74
  75 short uv_possible_blades;
  76 EXPORT_SYMBOL_GPL(uv_possible_blades);
  77
  78 unsigned long sn_rtc_cycles_per_second;
  79 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
  80
  81 /* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */
  82
  83 static cpumask_t uv_target_cpus(void)
  84 {
  85         return cpumask_of_cpu(0);
  86 }
  87
  88 static cpumask_t uv_vector_allocation_domain(int cpu)
  89 {
  90         cpumask_t domain = CPU_MASK_NONE;
  91         cpu_set(cpu, domain);
  92         return domain;
  93 }
  94
  95 int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
  96 {
  97         unsigned long val;
  98         int pnode;
  99
 100         pnode = uv_apicid_to_pnode(phys_apicid);
 101         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 102             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 103             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 104             APIC_DM_INIT;
 105         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 106         mdelay(10);
 107
 108         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 109             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 110             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 111             APIC_DM_STARTUP;
 112         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 113         return 0;
 114 }
 115
 116 static void uv_send_IPI_one(int cpu, int vector)
 117 {
 118         unsigned long val, apicid, lapicid;
 119         int pnode;
 120
 121         apicid = per_cpu(x86_cpu_to_apicid, cpu);
 122         lapicid = apicid & 0x3f;                /* ZZZ macro needed */
 123         pnode = uv_apicid_to_pnode(apicid);
 124         val =
 125             (1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
 126                                               UVH_IPI_INT_APIC_ID_SHFT) |
 127             (vector << UVH_IPI_INT_VECTOR_SHFT);
 128         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 129 }
 130
 131 static void uv_send_IPI_mask(cpumask_t mask, int vector)
 132 {
 133         unsigned int cpu;
 134
 135         for_each_possible_cpu(cpu)
 136                 if (cpu_isset(cpu, mask))
 137                         uv_send_IPI_one(cpu, vector);
 138 }
 139
 140 static void uv_send_IPI_allbutself(int vector)
 141 {
 142         cpumask_t mask = cpu_online_map;
 143
 144         cpu_clear(smp_processor_id(), mask);
 145
 146         if (!cpus_empty(mask))
 147                 uv_send_IPI_mask(mask, vector);
 148 }
 149
 150 static void uv_send_IPI_all(int vector)
 151 {
 152         uv_send_IPI_mask(cpu_online_map, vector);
 153 }
 154
 155 static int uv_apic_id_registered(void)
 156 {
 157         return 1;
 158 }
 159
 160 static void uv_init_apic_ldr(void)
 161 {
 162 }
 163
 164 static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask)
 165 {
 166         int cpu;
 167
 168         /*
 169          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 170          * May as well be the first.
 171          */
 172         cpu = first_cpu(cpumask);
 173         if ((unsigned)cpu < nr_cpu_ids)
 174                 return per_cpu(x86_cpu_to_apicid, cpu);
 175         else
 176                 return BAD_APICID;
 177 }
 178
 179 static unsigned int get_apic_id(unsigned long x)
 180 {
 181         unsigned int id;
 182
 183         WARN_ON(preemptible() && num_online_cpus() > 1);
 184         id = x | __get_cpu_var(x2apic_extra_bits);
 185
 186         return id;
 187 }
 188
 189 static unsigned long set_apic_id(unsigned int id)
 190 {
 191         unsigned long x;
 192
 193         /* maskout x2apic_extra_bits ? */
 194         x = id;
 195         return x;
 196 }
 197
 198 static unsigned int uv_read_apic_id(void)
 199 {
 200
 201         return get_apic_id(apic_read(APIC_ID));
 202 }
 203
 204 static unsigned int phys_pkg_id(int index_msb)
 205 {
 206         return uv_read_apic_id() >> index_msb;
 207 }
 208
 209 static void uv_send_IPI_self(int vector)
 210 {
 211         apic_write(APIC_SELF_IPI, vector);
 212 }
 213
 214 struct genapic apic_x2apic_uv_x = {
 215         .name = "UV large system",
 216         .acpi_madt_oem_check = uv_acpi_madt_oem_check,
 217         .int_delivery_mode = dest_Fixed,
 218         .int_dest_mode = (APIC_DEST_PHYSICAL != 0),
 219         .target_cpus = uv_target_cpus,
 220         .vector_allocation_domain = uv_vector_allocation_domain,
 221         .apic_id_registered = uv_apic_id_registered,
 222         .init_apic_ldr = uv_init_apic_ldr,
 223         .send_IPI_all = uv_send_IPI_all,
 224         .send_IPI_allbutself = uv_send_IPI_allbutself,
 225         .send_IPI_mask = uv_send_IPI_mask,
 226         .send_IPI_self = uv_send_IPI_self,
 227         .cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
 228         .phys_pkg_id = phys_pkg_id,
 229         .get_apic_id = get_apic_id,
 230         .set_apic_id = set_apic_id,
 231         .apic_id_mask = (0xFFFFFFFFu),
 232 };
 233
 234 static __cpuinit void set_x2apic_extra_bits(int pnode)
 235 {
 236         __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
 237 }
 238
 239 /*
 240  * Called on boot cpu.
 241  */
 242 static __init int boot_pnode_to_blade(int pnode)
 243 {
 244         int blade;
 245
 246         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 247                 if (pnode == uv_blade_info[blade].pnode)
 248                         return blade;
 249         BUG();
 250 }
 251
 252 struct redir_addr {
 253         unsigned long redirect;
 254         unsigned long alias;
 255 };
 256
 257 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 258
 259 static __initdata struct redir_addr redir_addrs[] = {
 260         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
 261         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
 262         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
 263 };
 264
 265 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 266 {
 267         union uvh_si_alias0_overlay_config_u alias;
 268         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 269         int i;
 270
 271         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
 272                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
 273                 if (alias.s.base == 0) {
 274                         *size = (1UL << alias.s.m_alias);
 275                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
 276                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 277                         return;
 278                 }
 279         }
 280         BUG();
 281 }
 282
 283 static __init void map_low_mmrs(void)
 284 {
 285         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 286         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 287 }
 288
 289 enum map_type {map_wb, map_uc};
 290
 291 static __init void map_high(char *id, unsigned long base, int shift,
 292                             int max_pnode, enum map_type map_type)
 293 {
 294         unsigned long bytes, paddr;
 295
 296         paddr = base << shift;
 297         bytes = (1UL << shift) * (max_pnode + 1);
 298         printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
 299                                                 paddr + bytes);
 300         if (map_type == map_uc)
 301                 init_extra_mapping_uc(paddr, bytes);
 302         else
 303                 init_extra_mapping_wb(paddr, bytes);
 304
 305 }
 306 static __init void map_gru_high(int max_pnode)
 307 {
 308         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 309         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 310
 311         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 312         if (gru.s.enable)
 313                 map_high("GRU", gru.s.base, shift, max_pnode, map_wb);
 314 }
 315
 316 static __init void map_config_high(int max_pnode)
 317 {
 318         union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
 319         int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
 320
 321         cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
 322         if (cfg.s.enable)
 323                 map_high("CONFIG", cfg.s.base, shift, max_pnode, map_uc);
 324 }
 325
 326 static __init void map_mmr_high(int max_pnode)
 327 {
 328         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 329         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 330
 331         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 332         if (mmr.s.enable)
 333                 map_high("MMR", mmr.s.base, shift, max_pnode, map_uc);
 334 }
 335
 336 static __init void map_mmioh_high(int max_pnode)
 337 {
 338         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 339         int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 340
 341         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
 342         if (mmioh.s.enable)
 343                 map_high("MMIOH", mmioh.s.base, shift, max_pnode, map_uc);
 344 }
 345
 346 static __init void uv_rtc_init(void)
 347 {
 348         long status;
 349         u64 ticks_per_sec;
 350
 351         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
 352                                         &ticks_per_sec);
 353         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
 354                 printk(KERN_WARNING
 355                         "unable to determine platform RTC clock frequency, "
 356                         "guessing.\n");
 357                 /* BIOS gives wrong value for clock freq. so guess */
 358                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 359         } else
 360                 sn_rtc_cycles_per_second = ticks_per_sec;
 361 }
 362
 363 /*
 364  * percpu heartbeat timer
 365  */
 366 static void uv_heartbeat(unsigned long ignored)
 367 {
 368         struct timer_list *timer = &uv_hub_info->scir.timer;
 369         unsigned char bits = uv_hub_info->scir.state;
 370
 371         /* flip heartbeat bit */
 372         bits ^= SCIR_CPU_HEARTBEAT;
 373
 374         /* is this cpu idle? */
 375         if (idle_cpu(raw_smp_processor_id()))
 376                 bits &= ~SCIR_CPU_ACTIVITY;
 377         else
 378                 bits |= SCIR_CPU_ACTIVITY;
 379
 380         /* update system controller interface reg */
 381         uv_set_scir_bits(bits);
 382
 383         /* enable next timer period */
 384         mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL);
 385 }
 386
 387 static void __cpuinit uv_heartbeat_enable(int cpu)
 388 {
 389         if (!uv_cpu_hub_info(cpu)->scir.enabled) {
 390                 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
 391
 392                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
 393                 setup_timer(timer, uv_heartbeat, cpu);
 394                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
 395                 add_timer_on(timer, cpu);
 396                 uv_cpu_hub_info(cpu)->scir.enabled = 1;
 397         }
 398
 399         /* check boot cpu */
 400         if (!uv_cpu_hub_info(0)->scir.enabled)
 401                 uv_heartbeat_enable(0);
 402 }
 403
 404 static void __cpuinit uv_heartbeat_disable(int cpu)
 405 {
 406         if (uv_cpu_hub_info(cpu)->scir.enabled) {
 407                 uv_cpu_hub_info(cpu)->scir.enabled = 0;
 408                 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
 409         }
 410         uv_set_cpu_scir_bits(cpu, 0xff);
 411 }
 412
 413 #ifdef CONFIG_HOTPLUG_CPU
 414 /*
 415  * cpu hotplug notifier
 416  */
 417 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
 418                                        unsigned long action, void *hcpu)
 419 {
 420         long cpu = (long)hcpu;
 421
 422         switch (action) {
 423         case CPU_ONLINE:
 424                 uv_heartbeat_enable(cpu);
 425                 break;
 426         case CPU_DOWN_PREPARE:
 427                 uv_heartbeat_disable(cpu);
 428                 break;
 429         default:
 430                 break;
 431         }
 432         return NOTIFY_OK;
 433 }
 434
 435 static __init void uv_scir_register_cpu_notifier(void)
 436 {
 437         hotcpu_notifier(uv_scir_cpu_notify, 0);
 438 }
 439
 440 #else /* !CONFIG_HOTPLUG_CPU */
 441
 442 static __init void uv_scir_register_cpu_notifier(void)
 443 {
 444 }
 445
 446 static __init int uv_init_heartbeat(void)
 447 {
 448         int cpu;
 449
 450         if (is_uv_system())
 451                 for_each_online_cpu(cpu)
 452                         uv_heartbeat_enable(cpu);
 453         return 0;
 454 }
 455
 456 late_initcall(uv_init_heartbeat);
 457
 458 #endif /* !CONFIG_HOTPLUG_CPU */
 459
 460 /*
 461  * Called on each cpu to initialize the per_cpu UV data area.
 462  *      ZZZ hotplug not supported yet
 463  */
 464 void __cpuinit uv_cpu_init(void)
 465 {
 466         /* CPU 0 initilization will be done via uv_system_init. */
 467         if (!uv_blade_info)
 468                 return;
 469
 470         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 471
 472         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
 473                 set_x2apic_extra_bits(uv_hub_info->pnode);
 474 }
 475
 476
 477 void __init uv_system_init(void)
 478 {
 479         union uvh_si_addr_map_config_u m_n_config;
 480         union uvh_node_id_u node_id;
 481         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
 482         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
 483         int max_pnode = 0;
 484         unsigned long mmr_base, present;
 485
 486         map_low_mmrs();
 487
 488         m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
 489         m_val = m_n_config.s.m_skt;
 490         n_val = m_n_config.s.n_skt;
 491         mmr_base =
 492             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
 493             ~UV_MMR_ENABLE;
 494         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
 495
 496         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
 497                 uv_possible_blades +=
 498                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
 499         printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
 500
 501         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
 502         uv_blade_info = alloc_bootmem_pages(bytes);
 503
 504         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
 505
 506         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
 507         uv_node_to_blade = alloc_bootmem_pages(bytes);
 508         memset(uv_node_to_blade, 255, bytes);
 509
 510         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
 511         uv_cpu_to_blade = alloc_bootmem_pages(bytes);
 512         memset(uv_cpu_to_blade, 255, bytes);
 513
 514         blade = 0;
 515         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
 516                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
 517                 for (j = 0; j < 64; j++) {
 518                         if (!test_bit(j, &present))
 519                                 continue;
 520                         uv_blade_info[blade].pnode = (i * 64 + j);
 521                         uv_blade_info[blade].nr_possible_cpus = 0;
 522                         uv_blade_info[blade].nr_online_cpus = 0;
 523                         blade++;
 524                 }
 525         }
 526
 527         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
 528         gnode_upper = (((unsigned long)node_id.s.node_id) &
 529                        ~((1 << n_val) - 1)) << m_val;
 530
 531         uv_bios_init();
 532         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id,
 533                             &sn_coherency_id, &sn_region_size);
 534         uv_rtc_init();
 535
 536         for_each_present_cpu(cpu) {
 537                 nid = cpu_to_node(cpu);
 538                 pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
 539                 blade = boot_pnode_to_blade(pnode);
 540                 lcpu = uv_blade_info[blade].nr_possible_cpus;
 541                 uv_blade_info[blade].nr_possible_cpus++;
 542
 543                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
 544                 uv_cpu_hub_info(cpu)->lowmem_remap_top =
 545                                         lowmem_redir_base + lowmem_redir_size;
 546                 uv_cpu_hub_info(cpu)->m_val = m_val;
 547                 uv_cpu_hub_info(cpu)->n_val = m_val;
 548                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
 549                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
 550                 uv_cpu_hub_info(cpu)->pnode = pnode;
 551                 uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
 552                 uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
 553                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
 554                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
 555                 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
 556                 uv_cpu_hub_info(cpu)->scir.offset = SCIR_LOCAL_MMR_BASE + lcpu;
 557                 uv_node_to_blade[nid] = blade;
 558                 uv_cpu_to_blade[cpu] = blade;
 559                 max_pnode = max(pnode, max_pnode);
 560
 561                 printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
 562                         "lcpu %d, blade %d\n",
 563                         cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
 564                         lcpu, blade);
 565         }
 566
 567         map_gru_high(max_pnode);
 568         map_mmr_high(max_pnode);
 569         map_config_high(max_pnode);
 570         map_mmioh_high(max_pnode);
 571
 572         uv_cpu_init();
 573         uv_scir_register_cpu_notifier();
 574         proc_mkdir("sgi_uv", NULL);
 575 }