arch/x86/kernel/cpu/perf_event_intel.c

   1 /*
   2  * Per core/cpu state
   3  *
   4  * Used to coordinate shared registers between HT threads or
   5  * among events on a single PMU.
   6  */
   7
   8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   9
  10 #include <linux/stddef.h>
  11 #include <linux/types.h>
  12 #include <linux/init.h>
  13 #include <linux/slab.h>
  14 #include <linux/export.h>
  15
  16 #include <asm/cpufeature.h>
  17 #include <asm/hardirq.h>
  18 #include <asm/apic.h>
  19
  20 #include "perf_event.h"
  21
  22 /*
  23  * Intel PerfMon, used on Core and later.
  24  */
  25 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
  26 {
  27         [PERF_COUNT_HW_CPU_CYCLES]              = 0x003c,
  28         [PERF_COUNT_HW_INSTRUCTIONS]            = 0x00c0,
  29         [PERF_COUNT_HW_CACHE_REFERENCES]        = 0x4f2e,
  30         [PERF_COUNT_HW_CACHE_MISSES]            = 0x412e,
  31         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x00c4,
  32         [PERF_COUNT_HW_BRANCH_MISSES]           = 0x00c5,
  33         [PERF_COUNT_HW_BUS_CYCLES]              = 0x013c,
  34         [PERF_COUNT_HW_REF_CPU_CYCLES]          = 0x0300, /* pseudo-encoding */
  35 };
  36
  37 static struct event_constraint intel_core_event_constraints[] __read_mostly =
  38 {
  39         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  40         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  41         INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  42         INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  43         INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  44         INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
  45         EVENT_CONSTRAINT_END
  46 };
  47
  48 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
  49 {
  50         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  51         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  52         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
  53         INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
  54         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  55         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  56         INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  57         INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  58         INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
  59         INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  60         INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
  61         INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
  62         INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
  63         EVENT_CONSTRAINT_END
  64 };
  65
  66 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
  67 {
  68         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  69         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  70         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
  71         INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
  72         INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
  73         INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
  74         INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
  75         INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
  76         INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
  77         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
  78         INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
  79         EVENT_CONSTRAINT_END
  80 };
  81
  82 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
  83 {
  84         INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
  85         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
  86         EVENT_EXTRA_END
  87 };
  88
  89 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
  90 {
  91         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  92         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  93         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
  94         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
  95         INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
  96         INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
  97         INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
  98         EVENT_CONSTRAINT_END
  99 };
 100
 101 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
 102 {
 103         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 104         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 105         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 106         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
 107         INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
 108         INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 109         INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 110         INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
 111         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 112         INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
 113         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
 114         INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 115         EVENT_CONSTRAINT_END
 116 };
 117
 118 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
 119 {
 120         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 121         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 122         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 123         INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
 124         INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
 125         INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
 126         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
 127         INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
 128         INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
 129         INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 130         INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 131         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 132         /*
 133          * Errata BV98 -- MEM_*_RETIRED events can leak between counters of SMT
 134          * siblings; disable these events because they can corrupt unrelated
 135          * counters.
 136          */
 137         INTEL_EVENT_CONSTRAINT(0xd0, 0x0), /* MEM_UOPS_RETIRED.* */
 138         INTEL_EVENT_CONSTRAINT(0xd1, 0x0), /* MEM_LOAD_UOPS_RETIRED.* */
 139         INTEL_EVENT_CONSTRAINT(0xd2, 0x0), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 140         INTEL_EVENT_CONSTRAINT(0xd3, 0x0), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 141         EVENT_CONSTRAINT_END
 142 };
 143
 144 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
 145 {
 146         INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
 147         INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
 148         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
 149         EVENT_EXTRA_END
 150 };
 151
 152 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
 153 {
 154         EVENT_CONSTRAINT_END
 155 };
 156
 157 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
 158 {
 159         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 160         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 161         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 162         EVENT_CONSTRAINT_END
 163 };
 164
 165 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
 166         INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
 167         INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
 168         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 169         EVENT_EXTRA_END
 170 };
 171
 172 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
 173         INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
 174         INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
 175         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 176         EVENT_EXTRA_END
 177 };
 178
 179 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
 180 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
 181 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
 182
 183 struct attribute *nhm_events_attrs[] = {
 184         EVENT_PTR(mem_ld_nhm),
 185         NULL,
 186 };
 187
 188 struct attribute *snb_events_attrs[] = {
 189         EVENT_PTR(mem_ld_snb),
 190         EVENT_PTR(mem_st_snb),
 191         NULL,
 192 };
 193
 194 static struct event_constraint intel_hsw_event_constraints[] = {
 195         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 196         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 197         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 198         INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.* */
 199         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 200         INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
 201         /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 202         INTEL_EVENT_CONSTRAINT(0x08a3, 0x4),
 203         /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 204         INTEL_EVENT_CONSTRAINT(0x0ca3, 0x4),
 205         /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
 206         INTEL_EVENT_CONSTRAINT(0x04a3, 0xf),
 207         EVENT_CONSTRAINT_END
 208 };
 209
 210 static u64 intel_pmu_event_map(int hw_event)
 211 {
 212         return intel_perfmon_event_map[hw_event];
 213 }
 214
 215 #define SNB_DMND_DATA_RD        (1ULL << 0)
 216 #define SNB_DMND_RFO            (1ULL << 1)
 217 #define SNB_DMND_IFETCH         (1ULL << 2)
 218 #define SNB_DMND_WB             (1ULL << 3)
 219 #define SNB_PF_DATA_RD          (1ULL << 4)
 220 #define SNB_PF_RFO              (1ULL << 5)
 221 #define SNB_PF_IFETCH           (1ULL << 6)
 222 #define SNB_LLC_DATA_RD         (1ULL << 7)
 223 #define SNB_LLC_RFO             (1ULL << 8)
 224 #define SNB_LLC_IFETCH          (1ULL << 9)
 225 #define SNB_BUS_LOCKS           (1ULL << 10)
 226 #define SNB_STRM_ST             (1ULL << 11)
 227 #define SNB_OTHER               (1ULL << 15)
 228 #define SNB_RESP_ANY            (1ULL << 16)
 229 #define SNB_NO_SUPP             (1ULL << 17)
 230 #define SNB_LLC_HITM            (1ULL << 18)
 231 #define SNB_LLC_HITE            (1ULL << 19)
 232 #define SNB_LLC_HITS            (1ULL << 20)
 233 #define SNB_LLC_HITF            (1ULL << 21)
 234 #define SNB_LOCAL               (1ULL << 22)
 235 #define SNB_REMOTE              (0xffULL << 23)
 236 #define SNB_SNP_NONE            (1ULL << 31)
 237 #define SNB_SNP_NOT_NEEDED      (1ULL << 32)
 238 #define SNB_SNP_MISS            (1ULL << 33)
 239 #define SNB_NO_FWD              (1ULL << 34)
 240 #define SNB_SNP_FWD             (1ULL << 35)
 241 #define SNB_HITM                (1ULL << 36)
 242 #define SNB_NON_DRAM            (1ULL << 37)
 243
 244 #define SNB_DMND_READ           (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
 245 #define SNB_DMND_WRITE          (SNB_DMND_RFO|SNB_LLC_RFO)
 246 #define SNB_DMND_PREFETCH       (SNB_PF_DATA_RD|SNB_PF_RFO)
 247
 248 #define SNB_SNP_ANY             (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
 249                                  SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
 250                                  SNB_HITM)
 251
 252 #define SNB_DRAM_ANY            (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
 253 #define SNB_DRAM_REMOTE         (SNB_REMOTE|SNB_SNP_ANY)
 254
 255 #define SNB_L3_ACCESS           SNB_RESP_ANY
 256 #define SNB_L3_MISS             (SNB_DRAM_ANY|SNB_NON_DRAM)
 257
 258 static __initconst const u64 snb_hw_cache_extra_regs
 259                                 [PERF_COUNT_HW_CACHE_MAX]
 260                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 261                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 262 {
 263  [ C(LL  ) ] = {
 264         [ C(OP_READ) ] = {
 265                 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
 266                 [ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_L3_MISS,
 267         },
 268         [ C(OP_WRITE) ] = {
 269                 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
 270                 [ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_L3_MISS,
 271         },
 272         [ C(OP_PREFETCH) ] = {
 273                 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
 274                 [ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
 275         },
 276  },
 277  [ C(NODE) ] = {
 278         [ C(OP_READ) ] = {
 279                 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
 280                 [ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
 281         },
 282         [ C(OP_WRITE) ] = {
 283                 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
 284                 [ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
 285         },
 286         [ C(OP_PREFETCH) ] = {
 287                 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
 288                 [ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
 289         },
 290  },
 291 };
 292
 293 static __initconst const u64 snb_hw_cache_event_ids
 294                                 [PERF_COUNT_HW_CACHE_MAX]
 295                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 296                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 297 {
 298  [ C(L1D) ] = {
 299         [ C(OP_READ) ] = {
 300                 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS        */
 301                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPLACEMENT              */
 302         },
 303         [ C(OP_WRITE) ] = {
 304                 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES       */
 305                 [ C(RESULT_MISS)   ] = 0x0851, /* L1D.ALL_M_REPLACEMENT        */
 306         },
 307         [ C(OP_PREFETCH) ] = {
 308                 [ C(RESULT_ACCESS) ] = 0x0,
 309                 [ C(RESULT_MISS)   ] = 0x024e, /* HW_PRE_REQ.DL1_MISS          */
 310         },
 311  },
 312  [ C(L1I ) ] = {
 313         [ C(OP_READ) ] = {
 314                 [ C(RESULT_ACCESS) ] = 0x0,
 315                 [ C(RESULT_MISS)   ] = 0x0280, /* ICACHE.MISSES */
 316         },
 317         [ C(OP_WRITE) ] = {
 318                 [ C(RESULT_ACCESS) ] = -1,
 319                 [ C(RESULT_MISS)   ] = -1,
 320         },
 321         [ C(OP_PREFETCH) ] = {
 322                 [ C(RESULT_ACCESS) ] = 0x0,
 323                 [ C(RESULT_MISS)   ] = 0x0,
 324         },
 325  },
 326  [ C(LL  ) ] = {
 327         [ C(OP_READ) ] = {
 328                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
 329                 [ C(RESULT_ACCESS) ] = 0x01b7,
 330                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
 331                 [ C(RESULT_MISS)   ] = 0x01b7,
 332         },
 333         [ C(OP_WRITE) ] = {
 334                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
 335                 [ C(RESULT_ACCESS) ] = 0x01b7,
 336                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
 337                 [ C(RESULT_MISS)   ] = 0x01b7,
 338         },
 339         [ C(OP_PREFETCH) ] = {
 340                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
 341                 [ C(RESULT_ACCESS) ] = 0x01b7,
 342                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
 343                 [ C(RESULT_MISS)   ] = 0x01b7,
 344         },
 345  },
 346  [ C(DTLB) ] = {
 347         [ C(OP_READ) ] = {
 348                 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
 349                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
 350         },
 351         [ C(OP_WRITE) ] = {
 352                 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
 353                 [ C(RESULT_MISS)   ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
 354         },
 355         [ C(OP_PREFETCH) ] = {
 356                 [ C(RESULT_ACCESS) ] = 0x0,
 357                 [ C(RESULT_MISS)   ] = 0x0,
 358         },
 359  },
 360  [ C(ITLB) ] = {
 361         [ C(OP_READ) ] = {
 362                 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT         */
 363                 [ C(RESULT_MISS)   ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK    */
 364         },
 365         [ C(OP_WRITE) ] = {
 366                 [ C(RESULT_ACCESS) ] = -1,
 367                 [ C(RESULT_MISS)   ] = -1,
 368         },
 369         [ C(OP_PREFETCH) ] = {
 370                 [ C(RESULT_ACCESS) ] = -1,
 371                 [ C(RESULT_MISS)   ] = -1,
 372         },
 373  },
 374  [ C(BPU ) ] = {
 375         [ C(OP_READ) ] = {
 376                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 377                 [ C(RESULT_MISS)   ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
 378         },
 379         [ C(OP_WRITE) ] = {
 380                 [ C(RESULT_ACCESS) ] = -1,
 381                 [ C(RESULT_MISS)   ] = -1,
 382         },
 383         [ C(OP_PREFETCH) ] = {
 384                 [ C(RESULT_ACCESS) ] = -1,
 385                 [ C(RESULT_MISS)   ] = -1,
 386         },
 387  },
 388  [ C(NODE) ] = {
 389         [ C(OP_READ) ] = {
 390                 [ C(RESULT_ACCESS) ] = 0x01b7,
 391                 [ C(RESULT_MISS)   ] = 0x01b7,
 392         },
 393         [ C(OP_WRITE) ] = {
 394                 [ C(RESULT_ACCESS) ] = 0x01b7,
 395                 [ C(RESULT_MISS)   ] = 0x01b7,
 396         },
 397         [ C(OP_PREFETCH) ] = {
 398                 [ C(RESULT_ACCESS) ] = 0x01b7,
 399                 [ C(RESULT_MISS)   ] = 0x01b7,
 400         },
 401  },
 402
 403 };
 404
 405 static __initconst const u64 westmere_hw_cache_event_ids
 406                                 [PERF_COUNT_HW_CACHE_MAX]
 407                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 408                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 409 {
 410  [ C(L1D) ] = {
 411         [ C(OP_READ) ] = {
 412                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
 413                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPL                     */
 414         },
 415         [ C(OP_WRITE) ] = {
 416                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
 417                 [ C(RESULT_MISS)   ] = 0x0251, /* L1D.M_REPL                   */
 418         },
 419         [ C(OP_PREFETCH) ] = {
 420                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
 421                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
 422         },
 423  },
 424  [ C(L1I ) ] = {
 425         [ C(OP_READ) ] = {
 426                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
 427                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
 428         },
 429         [ C(OP_WRITE) ] = {
 430                 [ C(RESULT_ACCESS) ] = -1,
 431                 [ C(RESULT_MISS)   ] = -1,
 432         },
 433         [ C(OP_PREFETCH) ] = {
 434                 [ C(RESULT_ACCESS) ] = 0x0,
 435                 [ C(RESULT_MISS)   ] = 0x0,
 436         },
 437  },
 438  [ C(LL  ) ] = {
 439         [ C(OP_READ) ] = {
 440                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
 441                 [ C(RESULT_ACCESS) ] = 0x01b7,
 442                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
 443                 [ C(RESULT_MISS)   ] = 0x01b7,
 444         },
 445         /*
 446          * Use RFO, not WRITEBACK, because a write miss would typically occur
 447          * on RFO.
 448          */
 449         [ C(OP_WRITE) ] = {
 450                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
 451                 [ C(RESULT_ACCESS) ] = 0x01b7,
 452                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
 453                 [ C(RESULT_MISS)   ] = 0x01b7,
 454         },
 455         [ C(OP_PREFETCH) ] = {
 456                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
 457                 [ C(RESULT_ACCESS) ] = 0x01b7,
 458                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
 459                 [ C(RESULT_MISS)   ] = 0x01b7,
 460         },
 461  },
 462  [ C(DTLB) ] = {
 463         [ C(OP_READ) ] = {
 464                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
 465                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
 466         },
 467         [ C(OP_WRITE) ] = {
 468                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
 469                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
 470         },
 471         [ C(OP_PREFETCH) ] = {
 472                 [ C(RESULT_ACCESS) ] = 0x0,
 473                 [ C(RESULT_MISS)   ] = 0x0,
 474         },
 475  },
 476  [ C(ITLB) ] = {
 477         [ C(OP_READ) ] = {
 478                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
 479                 [ C(RESULT_MISS)   ] = 0x0185, /* ITLB_MISSES.ANY              */
 480         },
 481         [ C(OP_WRITE) ] = {
 482                 [ C(RESULT_ACCESS) ] = -1,
 483                 [ C(RESULT_MISS)   ] = -1,
 484         },
 485         [ C(OP_PREFETCH) ] = {
 486                 [ C(RESULT_ACCESS) ] = -1,
 487                 [ C(RESULT_MISS)   ] = -1,
 488         },
 489  },
 490  [ C(BPU ) ] = {
 491         [ C(OP_READ) ] = {
 492                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 493                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
 494         },
 495         [ C(OP_WRITE) ] = {
 496                 [ C(RESULT_ACCESS) ] = -1,
 497                 [ C(RESULT_MISS)   ] = -1,
 498         },
 499         [ C(OP_PREFETCH) ] = {
 500                 [ C(RESULT_ACCESS) ] = -1,
 501                 [ C(RESULT_MISS)   ] = -1,
 502         },
 503  },
 504  [ C(NODE) ] = {
 505         [ C(OP_READ) ] = {
 506                 [ C(RESULT_ACCESS) ] = 0x01b7,
 507                 [ C(RESULT_MISS)   ] = 0x01b7,
 508         },
 509         [ C(OP_WRITE) ] = {
 510                 [ C(RESULT_ACCESS) ] = 0x01b7,
 511                 [ C(RESULT_MISS)   ] = 0x01b7,
 512         },
 513         [ C(OP_PREFETCH) ] = {
 514                 [ C(RESULT_ACCESS) ] = 0x01b7,
 515                 [ C(RESULT_MISS)   ] = 0x01b7,
 516         },
 517  },
 518 };
 519
 520 /*
 521  * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
 522  * See IA32 SDM Vol 3B 30.6.1.3
 523  */
 524
 525 #define NHM_DMND_DATA_RD        (1 << 0)
 526 #define NHM_DMND_RFO            (1 << 1)
 527 #define NHM_DMND_IFETCH         (1 << 2)
 528 #define NHM_DMND_WB             (1 << 3)
 529 #define NHM_PF_DATA_RD          (1 << 4)
 530 #define NHM_PF_DATA_RFO         (1 << 5)
 531 #define NHM_PF_IFETCH           (1 << 6)
 532 #define NHM_OFFCORE_OTHER       (1 << 7)
 533 #define NHM_UNCORE_HIT          (1 << 8)
 534 #define NHM_OTHER_CORE_HIT_SNP  (1 << 9)
 535 #define NHM_OTHER_CORE_HITM     (1 << 10)
 536                                 /* reserved */
 537 #define NHM_REMOTE_CACHE_FWD    (1 << 12)
 538 #define NHM_REMOTE_DRAM         (1 << 13)
 539 #define NHM_LOCAL_DRAM          (1 << 14)
 540 #define NHM_NON_DRAM            (1 << 15)
 541
 542 #define NHM_LOCAL               (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
 543 #define NHM_REMOTE              (NHM_REMOTE_DRAM)
 544
 545 #define NHM_DMND_READ           (NHM_DMND_DATA_RD)
 546 #define NHM_DMND_WRITE          (NHM_DMND_RFO|NHM_DMND_WB)
 547 #define NHM_DMND_PREFETCH       (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
 548
 549 #define NHM_L3_HIT      (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
 550 #define NHM_L3_MISS     (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
 551 #define NHM_L3_ACCESS   (NHM_L3_HIT|NHM_L3_MISS)
 552
 553 static __initconst const u64 nehalem_hw_cache_extra_regs
 554                                 [PERF_COUNT_HW_CACHE_MAX]
 555                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 556                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 557 {
 558  [ C(LL  ) ] = {
 559         [ C(OP_READ) ] = {
 560                 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
 561                 [ C(RESULT_MISS)   ] = NHM_DMND_READ|NHM_L3_MISS,
 562         },
 563         [ C(OP_WRITE) ] = {
 564                 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
 565                 [ C(RESULT_MISS)   ] = NHM_DMND_WRITE|NHM_L3_MISS,
 566         },
 567         [ C(OP_PREFETCH) ] = {
 568                 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
 569                 [ C(RESULT_MISS)   ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
 570         },
 571  },
 572  [ C(NODE) ] = {
 573         [ C(OP_READ) ] = {
 574                 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
 575                 [ C(RESULT_MISS)   ] = NHM_DMND_READ|NHM_REMOTE,
 576         },
 577         [ C(OP_WRITE) ] = {
 578                 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
 579                 [ C(RESULT_MISS)   ] = NHM_DMND_WRITE|NHM_REMOTE,
 580         },
 581         [ C(OP_PREFETCH) ] = {
 582                 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
 583                 [ C(RESULT_MISS)   ] = NHM_DMND_PREFETCH|NHM_REMOTE,
 584         },
 585  },
 586 };
 587
 588 static __initconst const u64 nehalem_hw_cache_event_ids
 589                                 [PERF_COUNT_HW_CACHE_MAX]
 590                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 591                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 592 {
 593  [ C(L1D) ] = {
 594         [ C(OP_READ) ] = {
 595                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
 596                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPL                     */
 597         },
 598         [ C(OP_WRITE) ] = {
 599                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
 600                 [ C(RESULT_MISS)   ] = 0x0251, /* L1D.M_REPL                   */
 601         },
 602         [ C(OP_PREFETCH) ] = {
 603                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
 604                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
 605         },
 606  },
 607  [ C(L1I ) ] = {
 608         [ C(OP_READ) ] = {
 609                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
 610                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
 611         },
 612         [ C(OP_WRITE) ] = {
 613                 [ C(RESULT_ACCESS) ] = -1,
 614                 [ C(RESULT_MISS)   ] = -1,
 615         },
 616         [ C(OP_PREFETCH) ] = {
 617                 [ C(RESULT_ACCESS) ] = 0x0,
 618                 [ C(RESULT_MISS)   ] = 0x0,
 619         },
 620  },
 621  [ C(LL  ) ] = {
 622         [ C(OP_READ) ] = {
 623                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
 624                 [ C(RESULT_ACCESS) ] = 0x01b7,
 625                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
 626                 [ C(RESULT_MISS)   ] = 0x01b7,
 627         },
 628         /*
 629          * Use RFO, not WRITEBACK, because a write miss would typically occur
 630          * on RFO.
 631          */
 632         [ C(OP_WRITE) ] = {
 633                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
 634                 [ C(RESULT_ACCESS) ] = 0x01b7,
 635                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
 636                 [ C(RESULT_MISS)   ] = 0x01b7,
 637         },
 638         [ C(OP_PREFETCH) ] = {
 639                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
 640                 [ C(RESULT_ACCESS) ] = 0x01b7,
 641                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
 642                 [ C(RESULT_MISS)   ] = 0x01b7,
 643         },
 644  },
 645  [ C(DTLB) ] = {
 646         [ C(OP_READ) ] = {
 647                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI   (alias)  */
 648                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
 649         },
 650         [ C(OP_WRITE) ] = {
 651                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI   (alias)  */
 652                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
 653         },
 654         [ C(OP_PREFETCH) ] = {
 655                 [ C(RESULT_ACCESS) ] = 0x0,
 656                 [ C(RESULT_MISS)   ] = 0x0,
 657         },
 658  },
 659  [ C(ITLB) ] = {
 660         [ C(OP_READ) ] = {
 661                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
 662                 [ C(RESULT_MISS)   ] = 0x20c8, /* ITLB_MISS_RETIRED            */
 663         },
 664         [ C(OP_WRITE) ] = {
 665                 [ C(RESULT_ACCESS) ] = -1,
 666                 [ C(RESULT_MISS)   ] = -1,
 667         },
 668         [ C(OP_PREFETCH) ] = {
 669                 [ C(RESULT_ACCESS) ] = -1,
 670                 [ C(RESULT_MISS)   ] = -1,
 671         },
 672  },
 673  [ C(BPU ) ] = {
 674         [ C(OP_READ) ] = {
 675                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 676                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
 677         },
 678         [ C(OP_WRITE) ] = {
 679                 [ C(RESULT_ACCESS) ] = -1,
 680                 [ C(RESULT_MISS)   ] = -1,
 681         },
 682         [ C(OP_PREFETCH) ] = {
 683                 [ C(RESULT_ACCESS) ] = -1,
 684                 [ C(RESULT_MISS)   ] = -1,
 685         },
 686  },
 687  [ C(NODE) ] = {
 688         [ C(OP_READ) ] = {
 689                 [ C(RESULT_ACCESS) ] = 0x01b7,
 690                 [ C(RESULT_MISS)   ] = 0x01b7,
 691         },
 692         [ C(OP_WRITE) ] = {
 693                 [ C(RESULT_ACCESS) ] = 0x01b7,
 694                 [ C(RESULT_MISS)   ] = 0x01b7,
 695         },
 696         [ C(OP_PREFETCH) ] = {
 697                 [ C(RESULT_ACCESS) ] = 0x01b7,
 698                 [ C(RESULT_MISS)   ] = 0x01b7,
 699         },
 700  },
 701 };
 702
 703 static __initconst const u64 core2_hw_cache_event_ids
 704                                 [PERF_COUNT_HW_CACHE_MAX]
 705                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 706                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 707 {
 708  [ C(L1D) ] = {
 709         [ C(OP_READ) ] = {
 710                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI          */
 711                 [ C(RESULT_MISS)   ] = 0x0140, /* L1D_CACHE_LD.I_STATE       */
 712         },
 713         [ C(OP_WRITE) ] = {
 714                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI          */
 715                 [ C(RESULT_MISS)   ] = 0x0141, /* L1D_CACHE_ST.I_STATE       */
 716         },
 717         [ C(OP_PREFETCH) ] = {
 718                 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS      */
 719                 [ C(RESULT_MISS)   ] = 0,
 720         },
 721  },
 722  [ C(L1I ) ] = {
 723         [ C(OP_READ) ] = {
 724                 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS                  */
 725                 [ C(RESULT_MISS)   ] = 0x0081, /* L1I.MISSES                 */
 726         },
 727         [ C(OP_WRITE) ] = {
 728                 [ C(RESULT_ACCESS) ] = -1,
 729                 [ C(RESULT_MISS)   ] = -1,
 730         },
 731         [ C(OP_PREFETCH) ] = {
 732                 [ C(RESULT_ACCESS) ] = 0,
 733                 [ C(RESULT_MISS)   ] = 0,
 734         },
 735  },
 736  [ C(LL  ) ] = {
 737         [ C(OP_READ) ] = {
 738                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
 739                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
 740         },
 741         [ C(OP_WRITE) ] = {
 742                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
 743                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
 744         },
 745         [ C(OP_PREFETCH) ] = {
 746                 [ C(RESULT_ACCESS) ] = 0,
 747                 [ C(RESULT_MISS)   ] = 0,
 748         },
 749  },
 750  [ C(DTLB) ] = {
 751         [ C(OP_READ) ] = {
 752                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI  (alias) */
 753                 [ C(RESULT_MISS)   ] = 0x0208, /* DTLB_MISSES.MISS_LD        */
 754         },
 755         [ C(OP_WRITE) ] = {
 756                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI  (alias) */
 757                 [ C(RESULT_MISS)   ] = 0x0808, /* DTLB_MISSES.MISS_ST        */
 758         },
 759         [ C(OP_PREFETCH) ] = {
 760                 [ C(RESULT_ACCESS) ] = 0,
 761                 [ C(RESULT_MISS)   ] = 0,
 762         },
 763  },
 764  [ C(ITLB) ] = {
 765         [ C(OP_READ) ] = {
 766                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
 767                 [ C(RESULT_MISS)   ] = 0x1282, /* ITLBMISSES                 */
 768         },
 769         [ C(OP_WRITE) ] = {
 770                 [ C(RESULT_ACCESS) ] = -1,
 771                 [ C(RESULT_MISS)   ] = -1,
 772         },
 773         [ C(OP_PREFETCH) ] = {
 774                 [ C(RESULT_ACCESS) ] = -1,
 775                 [ C(RESULT_MISS)   ] = -1,
 776         },
 777  },
 778  [ C(BPU ) ] = {
 779         [ C(OP_READ) ] = {
 780                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
 781                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
 782         },
 783         [ C(OP_WRITE) ] = {
 784                 [ C(RESULT_ACCESS) ] = -1,
 785                 [ C(RESULT_MISS)   ] = -1,
 786         },
 787         [ C(OP_PREFETCH) ] = {
 788                 [ C(RESULT_ACCESS) ] = -1,
 789                 [ C(RESULT_MISS)   ] = -1,
 790         },
 791  },
 792 };
 793
 794 static __initconst const u64 atom_hw_cache_event_ids
 795                                 [PERF_COUNT_HW_CACHE_MAX]
 796                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 797                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 798 {
 799  [ C(L1D) ] = {
 800         [ C(OP_READ) ] = {
 801                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD               */
 802                 [ C(RESULT_MISS)   ] = 0,
 803         },
 804         [ C(OP_WRITE) ] = {
 805                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST               */
 806                 [ C(RESULT_MISS)   ] = 0,
 807         },
 808         [ C(OP_PREFETCH) ] = {
 809                 [ C(RESULT_ACCESS) ] = 0x0,
 810                 [ C(RESULT_MISS)   ] = 0,
 811         },
 812  },
 813  [ C(L1I ) ] = {
 814         [ C(OP_READ) ] = {
 815                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                  */
 816                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                 */
 817         },
 818         [ C(OP_WRITE) ] = {
 819                 [ C(RESULT_ACCESS) ] = -1,
 820                 [ C(RESULT_MISS)   ] = -1,
 821         },
 822         [ C(OP_PREFETCH) ] = {
 823                 [ C(RESULT_ACCESS) ] = 0,
 824                 [ C(RESULT_MISS)   ] = 0,
 825         },
 826  },
 827  [ C(LL  ) ] = {
 828         [ C(OP_READ) ] = {
 829                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
 830                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
 831         },
 832         [ C(OP_WRITE) ] = {
 833                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
 834                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
 835         },
 836         [ C(OP_PREFETCH) ] = {
 837                 [ C(RESULT_ACCESS) ] = 0,
 838                 [ C(RESULT_MISS)   ] = 0,
 839         },
 840  },
 841  [ C(DTLB) ] = {
 842         [ C(OP_READ) ] = {
 843                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI  (alias) */
 844                 [ C(RESULT_MISS)   ] = 0x0508, /* DTLB_MISSES.MISS_LD        */
 845         },
 846         [ C(OP_WRITE) ] = {
 847                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI  (alias) */
 848                 [ C(RESULT_MISS)   ] = 0x0608, /* DTLB_MISSES.MISS_ST        */
 849         },
 850         [ C(OP_PREFETCH) ] = {
 851                 [ C(RESULT_ACCESS) ] = 0,
 852                 [ C(RESULT_MISS)   ] = 0,
 853         },
 854  },
 855  [ C(ITLB) ] = {
 856         [ C(OP_READ) ] = {
 857                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
 858                 [ C(RESULT_MISS)   ] = 0x0282, /* ITLB.MISSES                */
 859         },
 860         [ C(OP_WRITE) ] = {
 861                 [ C(RESULT_ACCESS) ] = -1,
 862                 [ C(RESULT_MISS)   ] = -1,
 863         },
 864         [ C(OP_PREFETCH) ] = {
 865                 [ C(RESULT_ACCESS) ] = -1,
 866                 [ C(RESULT_MISS)   ] = -1,
 867         },
 868  },
 869  [ C(BPU ) ] = {
 870         [ C(OP_READ) ] = {
 871                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
 872                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
 873         },
 874         [ C(OP_WRITE) ] = {
 875                 [ C(RESULT_ACCESS) ] = -1,
 876                 [ C(RESULT_MISS)   ] = -1,
 877         },
 878         [ C(OP_PREFETCH) ] = {
 879                 [ C(RESULT_ACCESS) ] = -1,
 880                 [ C(RESULT_MISS)   ] = -1,
 881         },
 882  },
 883 };
 884
 885 static inline bool intel_pmu_needs_lbr_smpl(struct perf_event *event)
 886 {
 887         /* user explicitly requested branch sampling */
 888         if (has_branch_stack(event))
 889                 return true;
 890
 891         /* implicit branch sampling to correct PEBS skid */
 892         if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1 &&
 893             x86_pmu.intel_cap.pebs_format < 2)
 894                 return true;
 895
 896         return false;
 897 }
 898
 899 static void intel_pmu_disable_all(void)
 900 {
 901         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 902
 903         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
 904
 905         if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
 906                 intel_pmu_disable_bts();
 907
 908         intel_pmu_pebs_disable_all();
 909         intel_pmu_lbr_disable_all();
 910 }
 911
 912 static void intel_pmu_enable_all(int added)
 913 {
 914         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 915
 916         intel_pmu_pebs_enable_all();
 917         intel_pmu_lbr_enable_all();
 918         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
 919                         x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
 920
 921         if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
 922                 struct perf_event *event =
 923                         cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
 924
 925                 if (WARN_ON_ONCE(!event))
 926                         return;
 927
 928                 intel_pmu_enable_bts(event->hw.config);
 929         }
 930 }
 931
 932 /*
 933  * Workaround for:
 934  *   Intel Errata AAK100 (model 26)
 935  *   Intel Errata AAP53  (model 30)
 936  *   Intel Errata BD53   (model 44)
 937  *
 938  * The official story:
 939  *   These chips need to be 'reset' when adding counters by programming the
 940  *   magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
 941  *   in sequence on the same PMC or on different PMCs.
 942  *
 943  * In practise it appears some of these events do in fact count, and
 944  * we need to programm all 4 events.
 945  */
 946 static void intel_pmu_nhm_workaround(void)
 947 {
 948         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 949         static const unsigned long nhm_magic[4] = {
 950                 0x4300B5,
 951                 0x4300D2,
 952                 0x4300B1,
 953                 0x4300B1
 954         };
 955         struct perf_event *event;
 956         int i;
 957
 958         /*
 959          * The Errata requires below steps:
 960          * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
 961          * 2) Configure 4 PERFEVTSELx with the magic events and clear
 962          *    the corresponding PMCx;
 963          * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
 964          * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
 965          * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
 966          */
 967
 968         /*
 969          * The real steps we choose are a little different from above.
 970          * A) To reduce MSR operations, we don't run step 1) as they
 971          *    are already cleared before this function is called;
 972          * B) Call x86_perf_event_update to save PMCx before configuring
 973          *    PERFEVTSELx with magic number;
 974          * C) With step 5), we do clear only when the PERFEVTSELx is
 975          *    not used currently.
 976          * D) Call x86_perf_event_set_period to restore PMCx;
 977          */
 978
 979         /* We always operate 4 pairs of PERF Counters */
 980         for (i = 0; i < 4; i++) {
 981                 event = cpuc->events[i];
 982                 if (event)
 983                         x86_perf_event_update(event);
 984         }
 985
 986         for (i = 0; i < 4; i++) {
 987                 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
 988                 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
 989         }
 990
 991         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
 992         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
 993
 994         for (i = 0; i < 4; i++) {
 995                 event = cpuc->events[i];
 996
 997                 if (event) {
 998                         x86_perf_event_set_period(event);
 999                         __x86_pmu_enable_event(&event->hw,
1000                                         ARCH_PERFMON_EVENTSEL_ENABLE);
1001                 } else
1002                         wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
1003         }
1004 }
1005
1006 static void intel_pmu_nhm_enable_all(int added)
1007 {
1008         if (added)
1009                 intel_pmu_nhm_workaround();
1010         intel_pmu_enable_all(added);
1011 }
1012
1013 static inline u64 intel_pmu_get_status(void)
1014 {
1015         u64 status;
1016
1017         rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1018
1019         return status;
1020 }
1021
1022 static inline void intel_pmu_ack_status(u64 ack)
1023 {
1024         wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1025 }
1026
1027 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
1028 {
1029         int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1030         u64 ctrl_val, mask;
1031
1032         mask = 0xfULL << (idx * 4);
1033
1034         rdmsrl(hwc->config_base, ctrl_val);
1035         ctrl_val &= ~mask;
1036         wrmsrl(hwc->config_base, ctrl_val);
1037 }
1038
1039 static void intel_pmu_disable_event(struct perf_event *event)
1040 {
1041         struct hw_perf_event *hwc = &event->hw;
1042         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1043
1044         if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
1045                 intel_pmu_disable_bts();
1046                 intel_pmu_drain_bts_buffer();
1047                 return;
1048         }
1049
1050         cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
1051         cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
1052
1053         /*
1054          * must disable before any actual event
1055          * because any event may be combined with LBR
1056          */
1057         if (intel_pmu_needs_lbr_smpl(event))
1058                 intel_pmu_lbr_disable(event);
1059
1060         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1061                 intel_pmu_disable_fixed(hwc);
1062                 return;
1063         }
1064
1065         x86_pmu_disable_event(event);
1066
1067         if (unlikely(event->attr.precise_ip))
1068                 intel_pmu_pebs_disable(event);
1069 }
1070
1071 static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
1072 {
1073         int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1074         u64 ctrl_val, bits, mask;
1075
1076         /*
1077          * Enable IRQ generation (0x8),
1078          * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1079          * if requested:
1080          */
1081         bits = 0x8ULL;
1082         if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1083                 bits |= 0x2;
1084         if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1085                 bits |= 0x1;
1086
1087         /*
1088          * ANY bit is supported in v3 and up
1089          */
1090         if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1091                 bits |= 0x4;
1092
1093         bits <<= (idx * 4);
1094         mask = 0xfULL << (idx * 4);
1095
1096         rdmsrl(hwc->config_base, ctrl_val);
1097         ctrl_val &= ~mask;
1098         ctrl_val |= bits;
1099         wrmsrl(hwc->config_base, ctrl_val);
1100 }
1101
1102 static void intel_pmu_enable_event(struct perf_event *event)
1103 {
1104         struct hw_perf_event *hwc = &event->hw;
1105         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1106
1107         if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
1108                 if (!__this_cpu_read(cpu_hw_events.enabled))
1109                         return;
1110
1111                 intel_pmu_enable_bts(hwc->config);
1112                 return;
1113         }
1114         /*
1115          * must enabled before any actual event
1116          * because any event may be combined with LBR
1117          */
1118         if (intel_pmu_needs_lbr_smpl(event))
1119                 intel_pmu_lbr_enable(event);
1120
1121         if (event->attr.exclude_host)
1122                 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1123         if (event->attr.exclude_guest)
1124                 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1125
1126         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1127                 intel_pmu_enable_fixed(hwc);
1128                 return;
1129         }
1130
1131         if (unlikely(event->attr.precise_ip))
1132                 intel_pmu_pebs_enable(event);
1133
1134         __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1135 }
1136
1137 /*
1138  * Save and restart an expired event. Called by NMI contexts,
1139  * so it has to be careful about preempting normal event ops:
1140  */
1141 int intel_pmu_save_and_restart(struct perf_event *event)
1142 {
1143         x86_perf_event_update(event);
1144         return x86_perf_event_set_period(event);
1145 }
1146
1147 static void intel_pmu_reset(void)
1148 {
1149         struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1150         unsigned long flags;
1151         int idx;
1152
1153         if (!x86_pmu.num_counters)
1154                 return;
1155
1156         local_irq_save(flags);
1157
1158         pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
1159
1160         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1161                 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
1162                 wrmsrl_safe(x86_pmu_event_addr(idx),  0ull);
1163         }
1164         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
1165                 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
1166
1167         if (ds)
1168                 ds->bts_index = ds->bts_buffer_base;
1169
1170         local_irq_restore(flags);
1171 }
1172
1173 /*
1174  * This handler is triggered by the local APIC, so the APIC IRQ handling
1175  * rules apply:
1176  */
1177 static int intel_pmu_handle_irq(struct pt_regs *regs)
1178 {
1179         struct perf_sample_data data;
1180         struct cpu_hw_events *cpuc;
1181         int bit, loops;
1182         u64 status;
1183         int handled;
1184
1185         cpuc = &__get_cpu_var(cpu_hw_events);
1186
1187         /*
1188          * No known reason to not always do late ACK,
1189          * but just in case do it opt-in.
1190          */
1191         if (!x86_pmu.late_ack)
1192                 apic_write(APIC_LVTPC, APIC_DM_NMI);
1193         intel_pmu_disable_all();
1194         handled = intel_pmu_drain_bts_buffer();
1195         status = intel_pmu_get_status();
1196         if (!status) {
1197                 intel_pmu_enable_all(0);
1198                 return handled;
1199         }
1200
1201         loops = 0;
1202 again:
1203         intel_pmu_ack_status(status);
1204         if (++loops > 100) {
1205                 static bool warned = false;
1206                 if (!warned) {
1207                         WARN(1, "perfevents: irq loop stuck!\n");
1208                         perf_event_print_debug();
1209                         warned = true;
1210                 }
1211                 intel_pmu_reset();
1212                 goto done;
1213         }
1214
1215         inc_irq_stat(apic_perf_irqs);
1216
1217         intel_pmu_lbr_read();
1218
1219         /*
1220          * PEBS overflow sets bit 62 in the global status register
1221          */
1222         if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1223                 handled++;
1224                 x86_pmu.drain_pebs(regs);
1225         }
1226
1227         for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
1228                 struct perf_event *event = cpuc->events[bit];
1229
1230                 handled++;
1231
1232                 if (!test_bit(bit, cpuc->active_mask))
1233                         continue;
1234
1235                 if (!intel_pmu_save_and_restart(event))
1236                         continue;
1237
1238                 perf_sample_data_init(&data, 0, event->hw.last_period);
1239
1240                 if (has_branch_stack(event))
1241                         data.br_stack = &cpuc->lbr_stack;
1242
1243                 if (perf_event_overflow(event, &data, regs))
1244                         x86_pmu_stop(event, 0);
1245         }
1246
1247         /*
1248          * Repeat if there is more work to be done:
1249          */
1250         status = intel_pmu_get_status();
1251         if (status)
1252                 goto again;
1253
1254 done:
1255         intel_pmu_enable_all(0);
1256         /*
1257          * Only unmask the NMI after the overflow counters
1258          * have been reset. This avoids spurious NMIs on
1259          * Haswell CPUs.
1260          */
1261         if (x86_pmu.late_ack)
1262                 apic_write(APIC_LVTPC, APIC_DM_NMI);
1263         return handled;
1264 }
1265
1266 static struct event_constraint *
1267 intel_bts_constraints(struct perf_event *event)
1268 {
1269         struct hw_perf_event *hwc = &event->hw;
1270         unsigned int hw_event, bts_event;
1271
1272         if (event->attr.freq)
1273                 return NULL;
1274
1275         hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1276         bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
1277
1278         if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
1279                 return &bts_constraint;
1280
1281         return NULL;
1282 }
1283
1284 static int intel_alt_er(int idx)
1285 {
1286         if (!(x86_pmu.er_flags & ERF_HAS_RSP_1))
1287                 return idx;
1288
1289         if (idx == EXTRA_REG_RSP_0)
1290                 return EXTRA_REG_RSP_1;
1291
1292         if (idx == EXTRA_REG_RSP_1)
1293                 return EXTRA_REG_RSP_0;
1294
1295         return idx;
1296 }
1297
1298 static void intel_fixup_er(struct perf_event *event, int idx)
1299 {
1300         event->hw.extra_reg.idx = idx;
1301
1302         if (idx == EXTRA_REG_RSP_0) {
1303                 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1304                 event->hw.config |= 0x01b7;
1305                 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
1306         } else if (idx == EXTRA_REG_RSP_1) {
1307                 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1308                 event->hw.config |= 0x01bb;
1309                 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
1310         }
1311 }
1312
1313 /*
1314  * manage allocation of shared extra msr for certain events
1315  *
1316  * sharing can be:
1317  * per-cpu: to be shared between the various events on a single PMU
1318  * per-core: per-cpu + shared by HT threads
1319  */
1320 static struct event_constraint *
1321 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
1322                                    struct perf_event *event,
1323                                    struct hw_perf_event_extra *reg)
1324 {
1325         struct event_constraint *c = &emptyconstraint;
1326         struct er_account *era;
1327         unsigned long flags;
1328         int idx = reg->idx;
1329
1330         /*
1331          * reg->alloc can be set due to existing state, so for fake cpuc we
1332          * need to ignore this, otherwise we might fail to allocate proper fake
1333          * state for this extra reg constraint. Also see the comment below.
1334          */
1335         if (reg->alloc && !cpuc->is_fake)
1336                 return NULL; /* call x86_get_event_constraint() */
1337
1338 again:
1339         era = &cpuc->shared_regs->regs[idx];
1340         /*
1341          * we use spin_lock_irqsave() to avoid lockdep issues when
1342          * passing a fake cpuc
1343          */
1344         raw_spin_lock_irqsave(&era->lock, flags);
1345
1346         if (!atomic_read(&era->ref) || era->config == reg->config) {
1347
1348                 /*
1349                  * If its a fake cpuc -- as per validate_{group,event}() we
1350                  * shouldn't touch event state and we can avoid doing so
1351                  * since both will only call get_event_constraints() once
1352                  * on each event, this avoids the need for reg->alloc.
1353                  *
1354                  * Not doing the ER fixup will only result in era->reg being
1355                  * wrong, but since we won't actually try and program hardware
1356                  * this isn't a problem either.
1357                  */
1358                 if (!cpuc->is_fake) {
1359                         if (idx != reg->idx)
1360                                 intel_fixup_er(event, idx);
1361
1362                         /*
1363                          * x86_schedule_events() can call get_event_constraints()
1364                          * multiple times on events in the case of incremental
1365                          * scheduling(). reg->alloc ensures we only do the ER
1366                          * allocation once.
1367                          */
1368                         reg->alloc = 1;
1369                 }
1370
1371                 /* lock in msr value */
1372                 era->config = reg->config;
1373                 era->reg = reg->reg;
1374
1375                 /* one more user */
1376                 atomic_inc(&era->ref);
1377
1378                 /*
1379                  * need to call x86_get_event_constraint()
1380                  * to check if associated event has constraints
1381                  */
1382                 c = NULL;
1383         } else {
1384                 idx = intel_alt_er(idx);
1385                 if (idx != reg->idx) {
1386                         raw_spin_unlock_irqrestore(&era->lock, flags);
1387                         goto again;
1388                 }
1389         }
1390         raw_spin_unlock_irqrestore(&era->lock, flags);
1391
1392         return c;
1393 }
1394
1395 static void
1396 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
1397                                    struct hw_perf_event_extra *reg)
1398 {
1399         struct er_account *era;
1400
1401         /*
1402          * Only put constraint if extra reg was actually allocated. Also takes
1403          * care of event which do not use an extra shared reg.
1404          *
1405          * Also, if this is a fake cpuc we shouldn't touch any event state
1406          * (reg->alloc) and we don't care about leaving inconsistent cpuc state
1407          * either since it'll be thrown out.
1408          */
1409         if (!reg->alloc || cpuc->is_fake)
1410                 return;
1411
1412         era = &cpuc->shared_regs->regs[reg->idx];
1413
1414         /* one fewer user */
1415         atomic_dec(&era->ref);
1416
1417         /* allocate again next time */
1418         reg->alloc = 0;
1419 }
1420
1421 static struct event_constraint *
1422 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
1423                               struct perf_event *event)
1424 {
1425         struct event_constraint *c = NULL, *d;
1426         struct hw_perf_event_extra *xreg, *breg;
1427
1428         xreg = &event->hw.extra_reg;
1429         if (xreg->idx != EXTRA_REG_NONE) {
1430                 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
1431                 if (c == &emptyconstraint)
1432                         return c;
1433         }
1434         breg = &event->hw.branch_reg;
1435         if (breg->idx != EXTRA_REG_NONE) {
1436                 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
1437                 if (d == &emptyconstraint) {
1438                         __intel_shared_reg_put_constraints(cpuc, xreg);
1439                         c = d;
1440                 }
1441         }
1442         return c;
1443 }
1444
1445 struct event_constraint *
1446 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1447 {
1448         struct event_constraint *c;
1449
1450         if (x86_pmu.event_constraints) {
1451                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1452                         if ((event->hw.config & c->cmask) == c->code) {
1453                                 /* hw.flags zeroed at initialization */
1454                                 event->hw.flags |= c->flags;
1455                                 return c;
1456                         }
1457                 }
1458         }
1459
1460         return &unconstrained;
1461 }
1462
1463 static struct event_constraint *
1464 intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1465 {
1466         struct event_constraint *c;
1467
1468         c = intel_bts_constraints(event);
1469         if (c)
1470                 return c;
1471
1472         c = intel_pebs_constraints(event);
1473         if (c)
1474                 return c;
1475
1476         c = intel_shared_regs_constraints(cpuc, event);
1477         if (c)
1478                 return c;
1479
1480         return x86_get_event_constraints(cpuc, event);
1481 }
1482
1483 static void
1484 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
1485                                         struct perf_event *event)
1486 {
1487         struct hw_perf_event_extra *reg;
1488
1489         reg = &event->hw.extra_reg;
1490         if (reg->idx != EXTRA_REG_NONE)
1491                 __intel_shared_reg_put_constraints(cpuc, reg);
1492
1493         reg = &event->hw.branch_reg;
1494         if (reg->idx != EXTRA_REG_NONE)
1495                 __intel_shared_reg_put_constraints(cpuc, reg);
1496 }
1497
1498 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
1499                                         struct perf_event *event)
1500 {
1501         event->hw.flags = 0;
1502         intel_put_shared_regs_event_constraints(cpuc, event);
1503 }
1504
1505 static void intel_pebs_aliases_core2(struct perf_event *event)
1506 {
1507         if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1508                 /*
1509                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1510                  * (0x003c) so that we can use it with PEBS.
1511                  *
1512                  * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1513                  * PEBS capable. However we can use INST_RETIRED.ANY_P
1514                  * (0x00c0), which is a PEBS capable event, to get the same
1515                  * count.
1516                  *
1517                  * INST_RETIRED.ANY_P counts the number of cycles that retires
1518                  * CNTMASK instructions. By setting CNTMASK to a value (16)
1519                  * larger than the maximum number of instructions that can be
1520                  * retired per cycle (4) and then inverting the condition, we
1521                  * count all cycles that retire 16 or less instructions, which
1522                  * is every cycle.
1523                  *
1524                  * Thereby we gain a PEBS capable cycle counter.
1525                  */
1526                 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
1527
1528                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1529                 event->hw.config = alt_config;
1530         }
1531 }
1532
1533 static void intel_pebs_aliases_snb(struct perf_event *event)
1534 {
1535         if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1536                 /*
1537                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1538                  * (0x003c) so that we can use it with PEBS.
1539                  *
1540                  * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1541                  * PEBS capable. However we can use UOPS_RETIRED.ALL
1542                  * (0x01c2), which is a PEBS capable event, to get the same
1543                  * count.
1544                  *
1545                  * UOPS_RETIRED.ALL counts the number of cycles that retires
1546                  * CNTMASK micro-ops. By setting CNTMASK to a value (16)
1547                  * larger than the maximum number of micro-ops that can be
1548                  * retired per cycle (4) and then inverting the condition, we
1549                  * count all cycles that retire 16 or less micro-ops, which
1550                  * is every cycle.
1551                  *
1552                  * Thereby we gain a PEBS capable cycle counter.
1553                  */
1554                 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
1555
1556                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1557                 event->hw.config = alt_config;
1558         }
1559 }
1560
1561 static int intel_pmu_hw_config(struct perf_event *event)
1562 {
1563         int ret = x86_pmu_hw_config(event);
1564
1565         if (ret)
1566                 return ret;
1567
1568         if (event->attr.precise_ip && x86_pmu.pebs_aliases)
1569                 x86_pmu.pebs_aliases(event);
1570
1571         if (intel_pmu_needs_lbr_smpl(event)) {
1572                 ret = intel_pmu_setup_lbr_filter(event);
1573                 if (ret)
1574                         return ret;
1575         }
1576
1577         if (event->attr.type != PERF_TYPE_RAW)
1578                 return 0;
1579
1580         if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
1581                 return 0;
1582
1583         if (x86_pmu.version < 3)
1584                 return -EINVAL;
1585
1586         if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
1587                 return -EACCES;
1588
1589         event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
1590
1591         return 0;
1592 }
1593
1594 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
1595 {
1596         if (x86_pmu.guest_get_msrs)
1597                 return x86_pmu.guest_get_msrs(nr);
1598         *nr = 0;
1599         return NULL;
1600 }
1601 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
1602
1603 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
1604 {
1605         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1606         struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1607
1608         arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
1609         arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
1610         arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
1611         /*
1612          * If PMU counter has PEBS enabled it is not enough to disable counter
1613          * on a guest entry since PEBS memory write can overshoot guest entry
1614          * and corrupt guest memory. Disabling PEBS solves the problem.
1615          */
1616         arr[1].msr = MSR_IA32_PEBS_ENABLE;
1617         arr[1].host = cpuc->pebs_enabled;
1618         arr[1].guest = 0;
1619
1620         *nr = 2;
1621         return arr;
1622 }
1623
1624 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
1625 {
1626         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1627         struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1628         int idx;
1629
1630         for (idx = 0; idx < x86_pmu.num_counters; idx++)  {
1631                 struct perf_event *event = cpuc->events[idx];
1632
1633                 arr[idx].msr = x86_pmu_config_addr(idx);
1634                 arr[idx].host = arr[idx].guest = 0;
1635
1636                 if (!test_bit(idx, cpuc->active_mask))
1637                         continue;
1638
1639                 arr[idx].host = arr[idx].guest =
1640                         event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
1641
1642                 if (event->attr.exclude_host)
1643                         arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1644                 else if (event->attr.exclude_guest)
1645                         arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1646         }
1647
1648         *nr = x86_pmu.num_counters;
1649         return arr;
1650 }
1651
1652 static void core_pmu_enable_event(struct perf_event *event)
1653 {
1654         if (!event->attr.exclude_host)
1655                 x86_pmu_enable_event(event);
1656 }
1657
1658 static void core_pmu_enable_all(int added)
1659 {
1660         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1661         int idx;
1662
1663         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1664                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
1665
1666                 if (!test_bit(idx, cpuc->active_mask) ||
1667                                 cpuc->events[idx]->attr.exclude_host)
1668                         continue;
1669
1670                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1671         }
1672 }
1673
1674 static int hsw_hw_config(struct perf_event *event)
1675 {
1676         int ret = intel_pmu_hw_config(event);
1677
1678         if (ret)
1679                 return ret;
1680         if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
1681                 return 0;
1682         event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
1683
1684         /*
1685          * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
1686          * PEBS or in ANY thread mode. Since the results are non-sensical forbid
1687          * this combination.
1688          */
1689         if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
1690              ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
1691               event->attr.precise_ip > 0))
1692                 return -EOPNOTSUPP;
1693
1694         return 0;
1695 }
1696
1697 static struct event_constraint counter2_constraint =
1698                         EVENT_CONSTRAINT(0, 0x4, 0);
1699
1700 static struct event_constraint *
1701 hsw_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1702 {
1703         struct event_constraint *c = intel_get_event_constraints(cpuc, event);
1704
1705         /* Handle special quirk on in_tx_checkpointed only in counter 2 */
1706         if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
1707                 if (c->idxmsk64 & (1U << 2))
1708                         return &counter2_constraint;
1709                 return &emptyconstraint;
1710         }
1711
1712         return c;
1713 }
1714
1715 PMU_FORMAT_ATTR(event,  "config:0-7"    );
1716 PMU_FORMAT_ATTR(umask,  "config:8-15"   );
1717 PMU_FORMAT_ATTR(edge,   "config:18"     );
1718 PMU_FORMAT_ATTR(pc,     "config:19"     );
1719 PMU_FORMAT_ATTR(any,    "config:21"     ); /* v3 + */
1720 PMU_FORMAT_ATTR(inv,    "config:23"     );
1721 PMU_FORMAT_ATTR(cmask,  "config:24-31"  );
1722 PMU_FORMAT_ATTR(in_tx,  "config:32");
1723 PMU_FORMAT_ATTR(in_tx_cp, "config:33");
1724
1725 static struct attribute *intel_arch_formats_attr[] = {
1726         &format_attr_event.attr,
1727         &format_attr_umask.attr,
1728         &format_attr_edge.attr,
1729         &format_attr_pc.attr,
1730         &format_attr_inv.attr,
1731         &format_attr_cmask.attr,
1732         NULL,
1733 };
1734
1735 ssize_t intel_event_sysfs_show(char *page, u64 config)
1736 {
1737         u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
1738
1739         return x86_event_sysfs_show(page, config, event);
1740 }
1741
1742 static __initconst const struct x86_pmu core_pmu = {
1743         .name                   = "core",
1744         .handle_irq             = x86_pmu_handle_irq,
1745         .disable_all            = x86_pmu_disable_all,
1746         .enable_all             = core_pmu_enable_all,
1747         .enable                 = core_pmu_enable_event,
1748         .disable                = x86_pmu_disable_event,
1749         .hw_config              = x86_pmu_hw_config,
1750         .schedule_events        = x86_schedule_events,
1751         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
1752         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
1753         .event_map              = intel_pmu_event_map,
1754         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
1755         .apic                   = 1,
1756         /*
1757          * Intel PMCs cannot be accessed sanely above 32 bit width,
1758          * so we install an artificial 1<<31 period regardless of
1759          * the generic event period:
1760          */
1761         .max_period             = (1ULL << 31) - 1,
1762         .get_event_constraints  = intel_get_event_constraints,
1763         .put_event_constraints  = intel_put_event_constraints,
1764         .event_constraints      = intel_core_event_constraints,
1765         .guest_get_msrs         = core_guest_get_msrs,
1766         .format_attrs           = intel_arch_formats_attr,
1767         .events_sysfs_show      = intel_event_sysfs_show,
1768 };
1769
1770 struct intel_shared_regs *allocate_shared_regs(int cpu)
1771 {
1772         struct intel_shared_regs *regs;
1773         int i;
1774
1775         regs = kzalloc_node(sizeof(struct intel_shared_regs),
1776                             GFP_KERNEL, cpu_to_node(cpu));
1777         if (regs) {
1778                 /*
1779                  * initialize the locks to keep lockdep happy
1780                  */
1781                 for (i = 0; i < EXTRA_REG_MAX; i++)
1782                         raw_spin_lock_init(&regs->regs[i].lock);
1783
1784                 regs->core_id = -1;
1785         }
1786         return regs;
1787 }
1788
1789 static int intel_pmu_cpu_prepare(int cpu)
1790 {
1791         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1792
1793         if (!(x86_pmu.extra_regs || x86_pmu.lbr_sel_map))
1794                 return NOTIFY_OK;
1795
1796         cpuc->shared_regs = allocate_shared_regs(cpu);
1797         if (!cpuc->shared_regs)
1798                 return NOTIFY_BAD;
1799
1800         return NOTIFY_OK;
1801 }
1802
1803 static void intel_pmu_cpu_starting(int cpu)
1804 {
1805         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1806         int core_id = topology_core_id(cpu);
1807         int i;
1808
1809         init_debug_store_on_cpu(cpu);
1810         /*
1811          * Deal with CPUs that don't clear their LBRs on power-up.
1812          */
1813         intel_pmu_lbr_reset();
1814
1815         cpuc->lbr_sel = NULL;
1816
1817         if (!cpuc->shared_regs)
1818                 return;
1819
1820         if (!(x86_pmu.er_flags & ERF_NO_HT_SHARING)) {
1821                 for_each_cpu(i, topology_thread_cpumask(cpu)) {
1822                         struct intel_shared_regs *pc;
1823
1824                         pc = per_cpu(cpu_hw_events, i).shared_regs;
1825                         if (pc && pc->core_id == core_id) {
1826                                 cpuc->kfree_on_online = cpuc->shared_regs;
1827                                 cpuc->shared_regs = pc;
1828                                 break;
1829                         }
1830                 }
1831                 cpuc->shared_regs->core_id = core_id;
1832                 cpuc->shared_regs->refcnt++;
1833         }
1834
1835         if (x86_pmu.lbr_sel_map)
1836                 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
1837 }
1838
1839 static void intel_pmu_cpu_dying(int cpu)
1840 {
1841         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1842         struct intel_shared_regs *pc;
1843
1844         pc = cpuc->shared_regs;
1845         if (pc) {
1846                 if (pc->core_id == -1 || --pc->refcnt == 0)
1847                         kfree(pc);
1848                 cpuc->shared_regs = NULL;
1849         }
1850
1851         fini_debug_store_on_cpu(cpu);
1852 }
1853
1854 static void intel_pmu_flush_branch_stack(void)
1855 {
1856         /*
1857          * Intel LBR does not tag entries with the
1858          * PID of the current task, then we need to
1859          * flush it on ctxsw
1860          * For now, we simply reset it
1861          */
1862         if (x86_pmu.lbr_nr)
1863                 intel_pmu_lbr_reset();
1864 }
1865
1866 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
1867
1868 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
1869
1870 static struct attribute *intel_arch3_formats_attr[] = {
1871         &format_attr_event.attr,
1872         &format_attr_umask.attr,
1873         &format_attr_edge.attr,
1874         &format_attr_pc.attr,
1875         &format_attr_any.attr,
1876         &format_attr_inv.attr,
1877         &format_attr_cmask.attr,
1878         &format_attr_in_tx.attr,
1879         &format_attr_in_tx_cp.attr,
1880
1881         &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
1882         &format_attr_ldlat.attr, /* PEBS load latency */
1883         NULL,
1884 };
1885
1886 static __initconst const struct x86_pmu intel_pmu = {
1887         .name                   = "Intel",
1888         .handle_irq             = intel_pmu_handle_irq,
1889         .disable_all            = intel_pmu_disable_all,
1890         .enable_all             = intel_pmu_enable_all,
1891         .enable                 = intel_pmu_enable_event,
1892         .disable                = intel_pmu_disable_event,
1893         .hw_config              = intel_pmu_hw_config,
1894         .schedule_events        = x86_schedule_events,
1895         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
1896         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
1897         .event_map              = intel_pmu_event_map,
1898         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
1899         .apic                   = 1,
1900         /*
1901          * Intel PMCs cannot be accessed sanely above 32 bit width,
1902          * so we install an artificial 1<<31 period regardless of
1903          * the generic event period:
1904          */
1905         .max_period             = (1ULL << 31) - 1,
1906         .get_event_constraints  = intel_get_event_constraints,
1907         .put_event_constraints  = intel_put_event_constraints,
1908         .pebs_aliases           = intel_pebs_aliases_core2,
1909
1910         .format_attrs           = intel_arch3_formats_attr,
1911         .events_sysfs_show      = intel_event_sysfs_show,
1912
1913         .cpu_prepare            = intel_pmu_cpu_prepare,
1914         .cpu_starting           = intel_pmu_cpu_starting,
1915         .cpu_dying              = intel_pmu_cpu_dying,
1916         .guest_get_msrs         = intel_guest_get_msrs,
1917         .flush_branch_stack     = intel_pmu_flush_branch_stack,
1918 };
1919
1920 static __init void intel_clovertown_quirk(void)
1921 {
1922         /*
1923          * PEBS is unreliable due to:
1924          *
1925          *   AJ67  - PEBS may experience CPL leaks
1926          *   AJ68  - PEBS PMI may be delayed by one event
1927          *   AJ69  - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
1928          *   AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
1929          *
1930          * AJ67 could be worked around by restricting the OS/USR flags.
1931          * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
1932          *
1933          * AJ106 could possibly be worked around by not allowing LBR
1934          *       usage from PEBS, including the fixup.
1935          * AJ68  could possibly be worked around by always programming
1936          *       a pebs_event_reset[0] value and coping with the lost events.
1937          *
1938          * But taken together it might just make sense to not enable PEBS on
1939          * these chips.
1940          */
1941         pr_warn("PEBS disabled due to CPU errata\n");
1942         x86_pmu.pebs = 0;
1943         x86_pmu.pebs_constraints = NULL;
1944 }
1945
1946 static int intel_snb_pebs_broken(int cpu)
1947 {
1948         u32 rev = UINT_MAX; /* default to broken for unknown models */
1949
1950         switch (cpu_data(cpu).x86_model) {
1951         case 42: /* SNB */
1952                 rev = 0x28;
1953                 break;
1954
1955         case 45: /* SNB-EP */
1956                 switch (cpu_data(cpu).x86_mask) {
1957                 case 6: rev = 0x618; break;
1958                 case 7: rev = 0x70c; break;
1959                 }
1960         }
1961
1962         return (cpu_data(cpu).microcode < rev);
1963 }
1964
1965 static void intel_snb_check_microcode(void)
1966 {
1967         int pebs_broken = 0;
1968         int cpu;
1969
1970         get_online_cpus();
1971         for_each_online_cpu(cpu) {
1972                 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
1973                         break;
1974         }
1975         put_online_cpus();
1976
1977         if (pebs_broken == x86_pmu.pebs_broken)
1978                 return;
1979
1980         /*
1981          * Serialized by the microcode lock..
1982          */
1983         if (x86_pmu.pebs_broken) {
1984                 pr_info("PEBS enabled due to microcode update\n");
1985                 x86_pmu.pebs_broken = 0;
1986         } else {
1987                 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
1988                 x86_pmu.pebs_broken = 1;
1989         }
1990 }
1991
1992 static __init void intel_sandybridge_quirk(void)
1993 {
1994         x86_pmu.check_microcode = intel_snb_check_microcode;
1995         intel_snb_check_microcode();
1996 }
1997
1998 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
1999         { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
2000         { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
2001         { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
2002         { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
2003         { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
2004         { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
2005         { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
2006 };
2007
2008 static __init void intel_arch_events_quirk(void)
2009 {
2010         int bit;
2011
2012         /* disable event that reported as not presend by cpuid */
2013         for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
2014                 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
2015                 pr_warn("CPUID marked event: \'%s\' unavailable\n",
2016                         intel_arch_events_map[bit].name);
2017         }
2018 }
2019
2020 static __init void intel_nehalem_quirk(void)
2021 {
2022         union cpuid10_ebx ebx;
2023
2024         ebx.full = x86_pmu.events_maskl;
2025         if (ebx.split.no_branch_misses_retired) {
2026                 /*
2027                  * Erratum AAJ80 detected, we work it around by using
2028                  * the BR_MISP_EXEC.ANY event. This will over-count
2029                  * branch-misses, but it's still much better than the
2030                  * architectural event which is often completely bogus:
2031                  */
2032                 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
2033                 ebx.split.no_branch_misses_retired = 0;
2034                 x86_pmu.events_maskl = ebx.full;
2035                 pr_info("CPU erratum AAJ80 worked around\n");
2036         }
2037 }
2038
2039 EVENT_ATTR_STR(mem-loads,      mem_ld_hsw,     "event=0xcd,umask=0x1,ldlat=3");
2040 EVENT_ATTR_STR(mem-stores,     mem_st_hsw,     "event=0xd0,umask=0x82")
2041
2042 static struct attribute *hsw_events_attrs[] = {
2043         EVENT_PTR(mem_ld_hsw),
2044         EVENT_PTR(mem_st_hsw),
2045         NULL
2046 };
2047
2048 __init int intel_pmu_init(void)
2049 {
2050         union cpuid10_edx edx;
2051         union cpuid10_eax eax;
2052         union cpuid10_ebx ebx;
2053         struct event_constraint *c;
2054         unsigned int unused;
2055         int version;
2056
2057         if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
2058                 switch (boot_cpu_data.x86) {
2059                 case 0x6:
2060                         return p6_pmu_init();
2061                 case 0xb:
2062                         return knc_pmu_init();
2063                 case 0xf:
2064                         return p4_pmu_init();
2065                 }
2066                 return -ENODEV;
2067         }
2068
2069         /*
2070          * Check whether the Architectural PerfMon supports
2071          * Branch Misses Retired hw_event or not.
2072          */
2073         cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
2074         if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
2075                 return -ENODEV;
2076
2077         version = eax.split.version_id;
2078         if (version < 2)
2079                 x86_pmu = core_pmu;
2080         else
2081                 x86_pmu = intel_pmu;
2082
2083         x86_pmu.version                 = version;
2084         x86_pmu.num_counters            = eax.split.num_counters;
2085         x86_pmu.cntval_bits             = eax.split.bit_width;
2086         x86_pmu.cntval_mask             = (1ULL << eax.split.bit_width) - 1;
2087
2088         x86_pmu.events_maskl            = ebx.full;
2089         x86_pmu.events_mask_len         = eax.split.mask_length;
2090
2091         x86_pmu.max_pebs_events         = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
2092
2093         /*
2094          * Quirk: v2 perfmon does not report fixed-purpose events, so
2095          * assume at least 3 events:
2096          */
2097         if (version > 1)
2098                 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
2099
2100         /*
2101          * v2 and above have a perf capabilities MSR
2102          */
2103         if (version > 1) {
2104                 u64 capabilities;
2105
2106                 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
2107                 x86_pmu.intel_cap.capabilities = capabilities;
2108         }
2109
2110         intel_ds_init();
2111
2112         x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
2113
2114         /*
2115          * Install the hw-cache-events table:
2116          */
2117         switch (boot_cpu_data.x86_model) {
2118         case 14: /* 65 nm core solo/duo, "Yonah" */
2119                 pr_cont("Core events, ");
2120                 break;
2121
2122         case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
2123                 x86_add_quirk(intel_clovertown_quirk);
2124         case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
2125         case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
2126         case 29: /* six-core 45 nm xeon "Dunnington" */
2127                 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
2128                        sizeof(hw_cache_event_ids));
2129
2130                 intel_pmu_lbr_init_core();
2131
2132                 x86_pmu.event_constraints = intel_core2_event_constraints;
2133                 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
2134                 pr_cont("Core2 events, ");
2135                 break;
2136
2137         case 26: /* 45 nm nehalem, "Bloomfield" */
2138         case 30: /* 45 nm nehalem, "Lynnfield" */
2139         case 46: /* 45 nm nehalem-ex, "Beckton" */
2140                 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
2141                        sizeof(hw_cache_event_ids));
2142                 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2143                        sizeof(hw_cache_extra_regs));
2144
2145                 intel_pmu_lbr_init_nhm();
2146
2147                 x86_pmu.event_constraints = intel_nehalem_event_constraints;
2148                 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
2149                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
2150                 x86_pmu.extra_regs = intel_nehalem_extra_regs;
2151
2152                 x86_pmu.cpu_events = nhm_events_attrs;
2153
2154                 /* UOPS_ISSUED.STALLED_CYCLES */
2155                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2156                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2157                 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
2158                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2159                         X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
2160
2161                 x86_add_quirk(intel_nehalem_quirk);
2162
2163                 pr_cont("Nehalem events, ");
2164                 break;
2165
2166         case 28: /* Atom */
2167         case 38: /* Lincroft */
2168         case 39: /* Penwell */
2169         case 53: /* Cloverview */
2170         case 54: /* Cedarview */
2171                 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
2172                        sizeof(hw_cache_event_ids));
2173
2174                 intel_pmu_lbr_init_atom();
2175
2176                 x86_pmu.event_constraints = intel_gen_event_constraints;
2177                 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
2178                 pr_cont("Atom events, ");
2179                 break;
2180
2181         case 37: /* 32 nm nehalem, "Clarkdale" */
2182         case 44: /* 32 nm nehalem, "Gulftown" */
2183         case 47: /* 32 nm Xeon E7 */
2184                 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
2185                        sizeof(hw_cache_event_ids));
2186                 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2187                        sizeof(hw_cache_extra_regs));
2188
2189                 intel_pmu_lbr_init_nhm();
2190
2191                 x86_pmu.event_constraints = intel_westmere_event_constraints;
2192                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
2193                 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
2194                 x86_pmu.extra_regs = intel_westmere_extra_regs;
2195                 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2196
2197                 x86_pmu.cpu_events = nhm_events_attrs;
2198
2199                 /* UOPS_ISSUED.STALLED_CYCLES */
2200                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2201                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2202                 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
2203                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2204                         X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
2205
2206                 pr_cont("Westmere events, ");
2207                 break;
2208
2209         case 42: /* SandyBridge */
2210         case 45: /* SandyBridge, "Romely-EP" */
2211                 x86_add_quirk(intel_sandybridge_quirk);
2212                 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2213                        sizeof(hw_cache_event_ids));
2214                 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2215                        sizeof(hw_cache_extra_regs));
2216
2217                 intel_pmu_lbr_init_snb();
2218
2219                 x86_pmu.event_constraints = intel_snb_event_constraints;
2220                 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
2221                 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
2222                 if (boot_cpu_data.x86_model == 45)
2223                         x86_pmu.extra_regs = intel_snbep_extra_regs;
2224                 else
2225                         x86_pmu.extra_regs = intel_snb_extra_regs;
2226                 /* all extra regs are per-cpu when HT is on */
2227                 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2228                 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2229
2230                 x86_pmu.cpu_events = snb_events_attrs;
2231
2232                 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
2233                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2234                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2235                 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
2236                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2237                         X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
2238
2239                 pr_cont("SandyBridge events, ");
2240                 break;
2241         case 58: /* IvyBridge */
2242         case 62: /* IvyBridge EP */
2243                 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2244                        sizeof(hw_cache_event_ids));
2245                 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2246                        sizeof(hw_cache_extra_regs));
2247
2248                 intel_pmu_lbr_init_snb();
2249
2250                 x86_pmu.event_constraints = intel_ivb_event_constraints;
2251                 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
2252                 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
2253                 if (boot_cpu_data.x86_model == 62)
2254                         x86_pmu.extra_regs = intel_snbep_extra_regs;
2255                 else
2256                         x86_pmu.extra_regs = intel_snb_extra_regs;
2257                 /* all extra regs are per-cpu when HT is on */
2258                 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2259                 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2260
2261                 x86_pmu.cpu_events = snb_events_attrs;
2262
2263                 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
2264                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2265                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2266
2267                 pr_cont("IvyBridge events, ");
2268                 break;
2269
2270
2271         case 60: /* Haswell Client */
2272         case 70:
2273         case 71:
2274         case 63:
2275                 x86_pmu.late_ack = true;
2276                 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids));
2277                 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
2278
2279                 intel_pmu_lbr_init_snb();
2280
2281                 x86_pmu.event_constraints = intel_hsw_event_constraints;
2282                 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
2283                 x86_pmu.extra_regs = intel_snb_extra_regs;
2284                 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
2285                 /* all extra regs are per-cpu when HT is on */
2286                 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2287                 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2288
2289                 x86_pmu.hw_config = hsw_hw_config;
2290                 x86_pmu.get_event_constraints = hsw_get_event_constraints;
2291                 x86_pmu.cpu_events = hsw_events_attrs;
2292                 pr_cont("Haswell events, ");
2293                 break;
2294
2295         default:
2296                 switch (x86_pmu.version) {
2297                 case 1:
2298                         x86_pmu.event_constraints = intel_v1_event_constraints;
2299                         pr_cont("generic architected perfmon v1, ");
2300                         break;
2301                 default:
2302                         /*
2303                          * default constraints for v2 and up
2304                          */
2305                         x86_pmu.event_constraints = intel_gen_event_constraints;
2306                         pr_cont("generic architected perfmon, ");
2307                         break;
2308                 }
2309         }
2310
2311         if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
2312                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
2313                      x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
2314                 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
2315         }
2316         x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
2317
2318         if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
2319                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
2320                      x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
2321                 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
2322         }
2323
2324         x86_pmu.intel_ctrl |=
2325                 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
2326
2327         if (x86_pmu.event_constraints) {
2328                 /*
2329                  * event on fixed counter2 (REF_CYCLES) only works on this
2330                  * counter, so do not extend mask to generic counters
2331                  */
2332                 for_each_event_constraint(c, x86_pmu.event_constraints) {
2333                         if (c->cmask != FIXED_EVENT_FLAGS
2334                             || c->idxmsk64 == INTEL_PMC_MSK_FIXED_REF_CYCLES) {
2335                                 continue;
2336                         }
2337
2338                         c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
2339                         c->weight += x86_pmu.num_counters;
2340                 }
2341         }
2342
2343         return 0;
2344 }