arch/x86/kernel/cpu/perf_event_intel.c

   1 /*
   2  * Per core/cpu state
   3  *
   4  * Used to coordinate shared registers between HT threads or
   5  * among events on a single PMU.
   6  */
   7
   8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   9
  10 #include <linux/stddef.h>
  11 #include <linux/types.h>
  12 #include <linux/init.h>
  13 #include <linux/slab.h>
  14 #include <linux/export.h>
  15
  16 #include <asm/hardirq.h>
  17 #include <asm/apic.h>
  18
  19 #include "perf_event.h"
  20
  21 /*
  22  * Intel PerfMon, used on Core and later.
  23  */
  24 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
  25 {
  26         [PERF_COUNT_HW_CPU_CYCLES]              = 0x003c,
  27         [PERF_COUNT_HW_INSTRUCTIONS]            = 0x00c0,
  28         [PERF_COUNT_HW_CACHE_REFERENCES]        = 0x4f2e,
  29         [PERF_COUNT_HW_CACHE_MISSES]            = 0x412e,
  30         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x00c4,
  31         [PERF_COUNT_HW_BRANCH_MISSES]           = 0x00c5,
  32         [PERF_COUNT_HW_BUS_CYCLES]              = 0x013c,
  33         [PERF_COUNT_HW_REF_CPU_CYCLES]          = 0x0300, /* pseudo-encoding */
  34 };
  35
  36 static struct event_constraint intel_core_event_constraints[] __read_mostly =
  37 {
  38         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  39         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  40         INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  41         INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  42         INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  43         INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
  44         EVENT_CONSTRAINT_END
  45 };
  46
  47 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
  48 {
  49         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  50         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  51         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
  52         INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
  53         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  54         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  55         INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  56         INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  57         INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
  58         INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  59         INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
  60         INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
  61         INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
  62         EVENT_CONSTRAINT_END
  63 };
  64
  65 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
  66 {
  67         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  68         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  69         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
  70         INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
  71         INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
  72         INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
  73         INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
  74         INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
  75         INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
  76         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
  77         INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
  78         EVENT_CONSTRAINT_END
  79 };
  80
  81 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
  82 {
  83         INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
  84         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
  85         EVENT_EXTRA_END
  86 };
  87
  88 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
  89 {
  90         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  91         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  92         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
  93         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
  94         INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
  95         INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
  96         INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
  97         EVENT_CONSTRAINT_END
  98 };
  99
 100 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
 101 {
 102         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 103         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 104         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 105         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
 106         INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
 107         INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 108         INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 109         INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
 110         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 111         INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
 112         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
 113         INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 114         EVENT_CONSTRAINT_END
 115 };
 116
 117 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
 118 {
 119         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 120         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 121         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 122         INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
 123         INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
 124         INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
 125         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
 126         INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
 127         INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
 128         INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 129         INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 130         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 131         /*
 132          * Errata BV98 -- MEM_*_RETIRED events can leak between counters of SMT
 133          * siblings; disable these events because they can corrupt unrelated
 134          * counters.
 135          */
 136         INTEL_EVENT_CONSTRAINT(0xd0, 0x0), /* MEM_UOPS_RETIRED.* */
 137         INTEL_EVENT_CONSTRAINT(0xd1, 0x0), /* MEM_LOAD_UOPS_RETIRED.* */
 138         INTEL_EVENT_CONSTRAINT(0xd2, 0x0), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 139         INTEL_EVENT_CONSTRAINT(0xd3, 0x0), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 140         EVENT_CONSTRAINT_END
 141 };
 142
 143 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
 144 {
 145         INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
 146         INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
 147         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
 148         EVENT_EXTRA_END
 149 };
 150
 151 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
 152 {
 153         EVENT_CONSTRAINT_END
 154 };
 155
 156 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
 157 {
 158         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 159         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 160         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 161         EVENT_CONSTRAINT_END
 162 };
 163
 164 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
 165         INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
 166         INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
 167         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 168         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 169         EVENT_EXTRA_END
 170 };
 171
 172 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
 173         INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
 174         INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
 175         EVENT_EXTRA_END
 176 };
 177
 178 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
 179 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
 180 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
 181
 182 struct attribute *nhm_events_attrs[] = {
 183         EVENT_PTR(mem_ld_nhm),
 184         NULL,
 185 };
 186
 187 struct attribute *snb_events_attrs[] = {
 188         EVENT_PTR(mem_ld_snb),
 189         EVENT_PTR(mem_st_snb),
 190         NULL,
 191 };
 192
 193 static u64 intel_pmu_event_map(int hw_event)
 194 {
 195         return intel_perfmon_event_map[hw_event];
 196 }
 197
 198 #define SNB_DMND_DATA_RD        (1ULL << 0)
 199 #define SNB_DMND_RFO            (1ULL << 1)
 200 #define SNB_DMND_IFETCH         (1ULL << 2)
 201 #define SNB_DMND_WB             (1ULL << 3)
 202 #define SNB_PF_DATA_RD          (1ULL << 4)
 203 #define SNB_PF_RFO              (1ULL << 5)
 204 #define SNB_PF_IFETCH           (1ULL << 6)
 205 #define SNB_LLC_DATA_RD         (1ULL << 7)
 206 #define SNB_LLC_RFO             (1ULL << 8)
 207 #define SNB_LLC_IFETCH          (1ULL << 9)
 208 #define SNB_BUS_LOCKS           (1ULL << 10)
 209 #define SNB_STRM_ST             (1ULL << 11)
 210 #define SNB_OTHER               (1ULL << 15)
 211 #define SNB_RESP_ANY            (1ULL << 16)
 212 #define SNB_NO_SUPP             (1ULL << 17)
 213 #define SNB_LLC_HITM            (1ULL << 18)
 214 #define SNB_LLC_HITE            (1ULL << 19)
 215 #define SNB_LLC_HITS            (1ULL << 20)
 216 #define SNB_LLC_HITF            (1ULL << 21)
 217 #define SNB_LOCAL               (1ULL << 22)
 218 #define SNB_REMOTE              (0xffULL << 23)
 219 #define SNB_SNP_NONE            (1ULL << 31)
 220 #define SNB_SNP_NOT_NEEDED      (1ULL << 32)
 221 #define SNB_SNP_MISS            (1ULL << 33)
 222 #define SNB_NO_FWD              (1ULL << 34)
 223 #define SNB_SNP_FWD             (1ULL << 35)
 224 #define SNB_HITM                (1ULL << 36)
 225 #define SNB_NON_DRAM            (1ULL << 37)
 226
 227 #define SNB_DMND_READ           (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
 228 #define SNB_DMND_WRITE          (SNB_DMND_RFO|SNB_LLC_RFO)
 229 #define SNB_DMND_PREFETCH       (SNB_PF_DATA_RD|SNB_PF_RFO)
 230
 231 #define SNB_SNP_ANY             (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
 232                                  SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
 233                                  SNB_HITM)
 234
 235 #define SNB_DRAM_ANY            (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
 236 #define SNB_DRAM_REMOTE         (SNB_REMOTE|SNB_SNP_ANY)
 237
 238 #define SNB_L3_ACCESS           SNB_RESP_ANY
 239 #define SNB_L3_MISS             (SNB_DRAM_ANY|SNB_NON_DRAM)
 240
 241 static __initconst const u64 snb_hw_cache_extra_regs
 242                                 [PERF_COUNT_HW_CACHE_MAX]
 243                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 244                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 245 {
 246  [ C(LL  ) ] = {
 247         [ C(OP_READ) ] = {
 248                 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
 249                 [ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_L3_MISS,
 250         },
 251         [ C(OP_WRITE) ] = {
 252                 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
 253                 [ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_L3_MISS,
 254         },
 255         [ C(OP_PREFETCH) ] = {
 256                 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
 257                 [ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
 258         },
 259  },
 260  [ C(NODE) ] = {
 261         [ C(OP_READ) ] = {
 262                 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
 263                 [ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
 264         },
 265         [ C(OP_WRITE) ] = {
 266                 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
 267                 [ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
 268         },
 269         [ C(OP_PREFETCH) ] = {
 270                 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
 271                 [ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
 272         },
 273  },
 274 };
 275
 276 static __initconst const u64 snb_hw_cache_event_ids
 277                                 [PERF_COUNT_HW_CACHE_MAX]
 278                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 279                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 280 {
 281  [ C(L1D) ] = {
 282         [ C(OP_READ) ] = {
 283                 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS        */
 284                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPLACEMENT              */
 285         },
 286         [ C(OP_WRITE) ] = {
 287                 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES       */
 288                 [ C(RESULT_MISS)   ] = 0x0851, /* L1D.ALL_M_REPLACEMENT        */
 289         },
 290         [ C(OP_PREFETCH) ] = {
 291                 [ C(RESULT_ACCESS) ] = 0x0,
 292                 [ C(RESULT_MISS)   ] = 0x024e, /* HW_PRE_REQ.DL1_MISS          */
 293         },
 294  },
 295  [ C(L1I ) ] = {
 296         [ C(OP_READ) ] = {
 297                 [ C(RESULT_ACCESS) ] = 0x0,
 298                 [ C(RESULT_MISS)   ] = 0x0280, /* ICACHE.MISSES */
 299         },
 300         [ C(OP_WRITE) ] = {
 301                 [ C(RESULT_ACCESS) ] = -1,
 302                 [ C(RESULT_MISS)   ] = -1,
 303         },
 304         [ C(OP_PREFETCH) ] = {
 305                 [ C(RESULT_ACCESS) ] = 0x0,
 306                 [ C(RESULT_MISS)   ] = 0x0,
 307         },
 308  },
 309  [ C(LL  ) ] = {
 310         [ C(OP_READ) ] = {
 311                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
 312                 [ C(RESULT_ACCESS) ] = 0x01b7,
 313                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
 314                 [ C(RESULT_MISS)   ] = 0x01b7,
 315         },
 316         [ C(OP_WRITE) ] = {
 317                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
 318                 [ C(RESULT_ACCESS) ] = 0x01b7,
 319                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
 320                 [ C(RESULT_MISS)   ] = 0x01b7,
 321         },
 322         [ C(OP_PREFETCH) ] = {
 323                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
 324                 [ C(RESULT_ACCESS) ] = 0x01b7,
 325                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
 326                 [ C(RESULT_MISS)   ] = 0x01b7,
 327         },
 328  },
 329  [ C(DTLB) ] = {
 330         [ C(OP_READ) ] = {
 331                 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
 332                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
 333         },
 334         [ C(OP_WRITE) ] = {
 335                 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
 336                 [ C(RESULT_MISS)   ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
 337         },
 338         [ C(OP_PREFETCH) ] = {
 339                 [ C(RESULT_ACCESS) ] = 0x0,
 340                 [ C(RESULT_MISS)   ] = 0x0,
 341         },
 342  },
 343  [ C(ITLB) ] = {
 344         [ C(OP_READ) ] = {
 345                 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT         */
 346                 [ C(RESULT_MISS)   ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK    */
 347         },
 348         [ C(OP_WRITE) ] = {
 349                 [ C(RESULT_ACCESS) ] = -1,
 350                 [ C(RESULT_MISS)   ] = -1,
 351         },
 352         [ C(OP_PREFETCH) ] = {
 353                 [ C(RESULT_ACCESS) ] = -1,
 354                 [ C(RESULT_MISS)   ] = -1,
 355         },
 356  },
 357  [ C(BPU ) ] = {
 358         [ C(OP_READ) ] = {
 359                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 360                 [ C(RESULT_MISS)   ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
 361         },
 362         [ C(OP_WRITE) ] = {
 363                 [ C(RESULT_ACCESS) ] = -1,
 364                 [ C(RESULT_MISS)   ] = -1,
 365         },
 366         [ C(OP_PREFETCH) ] = {
 367                 [ C(RESULT_ACCESS) ] = -1,
 368                 [ C(RESULT_MISS)   ] = -1,
 369         },
 370  },
 371  [ C(NODE) ] = {
 372         [ C(OP_READ) ] = {
 373                 [ C(RESULT_ACCESS) ] = 0x01b7,
 374                 [ C(RESULT_MISS)   ] = 0x01b7,
 375         },
 376         [ C(OP_WRITE) ] = {
 377                 [ C(RESULT_ACCESS) ] = 0x01b7,
 378                 [ C(RESULT_MISS)   ] = 0x01b7,
 379         },
 380         [ C(OP_PREFETCH) ] = {
 381                 [ C(RESULT_ACCESS) ] = 0x01b7,
 382                 [ C(RESULT_MISS)   ] = 0x01b7,
 383         },
 384  },
 385
 386 };
 387
 388 static __initconst const u64 westmere_hw_cache_event_ids
 389                                 [PERF_COUNT_HW_CACHE_MAX]
 390                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 391                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 392 {
 393  [ C(L1D) ] = {
 394         [ C(OP_READ) ] = {
 395                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
 396                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPL                     */
 397         },
 398         [ C(OP_WRITE) ] = {
 399                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
 400                 [ C(RESULT_MISS)   ] = 0x0251, /* L1D.M_REPL                   */
 401         },
 402         [ C(OP_PREFETCH) ] = {
 403                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
 404                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
 405         },
 406  },
 407  [ C(L1I ) ] = {
 408         [ C(OP_READ) ] = {
 409                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
 410                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
 411         },
 412         [ C(OP_WRITE) ] = {
 413                 [ C(RESULT_ACCESS) ] = -1,
 414                 [ C(RESULT_MISS)   ] = -1,
 415         },
 416         [ C(OP_PREFETCH) ] = {
 417                 [ C(RESULT_ACCESS) ] = 0x0,
 418                 [ C(RESULT_MISS)   ] = 0x0,
 419         },
 420  },
 421  [ C(LL  ) ] = {
 422         [ C(OP_READ) ] = {
 423                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
 424                 [ C(RESULT_ACCESS) ] = 0x01b7,
 425                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
 426                 [ C(RESULT_MISS)   ] = 0x01b7,
 427         },
 428         /*
 429          * Use RFO, not WRITEBACK, because a write miss would typically occur
 430          * on RFO.
 431          */
 432         [ C(OP_WRITE) ] = {
 433                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
 434                 [ C(RESULT_ACCESS) ] = 0x01b7,
 435                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
 436                 [ C(RESULT_MISS)   ] = 0x01b7,
 437         },
 438         [ C(OP_PREFETCH) ] = {
 439                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
 440                 [ C(RESULT_ACCESS) ] = 0x01b7,
 441                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
 442                 [ C(RESULT_MISS)   ] = 0x01b7,
 443         },
 444  },
 445  [ C(DTLB) ] = {
 446         [ C(OP_READ) ] = {
 447                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
 448                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
 449         },
 450         [ C(OP_WRITE) ] = {
 451                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
 452                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
 453         },
 454         [ C(OP_PREFETCH) ] = {
 455                 [ C(RESULT_ACCESS) ] = 0x0,
 456                 [ C(RESULT_MISS)   ] = 0x0,
 457         },
 458  },
 459  [ C(ITLB) ] = {
 460         [ C(OP_READ) ] = {
 461                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
 462                 [ C(RESULT_MISS)   ] = 0x0185, /* ITLB_MISSES.ANY              */
 463         },
 464         [ C(OP_WRITE) ] = {
 465                 [ C(RESULT_ACCESS) ] = -1,
 466                 [ C(RESULT_MISS)   ] = -1,
 467         },
 468         [ C(OP_PREFETCH) ] = {
 469                 [ C(RESULT_ACCESS) ] = -1,
 470                 [ C(RESULT_MISS)   ] = -1,
 471         },
 472  },
 473  [ C(BPU ) ] = {
 474         [ C(OP_READ) ] = {
 475                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 476                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
 477         },
 478         [ C(OP_WRITE) ] = {
 479                 [ C(RESULT_ACCESS) ] = -1,
 480                 [ C(RESULT_MISS)   ] = -1,
 481         },
 482         [ C(OP_PREFETCH) ] = {
 483                 [ C(RESULT_ACCESS) ] = -1,
 484                 [ C(RESULT_MISS)   ] = -1,
 485         },
 486  },
 487  [ C(NODE) ] = {
 488         [ C(OP_READ) ] = {
 489                 [ C(RESULT_ACCESS) ] = 0x01b7,
 490                 [ C(RESULT_MISS)   ] = 0x01b7,
 491         },
 492         [ C(OP_WRITE) ] = {
 493                 [ C(RESULT_ACCESS) ] = 0x01b7,
 494                 [ C(RESULT_MISS)   ] = 0x01b7,
 495         },
 496         [ C(OP_PREFETCH) ] = {
 497                 [ C(RESULT_ACCESS) ] = 0x01b7,
 498                 [ C(RESULT_MISS)   ] = 0x01b7,
 499         },
 500  },
 501 };
 502
 503 /*
 504  * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
 505  * See IA32 SDM Vol 3B 30.6.1.3
 506  */
 507
 508 #define NHM_DMND_DATA_RD        (1 << 0)
 509 #define NHM_DMND_RFO            (1 << 1)
 510 #define NHM_DMND_IFETCH         (1 << 2)
 511 #define NHM_DMND_WB             (1 << 3)
 512 #define NHM_PF_DATA_RD          (1 << 4)
 513 #define NHM_PF_DATA_RFO         (1 << 5)
 514 #define NHM_PF_IFETCH           (1 << 6)
 515 #define NHM_OFFCORE_OTHER       (1 << 7)
 516 #define NHM_UNCORE_HIT          (1 << 8)
 517 #define NHM_OTHER_CORE_HIT_SNP  (1 << 9)
 518 #define NHM_OTHER_CORE_HITM     (1 << 10)
 519                                 /* reserved */
 520 #define NHM_REMOTE_CACHE_FWD    (1 << 12)
 521 #define NHM_REMOTE_DRAM         (1 << 13)
 522 #define NHM_LOCAL_DRAM          (1 << 14)
 523 #define NHM_NON_DRAM            (1 << 15)
 524
 525 #define NHM_LOCAL               (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
 526 #define NHM_REMOTE              (NHM_REMOTE_DRAM)
 527
 528 #define NHM_DMND_READ           (NHM_DMND_DATA_RD)
 529 #define NHM_DMND_WRITE          (NHM_DMND_RFO|NHM_DMND_WB)
 530 #define NHM_DMND_PREFETCH       (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
 531
 532 #define NHM_L3_HIT      (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
 533 #define NHM_L3_MISS     (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
 534 #define NHM_L3_ACCESS   (NHM_L3_HIT|NHM_L3_MISS)
 535
 536 static __initconst const u64 nehalem_hw_cache_extra_regs
 537                                 [PERF_COUNT_HW_CACHE_MAX]
 538                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 539                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 540 {
 541  [ C(LL  ) ] = {
 542         [ C(OP_READ) ] = {
 543                 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
 544                 [ C(RESULT_MISS)   ] = NHM_DMND_READ|NHM_L3_MISS,
 545         },
 546         [ C(OP_WRITE) ] = {
 547                 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
 548                 [ C(RESULT_MISS)   ] = NHM_DMND_WRITE|NHM_L3_MISS,
 549         },
 550         [ C(OP_PREFETCH) ] = {
 551                 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
 552                 [ C(RESULT_MISS)   ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
 553         },
 554  },
 555  [ C(NODE) ] = {
 556         [ C(OP_READ) ] = {
 557                 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
 558                 [ C(RESULT_MISS)   ] = NHM_DMND_READ|NHM_REMOTE,
 559         },
 560         [ C(OP_WRITE) ] = {
 561                 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
 562                 [ C(RESULT_MISS)   ] = NHM_DMND_WRITE|NHM_REMOTE,
 563         },
 564         [ C(OP_PREFETCH) ] = {
 565                 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
 566                 [ C(RESULT_MISS)   ] = NHM_DMND_PREFETCH|NHM_REMOTE,
 567         },
 568  },
 569 };
 570
 571 static __initconst const u64 nehalem_hw_cache_event_ids
 572                                 [PERF_COUNT_HW_CACHE_MAX]
 573                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 574                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 575 {
 576  [ C(L1D) ] = {
 577         [ C(OP_READ) ] = {
 578                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
 579                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPL                     */
 580         },
 581         [ C(OP_WRITE) ] = {
 582                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
 583                 [ C(RESULT_MISS)   ] = 0x0251, /* L1D.M_REPL                   */
 584         },
 585         [ C(OP_PREFETCH) ] = {
 586                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
 587                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
 588         },
 589  },
 590  [ C(L1I ) ] = {
 591         [ C(OP_READ) ] = {
 592                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
 593                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
 594         },
 595         [ C(OP_WRITE) ] = {
 596                 [ C(RESULT_ACCESS) ] = -1,
 597                 [ C(RESULT_MISS)   ] = -1,
 598         },
 599         [ C(OP_PREFETCH) ] = {
 600                 [ C(RESULT_ACCESS) ] = 0x0,
 601                 [ C(RESULT_MISS)   ] = 0x0,
 602         },
 603  },
 604  [ C(LL  ) ] = {
 605         [ C(OP_READ) ] = {
 606                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
 607                 [ C(RESULT_ACCESS) ] = 0x01b7,
 608                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
 609                 [ C(RESULT_MISS)   ] = 0x01b7,
 610         },
 611         /*
 612          * Use RFO, not WRITEBACK, because a write miss would typically occur
 613          * on RFO.
 614          */
 615         [ C(OP_WRITE) ] = {
 616                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
 617                 [ C(RESULT_ACCESS) ] = 0x01b7,
 618                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
 619                 [ C(RESULT_MISS)   ] = 0x01b7,
 620         },
 621         [ C(OP_PREFETCH) ] = {
 622                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
 623                 [ C(RESULT_ACCESS) ] = 0x01b7,
 624                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
 625                 [ C(RESULT_MISS)   ] = 0x01b7,
 626         },
 627  },
 628  [ C(DTLB) ] = {
 629         [ C(OP_READ) ] = {
 630                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI   (alias)  */
 631                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
 632         },
 633         [ C(OP_WRITE) ] = {
 634                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI   (alias)  */
 635                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
 636         },
 637         [ C(OP_PREFETCH) ] = {
 638                 [ C(RESULT_ACCESS) ] = 0x0,
 639                 [ C(RESULT_MISS)   ] = 0x0,
 640         },
 641  },
 642  [ C(ITLB) ] = {
 643         [ C(OP_READ) ] = {
 644                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
 645                 [ C(RESULT_MISS)   ] = 0x20c8, /* ITLB_MISS_RETIRED            */
 646         },
 647         [ C(OP_WRITE) ] = {
 648                 [ C(RESULT_ACCESS) ] = -1,
 649                 [ C(RESULT_MISS)   ] = -1,
 650         },
 651         [ C(OP_PREFETCH) ] = {
 652                 [ C(RESULT_ACCESS) ] = -1,
 653                 [ C(RESULT_MISS)   ] = -1,
 654         },
 655  },
 656  [ C(BPU ) ] = {
 657         [ C(OP_READ) ] = {
 658                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 659                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
 660         },
 661         [ C(OP_WRITE) ] = {
 662                 [ C(RESULT_ACCESS) ] = -1,
 663                 [ C(RESULT_MISS)   ] = -1,
 664         },
 665         [ C(OP_PREFETCH) ] = {
 666                 [ C(RESULT_ACCESS) ] = -1,
 667                 [ C(RESULT_MISS)   ] = -1,
 668         },
 669  },
 670  [ C(NODE) ] = {
 671         [ C(OP_READ) ] = {
 672                 [ C(RESULT_ACCESS) ] = 0x01b7,
 673                 [ C(RESULT_MISS)   ] = 0x01b7,
 674         },
 675         [ C(OP_WRITE) ] = {
 676                 [ C(RESULT_ACCESS) ] = 0x01b7,
 677                 [ C(RESULT_MISS)   ] = 0x01b7,
 678         },
 679         [ C(OP_PREFETCH) ] = {
 680                 [ C(RESULT_ACCESS) ] = 0x01b7,
 681                 [ C(RESULT_MISS)   ] = 0x01b7,
 682         },
 683  },
 684 };
 685
 686 static __initconst const u64 core2_hw_cache_event_ids
 687                                 [PERF_COUNT_HW_CACHE_MAX]
 688                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 689                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 690 {
 691  [ C(L1D) ] = {
 692         [ C(OP_READ) ] = {
 693                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI          */
 694                 [ C(RESULT_MISS)   ] = 0x0140, /* L1D_CACHE_LD.I_STATE       */
 695         },
 696         [ C(OP_WRITE) ] = {
 697                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI          */
 698                 [ C(RESULT_MISS)   ] = 0x0141, /* L1D_CACHE_ST.I_STATE       */
 699         },
 700         [ C(OP_PREFETCH) ] = {
 701                 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS      */
 702                 [ C(RESULT_MISS)   ] = 0,
 703         },
 704  },
 705  [ C(L1I ) ] = {
 706         [ C(OP_READ) ] = {
 707                 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS                  */
 708                 [ C(RESULT_MISS)   ] = 0x0081, /* L1I.MISSES                 */
 709         },
 710         [ C(OP_WRITE) ] = {
 711                 [ C(RESULT_ACCESS) ] = -1,
 712                 [ C(RESULT_MISS)   ] = -1,
 713         },
 714         [ C(OP_PREFETCH) ] = {
 715                 [ C(RESULT_ACCESS) ] = 0,
 716                 [ C(RESULT_MISS)   ] = 0,
 717         },
 718  },
 719  [ C(LL  ) ] = {
 720         [ C(OP_READ) ] = {
 721                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
 722                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
 723         },
 724         [ C(OP_WRITE) ] = {
 725                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
 726                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
 727         },
 728         [ C(OP_PREFETCH) ] = {
 729                 [ C(RESULT_ACCESS) ] = 0,
 730                 [ C(RESULT_MISS)   ] = 0,
 731         },
 732  },
 733  [ C(DTLB) ] = {
 734         [ C(OP_READ) ] = {
 735                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI  (alias) */
 736                 [ C(RESULT_MISS)   ] = 0x0208, /* DTLB_MISSES.MISS_LD        */
 737         },
 738         [ C(OP_WRITE) ] = {
 739                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI  (alias) */
 740                 [ C(RESULT_MISS)   ] = 0x0808, /* DTLB_MISSES.MISS_ST        */
 741         },
 742         [ C(OP_PREFETCH) ] = {
 743                 [ C(RESULT_ACCESS) ] = 0,
 744                 [ C(RESULT_MISS)   ] = 0,
 745         },
 746  },
 747  [ C(ITLB) ] = {
 748         [ C(OP_READ) ] = {
 749                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
 750                 [ C(RESULT_MISS)   ] = 0x1282, /* ITLBMISSES                 */
 751         },
 752         [ C(OP_WRITE) ] = {
 753                 [ C(RESULT_ACCESS) ] = -1,
 754                 [ C(RESULT_MISS)   ] = -1,
 755         },
 756         [ C(OP_PREFETCH) ] = {
 757                 [ C(RESULT_ACCESS) ] = -1,
 758                 [ C(RESULT_MISS)   ] = -1,
 759         },
 760  },
 761  [ C(BPU ) ] = {
 762         [ C(OP_READ) ] = {
 763                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
 764                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
 765         },
 766         [ C(OP_WRITE) ] = {
 767                 [ C(RESULT_ACCESS) ] = -1,
 768                 [ C(RESULT_MISS)   ] = -1,
 769         },
 770         [ C(OP_PREFETCH) ] = {
 771                 [ C(RESULT_ACCESS) ] = -1,
 772                 [ C(RESULT_MISS)   ] = -1,
 773         },
 774  },
 775 };
 776
 777 static __initconst const u64 atom_hw_cache_event_ids
 778                                 [PERF_COUNT_HW_CACHE_MAX]
 779                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 780                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 781 {
 782  [ C(L1D) ] = {
 783         [ C(OP_READ) ] = {
 784                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD               */
 785                 [ C(RESULT_MISS)   ] = 0,
 786         },
 787         [ C(OP_WRITE) ] = {
 788                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST               */
 789                 [ C(RESULT_MISS)   ] = 0,
 790         },
 791         [ C(OP_PREFETCH) ] = {
 792                 [ C(RESULT_ACCESS) ] = 0x0,
 793                 [ C(RESULT_MISS)   ] = 0,
 794         },
 795  },
 796  [ C(L1I ) ] = {
 797         [ C(OP_READ) ] = {
 798                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                  */
 799                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                 */
 800         },
 801         [ C(OP_WRITE) ] = {
 802                 [ C(RESULT_ACCESS) ] = -1,
 803                 [ C(RESULT_MISS)   ] = -1,
 804         },
 805         [ C(OP_PREFETCH) ] = {
 806                 [ C(RESULT_ACCESS) ] = 0,
 807                 [ C(RESULT_MISS)   ] = 0,
 808         },
 809  },
 810  [ C(LL  ) ] = {
 811         [ C(OP_READ) ] = {
 812                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
 813                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
 814         },
 815         [ C(OP_WRITE) ] = {
 816                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
 817                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
 818         },
 819         [ C(OP_PREFETCH) ] = {
 820                 [ C(RESULT_ACCESS) ] = 0,
 821                 [ C(RESULT_MISS)   ] = 0,
 822         },
 823  },
 824  [ C(DTLB) ] = {
 825         [ C(OP_READ) ] = {
 826                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI  (alias) */
 827                 [ C(RESULT_MISS)   ] = 0x0508, /* DTLB_MISSES.MISS_LD        */
 828         },
 829         [ C(OP_WRITE) ] = {
 830                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI  (alias) */
 831                 [ C(RESULT_MISS)   ] = 0x0608, /* DTLB_MISSES.MISS_ST        */
 832         },
 833         [ C(OP_PREFETCH) ] = {
 834                 [ C(RESULT_ACCESS) ] = 0,
 835                 [ C(RESULT_MISS)   ] = 0,
 836         },
 837  },
 838  [ C(ITLB) ] = {
 839         [ C(OP_READ) ] = {
 840                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
 841                 [ C(RESULT_MISS)   ] = 0x0282, /* ITLB.MISSES                */
 842         },
 843         [ C(OP_WRITE) ] = {
 844                 [ C(RESULT_ACCESS) ] = -1,
 845                 [ C(RESULT_MISS)   ] = -1,
 846         },
 847         [ C(OP_PREFETCH) ] = {
 848                 [ C(RESULT_ACCESS) ] = -1,
 849                 [ C(RESULT_MISS)   ] = -1,
 850         },
 851  },
 852  [ C(BPU ) ] = {
 853         [ C(OP_READ) ] = {
 854                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
 855                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
 856         },
 857         [ C(OP_WRITE) ] = {
 858                 [ C(RESULT_ACCESS) ] = -1,
 859                 [ C(RESULT_MISS)   ] = -1,
 860         },
 861         [ C(OP_PREFETCH) ] = {
 862                 [ C(RESULT_ACCESS) ] = -1,
 863                 [ C(RESULT_MISS)   ] = -1,
 864         },
 865  },
 866 };
 867
 868 static inline bool intel_pmu_needs_lbr_smpl(struct perf_event *event)
 869 {
 870         /* user explicitly requested branch sampling */
 871         if (has_branch_stack(event))
 872                 return true;
 873
 874         /* implicit branch sampling to correct PEBS skid */
 875         if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1)
 876                 return true;
 877
 878         return false;
 879 }
 880
 881 static void intel_pmu_disable_all(void)
 882 {
 883         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 884
 885         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
 886
 887         if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
 888                 intel_pmu_disable_bts();
 889
 890         intel_pmu_pebs_disable_all();
 891         intel_pmu_lbr_disable_all();
 892 }
 893
 894 static void intel_pmu_enable_all(int added)
 895 {
 896         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 897
 898         intel_pmu_pebs_enable_all();
 899         intel_pmu_lbr_enable_all();
 900         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
 901                         x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
 902
 903         if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
 904                 struct perf_event *event =
 905                         cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
 906
 907                 if (WARN_ON_ONCE(!event))
 908                         return;
 909
 910                 intel_pmu_enable_bts(event->hw.config);
 911         }
 912 }
 913
 914 /*
 915  * Workaround for:
 916  *   Intel Errata AAK100 (model 26)
 917  *   Intel Errata AAP53  (model 30)
 918  *   Intel Errata BD53   (model 44)
 919  *
 920  * The official story:
 921  *   These chips need to be 'reset' when adding counters by programming the
 922  *   magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
 923  *   in sequence on the same PMC or on different PMCs.
 924  *
 925  * In practise it appears some of these events do in fact count, and
 926  * we need to programm all 4 events.
 927  */
 928 static void intel_pmu_nhm_workaround(void)
 929 {
 930         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 931         static const unsigned long nhm_magic[4] = {
 932                 0x4300B5,
 933                 0x4300D2,
 934                 0x4300B1,
 935                 0x4300B1
 936         };
 937         struct perf_event *event;
 938         int i;
 939
 940         /*
 941          * The Errata requires below steps:
 942          * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
 943          * 2) Configure 4 PERFEVTSELx with the magic events and clear
 944          *    the corresponding PMCx;
 945          * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
 946          * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
 947          * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
 948          */
 949
 950         /*
 951          * The real steps we choose are a little different from above.
 952          * A) To reduce MSR operations, we don't run step 1) as they
 953          *    are already cleared before this function is called;
 954          * B) Call x86_perf_event_update to save PMCx before configuring
 955          *    PERFEVTSELx with magic number;
 956          * C) With step 5), we do clear only when the PERFEVTSELx is
 957          *    not used currently.
 958          * D) Call x86_perf_event_set_period to restore PMCx;
 959          */
 960
 961         /* We always operate 4 pairs of PERF Counters */
 962         for (i = 0; i < 4; i++) {
 963                 event = cpuc->events[i];
 964                 if (event)
 965                         x86_perf_event_update(event);
 966         }
 967
 968         for (i = 0; i < 4; i++) {
 969                 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
 970                 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
 971         }
 972
 973         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
 974         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
 975
 976         for (i = 0; i < 4; i++) {
 977                 event = cpuc->events[i];
 978
 979                 if (event) {
 980                         x86_perf_event_set_period(event);
 981                         __x86_pmu_enable_event(&event->hw,
 982                                         ARCH_PERFMON_EVENTSEL_ENABLE);
 983                 } else
 984                         wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
 985         }
 986 }
 987
 988 static void intel_pmu_nhm_enable_all(int added)
 989 {
 990         if (added)
 991                 intel_pmu_nhm_workaround();
 992         intel_pmu_enable_all(added);
 993 }
 994
 995 static inline u64 intel_pmu_get_status(void)
 996 {
 997         u64 status;
 998
 999         rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1000
1001         return status;
1002 }
1003
1004 static inline void intel_pmu_ack_status(u64 ack)
1005 {
1006         wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1007 }
1008
1009 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
1010 {
1011         int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1012         u64 ctrl_val, mask;
1013
1014         mask = 0xfULL << (idx * 4);
1015
1016         rdmsrl(hwc->config_base, ctrl_val);
1017         ctrl_val &= ~mask;
1018         wrmsrl(hwc->config_base, ctrl_val);
1019 }
1020
1021 static void intel_pmu_disable_event(struct perf_event *event)
1022 {
1023         struct hw_perf_event *hwc = &event->hw;
1024         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1025
1026         if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
1027                 intel_pmu_disable_bts();
1028                 intel_pmu_drain_bts_buffer();
1029                 return;
1030         }
1031
1032         cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
1033         cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
1034
1035         /*
1036          * must disable before any actual event
1037          * because any event may be combined with LBR
1038          */
1039         if (intel_pmu_needs_lbr_smpl(event))
1040                 intel_pmu_lbr_disable(event);
1041
1042         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1043                 intel_pmu_disable_fixed(hwc);
1044                 return;
1045         }
1046
1047         x86_pmu_disable_event(event);
1048
1049         if (unlikely(event->attr.precise_ip))
1050                 intel_pmu_pebs_disable(event);
1051 }
1052
1053 static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
1054 {
1055         int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1056         u64 ctrl_val, bits, mask;
1057
1058         /*
1059          * Enable IRQ generation (0x8),
1060          * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1061          * if requested:
1062          */
1063         bits = 0x8ULL;
1064         if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1065                 bits |= 0x2;
1066         if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1067                 bits |= 0x1;
1068
1069         /*
1070          * ANY bit is supported in v3 and up
1071          */
1072         if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1073                 bits |= 0x4;
1074
1075         bits <<= (idx * 4);
1076         mask = 0xfULL << (idx * 4);
1077
1078         rdmsrl(hwc->config_base, ctrl_val);
1079         ctrl_val &= ~mask;
1080         ctrl_val |= bits;
1081         wrmsrl(hwc->config_base, ctrl_val);
1082 }
1083
1084 static void intel_pmu_enable_event(struct perf_event *event)
1085 {
1086         struct hw_perf_event *hwc = &event->hw;
1087         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1088
1089         if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
1090                 if (!__this_cpu_read(cpu_hw_events.enabled))
1091                         return;
1092
1093                 intel_pmu_enable_bts(hwc->config);
1094                 return;
1095         }
1096         /*
1097          * must enabled before any actual event
1098          * because any event may be combined with LBR
1099          */
1100         if (intel_pmu_needs_lbr_smpl(event))
1101                 intel_pmu_lbr_enable(event);
1102
1103         if (event->attr.exclude_host)
1104                 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1105         if (event->attr.exclude_guest)
1106                 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1107
1108         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1109                 intel_pmu_enable_fixed(hwc);
1110                 return;
1111         }
1112
1113         if (unlikely(event->attr.precise_ip))
1114                 intel_pmu_pebs_enable(event);
1115
1116         __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1117 }
1118
1119 /*
1120  * Save and restart an expired event. Called by NMI contexts,
1121  * so it has to be careful about preempting normal event ops:
1122  */
1123 int intel_pmu_save_and_restart(struct perf_event *event)
1124 {
1125         x86_perf_event_update(event);
1126         return x86_perf_event_set_period(event);
1127 }
1128
1129 static void intel_pmu_reset(void)
1130 {
1131         struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1132         unsigned long flags;
1133         int idx;
1134
1135         if (!x86_pmu.num_counters)
1136                 return;
1137
1138         local_irq_save(flags);
1139
1140         pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
1141
1142         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1143                 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
1144                 wrmsrl_safe(x86_pmu_event_addr(idx),  0ull);
1145         }
1146         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
1147                 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
1148
1149         if (ds)
1150                 ds->bts_index = ds->bts_buffer_base;
1151
1152         local_irq_restore(flags);
1153 }
1154
1155 /*
1156  * This handler is triggered by the local APIC, so the APIC IRQ handling
1157  * rules apply:
1158  */
1159 static int intel_pmu_handle_irq(struct pt_regs *regs)
1160 {
1161         struct perf_sample_data data;
1162         struct cpu_hw_events *cpuc;
1163         int bit, loops;
1164         u64 status;
1165         int handled;
1166
1167         cpuc = &__get_cpu_var(cpu_hw_events);
1168
1169         /*
1170          * Some chipsets need to unmask the LVTPC in a particular spot
1171          * inside the nmi handler.  As a result, the unmasking was pushed
1172          * into all the nmi handlers.
1173          *
1174          * This handler doesn't seem to have any issues with the unmasking
1175          * so it was left at the top.
1176          */
1177         apic_write(APIC_LVTPC, APIC_DM_NMI);
1178
1179         intel_pmu_disable_all();
1180         handled = intel_pmu_drain_bts_buffer();
1181         status = intel_pmu_get_status();
1182         if (!status) {
1183                 intel_pmu_enable_all(0);
1184                 return handled;
1185         }
1186
1187         loops = 0;
1188 again:
1189         intel_pmu_ack_status(status);
1190         if (++loops > 100) {
1191                 WARN_ONCE(1, "perfevents: irq loop stuck!\n");
1192                 perf_event_print_debug();
1193                 intel_pmu_reset();
1194                 goto done;
1195         }
1196
1197         inc_irq_stat(apic_perf_irqs);
1198
1199         intel_pmu_lbr_read();
1200
1201         /*
1202          * PEBS overflow sets bit 62 in the global status register
1203          */
1204         if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1205                 handled++;
1206                 x86_pmu.drain_pebs(regs);
1207         }
1208
1209         for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
1210                 struct perf_event *event = cpuc->events[bit];
1211
1212                 handled++;
1213
1214                 if (!test_bit(bit, cpuc->active_mask))
1215                         continue;
1216
1217                 if (!intel_pmu_save_and_restart(event))
1218                         continue;
1219
1220                 perf_sample_data_init(&data, 0, event->hw.last_period);
1221
1222                 if (has_branch_stack(event))
1223                         data.br_stack = &cpuc->lbr_stack;
1224
1225                 if (perf_event_overflow(event, &data, regs))
1226                         x86_pmu_stop(event, 0);
1227         }
1228
1229         /*
1230          * Repeat if there is more work to be done:
1231          */
1232         status = intel_pmu_get_status();
1233         if (status)
1234                 goto again;
1235
1236 done:
1237         intel_pmu_enable_all(0);
1238         return handled;
1239 }
1240
1241 static struct event_constraint *
1242 intel_bts_constraints(struct perf_event *event)
1243 {
1244         struct hw_perf_event *hwc = &event->hw;
1245         unsigned int hw_event, bts_event;
1246
1247         if (event->attr.freq)
1248                 return NULL;
1249
1250         hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1251         bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
1252
1253         if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
1254                 return &bts_constraint;
1255
1256         return NULL;
1257 }
1258
1259 static int intel_alt_er(int idx)
1260 {
1261         if (!(x86_pmu.er_flags & ERF_HAS_RSP_1))
1262                 return idx;
1263
1264         if (idx == EXTRA_REG_RSP_0)
1265                 return EXTRA_REG_RSP_1;
1266
1267         if (idx == EXTRA_REG_RSP_1)
1268                 return EXTRA_REG_RSP_0;
1269
1270         return idx;
1271 }
1272
1273 static void intel_fixup_er(struct perf_event *event, int idx)
1274 {
1275         event->hw.extra_reg.idx = idx;
1276
1277         if (idx == EXTRA_REG_RSP_0) {
1278                 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1279                 event->hw.config |= 0x01b7;
1280                 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
1281         } else if (idx == EXTRA_REG_RSP_1) {
1282                 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1283                 event->hw.config |= 0x01bb;
1284                 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
1285         }
1286 }
1287
1288 /*
1289  * manage allocation of shared extra msr for certain events
1290  *
1291  * sharing can be:
1292  * per-cpu: to be shared between the various events on a single PMU
1293  * per-core: per-cpu + shared by HT threads
1294  */
1295 static struct event_constraint *
1296 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
1297                                    struct perf_event *event,
1298                                    struct hw_perf_event_extra *reg)
1299 {
1300         struct event_constraint *c = &emptyconstraint;
1301         struct er_account *era;
1302         unsigned long flags;
1303         int idx = reg->idx;
1304
1305         /*
1306          * reg->alloc can be set due to existing state, so for fake cpuc we
1307          * need to ignore this, otherwise we might fail to allocate proper fake
1308          * state for this extra reg constraint. Also see the comment below.
1309          */
1310         if (reg->alloc && !cpuc->is_fake)
1311                 return NULL; /* call x86_get_event_constraint() */
1312
1313 again:
1314         era = &cpuc->shared_regs->regs[idx];
1315         /*
1316          * we use spin_lock_irqsave() to avoid lockdep issues when
1317          * passing a fake cpuc
1318          */
1319         raw_spin_lock_irqsave(&era->lock, flags);
1320
1321         if (!atomic_read(&era->ref) || era->config == reg->config) {
1322
1323                 /*
1324                  * If its a fake cpuc -- as per validate_{group,event}() we
1325                  * shouldn't touch event state and we can avoid doing so
1326                  * since both will only call get_event_constraints() once
1327                  * on each event, this avoids the need for reg->alloc.
1328                  *
1329                  * Not doing the ER fixup will only result in era->reg being
1330                  * wrong, but since we won't actually try and program hardware
1331                  * this isn't a problem either.
1332                  */
1333                 if (!cpuc->is_fake) {
1334                         if (idx != reg->idx)
1335                                 intel_fixup_er(event, idx);
1336
1337                         /*
1338                          * x86_schedule_events() can call get_event_constraints()
1339                          * multiple times on events in the case of incremental
1340                          * scheduling(). reg->alloc ensures we only do the ER
1341                          * allocation once.
1342                          */
1343                         reg->alloc = 1;
1344                 }
1345
1346                 /* lock in msr value */
1347                 era->config = reg->config;
1348                 era->reg = reg->reg;
1349
1350                 /* one more user */
1351                 atomic_inc(&era->ref);
1352
1353                 /*
1354                  * need to call x86_get_event_constraint()
1355                  * to check if associated event has constraints
1356                  */
1357                 c = NULL;
1358         } else {
1359                 idx = intel_alt_er(idx);
1360                 if (idx != reg->idx) {
1361                         raw_spin_unlock_irqrestore(&era->lock, flags);
1362                         goto again;
1363                 }
1364         }
1365         raw_spin_unlock_irqrestore(&era->lock, flags);
1366
1367         return c;
1368 }
1369
1370 static void
1371 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
1372                                    struct hw_perf_event_extra *reg)
1373 {
1374         struct er_account *era;
1375
1376         /*
1377          * Only put constraint if extra reg was actually allocated. Also takes
1378          * care of event which do not use an extra shared reg.
1379          *
1380          * Also, if this is a fake cpuc we shouldn't touch any event state
1381          * (reg->alloc) and we don't care about leaving inconsistent cpuc state
1382          * either since it'll be thrown out.
1383          */
1384         if (!reg->alloc || cpuc->is_fake)
1385                 return;
1386
1387         era = &cpuc->shared_regs->regs[reg->idx];
1388
1389         /* one fewer user */
1390         atomic_dec(&era->ref);
1391
1392         /* allocate again next time */
1393         reg->alloc = 0;
1394 }
1395
1396 static struct event_constraint *
1397 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
1398                               struct perf_event *event)
1399 {
1400         struct event_constraint *c = NULL, *d;
1401         struct hw_perf_event_extra *xreg, *breg;
1402
1403         xreg = &event->hw.extra_reg;
1404         if (xreg->idx != EXTRA_REG_NONE) {
1405                 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
1406                 if (c == &emptyconstraint)
1407                         return c;
1408         }
1409         breg = &event->hw.branch_reg;
1410         if (breg->idx != EXTRA_REG_NONE) {
1411                 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
1412                 if (d == &emptyconstraint) {
1413                         __intel_shared_reg_put_constraints(cpuc, xreg);
1414                         c = d;
1415                 }
1416         }
1417         return c;
1418 }
1419
1420 struct event_constraint *
1421 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1422 {
1423         struct event_constraint *c;
1424
1425         if (x86_pmu.event_constraints) {
1426                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1427                         if ((event->hw.config & c->cmask) == c->code) {
1428                                 /* hw.flags zeroed at initialization */
1429                                 event->hw.flags |= c->flags;
1430                                 return c;
1431                         }
1432                 }
1433         }
1434
1435         return &unconstrained;
1436 }
1437
1438 static struct event_constraint *
1439 intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1440 {
1441         struct event_constraint *c;
1442
1443         c = intel_bts_constraints(event);
1444         if (c)
1445                 return c;
1446
1447         c = intel_pebs_constraints(event);
1448         if (c)
1449                 return c;
1450
1451         c = intel_shared_regs_constraints(cpuc, event);
1452         if (c)
1453                 return c;
1454
1455         return x86_get_event_constraints(cpuc, event);
1456 }
1457
1458 static void
1459 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
1460                                         struct perf_event *event)
1461 {
1462         struct hw_perf_event_extra *reg;
1463
1464         reg = &event->hw.extra_reg;
1465         if (reg->idx != EXTRA_REG_NONE)
1466                 __intel_shared_reg_put_constraints(cpuc, reg);
1467
1468         reg = &event->hw.branch_reg;
1469         if (reg->idx != EXTRA_REG_NONE)
1470                 __intel_shared_reg_put_constraints(cpuc, reg);
1471 }
1472
1473 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
1474                                         struct perf_event *event)
1475 {
1476         event->hw.flags = 0;
1477         intel_put_shared_regs_event_constraints(cpuc, event);
1478 }
1479
1480 static void intel_pebs_aliases_core2(struct perf_event *event)
1481 {
1482         if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1483                 /*
1484                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1485                  * (0x003c) so that we can use it with PEBS.
1486                  *
1487                  * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1488                  * PEBS capable. However we can use INST_RETIRED.ANY_P
1489                  * (0x00c0), which is a PEBS capable event, to get the same
1490                  * count.
1491                  *
1492                  * INST_RETIRED.ANY_P counts the number of cycles that retires
1493                  * CNTMASK instructions. By setting CNTMASK to a value (16)
1494                  * larger than the maximum number of instructions that can be
1495                  * retired per cycle (4) and then inverting the condition, we
1496                  * count all cycles that retire 16 or less instructions, which
1497                  * is every cycle.
1498                  *
1499                  * Thereby we gain a PEBS capable cycle counter.
1500                  */
1501                 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
1502
1503                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1504                 event->hw.config = alt_config;
1505         }
1506 }
1507
1508 static void intel_pebs_aliases_snb(struct perf_event *event)
1509 {
1510         if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1511                 /*
1512                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1513                  * (0x003c) so that we can use it with PEBS.
1514                  *
1515                  * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1516                  * PEBS capable. However we can use UOPS_RETIRED.ALL
1517                  * (0x01c2), which is a PEBS capable event, to get the same
1518                  * count.
1519                  *
1520                  * UOPS_RETIRED.ALL counts the number of cycles that retires
1521                  * CNTMASK micro-ops. By setting CNTMASK to a value (16)
1522                  * larger than the maximum number of micro-ops that can be
1523                  * retired per cycle (4) and then inverting the condition, we
1524                  * count all cycles that retire 16 or less micro-ops, which
1525                  * is every cycle.
1526                  *
1527                  * Thereby we gain a PEBS capable cycle counter.
1528                  */
1529                 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
1530
1531                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1532                 event->hw.config = alt_config;
1533         }
1534 }
1535
1536 static int intel_pmu_hw_config(struct perf_event *event)
1537 {
1538         int ret = x86_pmu_hw_config(event);
1539
1540         if (ret)
1541                 return ret;
1542
1543         if (event->attr.precise_ip && x86_pmu.pebs_aliases)
1544                 x86_pmu.pebs_aliases(event);
1545
1546         if (intel_pmu_needs_lbr_smpl(event)) {
1547                 ret = intel_pmu_setup_lbr_filter(event);
1548                 if (ret)
1549                         return ret;
1550         }
1551
1552         if (event->attr.type != PERF_TYPE_RAW)
1553                 return 0;
1554
1555         if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
1556                 return 0;
1557
1558         if (x86_pmu.version < 3)
1559                 return -EINVAL;
1560
1561         if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
1562                 return -EACCES;
1563
1564         event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
1565
1566         return 0;
1567 }
1568
1569 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
1570 {
1571         if (x86_pmu.guest_get_msrs)
1572                 return x86_pmu.guest_get_msrs(nr);
1573         *nr = 0;
1574         return NULL;
1575 }
1576 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
1577
1578 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
1579 {
1580         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1581         struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1582
1583         arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
1584         arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
1585         arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
1586         /*
1587          * If PMU counter has PEBS enabled it is not enough to disable counter
1588          * on a guest entry since PEBS memory write can overshoot guest entry
1589          * and corrupt guest memory. Disabling PEBS solves the problem.
1590          */
1591         arr[1].msr = MSR_IA32_PEBS_ENABLE;
1592         arr[1].host = cpuc->pebs_enabled;
1593         arr[1].guest = 0;
1594
1595         *nr = 2;
1596         return arr;
1597 }
1598
1599 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
1600 {
1601         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1602         struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1603         int idx;
1604
1605         for (idx = 0; idx < x86_pmu.num_counters; idx++)  {
1606                 struct perf_event *event = cpuc->events[idx];
1607
1608                 arr[idx].msr = x86_pmu_config_addr(idx);
1609                 arr[idx].host = arr[idx].guest = 0;
1610
1611                 if (!test_bit(idx, cpuc->active_mask))
1612                         continue;
1613
1614                 arr[idx].host = arr[idx].guest =
1615                         event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
1616
1617                 if (event->attr.exclude_host)
1618                         arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1619                 else if (event->attr.exclude_guest)
1620                         arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1621         }
1622
1623         *nr = x86_pmu.num_counters;
1624         return arr;
1625 }
1626
1627 static void core_pmu_enable_event(struct perf_event *event)
1628 {
1629         if (!event->attr.exclude_host)
1630                 x86_pmu_enable_event(event);
1631 }
1632
1633 static void core_pmu_enable_all(int added)
1634 {
1635         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1636         int idx;
1637
1638         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1639                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
1640
1641                 if (!test_bit(idx, cpuc->active_mask) ||
1642                                 cpuc->events[idx]->attr.exclude_host)
1643                         continue;
1644
1645                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1646         }
1647 }
1648
1649 PMU_FORMAT_ATTR(event,  "config:0-7"    );
1650 PMU_FORMAT_ATTR(umask,  "config:8-15"   );
1651 PMU_FORMAT_ATTR(edge,   "config:18"     );
1652 PMU_FORMAT_ATTR(pc,     "config:19"     );
1653 PMU_FORMAT_ATTR(any,    "config:21"     ); /* v3 + */
1654 PMU_FORMAT_ATTR(inv,    "config:23"     );
1655 PMU_FORMAT_ATTR(cmask,  "config:24-31"  );
1656
1657 static struct attribute *intel_arch_formats_attr[] = {
1658         &format_attr_event.attr,
1659         &format_attr_umask.attr,
1660         &format_attr_edge.attr,
1661         &format_attr_pc.attr,
1662         &format_attr_inv.attr,
1663         &format_attr_cmask.attr,
1664         NULL,
1665 };
1666
1667 ssize_t intel_event_sysfs_show(char *page, u64 config)
1668 {
1669         u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
1670
1671         return x86_event_sysfs_show(page, config, event);
1672 }
1673
1674 static __initconst const struct x86_pmu core_pmu = {
1675         .name                   = "core",
1676         .handle_irq             = x86_pmu_handle_irq,
1677         .disable_all            = x86_pmu_disable_all,
1678         .enable_all             = core_pmu_enable_all,
1679         .enable                 = core_pmu_enable_event,
1680         .disable                = x86_pmu_disable_event,
1681         .hw_config              = x86_pmu_hw_config,
1682         .schedule_events        = x86_schedule_events,
1683         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
1684         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
1685         .event_map              = intel_pmu_event_map,
1686         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
1687         .apic                   = 1,
1688         /*
1689          * Intel PMCs cannot be accessed sanely above 32 bit width,
1690          * so we install an artificial 1<<31 period regardless of
1691          * the generic event period:
1692          */
1693         .max_period             = (1ULL << 31) - 1,
1694         .get_event_constraints  = intel_get_event_constraints,
1695         .put_event_constraints  = intel_put_event_constraints,
1696         .event_constraints      = intel_core_event_constraints,
1697         .guest_get_msrs         = core_guest_get_msrs,
1698         .format_attrs           = intel_arch_formats_attr,
1699         .events_sysfs_show      = intel_event_sysfs_show,
1700 };
1701
1702 struct intel_shared_regs *allocate_shared_regs(int cpu)
1703 {
1704         struct intel_shared_regs *regs;
1705         int i;
1706
1707         regs = kzalloc_node(sizeof(struct intel_shared_regs),
1708                             GFP_KERNEL, cpu_to_node(cpu));
1709         if (regs) {
1710                 /*
1711                  * initialize the locks to keep lockdep happy
1712                  */
1713                 for (i = 0; i < EXTRA_REG_MAX; i++)
1714                         raw_spin_lock_init(&regs->regs[i].lock);
1715
1716                 regs->core_id = -1;
1717         }
1718         return regs;
1719 }
1720
1721 static int intel_pmu_cpu_prepare(int cpu)
1722 {
1723         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1724
1725         if (!(x86_pmu.extra_regs || x86_pmu.lbr_sel_map))
1726                 return NOTIFY_OK;
1727
1728         cpuc->shared_regs = allocate_shared_regs(cpu);
1729         if (!cpuc->shared_regs)
1730                 return NOTIFY_BAD;
1731
1732         return NOTIFY_OK;
1733 }
1734
1735 static void intel_pmu_cpu_starting(int cpu)
1736 {
1737         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1738         int core_id = topology_core_id(cpu);
1739         int i;
1740
1741         init_debug_store_on_cpu(cpu);
1742         /*
1743          * Deal with CPUs that don't clear their LBRs on power-up.
1744          */
1745         intel_pmu_lbr_reset();
1746
1747         cpuc->lbr_sel = NULL;
1748
1749         if (!cpuc->shared_regs)
1750                 return;
1751
1752         if (!(x86_pmu.er_flags & ERF_NO_HT_SHARING)) {
1753                 for_each_cpu(i, topology_thread_cpumask(cpu)) {
1754                         struct intel_shared_regs *pc;
1755
1756                         pc = per_cpu(cpu_hw_events, i).shared_regs;
1757                         if (pc && pc->core_id == core_id) {
1758                                 cpuc->kfree_on_online = cpuc->shared_regs;
1759                                 cpuc->shared_regs = pc;
1760                                 break;
1761                         }
1762                 }
1763                 cpuc->shared_regs->core_id = core_id;
1764                 cpuc->shared_regs->refcnt++;
1765         }
1766
1767         if (x86_pmu.lbr_sel_map)
1768                 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
1769 }
1770
1771 static void intel_pmu_cpu_dying(int cpu)
1772 {
1773         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1774         struct intel_shared_regs *pc;
1775
1776         pc = cpuc->shared_regs;
1777         if (pc) {
1778                 if (pc->core_id == -1 || --pc->refcnt == 0)
1779                         kfree(pc);
1780                 cpuc->shared_regs = NULL;
1781         }
1782
1783         fini_debug_store_on_cpu(cpu);
1784 }
1785
1786 static void intel_pmu_flush_branch_stack(void)
1787 {
1788         /*
1789          * Intel LBR does not tag entries with the
1790          * PID of the current task, then we need to
1791          * flush it on ctxsw
1792          * For now, we simply reset it
1793          */
1794         if (x86_pmu.lbr_nr)
1795                 intel_pmu_lbr_reset();
1796 }
1797
1798 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
1799
1800 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
1801
1802 static struct attribute *intel_arch3_formats_attr[] = {
1803         &format_attr_event.attr,
1804         &format_attr_umask.attr,
1805         &format_attr_edge.attr,
1806         &format_attr_pc.attr,
1807         &format_attr_any.attr,
1808         &format_attr_inv.attr,
1809         &format_attr_cmask.attr,
1810
1811         &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
1812         &format_attr_ldlat.attr, /* PEBS load latency */
1813         NULL,
1814 };
1815
1816 static __initconst const struct x86_pmu intel_pmu = {
1817         .name                   = "Intel",
1818         .handle_irq             = intel_pmu_handle_irq,
1819         .disable_all            = intel_pmu_disable_all,
1820         .enable_all             = intel_pmu_enable_all,
1821         .enable                 = intel_pmu_enable_event,
1822         .disable                = intel_pmu_disable_event,
1823         .hw_config              = intel_pmu_hw_config,
1824         .schedule_events        = x86_schedule_events,
1825         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
1826         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
1827         .event_map              = intel_pmu_event_map,
1828         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
1829         .apic                   = 1,
1830         /*
1831          * Intel PMCs cannot be accessed sanely above 32 bit width,
1832          * so we install an artificial 1<<31 period regardless of
1833          * the generic event period:
1834          */
1835         .max_period             = (1ULL << 31) - 1,
1836         .get_event_constraints  = intel_get_event_constraints,
1837         .put_event_constraints  = intel_put_event_constraints,
1838         .pebs_aliases           = intel_pebs_aliases_core2,
1839
1840         .format_attrs           = intel_arch3_formats_attr,
1841         .events_sysfs_show      = intel_event_sysfs_show,
1842
1843         .cpu_prepare            = intel_pmu_cpu_prepare,
1844         .cpu_starting           = intel_pmu_cpu_starting,
1845         .cpu_dying              = intel_pmu_cpu_dying,
1846         .guest_get_msrs         = intel_guest_get_msrs,
1847         .flush_branch_stack     = intel_pmu_flush_branch_stack,
1848 };
1849
1850 static __init void intel_clovertown_quirk(void)
1851 {
1852         /*
1853          * PEBS is unreliable due to:
1854          *
1855          *   AJ67  - PEBS may experience CPL leaks
1856          *   AJ68  - PEBS PMI may be delayed by one event
1857          *   AJ69  - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
1858          *   AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
1859          *
1860          * AJ67 could be worked around by restricting the OS/USR flags.
1861          * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
1862          *
1863          * AJ106 could possibly be worked around by not allowing LBR
1864          *       usage from PEBS, including the fixup.
1865          * AJ68  could possibly be worked around by always programming
1866          *       a pebs_event_reset[0] value and coping with the lost events.
1867          *
1868          * But taken together it might just make sense to not enable PEBS on
1869          * these chips.
1870          */
1871         pr_warn("PEBS disabled due to CPU errata\n");
1872         x86_pmu.pebs = 0;
1873         x86_pmu.pebs_constraints = NULL;
1874 }
1875
1876 static int intel_snb_pebs_broken(int cpu)
1877 {
1878         u32 rev = UINT_MAX; /* default to broken for unknown models */
1879
1880         switch (cpu_data(cpu).x86_model) {
1881         case 42: /* SNB */
1882                 rev = 0x28;
1883                 break;
1884
1885         case 45: /* SNB-EP */
1886                 switch (cpu_data(cpu).x86_mask) {
1887                 case 6: rev = 0x618; break;
1888                 case 7: rev = 0x70c; break;
1889                 }
1890         }
1891
1892         return (cpu_data(cpu).microcode < rev);
1893 }
1894
1895 static void intel_snb_check_microcode(void)
1896 {
1897         int pebs_broken = 0;
1898         int cpu;
1899
1900         get_online_cpus();
1901         for_each_online_cpu(cpu) {
1902                 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
1903                         break;
1904         }
1905         put_online_cpus();
1906
1907         if (pebs_broken == x86_pmu.pebs_broken)
1908                 return;
1909
1910         /*
1911          * Serialized by the microcode lock..
1912          */
1913         if (x86_pmu.pebs_broken) {
1914                 pr_info("PEBS enabled due to microcode update\n");
1915                 x86_pmu.pebs_broken = 0;
1916         } else {
1917                 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
1918                 x86_pmu.pebs_broken = 1;
1919         }
1920 }
1921
1922 static __init void intel_sandybridge_quirk(void)
1923 {
1924         x86_pmu.check_microcode = intel_snb_check_microcode;
1925         intel_snb_check_microcode();
1926 }
1927
1928 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
1929         { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
1930         { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
1931         { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
1932         { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
1933         { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
1934         { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
1935         { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
1936 };
1937
1938 static __init void intel_arch_events_quirk(void)
1939 {
1940         int bit;
1941
1942         /* disable event that reported as not presend by cpuid */
1943         for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
1944                 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
1945                 pr_warn("CPUID marked event: \'%s\' unavailable\n",
1946                         intel_arch_events_map[bit].name);
1947         }
1948 }
1949
1950 static __init void intel_nehalem_quirk(void)
1951 {
1952         union cpuid10_ebx ebx;
1953
1954         ebx.full = x86_pmu.events_maskl;
1955         if (ebx.split.no_branch_misses_retired) {
1956                 /*
1957                  * Erratum AAJ80 detected, we work it around by using
1958                  * the BR_MISP_EXEC.ANY event. This will over-count
1959                  * branch-misses, but it's still much better than the
1960                  * architectural event which is often completely bogus:
1961                  */
1962                 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
1963                 ebx.split.no_branch_misses_retired = 0;
1964                 x86_pmu.events_maskl = ebx.full;
1965                 pr_info("CPU erratum AAJ80 worked around\n");
1966         }
1967 }
1968
1969 __init int intel_pmu_init(void)
1970 {
1971         union cpuid10_edx edx;
1972         union cpuid10_eax eax;
1973         union cpuid10_ebx ebx;
1974         struct event_constraint *c;
1975         unsigned int unused;
1976         int version;
1977
1978         if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
1979                 switch (boot_cpu_data.x86) {
1980                 case 0x6:
1981                         return p6_pmu_init();
1982                 case 0xb:
1983                         return knc_pmu_init();
1984                 case 0xf:
1985                         return p4_pmu_init();
1986                 }
1987                 return -ENODEV;
1988         }
1989
1990         /*
1991          * Check whether the Architectural PerfMon supports
1992          * Branch Misses Retired hw_event or not.
1993          */
1994         cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
1995         if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
1996                 return -ENODEV;
1997
1998         version = eax.split.version_id;
1999         if (version < 2)
2000                 x86_pmu = core_pmu;
2001         else
2002                 x86_pmu = intel_pmu;
2003
2004         x86_pmu.version                 = version;
2005         x86_pmu.num_counters            = eax.split.num_counters;
2006         x86_pmu.cntval_bits             = eax.split.bit_width;
2007         x86_pmu.cntval_mask             = (1ULL << eax.split.bit_width) - 1;
2008
2009         x86_pmu.events_maskl            = ebx.full;
2010         x86_pmu.events_mask_len         = eax.split.mask_length;
2011
2012         x86_pmu.max_pebs_events         = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
2013
2014         /*
2015          * Quirk: v2 perfmon does not report fixed-purpose events, so
2016          * assume at least 3 events:
2017          */
2018         if (version > 1)
2019                 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
2020
2021         /*
2022          * v2 and above have a perf capabilities MSR
2023          */
2024         if (version > 1) {
2025                 u64 capabilities;
2026
2027                 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
2028                 x86_pmu.intel_cap.capabilities = capabilities;
2029         }
2030
2031         intel_ds_init();
2032
2033         x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
2034
2035         /*
2036          * Install the hw-cache-events table:
2037          */
2038         switch (boot_cpu_data.x86_model) {
2039         case 14: /* 65 nm core solo/duo, "Yonah" */
2040                 pr_cont("Core events, ");
2041                 break;
2042
2043         case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
2044                 x86_add_quirk(intel_clovertown_quirk);
2045         case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
2046         case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
2047         case 29: /* six-core 45 nm xeon "Dunnington" */
2048                 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
2049                        sizeof(hw_cache_event_ids));
2050
2051                 intel_pmu_lbr_init_core();
2052
2053                 x86_pmu.event_constraints = intel_core2_event_constraints;
2054                 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
2055                 pr_cont("Core2 events, ");
2056                 break;
2057
2058         case 26: /* 45 nm nehalem, "Bloomfield" */
2059         case 30: /* 45 nm nehalem, "Lynnfield" */
2060         case 46: /* 45 nm nehalem-ex, "Beckton" */
2061                 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
2062                        sizeof(hw_cache_event_ids));
2063                 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2064                        sizeof(hw_cache_extra_regs));
2065
2066                 intel_pmu_lbr_init_nhm();
2067
2068                 x86_pmu.event_constraints = intel_nehalem_event_constraints;
2069                 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
2070                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
2071                 x86_pmu.extra_regs = intel_nehalem_extra_regs;
2072
2073                 x86_pmu.cpu_events = nhm_events_attrs;
2074
2075                 /* UOPS_ISSUED.STALLED_CYCLES */
2076                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2077                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2078                 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
2079                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2080                         X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
2081
2082                 x86_add_quirk(intel_nehalem_quirk);
2083
2084                 pr_cont("Nehalem events, ");
2085                 break;
2086
2087         case 28: /* Atom */
2088         case 38: /* Lincroft */
2089         case 39: /* Penwell */
2090         case 53: /* Cloverview */
2091         case 54: /* Cedarview */
2092                 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
2093                        sizeof(hw_cache_event_ids));
2094
2095                 intel_pmu_lbr_init_atom();
2096
2097                 x86_pmu.event_constraints = intel_gen_event_constraints;
2098                 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
2099                 pr_cont("Atom events, ");
2100                 break;
2101
2102         case 37: /* 32 nm nehalem, "Clarkdale" */
2103         case 44: /* 32 nm nehalem, "Gulftown" */
2104         case 47: /* 32 nm Xeon E7 */
2105                 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
2106                        sizeof(hw_cache_event_ids));
2107                 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2108                        sizeof(hw_cache_extra_regs));
2109
2110                 intel_pmu_lbr_init_nhm();
2111
2112                 x86_pmu.event_constraints = intel_westmere_event_constraints;
2113                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
2114                 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
2115                 x86_pmu.extra_regs = intel_westmere_extra_regs;
2116                 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2117
2118                 x86_pmu.cpu_events = nhm_events_attrs;
2119
2120                 /* UOPS_ISSUED.STALLED_CYCLES */
2121                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2122                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2123                 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
2124                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2125                         X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
2126
2127                 pr_cont("Westmere events, ");
2128                 break;
2129
2130         case 42: /* SandyBridge */
2131         case 45: /* SandyBridge, "Romely-EP" */
2132                 x86_add_quirk(intel_sandybridge_quirk);
2133                 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2134                        sizeof(hw_cache_event_ids));
2135                 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2136                        sizeof(hw_cache_extra_regs));
2137
2138                 intel_pmu_lbr_init_snb();
2139
2140                 x86_pmu.event_constraints = intel_snb_event_constraints;
2141                 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
2142                 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
2143                 if (boot_cpu_data.x86_model == 45)
2144                         x86_pmu.extra_regs = intel_snbep_extra_regs;
2145                 else
2146                         x86_pmu.extra_regs = intel_snb_extra_regs;
2147                 /* all extra regs are per-cpu when HT is on */
2148                 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2149                 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2150
2151                 x86_pmu.cpu_events = snb_events_attrs;
2152
2153                 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
2154                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2155                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2156                 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
2157                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2158                         X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
2159
2160                 pr_cont("SandyBridge events, ");
2161                 break;
2162         case 58: /* IvyBridge */
2163         case 62: /* IvyBridge EP */
2164                 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2165                        sizeof(hw_cache_event_ids));
2166                 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2167                        sizeof(hw_cache_extra_regs));
2168
2169                 intel_pmu_lbr_init_snb();
2170
2171                 x86_pmu.event_constraints = intel_ivb_event_constraints;
2172                 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
2173                 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
2174                 if (boot_cpu_data.x86_model == 62)
2175                         x86_pmu.extra_regs = intel_snbep_extra_regs;
2176                 else
2177                         x86_pmu.extra_regs = intel_snb_extra_regs;
2178                 /* all extra regs are per-cpu when HT is on */
2179                 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2180                 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2181
2182                 x86_pmu.cpu_events = snb_events_attrs;
2183
2184                 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
2185                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2186                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2187
2188                 pr_cont("IvyBridge events, ");
2189                 break;
2190
2191
2192         default:
2193                 switch (x86_pmu.version) {
2194                 case 1:
2195                         x86_pmu.event_constraints = intel_v1_event_constraints;
2196                         pr_cont("generic architected perfmon v1, ");
2197                         break;
2198                 default:
2199                         /*
2200                          * default constraints for v2 and up
2201                          */
2202                         x86_pmu.event_constraints = intel_gen_event_constraints;
2203                         pr_cont("generic architected perfmon, ");
2204                         break;
2205                 }
2206         }
2207
2208         if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
2209                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
2210                      x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
2211                 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
2212         }
2213         x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
2214
2215         if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
2216                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
2217                      x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
2218                 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
2219         }
2220
2221         x86_pmu.intel_ctrl |=
2222                 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
2223
2224         if (x86_pmu.event_constraints) {
2225                 /*
2226                  * event on fixed counter2 (REF_CYCLES) only works on this
2227                  * counter, so do not extend mask to generic counters
2228                  */
2229                 for_each_event_constraint(c, x86_pmu.event_constraints) {
2230                         if (c->cmask != X86_RAW_EVENT_MASK
2231                             || c->idxmsk64 == INTEL_PMC_MSK_FIXED_REF_CYCLES) {
2232                                 continue;
2233                         }
2234
2235                         c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
2236                         c->weight += x86_pmu.num_counters;
2237                 }
2238         }
2239
2240         return 0;
2241 }