arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/highmem.h>
  26 #include <linux/cpu.h>
  27 #include <linux/bitops.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/compat.h>
  33
  34 static u64 perf_event_mask __read_mostly;
  35
  36 /* The maximal number of PEBS events: */
  37 #define MAX_PEBS_EVENTS 4
  38
  39 /* The size of a BTS record in bytes: */
  40 #define BTS_RECORD_SIZE         24
  41
  42 /* The size of a per-cpu BTS buffer in bytes: */
  43 #define BTS_BUFFER_SIZE         (BTS_RECORD_SIZE * 2048)
  44
  45 /* The BTS overflow threshold in bytes from the end of the buffer: */
  46 #define BTS_OVFL_TH             (BTS_RECORD_SIZE * 128)
  47
  48
  49 /*
  50  * Bits in the debugctlmsr controlling branch tracing.
  51  */
  52 #define X86_DEBUGCTL_TR                 (1 << 6)
  53 #define X86_DEBUGCTL_BTS                (1 << 7)
  54 #define X86_DEBUGCTL_BTINT              (1 << 8)
  55 #define X86_DEBUGCTL_BTS_OFF_OS         (1 << 9)
  56 #define X86_DEBUGCTL_BTS_OFF_USR        (1 << 10)
  57
  58 /*
  59  * A debug store configuration.
  60  *
  61  * We only support architectures that use 64bit fields.
  62  */
  63 struct debug_store {
  64         u64     bts_buffer_base;
  65         u64     bts_index;
  66         u64     bts_absolute_maximum;
  67         u64     bts_interrupt_threshold;
  68         u64     pebs_buffer_base;
  69         u64     pebs_index;
  70         u64     pebs_absolute_maximum;
  71         u64     pebs_interrupt_threshold;
  72         u64     pebs_event_reset[MAX_PEBS_EVENTS];
  73 };
  74
  75 struct event_constraint {
  76         union {
  77                 unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  78                 u64             idxmsk64;
  79         };
  80         u64     code;
  81         u64     cmask;
  82         int     weight;
  83 };
  84
  85 struct amd_nb {
  86         int nb_id;  /* NorthBridge id */
  87         int refcnt; /* reference count */
  88         struct perf_event *owners[X86_PMC_IDX_MAX];
  89         struct event_constraint event_constraints[X86_PMC_IDX_MAX];
  90 };
  91
  92 struct cpu_hw_events {
  93         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
  94         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  95         unsigned long           interrupts;
  96         int                     enabled;
  97         struct debug_store      *ds;
  98
  99         int                     n_events;
 100         int                     n_added;
 101         int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
 102         u64                     tags[X86_PMC_IDX_MAX];
 103         struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
 104         struct amd_nb           *amd_nb;
 105 };
 106
 107 #define __EVENT_CONSTRAINT(c, n, m, w) {\
 108         { .idxmsk64 = (n) },            \
 109         .code = (c),                    \
 110         .cmask = (m),                   \
 111         .weight = (w),                  \
 112 }
 113
 114 #define EVENT_CONSTRAINT(c, n, m)       \
 115         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
 116
 117 #define INTEL_EVENT_CONSTRAINT(c, n)    \
 118         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVTSEL_MASK)
 119
 120 #define FIXED_EVENT_CONSTRAINT(c, n)    \
 121         EVENT_CONSTRAINT(c, (1ULL << (32+n)), INTEL_ARCH_FIXED_MASK)
 122
 123 #define EVENT_CONSTRAINT_END            \
 124         EVENT_CONSTRAINT(0, 0, 0)
 125
 126 #define for_each_event_constraint(e, c) \
 127         for ((e) = (c); (e)->cmask; (e)++)
 128
 129 /*
 130  * struct x86_pmu - generic x86 pmu
 131  */
 132 struct x86_pmu {
 133         const char      *name;
 134         int             version;
 135         int             (*handle_irq)(struct pt_regs *);
 136         void            (*disable_all)(void);
 137         void            (*enable_all)(void);
 138         void            (*enable)(struct perf_event *);
 139         void            (*disable)(struct perf_event *);
 140         unsigned        eventsel;
 141         unsigned        perfctr;
 142         u64             (*event_map)(int);
 143         u64             (*raw_event)(u64);
 144         int             max_events;
 145         int             num_events;
 146         int             num_events_fixed;
 147         int             event_bits;
 148         u64             event_mask;
 149         int             apic;
 150         u64             max_period;
 151         u64             intel_ctrl;
 152         void            (*enable_bts)(u64 config);
 153         void            (*disable_bts)(void);
 154
 155         struct event_constraint *
 156                         (*get_event_constraints)(struct cpu_hw_events *cpuc,
 157                                                  struct perf_event *event);
 158
 159         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
 160                                                  struct perf_event *event);
 161         struct event_constraint *event_constraints;
 162
 163         int             (*cpu_prepare)(int cpu);
 164         void            (*cpu_starting)(int cpu);
 165         void            (*cpu_dying)(int cpu);
 166         void            (*cpu_dead)(int cpu);
 167 };
 168
 169 static struct x86_pmu x86_pmu __read_mostly;
 170
 171 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
 172         .enabled = 1,
 173 };
 174
 175 static int x86_perf_event_set_period(struct perf_event *event);
 176
 177 /*
 178  * Generalized hw caching related hw_event table, filled
 179  * in on a per model basis. A value of 0 means
 180  * 'not supported', -1 means 'hw_event makes no sense on
 181  * this CPU', any other value means the raw hw_event
 182  * ID.
 183  */
 184
 185 #define C(x) PERF_COUNT_HW_CACHE_##x
 186
 187 static u64 __read_mostly hw_cache_event_ids
 188                                 [PERF_COUNT_HW_CACHE_MAX]
 189                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 190                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 191
 192 /*
 193  * Propagate event elapsed time into the generic event.
 194  * Can only be executed on the CPU where the event is active.
 195  * Returns the delta events processed.
 196  */
 197 static u64
 198 x86_perf_event_update(struct perf_event *event)
 199 {
 200         struct hw_perf_event *hwc = &event->hw;
 201         int shift = 64 - x86_pmu.event_bits;
 202         u64 prev_raw_count, new_raw_count;
 203         int idx = hwc->idx;
 204         s64 delta;
 205
 206         if (idx == X86_PMC_IDX_FIXED_BTS)
 207                 return 0;
 208
 209         /*
 210          * Careful: an NMI might modify the previous event value.
 211          *
 212          * Our tactic to handle this is to first atomically read and
 213          * exchange a new raw count - then add that new-prev delta
 214          * count to the generic event atomically:
 215          */
 216 again:
 217         prev_raw_count = atomic64_read(&hwc->prev_count);
 218         rdmsrl(hwc->event_base + idx, new_raw_count);
 219
 220         if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
 221                                         new_raw_count) != prev_raw_count)
 222                 goto again;
 223
 224         /*
 225          * Now we have the new raw value and have updated the prev
 226          * timestamp already. We can now calculate the elapsed delta
 227          * (event-)time and add that to the generic event.
 228          *
 229          * Careful, not all hw sign-extends above the physical width
 230          * of the count.
 231          */
 232         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 233         delta >>= shift;
 234
 235         atomic64_add(delta, &event->count);
 236         atomic64_sub(delta, &hwc->period_left);
 237
 238         return new_raw_count;
 239 }
 240
 241 static atomic_t active_events;
 242 static DEFINE_MUTEX(pmc_reserve_mutex);
 243
 244 static bool reserve_pmc_hardware(void)
 245 {
 246 #ifdef CONFIG_X86_LOCAL_APIC
 247         int i;
 248
 249         if (nmi_watchdog == NMI_LOCAL_APIC)
 250                 disable_lapic_nmi_watchdog();
 251
 252         for (i = 0; i < x86_pmu.num_events; i++) {
 253                 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
 254                         goto perfctr_fail;
 255         }
 256
 257         for (i = 0; i < x86_pmu.num_events; i++) {
 258                 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
 259                         goto eventsel_fail;
 260         }
 261 #endif
 262
 263         return true;
 264
 265 #ifdef CONFIG_X86_LOCAL_APIC
 266 eventsel_fail:
 267         for (i--; i >= 0; i--)
 268                 release_evntsel_nmi(x86_pmu.eventsel + i);
 269
 270         i = x86_pmu.num_events;
 271
 272 perfctr_fail:
 273         for (i--; i >= 0; i--)
 274                 release_perfctr_nmi(x86_pmu.perfctr + i);
 275
 276         if (nmi_watchdog == NMI_LOCAL_APIC)
 277                 enable_lapic_nmi_watchdog();
 278
 279         return false;
 280 #endif
 281 }
 282
 283 static void release_pmc_hardware(void)
 284 {
 285 #ifdef CONFIG_X86_LOCAL_APIC
 286         int i;
 287
 288         for (i = 0; i < x86_pmu.num_events; i++) {
 289                 release_perfctr_nmi(x86_pmu.perfctr + i);
 290                 release_evntsel_nmi(x86_pmu.eventsel + i);
 291         }
 292
 293         if (nmi_watchdog == NMI_LOCAL_APIC)
 294                 enable_lapic_nmi_watchdog();
 295 #endif
 296 }
 297
 298 static inline bool bts_available(void)
 299 {
 300         return x86_pmu.enable_bts != NULL;
 301 }
 302
 303 static void init_debug_store_on_cpu(int cpu)
 304 {
 305         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 306
 307         if (!ds)
 308                 return;
 309
 310         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
 311                      (u32)((u64)(unsigned long)ds),
 312                      (u32)((u64)(unsigned long)ds >> 32));
 313 }
 314
 315 static void fini_debug_store_on_cpu(int cpu)
 316 {
 317         if (!per_cpu(cpu_hw_events, cpu).ds)
 318                 return;
 319
 320         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
 321 }
 322
 323 static void release_bts_hardware(void)
 324 {
 325         int cpu;
 326
 327         if (!bts_available())
 328                 return;
 329
 330         get_online_cpus();
 331
 332         for_each_online_cpu(cpu)
 333                 fini_debug_store_on_cpu(cpu);
 334
 335         for_each_possible_cpu(cpu) {
 336                 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 337
 338                 if (!ds)
 339                         continue;
 340
 341                 per_cpu(cpu_hw_events, cpu).ds = NULL;
 342
 343                 kfree((void *)(unsigned long)ds->bts_buffer_base);
 344                 kfree(ds);
 345         }
 346
 347         put_online_cpus();
 348 }
 349
 350 static int reserve_bts_hardware(void)
 351 {
 352         int cpu, err = 0;
 353
 354         if (!bts_available())
 355                 return 0;
 356
 357         get_online_cpus();
 358
 359         for_each_possible_cpu(cpu) {
 360                 struct debug_store *ds;
 361                 void *buffer;
 362
 363                 err = -ENOMEM;
 364                 buffer = kzalloc(BTS_BUFFER_SIZE, GFP_KERNEL);
 365                 if (unlikely(!buffer))
 366                         break;
 367
 368                 ds = kzalloc(sizeof(*ds), GFP_KERNEL);
 369                 if (unlikely(!ds)) {
 370                         kfree(buffer);
 371                         break;
 372                 }
 373
 374                 ds->bts_buffer_base = (u64)(unsigned long)buffer;
 375                 ds->bts_index = ds->bts_buffer_base;
 376                 ds->bts_absolute_maximum =
 377                         ds->bts_buffer_base + BTS_BUFFER_SIZE;
 378                 ds->bts_interrupt_threshold =
 379                         ds->bts_absolute_maximum - BTS_OVFL_TH;
 380
 381                 per_cpu(cpu_hw_events, cpu).ds = ds;
 382                 err = 0;
 383         }
 384
 385         if (err)
 386                 release_bts_hardware();
 387         else {
 388                 for_each_online_cpu(cpu)
 389                         init_debug_store_on_cpu(cpu);
 390         }
 391
 392         put_online_cpus();
 393
 394         return err;
 395 }
 396
 397 static void hw_perf_event_destroy(struct perf_event *event)
 398 {
 399         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 400                 release_pmc_hardware();
 401                 release_bts_hardware();
 402                 mutex_unlock(&pmc_reserve_mutex);
 403         }
 404 }
 405
 406 static inline int x86_pmu_initialized(void)
 407 {
 408         return x86_pmu.handle_irq != NULL;
 409 }
 410
 411 static inline int
 412 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
 413 {
 414         unsigned int cache_type, cache_op, cache_result;
 415         u64 config, val;
 416
 417         config = attr->config;
 418
 419         cache_type = (config >>  0) & 0xff;
 420         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 421                 return -EINVAL;
 422
 423         cache_op = (config >>  8) & 0xff;
 424         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 425                 return -EINVAL;
 426
 427         cache_result = (config >> 16) & 0xff;
 428         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 429                 return -EINVAL;
 430
 431         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 432
 433         if (val == 0)
 434                 return -ENOENT;
 435
 436         if (val == -1)
 437                 return -EINVAL;
 438
 439         hwc->config |= val;
 440
 441         return 0;
 442 }
 443
 444 /*
 445  * Setup the hardware configuration for a given attr_type
 446  */
 447 static int __hw_perf_event_init(struct perf_event *event)
 448 {
 449         struct perf_event_attr *attr = &event->attr;
 450         struct hw_perf_event *hwc = &event->hw;
 451         u64 config;
 452         int err;
 453
 454         if (!x86_pmu_initialized())
 455                 return -ENODEV;
 456
 457         err = 0;
 458         if (!atomic_inc_not_zero(&active_events)) {
 459                 mutex_lock(&pmc_reserve_mutex);
 460                 if (atomic_read(&active_events) == 0) {
 461                         if (!reserve_pmc_hardware())
 462                                 err = -EBUSY;
 463                         else
 464                                 err = reserve_bts_hardware();
 465                 }
 466                 if (!err)
 467                         atomic_inc(&active_events);
 468                 mutex_unlock(&pmc_reserve_mutex);
 469         }
 470         if (err)
 471                 return err;
 472
 473         event->destroy = hw_perf_event_destroy;
 474
 475         /*
 476          * Generate PMC IRQs:
 477          * (keep 'enabled' bit clear for now)
 478          */
 479         hwc->config = ARCH_PERFMON_EVENTSEL_INT;
 480
 481         hwc->idx = -1;
 482         hwc->last_cpu = -1;
 483         hwc->last_tag = ~0ULL;
 484
 485         /*
 486          * Count user and OS events unless requested not to.
 487          */
 488         if (!attr->exclude_user)
 489                 hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
 490         if (!attr->exclude_kernel)
 491                 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
 492
 493         if (!hwc->sample_period) {
 494                 hwc->sample_period = x86_pmu.max_period;
 495                 hwc->last_period = hwc->sample_period;
 496                 atomic64_set(&hwc->period_left, hwc->sample_period);
 497         } else {
 498                 /*
 499                  * If we have a PMU initialized but no APIC
 500                  * interrupts, we cannot sample hardware
 501                  * events (user-space has to fall back and
 502                  * sample via a hrtimer based software event):
 503                  */
 504                 if (!x86_pmu.apic)
 505                         return -EOPNOTSUPP;
 506         }
 507
 508         /*
 509          * Raw hw_event type provide the config in the hw_event structure
 510          */
 511         if (attr->type == PERF_TYPE_RAW) {
 512                 hwc->config |= x86_pmu.raw_event(attr->config);
 513                 if ((hwc->config & ARCH_PERFMON_EVENTSEL_ANY) &&
 514                     perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
 515                         return -EACCES;
 516                 return 0;
 517         }
 518
 519         if (attr->type == PERF_TYPE_HW_CACHE)
 520                 return set_ext_hw_attr(hwc, attr);
 521
 522         if (attr->config >= x86_pmu.max_events)
 523                 return -EINVAL;
 524
 525         /*
 526          * The generic map:
 527          */
 528         config = x86_pmu.event_map(attr->config);
 529
 530         if (config == 0)
 531                 return -ENOENT;
 532
 533         if (config == -1LL)
 534                 return -EINVAL;
 535
 536         /*
 537          * Branch tracing:
 538          */
 539         if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
 540             (hwc->sample_period == 1)) {
 541                 /* BTS is not supported by this architecture. */
 542                 if (!bts_available())
 543                         return -EOPNOTSUPP;
 544
 545                 /* BTS is currently only allowed for user-mode. */
 546                 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
 547                         return -EOPNOTSUPP;
 548         }
 549
 550         hwc->config |= config;
 551
 552         return 0;
 553 }
 554
 555 static void x86_pmu_disable_all(void)
 556 {
 557         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 558         int idx;
 559
 560         for (idx = 0; idx < x86_pmu.num_events; idx++) {
 561                 u64 val;
 562
 563                 if (!test_bit(idx, cpuc->active_mask))
 564                         continue;
 565                 rdmsrl(x86_pmu.eventsel + idx, val);
 566                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 567                         continue;
 568                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 569                 wrmsrl(x86_pmu.eventsel + idx, val);
 570         }
 571 }
 572
 573 void hw_perf_disable(void)
 574 {
 575         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 576
 577         if (!x86_pmu_initialized())
 578                 return;
 579
 580         if (!cpuc->enabled)
 581                 return;
 582
 583         cpuc->n_added = 0;
 584         cpuc->enabled = 0;
 585         barrier();
 586
 587         x86_pmu.disable_all();
 588 }
 589
 590 static void x86_pmu_enable_all(void)
 591 {
 592         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 593         int idx;
 594
 595         for (idx = 0; idx < x86_pmu.num_events; idx++) {
 596                 struct perf_event *event = cpuc->events[idx];
 597                 u64 val;
 598
 599                 if (!test_bit(idx, cpuc->active_mask))
 600                         continue;
 601
 602                 val = event->hw.config;
 603                 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
 604                 wrmsrl(x86_pmu.eventsel + idx, val);
 605         }
 606 }
 607
 608 static const struct pmu pmu;
 609
 610 static inline int is_x86_event(struct perf_event *event)
 611 {
 612         return event->pmu == &pmu;
 613 }
 614
 615 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 616 {
 617         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
 618         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 619         int i, j, w, wmax, num = 0;
 620         struct hw_perf_event *hwc;
 621
 622         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 623
 624         for (i = 0; i < n; i++) {
 625                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 626                 constraints[i] = c;
 627         }
 628
 629         /*
 630          * fastpath, try to reuse previous register
 631          */
 632         for (i = 0; i < n; i++) {
 633                 hwc = &cpuc->event_list[i]->hw;
 634                 c = constraints[i];
 635
 636                 /* never assigned */
 637                 if (hwc->idx == -1)
 638                         break;
 639
 640                 /* constraint still honored */
 641                 if (!test_bit(hwc->idx, c->idxmsk))
 642                         break;
 643
 644                 /* not already used */
 645                 if (test_bit(hwc->idx, used_mask))
 646                         break;
 647
 648                 __set_bit(hwc->idx, used_mask);
 649                 if (assign)
 650                         assign[i] = hwc->idx;
 651         }
 652         if (i == n)
 653                 goto done;
 654
 655         /*
 656          * begin slow path
 657          */
 658
 659         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 660
 661         /*
 662          * weight = number of possible counters
 663          *
 664          * 1    = most constrained, only works on one counter
 665          * wmax = least constrained, works on any counter
 666          *
 667          * assign events to counters starting with most
 668          * constrained events.
 669          */
 670         wmax = x86_pmu.num_events;
 671
 672         /*
 673          * when fixed event counters are present,
 674          * wmax is incremented by 1 to account
 675          * for one more choice
 676          */
 677         if (x86_pmu.num_events_fixed)
 678                 wmax++;
 679
 680         for (w = 1, num = n; num && w <= wmax; w++) {
 681                 /* for each event */
 682                 for (i = 0; num && i < n; i++) {
 683                         c = constraints[i];
 684                         hwc = &cpuc->event_list[i]->hw;
 685
 686                         if (c->weight != w)
 687                                 continue;
 688
 689                         for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
 690                                 if (!test_bit(j, used_mask))
 691                                         break;
 692                         }
 693
 694                         if (j == X86_PMC_IDX_MAX)
 695                                 break;
 696
 697                         __set_bit(j, used_mask);
 698
 699                         if (assign)
 700                                 assign[i] = j;
 701                         num--;
 702                 }
 703         }
 704 done:
 705         /*
 706          * scheduling failed or is just a simulation,
 707          * free resources if necessary
 708          */
 709         if (!assign || num) {
 710                 for (i = 0; i < n; i++) {
 711                         if (x86_pmu.put_event_constraints)
 712                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
 713                 }
 714         }
 715         return num ? -ENOSPC : 0;
 716 }
 717
 718 /*
 719  * dogrp: true if must collect siblings events (group)
 720  * returns total number of events and error code
 721  */
 722 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 723 {
 724         struct perf_event *event;
 725         int n, max_count;
 726
 727         max_count = x86_pmu.num_events + x86_pmu.num_events_fixed;
 728
 729         /* current number of events already accepted */
 730         n = cpuc->n_events;
 731
 732         if (is_x86_event(leader)) {
 733                 if (n >= max_count)
 734                         return -ENOSPC;
 735                 cpuc->event_list[n] = leader;
 736                 n++;
 737         }
 738         if (!dogrp)
 739                 return n;
 740
 741         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 742                 if (!is_x86_event(event) ||
 743                     event->state <= PERF_EVENT_STATE_OFF)
 744                         continue;
 745
 746                 if (n >= max_count)
 747                         return -ENOSPC;
 748
 749                 cpuc->event_list[n] = event;
 750                 n++;
 751         }
 752         return n;
 753 }
 754
 755 static inline void x86_assign_hw_event(struct perf_event *event,
 756                                 struct cpu_hw_events *cpuc, int i)
 757 {
 758         struct hw_perf_event *hwc = &event->hw;
 759
 760         hwc->idx = cpuc->assign[i];
 761         hwc->last_cpu = smp_processor_id();
 762         hwc->last_tag = ++cpuc->tags[i];
 763
 764         if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
 765                 hwc->config_base = 0;
 766                 hwc->event_base = 0;
 767         } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
 768                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 769                 /*
 770                  * We set it so that event_base + idx in wrmsr/rdmsr maps to
 771                  * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
 772                  */
 773                 hwc->event_base =
 774                         MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
 775         } else {
 776                 hwc->config_base = x86_pmu.eventsel;
 777                 hwc->event_base  = x86_pmu.perfctr;
 778         }
 779 }
 780
 781 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 782                                         struct cpu_hw_events *cpuc,
 783                                         int i)
 784 {
 785         return hwc->idx == cpuc->assign[i] &&
 786                 hwc->last_cpu == smp_processor_id() &&
 787                 hwc->last_tag == cpuc->tags[i];
 788 }
 789
 790 static int x86_pmu_start(struct perf_event *event);
 791 static void x86_pmu_stop(struct perf_event *event);
 792
 793 void hw_perf_enable(void)
 794 {
 795         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 796         struct perf_event *event;
 797         struct hw_perf_event *hwc;
 798         int i;
 799
 800         if (!x86_pmu_initialized())
 801                 return;
 802
 803         if (cpuc->enabled)
 804                 return;
 805
 806         if (cpuc->n_added) {
 807                 int n_running = cpuc->n_events - cpuc->n_added;
 808                 /*
 809                  * apply assignment obtained either from
 810                  * hw_perf_group_sched_in() or x86_pmu_enable()
 811                  *
 812                  * step1: save events moving to new counters
 813                  * step2: reprogram moved events into new counters
 814                  */
 815                 for (i = 0; i < n_running; i++) {
 816                         event = cpuc->event_list[i];
 817                         hwc = &event->hw;
 818
 819                         /*
 820                          * we can avoid reprogramming counter if:
 821                          * - assigned same counter as last time
 822                          * - running on same CPU as last time
 823                          * - no other event has used the counter since
 824                          */
 825                         if (hwc->idx == -1 ||
 826                             match_prev_assignment(hwc, cpuc, i))
 827                                 continue;
 828
 829                         x86_pmu_stop(event);
 830                 }
 831
 832                 for (i = 0; i < cpuc->n_events; i++) {
 833                         event = cpuc->event_list[i];
 834                         hwc = &event->hw;
 835
 836                         if (!match_prev_assignment(hwc, cpuc, i))
 837                                 x86_assign_hw_event(event, cpuc, i);
 838                         else if (i < n_running)
 839                                 continue;
 840
 841                         x86_pmu_start(event);
 842                 }
 843                 cpuc->n_added = 0;
 844                 perf_events_lapic_init();
 845         }
 846
 847         cpuc->enabled = 1;
 848         barrier();
 849
 850         x86_pmu.enable_all();
 851 }
 852
 853 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc)
 854 {
 855         (void)checking_wrmsrl(hwc->config_base + hwc->idx,
 856                               hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE);
 857 }
 858
 859 static inline void x86_pmu_disable_event(struct perf_event *event)
 860 {
 861         struct hw_perf_event *hwc = &event->hw;
 862         (void)checking_wrmsrl(hwc->config_base + hwc->idx, hwc->config);
 863 }
 864
 865 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
 866
 867 /*
 868  * Set the next IRQ period, based on the hwc->period_left value.
 869  * To be called with the event disabled in hw:
 870  */
 871 static int
 872 x86_perf_event_set_period(struct perf_event *event)
 873 {
 874         struct hw_perf_event *hwc = &event->hw;
 875         s64 left = atomic64_read(&hwc->period_left);
 876         s64 period = hwc->sample_period;
 877         int err, ret = 0, idx = hwc->idx;
 878
 879         if (idx == X86_PMC_IDX_FIXED_BTS)
 880                 return 0;
 881
 882         /*
 883          * If we are way outside a reasonable range then just skip forward:
 884          */
 885         if (unlikely(left <= -period)) {
 886                 left = period;
 887                 atomic64_set(&hwc->period_left, left);
 888                 hwc->last_period = period;
 889                 ret = 1;
 890         }
 891
 892         if (unlikely(left <= 0)) {
 893                 left += period;
 894                 atomic64_set(&hwc->period_left, left);
 895                 hwc->last_period = period;
 896                 ret = 1;
 897         }
 898         /*
 899          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
 900          */
 901         if (unlikely(left < 2))
 902                 left = 2;
 903
 904         if (left > x86_pmu.max_period)
 905                 left = x86_pmu.max_period;
 906
 907         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
 908
 909         /*
 910          * The hw event starts counting from this event offset,
 911          * mark it to be able to extra future deltas:
 912          */
 913         atomic64_set(&hwc->prev_count, (u64)-left);
 914
 915         err = checking_wrmsrl(hwc->event_base + idx,
 916                              (u64)(-left) & x86_pmu.event_mask);
 917
 918         perf_event_update_userpage(event);
 919
 920         return ret;
 921 }
 922
 923 static void x86_pmu_enable_event(struct perf_event *event)
 924 {
 925         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 926         if (cpuc->enabled)
 927                 __x86_pmu_enable_event(&event->hw);
 928 }
 929
 930 /*
 931  * activate a single event
 932  *
 933  * The event is added to the group of enabled events
 934  * but only if it can be scehduled with existing events.
 935  *
 936  * Called with PMU disabled. If successful and return value 1,
 937  * then guaranteed to call perf_enable() and hw_perf_enable()
 938  */
 939 static int x86_pmu_enable(struct perf_event *event)
 940 {
 941         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 942         struct hw_perf_event *hwc;
 943         int assign[X86_PMC_IDX_MAX];
 944         int n, n0, ret;
 945
 946         hwc = &event->hw;
 947
 948         n0 = cpuc->n_events;
 949         n = collect_events(cpuc, event, false);
 950         if (n < 0)
 951                 return n;
 952
 953         ret = x86_schedule_events(cpuc, n, assign);
 954         if (ret)
 955                 return ret;
 956         /*
 957          * copy new assignment, now we know it is possible
 958          * will be used by hw_perf_enable()
 959          */
 960         memcpy(cpuc->assign, assign, n*sizeof(int));
 961
 962         cpuc->n_events = n;
 963         cpuc->n_added += n - n0;
 964
 965         return 0;
 966 }
 967
 968 static int x86_pmu_start(struct perf_event *event)
 969 {
 970         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 971         int idx = event->hw.idx;
 972
 973         if (idx == -1)
 974                 return -EAGAIN;
 975
 976         x86_perf_event_set_period(event);
 977         cpuc->events[idx] = event;
 978         __set_bit(idx, cpuc->active_mask);
 979         x86_pmu.enable(event);
 980         perf_event_update_userpage(event);
 981
 982         return 0;
 983 }
 984
 985 static void x86_pmu_unthrottle(struct perf_event *event)
 986 {
 987         int ret = x86_pmu_start(event);
 988         WARN_ON_ONCE(ret);
 989 }
 990
 991 void perf_event_print_debug(void)
 992 {
 993         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
 994         struct cpu_hw_events *cpuc;
 995         unsigned long flags;
 996         int cpu, idx;
 997
 998         if (!x86_pmu.num_events)
 999                 return;
1000
1001         local_irq_save(flags);
1002
1003         cpu = smp_processor_id();
1004         cpuc = &per_cpu(cpu_hw_events, cpu);
1005
1006         if (x86_pmu.version >= 2) {
1007                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1008                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1009                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1010                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1011
1012                 pr_info("\n");
1013                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1014                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1015                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1016                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1017         }
1018         pr_info("CPU#%d: active:       %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1019
1020         for (idx = 0; idx < x86_pmu.num_events; idx++) {
1021                 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1022                 rdmsrl(x86_pmu.perfctr  + idx, pmc_count);
1023
1024                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1025
1026                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1027                         cpu, idx, pmc_ctrl);
1028                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1029                         cpu, idx, pmc_count);
1030                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1031                         cpu, idx, prev_left);
1032         }
1033         for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
1034                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1035
1036                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1037                         cpu, idx, pmc_count);
1038         }
1039         local_irq_restore(flags);
1040 }
1041
1042 static void x86_pmu_stop(struct perf_event *event)
1043 {
1044         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1045         struct hw_perf_event *hwc = &event->hw;
1046         int idx = hwc->idx;
1047
1048         if (!__test_and_clear_bit(idx, cpuc->active_mask))
1049                 return;
1050
1051         x86_pmu.disable(event);
1052
1053         /*
1054          * Drain the remaining delta count out of a event
1055          * that we are disabling:
1056          */
1057         x86_perf_event_update(event);
1058
1059         cpuc->events[idx] = NULL;
1060 }
1061
1062 static void x86_pmu_disable(struct perf_event *event)
1063 {
1064         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1065         int i;
1066
1067         x86_pmu_stop(event);
1068
1069         for (i = 0; i < cpuc->n_events; i++) {
1070                 if (event == cpuc->event_list[i]) {
1071
1072                         if (x86_pmu.put_event_constraints)
1073                                 x86_pmu.put_event_constraints(cpuc, event);
1074
1075                         while (++i < cpuc->n_events)
1076                                 cpuc->event_list[i-1] = cpuc->event_list[i];
1077
1078                         --cpuc->n_events;
1079                         break;
1080                 }
1081         }
1082         perf_event_update_userpage(event);
1083 }
1084
1085 static int x86_pmu_handle_irq(struct pt_regs *regs)
1086 {
1087         struct perf_sample_data data;
1088         struct cpu_hw_events *cpuc;
1089         struct perf_event *event;
1090         struct hw_perf_event *hwc;
1091         int idx, handled = 0;
1092         u64 val;
1093
1094         perf_sample_data_init(&data, 0);
1095
1096         cpuc = &__get_cpu_var(cpu_hw_events);
1097
1098         for (idx = 0; idx < x86_pmu.num_events; idx++) {
1099                 if (!test_bit(idx, cpuc->active_mask))
1100                         continue;
1101
1102                 event = cpuc->events[idx];
1103                 hwc = &event->hw;
1104
1105                 val = x86_perf_event_update(event);
1106                 if (val & (1ULL << (x86_pmu.event_bits - 1)))
1107                         continue;
1108
1109                 /*
1110                  * event overflow
1111                  */
1112                 handled         = 1;
1113                 data.period     = event->hw.last_period;
1114
1115                 if (!x86_perf_event_set_period(event))
1116                         continue;
1117
1118                 if (perf_event_overflow(event, 1, &data, regs))
1119                         x86_pmu_stop(event);
1120         }
1121
1122         if (handled)
1123                 inc_irq_stat(apic_perf_irqs);
1124
1125         return handled;
1126 }
1127
1128 void smp_perf_pending_interrupt(struct pt_regs *regs)
1129 {
1130         irq_enter();
1131         ack_APIC_irq();
1132         inc_irq_stat(apic_pending_irqs);
1133         perf_event_do_pending();
1134         irq_exit();
1135 }
1136
1137 void set_perf_event_pending(void)
1138 {
1139 #ifdef CONFIG_X86_LOCAL_APIC
1140         if (!x86_pmu.apic || !x86_pmu_initialized())
1141                 return;
1142
1143         apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1144 #endif
1145 }
1146
1147 void perf_events_lapic_init(void)
1148 {
1149 #ifdef CONFIG_X86_LOCAL_APIC
1150         if (!x86_pmu.apic || !x86_pmu_initialized())
1151                 return;
1152
1153         /*
1154          * Always use NMI for PMU
1155          */
1156         apic_write(APIC_LVTPC, APIC_DM_NMI);
1157 #endif
1158 }
1159
1160 static int __kprobes
1161 perf_event_nmi_handler(struct notifier_block *self,
1162                          unsigned long cmd, void *__args)
1163 {
1164         struct die_args *args = __args;
1165         struct pt_regs *regs;
1166
1167         if (!atomic_read(&active_events))
1168                 return NOTIFY_DONE;
1169
1170         switch (cmd) {
1171         case DIE_NMI:
1172         case DIE_NMI_IPI:
1173                 break;
1174
1175         default:
1176                 return NOTIFY_DONE;
1177         }
1178
1179         regs = args->regs;
1180
1181 #ifdef CONFIG_X86_LOCAL_APIC
1182         apic_write(APIC_LVTPC, APIC_DM_NMI);
1183 #endif
1184         /*
1185          * Can't rely on the handled return value to say it was our NMI, two
1186          * events could trigger 'simultaneously' raising two back-to-back NMIs.
1187          *
1188          * If the first NMI handles both, the latter will be empty and daze
1189          * the CPU.
1190          */
1191         x86_pmu.handle_irq(regs);
1192
1193         return NOTIFY_STOP;
1194 }
1195
1196 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1197         .notifier_call          = perf_event_nmi_handler,
1198         .next                   = NULL,
1199         .priority               = 1
1200 };
1201
1202 static struct event_constraint unconstrained;
1203 static struct event_constraint emptyconstraint;
1204
1205 static struct event_constraint *
1206 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1207 {
1208         struct event_constraint *c;
1209
1210         if (x86_pmu.event_constraints) {
1211                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1212                         if ((event->hw.config & c->cmask) == c->code)
1213                                 return c;
1214                 }
1215         }
1216
1217         return &unconstrained;
1218 }
1219
1220 static int x86_event_sched_in(struct perf_event *event,
1221                           struct perf_cpu_context *cpuctx)
1222 {
1223         int ret = 0;
1224
1225         event->state = PERF_EVENT_STATE_ACTIVE;
1226         event->oncpu = smp_processor_id();
1227         event->tstamp_running += event->ctx->time - event->tstamp_stopped;
1228
1229         if (!is_x86_event(event))
1230                 ret = event->pmu->enable(event);
1231
1232         if (!ret && !is_software_event(event))
1233                 cpuctx->active_oncpu++;
1234
1235         if (!ret && event->attr.exclusive)
1236                 cpuctx->exclusive = 1;
1237
1238         return ret;
1239 }
1240
1241 static void x86_event_sched_out(struct perf_event *event,
1242                             struct perf_cpu_context *cpuctx)
1243 {
1244         event->state = PERF_EVENT_STATE_INACTIVE;
1245         event->oncpu = -1;
1246
1247         if (!is_x86_event(event))
1248                 event->pmu->disable(event);
1249
1250         event->tstamp_running -= event->ctx->time - event->tstamp_stopped;
1251
1252         if (!is_software_event(event))
1253                 cpuctx->active_oncpu--;
1254
1255         if (event->attr.exclusive || !cpuctx->active_oncpu)
1256                 cpuctx->exclusive = 0;
1257 }
1258
1259 /*
1260  * Called to enable a whole group of events.
1261  * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
1262  * Assumes the caller has disabled interrupts and has
1263  * frozen the PMU with hw_perf_save_disable.
1264  *
1265  * called with PMU disabled. If successful and return value 1,
1266  * then guaranteed to call perf_enable() and hw_perf_enable()
1267  */
1268 int hw_perf_group_sched_in(struct perf_event *leader,
1269                struct perf_cpu_context *cpuctx,
1270                struct perf_event_context *ctx)
1271 {
1272         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1273         struct perf_event *sub;
1274         int assign[X86_PMC_IDX_MAX];
1275         int n0, n1, ret;
1276
1277         /* n0 = total number of events */
1278         n0 = collect_events(cpuc, leader, true);
1279         if (n0 < 0)
1280                 return n0;
1281
1282         ret = x86_schedule_events(cpuc, n0, assign);
1283         if (ret)
1284                 return ret;
1285
1286         ret = x86_event_sched_in(leader, cpuctx);
1287         if (ret)
1288                 return ret;
1289
1290         n1 = 1;
1291         list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1292                 if (sub->state > PERF_EVENT_STATE_OFF) {
1293                         ret = x86_event_sched_in(sub, cpuctx);
1294                         if (ret)
1295                                 goto undo;
1296                         ++n1;
1297                 }
1298         }
1299         /*
1300          * copy new assignment, now we know it is possible
1301          * will be used by hw_perf_enable()
1302          */
1303         memcpy(cpuc->assign, assign, n0*sizeof(int));
1304
1305         cpuc->n_events  = n0;
1306         cpuc->n_added  += n1;
1307         ctx->nr_active += n1;
1308
1309         /*
1310          * 1 means successful and events are active
1311          * This is not quite true because we defer
1312          * actual activation until hw_perf_enable() but
1313          * this way we* ensure caller won't try to enable
1314          * individual events
1315          */
1316         return 1;
1317 undo:
1318         x86_event_sched_out(leader, cpuctx);
1319         n0  = 1;
1320         list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1321                 if (sub->state == PERF_EVENT_STATE_ACTIVE) {
1322                         x86_event_sched_out(sub, cpuctx);
1323                         if (++n0 == n1)
1324                                 break;
1325                 }
1326         }
1327         return ret;
1328 }
1329
1330 #include "perf_event_amd.c"
1331 #include "perf_event_p6.c"
1332 #include "perf_event_intel.c"
1333
1334 static int __cpuinit
1335 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1336 {
1337         unsigned int cpu = (long)hcpu;
1338         int ret = NOTIFY_OK;
1339
1340         switch (action & ~CPU_TASKS_FROZEN) {
1341         case CPU_UP_PREPARE:
1342                 if (x86_pmu.cpu_prepare)
1343                         ret = x86_pmu.cpu_prepare(cpu);
1344                 break;
1345
1346         case CPU_STARTING:
1347                 if (x86_pmu.cpu_starting)
1348                         x86_pmu.cpu_starting(cpu);
1349                 break;
1350
1351         case CPU_DYING:
1352                 if (x86_pmu.cpu_dying)
1353                         x86_pmu.cpu_dying(cpu);
1354                 break;
1355
1356         case CPU_UP_CANCELED:
1357         case CPU_DEAD:
1358                 if (x86_pmu.cpu_dead)
1359                         x86_pmu.cpu_dead(cpu);
1360                 break;
1361
1362         default:
1363                 break;
1364         }
1365
1366         return ret;
1367 }
1368
1369 static void __init pmu_check_apic(void)
1370 {
1371         if (cpu_has_apic)
1372                 return;
1373
1374         x86_pmu.apic = 0;
1375         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1376         pr_info("no hardware sampling interrupt available.\n");
1377 }
1378
1379 void __init init_hw_perf_events(void)
1380 {
1381         struct event_constraint *c;
1382         int err;
1383
1384         pr_info("Performance Events: ");
1385
1386         switch (boot_cpu_data.x86_vendor) {
1387         case X86_VENDOR_INTEL:
1388                 err = intel_pmu_init();
1389                 break;
1390         case X86_VENDOR_AMD:
1391                 err = amd_pmu_init();
1392                 break;
1393         default:
1394                 return;
1395         }
1396         if (err != 0) {
1397                 pr_cont("no PMU driver, software events only.\n");
1398                 return;
1399         }
1400
1401         pmu_check_apic();
1402
1403         pr_cont("%s PMU driver.\n", x86_pmu.name);
1404
1405         if (x86_pmu.num_events > X86_PMC_MAX_GENERIC) {
1406                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1407                      x86_pmu.num_events, X86_PMC_MAX_GENERIC);
1408                 x86_pmu.num_events = X86_PMC_MAX_GENERIC;
1409         }
1410         perf_event_mask = (1 << x86_pmu.num_events) - 1;
1411         perf_max_events = x86_pmu.num_events;
1412
1413         if (x86_pmu.num_events_fixed > X86_PMC_MAX_FIXED) {
1414                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1415                      x86_pmu.num_events_fixed, X86_PMC_MAX_FIXED);
1416                 x86_pmu.num_events_fixed = X86_PMC_MAX_FIXED;
1417         }
1418
1419         perf_event_mask |=
1420                 ((1LL << x86_pmu.num_events_fixed)-1) << X86_PMC_IDX_FIXED;
1421         x86_pmu.intel_ctrl = perf_event_mask;
1422
1423         perf_events_lapic_init();
1424         register_die_notifier(&perf_event_nmi_notifier);
1425
1426         unconstrained = (struct event_constraint)
1427                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_events) - 1,
1428                                    0, x86_pmu.num_events);
1429
1430         if (x86_pmu.event_constraints) {
1431                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1432                         if (c->cmask != INTEL_ARCH_FIXED_MASK)
1433                                 continue;
1434
1435                         c->idxmsk64 |= (1ULL << x86_pmu.num_events) - 1;
1436                         c->weight += x86_pmu.num_events;
1437                 }
1438         }
1439
1440         pr_info("... version:                %d\n",     x86_pmu.version);
1441         pr_info("... bit width:              %d\n",     x86_pmu.event_bits);
1442         pr_info("... generic registers:      %d\n",     x86_pmu.num_events);
1443         pr_info("... value mask:             %016Lx\n", x86_pmu.event_mask);
1444         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1445         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_events_fixed);
1446         pr_info("... event mask:             %016Lx\n", perf_event_mask);
1447
1448         perf_cpu_notifier(x86_pmu_notifier);
1449 }
1450
1451 static inline void x86_pmu_read(struct perf_event *event)
1452 {
1453         x86_perf_event_update(event);
1454 }
1455
1456 static const struct pmu pmu = {
1457         .enable         = x86_pmu_enable,
1458         .disable        = x86_pmu_disable,
1459         .start          = x86_pmu_start,
1460         .stop           = x86_pmu_stop,
1461         .read           = x86_pmu_read,
1462         .unthrottle     = x86_pmu_unthrottle,
1463 };
1464
1465 /*
1466  * validate a single event group
1467  *
1468  * validation include:
1469  *      - check events are compatible which each other
1470  *      - events do not compete for the same counter
1471  *      - number of events <= number of counters
1472  *
1473  * validation ensures the group can be loaded onto the
1474  * PMU if it was the only group available.
1475  */
1476 static int validate_group(struct perf_event *event)
1477 {
1478         struct perf_event *leader = event->group_leader;
1479         struct cpu_hw_events *fake_cpuc;
1480         int ret, n;
1481
1482         ret = -ENOMEM;
1483         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1484         if (!fake_cpuc)
1485                 goto out;
1486
1487         /*
1488          * the event is not yet connected with its
1489          * siblings therefore we must first collect
1490          * existing siblings, then add the new event
1491          * before we can simulate the scheduling
1492          */
1493         ret = -ENOSPC;
1494         n = collect_events(fake_cpuc, leader, true);
1495         if (n < 0)
1496                 goto out_free;
1497
1498         fake_cpuc->n_events = n;
1499         n = collect_events(fake_cpuc, event, false);
1500         if (n < 0)
1501                 goto out_free;
1502
1503         fake_cpuc->n_events = n;
1504
1505         ret = x86_schedule_events(fake_cpuc, n, NULL);
1506
1507 out_free:
1508         kfree(fake_cpuc);
1509 out:
1510         return ret;
1511 }
1512
1513 const struct pmu *hw_perf_event_init(struct perf_event *event)
1514 {
1515         const struct pmu *tmp;
1516         int err;
1517
1518         err = __hw_perf_event_init(event);
1519         if (!err) {
1520                 /*
1521                  * we temporarily connect event to its pmu
1522                  * such that validate_group() can classify
1523                  * it as an x86 event using is_x86_event()
1524                  */
1525                 tmp = event->pmu;
1526                 event->pmu = &pmu;
1527
1528                 if (event->group_leader != event)
1529                         err = validate_group(event);
1530
1531                 event->pmu = tmp;
1532         }
1533         if (err) {
1534                 if (event->destroy)
1535                         event->destroy(event);
1536                 return ERR_PTR(err);
1537         }
1538
1539         return &pmu;
1540 }
1541
1542 /*
1543  * callchain support
1544  */
1545
1546 static inline
1547 void callchain_store(struct perf_callchain_entry *entry, u64 ip)
1548 {
1549         if (entry->nr < PERF_MAX_STACK_DEPTH)
1550                 entry->ip[entry->nr++] = ip;
1551 }
1552
1553 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
1554 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry);
1555
1556
1557 static void
1558 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1559 {
1560         /* Ignore warnings */
1561 }
1562
1563 static void backtrace_warning(void *data, char *msg)
1564 {
1565         /* Ignore warnings */
1566 }
1567
1568 static int backtrace_stack(void *data, char *name)
1569 {
1570         return 0;
1571 }
1572
1573 static void backtrace_address(void *data, unsigned long addr, int reliable)
1574 {
1575         struct perf_callchain_entry *entry = data;
1576
1577         if (reliable)
1578                 callchain_store(entry, addr);
1579 }
1580
1581 static const struct stacktrace_ops backtrace_ops = {
1582         .warning                = backtrace_warning,
1583         .warning_symbol         = backtrace_warning_symbol,
1584         .stack                  = backtrace_stack,
1585         .address                = backtrace_address,
1586         .walk_stack             = print_context_stack_bp,
1587 };
1588
1589 #include "../dumpstack.h"
1590
1591 static void
1592 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1593 {
1594         callchain_store(entry, PERF_CONTEXT_KERNEL);
1595         callchain_store(entry, regs->ip);
1596
1597         dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
1598 }
1599
1600 /*
1601  * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
1602  */
1603 static unsigned long
1604 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
1605 {
1606         unsigned long offset, addr = (unsigned long)from;
1607         int type = in_nmi() ? KM_NMI : KM_IRQ0;
1608         unsigned long size, len = 0;
1609         struct page *page;
1610         void *map;
1611         int ret;
1612
1613         do {
1614                 ret = __get_user_pages_fast(addr, 1, 0, &page);
1615                 if (!ret)
1616                         break;
1617
1618                 offset = addr & (PAGE_SIZE - 1);
1619                 size = min(PAGE_SIZE - offset, n - len);
1620
1621                 map = kmap_atomic(page, type);
1622                 memcpy(to, map+offset, size);
1623                 kunmap_atomic(map, type);
1624                 put_page(page);
1625
1626                 len  += size;
1627                 to   += size;
1628                 addr += size;
1629
1630         } while (len < n);
1631
1632         return len;
1633 }
1634
1635 #ifdef CONFIG_COMPAT
1636 static inline int
1637 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1638 {
1639         /* 32-bit process in 64-bit kernel. */
1640         struct stack_frame_ia32 frame;
1641         const void __user *fp;
1642
1643         if (!test_thread_flag(TIF_IA32))
1644                 return 0;
1645
1646         fp = compat_ptr(regs->bp);
1647         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1648                 unsigned long bytes;
1649                 frame.next_frame     = 0;
1650                 frame.return_address = 0;
1651
1652                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1653                 if (bytes != sizeof(frame))
1654                         break;
1655
1656                 if (fp < compat_ptr(regs->sp))
1657                         break;
1658
1659                 callchain_store(entry, frame.return_address);
1660                 fp = compat_ptr(frame.next_frame);
1661         }
1662         return 1;
1663 }
1664 #else
1665 static inline int
1666 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1667 {
1668     return 0;
1669 }
1670 #endif
1671
1672 static void
1673 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1674 {
1675         struct stack_frame frame;
1676         const void __user *fp;
1677
1678         if (!user_mode(regs))
1679                 regs = task_pt_regs(current);
1680
1681         fp = (void __user *)regs->bp;
1682
1683         callchain_store(entry, PERF_CONTEXT_USER);
1684         callchain_store(entry, regs->ip);
1685
1686         if (perf_callchain_user32(regs, entry))
1687                 return;
1688
1689         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1690                 unsigned long bytes;
1691                 frame.next_frame             = NULL;
1692                 frame.return_address = 0;
1693
1694                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1695                 if (bytes != sizeof(frame))
1696                         break;
1697
1698                 if ((unsigned long)fp < regs->sp)
1699                         break;
1700
1701                 callchain_store(entry, frame.return_address);
1702                 fp = frame.next_frame;
1703         }
1704 }
1705
1706 static void
1707 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1708 {
1709         int is_user;
1710
1711         if (!regs)
1712                 return;
1713
1714         is_user = user_mode(regs);
1715
1716         if (is_user && current->state != TASK_RUNNING)
1717                 return;
1718
1719         if (!is_user)
1720                 perf_callchain_kernel(regs, entry);
1721
1722         if (current->mm)
1723                 perf_callchain_user(regs, entry);
1724 }
1725
1726 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1727 {
1728         struct perf_callchain_entry *entry;
1729
1730         if (in_nmi())
1731                 entry = &__get_cpu_var(pmc_nmi_entry);
1732         else
1733                 entry = &__get_cpu_var(pmc_irq_entry);
1734
1735         entry->nr = 0;
1736
1737         perf_do_callchain(regs, entry);
1738
1739         return entry;
1740 }
1741
1742 void perf_arch_fetch_caller_regs(struct pt_regs *regs, unsigned long ip, int skip)
1743 {
1744         regs->ip = ip;
1745         /*
1746          * perf_arch_fetch_caller_regs adds another call, we need to increment
1747          * the skip level
1748          */
1749         regs->bp = rewind_frame_pointer(skip + 1);
1750         regs->cs = __KERNEL_CS;
1751         local_save_flags(regs->flags);
1752 }