arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/highmem.h>
  26 #include <linux/cpu.h>
  27 #include <linux/bitops.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/compat.h>
  33
  34 #if 0
  35 #undef wrmsrl
  36 #define wrmsrl(msr, val)                                        \
  37 do {                                                            \
  38         trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
  39                         (unsigned long)(val));                  \
  40         native_write_msr((msr), (u32)((u64)(val)),              \
  41                         (u32)((u64)(val) >> 32));               \
  42 } while (0)
  43 #endif
  44
  45 /*
  46  * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
  47  */
  48 static unsigned long
  49 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
  50 {
  51         unsigned long offset, addr = (unsigned long)from;
  52         int type = in_nmi() ? KM_NMI : KM_IRQ0;
  53         unsigned long size, len = 0;
  54         struct page *page;
  55         void *map;
  56         int ret;
  57
  58         do {
  59                 ret = __get_user_pages_fast(addr, 1, 0, &page);
  60                 if (!ret)
  61                         break;
  62
  63                 offset = addr & (PAGE_SIZE - 1);
  64                 size = min(PAGE_SIZE - offset, n - len);
  65
  66                 map = kmap_atomic(page, type);
  67                 memcpy(to, map+offset, size);
  68                 kunmap_atomic(map, type);
  69                 put_page(page);
  70
  71                 len  += size;
  72                 to   += size;
  73                 addr += size;
  74
  75         } while (len < n);
  76
  77         return len;
  78 }
  79
  80 struct event_constraint {
  81         union {
  82                 unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  83                 u64             idxmsk64;
  84         };
  85         u64     code;
  86         u64     cmask;
  87         int     weight;
  88 };
  89
  90 struct amd_nb {
  91         int nb_id;  /* NorthBridge id */
  92         int refcnt; /* reference count */
  93         struct perf_event *owners[X86_PMC_IDX_MAX];
  94         struct event_constraint event_constraints[X86_PMC_IDX_MAX];
  95 };
  96
  97 #define MAX_LBR_ENTRIES         16
  98
  99 struct cpu_hw_events {
 100         /*
 101          * Generic x86 PMC bits
 102          */
 103         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
 104         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 105         int                     enabled;
 106
 107         int                     n_events;
 108         int                     n_added;
 109         int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
 110         u64                     tags[X86_PMC_IDX_MAX];
 111         struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
 112
 113         /*
 114          * Intel DebugStore bits
 115          */
 116         struct debug_store      *ds;
 117         u64                     pebs_enabled;
 118
 119         /*
 120          * Intel LBR bits
 121          */
 122         int                             lbr_users;
 123         void                            *lbr_context;
 124         struct perf_branch_stack        lbr_stack;
 125         struct perf_branch_entry        lbr_entries[MAX_LBR_ENTRIES];
 126
 127         /*
 128          * AMD specific bits
 129          */
 130         struct amd_nb           *amd_nb;
 131 };
 132
 133 #define __EVENT_CONSTRAINT(c, n, m, w) {\
 134         { .idxmsk64 = (n) },            \
 135         .code = (c),                    \
 136         .cmask = (m),                   \
 137         .weight = (w),                  \
 138 }
 139
 140 #define EVENT_CONSTRAINT(c, n, m)       \
 141         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
 142
 143 /*
 144  * Constraint on the Event code.
 145  */
 146 #define INTEL_EVENT_CONSTRAINT(c, n)    \
 147         EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
 148
 149 /*
 150  * Constraint on the Event code + UMask + fixed-mask
 151  *
 152  * filter mask to validate fixed counter events.
 153  * the following filters disqualify for fixed counters:
 154  *  - inv
 155  *  - edge
 156  *  - cnt-mask
 157  *  The other filters are supported by fixed counters.
 158  *  The any-thread option is supported starting with v3.
 159  */
 160 #define FIXED_EVENT_CONSTRAINT(c, n)    \
 161         EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
 162
 163 /*
 164  * Constraint on the Event code + UMask
 165  */
 166 #define PEBS_EVENT_CONSTRAINT(c, n)     \
 167         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
 168
 169 #define EVENT_CONSTRAINT_END            \
 170         EVENT_CONSTRAINT(0, 0, 0)
 171
 172 #define for_each_event_constraint(e, c) \
 173         for ((e) = (c); (e)->cmask; (e)++)
 174
 175 union perf_capabilities {
 176         struct {
 177                 u64     lbr_format    : 6;
 178                 u64     pebs_trap     : 1;
 179                 u64     pebs_arch_reg : 1;
 180                 u64     pebs_format   : 4;
 181                 u64     smm_freeze    : 1;
 182         };
 183         u64     capabilities;
 184 };
 185
 186 /*
 187  * struct x86_pmu - generic x86 pmu
 188  */
 189 struct x86_pmu {
 190         /*
 191          * Generic x86 PMC bits
 192          */
 193         const char      *name;
 194         int             version;
 195         int             (*handle_irq)(struct pt_regs *);
 196         void            (*disable_all)(void);
 197         void            (*enable_all)(int added);
 198         void            (*enable)(struct perf_event *);
 199         void            (*disable)(struct perf_event *);
 200         int             (*hw_config)(struct perf_event *event);
 201         int             (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
 202         unsigned        eventsel;
 203         unsigned        perfctr;
 204         u64             (*event_map)(int);
 205         int             max_events;
 206         int             num_counters;
 207         int             num_counters_fixed;
 208         int             cntval_bits;
 209         u64             cntval_mask;
 210         int             apic;
 211         u64             max_period;
 212         struct event_constraint *
 213                         (*get_event_constraints)(struct cpu_hw_events *cpuc,
 214                                                  struct perf_event *event);
 215
 216         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
 217                                                  struct perf_event *event);
 218         struct event_constraint *event_constraints;
 219         void            (*quirks)(void);
 220
 221         int             (*cpu_prepare)(int cpu);
 222         void            (*cpu_starting)(int cpu);
 223         void            (*cpu_dying)(int cpu);
 224         void            (*cpu_dead)(int cpu);
 225
 226         /*
 227          * Intel Arch Perfmon v2+
 228          */
 229         u64                     intel_ctrl;
 230         union perf_capabilities intel_cap;
 231
 232         /*
 233          * Intel DebugStore bits
 234          */
 235         int             bts, pebs;
 236         int             pebs_record_size;
 237         void            (*drain_pebs)(struct pt_regs *regs);
 238         struct event_constraint *pebs_constraints;
 239
 240         /*
 241          * Intel LBR
 242          */
 243         unsigned long   lbr_tos, lbr_from, lbr_to; /* MSR base regs       */
 244         int             lbr_nr;                    /* hardware stack size */
 245 };
 246
 247 static struct x86_pmu x86_pmu __read_mostly;
 248
 249 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
 250         .enabled = 1,
 251 };
 252
 253 static int x86_perf_event_set_period(struct perf_event *event);
 254
 255 /*
 256  * Generalized hw caching related hw_event table, filled
 257  * in on a per model basis. A value of 0 means
 258  * 'not supported', -1 means 'hw_event makes no sense on
 259  * this CPU', any other value means the raw hw_event
 260  * ID.
 261  */
 262
 263 #define C(x) PERF_COUNT_HW_CACHE_##x
 264
 265 static u64 __read_mostly hw_cache_event_ids
 266                                 [PERF_COUNT_HW_CACHE_MAX]
 267                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 268                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 269
 270 /*
 271  * Propagate event elapsed time into the generic event.
 272  * Can only be executed on the CPU where the event is active.
 273  * Returns the delta events processed.
 274  */
 275 static u64
 276 x86_perf_event_update(struct perf_event *event)
 277 {
 278         struct hw_perf_event *hwc = &event->hw;
 279         int shift = 64 - x86_pmu.cntval_bits;
 280         u64 prev_raw_count, new_raw_count;
 281         int idx = hwc->idx;
 282         s64 delta;
 283
 284         if (idx == X86_PMC_IDX_FIXED_BTS)
 285                 return 0;
 286
 287         /*
 288          * Careful: an NMI might modify the previous event value.
 289          *
 290          * Our tactic to handle this is to first atomically read and
 291          * exchange a new raw count - then add that new-prev delta
 292          * count to the generic event atomically:
 293          */
 294 again:
 295         prev_raw_count = atomic64_read(&hwc->prev_count);
 296         rdmsrl(hwc->event_base + idx, new_raw_count);
 297
 298         if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
 299                                         new_raw_count) != prev_raw_count)
 300                 goto again;
 301
 302         /*
 303          * Now we have the new raw value and have updated the prev
 304          * timestamp already. We can now calculate the elapsed delta
 305          * (event-)time and add that to the generic event.
 306          *
 307          * Careful, not all hw sign-extends above the physical width
 308          * of the count.
 309          */
 310         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 311         delta >>= shift;
 312
 313         atomic64_add(delta, &event->count);
 314         atomic64_sub(delta, &hwc->period_left);
 315
 316         return new_raw_count;
 317 }
 318
 319 static atomic_t active_events;
 320 static DEFINE_MUTEX(pmc_reserve_mutex);
 321
 322 #ifdef CONFIG_X86_LOCAL_APIC
 323
 324 static bool reserve_pmc_hardware(void)
 325 {
 326         int i;
 327
 328         if (nmi_watchdog == NMI_LOCAL_APIC)
 329                 disable_lapic_nmi_watchdog();
 330
 331         for (i = 0; i < x86_pmu.num_counters; i++) {
 332                 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
 333                         goto perfctr_fail;
 334         }
 335
 336         for (i = 0; i < x86_pmu.num_counters; i++) {
 337                 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
 338                         goto eventsel_fail;
 339         }
 340
 341         return true;
 342
 343 eventsel_fail:
 344         for (i--; i >= 0; i--)
 345                 release_evntsel_nmi(x86_pmu.eventsel + i);
 346
 347         i = x86_pmu.num_counters;
 348
 349 perfctr_fail:
 350         for (i--; i >= 0; i--)
 351                 release_perfctr_nmi(x86_pmu.perfctr + i);
 352
 353         if (nmi_watchdog == NMI_LOCAL_APIC)
 354                 enable_lapic_nmi_watchdog();
 355
 356         return false;
 357 }
 358
 359 static void release_pmc_hardware(void)
 360 {
 361         int i;
 362
 363         for (i = 0; i < x86_pmu.num_counters; i++) {
 364                 release_perfctr_nmi(x86_pmu.perfctr + i);
 365                 release_evntsel_nmi(x86_pmu.eventsel + i);
 366         }
 367
 368         if (nmi_watchdog == NMI_LOCAL_APIC)
 369                 enable_lapic_nmi_watchdog();
 370 }
 371
 372 #else
 373
 374 static bool reserve_pmc_hardware(void) { return true; }
 375 static void release_pmc_hardware(void) {}
 376
 377 #endif
 378
 379 static int reserve_ds_buffers(void);
 380 static void release_ds_buffers(void);
 381
 382 static void hw_perf_event_destroy(struct perf_event *event)
 383 {
 384         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 385                 release_pmc_hardware();
 386                 release_ds_buffers();
 387                 mutex_unlock(&pmc_reserve_mutex);
 388         }
 389 }
 390
 391 static inline int x86_pmu_initialized(void)
 392 {
 393         return x86_pmu.handle_irq != NULL;
 394 }
 395
 396 static inline int
 397 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
 398 {
 399         unsigned int cache_type, cache_op, cache_result;
 400         u64 config, val;
 401
 402         config = attr->config;
 403
 404         cache_type = (config >>  0) & 0xff;
 405         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 406                 return -EINVAL;
 407
 408         cache_op = (config >>  8) & 0xff;
 409         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 410                 return -EINVAL;
 411
 412         cache_result = (config >> 16) & 0xff;
 413         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 414                 return -EINVAL;
 415
 416         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 417
 418         if (val == 0)
 419                 return -ENOENT;
 420
 421         if (val == -1)
 422                 return -EINVAL;
 423
 424         hwc->config |= val;
 425
 426         return 0;
 427 }
 428
 429 static int x86_setup_perfctr(struct perf_event *event)
 430 {
 431         struct perf_event_attr *attr = &event->attr;
 432         struct hw_perf_event *hwc = &event->hw;
 433         u64 config;
 434
 435         if (!hwc->sample_period) {
 436                 hwc->sample_period = x86_pmu.max_period;
 437                 hwc->last_period = hwc->sample_period;
 438                 atomic64_set(&hwc->period_left, hwc->sample_period);
 439         } else {
 440                 /*
 441                  * If we have a PMU initialized but no APIC
 442                  * interrupts, we cannot sample hardware
 443                  * events (user-space has to fall back and
 444                  * sample via a hrtimer based software event):
 445                  */
 446                 if (!x86_pmu.apic)
 447                         return -EOPNOTSUPP;
 448         }
 449
 450         if (attr->type == PERF_TYPE_RAW)
 451                 return 0;
 452
 453         if (attr->type == PERF_TYPE_HW_CACHE)
 454                 return set_ext_hw_attr(hwc, attr);
 455
 456         if (attr->config >= x86_pmu.max_events)
 457                 return -EINVAL;
 458
 459         /*
 460          * The generic map:
 461          */
 462         config = x86_pmu.event_map(attr->config);
 463
 464         if (config == 0)
 465                 return -ENOENT;
 466
 467         if (config == -1LL)
 468                 return -EINVAL;
 469
 470         /*
 471          * Branch tracing:
 472          */
 473         if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
 474             (hwc->sample_period == 1)) {
 475                 /* BTS is not supported by this architecture. */
 476                 if (!x86_pmu.bts)
 477                         return -EOPNOTSUPP;
 478
 479                 /* BTS is currently only allowed for user-mode. */
 480                 if (!attr->exclude_kernel)
 481                         return -EOPNOTSUPP;
 482         }
 483
 484         hwc->config |= config;
 485
 486         return 0;
 487 }
 488
 489 static int x86_pmu_hw_config(struct perf_event *event)
 490 {
 491         /*
 492          * Generate PMC IRQs:
 493          * (keep 'enabled' bit clear for now)
 494          */
 495         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 496
 497         /*
 498          * Count user and OS events unless requested not to
 499          */
 500         if (!event->attr.exclude_user)
 501                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 502         if (!event->attr.exclude_kernel)
 503                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 504
 505         if (event->attr.type == PERF_TYPE_RAW)
 506                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 507
 508         return 0;
 509 }
 510
 511 /*
 512  * Setup the hardware configuration for a given attr_type
 513  */
 514 static int __hw_perf_event_init(struct perf_event *event)
 515 {
 516         int err;
 517
 518         if (!x86_pmu_initialized())
 519                 return -ENODEV;
 520
 521         err = 0;
 522         if (!atomic_inc_not_zero(&active_events)) {
 523                 mutex_lock(&pmc_reserve_mutex);
 524                 if (atomic_read(&active_events) == 0) {
 525                         if (!reserve_pmc_hardware())
 526                                 err = -EBUSY;
 527                         else {
 528                                 err = reserve_ds_buffers();
 529                                 if (err)
 530                                         release_pmc_hardware();
 531                         }
 532                 }
 533                 if (!err)
 534                         atomic_inc(&active_events);
 535                 mutex_unlock(&pmc_reserve_mutex);
 536         }
 537         if (err)
 538                 return err;
 539
 540         event->destroy = hw_perf_event_destroy;
 541
 542         event->hw.idx = -1;
 543         event->hw.last_cpu = -1;
 544         event->hw.last_tag = ~0ULL;
 545
 546         /* Processor specifics */
 547         err = x86_pmu.hw_config(event);
 548         if (err)
 549                 return err;
 550
 551         return x86_setup_perfctr(event);
 552 }
 553
 554 static void x86_pmu_disable_all(void)
 555 {
 556         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 557         int idx;
 558
 559         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 560                 u64 val;
 561
 562                 if (!test_bit(idx, cpuc->active_mask))
 563                         continue;
 564                 rdmsrl(x86_pmu.eventsel + idx, val);
 565                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 566                         continue;
 567                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 568                 wrmsrl(x86_pmu.eventsel + idx, val);
 569         }
 570 }
 571
 572 void hw_perf_disable(void)
 573 {
 574         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 575
 576         if (!x86_pmu_initialized())
 577                 return;
 578
 579         if (!cpuc->enabled)
 580                 return;
 581
 582         cpuc->n_added = 0;
 583         cpuc->enabled = 0;
 584         barrier();
 585
 586         x86_pmu.disable_all();
 587 }
 588
 589 static void x86_pmu_enable_all(int added)
 590 {
 591         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 592         int idx;
 593
 594         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 595                 struct perf_event *event = cpuc->events[idx];
 596                 u64 val;
 597
 598                 if (!test_bit(idx, cpuc->active_mask))
 599                         continue;
 600
 601                 val = event->hw.config;
 602                 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
 603                 wrmsrl(x86_pmu.eventsel + idx, val);
 604         }
 605 }
 606
 607 static const struct pmu pmu;
 608
 609 static inline int is_x86_event(struct perf_event *event)
 610 {
 611         return event->pmu == &pmu;
 612 }
 613
 614 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 615 {
 616         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
 617         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 618         int i, j, w, wmax, num = 0;
 619         struct hw_perf_event *hwc;
 620
 621         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 622
 623         for (i = 0; i < n; i++) {
 624                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 625                 constraints[i] = c;
 626         }
 627
 628         /*
 629          * fastpath, try to reuse previous register
 630          */
 631         for (i = 0; i < n; i++) {
 632                 hwc = &cpuc->event_list[i]->hw;
 633                 c = constraints[i];
 634
 635                 /* never assigned */
 636                 if (hwc->idx == -1)
 637                         break;
 638
 639                 /* constraint still honored */
 640                 if (!test_bit(hwc->idx, c->idxmsk))
 641                         break;
 642
 643                 /* not already used */
 644                 if (test_bit(hwc->idx, used_mask))
 645                         break;
 646
 647                 __set_bit(hwc->idx, used_mask);
 648                 if (assign)
 649                         assign[i] = hwc->idx;
 650         }
 651         if (i == n)
 652                 goto done;
 653
 654         /*
 655          * begin slow path
 656          */
 657
 658         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 659
 660         /*
 661          * weight = number of possible counters
 662          *
 663          * 1    = most constrained, only works on one counter
 664          * wmax = least constrained, works on any counter
 665          *
 666          * assign events to counters starting with most
 667          * constrained events.
 668          */
 669         wmax = x86_pmu.num_counters;
 670
 671         /*
 672          * when fixed event counters are present,
 673          * wmax is incremented by 1 to account
 674          * for one more choice
 675          */
 676         if (x86_pmu.num_counters_fixed)
 677                 wmax++;
 678
 679         for (w = 1, num = n; num && w <= wmax; w++) {
 680                 /* for each event */
 681                 for (i = 0; num && i < n; i++) {
 682                         c = constraints[i];
 683                         hwc = &cpuc->event_list[i]->hw;
 684
 685                         if (c->weight != w)
 686                                 continue;
 687
 688                         for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
 689                                 if (!test_bit(j, used_mask))
 690                                         break;
 691                         }
 692
 693                         if (j == X86_PMC_IDX_MAX)
 694                                 break;
 695
 696                         __set_bit(j, used_mask);
 697
 698                         if (assign)
 699                                 assign[i] = j;
 700                         num--;
 701                 }
 702         }
 703 done:
 704         /*
 705          * scheduling failed or is just a simulation,
 706          * free resources if necessary
 707          */
 708         if (!assign || num) {
 709                 for (i = 0; i < n; i++) {
 710                         if (x86_pmu.put_event_constraints)
 711                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
 712                 }
 713         }
 714         return num ? -ENOSPC : 0;
 715 }
 716
 717 /*
 718  * dogrp: true if must collect siblings events (group)
 719  * returns total number of events and error code
 720  */
 721 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 722 {
 723         struct perf_event *event;
 724         int n, max_count;
 725
 726         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 727
 728         /* current number of events already accepted */
 729         n = cpuc->n_events;
 730
 731         if (is_x86_event(leader)) {
 732                 if (n >= max_count)
 733                         return -ENOSPC;
 734                 cpuc->event_list[n] = leader;
 735                 n++;
 736         }
 737         if (!dogrp)
 738                 return n;
 739
 740         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 741                 if (!is_x86_event(event) ||
 742                     event->state <= PERF_EVENT_STATE_OFF)
 743                         continue;
 744
 745                 if (n >= max_count)
 746                         return -ENOSPC;
 747
 748                 cpuc->event_list[n] = event;
 749                 n++;
 750         }
 751         return n;
 752 }
 753
 754 static inline void x86_assign_hw_event(struct perf_event *event,
 755                                 struct cpu_hw_events *cpuc, int i)
 756 {
 757         struct hw_perf_event *hwc = &event->hw;
 758
 759         hwc->idx = cpuc->assign[i];
 760         hwc->last_cpu = smp_processor_id();
 761         hwc->last_tag = ++cpuc->tags[i];
 762
 763         if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
 764                 hwc->config_base = 0;
 765                 hwc->event_base = 0;
 766         } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
 767                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 768                 /*
 769                  * We set it so that event_base + idx in wrmsr/rdmsr maps to
 770                  * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
 771                  */
 772                 hwc->event_base =
 773                         MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
 774         } else {
 775                 hwc->config_base = x86_pmu.eventsel;
 776                 hwc->event_base  = x86_pmu.perfctr;
 777         }
 778 }
 779
 780 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 781                                         struct cpu_hw_events *cpuc,
 782                                         int i)
 783 {
 784         return hwc->idx == cpuc->assign[i] &&
 785                 hwc->last_cpu == smp_processor_id() &&
 786                 hwc->last_tag == cpuc->tags[i];
 787 }
 788
 789 static int x86_pmu_start(struct perf_event *event);
 790 static void x86_pmu_stop(struct perf_event *event);
 791
 792 void hw_perf_enable(void)
 793 {
 794         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 795         struct perf_event *event;
 796         struct hw_perf_event *hwc;
 797         int i, added = cpuc->n_added;
 798
 799         if (!x86_pmu_initialized())
 800                 return;
 801
 802         if (cpuc->enabled)
 803                 return;
 804
 805         if (cpuc->n_added) {
 806                 int n_running = cpuc->n_events - cpuc->n_added;
 807                 /*
 808                  * apply assignment obtained either from
 809                  * hw_perf_group_sched_in() or x86_pmu_enable()
 810                  *
 811                  * step1: save events moving to new counters
 812                  * step2: reprogram moved events into new counters
 813                  */
 814                 for (i = 0; i < n_running; i++) {
 815                         event = cpuc->event_list[i];
 816                         hwc = &event->hw;
 817
 818                         /*
 819                          * we can avoid reprogramming counter if:
 820                          * - assigned same counter as last time
 821                          * - running on same CPU as last time
 822                          * - no other event has used the counter since
 823                          */
 824                         if (hwc->idx == -1 ||
 825                             match_prev_assignment(hwc, cpuc, i))
 826                                 continue;
 827
 828                         x86_pmu_stop(event);
 829                 }
 830
 831                 for (i = 0; i < cpuc->n_events; i++) {
 832                         event = cpuc->event_list[i];
 833                         hwc = &event->hw;
 834
 835                         if (!match_prev_assignment(hwc, cpuc, i))
 836                                 x86_assign_hw_event(event, cpuc, i);
 837                         else if (i < n_running)
 838                                 continue;
 839
 840                         x86_pmu_start(event);
 841                 }
 842                 cpuc->n_added = 0;
 843                 perf_events_lapic_init();
 844         }
 845
 846         cpuc->enabled = 1;
 847         barrier();
 848
 849         x86_pmu.enable_all(added);
 850 }
 851
 852 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc)
 853 {
 854         wrmsrl(hwc->config_base + hwc->idx,
 855                               hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE);
 856 }
 857
 858 static inline void x86_pmu_disable_event(struct perf_event *event)
 859 {
 860         struct hw_perf_event *hwc = &event->hw;
 861
 862         wrmsrl(hwc->config_base + hwc->idx, hwc->config);
 863 }
 864
 865 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
 866
 867 /*
 868  * Set the next IRQ period, based on the hwc->period_left value.
 869  * To be called with the event disabled in hw:
 870  */
 871 static int
 872 x86_perf_event_set_period(struct perf_event *event)
 873 {
 874         struct hw_perf_event *hwc = &event->hw;
 875         s64 left = atomic64_read(&hwc->period_left);
 876         s64 period = hwc->sample_period;
 877         int ret = 0, idx = hwc->idx;
 878
 879         if (idx == X86_PMC_IDX_FIXED_BTS)
 880                 return 0;
 881
 882         /*
 883          * If we are way outside a reasonable range then just skip forward:
 884          */
 885         if (unlikely(left <= -period)) {
 886                 left = period;
 887                 atomic64_set(&hwc->period_left, left);
 888                 hwc->last_period = period;
 889                 ret = 1;
 890         }
 891
 892         if (unlikely(left <= 0)) {
 893                 left += period;
 894                 atomic64_set(&hwc->period_left, left);
 895                 hwc->last_period = period;
 896                 ret = 1;
 897         }
 898         /*
 899          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
 900          */
 901         if (unlikely(left < 2))
 902                 left = 2;
 903
 904         if (left > x86_pmu.max_period)
 905                 left = x86_pmu.max_period;
 906
 907         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
 908
 909         /*
 910          * The hw event starts counting from this event offset,
 911          * mark it to be able to extra future deltas:
 912          */
 913         atomic64_set(&hwc->prev_count, (u64)-left);
 914
 915         wrmsrl(hwc->event_base + idx,
 916                         (u64)(-left) & x86_pmu.cntval_mask);
 917
 918         perf_event_update_userpage(event);
 919
 920         return ret;
 921 }
 922
 923 static void x86_pmu_enable_event(struct perf_event *event)
 924 {
 925         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 926         if (cpuc->enabled)
 927                 __x86_pmu_enable_event(&event->hw);
 928 }
 929
 930 /*
 931  * activate a single event
 932  *
 933  * The event is added to the group of enabled events
 934  * but only if it can be scehduled with existing events.
 935  *
 936  * Called with PMU disabled. If successful and return value 1,
 937  * then guaranteed to call perf_enable() and hw_perf_enable()
 938  */
 939 static int x86_pmu_enable(struct perf_event *event)
 940 {
 941         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 942         struct hw_perf_event *hwc;
 943         int assign[X86_PMC_IDX_MAX];
 944         int n, n0, ret;
 945
 946         hwc = &event->hw;
 947
 948         n0 = cpuc->n_events;
 949         n = collect_events(cpuc, event, false);
 950         if (n < 0)
 951                 return n;
 952
 953         ret = x86_pmu.schedule_events(cpuc, n, assign);
 954         if (ret)
 955                 return ret;
 956         /*
 957          * copy new assignment, now we know it is possible
 958          * will be used by hw_perf_enable()
 959          */
 960         memcpy(cpuc->assign, assign, n*sizeof(int));
 961
 962         cpuc->n_events = n;
 963         cpuc->n_added += n - n0;
 964
 965         return 0;
 966 }
 967
 968 static int x86_pmu_start(struct perf_event *event)
 969 {
 970         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 971         int idx = event->hw.idx;
 972
 973         if (idx == -1)
 974                 return -EAGAIN;
 975
 976         x86_perf_event_set_period(event);
 977         cpuc->events[idx] = event;
 978         __set_bit(idx, cpuc->active_mask);
 979         x86_pmu.enable(event);
 980         perf_event_update_userpage(event);
 981
 982         return 0;
 983 }
 984
 985 static void x86_pmu_unthrottle(struct perf_event *event)
 986 {
 987         int ret = x86_pmu_start(event);
 988         WARN_ON_ONCE(ret);
 989 }
 990
 991 void perf_event_print_debug(void)
 992 {
 993         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
 994         u64 pebs;
 995         struct cpu_hw_events *cpuc;
 996         unsigned long flags;
 997         int cpu, idx;
 998
 999         if (!x86_pmu.num_counters)
1000                 return;
1001
1002         local_irq_save(flags);
1003
1004         cpu = smp_processor_id();
1005         cpuc = &per_cpu(cpu_hw_events, cpu);
1006
1007         if (x86_pmu.version >= 2) {
1008                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1009                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1010                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1011                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1012                 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1013
1014                 pr_info("\n");
1015                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1016                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1017                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1018                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1019                 pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1020         }
1021         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1022
1023         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1024                 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1025                 rdmsrl(x86_pmu.perfctr  + idx, pmc_count);
1026
1027                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1028
1029                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1030                         cpu, idx, pmc_ctrl);
1031                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1032                         cpu, idx, pmc_count);
1033                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1034                         cpu, idx, prev_left);
1035         }
1036         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1037                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1038
1039                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1040                         cpu, idx, pmc_count);
1041         }
1042         local_irq_restore(flags);
1043 }
1044
1045 static void x86_pmu_stop(struct perf_event *event)
1046 {
1047         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1048         struct hw_perf_event *hwc = &event->hw;
1049         int idx = hwc->idx;
1050
1051         if (!__test_and_clear_bit(idx, cpuc->active_mask))
1052                 return;
1053
1054         x86_pmu.disable(event);
1055
1056         /*
1057          * Drain the remaining delta count out of a event
1058          * that we are disabling:
1059          */
1060         x86_perf_event_update(event);
1061
1062         cpuc->events[idx] = NULL;
1063 }
1064
1065 static void x86_pmu_disable(struct perf_event *event)
1066 {
1067         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1068         int i;
1069
1070         x86_pmu_stop(event);
1071
1072         for (i = 0; i < cpuc->n_events; i++) {
1073                 if (event == cpuc->event_list[i]) {
1074
1075                         if (x86_pmu.put_event_constraints)
1076                                 x86_pmu.put_event_constraints(cpuc, event);
1077
1078                         while (++i < cpuc->n_events)
1079                                 cpuc->event_list[i-1] = cpuc->event_list[i];
1080
1081                         --cpuc->n_events;
1082                         break;
1083                 }
1084         }
1085         perf_event_update_userpage(event);
1086 }
1087
1088 static int x86_pmu_handle_irq(struct pt_regs *regs)
1089 {
1090         struct perf_sample_data data;
1091         struct cpu_hw_events *cpuc;
1092         struct perf_event *event;
1093         struct hw_perf_event *hwc;
1094         int idx, handled = 0;
1095         u64 val;
1096
1097         perf_sample_data_init(&data, 0);
1098
1099         cpuc = &__get_cpu_var(cpu_hw_events);
1100
1101         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1102                 if (!test_bit(idx, cpuc->active_mask))
1103                         continue;
1104
1105                 event = cpuc->events[idx];
1106                 hwc = &event->hw;
1107
1108                 val = x86_perf_event_update(event);
1109                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1110                         continue;
1111
1112                 /*
1113                  * event overflow
1114                  */
1115                 handled         = 1;
1116                 data.period     = event->hw.last_period;
1117
1118                 if (!x86_perf_event_set_period(event))
1119                         continue;
1120
1121                 if (perf_event_overflow(event, 1, &data, regs))
1122                         x86_pmu_stop(event);
1123         }
1124
1125         if (handled)
1126                 inc_irq_stat(apic_perf_irqs);
1127
1128         return handled;
1129 }
1130
1131 void smp_perf_pending_interrupt(struct pt_regs *regs)
1132 {
1133         irq_enter();
1134         ack_APIC_irq();
1135         inc_irq_stat(apic_pending_irqs);
1136         perf_event_do_pending();
1137         irq_exit();
1138 }
1139
1140 void set_perf_event_pending(void)
1141 {
1142 #ifdef CONFIG_X86_LOCAL_APIC
1143         if (!x86_pmu.apic || !x86_pmu_initialized())
1144                 return;
1145
1146         apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1147 #endif
1148 }
1149
1150 void perf_events_lapic_init(void)
1151 {
1152         if (!x86_pmu.apic || !x86_pmu_initialized())
1153                 return;
1154
1155         /*
1156          * Always use NMI for PMU
1157          */
1158         apic_write(APIC_LVTPC, APIC_DM_NMI);
1159 }
1160
1161 static int __kprobes
1162 perf_event_nmi_handler(struct notifier_block *self,
1163                          unsigned long cmd, void *__args)
1164 {
1165         struct die_args *args = __args;
1166         struct pt_regs *regs;
1167
1168         if (!atomic_read(&active_events))
1169                 return NOTIFY_DONE;
1170
1171         switch (cmd) {
1172         case DIE_NMI:
1173         case DIE_NMI_IPI:
1174                 break;
1175
1176         default:
1177                 return NOTIFY_DONE;
1178         }
1179
1180         regs = args->regs;
1181
1182         apic_write(APIC_LVTPC, APIC_DM_NMI);
1183         /*
1184          * Can't rely on the handled return value to say it was our NMI, two
1185          * events could trigger 'simultaneously' raising two back-to-back NMIs.
1186          *
1187          * If the first NMI handles both, the latter will be empty and daze
1188          * the CPU.
1189          */
1190         x86_pmu.handle_irq(regs);
1191
1192         return NOTIFY_STOP;
1193 }
1194
1195 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1196         .notifier_call          = perf_event_nmi_handler,
1197         .next                   = NULL,
1198         .priority               = 1
1199 };
1200
1201 static struct event_constraint unconstrained;
1202 static struct event_constraint emptyconstraint;
1203
1204 static struct event_constraint *
1205 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1206 {
1207         struct event_constraint *c;
1208
1209         if (x86_pmu.event_constraints) {
1210                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1211                         if ((event->hw.config & c->cmask) == c->code)
1212                                 return c;
1213                 }
1214         }
1215
1216         return &unconstrained;
1217 }
1218
1219 static int x86_event_sched_in(struct perf_event *event,
1220                           struct perf_cpu_context *cpuctx)
1221 {
1222         int ret = 0;
1223
1224         event->state = PERF_EVENT_STATE_ACTIVE;
1225         event->oncpu = smp_processor_id();
1226         event->tstamp_running += event->ctx->time - event->tstamp_stopped;
1227
1228         if (!is_x86_event(event))
1229                 ret = event->pmu->enable(event);
1230
1231         if (!ret && !is_software_event(event))
1232                 cpuctx->active_oncpu++;
1233
1234         if (!ret && event->attr.exclusive)
1235                 cpuctx->exclusive = 1;
1236
1237         return ret;
1238 }
1239
1240 static void x86_event_sched_out(struct perf_event *event,
1241                             struct perf_cpu_context *cpuctx)
1242 {
1243         event->state = PERF_EVENT_STATE_INACTIVE;
1244         event->oncpu = -1;
1245
1246         if (!is_x86_event(event))
1247                 event->pmu->disable(event);
1248
1249         event->tstamp_running -= event->ctx->time - event->tstamp_stopped;
1250
1251         if (!is_software_event(event))
1252                 cpuctx->active_oncpu--;
1253
1254         if (event->attr.exclusive || !cpuctx->active_oncpu)
1255                 cpuctx->exclusive = 0;
1256 }
1257
1258 /*
1259  * Called to enable a whole group of events.
1260  * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
1261  * Assumes the caller has disabled interrupts and has
1262  * frozen the PMU with hw_perf_save_disable.
1263  *
1264  * called with PMU disabled. If successful and return value 1,
1265  * then guaranteed to call perf_enable() and hw_perf_enable()
1266  */
1267 int hw_perf_group_sched_in(struct perf_event *leader,
1268                struct perf_cpu_context *cpuctx,
1269                struct perf_event_context *ctx)
1270 {
1271         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1272         struct perf_event *sub;
1273         int assign[X86_PMC_IDX_MAX];
1274         int n0, n1, ret;
1275
1276         if (!x86_pmu_initialized())
1277                 return 0;
1278
1279         /* n0 = total number of events */
1280         n0 = collect_events(cpuc, leader, true);
1281         if (n0 < 0)
1282                 return n0;
1283
1284         ret = x86_pmu.schedule_events(cpuc, n0, assign);
1285         if (ret)
1286                 return ret;
1287
1288         ret = x86_event_sched_in(leader, cpuctx);
1289         if (ret)
1290                 return ret;
1291
1292         n1 = 1;
1293         list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1294                 if (sub->state > PERF_EVENT_STATE_OFF) {
1295                         ret = x86_event_sched_in(sub, cpuctx);
1296                         if (ret)
1297                                 goto undo;
1298                         ++n1;
1299                 }
1300         }
1301         /*
1302          * copy new assignment, now we know it is possible
1303          * will be used by hw_perf_enable()
1304          */
1305         memcpy(cpuc->assign, assign, n0*sizeof(int));
1306
1307         cpuc->n_events  = n0;
1308         cpuc->n_added  += n1;
1309         ctx->nr_active += n1;
1310
1311         /*
1312          * 1 means successful and events are active
1313          * This is not quite true because we defer
1314          * actual activation until hw_perf_enable() but
1315          * this way we* ensure caller won't try to enable
1316          * individual events
1317          */
1318         return 1;
1319 undo:
1320         x86_event_sched_out(leader, cpuctx);
1321         n0  = 1;
1322         list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1323                 if (sub->state == PERF_EVENT_STATE_ACTIVE) {
1324                         x86_event_sched_out(sub, cpuctx);
1325                         if (++n0 == n1)
1326                                 break;
1327                 }
1328         }
1329         return ret;
1330 }
1331
1332 #include "perf_event_amd.c"
1333 #include "perf_event_p6.c"
1334 #include "perf_event_p4.c"
1335 #include "perf_event_intel_lbr.c"
1336 #include "perf_event_intel_ds.c"
1337 #include "perf_event_intel.c"
1338
1339 static int __cpuinit
1340 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1341 {
1342         unsigned int cpu = (long)hcpu;
1343         int ret = NOTIFY_OK;
1344
1345         switch (action & ~CPU_TASKS_FROZEN) {
1346         case CPU_UP_PREPARE:
1347                 if (x86_pmu.cpu_prepare)
1348                         ret = x86_pmu.cpu_prepare(cpu);
1349                 break;
1350
1351         case CPU_STARTING:
1352                 if (x86_pmu.cpu_starting)
1353                         x86_pmu.cpu_starting(cpu);
1354                 break;
1355
1356         case CPU_DYING:
1357                 if (x86_pmu.cpu_dying)
1358                         x86_pmu.cpu_dying(cpu);
1359                 break;
1360
1361         case CPU_UP_CANCELED:
1362         case CPU_DEAD:
1363                 if (x86_pmu.cpu_dead)
1364                         x86_pmu.cpu_dead(cpu);
1365                 break;
1366
1367         default:
1368                 break;
1369         }
1370
1371         return ret;
1372 }
1373
1374 static void __init pmu_check_apic(void)
1375 {
1376         if (cpu_has_apic)
1377                 return;
1378
1379         x86_pmu.apic = 0;
1380         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1381         pr_info("no hardware sampling interrupt available.\n");
1382 }
1383
1384 void __init init_hw_perf_events(void)
1385 {
1386         struct event_constraint *c;
1387         int err;
1388
1389         pr_info("Performance Events: ");
1390
1391         switch (boot_cpu_data.x86_vendor) {
1392         case X86_VENDOR_INTEL:
1393                 err = intel_pmu_init();
1394                 break;
1395         case X86_VENDOR_AMD:
1396                 err = amd_pmu_init();
1397                 break;
1398         default:
1399                 return;
1400         }
1401         if (err != 0) {
1402                 pr_cont("no PMU driver, software events only.\n");
1403                 return;
1404         }
1405
1406         pmu_check_apic();
1407
1408         pr_cont("%s PMU driver.\n", x86_pmu.name);
1409
1410         if (x86_pmu.quirks)
1411                 x86_pmu.quirks();
1412
1413         if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1414                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1415                      x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1416                 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1417         }
1418         x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1419         perf_max_events = x86_pmu.num_counters;
1420
1421         if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1422                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1423                      x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1424                 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1425         }
1426
1427         x86_pmu.intel_ctrl |=
1428                 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1429
1430         perf_events_lapic_init();
1431         register_die_notifier(&perf_event_nmi_notifier);
1432
1433         unconstrained = (struct event_constraint)
1434                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1435                                    0, x86_pmu.num_counters);
1436
1437         if (x86_pmu.event_constraints) {
1438                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1439                         if (c->cmask != X86_RAW_EVENT_MASK)
1440                                 continue;
1441
1442                         c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1443                         c->weight += x86_pmu.num_counters;
1444                 }
1445         }
1446
1447         pr_info("... version:                %d\n",     x86_pmu.version);
1448         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1449         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1450         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1451         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1452         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1453         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1454
1455         perf_cpu_notifier(x86_pmu_notifier);
1456 }
1457
1458 static inline void x86_pmu_read(struct perf_event *event)
1459 {
1460         x86_perf_event_update(event);
1461 }
1462
1463 static const struct pmu pmu = {
1464         .enable         = x86_pmu_enable,
1465         .disable        = x86_pmu_disable,
1466         .start          = x86_pmu_start,
1467         .stop           = x86_pmu_stop,
1468         .read           = x86_pmu_read,
1469         .unthrottle     = x86_pmu_unthrottle,
1470 };
1471
1472 /*
1473  * validate that we can schedule this event
1474  */
1475 static int validate_event(struct perf_event *event)
1476 {
1477         struct cpu_hw_events *fake_cpuc;
1478         struct event_constraint *c;
1479         int ret = 0;
1480
1481         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1482         if (!fake_cpuc)
1483                 return -ENOMEM;
1484
1485         c = x86_pmu.get_event_constraints(fake_cpuc, event);
1486
1487         if (!c || !c->weight)
1488                 ret = -ENOSPC;
1489
1490         if (x86_pmu.put_event_constraints)
1491                 x86_pmu.put_event_constraints(fake_cpuc, event);
1492
1493         kfree(fake_cpuc);
1494
1495         return ret;
1496 }
1497
1498 /*
1499  * validate a single event group
1500  *
1501  * validation include:
1502  *      - check events are compatible which each other
1503  *      - events do not compete for the same counter
1504  *      - number of events <= number of counters
1505  *
1506  * validation ensures the group can be loaded onto the
1507  * PMU if it was the only group available.
1508  */
1509 static int validate_group(struct perf_event *event)
1510 {
1511         struct perf_event *leader = event->group_leader;
1512         struct cpu_hw_events *fake_cpuc;
1513         int ret, n;
1514
1515         ret = -ENOMEM;
1516         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1517         if (!fake_cpuc)
1518                 goto out;
1519
1520         /*
1521          * the event is not yet connected with its
1522          * siblings therefore we must first collect
1523          * existing siblings, then add the new event
1524          * before we can simulate the scheduling
1525          */
1526         ret = -ENOSPC;
1527         n = collect_events(fake_cpuc, leader, true);
1528         if (n < 0)
1529                 goto out_free;
1530
1531         fake_cpuc->n_events = n;
1532         n = collect_events(fake_cpuc, event, false);
1533         if (n < 0)
1534                 goto out_free;
1535
1536         fake_cpuc->n_events = n;
1537
1538         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1539
1540 out_free:
1541         kfree(fake_cpuc);
1542 out:
1543         return ret;
1544 }
1545
1546 const struct pmu *hw_perf_event_init(struct perf_event *event)
1547 {
1548         const struct pmu *tmp;
1549         int err;
1550
1551         err = __hw_perf_event_init(event);
1552         if (!err) {
1553                 /*
1554                  * we temporarily connect event to its pmu
1555                  * such that validate_group() can classify
1556                  * it as an x86 event using is_x86_event()
1557                  */
1558                 tmp = event->pmu;
1559                 event->pmu = &pmu;
1560
1561                 if (event->group_leader != event)
1562                         err = validate_group(event);
1563                 else
1564                         err = validate_event(event);
1565
1566                 event->pmu = tmp;
1567         }
1568         if (err) {
1569                 if (event->destroy)
1570                         event->destroy(event);
1571                 return ERR_PTR(err);
1572         }
1573
1574         return &pmu;
1575 }
1576
1577 /*
1578  * callchain support
1579  */
1580
1581 static inline
1582 void callchain_store(struct perf_callchain_entry *entry, u64 ip)
1583 {
1584         if (entry->nr < PERF_MAX_STACK_DEPTH)
1585                 entry->ip[entry->nr++] = ip;
1586 }
1587
1588 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
1589 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry);
1590
1591
1592 static void
1593 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1594 {
1595         /* Ignore warnings */
1596 }
1597
1598 static void backtrace_warning(void *data, char *msg)
1599 {
1600         /* Ignore warnings */
1601 }
1602
1603 static int backtrace_stack(void *data, char *name)
1604 {
1605         return 0;
1606 }
1607
1608 static void backtrace_address(void *data, unsigned long addr, int reliable)
1609 {
1610         struct perf_callchain_entry *entry = data;
1611
1612         callchain_store(entry, addr);
1613 }
1614
1615 static const struct stacktrace_ops backtrace_ops = {
1616         .warning                = backtrace_warning,
1617         .warning_symbol         = backtrace_warning_symbol,
1618         .stack                  = backtrace_stack,
1619         .address                = backtrace_address,
1620         .walk_stack             = print_context_stack_bp,
1621 };
1622
1623 #include "../dumpstack.h"
1624
1625 static void
1626 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1627 {
1628         callchain_store(entry, PERF_CONTEXT_KERNEL);
1629         callchain_store(entry, regs->ip);
1630
1631         dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
1632 }
1633
1634 #ifdef CONFIG_COMPAT
1635 static inline int
1636 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1637 {
1638         /* 32-bit process in 64-bit kernel. */
1639         struct stack_frame_ia32 frame;
1640         const void __user *fp;
1641
1642         if (!test_thread_flag(TIF_IA32))
1643                 return 0;
1644
1645         fp = compat_ptr(regs->bp);
1646         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1647                 unsigned long bytes;
1648                 frame.next_frame     = 0;
1649                 frame.return_address = 0;
1650
1651                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1652                 if (bytes != sizeof(frame))
1653                         break;
1654
1655                 if (fp < compat_ptr(regs->sp))
1656                         break;
1657
1658                 callchain_store(entry, frame.return_address);
1659                 fp = compat_ptr(frame.next_frame);
1660         }
1661         return 1;
1662 }
1663 #else
1664 static inline int
1665 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1666 {
1667     return 0;
1668 }
1669 #endif
1670
1671 static void
1672 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1673 {
1674         struct stack_frame frame;
1675         const void __user *fp;
1676
1677         if (!user_mode(regs))
1678                 regs = task_pt_regs(current);
1679
1680         fp = (void __user *)regs->bp;
1681
1682         callchain_store(entry, PERF_CONTEXT_USER);
1683         callchain_store(entry, regs->ip);
1684
1685         if (perf_callchain_user32(regs, entry))
1686                 return;
1687
1688         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1689                 unsigned long bytes;
1690                 frame.next_frame             = NULL;
1691                 frame.return_address = 0;
1692
1693                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1694                 if (bytes != sizeof(frame))
1695                         break;
1696
1697                 if ((unsigned long)fp < regs->sp)
1698                         break;
1699
1700                 callchain_store(entry, frame.return_address);
1701                 fp = frame.next_frame;
1702         }
1703 }
1704
1705 static void
1706 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1707 {
1708         int is_user;
1709
1710         if (!regs)
1711                 return;
1712
1713         is_user = user_mode(regs);
1714
1715         if (is_user && current->state != TASK_RUNNING)
1716                 return;
1717
1718         if (!is_user)
1719                 perf_callchain_kernel(regs, entry);
1720
1721         if (current->mm)
1722                 perf_callchain_user(regs, entry);
1723 }
1724
1725 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1726 {
1727         struct perf_callchain_entry *entry;
1728
1729         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1730                 /* TODO: We don't support guest os callchain now */
1731                 return NULL;
1732         }
1733
1734         if (in_nmi())
1735                 entry = &__get_cpu_var(pmc_nmi_entry);
1736         else
1737                 entry = &__get_cpu_var(pmc_irq_entry);
1738
1739         entry->nr = 0;
1740
1741         perf_do_callchain(regs, entry);
1742
1743         return entry;
1744 }
1745
1746 void perf_arch_fetch_caller_regs(struct pt_regs *regs, unsigned long ip, int skip)
1747 {
1748         regs->ip = ip;
1749         /*
1750          * perf_arch_fetch_caller_regs adds another call, we need to increment
1751          * the skip level
1752          */
1753         regs->bp = rewind_frame_pointer(skip + 1);
1754         regs->cs = __KERNEL_CS;
1755         local_save_flags(regs->flags);
1756 }
1757
1758 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1759 {
1760         unsigned long ip;
1761
1762         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1763                 ip = perf_guest_cbs->get_guest_ip();
1764         else
1765                 ip = instruction_pointer(regs);
1766
1767         return ip;
1768 }
1769
1770 unsigned long perf_misc_flags(struct pt_regs *regs)
1771 {
1772         int misc = 0;
1773
1774         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1775                 if (perf_guest_cbs->is_user_mode())
1776                         misc |= PERF_RECORD_MISC_GUEST_USER;
1777                 else
1778                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1779         } else {
1780                 if (user_mode(regs))
1781                         misc |= PERF_RECORD_MISC_USER;
1782                 else
1783                         misc |= PERF_RECORD_MISC_KERNEL;
1784         }
1785
1786         if (regs->flags & PERF_EFLAGS_EXACT)
1787                 misc |= PERF_RECORD_MISC_EXACT;
1788
1789         return misc;
1790 }