arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/highmem.h>
  25 #include <linux/cpu.h>
  26 #include <linux/bitops.h>
  27
  28 #include <asm/apic.h>
  29 #include <asm/stacktrace.h>
  30 #include <asm/nmi.h>
  31
  32 static u64 perf_event_mask __read_mostly;
  33
  34 /* The maximal number of PEBS events: */
  35 #define MAX_PEBS_EVENTS 4
  36
  37 /* The size of a BTS record in bytes: */
  38 #define BTS_RECORD_SIZE         24
  39
  40 /* The size of a per-cpu BTS buffer in bytes: */
  41 #define BTS_BUFFER_SIZE         (BTS_RECORD_SIZE * 2048)
  42
  43 /* The BTS overflow threshold in bytes from the end of the buffer: */
  44 #define BTS_OVFL_TH             (BTS_RECORD_SIZE * 128)
  45
  46
  47 /*
  48  * Bits in the debugctlmsr controlling branch tracing.
  49  */
  50 #define X86_DEBUGCTL_TR                 (1 << 6)
  51 #define X86_DEBUGCTL_BTS                (1 << 7)
  52 #define X86_DEBUGCTL_BTINT              (1 << 8)
  53 #define X86_DEBUGCTL_BTS_OFF_OS         (1 << 9)
  54 #define X86_DEBUGCTL_BTS_OFF_USR        (1 << 10)
  55
  56 /*
  57  * A debug store configuration.
  58  *
  59  * We only support architectures that use 64bit fields.
  60  */
  61 struct debug_store {
  62         u64     bts_buffer_base;
  63         u64     bts_index;
  64         u64     bts_absolute_maximum;
  65         u64     bts_interrupt_threshold;
  66         u64     pebs_buffer_base;
  67         u64     pebs_index;
  68         u64     pebs_absolute_maximum;
  69         u64     pebs_interrupt_threshold;
  70         u64     pebs_event_reset[MAX_PEBS_EVENTS];
  71 };
  72
  73 struct event_constraint {
  74         union {
  75                 unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  76                 u64             idxmsk64[1];
  77         };
  78         int     code;
  79         int     cmask;
  80         int     weight;
  81 };
  82
  83 struct amd_nb {
  84         int nb_id;  /* NorthBridge id */
  85         int refcnt; /* reference count */
  86         struct perf_event *owners[X86_PMC_IDX_MAX];
  87         struct event_constraint event_constraints[X86_PMC_IDX_MAX];
  88 };
  89
  90 struct cpu_hw_events {
  91         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
  92         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  93         unsigned long           interrupts;
  94         int                     enabled;
  95         struct debug_store      *ds;
  96
  97         int                     n_events;
  98         int                     n_added;
  99         int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
 100         u64                     tags[X86_PMC_IDX_MAX];
 101         struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
 102         struct amd_nb           *amd_nb;
 103 };
 104
 105 #define __EVENT_CONSTRAINT(c, n, m, w) {\
 106         { .idxmsk64[0] = (n) },         \
 107         .code = (c),                    \
 108         .cmask = (m),                   \
 109         .weight = (w),                  \
 110 }
 111
 112 #define EVENT_CONSTRAINT(c, n, m)       \
 113         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
 114
 115 #define INTEL_EVENT_CONSTRAINT(c, n)    \
 116         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVTSEL_MASK)
 117
 118 #define FIXED_EVENT_CONSTRAINT(c, n)    \
 119         EVENT_CONSTRAINT(c, n, INTEL_ARCH_FIXED_MASK)
 120
 121 #define EVENT_CONSTRAINT_END            \
 122         EVENT_CONSTRAINT(0, 0, 0)
 123
 124 #define for_each_event_constraint(e, c) \
 125         for ((e) = (c); (e)->cmask; (e)++)
 126
 127 /*
 128  * struct x86_pmu - generic x86 pmu
 129  */
 130 struct x86_pmu {
 131         const char      *name;
 132         int             version;
 133         int             (*handle_irq)(struct pt_regs *);
 134         void            (*disable_all)(void);
 135         void            (*enable_all)(void);
 136         void            (*enable)(struct hw_perf_event *, int);
 137         void            (*disable)(struct hw_perf_event *, int);
 138         unsigned        eventsel;
 139         unsigned        perfctr;
 140         u64             (*event_map)(int);
 141         u64             (*raw_event)(u64);
 142         int             max_events;
 143         int             num_events;
 144         int             num_events_fixed;
 145         int             event_bits;
 146         u64             event_mask;
 147         int             apic;
 148         u64             max_period;
 149         u64             intel_ctrl;
 150         void            (*enable_bts)(u64 config);
 151         void            (*disable_bts)(void);
 152
 153         struct event_constraint *
 154                         (*get_event_constraints)(struct cpu_hw_events *cpuc,
 155                                                  struct perf_event *event);
 156
 157         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
 158                                                  struct perf_event *event);
 159         struct event_constraint *event_constraints;
 160 };
 161
 162 static struct x86_pmu x86_pmu __read_mostly;
 163
 164 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
 165         .enabled = 1,
 166 };
 167
 168 static int x86_perf_event_set_period(struct perf_event *event,
 169                              struct hw_perf_event *hwc, int idx);
 170
 171 /*
 172  * Generalized hw caching related hw_event table, filled
 173  * in on a per model basis. A value of 0 means
 174  * 'not supported', -1 means 'hw_event makes no sense on
 175  * this CPU', any other value means the raw hw_event
 176  * ID.
 177  */
 178
 179 #define C(x) PERF_COUNT_HW_CACHE_##x
 180
 181 static u64 __read_mostly hw_cache_event_ids
 182                                 [PERF_COUNT_HW_CACHE_MAX]
 183                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 184                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 185
 186 /*
 187  * Propagate event elapsed time into the generic event.
 188  * Can only be executed on the CPU where the event is active.
 189  * Returns the delta events processed.
 190  */
 191 static u64
 192 x86_perf_event_update(struct perf_event *event,
 193                         struct hw_perf_event *hwc, int idx)
 194 {
 195         int shift = 64 - x86_pmu.event_bits;
 196         u64 prev_raw_count, new_raw_count;
 197         s64 delta;
 198
 199         if (idx == X86_PMC_IDX_FIXED_BTS)
 200                 return 0;
 201
 202         /*
 203          * Careful: an NMI might modify the previous event value.
 204          *
 205          * Our tactic to handle this is to first atomically read and
 206          * exchange a new raw count - then add that new-prev delta
 207          * count to the generic event atomically:
 208          */
 209 again:
 210         prev_raw_count = atomic64_read(&hwc->prev_count);
 211         rdmsrl(hwc->event_base + idx, new_raw_count);
 212
 213         if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
 214                                         new_raw_count) != prev_raw_count)
 215                 goto again;
 216
 217         /*
 218          * Now we have the new raw value and have updated the prev
 219          * timestamp already. We can now calculate the elapsed delta
 220          * (event-)time and add that to the generic event.
 221          *
 222          * Careful, not all hw sign-extends above the physical width
 223          * of the count.
 224          */
 225         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 226         delta >>= shift;
 227
 228         atomic64_add(delta, &event->count);
 229         atomic64_sub(delta, &hwc->period_left);
 230
 231         return new_raw_count;
 232 }
 233
 234 static atomic_t active_events;
 235 static DEFINE_MUTEX(pmc_reserve_mutex);
 236
 237 static bool reserve_pmc_hardware(void)
 238 {
 239 #ifdef CONFIG_X86_LOCAL_APIC
 240         int i;
 241
 242         if (nmi_watchdog == NMI_LOCAL_APIC)
 243                 disable_lapic_nmi_watchdog();
 244
 245         for (i = 0; i < x86_pmu.num_events; i++) {
 246                 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
 247                         goto perfctr_fail;
 248         }
 249
 250         for (i = 0; i < x86_pmu.num_events; i++) {
 251                 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
 252                         goto eventsel_fail;
 253         }
 254 #endif
 255
 256         return true;
 257
 258 #ifdef CONFIG_X86_LOCAL_APIC
 259 eventsel_fail:
 260         for (i--; i >= 0; i--)
 261                 release_evntsel_nmi(x86_pmu.eventsel + i);
 262
 263         i = x86_pmu.num_events;
 264
 265 perfctr_fail:
 266         for (i--; i >= 0; i--)
 267                 release_perfctr_nmi(x86_pmu.perfctr + i);
 268
 269         if (nmi_watchdog == NMI_LOCAL_APIC)
 270                 enable_lapic_nmi_watchdog();
 271
 272         return false;
 273 #endif
 274 }
 275
 276 static void release_pmc_hardware(void)
 277 {
 278 #ifdef CONFIG_X86_LOCAL_APIC
 279         int i;
 280
 281         for (i = 0; i < x86_pmu.num_events; i++) {
 282                 release_perfctr_nmi(x86_pmu.perfctr + i);
 283                 release_evntsel_nmi(x86_pmu.eventsel + i);
 284         }
 285
 286         if (nmi_watchdog == NMI_LOCAL_APIC)
 287                 enable_lapic_nmi_watchdog();
 288 #endif
 289 }
 290
 291 static inline bool bts_available(void)
 292 {
 293         return x86_pmu.enable_bts != NULL;
 294 }
 295
 296 static inline void init_debug_store_on_cpu(int cpu)
 297 {
 298         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 299
 300         if (!ds)
 301                 return;
 302
 303         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
 304                      (u32)((u64)(unsigned long)ds),
 305                      (u32)((u64)(unsigned long)ds >> 32));
 306 }
 307
 308 static inline void fini_debug_store_on_cpu(int cpu)
 309 {
 310         if (!per_cpu(cpu_hw_events, cpu).ds)
 311                 return;
 312
 313         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
 314 }
 315
 316 static void release_bts_hardware(void)
 317 {
 318         int cpu;
 319
 320         if (!bts_available())
 321                 return;
 322
 323         get_online_cpus();
 324
 325         for_each_online_cpu(cpu)
 326                 fini_debug_store_on_cpu(cpu);
 327
 328         for_each_possible_cpu(cpu) {
 329                 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 330
 331                 if (!ds)
 332                         continue;
 333
 334                 per_cpu(cpu_hw_events, cpu).ds = NULL;
 335
 336                 kfree((void *)(unsigned long)ds->bts_buffer_base);
 337                 kfree(ds);
 338         }
 339
 340         put_online_cpus();
 341 }
 342
 343 static int reserve_bts_hardware(void)
 344 {
 345         int cpu, err = 0;
 346
 347         if (!bts_available())
 348                 return 0;
 349
 350         get_online_cpus();
 351
 352         for_each_possible_cpu(cpu) {
 353                 struct debug_store *ds;
 354                 void *buffer;
 355
 356                 err = -ENOMEM;
 357                 buffer = kzalloc(BTS_BUFFER_SIZE, GFP_KERNEL);
 358                 if (unlikely(!buffer))
 359                         break;
 360
 361                 ds = kzalloc(sizeof(*ds), GFP_KERNEL);
 362                 if (unlikely(!ds)) {
 363                         kfree(buffer);
 364                         break;
 365                 }
 366
 367                 ds->bts_buffer_base = (u64)(unsigned long)buffer;
 368                 ds->bts_index = ds->bts_buffer_base;
 369                 ds->bts_absolute_maximum =
 370                         ds->bts_buffer_base + BTS_BUFFER_SIZE;
 371                 ds->bts_interrupt_threshold =
 372                         ds->bts_absolute_maximum - BTS_OVFL_TH;
 373
 374                 per_cpu(cpu_hw_events, cpu).ds = ds;
 375                 err = 0;
 376         }
 377
 378         if (err)
 379                 release_bts_hardware();
 380         else {
 381                 for_each_online_cpu(cpu)
 382                         init_debug_store_on_cpu(cpu);
 383         }
 384
 385         put_online_cpus();
 386
 387         return err;
 388 }
 389
 390 static void hw_perf_event_destroy(struct perf_event *event)
 391 {
 392         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 393                 release_pmc_hardware();
 394                 release_bts_hardware();
 395                 mutex_unlock(&pmc_reserve_mutex);
 396         }
 397 }
 398
 399 static inline int x86_pmu_initialized(void)
 400 {
 401         return x86_pmu.handle_irq != NULL;
 402 }
 403
 404 static inline int
 405 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
 406 {
 407         unsigned int cache_type, cache_op, cache_result;
 408         u64 config, val;
 409
 410         config = attr->config;
 411
 412         cache_type = (config >>  0) & 0xff;
 413         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 414                 return -EINVAL;
 415
 416         cache_op = (config >>  8) & 0xff;
 417         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 418                 return -EINVAL;
 419
 420         cache_result = (config >> 16) & 0xff;
 421         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 422                 return -EINVAL;
 423
 424         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 425
 426         if (val == 0)
 427                 return -ENOENT;
 428
 429         if (val == -1)
 430                 return -EINVAL;
 431
 432         hwc->config |= val;
 433
 434         return 0;
 435 }
 436
 437 /*
 438  * Setup the hardware configuration for a given attr_type
 439  */
 440 static int __hw_perf_event_init(struct perf_event *event)
 441 {
 442         struct perf_event_attr *attr = &event->attr;
 443         struct hw_perf_event *hwc = &event->hw;
 444         u64 config;
 445         int err;
 446
 447         if (!x86_pmu_initialized())
 448                 return -ENODEV;
 449
 450         err = 0;
 451         if (!atomic_inc_not_zero(&active_events)) {
 452                 mutex_lock(&pmc_reserve_mutex);
 453                 if (atomic_read(&active_events) == 0) {
 454                         if (!reserve_pmc_hardware())
 455                                 err = -EBUSY;
 456                         else
 457                                 err = reserve_bts_hardware();
 458                 }
 459                 if (!err)
 460                         atomic_inc(&active_events);
 461                 mutex_unlock(&pmc_reserve_mutex);
 462         }
 463         if (err)
 464                 return err;
 465
 466         event->destroy = hw_perf_event_destroy;
 467
 468         /*
 469          * Generate PMC IRQs:
 470          * (keep 'enabled' bit clear for now)
 471          */
 472         hwc->config = ARCH_PERFMON_EVENTSEL_INT;
 473
 474         hwc->idx = -1;
 475         hwc->last_cpu = -1;
 476         hwc->last_tag = ~0ULL;
 477
 478         /*
 479          * Count user and OS events unless requested not to.
 480          */
 481         if (!attr->exclude_user)
 482                 hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
 483         if (!attr->exclude_kernel)
 484                 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
 485
 486         if (!hwc->sample_period) {
 487                 hwc->sample_period = x86_pmu.max_period;
 488                 hwc->last_period = hwc->sample_period;
 489                 atomic64_set(&hwc->period_left, hwc->sample_period);
 490         } else {
 491                 /*
 492                  * If we have a PMU initialized but no APIC
 493                  * interrupts, we cannot sample hardware
 494                  * events (user-space has to fall back and
 495                  * sample via a hrtimer based software event):
 496                  */
 497                 if (!x86_pmu.apic)
 498                         return -EOPNOTSUPP;
 499         }
 500
 501         /*
 502          * Raw hw_event type provide the config in the hw_event structure
 503          */
 504         if (attr->type == PERF_TYPE_RAW) {
 505                 hwc->config |= x86_pmu.raw_event(attr->config);
 506                 return 0;
 507         }
 508
 509         if (attr->type == PERF_TYPE_HW_CACHE)
 510                 return set_ext_hw_attr(hwc, attr);
 511
 512         if (attr->config >= x86_pmu.max_events)
 513                 return -EINVAL;
 514
 515         /*
 516          * The generic map:
 517          */
 518         config = x86_pmu.event_map(attr->config);
 519
 520         if (config == 0)
 521                 return -ENOENT;
 522
 523         if (config == -1LL)
 524                 return -EINVAL;
 525
 526         /*
 527          * Branch tracing:
 528          */
 529         if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
 530             (hwc->sample_period == 1)) {
 531                 /* BTS is not supported by this architecture. */
 532                 if (!bts_available())
 533                         return -EOPNOTSUPP;
 534
 535                 /* BTS is currently only allowed for user-mode. */
 536                 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
 537                         return -EOPNOTSUPP;
 538         }
 539
 540         hwc->config |= config;
 541
 542         return 0;
 543 }
 544
 545 static void x86_pmu_disable_all(void)
 546 {
 547         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 548         int idx;
 549
 550         for (idx = 0; idx < x86_pmu.num_events; idx++) {
 551                 u64 val;
 552
 553                 if (!test_bit(idx, cpuc->active_mask))
 554                         continue;
 555                 rdmsrl(x86_pmu.eventsel + idx, val);
 556                 if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE))
 557                         continue;
 558                 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
 559                 wrmsrl(x86_pmu.eventsel + idx, val);
 560         }
 561 }
 562
 563 void hw_perf_disable(void)
 564 {
 565         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 566
 567         if (!x86_pmu_initialized())
 568                 return;
 569
 570         if (!cpuc->enabled)
 571                 return;
 572
 573         cpuc->n_added = 0;
 574         cpuc->enabled = 0;
 575         barrier();
 576
 577         x86_pmu.disable_all();
 578 }
 579
 580 static void x86_pmu_enable_all(void)
 581 {
 582         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 583         int idx;
 584
 585         for (idx = 0; idx < x86_pmu.num_events; idx++) {
 586                 struct perf_event *event = cpuc->events[idx];
 587                 u64 val;
 588
 589                 if (!test_bit(idx, cpuc->active_mask))
 590                         continue;
 591
 592                 val = event->hw.config;
 593                 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
 594                 wrmsrl(x86_pmu.eventsel + idx, val);
 595         }
 596 }
 597
 598 static const struct pmu pmu;
 599
 600 static inline int is_x86_event(struct perf_event *event)
 601 {
 602         return event->pmu == &pmu;
 603 }
 604
 605 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 606 {
 607         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
 608         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 609         int i, j, w, wmax, num = 0;
 610         struct hw_perf_event *hwc;
 611
 612         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 613
 614         for (i = 0; i < n; i++) {
 615                 constraints[i] =
 616                   x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 617         }
 618
 619         /*
 620          * fastpath, try to reuse previous register
 621          */
 622         for (i = 0; i < n; i++) {
 623                 hwc = &cpuc->event_list[i]->hw;
 624                 c = constraints[i];
 625
 626                 /* never assigned */
 627                 if (hwc->idx == -1)
 628                         break;
 629
 630                 /* constraint still honored */
 631                 if (!test_bit(hwc->idx, c->idxmsk))
 632                         break;
 633
 634                 /* not already used */
 635                 if (test_bit(hwc->idx, used_mask))
 636                         break;
 637
 638                 set_bit(hwc->idx, used_mask);
 639                 if (assign)
 640                         assign[i] = hwc->idx;
 641         }
 642         if (i == n)
 643                 goto done;
 644
 645         /*
 646          * begin slow path
 647          */
 648
 649         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 650
 651         /*
 652          * weight = number of possible counters
 653          *
 654          * 1    = most constrained, only works on one counter
 655          * wmax = least constrained, works on any counter
 656          *
 657          * assign events to counters starting with most
 658          * constrained events.
 659          */
 660         wmax = x86_pmu.num_events;
 661
 662         /*
 663          * when fixed event counters are present,
 664          * wmax is incremented by 1 to account
 665          * for one more choice
 666          */
 667         if (x86_pmu.num_events_fixed)
 668                 wmax++;
 669
 670         for (w = 1, num = n; num && w <= wmax; w++) {
 671                 /* for each event */
 672                 for (i = 0; num && i < n; i++) {
 673                         c = constraints[i];
 674                         hwc = &cpuc->event_list[i]->hw;
 675
 676                         if (c->weight != w)
 677                                 continue;
 678
 679                         for_each_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
 680                                 if (!test_bit(j, used_mask))
 681                                         break;
 682                         }
 683
 684                         if (j == X86_PMC_IDX_MAX)
 685                                 break;
 686
 687                         set_bit(j, used_mask);
 688
 689                         if (assign)
 690                                 assign[i] = j;
 691                         num--;
 692                 }
 693         }
 694 done:
 695         /*
 696          * scheduling failed or is just a simulation,
 697          * free resources if necessary
 698          */
 699         if (!assign || num) {
 700                 for (i = 0; i < n; i++) {
 701                         if (x86_pmu.put_event_constraints)
 702                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
 703                 }
 704         }
 705         return num ? -ENOSPC : 0;
 706 }
 707
 708 /*
 709  * dogrp: true if must collect siblings events (group)
 710  * returns total number of events and error code
 711  */
 712 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 713 {
 714         struct perf_event *event;
 715         int n, max_count;
 716
 717         max_count = x86_pmu.num_events + x86_pmu.num_events_fixed;
 718
 719         /* current number of events already accepted */
 720         n = cpuc->n_events;
 721
 722         if (is_x86_event(leader)) {
 723                 if (n >= max_count)
 724                         return -ENOSPC;
 725                 cpuc->event_list[n] = leader;
 726                 n++;
 727         }
 728         if (!dogrp)
 729                 return n;
 730
 731         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 732                 if (!is_x86_event(event) ||
 733                     event->state <= PERF_EVENT_STATE_OFF)
 734                         continue;
 735
 736                 if (n >= max_count)
 737                         return -ENOSPC;
 738
 739                 cpuc->event_list[n] = event;
 740                 n++;
 741         }
 742         return n;
 743 }
 744
 745 static inline void x86_assign_hw_event(struct perf_event *event,
 746                                 struct cpu_hw_events *cpuc, int i)
 747 {
 748         struct hw_perf_event *hwc = &event->hw;
 749
 750         hwc->idx = cpuc->assign[i];
 751         hwc->last_cpu = smp_processor_id();
 752         hwc->last_tag = ++cpuc->tags[i];
 753
 754         if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
 755                 hwc->config_base = 0;
 756                 hwc->event_base = 0;
 757         } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
 758                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 759                 /*
 760                  * We set it so that event_base + idx in wrmsr/rdmsr maps to
 761                  * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
 762                  */
 763                 hwc->event_base =
 764                         MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
 765         } else {
 766                 hwc->config_base = x86_pmu.eventsel;
 767                 hwc->event_base  = x86_pmu.perfctr;
 768         }
 769 }
 770
 771 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 772                                         struct cpu_hw_events *cpuc,
 773                                         int i)
 774 {
 775         return hwc->idx == cpuc->assign[i] &&
 776                 hwc->last_cpu == smp_processor_id() &&
 777                 hwc->last_tag == cpuc->tags[i];
 778 }
 779
 780 static void x86_pmu_stop(struct perf_event *event);
 781
 782 void hw_perf_enable(void)
 783 {
 784         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 785         struct perf_event *event;
 786         struct hw_perf_event *hwc;
 787         int i;
 788
 789         if (!x86_pmu_initialized())
 790                 return;
 791
 792         if (cpuc->enabled)
 793                 return;
 794
 795         if (cpuc->n_added) {
 796                 /*
 797                  * apply assignment obtained either from
 798                  * hw_perf_group_sched_in() or x86_pmu_enable()
 799                  *
 800                  * step1: save events moving to new counters
 801                  * step2: reprogram moved events into new counters
 802                  */
 803                 for (i = 0; i < cpuc->n_events; i++) {
 804
 805                         event = cpuc->event_list[i];
 806                         hwc = &event->hw;
 807
 808                         /*
 809                          * we can avoid reprogramming counter if:
 810                          * - assigned same counter as last time
 811                          * - running on same CPU as last time
 812                          * - no other event has used the counter since
 813                          */
 814                         if (hwc->idx == -1 ||
 815                             match_prev_assignment(hwc, cpuc, i))
 816                                 continue;
 817
 818                         x86_pmu_stop(event);
 819
 820                         hwc->idx = -1;
 821                 }
 822
 823                 for (i = 0; i < cpuc->n_events; i++) {
 824
 825                         event = cpuc->event_list[i];
 826                         hwc = &event->hw;
 827
 828                         if (hwc->idx == -1) {
 829                                 x86_assign_hw_event(event, cpuc, i);
 830                                 x86_perf_event_set_period(event, hwc, hwc->idx);
 831                         }
 832                         /*
 833                          * need to mark as active because x86_pmu_disable()
 834                          * clear active_mask and events[] yet it preserves
 835                          * idx
 836                          */
 837                         set_bit(hwc->idx, cpuc->active_mask);
 838                         cpuc->events[hwc->idx] = event;
 839
 840                         x86_pmu.enable(hwc, hwc->idx);
 841                         perf_event_update_userpage(event);
 842                 }
 843                 cpuc->n_added = 0;
 844                 perf_events_lapic_init();
 845         }
 846
 847         cpuc->enabled = 1;
 848         barrier();
 849
 850         x86_pmu.enable_all();
 851 }
 852
 853 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
 854 {
 855         (void)checking_wrmsrl(hwc->config_base + idx,
 856                               hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE);
 857 }
 858
 859 static inline void x86_pmu_disable_event(struct hw_perf_event *hwc, int idx)
 860 {
 861         (void)checking_wrmsrl(hwc->config_base + idx, hwc->config);
 862 }
 863
 864 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
 865
 866 /*
 867  * Set the next IRQ period, based on the hwc->period_left value.
 868  * To be called with the event disabled in hw:
 869  */
 870 static int
 871 x86_perf_event_set_period(struct perf_event *event,
 872                              struct hw_perf_event *hwc, int idx)
 873 {
 874         s64 left = atomic64_read(&hwc->period_left);
 875         s64 period = hwc->sample_period;
 876         int err, ret = 0;
 877
 878         if (idx == X86_PMC_IDX_FIXED_BTS)
 879                 return 0;
 880
 881         /*
 882          * If we are way outside a reasonable range then just skip forward:
 883          */
 884         if (unlikely(left <= -period)) {
 885                 left = period;
 886                 atomic64_set(&hwc->period_left, left);
 887                 hwc->last_period = period;
 888                 ret = 1;
 889         }
 890
 891         if (unlikely(left <= 0)) {
 892                 left += period;
 893                 atomic64_set(&hwc->period_left, left);
 894                 hwc->last_period = period;
 895                 ret = 1;
 896         }
 897         /*
 898          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
 899          */
 900         if (unlikely(left < 2))
 901                 left = 2;
 902
 903         if (left > x86_pmu.max_period)
 904                 left = x86_pmu.max_period;
 905
 906         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
 907
 908         /*
 909          * The hw event starts counting from this event offset,
 910          * mark it to be able to extra future deltas:
 911          */
 912         atomic64_set(&hwc->prev_count, (u64)-left);
 913
 914         err = checking_wrmsrl(hwc->event_base + idx,
 915                              (u64)(-left) & x86_pmu.event_mask);
 916
 917         perf_event_update_userpage(event);
 918
 919         return ret;
 920 }
 921
 922 static void x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
 923 {
 924         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 925         if (cpuc->enabled)
 926                 __x86_pmu_enable_event(hwc, idx);
 927 }
 928
 929 /*
 930  * activate a single event
 931  *
 932  * The event is added to the group of enabled events
 933  * but only if it can be scehduled with existing events.
 934  *
 935  * Called with PMU disabled. If successful and return value 1,
 936  * then guaranteed to call perf_enable() and hw_perf_enable()
 937  */
 938 static int x86_pmu_enable(struct perf_event *event)
 939 {
 940         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 941         struct hw_perf_event *hwc;
 942         int assign[X86_PMC_IDX_MAX];
 943         int n, n0, ret;
 944
 945         hwc = &event->hw;
 946
 947         n0 = cpuc->n_events;
 948         n = collect_events(cpuc, event, false);
 949         if (n < 0)
 950                 return n;
 951
 952         ret = x86_schedule_events(cpuc, n, assign);
 953         if (ret)
 954                 return ret;
 955         /*
 956          * copy new assignment, now we know it is possible
 957          * will be used by hw_perf_enable()
 958          */
 959         memcpy(cpuc->assign, assign, n*sizeof(int));
 960
 961         cpuc->n_events = n;
 962         cpuc->n_added  = n - n0;
 963
 964         return 0;
 965 }
 966
 967 static int x86_pmu_start(struct perf_event *event)
 968 {
 969         struct hw_perf_event *hwc = &event->hw;
 970
 971         if (hwc->idx == -1)
 972                 return -EAGAIN;
 973
 974         x86_perf_event_set_period(event, hwc, hwc->idx);
 975         x86_pmu.enable(hwc, hwc->idx);
 976
 977         return 0;
 978 }
 979
 980 static void x86_pmu_unthrottle(struct perf_event *event)
 981 {
 982         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 983         struct hw_perf_event *hwc = &event->hw;
 984
 985         if (WARN_ON_ONCE(hwc->idx >= X86_PMC_IDX_MAX ||
 986                                 cpuc->events[hwc->idx] != event))
 987                 return;
 988
 989         x86_pmu.enable(hwc, hwc->idx);
 990 }
 991
 992 void perf_event_print_debug(void)
 993 {
 994         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
 995         struct cpu_hw_events *cpuc;
 996         unsigned long flags;
 997         int cpu, idx;
 998
 999         if (!x86_pmu.num_events)
1000                 return;
1001
1002         local_irq_save(flags);
1003
1004         cpu = smp_processor_id();
1005         cpuc = &per_cpu(cpu_hw_events, cpu);
1006
1007         if (x86_pmu.version >= 2) {
1008                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1009                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1010                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1011                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1012
1013                 pr_info("\n");
1014                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1015                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1016                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1017                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1018         }
1019         pr_info("CPU#%d: active:       %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1020
1021         for (idx = 0; idx < x86_pmu.num_events; idx++) {
1022                 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1023                 rdmsrl(x86_pmu.perfctr  + idx, pmc_count);
1024
1025                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1026
1027                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1028                         cpu, idx, pmc_ctrl);
1029                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1030                         cpu, idx, pmc_count);
1031                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1032                         cpu, idx, prev_left);
1033         }
1034         for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
1035                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1036
1037                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1038                         cpu, idx, pmc_count);
1039         }
1040         local_irq_restore(flags);
1041 }
1042
1043 static void x86_pmu_stop(struct perf_event *event)
1044 {
1045         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1046         struct hw_perf_event *hwc = &event->hw;
1047         int idx = hwc->idx;
1048
1049         /*
1050          * Must be done before we disable, otherwise the nmi handler
1051          * could reenable again:
1052          */
1053         clear_bit(idx, cpuc->active_mask);
1054         x86_pmu.disable(hwc, idx);
1055
1056         /*
1057          * Drain the remaining delta count out of a event
1058          * that we are disabling:
1059          */
1060         x86_perf_event_update(event, hwc, idx);
1061
1062         cpuc->events[idx] = NULL;
1063 }
1064
1065 static void x86_pmu_disable(struct perf_event *event)
1066 {
1067         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1068         int i;
1069
1070         x86_pmu_stop(event);
1071
1072         for (i = 0; i < cpuc->n_events; i++) {
1073                 if (event == cpuc->event_list[i]) {
1074
1075                         if (x86_pmu.put_event_constraints)
1076                                 x86_pmu.put_event_constraints(cpuc, event);
1077
1078                         while (++i < cpuc->n_events)
1079                                 cpuc->event_list[i-1] = cpuc->event_list[i];
1080
1081                         --cpuc->n_events;
1082                         break;
1083                 }
1084         }
1085         perf_event_update_userpage(event);
1086 }
1087
1088 static int x86_pmu_handle_irq(struct pt_regs *regs)
1089 {
1090         struct perf_sample_data data;
1091         struct cpu_hw_events *cpuc;
1092         struct perf_event *event;
1093         struct hw_perf_event *hwc;
1094         int idx, handled = 0;
1095         u64 val;
1096
1097         data.addr = 0;
1098         data.raw = NULL;
1099
1100         cpuc = &__get_cpu_var(cpu_hw_events);
1101
1102         for (idx = 0; idx < x86_pmu.num_events; idx++) {
1103                 if (!test_bit(idx, cpuc->active_mask))
1104                         continue;
1105
1106                 event = cpuc->events[idx];
1107                 hwc = &event->hw;
1108
1109                 val = x86_perf_event_update(event, hwc, idx);
1110                 if (val & (1ULL << (x86_pmu.event_bits - 1)))
1111                         continue;
1112
1113                 /*
1114                  * event overflow
1115                  */
1116                 handled         = 1;
1117                 data.period     = event->hw.last_period;
1118
1119                 if (!x86_perf_event_set_period(event, hwc, idx))
1120                         continue;
1121
1122                 if (perf_event_overflow(event, 1, &data, regs))
1123                         x86_pmu.disable(hwc, idx);
1124         }
1125
1126         if (handled)
1127                 inc_irq_stat(apic_perf_irqs);
1128
1129         return handled;
1130 }
1131
1132 void smp_perf_pending_interrupt(struct pt_regs *regs)
1133 {
1134         irq_enter();
1135         ack_APIC_irq();
1136         inc_irq_stat(apic_pending_irqs);
1137         perf_event_do_pending();
1138         irq_exit();
1139 }
1140
1141 void set_perf_event_pending(void)
1142 {
1143 #ifdef CONFIG_X86_LOCAL_APIC
1144         if (!x86_pmu.apic || !x86_pmu_initialized())
1145                 return;
1146
1147         apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1148 #endif
1149 }
1150
1151 void perf_events_lapic_init(void)
1152 {
1153 #ifdef CONFIG_X86_LOCAL_APIC
1154         if (!x86_pmu.apic || !x86_pmu_initialized())
1155                 return;
1156
1157         /*
1158          * Always use NMI for PMU
1159          */
1160         apic_write(APIC_LVTPC, APIC_DM_NMI);
1161 #endif
1162 }
1163
1164 static int __kprobes
1165 perf_event_nmi_handler(struct notifier_block *self,
1166                          unsigned long cmd, void *__args)
1167 {
1168         struct die_args *args = __args;
1169         struct pt_regs *regs;
1170
1171         if (!atomic_read(&active_events))
1172                 return NOTIFY_DONE;
1173
1174         switch (cmd) {
1175         case DIE_NMI:
1176         case DIE_NMI_IPI:
1177                 break;
1178
1179         default:
1180                 return NOTIFY_DONE;
1181         }
1182
1183         regs = args->regs;
1184
1185 #ifdef CONFIG_X86_LOCAL_APIC
1186         apic_write(APIC_LVTPC, APIC_DM_NMI);
1187 #endif
1188         /*
1189          * Can't rely on the handled return value to say it was our NMI, two
1190          * events could trigger 'simultaneously' raising two back-to-back NMIs.
1191          *
1192          * If the first NMI handles both, the latter will be empty and daze
1193          * the CPU.
1194          */
1195         x86_pmu.handle_irq(regs);
1196
1197         return NOTIFY_STOP;
1198 }
1199
1200 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1201         .notifier_call          = perf_event_nmi_handler,
1202         .next                   = NULL,
1203         .priority               = 1
1204 };
1205
1206 static struct event_constraint unconstrained;
1207 static struct event_constraint emptyconstraint;
1208
1209 static struct event_constraint *
1210 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1211 {
1212         struct event_constraint *c;
1213
1214         if (x86_pmu.event_constraints) {
1215                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1216                         if ((event->hw.config & c->cmask) == c->code)
1217                                 return c;
1218                 }
1219         }
1220
1221         return &unconstrained;
1222 }
1223
1224 static int x86_event_sched_in(struct perf_event *event,
1225                           struct perf_cpu_context *cpuctx)
1226 {
1227         int ret = 0;
1228
1229         event->state = PERF_EVENT_STATE_ACTIVE;
1230         event->oncpu = smp_processor_id();
1231         event->tstamp_running += event->ctx->time - event->tstamp_stopped;
1232
1233         if (!is_x86_event(event))
1234                 ret = event->pmu->enable(event);
1235
1236         if (!ret && !is_software_event(event))
1237                 cpuctx->active_oncpu++;
1238
1239         if (!ret && event->attr.exclusive)
1240                 cpuctx->exclusive = 1;
1241
1242         return ret;
1243 }
1244
1245 static void x86_event_sched_out(struct perf_event *event,
1246                             struct perf_cpu_context *cpuctx)
1247 {
1248         event->state = PERF_EVENT_STATE_INACTIVE;
1249         event->oncpu = -1;
1250
1251         if (!is_x86_event(event))
1252                 event->pmu->disable(event);
1253
1254         event->tstamp_running -= event->ctx->time - event->tstamp_stopped;
1255
1256         if (!is_software_event(event))
1257                 cpuctx->active_oncpu--;
1258
1259         if (event->attr.exclusive || !cpuctx->active_oncpu)
1260                 cpuctx->exclusive = 0;
1261 }
1262
1263 /*
1264  * Called to enable a whole group of events.
1265  * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
1266  * Assumes the caller has disabled interrupts and has
1267  * frozen the PMU with hw_perf_save_disable.
1268  *
1269  * called with PMU disabled. If successful and return value 1,
1270  * then guaranteed to call perf_enable() and hw_perf_enable()
1271  */
1272 int hw_perf_group_sched_in(struct perf_event *leader,
1273                struct perf_cpu_context *cpuctx,
1274                struct perf_event_context *ctx)
1275 {
1276         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1277         struct perf_event *sub;
1278         int assign[X86_PMC_IDX_MAX];
1279         int n0, n1, ret;
1280
1281         /* n0 = total number of events */
1282         n0 = collect_events(cpuc, leader, true);
1283         if (n0 < 0)
1284                 return n0;
1285
1286         ret = x86_schedule_events(cpuc, n0, assign);
1287         if (ret)
1288                 return ret;
1289
1290         ret = x86_event_sched_in(leader, cpuctx);
1291         if (ret)
1292                 return ret;
1293
1294         n1 = 1;
1295         list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1296                 if (sub->state > PERF_EVENT_STATE_OFF) {
1297                         ret = x86_event_sched_in(sub, cpuctx);
1298                         if (ret)
1299                                 goto undo;
1300                         ++n1;
1301                 }
1302         }
1303         /*
1304          * copy new assignment, now we know it is possible
1305          * will be used by hw_perf_enable()
1306          */
1307         memcpy(cpuc->assign, assign, n0*sizeof(int));
1308
1309         cpuc->n_events  = n0;
1310         cpuc->n_added   = n1;
1311         ctx->nr_active += n1;
1312
1313         /*
1314          * 1 means successful and events are active
1315          * This is not quite true because we defer
1316          * actual activation until hw_perf_enable() but
1317          * this way we* ensure caller won't try to enable
1318          * individual events
1319          */
1320         return 1;
1321 undo:
1322         x86_event_sched_out(leader, cpuctx);
1323         n0  = 1;
1324         list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1325                 if (sub->state == PERF_EVENT_STATE_ACTIVE) {
1326                         x86_event_sched_out(sub, cpuctx);
1327                         if (++n0 == n1)
1328                                 break;
1329                 }
1330         }
1331         return ret;
1332 }
1333
1334 #include "perf_event_amd.c"
1335 #include "perf_event_p6.c"
1336 #include "perf_event_intel.c"
1337
1338 static void __init pmu_check_apic(void)
1339 {
1340         if (cpu_has_apic)
1341                 return;
1342
1343         x86_pmu.apic = 0;
1344         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1345         pr_info("no hardware sampling interrupt available.\n");
1346 }
1347
1348 void __init init_hw_perf_events(void)
1349 {
1350         int err;
1351
1352         pr_info("Performance Events: ");
1353
1354         switch (boot_cpu_data.x86_vendor) {
1355         case X86_VENDOR_INTEL:
1356                 err = intel_pmu_init();
1357                 break;
1358         case X86_VENDOR_AMD:
1359                 err = amd_pmu_init();
1360                 break;
1361         default:
1362                 return;
1363         }
1364         if (err != 0) {
1365                 pr_cont("no PMU driver, software events only.\n");
1366                 return;
1367         }
1368
1369         pmu_check_apic();
1370
1371         pr_cont("%s PMU driver.\n", x86_pmu.name);
1372
1373         if (x86_pmu.num_events > X86_PMC_MAX_GENERIC) {
1374                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1375                      x86_pmu.num_events, X86_PMC_MAX_GENERIC);
1376                 x86_pmu.num_events = X86_PMC_MAX_GENERIC;
1377         }
1378         perf_event_mask = (1 << x86_pmu.num_events) - 1;
1379         perf_max_events = x86_pmu.num_events;
1380
1381         if (x86_pmu.num_events_fixed > X86_PMC_MAX_FIXED) {
1382                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1383                      x86_pmu.num_events_fixed, X86_PMC_MAX_FIXED);
1384                 x86_pmu.num_events_fixed = X86_PMC_MAX_FIXED;
1385         }
1386
1387         perf_event_mask |=
1388                 ((1LL << x86_pmu.num_events_fixed)-1) << X86_PMC_IDX_FIXED;
1389         x86_pmu.intel_ctrl = perf_event_mask;
1390
1391         perf_events_lapic_init();
1392         register_die_notifier(&perf_event_nmi_notifier);
1393
1394         unconstrained = (struct event_constraint)
1395                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_events) - 1,
1396                                    0, x86_pmu.num_events);
1397
1398         pr_info("... version:                %d\n",     x86_pmu.version);
1399         pr_info("... bit width:              %d\n",     x86_pmu.event_bits);
1400         pr_info("... generic registers:      %d\n",     x86_pmu.num_events);
1401         pr_info("... value mask:             %016Lx\n", x86_pmu.event_mask);
1402         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1403         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_events_fixed);
1404         pr_info("... event mask:             %016Lx\n", perf_event_mask);
1405 }
1406
1407 static inline void x86_pmu_read(struct perf_event *event)
1408 {
1409         x86_perf_event_update(event, &event->hw, event->hw.idx);
1410 }
1411
1412 static const struct pmu pmu = {
1413         .enable         = x86_pmu_enable,
1414         .disable        = x86_pmu_disable,
1415         .start          = x86_pmu_start,
1416         .stop           = x86_pmu_stop,
1417         .read           = x86_pmu_read,
1418         .unthrottle     = x86_pmu_unthrottle,
1419 };
1420
1421 /*
1422  * validate a single event group
1423  *
1424  * validation include:
1425  *      - check events are compatible which each other
1426  *      - events do not compete for the same counter
1427  *      - number of events <= number of counters
1428  *
1429  * validation ensures the group can be loaded onto the
1430  * PMU if it was the only group available.
1431  */
1432 static int validate_group(struct perf_event *event)
1433 {
1434         struct perf_event *leader = event->group_leader;
1435         struct cpu_hw_events *fake_cpuc;
1436         int ret, n;
1437
1438         ret = -ENOMEM;
1439         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1440         if (!fake_cpuc)
1441                 goto out;
1442
1443         /*
1444          * the event is not yet connected with its
1445          * siblings therefore we must first collect
1446          * existing siblings, then add the new event
1447          * before we can simulate the scheduling
1448          */
1449         ret = -ENOSPC;
1450         n = collect_events(fake_cpuc, leader, true);
1451         if (n < 0)
1452                 goto out_free;
1453
1454         fake_cpuc->n_events = n;
1455         n = collect_events(fake_cpuc, event, false);
1456         if (n < 0)
1457                 goto out_free;
1458
1459         fake_cpuc->n_events = n;
1460
1461         ret = x86_schedule_events(fake_cpuc, n, NULL);
1462
1463 out_free:
1464         kfree(fake_cpuc);
1465 out:
1466         return ret;
1467 }
1468
1469 const struct pmu *hw_perf_event_init(struct perf_event *event)
1470 {
1471         const struct pmu *tmp;
1472         int err;
1473
1474         err = __hw_perf_event_init(event);
1475         if (!err) {
1476                 /*
1477                  * we temporarily connect event to its pmu
1478                  * such that validate_group() can classify
1479                  * it as an x86 event using is_x86_event()
1480                  */
1481                 tmp = event->pmu;
1482                 event->pmu = &pmu;
1483
1484                 if (event->group_leader != event)
1485                         err = validate_group(event);
1486
1487                 event->pmu = tmp;
1488         }
1489         if (err) {
1490                 if (event->destroy)
1491                         event->destroy(event);
1492                 return ERR_PTR(err);
1493         }
1494
1495         return &pmu;
1496 }
1497
1498 /*
1499  * callchain support
1500  */
1501
1502 static inline
1503 void callchain_store(struct perf_callchain_entry *entry, u64 ip)
1504 {
1505         if (entry->nr < PERF_MAX_STACK_DEPTH)
1506                 entry->ip[entry->nr++] = ip;
1507 }
1508
1509 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
1510 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry);
1511
1512
1513 static void
1514 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1515 {
1516         /* Ignore warnings */
1517 }
1518
1519 static void backtrace_warning(void *data, char *msg)
1520 {
1521         /* Ignore warnings */
1522 }
1523
1524 static int backtrace_stack(void *data, char *name)
1525 {
1526         return 0;
1527 }
1528
1529 static void backtrace_address(void *data, unsigned long addr, int reliable)
1530 {
1531         struct perf_callchain_entry *entry = data;
1532
1533         if (reliable)
1534                 callchain_store(entry, addr);
1535 }
1536
1537 static const struct stacktrace_ops backtrace_ops = {
1538         .warning                = backtrace_warning,
1539         .warning_symbol         = backtrace_warning_symbol,
1540         .stack                  = backtrace_stack,
1541         .address                = backtrace_address,
1542         .walk_stack             = print_context_stack_bp,
1543 };
1544
1545 #include "../dumpstack.h"
1546
1547 static void
1548 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1549 {
1550         callchain_store(entry, PERF_CONTEXT_KERNEL);
1551         callchain_store(entry, regs->ip);
1552
1553         dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
1554 }
1555
1556 /*
1557  * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
1558  */
1559 static unsigned long
1560 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
1561 {
1562         unsigned long offset, addr = (unsigned long)from;
1563         int type = in_nmi() ? KM_NMI : KM_IRQ0;
1564         unsigned long size, len = 0;
1565         struct page *page;
1566         void *map;
1567         int ret;
1568
1569         do {
1570                 ret = __get_user_pages_fast(addr, 1, 0, &page);
1571                 if (!ret)
1572                         break;
1573
1574                 offset = addr & (PAGE_SIZE - 1);
1575                 size = min(PAGE_SIZE - offset, n - len);
1576
1577                 map = kmap_atomic(page, type);
1578                 memcpy(to, map+offset, size);
1579                 kunmap_atomic(map, type);
1580                 put_page(page);
1581
1582                 len  += size;
1583                 to   += size;
1584                 addr += size;
1585
1586         } while (len < n);
1587
1588         return len;
1589 }
1590
1591 static int copy_stack_frame(const void __user *fp, struct stack_frame *frame)
1592 {
1593         unsigned long bytes;
1594
1595         bytes = copy_from_user_nmi(frame, fp, sizeof(*frame));
1596
1597         return bytes == sizeof(*frame);
1598 }
1599
1600 static void
1601 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1602 {
1603         struct stack_frame frame;
1604         const void __user *fp;
1605
1606         if (!user_mode(regs))
1607                 regs = task_pt_regs(current);
1608
1609         fp = (void __user *)regs->bp;
1610
1611         callchain_store(entry, PERF_CONTEXT_USER);
1612         callchain_store(entry, regs->ip);
1613
1614         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1615                 frame.next_frame             = NULL;
1616                 frame.return_address = 0;
1617
1618                 if (!copy_stack_frame(fp, &frame))
1619                         break;
1620
1621                 if ((unsigned long)fp < regs->sp)
1622                         break;
1623
1624                 callchain_store(entry, frame.return_address);
1625                 fp = frame.next_frame;
1626         }
1627 }
1628
1629 static void
1630 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1631 {
1632         int is_user;
1633
1634         if (!regs)
1635                 return;
1636
1637         is_user = user_mode(regs);
1638
1639         if (is_user && current->state != TASK_RUNNING)
1640                 return;
1641
1642         if (!is_user)
1643                 perf_callchain_kernel(regs, entry);
1644
1645         if (current->mm)
1646                 perf_callchain_user(regs, entry);
1647 }
1648
1649 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1650 {
1651         struct perf_callchain_entry *entry;
1652
1653         if (in_nmi())
1654                 entry = &__get_cpu_var(pmc_nmi_entry);
1655         else
1656                 entry = &__get_cpu_var(pmc_irq_entry);
1657
1658         entry->nr = 0;
1659
1660         perf_do_callchain(regs, entry);
1661
1662         return entry;
1663 }
1664
1665 void hw_perf_event_setup_online(int cpu)
1666 {
1667         init_debug_store_on_cpu(cpu);
1668
1669         switch (boot_cpu_data.x86_vendor) {
1670         case X86_VENDOR_AMD:
1671                 amd_pmu_cpu_online(cpu);
1672                 break;
1673         default:
1674                 return;
1675         }
1676 }
1677
1678 void hw_perf_event_setup_offline(int cpu)
1679 {
1680         init_debug_store_on_cpu(cpu);
1681
1682         switch (boot_cpu_data.x86_vendor) {
1683         case X86_VENDOR_AMD:
1684                 amd_pmu_cpu_offline(cpu);
1685                 break;
1686         default:
1687                 return;
1688         }
1689 }