arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/highmem.h>
  26 #include <linux/cpu.h>
  27 #include <linux/bitops.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/compat.h>
  33
  34 #if 0
  35 #undef wrmsrl
  36 #define wrmsrl(msr, val)                                        \
  37 do {                                                            \
  38         trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
  39                         (unsigned long)(val));                  \
  40         native_write_msr((msr), (u32)((u64)(val)),              \
  41                         (u32)((u64)(val) >> 32));               \
  42 } while (0)
  43 #endif
  44
  45 /*
  46  * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
  47  */
  48 static unsigned long
  49 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
  50 {
  51         unsigned long offset, addr = (unsigned long)from;
  52         int type = in_nmi() ? KM_NMI : KM_IRQ0;
  53         unsigned long size, len = 0;
  54         struct page *page;
  55         void *map;
  56         int ret;
  57
  58         do {
  59                 ret = __get_user_pages_fast(addr, 1, 0, &page);
  60                 if (!ret)
  61                         break;
  62
  63                 offset = addr & (PAGE_SIZE - 1);
  64                 size = min(PAGE_SIZE - offset, n - len);
  65
  66                 map = kmap_atomic(page, type);
  67                 memcpy(to, map+offset, size);
  68                 kunmap_atomic(map, type);
  69                 put_page(page);
  70
  71                 len  += size;
  72                 to   += size;
  73                 addr += size;
  74
  75         } while (len < n);
  76
  77         return len;
  78 }
  79
  80 struct event_constraint {
  81         union {
  82                 unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  83                 u64             idxmsk64;
  84         };
  85         u64     code;
  86         u64     cmask;
  87         int     weight;
  88 };
  89
  90 struct amd_nb {
  91         int nb_id;  /* NorthBridge id */
  92         int refcnt; /* reference count */
  93         struct perf_event *owners[X86_PMC_IDX_MAX];
  94         struct event_constraint event_constraints[X86_PMC_IDX_MAX];
  95 };
  96
  97 #define MAX_LBR_ENTRIES         16
  98
  99 struct cpu_hw_events {
 100         /*
 101          * Generic x86 PMC bits
 102          */
 103         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
 104         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 105         int                     enabled;
 106
 107         int                     n_events;
 108         int                     n_added;
 109         int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
 110         u64                     tags[X86_PMC_IDX_MAX];
 111         struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
 112
 113         /*
 114          * Intel DebugStore bits
 115          */
 116         struct debug_store      *ds;
 117         u64                     pebs_enabled;
 118
 119         /*
 120          * Intel LBR bits
 121          */
 122         int                             lbr_users;
 123         void                            *lbr_context;
 124         struct perf_branch_stack        lbr_stack;
 125         struct perf_branch_entry        lbr_entries[MAX_LBR_ENTRIES];
 126
 127         /*
 128          * AMD specific bits
 129          */
 130         struct amd_nb           *amd_nb;
 131 };
 132
 133 #define __EVENT_CONSTRAINT(c, n, m, w) {\
 134         { .idxmsk64 = (n) },            \
 135         .code = (c),                    \
 136         .cmask = (m),                   \
 137         .weight = (w),                  \
 138 }
 139
 140 #define EVENT_CONSTRAINT(c, n, m)       \
 141         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
 142
 143 /*
 144  * Constraint on the Event code.
 145  */
 146 #define INTEL_EVENT_CONSTRAINT(c, n)    \
 147         EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
 148
 149 /*
 150  * Constraint on the Event code + UMask + fixed-mask
 151  *
 152  * filter mask to validate fixed counter events.
 153  * the following filters disqualify for fixed counters:
 154  *  - inv
 155  *  - edge
 156  *  - cnt-mask
 157  *  The other filters are supported by fixed counters.
 158  *  The any-thread option is supported starting with v3.
 159  */
 160 #define FIXED_EVENT_CONSTRAINT(c, n)    \
 161         EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
 162
 163 /*
 164  * Constraint on the Event code + UMask
 165  */
 166 #define PEBS_EVENT_CONSTRAINT(c, n)     \
 167         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
 168
 169 #define EVENT_CONSTRAINT_END            \
 170         EVENT_CONSTRAINT(0, 0, 0)
 171
 172 #define for_each_event_constraint(e, c) \
 173         for ((e) = (c); (e)->cmask; (e)++)
 174
 175 union perf_capabilities {
 176         struct {
 177                 u64     lbr_format    : 6;
 178                 u64     pebs_trap     : 1;
 179                 u64     pebs_arch_reg : 1;
 180                 u64     pebs_format   : 4;
 181                 u64     smm_freeze    : 1;
 182         };
 183         u64     capabilities;
 184 };
 185
 186 /*
 187  * struct x86_pmu - generic x86 pmu
 188  */
 189 struct x86_pmu {
 190         /*
 191          * Generic x86 PMC bits
 192          */
 193         const char      *name;
 194         int             version;
 195         int             (*handle_irq)(struct pt_regs *);
 196         void            (*disable_all)(void);
 197         void            (*enable_all)(int added);
 198         void            (*enable)(struct perf_event *);
 199         void            (*disable)(struct perf_event *);
 200         int             (*hw_config)(struct perf_event *event);
 201         int             (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
 202         unsigned        eventsel;
 203         unsigned        perfctr;
 204         u64             (*event_map)(int);
 205         int             max_events;
 206         int             num_counters;
 207         int             num_counters_fixed;
 208         int             cntval_bits;
 209         u64             cntval_mask;
 210         int             apic;
 211         u64             max_period;
 212         struct event_constraint *
 213                         (*get_event_constraints)(struct cpu_hw_events *cpuc,
 214                                                  struct perf_event *event);
 215
 216         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
 217                                                  struct perf_event *event);
 218         struct event_constraint *event_constraints;
 219         void            (*quirks)(void);
 220
 221         int             (*cpu_prepare)(int cpu);
 222         void            (*cpu_starting)(int cpu);
 223         void            (*cpu_dying)(int cpu);
 224         void            (*cpu_dead)(int cpu);
 225
 226         /*
 227          * Intel Arch Perfmon v2+
 228          */
 229         u64                     intel_ctrl;
 230         union perf_capabilities intel_cap;
 231
 232         /*
 233          * Intel DebugStore bits
 234          */
 235         int             bts, pebs;
 236         int             pebs_record_size;
 237         void            (*drain_pebs)(struct pt_regs *regs);
 238         struct event_constraint *pebs_constraints;
 239
 240         /*
 241          * Intel LBR
 242          */
 243         unsigned long   lbr_tos, lbr_from, lbr_to; /* MSR base regs       */
 244         int             lbr_nr;                    /* hardware stack size */
 245 };
 246
 247 static struct x86_pmu x86_pmu __read_mostly;
 248
 249 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
 250         .enabled = 1,
 251 };
 252
 253 static int x86_perf_event_set_period(struct perf_event *event);
 254
 255 /*
 256  * Generalized hw caching related hw_event table, filled
 257  * in on a per model basis. A value of 0 means
 258  * 'not supported', -1 means 'hw_event makes no sense on
 259  * this CPU', any other value means the raw hw_event
 260  * ID.
 261  */
 262
 263 #define C(x) PERF_COUNT_HW_CACHE_##x
 264
 265 static u64 __read_mostly hw_cache_event_ids
 266                                 [PERF_COUNT_HW_CACHE_MAX]
 267                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 268                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 269
 270 /*
 271  * Propagate event elapsed time into the generic event.
 272  * Can only be executed on the CPU where the event is active.
 273  * Returns the delta events processed.
 274  */
 275 static u64
 276 x86_perf_event_update(struct perf_event *event)
 277 {
 278         struct hw_perf_event *hwc = &event->hw;
 279         int shift = 64 - x86_pmu.cntval_bits;
 280         u64 prev_raw_count, new_raw_count;
 281         int idx = hwc->idx;
 282         s64 delta;
 283
 284         if (idx == X86_PMC_IDX_FIXED_BTS)
 285                 return 0;
 286
 287         /*
 288          * Careful: an NMI might modify the previous event value.
 289          *
 290          * Our tactic to handle this is to first atomically read and
 291          * exchange a new raw count - then add that new-prev delta
 292          * count to the generic event atomically:
 293          */
 294 again:
 295         prev_raw_count = atomic64_read(&hwc->prev_count);
 296         rdmsrl(hwc->event_base + idx, new_raw_count);
 297
 298         if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
 299                                         new_raw_count) != prev_raw_count)
 300                 goto again;
 301
 302         /*
 303          * Now we have the new raw value and have updated the prev
 304          * timestamp already. We can now calculate the elapsed delta
 305          * (event-)time and add that to the generic event.
 306          *
 307          * Careful, not all hw sign-extends above the physical width
 308          * of the count.
 309          */
 310         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 311         delta >>= shift;
 312
 313         atomic64_add(delta, &event->count);
 314         atomic64_sub(delta, &hwc->period_left);
 315
 316         return new_raw_count;
 317 }
 318
 319 static atomic_t active_events;
 320 static DEFINE_MUTEX(pmc_reserve_mutex);
 321
 322 #ifdef CONFIG_X86_LOCAL_APIC
 323
 324 static bool reserve_pmc_hardware(void)
 325 {
 326         int i;
 327
 328         if (nmi_watchdog == NMI_LOCAL_APIC)
 329                 disable_lapic_nmi_watchdog();
 330
 331         for (i = 0; i < x86_pmu.num_counters; i++) {
 332                 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
 333                         goto perfctr_fail;
 334         }
 335
 336         for (i = 0; i < x86_pmu.num_counters; i++) {
 337                 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
 338                         goto eventsel_fail;
 339         }
 340
 341         return true;
 342
 343 eventsel_fail:
 344         for (i--; i >= 0; i--)
 345                 release_evntsel_nmi(x86_pmu.eventsel + i);
 346
 347         i = x86_pmu.num_counters;
 348
 349 perfctr_fail:
 350         for (i--; i >= 0; i--)
 351                 release_perfctr_nmi(x86_pmu.perfctr + i);
 352
 353         if (nmi_watchdog == NMI_LOCAL_APIC)
 354                 enable_lapic_nmi_watchdog();
 355
 356         return false;
 357 }
 358
 359 static void release_pmc_hardware(void)
 360 {
 361         int i;
 362
 363         for (i = 0; i < x86_pmu.num_counters; i++) {
 364                 release_perfctr_nmi(x86_pmu.perfctr + i);
 365                 release_evntsel_nmi(x86_pmu.eventsel + i);
 366         }
 367
 368         if (nmi_watchdog == NMI_LOCAL_APIC)
 369                 enable_lapic_nmi_watchdog();
 370 }
 371
 372 #else
 373
 374 static bool reserve_pmc_hardware(void) { return true; }
 375 static void release_pmc_hardware(void) {}
 376
 377 #endif
 378
 379 static int reserve_ds_buffers(void);
 380 static void release_ds_buffers(void);
 381
 382 static void hw_perf_event_destroy(struct perf_event *event)
 383 {
 384         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 385                 release_pmc_hardware();
 386                 release_ds_buffers();
 387                 mutex_unlock(&pmc_reserve_mutex);
 388         }
 389 }
 390
 391 static inline int x86_pmu_initialized(void)
 392 {
 393         return x86_pmu.handle_irq != NULL;
 394 }
 395
 396 static inline int
 397 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
 398 {
 399         unsigned int cache_type, cache_op, cache_result;
 400         u64 config, val;
 401
 402         config = attr->config;
 403
 404         cache_type = (config >>  0) & 0xff;
 405         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 406                 return -EINVAL;
 407
 408         cache_op = (config >>  8) & 0xff;
 409         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 410                 return -EINVAL;
 411
 412         cache_result = (config >> 16) & 0xff;
 413         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 414                 return -EINVAL;
 415
 416         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 417
 418         if (val == 0)
 419                 return -ENOENT;
 420
 421         if (val == -1)
 422                 return -EINVAL;
 423
 424         hwc->config |= val;
 425
 426         return 0;
 427 }
 428
 429 static int x86_pmu_hw_config(struct perf_event *event)
 430 {
 431         /*
 432          * Generate PMC IRQs:
 433          * (keep 'enabled' bit clear for now)
 434          */
 435         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 436
 437         /*
 438          * Count user and OS events unless requested not to
 439          */
 440         if (!event->attr.exclude_user)
 441                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 442         if (!event->attr.exclude_kernel)
 443                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 444
 445         if (event->attr.type == PERF_TYPE_RAW)
 446                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 447
 448         return 0;
 449 }
 450
 451 /*
 452  * Setup the hardware configuration for a given attr_type
 453  */
 454 static int __hw_perf_event_init(struct perf_event *event)
 455 {
 456         struct perf_event_attr *attr = &event->attr;
 457         struct hw_perf_event *hwc = &event->hw;
 458         u64 config;
 459         int err;
 460
 461         if (!x86_pmu_initialized())
 462                 return -ENODEV;
 463
 464         err = 0;
 465         if (!atomic_inc_not_zero(&active_events)) {
 466                 mutex_lock(&pmc_reserve_mutex);
 467                 if (atomic_read(&active_events) == 0) {
 468                         if (!reserve_pmc_hardware())
 469                                 err = -EBUSY;
 470                         else {
 471                                 err = reserve_ds_buffers();
 472                                 if (err)
 473                                         release_pmc_hardware();
 474                         }
 475                 }
 476                 if (!err)
 477                         atomic_inc(&active_events);
 478                 mutex_unlock(&pmc_reserve_mutex);
 479         }
 480         if (err)
 481                 return err;
 482
 483         event->destroy = hw_perf_event_destroy;
 484
 485         hwc->idx = -1;
 486         hwc->last_cpu = -1;
 487         hwc->last_tag = ~0ULL;
 488
 489         /* Processor specifics */
 490         err = x86_pmu.hw_config(event);
 491         if (err)
 492                 return err;
 493
 494         if (!hwc->sample_period) {
 495                 hwc->sample_period = x86_pmu.max_period;
 496                 hwc->last_period = hwc->sample_period;
 497                 atomic64_set(&hwc->period_left, hwc->sample_period);
 498         } else {
 499                 /*
 500                  * If we have a PMU initialized but no APIC
 501                  * interrupts, we cannot sample hardware
 502                  * events (user-space has to fall back and
 503                  * sample via a hrtimer based software event):
 504                  */
 505                 if (!x86_pmu.apic)
 506                         return -EOPNOTSUPP;
 507         }
 508
 509         if (attr->type == PERF_TYPE_RAW)
 510                 return 0;
 511
 512         if (attr->type == PERF_TYPE_HW_CACHE)
 513                 return set_ext_hw_attr(hwc, attr);
 514
 515         if (attr->config >= x86_pmu.max_events)
 516                 return -EINVAL;
 517
 518         /*
 519          * The generic map:
 520          */
 521         config = x86_pmu.event_map(attr->config);
 522
 523         if (config == 0)
 524                 return -ENOENT;
 525
 526         if (config == -1LL)
 527                 return -EINVAL;
 528
 529         /*
 530          * Branch tracing:
 531          */
 532         if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
 533             (hwc->sample_period == 1)) {
 534                 /* BTS is not supported by this architecture. */
 535                 if (!x86_pmu.bts)
 536                         return -EOPNOTSUPP;
 537
 538                 /* BTS is currently only allowed for user-mode. */
 539                 if (!attr->exclude_kernel)
 540                         return -EOPNOTSUPP;
 541         }
 542
 543         hwc->config |= config;
 544
 545         return 0;
 546 }
 547
 548 static void x86_pmu_disable_all(void)
 549 {
 550         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 551         int idx;
 552
 553         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 554                 u64 val;
 555
 556                 if (!test_bit(idx, cpuc->active_mask))
 557                         continue;
 558                 rdmsrl(x86_pmu.eventsel + idx, val);
 559                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 560                         continue;
 561                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 562                 wrmsrl(x86_pmu.eventsel + idx, val);
 563         }
 564 }
 565
 566 void hw_perf_disable(void)
 567 {
 568         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 569
 570         if (!x86_pmu_initialized())
 571                 return;
 572
 573         if (!cpuc->enabled)
 574                 return;
 575
 576         cpuc->n_added = 0;
 577         cpuc->enabled = 0;
 578         barrier();
 579
 580         x86_pmu.disable_all();
 581 }
 582
 583 static void x86_pmu_enable_all(int added)
 584 {
 585         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 586         int idx;
 587
 588         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 589                 struct perf_event *event = cpuc->events[idx];
 590                 u64 val;
 591
 592                 if (!test_bit(idx, cpuc->active_mask))
 593                         continue;
 594
 595                 val = event->hw.config;
 596                 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
 597                 wrmsrl(x86_pmu.eventsel + idx, val);
 598         }
 599 }
 600
 601 static const struct pmu pmu;
 602
 603 static inline int is_x86_event(struct perf_event *event)
 604 {
 605         return event->pmu == &pmu;
 606 }
 607
 608 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 609 {
 610         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
 611         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 612         int i, j, w, wmax, num = 0;
 613         struct hw_perf_event *hwc;
 614
 615         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 616
 617         for (i = 0; i < n; i++) {
 618                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 619                 constraints[i] = c;
 620         }
 621
 622         /*
 623          * fastpath, try to reuse previous register
 624          */
 625         for (i = 0; i < n; i++) {
 626                 hwc = &cpuc->event_list[i]->hw;
 627                 c = constraints[i];
 628
 629                 /* never assigned */
 630                 if (hwc->idx == -1)
 631                         break;
 632
 633                 /* constraint still honored */
 634                 if (!test_bit(hwc->idx, c->idxmsk))
 635                         break;
 636
 637                 /* not already used */
 638                 if (test_bit(hwc->idx, used_mask))
 639                         break;
 640
 641                 __set_bit(hwc->idx, used_mask);
 642                 if (assign)
 643                         assign[i] = hwc->idx;
 644         }
 645         if (i == n)
 646                 goto done;
 647
 648         /*
 649          * begin slow path
 650          */
 651
 652         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 653
 654         /*
 655          * weight = number of possible counters
 656          *
 657          * 1    = most constrained, only works on one counter
 658          * wmax = least constrained, works on any counter
 659          *
 660          * assign events to counters starting with most
 661          * constrained events.
 662          */
 663         wmax = x86_pmu.num_counters;
 664
 665         /*
 666          * when fixed event counters are present,
 667          * wmax is incremented by 1 to account
 668          * for one more choice
 669          */
 670         if (x86_pmu.num_counters_fixed)
 671                 wmax++;
 672
 673         for (w = 1, num = n; num && w <= wmax; w++) {
 674                 /* for each event */
 675                 for (i = 0; num && i < n; i++) {
 676                         c = constraints[i];
 677                         hwc = &cpuc->event_list[i]->hw;
 678
 679                         if (c->weight != w)
 680                                 continue;
 681
 682                         for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
 683                                 if (!test_bit(j, used_mask))
 684                                         break;
 685                         }
 686
 687                         if (j == X86_PMC_IDX_MAX)
 688                                 break;
 689
 690                         __set_bit(j, used_mask);
 691
 692                         if (assign)
 693                                 assign[i] = j;
 694                         num--;
 695                 }
 696         }
 697 done:
 698         /*
 699          * scheduling failed or is just a simulation,
 700          * free resources if necessary
 701          */
 702         if (!assign || num) {
 703                 for (i = 0; i < n; i++) {
 704                         if (x86_pmu.put_event_constraints)
 705                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
 706                 }
 707         }
 708         return num ? -ENOSPC : 0;
 709 }
 710
 711 /*
 712  * dogrp: true if must collect siblings events (group)
 713  * returns total number of events and error code
 714  */
 715 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 716 {
 717         struct perf_event *event;
 718         int n, max_count;
 719
 720         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 721
 722         /* current number of events already accepted */
 723         n = cpuc->n_events;
 724
 725         if (is_x86_event(leader)) {
 726                 if (n >= max_count)
 727                         return -ENOSPC;
 728                 cpuc->event_list[n] = leader;
 729                 n++;
 730         }
 731         if (!dogrp)
 732                 return n;
 733
 734         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 735                 if (!is_x86_event(event) ||
 736                     event->state <= PERF_EVENT_STATE_OFF)
 737                         continue;
 738
 739                 if (n >= max_count)
 740                         return -ENOSPC;
 741
 742                 cpuc->event_list[n] = event;
 743                 n++;
 744         }
 745         return n;
 746 }
 747
 748 static inline void x86_assign_hw_event(struct perf_event *event,
 749                                 struct cpu_hw_events *cpuc, int i)
 750 {
 751         struct hw_perf_event *hwc = &event->hw;
 752
 753         hwc->idx = cpuc->assign[i];
 754         hwc->last_cpu = smp_processor_id();
 755         hwc->last_tag = ++cpuc->tags[i];
 756
 757         if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
 758                 hwc->config_base = 0;
 759                 hwc->event_base = 0;
 760         } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
 761                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 762                 /*
 763                  * We set it so that event_base + idx in wrmsr/rdmsr maps to
 764                  * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
 765                  */
 766                 hwc->event_base =
 767                         MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
 768         } else {
 769                 hwc->config_base = x86_pmu.eventsel;
 770                 hwc->event_base  = x86_pmu.perfctr;
 771         }
 772 }
 773
 774 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 775                                         struct cpu_hw_events *cpuc,
 776                                         int i)
 777 {
 778         return hwc->idx == cpuc->assign[i] &&
 779                 hwc->last_cpu == smp_processor_id() &&
 780                 hwc->last_tag == cpuc->tags[i];
 781 }
 782
 783 static int x86_pmu_start(struct perf_event *event);
 784 static void x86_pmu_stop(struct perf_event *event);
 785
 786 void hw_perf_enable(void)
 787 {
 788         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 789         struct perf_event *event;
 790         struct hw_perf_event *hwc;
 791         int i, added = cpuc->n_added;
 792
 793         if (!x86_pmu_initialized())
 794                 return;
 795
 796         if (cpuc->enabled)
 797                 return;
 798
 799         if (cpuc->n_added) {
 800                 int n_running = cpuc->n_events - cpuc->n_added;
 801                 /*
 802                  * apply assignment obtained either from
 803                  * hw_perf_group_sched_in() or x86_pmu_enable()
 804                  *
 805                  * step1: save events moving to new counters
 806                  * step2: reprogram moved events into new counters
 807                  */
 808                 for (i = 0; i < n_running; i++) {
 809                         event = cpuc->event_list[i];
 810                         hwc = &event->hw;
 811
 812                         /*
 813                          * we can avoid reprogramming counter if:
 814                          * - assigned same counter as last time
 815                          * - running on same CPU as last time
 816                          * - no other event has used the counter since
 817                          */
 818                         if (hwc->idx == -1 ||
 819                             match_prev_assignment(hwc, cpuc, i))
 820                                 continue;
 821
 822                         x86_pmu_stop(event);
 823                 }
 824
 825                 for (i = 0; i < cpuc->n_events; i++) {
 826                         event = cpuc->event_list[i];
 827                         hwc = &event->hw;
 828
 829                         if (!match_prev_assignment(hwc, cpuc, i))
 830                                 x86_assign_hw_event(event, cpuc, i);
 831                         else if (i < n_running)
 832                                 continue;
 833
 834                         x86_pmu_start(event);
 835                 }
 836                 cpuc->n_added = 0;
 837                 perf_events_lapic_init();
 838         }
 839
 840         cpuc->enabled = 1;
 841         barrier();
 842
 843         x86_pmu.enable_all(added);
 844 }
 845
 846 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc)
 847 {
 848         wrmsrl(hwc->config_base + hwc->idx,
 849                               hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE);
 850 }
 851
 852 static inline void x86_pmu_disable_event(struct perf_event *event)
 853 {
 854         struct hw_perf_event *hwc = &event->hw;
 855
 856         wrmsrl(hwc->config_base + hwc->idx, hwc->config);
 857 }
 858
 859 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
 860
 861 /*
 862  * Set the next IRQ period, based on the hwc->period_left value.
 863  * To be called with the event disabled in hw:
 864  */
 865 static int
 866 x86_perf_event_set_period(struct perf_event *event)
 867 {
 868         struct hw_perf_event *hwc = &event->hw;
 869         s64 left = atomic64_read(&hwc->period_left);
 870         s64 period = hwc->sample_period;
 871         int ret = 0, idx = hwc->idx;
 872
 873         if (idx == X86_PMC_IDX_FIXED_BTS)
 874                 return 0;
 875
 876         /*
 877          * If we are way outside a reasonable range then just skip forward:
 878          */
 879         if (unlikely(left <= -period)) {
 880                 left = period;
 881                 atomic64_set(&hwc->period_left, left);
 882                 hwc->last_period = period;
 883                 ret = 1;
 884         }
 885
 886         if (unlikely(left <= 0)) {
 887                 left += period;
 888                 atomic64_set(&hwc->period_left, left);
 889                 hwc->last_period = period;
 890                 ret = 1;
 891         }
 892         /*
 893          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
 894          */
 895         if (unlikely(left < 2))
 896                 left = 2;
 897
 898         if (left > x86_pmu.max_period)
 899                 left = x86_pmu.max_period;
 900
 901         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
 902
 903         /*
 904          * The hw event starts counting from this event offset,
 905          * mark it to be able to extra future deltas:
 906          */
 907         atomic64_set(&hwc->prev_count, (u64)-left);
 908
 909         wrmsrl(hwc->event_base + idx,
 910                         (u64)(-left) & x86_pmu.cntval_mask);
 911
 912         perf_event_update_userpage(event);
 913
 914         return ret;
 915 }
 916
 917 static void x86_pmu_enable_event(struct perf_event *event)
 918 {
 919         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 920         if (cpuc->enabled)
 921                 __x86_pmu_enable_event(&event->hw);
 922 }
 923
 924 /*
 925  * activate a single event
 926  *
 927  * The event is added to the group of enabled events
 928  * but only if it can be scehduled with existing events.
 929  *
 930  * Called with PMU disabled. If successful and return value 1,
 931  * then guaranteed to call perf_enable() and hw_perf_enable()
 932  */
 933 static int x86_pmu_enable(struct perf_event *event)
 934 {
 935         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 936         struct hw_perf_event *hwc;
 937         int assign[X86_PMC_IDX_MAX];
 938         int n, n0, ret;
 939
 940         hwc = &event->hw;
 941
 942         n0 = cpuc->n_events;
 943         n = collect_events(cpuc, event, false);
 944         if (n < 0)
 945                 return n;
 946
 947         ret = x86_pmu.schedule_events(cpuc, n, assign);
 948         if (ret)
 949                 return ret;
 950         /*
 951          * copy new assignment, now we know it is possible
 952          * will be used by hw_perf_enable()
 953          */
 954         memcpy(cpuc->assign, assign, n*sizeof(int));
 955
 956         cpuc->n_events = n;
 957         cpuc->n_added += n - n0;
 958
 959         return 0;
 960 }
 961
 962 static int x86_pmu_start(struct perf_event *event)
 963 {
 964         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 965         int idx = event->hw.idx;
 966
 967         if (idx == -1)
 968                 return -EAGAIN;
 969
 970         x86_perf_event_set_period(event);
 971         cpuc->events[idx] = event;
 972         __set_bit(idx, cpuc->active_mask);
 973         x86_pmu.enable(event);
 974         perf_event_update_userpage(event);
 975
 976         return 0;
 977 }
 978
 979 static void x86_pmu_unthrottle(struct perf_event *event)
 980 {
 981         int ret = x86_pmu_start(event);
 982         WARN_ON_ONCE(ret);
 983 }
 984
 985 void perf_event_print_debug(void)
 986 {
 987         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
 988         u64 pebs;
 989         struct cpu_hw_events *cpuc;
 990         unsigned long flags;
 991         int cpu, idx;
 992
 993         if (!x86_pmu.num_counters)
 994                 return;
 995
 996         local_irq_save(flags);
 997
 998         cpu = smp_processor_id();
 999         cpuc = &per_cpu(cpu_hw_events, cpu);
1000
1001         if (x86_pmu.version >= 2) {
1002                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1003                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1004                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1005                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1006                 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1007
1008                 pr_info("\n");
1009                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1010                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1011                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1012                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1013                 pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1014         }
1015         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1016
1017         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1018                 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1019                 rdmsrl(x86_pmu.perfctr  + idx, pmc_count);
1020
1021                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1022
1023                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1024                         cpu, idx, pmc_ctrl);
1025                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1026                         cpu, idx, pmc_count);
1027                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1028                         cpu, idx, prev_left);
1029         }
1030         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1031                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1032
1033                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1034                         cpu, idx, pmc_count);
1035         }
1036         local_irq_restore(flags);
1037 }
1038
1039 static void x86_pmu_stop(struct perf_event *event)
1040 {
1041         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1042         struct hw_perf_event *hwc = &event->hw;
1043         int idx = hwc->idx;
1044
1045         if (!__test_and_clear_bit(idx, cpuc->active_mask))
1046                 return;
1047
1048         x86_pmu.disable(event);
1049
1050         /*
1051          * Drain the remaining delta count out of a event
1052          * that we are disabling:
1053          */
1054         x86_perf_event_update(event);
1055
1056         cpuc->events[idx] = NULL;
1057 }
1058
1059 static void x86_pmu_disable(struct perf_event *event)
1060 {
1061         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1062         int i;
1063
1064         x86_pmu_stop(event);
1065
1066         for (i = 0; i < cpuc->n_events; i++) {
1067                 if (event == cpuc->event_list[i]) {
1068
1069                         if (x86_pmu.put_event_constraints)
1070                                 x86_pmu.put_event_constraints(cpuc, event);
1071
1072                         while (++i < cpuc->n_events)
1073                                 cpuc->event_list[i-1] = cpuc->event_list[i];
1074
1075                         --cpuc->n_events;
1076                         break;
1077                 }
1078         }
1079         perf_event_update_userpage(event);
1080 }
1081
1082 static int x86_pmu_handle_irq(struct pt_regs *regs)
1083 {
1084         struct perf_sample_data data;
1085         struct cpu_hw_events *cpuc;
1086         struct perf_event *event;
1087         struct hw_perf_event *hwc;
1088         int idx, handled = 0;
1089         u64 val;
1090
1091         perf_sample_data_init(&data, 0);
1092
1093         cpuc = &__get_cpu_var(cpu_hw_events);
1094
1095         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1096                 if (!test_bit(idx, cpuc->active_mask))
1097                         continue;
1098
1099                 event = cpuc->events[idx];
1100                 hwc = &event->hw;
1101
1102                 val = x86_perf_event_update(event);
1103                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1104                         continue;
1105
1106                 /*
1107                  * event overflow
1108                  */
1109                 handled         = 1;
1110                 data.period     = event->hw.last_period;
1111
1112                 if (!x86_perf_event_set_period(event))
1113                         continue;
1114
1115                 if (perf_event_overflow(event, 1, &data, regs))
1116                         x86_pmu_stop(event);
1117         }
1118
1119         if (handled)
1120                 inc_irq_stat(apic_perf_irqs);
1121
1122         return handled;
1123 }
1124
1125 void smp_perf_pending_interrupt(struct pt_regs *regs)
1126 {
1127         irq_enter();
1128         ack_APIC_irq();
1129         inc_irq_stat(apic_pending_irqs);
1130         perf_event_do_pending();
1131         irq_exit();
1132 }
1133
1134 void set_perf_event_pending(void)
1135 {
1136 #ifdef CONFIG_X86_LOCAL_APIC
1137         if (!x86_pmu.apic || !x86_pmu_initialized())
1138                 return;
1139
1140         apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1141 #endif
1142 }
1143
1144 void perf_events_lapic_init(void)
1145 {
1146         if (!x86_pmu.apic || !x86_pmu_initialized())
1147                 return;
1148
1149         /*
1150          * Always use NMI for PMU
1151          */
1152         apic_write(APIC_LVTPC, APIC_DM_NMI);
1153 }
1154
1155 static int __kprobes
1156 perf_event_nmi_handler(struct notifier_block *self,
1157                          unsigned long cmd, void *__args)
1158 {
1159         struct die_args *args = __args;
1160         struct pt_regs *regs;
1161
1162         if (!atomic_read(&active_events))
1163                 return NOTIFY_DONE;
1164
1165         switch (cmd) {
1166         case DIE_NMI:
1167         case DIE_NMI_IPI:
1168                 break;
1169
1170         default:
1171                 return NOTIFY_DONE;
1172         }
1173
1174         regs = args->regs;
1175
1176         apic_write(APIC_LVTPC, APIC_DM_NMI);
1177         /*
1178          * Can't rely on the handled return value to say it was our NMI, two
1179          * events could trigger 'simultaneously' raising two back-to-back NMIs.
1180          *
1181          * If the first NMI handles both, the latter will be empty and daze
1182          * the CPU.
1183          */
1184         x86_pmu.handle_irq(regs);
1185
1186         return NOTIFY_STOP;
1187 }
1188
1189 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1190         .notifier_call          = perf_event_nmi_handler,
1191         .next                   = NULL,
1192         .priority               = 1
1193 };
1194
1195 static struct event_constraint unconstrained;
1196 static struct event_constraint emptyconstraint;
1197
1198 static struct event_constraint *
1199 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1200 {
1201         struct event_constraint *c;
1202
1203         if (x86_pmu.event_constraints) {
1204                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1205                         if ((event->hw.config & c->cmask) == c->code)
1206                                 return c;
1207                 }
1208         }
1209
1210         return &unconstrained;
1211 }
1212
1213 static int x86_event_sched_in(struct perf_event *event,
1214                           struct perf_cpu_context *cpuctx)
1215 {
1216         int ret = 0;
1217
1218         event->state = PERF_EVENT_STATE_ACTIVE;
1219         event->oncpu = smp_processor_id();
1220         event->tstamp_running += event->ctx->time - event->tstamp_stopped;
1221
1222         if (!is_x86_event(event))
1223                 ret = event->pmu->enable(event);
1224
1225         if (!ret && !is_software_event(event))
1226                 cpuctx->active_oncpu++;
1227
1228         if (!ret && event->attr.exclusive)
1229                 cpuctx->exclusive = 1;
1230
1231         return ret;
1232 }
1233
1234 static void x86_event_sched_out(struct perf_event *event,
1235                             struct perf_cpu_context *cpuctx)
1236 {
1237         event->state = PERF_EVENT_STATE_INACTIVE;
1238         event->oncpu = -1;
1239
1240         if (!is_x86_event(event))
1241                 event->pmu->disable(event);
1242
1243         event->tstamp_running -= event->ctx->time - event->tstamp_stopped;
1244
1245         if (!is_software_event(event))
1246                 cpuctx->active_oncpu--;
1247
1248         if (event->attr.exclusive || !cpuctx->active_oncpu)
1249                 cpuctx->exclusive = 0;
1250 }
1251
1252 /*
1253  * Called to enable a whole group of events.
1254  * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
1255  * Assumes the caller has disabled interrupts and has
1256  * frozen the PMU with hw_perf_save_disable.
1257  *
1258  * called with PMU disabled. If successful and return value 1,
1259  * then guaranteed to call perf_enable() and hw_perf_enable()
1260  */
1261 int hw_perf_group_sched_in(struct perf_event *leader,
1262                struct perf_cpu_context *cpuctx,
1263                struct perf_event_context *ctx)
1264 {
1265         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1266         struct perf_event *sub;
1267         int assign[X86_PMC_IDX_MAX];
1268         int n0, n1, ret;
1269
1270         if (!x86_pmu_initialized())
1271                 return 0;
1272
1273         /* n0 = total number of events */
1274         n0 = collect_events(cpuc, leader, true);
1275         if (n0 < 0)
1276                 return n0;
1277
1278         ret = x86_pmu.schedule_events(cpuc, n0, assign);
1279         if (ret)
1280                 return ret;
1281
1282         ret = x86_event_sched_in(leader, cpuctx);
1283         if (ret)
1284                 return ret;
1285
1286         n1 = 1;
1287         list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1288                 if (sub->state > PERF_EVENT_STATE_OFF) {
1289                         ret = x86_event_sched_in(sub, cpuctx);
1290                         if (ret)
1291                                 goto undo;
1292                         ++n1;
1293                 }
1294         }
1295         /*
1296          * copy new assignment, now we know it is possible
1297          * will be used by hw_perf_enable()
1298          */
1299         memcpy(cpuc->assign, assign, n0*sizeof(int));
1300
1301         cpuc->n_events  = n0;
1302         cpuc->n_added  += n1;
1303         ctx->nr_active += n1;
1304
1305         /*
1306          * 1 means successful and events are active
1307          * This is not quite true because we defer
1308          * actual activation until hw_perf_enable() but
1309          * this way we* ensure caller won't try to enable
1310          * individual events
1311          */
1312         return 1;
1313 undo:
1314         x86_event_sched_out(leader, cpuctx);
1315         n0  = 1;
1316         list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1317                 if (sub->state == PERF_EVENT_STATE_ACTIVE) {
1318                         x86_event_sched_out(sub, cpuctx);
1319                         if (++n0 == n1)
1320                                 break;
1321                 }
1322         }
1323         return ret;
1324 }
1325
1326 #include "perf_event_amd.c"
1327 #include "perf_event_p6.c"
1328 #include "perf_event_p4.c"
1329 #include "perf_event_intel_lbr.c"
1330 #include "perf_event_intel_ds.c"
1331 #include "perf_event_intel.c"
1332
1333 static int __cpuinit
1334 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1335 {
1336         unsigned int cpu = (long)hcpu;
1337         int ret = NOTIFY_OK;
1338
1339         switch (action & ~CPU_TASKS_FROZEN) {
1340         case CPU_UP_PREPARE:
1341                 if (x86_pmu.cpu_prepare)
1342                         ret = x86_pmu.cpu_prepare(cpu);
1343                 break;
1344
1345         case CPU_STARTING:
1346                 if (x86_pmu.cpu_starting)
1347                         x86_pmu.cpu_starting(cpu);
1348                 break;
1349
1350         case CPU_DYING:
1351                 if (x86_pmu.cpu_dying)
1352                         x86_pmu.cpu_dying(cpu);
1353                 break;
1354
1355         case CPU_UP_CANCELED:
1356         case CPU_DEAD:
1357                 if (x86_pmu.cpu_dead)
1358                         x86_pmu.cpu_dead(cpu);
1359                 break;
1360
1361         default:
1362                 break;
1363         }
1364
1365         return ret;
1366 }
1367
1368 static void __init pmu_check_apic(void)
1369 {
1370         if (cpu_has_apic)
1371                 return;
1372
1373         x86_pmu.apic = 0;
1374         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1375         pr_info("no hardware sampling interrupt available.\n");
1376 }
1377
1378 void __init init_hw_perf_events(void)
1379 {
1380         struct event_constraint *c;
1381         int err;
1382
1383         pr_info("Performance Events: ");
1384
1385         switch (boot_cpu_data.x86_vendor) {
1386         case X86_VENDOR_INTEL:
1387                 err = intel_pmu_init();
1388                 break;
1389         case X86_VENDOR_AMD:
1390                 err = amd_pmu_init();
1391                 break;
1392         default:
1393                 return;
1394         }
1395         if (err != 0) {
1396                 pr_cont("no PMU driver, software events only.\n");
1397                 return;
1398         }
1399
1400         pmu_check_apic();
1401
1402         pr_cont("%s PMU driver.\n", x86_pmu.name);
1403
1404         if (x86_pmu.quirks)
1405                 x86_pmu.quirks();
1406
1407         if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1408                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1409                      x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1410                 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1411         }
1412         x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1413         perf_max_events = x86_pmu.num_counters;
1414
1415         if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1416                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1417                      x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1418                 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1419         }
1420
1421         x86_pmu.intel_ctrl |=
1422                 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1423
1424         perf_events_lapic_init();
1425         register_die_notifier(&perf_event_nmi_notifier);
1426
1427         unconstrained = (struct event_constraint)
1428                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1429                                    0, x86_pmu.num_counters);
1430
1431         if (x86_pmu.event_constraints) {
1432                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1433                         if (c->cmask != X86_RAW_EVENT_MASK)
1434                                 continue;
1435
1436                         c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1437                         c->weight += x86_pmu.num_counters;
1438                 }
1439         }
1440
1441         pr_info("... version:                %d\n",     x86_pmu.version);
1442         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1443         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1444         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1445         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1446         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1447         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1448
1449         perf_cpu_notifier(x86_pmu_notifier);
1450 }
1451
1452 static inline void x86_pmu_read(struct perf_event *event)
1453 {
1454         x86_perf_event_update(event);
1455 }
1456
1457 static const struct pmu pmu = {
1458         .enable         = x86_pmu_enable,
1459         .disable        = x86_pmu_disable,
1460         .start          = x86_pmu_start,
1461         .stop           = x86_pmu_stop,
1462         .read           = x86_pmu_read,
1463         .unthrottle     = x86_pmu_unthrottle,
1464 };
1465
1466 /*
1467  * validate that we can schedule this event
1468  */
1469 static int validate_event(struct perf_event *event)
1470 {
1471         struct cpu_hw_events *fake_cpuc;
1472         struct event_constraint *c;
1473         int ret = 0;
1474
1475         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1476         if (!fake_cpuc)
1477                 return -ENOMEM;
1478
1479         c = x86_pmu.get_event_constraints(fake_cpuc, event);
1480
1481         if (!c || !c->weight)
1482                 ret = -ENOSPC;
1483
1484         if (x86_pmu.put_event_constraints)
1485                 x86_pmu.put_event_constraints(fake_cpuc, event);
1486
1487         kfree(fake_cpuc);
1488
1489         return ret;
1490 }
1491
1492 /*
1493  * validate a single event group
1494  *
1495  * validation include:
1496  *      - check events are compatible which each other
1497  *      - events do not compete for the same counter
1498  *      - number of events <= number of counters
1499  *
1500  * validation ensures the group can be loaded onto the
1501  * PMU if it was the only group available.
1502  */
1503 static int validate_group(struct perf_event *event)
1504 {
1505         struct perf_event *leader = event->group_leader;
1506         struct cpu_hw_events *fake_cpuc;
1507         int ret, n;
1508
1509         ret = -ENOMEM;
1510         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1511         if (!fake_cpuc)
1512                 goto out;
1513
1514         /*
1515          * the event is not yet connected with its
1516          * siblings therefore we must first collect
1517          * existing siblings, then add the new event
1518          * before we can simulate the scheduling
1519          */
1520         ret = -ENOSPC;
1521         n = collect_events(fake_cpuc, leader, true);
1522         if (n < 0)
1523                 goto out_free;
1524
1525         fake_cpuc->n_events = n;
1526         n = collect_events(fake_cpuc, event, false);
1527         if (n < 0)
1528                 goto out_free;
1529
1530         fake_cpuc->n_events = n;
1531
1532         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1533
1534 out_free:
1535         kfree(fake_cpuc);
1536 out:
1537         return ret;
1538 }
1539
1540 const struct pmu *hw_perf_event_init(struct perf_event *event)
1541 {
1542         const struct pmu *tmp;
1543         int err;
1544
1545         err = __hw_perf_event_init(event);
1546         if (!err) {
1547                 /*
1548                  * we temporarily connect event to its pmu
1549                  * such that validate_group() can classify
1550                  * it as an x86 event using is_x86_event()
1551                  */
1552                 tmp = event->pmu;
1553                 event->pmu = &pmu;
1554
1555                 if (event->group_leader != event)
1556                         err = validate_group(event);
1557                 else
1558                         err = validate_event(event);
1559
1560                 event->pmu = tmp;
1561         }
1562         if (err) {
1563                 if (event->destroy)
1564                         event->destroy(event);
1565                 return ERR_PTR(err);
1566         }
1567
1568         return &pmu;
1569 }
1570
1571 /*
1572  * callchain support
1573  */
1574
1575 static inline
1576 void callchain_store(struct perf_callchain_entry *entry, u64 ip)
1577 {
1578         if (entry->nr < PERF_MAX_STACK_DEPTH)
1579                 entry->ip[entry->nr++] = ip;
1580 }
1581
1582 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
1583 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry);
1584
1585
1586 static void
1587 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1588 {
1589         /* Ignore warnings */
1590 }
1591
1592 static void backtrace_warning(void *data, char *msg)
1593 {
1594         /* Ignore warnings */
1595 }
1596
1597 static int backtrace_stack(void *data, char *name)
1598 {
1599         return 0;
1600 }
1601
1602 static void backtrace_address(void *data, unsigned long addr, int reliable)
1603 {
1604         struct perf_callchain_entry *entry = data;
1605
1606         callchain_store(entry, addr);
1607 }
1608
1609 static const struct stacktrace_ops backtrace_ops = {
1610         .warning                = backtrace_warning,
1611         .warning_symbol         = backtrace_warning_symbol,
1612         .stack                  = backtrace_stack,
1613         .address                = backtrace_address,
1614         .walk_stack             = print_context_stack_bp,
1615 };
1616
1617 #include "../dumpstack.h"
1618
1619 static void
1620 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1621 {
1622         callchain_store(entry, PERF_CONTEXT_KERNEL);
1623         callchain_store(entry, regs->ip);
1624
1625         dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
1626 }
1627
1628 #ifdef CONFIG_COMPAT
1629 static inline int
1630 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1631 {
1632         /* 32-bit process in 64-bit kernel. */
1633         struct stack_frame_ia32 frame;
1634         const void __user *fp;
1635
1636         if (!test_thread_flag(TIF_IA32))
1637                 return 0;
1638
1639         fp = compat_ptr(regs->bp);
1640         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1641                 unsigned long bytes;
1642                 frame.next_frame     = 0;
1643                 frame.return_address = 0;
1644
1645                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1646                 if (bytes != sizeof(frame))
1647                         break;
1648
1649                 if (fp < compat_ptr(regs->sp))
1650                         break;
1651
1652                 callchain_store(entry, frame.return_address);
1653                 fp = compat_ptr(frame.next_frame);
1654         }
1655         return 1;
1656 }
1657 #else
1658 static inline int
1659 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1660 {
1661     return 0;
1662 }
1663 #endif
1664
1665 static void
1666 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1667 {
1668         struct stack_frame frame;
1669         const void __user *fp;
1670
1671         if (!user_mode(regs))
1672                 regs = task_pt_regs(current);
1673
1674         fp = (void __user *)regs->bp;
1675
1676         callchain_store(entry, PERF_CONTEXT_USER);
1677         callchain_store(entry, regs->ip);
1678
1679         if (perf_callchain_user32(regs, entry))
1680                 return;
1681
1682         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1683                 unsigned long bytes;
1684                 frame.next_frame             = NULL;
1685                 frame.return_address = 0;
1686
1687                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1688                 if (bytes != sizeof(frame))
1689                         break;
1690
1691                 if ((unsigned long)fp < regs->sp)
1692                         break;
1693
1694                 callchain_store(entry, frame.return_address);
1695                 fp = frame.next_frame;
1696         }
1697 }
1698
1699 static void
1700 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1701 {
1702         int is_user;
1703
1704         if (!regs)
1705                 return;
1706
1707         is_user = user_mode(regs);
1708
1709         if (is_user && current->state != TASK_RUNNING)
1710                 return;
1711
1712         if (!is_user)
1713                 perf_callchain_kernel(regs, entry);
1714
1715         if (current->mm)
1716                 perf_callchain_user(regs, entry);
1717 }
1718
1719 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1720 {
1721         struct perf_callchain_entry *entry;
1722
1723         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1724                 /* TODO: We don't support guest os callchain now */
1725                 return NULL;
1726         }
1727
1728         if (in_nmi())
1729                 entry = &__get_cpu_var(pmc_nmi_entry);
1730         else
1731                 entry = &__get_cpu_var(pmc_irq_entry);
1732
1733         entry->nr = 0;
1734
1735         perf_do_callchain(regs, entry);
1736
1737         return entry;
1738 }
1739
1740 void perf_arch_fetch_caller_regs(struct pt_regs *regs, unsigned long ip, int skip)
1741 {
1742         regs->ip = ip;
1743         /*
1744          * perf_arch_fetch_caller_regs adds another call, we need to increment
1745          * the skip level
1746          */
1747         regs->bp = rewind_frame_pointer(skip + 1);
1748         regs->cs = __KERNEL_CS;
1749         local_save_flags(regs->flags);
1750 }
1751
1752 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1753 {
1754         unsigned long ip;
1755
1756         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1757                 ip = perf_guest_cbs->get_guest_ip();
1758         else
1759                 ip = instruction_pointer(regs);
1760
1761         return ip;
1762 }
1763
1764 unsigned long perf_misc_flags(struct pt_regs *regs)
1765 {
1766         int misc = 0;
1767
1768         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1769                 if (perf_guest_cbs->is_user_mode())
1770                         misc |= PERF_RECORD_MISC_GUEST_USER;
1771                 else
1772                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1773         } else {
1774                 if (user_mode(regs))
1775                         misc |= PERF_RECORD_MISC_USER;
1776                 else
1777                         misc |= PERF_RECORD_MISC_KERNEL;
1778         }
1779
1780         if (regs->flags & PERF_EFLAGS_EXACT)
1781                 misc |= PERF_RECORD_MISC_EXACT;
1782
1783         return misc;
1784 }