arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/highmem.h>
  26 #include <linux/cpu.h>
  27 #include <linux/bitops.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/compat.h>
  33
  34 #if 0
  35 #undef wrmsrl
  36 #define wrmsrl(msr, val)                                        \
  37 do {                                                            \
  38         trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
  39                         (unsigned long)(val));                  \
  40         native_write_msr((msr), (u32)((u64)(val)),              \
  41                         (u32)((u64)(val) >> 32));               \
  42 } while (0)
  43 #endif
  44
  45 /*
  46  * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
  47  */
  48 static unsigned long
  49 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
  50 {
  51         unsigned long offset, addr = (unsigned long)from;
  52         int type = in_nmi() ? KM_NMI : KM_IRQ0;
  53         unsigned long size, len = 0;
  54         struct page *page;
  55         void *map;
  56         int ret;
  57
  58         do {
  59                 ret = __get_user_pages_fast(addr, 1, 0, &page);
  60                 if (!ret)
  61                         break;
  62
  63                 offset = addr & (PAGE_SIZE - 1);
  64                 size = min(PAGE_SIZE - offset, n - len);
  65
  66                 map = kmap_atomic(page, type);
  67                 memcpy(to, map+offset, size);
  68                 kunmap_atomic(map, type);
  69                 put_page(page);
  70
  71                 len  += size;
  72                 to   += size;
  73                 addr += size;
  74
  75         } while (len < n);
  76
  77         return len;
  78 }
  79
  80 struct event_constraint {
  81         union {
  82                 unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  83                 u64             idxmsk64;
  84         };
  85         u64     code;
  86         u64     cmask;
  87         int     weight;
  88 };
  89
  90 struct amd_nb {
  91         int nb_id;  /* NorthBridge id */
  92         int refcnt; /* reference count */
  93         struct perf_event *owners[X86_PMC_IDX_MAX];
  94         struct event_constraint event_constraints[X86_PMC_IDX_MAX];
  95 };
  96
  97 #define MAX_LBR_ENTRIES         16
  98
  99 struct cpu_hw_events {
 100         /*
 101          * Generic x86 PMC bits
 102          */
 103         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
 104         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 105         int                     enabled;
 106
 107         int                     n_events;
 108         int                     n_added;
 109         int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
 110         u64                     tags[X86_PMC_IDX_MAX];
 111         struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
 112
 113         /*
 114          * Intel DebugStore bits
 115          */
 116         struct debug_store      *ds;
 117         u64                     pebs_enabled;
 118
 119         /*
 120          * Intel LBR bits
 121          */
 122         int                             lbr_users;
 123         void                            *lbr_context;
 124         struct perf_branch_stack        lbr_stack;
 125         struct perf_branch_entry        lbr_entries[MAX_LBR_ENTRIES];
 126
 127         /*
 128          * AMD specific bits
 129          */
 130         struct amd_nb           *amd_nb;
 131 };
 132
 133 #define __EVENT_CONSTRAINT(c, n, m, w) {\
 134         { .idxmsk64 = (n) },            \
 135         .code = (c),                    \
 136         .cmask = (m),                   \
 137         .weight = (w),                  \
 138 }
 139
 140 #define EVENT_CONSTRAINT(c, n, m)       \
 141         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
 142
 143 /*
 144  * Constraint on the Event code.
 145  */
 146 #define INTEL_EVENT_CONSTRAINT(c, n)    \
 147         EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
 148
 149 /*
 150  * Constraint on the Event code + UMask + fixed-mask
 151  *
 152  * filter mask to validate fixed counter events.
 153  * the following filters disqualify for fixed counters:
 154  *  - inv
 155  *  - edge
 156  *  - cnt-mask
 157  *  The other filters are supported by fixed counters.
 158  *  The any-thread option is supported starting with v3.
 159  */
 160 #define FIXED_EVENT_CONSTRAINT(c, n)    \
 161         EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
 162
 163 /*
 164  * Constraint on the Event code + UMask
 165  */
 166 #define PEBS_EVENT_CONSTRAINT(c, n)     \
 167         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
 168
 169 #define EVENT_CONSTRAINT_END            \
 170         EVENT_CONSTRAINT(0, 0, 0)
 171
 172 #define for_each_event_constraint(e, c) \
 173         for ((e) = (c); (e)->cmask; (e)++)
 174
 175 union perf_capabilities {
 176         struct {
 177                 u64     lbr_format    : 6;
 178                 u64     pebs_trap     : 1;
 179                 u64     pebs_arch_reg : 1;
 180                 u64     pebs_format   : 4;
 181                 u64     smm_freeze    : 1;
 182         };
 183         u64     capabilities;
 184 };
 185
 186 /*
 187  * struct x86_pmu - generic x86 pmu
 188  */
 189 struct x86_pmu {
 190         /*
 191          * Generic x86 PMC bits
 192          */
 193         const char      *name;
 194         int             version;
 195         int             (*handle_irq)(struct pt_regs *);
 196         void            (*disable_all)(void);
 197         void            (*enable_all)(int added);
 198         void            (*enable)(struct perf_event *);
 199         void            (*disable)(struct perf_event *);
 200         int             (*hw_config)(struct perf_event *event);
 201         int             (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
 202         unsigned        eventsel;
 203         unsigned        perfctr;
 204         u64             (*event_map)(int);
 205         int             max_events;
 206         int             num_counters;
 207         int             num_counters_fixed;
 208         int             cntval_bits;
 209         u64             cntval_mask;
 210         int             apic;
 211         u64             max_period;
 212         struct event_constraint *
 213                         (*get_event_constraints)(struct cpu_hw_events *cpuc,
 214                                                  struct perf_event *event);
 215
 216         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
 217                                                  struct perf_event *event);
 218         struct event_constraint *event_constraints;
 219         void            (*quirks)(void);
 220
 221         int             (*cpu_prepare)(int cpu);
 222         void            (*cpu_starting)(int cpu);
 223         void            (*cpu_dying)(int cpu);
 224         void            (*cpu_dead)(int cpu);
 225
 226         /*
 227          * Intel Arch Perfmon v2+
 228          */
 229         u64                     intel_ctrl;
 230         union perf_capabilities intel_cap;
 231
 232         /*
 233          * Intel DebugStore bits
 234          */
 235         int             bts, pebs;
 236         int             pebs_record_size;
 237         void            (*drain_pebs)(struct pt_regs *regs);
 238         struct event_constraint *pebs_constraints;
 239
 240         /*
 241          * Intel LBR
 242          */
 243         unsigned long   lbr_tos, lbr_from, lbr_to; /* MSR base regs       */
 244         int             lbr_nr;                    /* hardware stack size */
 245 };
 246
 247 static struct x86_pmu x86_pmu __read_mostly;
 248
 249 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
 250         .enabled = 1,
 251 };
 252
 253 static int x86_perf_event_set_period(struct perf_event *event);
 254
 255 /*
 256  * Generalized hw caching related hw_event table, filled
 257  * in on a per model basis. A value of 0 means
 258  * 'not supported', -1 means 'hw_event makes no sense on
 259  * this CPU', any other value means the raw hw_event
 260  * ID.
 261  */
 262
 263 #define C(x) PERF_COUNT_HW_CACHE_##x
 264
 265 static u64 __read_mostly hw_cache_event_ids
 266                                 [PERF_COUNT_HW_CACHE_MAX]
 267                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 268                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 269
 270 /*
 271  * Propagate event elapsed time into the generic event.
 272  * Can only be executed on the CPU where the event is active.
 273  * Returns the delta events processed.
 274  */
 275 static u64
 276 x86_perf_event_update(struct perf_event *event)
 277 {
 278         struct hw_perf_event *hwc = &event->hw;
 279         int shift = 64 - x86_pmu.cntval_bits;
 280         u64 prev_raw_count, new_raw_count;
 281         int idx = hwc->idx;
 282         s64 delta;
 283
 284         if (idx == X86_PMC_IDX_FIXED_BTS)
 285                 return 0;
 286
 287         /*
 288          * Careful: an NMI might modify the previous event value.
 289          *
 290          * Our tactic to handle this is to first atomically read and
 291          * exchange a new raw count - then add that new-prev delta
 292          * count to the generic event atomically:
 293          */
 294 again:
 295         prev_raw_count = atomic64_read(&hwc->prev_count);
 296         rdmsrl(hwc->event_base + idx, new_raw_count);
 297
 298         if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
 299                                         new_raw_count) != prev_raw_count)
 300                 goto again;
 301
 302         /*
 303          * Now we have the new raw value and have updated the prev
 304          * timestamp already. We can now calculate the elapsed delta
 305          * (event-)time and add that to the generic event.
 306          *
 307          * Careful, not all hw sign-extends above the physical width
 308          * of the count.
 309          */
 310         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 311         delta >>= shift;
 312
 313         atomic64_add(delta, &event->count);
 314         atomic64_sub(delta, &hwc->period_left);
 315
 316         return new_raw_count;
 317 }
 318
 319 static atomic_t active_events;
 320 static DEFINE_MUTEX(pmc_reserve_mutex);
 321
 322 #ifdef CONFIG_X86_LOCAL_APIC
 323
 324 static bool reserve_pmc_hardware(void)
 325 {
 326         int i;
 327
 328         if (nmi_watchdog == NMI_LOCAL_APIC)
 329                 disable_lapic_nmi_watchdog();
 330
 331         for (i = 0; i < x86_pmu.num_counters; i++) {
 332                 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
 333                         goto perfctr_fail;
 334         }
 335
 336         for (i = 0; i < x86_pmu.num_counters; i++) {
 337                 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
 338                         goto eventsel_fail;
 339         }
 340
 341         return true;
 342
 343 eventsel_fail:
 344         for (i--; i >= 0; i--)
 345                 release_evntsel_nmi(x86_pmu.eventsel + i);
 346
 347         i = x86_pmu.num_counters;
 348
 349 perfctr_fail:
 350         for (i--; i >= 0; i--)
 351                 release_perfctr_nmi(x86_pmu.perfctr + i);
 352
 353         if (nmi_watchdog == NMI_LOCAL_APIC)
 354                 enable_lapic_nmi_watchdog();
 355
 356         return false;
 357 }
 358
 359 static void release_pmc_hardware(void)
 360 {
 361         int i;
 362
 363         for (i = 0; i < x86_pmu.num_counters; i++) {
 364                 release_perfctr_nmi(x86_pmu.perfctr + i);
 365                 release_evntsel_nmi(x86_pmu.eventsel + i);
 366         }
 367
 368         if (nmi_watchdog == NMI_LOCAL_APIC)
 369                 enable_lapic_nmi_watchdog();
 370 }
 371
 372 #else
 373
 374 static bool reserve_pmc_hardware(void) { return true; }
 375 static void release_pmc_hardware(void) {}
 376
 377 #endif
 378
 379 static int reserve_ds_buffers(void);
 380 static void release_ds_buffers(void);
 381
 382 static void hw_perf_event_destroy(struct perf_event *event)
 383 {
 384         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 385                 release_pmc_hardware();
 386                 release_ds_buffers();
 387                 mutex_unlock(&pmc_reserve_mutex);
 388         }
 389 }
 390
 391 static inline int x86_pmu_initialized(void)
 392 {
 393         return x86_pmu.handle_irq != NULL;
 394 }
 395
 396 static inline int
 397 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
 398 {
 399         unsigned int cache_type, cache_op, cache_result;
 400         u64 config, val;
 401
 402         config = attr->config;
 403
 404         cache_type = (config >>  0) & 0xff;
 405         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 406                 return -EINVAL;
 407
 408         cache_op = (config >>  8) & 0xff;
 409         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 410                 return -EINVAL;
 411
 412         cache_result = (config >> 16) & 0xff;
 413         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 414                 return -EINVAL;
 415
 416         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 417
 418         if (val == 0)
 419                 return -ENOENT;
 420
 421         if (val == -1)
 422                 return -EINVAL;
 423
 424         hwc->config |= val;
 425
 426         return 0;
 427 }
 428
 429 static int x86_setup_perfctr(struct perf_event *event);
 430
 431 static int x86_pmu_hw_config(struct perf_event *event)
 432 {
 433         /*
 434          * Generate PMC IRQs:
 435          * (keep 'enabled' bit clear for now)
 436          */
 437         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 438
 439         /*
 440          * Count user and OS events unless requested not to
 441          */
 442         if (!event->attr.exclude_user)
 443                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 444         if (!event->attr.exclude_kernel)
 445                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 446
 447         if (event->attr.type == PERF_TYPE_RAW)
 448                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 449
 450         return 0;
 451 }
 452
 453 /*
 454  * Setup the hardware configuration for a given attr_type
 455  */
 456 static int __hw_perf_event_init(struct perf_event *event)
 457 {
 458         int err;
 459
 460         if (!x86_pmu_initialized())
 461                 return -ENODEV;
 462
 463         err = 0;
 464         if (!atomic_inc_not_zero(&active_events)) {
 465                 mutex_lock(&pmc_reserve_mutex);
 466                 if (atomic_read(&active_events) == 0) {
 467                         if (!reserve_pmc_hardware())
 468                                 err = -EBUSY;
 469                         else {
 470                                 err = reserve_ds_buffers();
 471                                 if (err)
 472                                         release_pmc_hardware();
 473                         }
 474                 }
 475                 if (!err)
 476                         atomic_inc(&active_events);
 477                 mutex_unlock(&pmc_reserve_mutex);
 478         }
 479         if (err)
 480                 return err;
 481
 482         event->destroy = hw_perf_event_destroy;
 483
 484         event->hw.idx = -1;
 485         event->hw.last_cpu = -1;
 486         event->hw.last_tag = ~0ULL;
 487
 488         /* Processor specifics */
 489         err = x86_pmu.hw_config(event);
 490         if (err)
 491                 return err;
 492
 493         return x86_setup_perfctr(event);
 494 }
 495
 496 static int x86_setup_perfctr(struct perf_event *event)
 497 {
 498         struct perf_event_attr *attr = &event->attr;
 499         struct hw_perf_event *hwc = &event->hw;
 500         u64 config;
 501
 502         if (!hwc->sample_period) {
 503                 hwc->sample_period = x86_pmu.max_period;
 504                 hwc->last_period = hwc->sample_period;
 505                 atomic64_set(&hwc->period_left, hwc->sample_period);
 506         } else {
 507                 /*
 508                  * If we have a PMU initialized but no APIC
 509                  * interrupts, we cannot sample hardware
 510                  * events (user-space has to fall back and
 511                  * sample via a hrtimer based software event):
 512                  */
 513                 if (!x86_pmu.apic)
 514                         return -EOPNOTSUPP;
 515         }
 516
 517         if (attr->type == PERF_TYPE_RAW)
 518                 return 0;
 519
 520         if (attr->type == PERF_TYPE_HW_CACHE)
 521                 return set_ext_hw_attr(hwc, attr);
 522
 523         if (attr->config >= x86_pmu.max_events)
 524                 return -EINVAL;
 525
 526         /*
 527          * The generic map:
 528          */
 529         config = x86_pmu.event_map(attr->config);
 530
 531         if (config == 0)
 532                 return -ENOENT;
 533
 534         if (config == -1LL)
 535                 return -EINVAL;
 536
 537         /*
 538          * Branch tracing:
 539          */
 540         if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
 541             (hwc->sample_period == 1)) {
 542                 /* BTS is not supported by this architecture. */
 543                 if (!x86_pmu.bts)
 544                         return -EOPNOTSUPP;
 545
 546                 /* BTS is currently only allowed for user-mode. */
 547                 if (!attr->exclude_kernel)
 548                         return -EOPNOTSUPP;
 549         }
 550
 551         hwc->config |= config;
 552
 553         return 0;
 554 }
 555
 556 static void x86_pmu_disable_all(void)
 557 {
 558         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 559         int idx;
 560
 561         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 562                 u64 val;
 563
 564                 if (!test_bit(idx, cpuc->active_mask))
 565                         continue;
 566                 rdmsrl(x86_pmu.eventsel + idx, val);
 567                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 568                         continue;
 569                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 570                 wrmsrl(x86_pmu.eventsel + idx, val);
 571         }
 572 }
 573
 574 void hw_perf_disable(void)
 575 {
 576         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 577
 578         if (!x86_pmu_initialized())
 579                 return;
 580
 581         if (!cpuc->enabled)
 582                 return;
 583
 584         cpuc->n_added = 0;
 585         cpuc->enabled = 0;
 586         barrier();
 587
 588         x86_pmu.disable_all();
 589 }
 590
 591 static void x86_pmu_enable_all(int added)
 592 {
 593         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 594         int idx;
 595
 596         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 597                 struct perf_event *event = cpuc->events[idx];
 598                 u64 val;
 599
 600                 if (!test_bit(idx, cpuc->active_mask))
 601                         continue;
 602
 603                 val = event->hw.config;
 604                 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
 605                 wrmsrl(x86_pmu.eventsel + idx, val);
 606         }
 607 }
 608
 609 static const struct pmu pmu;
 610
 611 static inline int is_x86_event(struct perf_event *event)
 612 {
 613         return event->pmu == &pmu;
 614 }
 615
 616 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 617 {
 618         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
 619         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 620         int i, j, w, wmax, num = 0;
 621         struct hw_perf_event *hwc;
 622
 623         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 624
 625         for (i = 0; i < n; i++) {
 626                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 627                 constraints[i] = c;
 628         }
 629
 630         /*
 631          * fastpath, try to reuse previous register
 632          */
 633         for (i = 0; i < n; i++) {
 634                 hwc = &cpuc->event_list[i]->hw;
 635                 c = constraints[i];
 636
 637                 /* never assigned */
 638                 if (hwc->idx == -1)
 639                         break;
 640
 641                 /* constraint still honored */
 642                 if (!test_bit(hwc->idx, c->idxmsk))
 643                         break;
 644
 645                 /* not already used */
 646                 if (test_bit(hwc->idx, used_mask))
 647                         break;
 648
 649                 __set_bit(hwc->idx, used_mask);
 650                 if (assign)
 651                         assign[i] = hwc->idx;
 652         }
 653         if (i == n)
 654                 goto done;
 655
 656         /*
 657          * begin slow path
 658          */
 659
 660         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 661
 662         /*
 663          * weight = number of possible counters
 664          *
 665          * 1    = most constrained, only works on one counter
 666          * wmax = least constrained, works on any counter
 667          *
 668          * assign events to counters starting with most
 669          * constrained events.
 670          */
 671         wmax = x86_pmu.num_counters;
 672
 673         /*
 674          * when fixed event counters are present,
 675          * wmax is incremented by 1 to account
 676          * for one more choice
 677          */
 678         if (x86_pmu.num_counters_fixed)
 679                 wmax++;
 680
 681         for (w = 1, num = n; num && w <= wmax; w++) {
 682                 /* for each event */
 683                 for (i = 0; num && i < n; i++) {
 684                         c = constraints[i];
 685                         hwc = &cpuc->event_list[i]->hw;
 686
 687                         if (c->weight != w)
 688                                 continue;
 689
 690                         for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
 691                                 if (!test_bit(j, used_mask))
 692                                         break;
 693                         }
 694
 695                         if (j == X86_PMC_IDX_MAX)
 696                                 break;
 697
 698                         __set_bit(j, used_mask);
 699
 700                         if (assign)
 701                                 assign[i] = j;
 702                         num--;
 703                 }
 704         }
 705 done:
 706         /*
 707          * scheduling failed or is just a simulation,
 708          * free resources if necessary
 709          */
 710         if (!assign || num) {
 711                 for (i = 0; i < n; i++) {
 712                         if (x86_pmu.put_event_constraints)
 713                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
 714                 }
 715         }
 716         return num ? -ENOSPC : 0;
 717 }
 718
 719 /*
 720  * dogrp: true if must collect siblings events (group)
 721  * returns total number of events and error code
 722  */
 723 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 724 {
 725         struct perf_event *event;
 726         int n, max_count;
 727
 728         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 729
 730         /* current number of events already accepted */
 731         n = cpuc->n_events;
 732
 733         if (is_x86_event(leader)) {
 734                 if (n >= max_count)
 735                         return -ENOSPC;
 736                 cpuc->event_list[n] = leader;
 737                 n++;
 738         }
 739         if (!dogrp)
 740                 return n;
 741
 742         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 743                 if (!is_x86_event(event) ||
 744                     event->state <= PERF_EVENT_STATE_OFF)
 745                         continue;
 746
 747                 if (n >= max_count)
 748                         return -ENOSPC;
 749
 750                 cpuc->event_list[n] = event;
 751                 n++;
 752         }
 753         return n;
 754 }
 755
 756 static inline void x86_assign_hw_event(struct perf_event *event,
 757                                 struct cpu_hw_events *cpuc, int i)
 758 {
 759         struct hw_perf_event *hwc = &event->hw;
 760
 761         hwc->idx = cpuc->assign[i];
 762         hwc->last_cpu = smp_processor_id();
 763         hwc->last_tag = ++cpuc->tags[i];
 764
 765         if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
 766                 hwc->config_base = 0;
 767                 hwc->event_base = 0;
 768         } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
 769                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 770                 /*
 771                  * We set it so that event_base + idx in wrmsr/rdmsr maps to
 772                  * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
 773                  */
 774                 hwc->event_base =
 775                         MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
 776         } else {
 777                 hwc->config_base = x86_pmu.eventsel;
 778                 hwc->event_base  = x86_pmu.perfctr;
 779         }
 780 }
 781
 782 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 783                                         struct cpu_hw_events *cpuc,
 784                                         int i)
 785 {
 786         return hwc->idx == cpuc->assign[i] &&
 787                 hwc->last_cpu == smp_processor_id() &&
 788                 hwc->last_tag == cpuc->tags[i];
 789 }
 790
 791 static int x86_pmu_start(struct perf_event *event);
 792 static void x86_pmu_stop(struct perf_event *event);
 793
 794 void hw_perf_enable(void)
 795 {
 796         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 797         struct perf_event *event;
 798         struct hw_perf_event *hwc;
 799         int i, added = cpuc->n_added;
 800
 801         if (!x86_pmu_initialized())
 802                 return;
 803
 804         if (cpuc->enabled)
 805                 return;
 806
 807         if (cpuc->n_added) {
 808                 int n_running = cpuc->n_events - cpuc->n_added;
 809                 /*
 810                  * apply assignment obtained either from
 811                  * hw_perf_group_sched_in() or x86_pmu_enable()
 812                  *
 813                  * step1: save events moving to new counters
 814                  * step2: reprogram moved events into new counters
 815                  */
 816                 for (i = 0; i < n_running; i++) {
 817                         event = cpuc->event_list[i];
 818                         hwc = &event->hw;
 819
 820                         /*
 821                          * we can avoid reprogramming counter if:
 822                          * - assigned same counter as last time
 823                          * - running on same CPU as last time
 824                          * - no other event has used the counter since
 825                          */
 826                         if (hwc->idx == -1 ||
 827                             match_prev_assignment(hwc, cpuc, i))
 828                                 continue;
 829
 830                         x86_pmu_stop(event);
 831                 }
 832
 833                 for (i = 0; i < cpuc->n_events; i++) {
 834                         event = cpuc->event_list[i];
 835                         hwc = &event->hw;
 836
 837                         if (!match_prev_assignment(hwc, cpuc, i))
 838                                 x86_assign_hw_event(event, cpuc, i);
 839                         else if (i < n_running)
 840                                 continue;
 841
 842                         x86_pmu_start(event);
 843                 }
 844                 cpuc->n_added = 0;
 845                 perf_events_lapic_init();
 846         }
 847
 848         cpuc->enabled = 1;
 849         barrier();
 850
 851         x86_pmu.enable_all(added);
 852 }
 853
 854 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc)
 855 {
 856         wrmsrl(hwc->config_base + hwc->idx,
 857                               hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE);
 858 }
 859
 860 static inline void x86_pmu_disable_event(struct perf_event *event)
 861 {
 862         struct hw_perf_event *hwc = &event->hw;
 863
 864         wrmsrl(hwc->config_base + hwc->idx, hwc->config);
 865 }
 866
 867 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
 868
 869 /*
 870  * Set the next IRQ period, based on the hwc->period_left value.
 871  * To be called with the event disabled in hw:
 872  */
 873 static int
 874 x86_perf_event_set_period(struct perf_event *event)
 875 {
 876         struct hw_perf_event *hwc = &event->hw;
 877         s64 left = atomic64_read(&hwc->period_left);
 878         s64 period = hwc->sample_period;
 879         int ret = 0, idx = hwc->idx;
 880
 881         if (idx == X86_PMC_IDX_FIXED_BTS)
 882                 return 0;
 883
 884         /*
 885          * If we are way outside a reasonable range then just skip forward:
 886          */
 887         if (unlikely(left <= -period)) {
 888                 left = period;
 889                 atomic64_set(&hwc->period_left, left);
 890                 hwc->last_period = period;
 891                 ret = 1;
 892         }
 893
 894         if (unlikely(left <= 0)) {
 895                 left += period;
 896                 atomic64_set(&hwc->period_left, left);
 897                 hwc->last_period = period;
 898                 ret = 1;
 899         }
 900         /*
 901          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
 902          */
 903         if (unlikely(left < 2))
 904                 left = 2;
 905
 906         if (left > x86_pmu.max_period)
 907                 left = x86_pmu.max_period;
 908
 909         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
 910
 911         /*
 912          * The hw event starts counting from this event offset,
 913          * mark it to be able to extra future deltas:
 914          */
 915         atomic64_set(&hwc->prev_count, (u64)-left);
 916
 917         wrmsrl(hwc->event_base + idx,
 918                         (u64)(-left) & x86_pmu.cntval_mask);
 919
 920         perf_event_update_userpage(event);
 921
 922         return ret;
 923 }
 924
 925 static void x86_pmu_enable_event(struct perf_event *event)
 926 {
 927         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 928         if (cpuc->enabled)
 929                 __x86_pmu_enable_event(&event->hw);
 930 }
 931
 932 /*
 933  * activate a single event
 934  *
 935  * The event is added to the group of enabled events
 936  * but only if it can be scehduled with existing events.
 937  *
 938  * Called with PMU disabled. If successful and return value 1,
 939  * then guaranteed to call perf_enable() and hw_perf_enable()
 940  */
 941 static int x86_pmu_enable(struct perf_event *event)
 942 {
 943         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 944         struct hw_perf_event *hwc;
 945         int assign[X86_PMC_IDX_MAX];
 946         int n, n0, ret;
 947
 948         hwc = &event->hw;
 949
 950         n0 = cpuc->n_events;
 951         n = collect_events(cpuc, event, false);
 952         if (n < 0)
 953                 return n;
 954
 955         ret = x86_pmu.schedule_events(cpuc, n, assign);
 956         if (ret)
 957                 return ret;
 958         /*
 959          * copy new assignment, now we know it is possible
 960          * will be used by hw_perf_enable()
 961          */
 962         memcpy(cpuc->assign, assign, n*sizeof(int));
 963
 964         cpuc->n_events = n;
 965         cpuc->n_added += n - n0;
 966
 967         return 0;
 968 }
 969
 970 static int x86_pmu_start(struct perf_event *event)
 971 {
 972         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 973         int idx = event->hw.idx;
 974
 975         if (idx == -1)
 976                 return -EAGAIN;
 977
 978         x86_perf_event_set_period(event);
 979         cpuc->events[idx] = event;
 980         __set_bit(idx, cpuc->active_mask);
 981         x86_pmu.enable(event);
 982         perf_event_update_userpage(event);
 983
 984         return 0;
 985 }
 986
 987 static void x86_pmu_unthrottle(struct perf_event *event)
 988 {
 989         int ret = x86_pmu_start(event);
 990         WARN_ON_ONCE(ret);
 991 }
 992
 993 void perf_event_print_debug(void)
 994 {
 995         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
 996         u64 pebs;
 997         struct cpu_hw_events *cpuc;
 998         unsigned long flags;
 999         int cpu, idx;
1000
1001         if (!x86_pmu.num_counters)
1002                 return;
1003
1004         local_irq_save(flags);
1005
1006         cpu = smp_processor_id();
1007         cpuc = &per_cpu(cpu_hw_events, cpu);
1008
1009         if (x86_pmu.version >= 2) {
1010                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1011                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1012                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1013                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1014                 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1015
1016                 pr_info("\n");
1017                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1018                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1019                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1020                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1021                 pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1022         }
1023         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1024
1025         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1026                 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1027                 rdmsrl(x86_pmu.perfctr  + idx, pmc_count);
1028
1029                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1030
1031                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1032                         cpu, idx, pmc_ctrl);
1033                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1034                         cpu, idx, pmc_count);
1035                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1036                         cpu, idx, prev_left);
1037         }
1038         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1039                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1040
1041                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1042                         cpu, idx, pmc_count);
1043         }
1044         local_irq_restore(flags);
1045 }
1046
1047 static void x86_pmu_stop(struct perf_event *event)
1048 {
1049         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1050         struct hw_perf_event *hwc = &event->hw;
1051         int idx = hwc->idx;
1052
1053         if (!__test_and_clear_bit(idx, cpuc->active_mask))
1054                 return;
1055
1056         x86_pmu.disable(event);
1057
1058         /*
1059          * Drain the remaining delta count out of a event
1060          * that we are disabling:
1061          */
1062         x86_perf_event_update(event);
1063
1064         cpuc->events[idx] = NULL;
1065 }
1066
1067 static void x86_pmu_disable(struct perf_event *event)
1068 {
1069         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1070         int i;
1071
1072         x86_pmu_stop(event);
1073
1074         for (i = 0; i < cpuc->n_events; i++) {
1075                 if (event == cpuc->event_list[i]) {
1076
1077                         if (x86_pmu.put_event_constraints)
1078                                 x86_pmu.put_event_constraints(cpuc, event);
1079
1080                         while (++i < cpuc->n_events)
1081                                 cpuc->event_list[i-1] = cpuc->event_list[i];
1082
1083                         --cpuc->n_events;
1084                         break;
1085                 }
1086         }
1087         perf_event_update_userpage(event);
1088 }
1089
1090 static int x86_pmu_handle_irq(struct pt_regs *regs)
1091 {
1092         struct perf_sample_data data;
1093         struct cpu_hw_events *cpuc;
1094         struct perf_event *event;
1095         struct hw_perf_event *hwc;
1096         int idx, handled = 0;
1097         u64 val;
1098
1099         perf_sample_data_init(&data, 0);
1100
1101         cpuc = &__get_cpu_var(cpu_hw_events);
1102
1103         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1104                 if (!test_bit(idx, cpuc->active_mask))
1105                         continue;
1106
1107                 event = cpuc->events[idx];
1108                 hwc = &event->hw;
1109
1110                 val = x86_perf_event_update(event);
1111                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1112                         continue;
1113
1114                 /*
1115                  * event overflow
1116                  */
1117                 handled         = 1;
1118                 data.period     = event->hw.last_period;
1119
1120                 if (!x86_perf_event_set_period(event))
1121                         continue;
1122
1123                 if (perf_event_overflow(event, 1, &data, regs))
1124                         x86_pmu_stop(event);
1125         }
1126
1127         if (handled)
1128                 inc_irq_stat(apic_perf_irqs);
1129
1130         return handled;
1131 }
1132
1133 void smp_perf_pending_interrupt(struct pt_regs *regs)
1134 {
1135         irq_enter();
1136         ack_APIC_irq();
1137         inc_irq_stat(apic_pending_irqs);
1138         perf_event_do_pending();
1139         irq_exit();
1140 }
1141
1142 void set_perf_event_pending(void)
1143 {
1144 #ifdef CONFIG_X86_LOCAL_APIC
1145         if (!x86_pmu.apic || !x86_pmu_initialized())
1146                 return;
1147
1148         apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1149 #endif
1150 }
1151
1152 void perf_events_lapic_init(void)
1153 {
1154         if (!x86_pmu.apic || !x86_pmu_initialized())
1155                 return;
1156
1157         /*
1158          * Always use NMI for PMU
1159          */
1160         apic_write(APIC_LVTPC, APIC_DM_NMI);
1161 }
1162
1163 static int __kprobes
1164 perf_event_nmi_handler(struct notifier_block *self,
1165                          unsigned long cmd, void *__args)
1166 {
1167         struct die_args *args = __args;
1168         struct pt_regs *regs;
1169
1170         if (!atomic_read(&active_events))
1171                 return NOTIFY_DONE;
1172
1173         switch (cmd) {
1174         case DIE_NMI:
1175         case DIE_NMI_IPI:
1176                 break;
1177
1178         default:
1179                 return NOTIFY_DONE;
1180         }
1181
1182         regs = args->regs;
1183
1184         apic_write(APIC_LVTPC, APIC_DM_NMI);
1185         /*
1186          * Can't rely on the handled return value to say it was our NMI, two
1187          * events could trigger 'simultaneously' raising two back-to-back NMIs.
1188          *
1189          * If the first NMI handles both, the latter will be empty and daze
1190          * the CPU.
1191          */
1192         x86_pmu.handle_irq(regs);
1193
1194         return NOTIFY_STOP;
1195 }
1196
1197 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1198         .notifier_call          = perf_event_nmi_handler,
1199         .next                   = NULL,
1200         .priority               = 1
1201 };
1202
1203 static struct event_constraint unconstrained;
1204 static struct event_constraint emptyconstraint;
1205
1206 static struct event_constraint *
1207 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1208 {
1209         struct event_constraint *c;
1210
1211         if (x86_pmu.event_constraints) {
1212                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1213                         if ((event->hw.config & c->cmask) == c->code)
1214                                 return c;
1215                 }
1216         }
1217
1218         return &unconstrained;
1219 }
1220
1221 static int x86_event_sched_in(struct perf_event *event,
1222                           struct perf_cpu_context *cpuctx)
1223 {
1224         int ret = 0;
1225
1226         event->state = PERF_EVENT_STATE_ACTIVE;
1227         event->oncpu = smp_processor_id();
1228         event->tstamp_running += event->ctx->time - event->tstamp_stopped;
1229
1230         if (!is_x86_event(event))
1231                 ret = event->pmu->enable(event);
1232
1233         if (!ret && !is_software_event(event))
1234                 cpuctx->active_oncpu++;
1235
1236         if (!ret && event->attr.exclusive)
1237                 cpuctx->exclusive = 1;
1238
1239         return ret;
1240 }
1241
1242 static void x86_event_sched_out(struct perf_event *event,
1243                             struct perf_cpu_context *cpuctx)
1244 {
1245         event->state = PERF_EVENT_STATE_INACTIVE;
1246         event->oncpu = -1;
1247
1248         if (!is_x86_event(event))
1249                 event->pmu->disable(event);
1250
1251         event->tstamp_running -= event->ctx->time - event->tstamp_stopped;
1252
1253         if (!is_software_event(event))
1254                 cpuctx->active_oncpu--;
1255
1256         if (event->attr.exclusive || !cpuctx->active_oncpu)
1257                 cpuctx->exclusive = 0;
1258 }
1259
1260 /*
1261  * Called to enable a whole group of events.
1262  * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
1263  * Assumes the caller has disabled interrupts and has
1264  * frozen the PMU with hw_perf_save_disable.
1265  *
1266  * called with PMU disabled. If successful and return value 1,
1267  * then guaranteed to call perf_enable() and hw_perf_enable()
1268  */
1269 int hw_perf_group_sched_in(struct perf_event *leader,
1270                struct perf_cpu_context *cpuctx,
1271                struct perf_event_context *ctx)
1272 {
1273         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1274         struct perf_event *sub;
1275         int assign[X86_PMC_IDX_MAX];
1276         int n0, n1, ret;
1277
1278         if (!x86_pmu_initialized())
1279                 return 0;
1280
1281         /* n0 = total number of events */
1282         n0 = collect_events(cpuc, leader, true);
1283         if (n0 < 0)
1284                 return n0;
1285
1286         ret = x86_pmu.schedule_events(cpuc, n0, assign);
1287         if (ret)
1288                 return ret;
1289
1290         ret = x86_event_sched_in(leader, cpuctx);
1291         if (ret)
1292                 return ret;
1293
1294         n1 = 1;
1295         list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1296                 if (sub->state > PERF_EVENT_STATE_OFF) {
1297                         ret = x86_event_sched_in(sub, cpuctx);
1298                         if (ret)
1299                                 goto undo;
1300                         ++n1;
1301                 }
1302         }
1303         /*
1304          * copy new assignment, now we know it is possible
1305          * will be used by hw_perf_enable()
1306          */
1307         memcpy(cpuc->assign, assign, n0*sizeof(int));
1308
1309         cpuc->n_events  = n0;
1310         cpuc->n_added  += n1;
1311         ctx->nr_active += n1;
1312
1313         /*
1314          * 1 means successful and events are active
1315          * This is not quite true because we defer
1316          * actual activation until hw_perf_enable() but
1317          * this way we* ensure caller won't try to enable
1318          * individual events
1319          */
1320         return 1;
1321 undo:
1322         x86_event_sched_out(leader, cpuctx);
1323         n0  = 1;
1324         list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1325                 if (sub->state == PERF_EVENT_STATE_ACTIVE) {
1326                         x86_event_sched_out(sub, cpuctx);
1327                         if (++n0 == n1)
1328                                 break;
1329                 }
1330         }
1331         return ret;
1332 }
1333
1334 #include "perf_event_amd.c"
1335 #include "perf_event_p6.c"
1336 #include "perf_event_p4.c"
1337 #include "perf_event_intel_lbr.c"
1338 #include "perf_event_intel_ds.c"
1339 #include "perf_event_intel.c"
1340
1341 static int __cpuinit
1342 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1343 {
1344         unsigned int cpu = (long)hcpu;
1345         int ret = NOTIFY_OK;
1346
1347         switch (action & ~CPU_TASKS_FROZEN) {
1348         case CPU_UP_PREPARE:
1349                 if (x86_pmu.cpu_prepare)
1350                         ret = x86_pmu.cpu_prepare(cpu);
1351                 break;
1352
1353         case CPU_STARTING:
1354                 if (x86_pmu.cpu_starting)
1355                         x86_pmu.cpu_starting(cpu);
1356                 break;
1357
1358         case CPU_DYING:
1359                 if (x86_pmu.cpu_dying)
1360                         x86_pmu.cpu_dying(cpu);
1361                 break;
1362
1363         case CPU_UP_CANCELED:
1364         case CPU_DEAD:
1365                 if (x86_pmu.cpu_dead)
1366                         x86_pmu.cpu_dead(cpu);
1367                 break;
1368
1369         default:
1370                 break;
1371         }
1372
1373         return ret;
1374 }
1375
1376 static void __init pmu_check_apic(void)
1377 {
1378         if (cpu_has_apic)
1379                 return;
1380
1381         x86_pmu.apic = 0;
1382         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1383         pr_info("no hardware sampling interrupt available.\n");
1384 }
1385
1386 void __init init_hw_perf_events(void)
1387 {
1388         struct event_constraint *c;
1389         int err;
1390
1391         pr_info("Performance Events: ");
1392
1393         switch (boot_cpu_data.x86_vendor) {
1394         case X86_VENDOR_INTEL:
1395                 err = intel_pmu_init();
1396                 break;
1397         case X86_VENDOR_AMD:
1398                 err = amd_pmu_init();
1399                 break;
1400         default:
1401                 return;
1402         }
1403         if (err != 0) {
1404                 pr_cont("no PMU driver, software events only.\n");
1405                 return;
1406         }
1407
1408         pmu_check_apic();
1409
1410         pr_cont("%s PMU driver.\n", x86_pmu.name);
1411
1412         if (x86_pmu.quirks)
1413                 x86_pmu.quirks();
1414
1415         if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1416                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1417                      x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1418                 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1419         }
1420         x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1421         perf_max_events = x86_pmu.num_counters;
1422
1423         if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1424                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1425                      x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1426                 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1427         }
1428
1429         x86_pmu.intel_ctrl |=
1430                 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1431
1432         perf_events_lapic_init();
1433         register_die_notifier(&perf_event_nmi_notifier);
1434
1435         unconstrained = (struct event_constraint)
1436                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1437                                    0, x86_pmu.num_counters);
1438
1439         if (x86_pmu.event_constraints) {
1440                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1441                         if (c->cmask != X86_RAW_EVENT_MASK)
1442                                 continue;
1443
1444                         c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1445                         c->weight += x86_pmu.num_counters;
1446                 }
1447         }
1448
1449         pr_info("... version:                %d\n",     x86_pmu.version);
1450         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1451         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1452         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1453         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1454         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1455         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1456
1457         perf_cpu_notifier(x86_pmu_notifier);
1458 }
1459
1460 static inline void x86_pmu_read(struct perf_event *event)
1461 {
1462         x86_perf_event_update(event);
1463 }
1464
1465 static const struct pmu pmu = {
1466         .enable         = x86_pmu_enable,
1467         .disable        = x86_pmu_disable,
1468         .start          = x86_pmu_start,
1469         .stop           = x86_pmu_stop,
1470         .read           = x86_pmu_read,
1471         .unthrottle     = x86_pmu_unthrottle,
1472 };
1473
1474 /*
1475  * validate that we can schedule this event
1476  */
1477 static int validate_event(struct perf_event *event)
1478 {
1479         struct cpu_hw_events *fake_cpuc;
1480         struct event_constraint *c;
1481         int ret = 0;
1482
1483         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1484         if (!fake_cpuc)
1485                 return -ENOMEM;
1486
1487         c = x86_pmu.get_event_constraints(fake_cpuc, event);
1488
1489         if (!c || !c->weight)
1490                 ret = -ENOSPC;
1491
1492         if (x86_pmu.put_event_constraints)
1493                 x86_pmu.put_event_constraints(fake_cpuc, event);
1494
1495         kfree(fake_cpuc);
1496
1497         return ret;
1498 }
1499
1500 /*
1501  * validate a single event group
1502  *
1503  * validation include:
1504  *      - check events are compatible which each other
1505  *      - events do not compete for the same counter
1506  *      - number of events <= number of counters
1507  *
1508  * validation ensures the group can be loaded onto the
1509  * PMU if it was the only group available.
1510  */
1511 static int validate_group(struct perf_event *event)
1512 {
1513         struct perf_event *leader = event->group_leader;
1514         struct cpu_hw_events *fake_cpuc;
1515         int ret, n;
1516
1517         ret = -ENOMEM;
1518         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1519         if (!fake_cpuc)
1520                 goto out;
1521
1522         /*
1523          * the event is not yet connected with its
1524          * siblings therefore we must first collect
1525          * existing siblings, then add the new event
1526          * before we can simulate the scheduling
1527          */
1528         ret = -ENOSPC;
1529         n = collect_events(fake_cpuc, leader, true);
1530         if (n < 0)
1531                 goto out_free;
1532
1533         fake_cpuc->n_events = n;
1534         n = collect_events(fake_cpuc, event, false);
1535         if (n < 0)
1536                 goto out_free;
1537
1538         fake_cpuc->n_events = n;
1539
1540         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1541
1542 out_free:
1543         kfree(fake_cpuc);
1544 out:
1545         return ret;
1546 }
1547
1548 const struct pmu *hw_perf_event_init(struct perf_event *event)
1549 {
1550         const struct pmu *tmp;
1551         int err;
1552
1553         err = __hw_perf_event_init(event);
1554         if (!err) {
1555                 /*
1556                  * we temporarily connect event to its pmu
1557                  * such that validate_group() can classify
1558                  * it as an x86 event using is_x86_event()
1559                  */
1560                 tmp = event->pmu;
1561                 event->pmu = &pmu;
1562
1563                 if (event->group_leader != event)
1564                         err = validate_group(event);
1565                 else
1566                         err = validate_event(event);
1567
1568                 event->pmu = tmp;
1569         }
1570         if (err) {
1571                 if (event->destroy)
1572                         event->destroy(event);
1573                 return ERR_PTR(err);
1574         }
1575
1576         return &pmu;
1577 }
1578
1579 /*
1580  * callchain support
1581  */
1582
1583 static inline
1584 void callchain_store(struct perf_callchain_entry *entry, u64 ip)
1585 {
1586         if (entry->nr < PERF_MAX_STACK_DEPTH)
1587                 entry->ip[entry->nr++] = ip;
1588 }
1589
1590 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
1591 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry);
1592
1593
1594 static void
1595 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1596 {
1597         /* Ignore warnings */
1598 }
1599
1600 static void backtrace_warning(void *data, char *msg)
1601 {
1602         /* Ignore warnings */
1603 }
1604
1605 static int backtrace_stack(void *data, char *name)
1606 {
1607         return 0;
1608 }
1609
1610 static void backtrace_address(void *data, unsigned long addr, int reliable)
1611 {
1612         struct perf_callchain_entry *entry = data;
1613
1614         callchain_store(entry, addr);
1615 }
1616
1617 static const struct stacktrace_ops backtrace_ops = {
1618         .warning                = backtrace_warning,
1619         .warning_symbol         = backtrace_warning_symbol,
1620         .stack                  = backtrace_stack,
1621         .address                = backtrace_address,
1622         .walk_stack             = print_context_stack_bp,
1623 };
1624
1625 #include "../dumpstack.h"
1626
1627 static void
1628 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1629 {
1630         callchain_store(entry, PERF_CONTEXT_KERNEL);
1631         callchain_store(entry, regs->ip);
1632
1633         dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
1634 }
1635
1636 #ifdef CONFIG_COMPAT
1637 static inline int
1638 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1639 {
1640         /* 32-bit process in 64-bit kernel. */
1641         struct stack_frame_ia32 frame;
1642         const void __user *fp;
1643
1644         if (!test_thread_flag(TIF_IA32))
1645                 return 0;
1646
1647         fp = compat_ptr(regs->bp);
1648         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1649                 unsigned long bytes;
1650                 frame.next_frame     = 0;
1651                 frame.return_address = 0;
1652
1653                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1654                 if (bytes != sizeof(frame))
1655                         break;
1656
1657                 if (fp < compat_ptr(regs->sp))
1658                         break;
1659
1660                 callchain_store(entry, frame.return_address);
1661                 fp = compat_ptr(frame.next_frame);
1662         }
1663         return 1;
1664 }
1665 #else
1666 static inline int
1667 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1668 {
1669     return 0;
1670 }
1671 #endif
1672
1673 static void
1674 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1675 {
1676         struct stack_frame frame;
1677         const void __user *fp;
1678
1679         if (!user_mode(regs))
1680                 regs = task_pt_regs(current);
1681
1682         fp = (void __user *)regs->bp;
1683
1684         callchain_store(entry, PERF_CONTEXT_USER);
1685         callchain_store(entry, regs->ip);
1686
1687         if (perf_callchain_user32(regs, entry))
1688                 return;
1689
1690         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1691                 unsigned long bytes;
1692                 frame.next_frame             = NULL;
1693                 frame.return_address = 0;
1694
1695                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1696                 if (bytes != sizeof(frame))
1697                         break;
1698
1699                 if ((unsigned long)fp < regs->sp)
1700                         break;
1701
1702                 callchain_store(entry, frame.return_address);
1703                 fp = frame.next_frame;
1704         }
1705 }
1706
1707 static void
1708 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1709 {
1710         int is_user;
1711
1712         if (!regs)
1713                 return;
1714
1715         is_user = user_mode(regs);
1716
1717         if (is_user && current->state != TASK_RUNNING)
1718                 return;
1719
1720         if (!is_user)
1721                 perf_callchain_kernel(regs, entry);
1722
1723         if (current->mm)
1724                 perf_callchain_user(regs, entry);
1725 }
1726
1727 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1728 {
1729         struct perf_callchain_entry *entry;
1730
1731         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1732                 /* TODO: We don't support guest os callchain now */
1733                 return NULL;
1734         }
1735
1736         if (in_nmi())
1737                 entry = &__get_cpu_var(pmc_nmi_entry);
1738         else
1739                 entry = &__get_cpu_var(pmc_irq_entry);
1740
1741         entry->nr = 0;
1742
1743         perf_do_callchain(regs, entry);
1744
1745         return entry;
1746 }
1747
1748 void perf_arch_fetch_caller_regs(struct pt_regs *regs, unsigned long ip, int skip)
1749 {
1750         regs->ip = ip;
1751         /*
1752          * perf_arch_fetch_caller_regs adds another call, we need to increment
1753          * the skip level
1754          */
1755         regs->bp = rewind_frame_pointer(skip + 1);
1756         regs->cs = __KERNEL_CS;
1757         local_save_flags(regs->flags);
1758 }
1759
1760 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1761 {
1762         unsigned long ip;
1763
1764         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1765                 ip = perf_guest_cbs->get_guest_ip();
1766         else
1767                 ip = instruction_pointer(regs);
1768
1769         return ip;
1770 }
1771
1772 unsigned long perf_misc_flags(struct pt_regs *regs)
1773 {
1774         int misc = 0;
1775
1776         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1777                 if (perf_guest_cbs->is_user_mode())
1778                         misc |= PERF_RECORD_MISC_GUEST_USER;
1779                 else
1780                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1781         } else {
1782                 if (user_mode(regs))
1783                         misc |= PERF_RECORD_MISC_USER;
1784                 else
1785                         misc |= PERF_RECORD_MISC_KERNEL;
1786         }
1787
1788         if (regs->flags & PERF_EFLAGS_EXACT)
1789                 misc |= PERF_RECORD_MISC_EXACT;
1790
1791         return misc;
1792 }