2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/highmem.h>
26 #include <linux/cpu.h>
27 #include <linux/bitops.h>
30 #include <asm/stacktrace.h>
32 #include <asm/compat.h>
36 #define wrmsrl(msr, val) \
38 trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
39 (unsigned long)(val)); \
40 native_write_msr((msr), (u32)((u64)(val)), \
41 (u32)((u64)(val) >> 32)); \
46 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
49 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
51 unsigned long offset, addr = (unsigned long)from;
52 int type = in_nmi() ? KM_NMI : KM_IRQ0;
53 unsigned long size, len = 0;
59 ret = __get_user_pages_fast(addr, 1, 0, &page);
63 offset = addr & (PAGE_SIZE - 1);
64 size = min(PAGE_SIZE - offset, n - len);
66 map = kmap_atomic(page, type);
67 memcpy(to, map+offset, size);
68 kunmap_atomic(map, type);
80 struct event_constraint {
82 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
91 int nb_id; /* NorthBridge id */
92 int refcnt; /* reference count */
93 struct perf_event *owners[X86_PMC_IDX_MAX];
94 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
97 #define MAX_LBR_ENTRIES 16
99 struct cpu_hw_events {
101 * Generic x86 PMC bits
103 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
104 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
109 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
110 u64 tags[X86_PMC_IDX_MAX];
111 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
114 * Intel DebugStore bits
116 struct debug_store *ds;
124 struct perf_branch_stack lbr_stack;
125 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
130 struct amd_nb *amd_nb;
133 #define __EVENT_CONSTRAINT(c, n, m, w) {\
134 { .idxmsk64 = (n) }, \
140 #define EVENT_CONSTRAINT(c, n, m) \
141 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
144 * Constraint on the Event code.
146 #define INTEL_EVENT_CONSTRAINT(c, n) \
147 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
150 * Constraint on the Event code + UMask + fixed-mask
152 * filter mask to validate fixed counter events.
153 * the following filters disqualify for fixed counters:
157 * The other filters are supported by fixed counters.
158 * The any-thread option is supported starting with v3.
160 #define FIXED_EVENT_CONSTRAINT(c, n) \
161 EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
164 * Constraint on the Event code + UMask
166 #define PEBS_EVENT_CONSTRAINT(c, n) \
167 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
169 #define EVENT_CONSTRAINT_END \
170 EVENT_CONSTRAINT(0, 0, 0)
172 #define for_each_event_constraint(e, c) \
173 for ((e) = (c); (e)->cmask; (e)++)
175 union perf_capabilities {
179 u64 pebs_arch_reg : 1;
187 * struct x86_pmu - generic x86 pmu
191 * Generic x86 PMC bits
195 int (*handle_irq)(struct pt_regs *);
196 void (*disable_all)(void);
197 void (*enable_all)(int added);
198 void (*enable)(struct perf_event *);
199 void (*disable)(struct perf_event *);
200 int (*hw_config)(struct perf_event *event);
201 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
204 u64 (*event_map)(int);
207 int num_counters_fixed;
212 struct event_constraint *
213 (*get_event_constraints)(struct cpu_hw_events *cpuc,
214 struct perf_event *event);
216 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
217 struct perf_event *event);
218 struct event_constraint *event_constraints;
219 void (*quirks)(void);
221 int (*cpu_prepare)(int cpu);
222 void (*cpu_starting)(int cpu);
223 void (*cpu_dying)(int cpu);
224 void (*cpu_dead)(int cpu);
227 * Intel Arch Perfmon v2+
230 union perf_capabilities intel_cap;
233 * Intel DebugStore bits
236 int pebs_record_size;
237 void (*drain_pebs)(struct pt_regs *regs);
238 struct event_constraint *pebs_constraints;
243 unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
244 int lbr_nr; /* hardware stack size */
247 static struct x86_pmu x86_pmu __read_mostly;
249 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
253 static int x86_perf_event_set_period(struct perf_event *event);
256 * Generalized hw caching related hw_event table, filled
257 * in on a per model basis. A value of 0 means
258 * 'not supported', -1 means 'hw_event makes no sense on
259 * this CPU', any other value means the raw hw_event
263 #define C(x) PERF_COUNT_HW_CACHE_##x
265 static u64 __read_mostly hw_cache_event_ids
266 [PERF_COUNT_HW_CACHE_MAX]
267 [PERF_COUNT_HW_CACHE_OP_MAX]
268 [PERF_COUNT_HW_CACHE_RESULT_MAX];
271 * Propagate event elapsed time into the generic event.
272 * Can only be executed on the CPU where the event is active.
273 * Returns the delta events processed.
276 x86_perf_event_update(struct perf_event *event)
278 struct hw_perf_event *hwc = &event->hw;
279 int shift = 64 - x86_pmu.cntval_bits;
280 u64 prev_raw_count, new_raw_count;
284 if (idx == X86_PMC_IDX_FIXED_BTS)
288 * Careful: an NMI might modify the previous event value.
290 * Our tactic to handle this is to first atomically read and
291 * exchange a new raw count - then add that new-prev delta
292 * count to the generic event atomically:
295 prev_raw_count = atomic64_read(&hwc->prev_count);
296 rdmsrl(hwc->event_base + idx, new_raw_count);
298 if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
299 new_raw_count) != prev_raw_count)
303 * Now we have the new raw value and have updated the prev
304 * timestamp already. We can now calculate the elapsed delta
305 * (event-)time and add that to the generic event.
307 * Careful, not all hw sign-extends above the physical width
310 delta = (new_raw_count << shift) - (prev_raw_count << shift);
313 atomic64_add(delta, &event->count);
314 atomic64_sub(delta, &hwc->period_left);
316 return new_raw_count;
319 static atomic_t active_events;
320 static DEFINE_MUTEX(pmc_reserve_mutex);
322 #ifdef CONFIG_X86_LOCAL_APIC
324 static bool reserve_pmc_hardware(void)
328 if (nmi_watchdog == NMI_LOCAL_APIC)
329 disable_lapic_nmi_watchdog();
331 for (i = 0; i < x86_pmu.num_counters; i++) {
332 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
336 for (i = 0; i < x86_pmu.num_counters; i++) {
337 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
344 for (i--; i >= 0; i--)
345 release_evntsel_nmi(x86_pmu.eventsel + i);
347 i = x86_pmu.num_counters;
350 for (i--; i >= 0; i--)
351 release_perfctr_nmi(x86_pmu.perfctr + i);
353 if (nmi_watchdog == NMI_LOCAL_APIC)
354 enable_lapic_nmi_watchdog();
359 static void release_pmc_hardware(void)
363 for (i = 0; i < x86_pmu.num_counters; i++) {
364 release_perfctr_nmi(x86_pmu.perfctr + i);
365 release_evntsel_nmi(x86_pmu.eventsel + i);
368 if (nmi_watchdog == NMI_LOCAL_APIC)
369 enable_lapic_nmi_watchdog();
374 static bool reserve_pmc_hardware(void) { return true; }
375 static void release_pmc_hardware(void) {}
379 static int reserve_ds_buffers(void);
380 static void release_ds_buffers(void);
382 static void hw_perf_event_destroy(struct perf_event *event)
384 if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
385 release_pmc_hardware();
386 release_ds_buffers();
387 mutex_unlock(&pmc_reserve_mutex);
391 static inline int x86_pmu_initialized(void)
393 return x86_pmu.handle_irq != NULL;
397 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
399 unsigned int cache_type, cache_op, cache_result;
402 config = attr->config;
404 cache_type = (config >> 0) & 0xff;
405 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
408 cache_op = (config >> 8) & 0xff;
409 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
412 cache_result = (config >> 16) & 0xff;
413 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
416 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
429 static int x86_pmu_hw_config(struct perf_event *event)
433 * (keep 'enabled' bit clear for now)
435 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
438 * Count user and OS events unless requested not to
440 if (!event->attr.exclude_user)
441 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
442 if (!event->attr.exclude_kernel)
443 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
445 if (event->attr.type == PERF_TYPE_RAW)
446 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
452 * Setup the hardware configuration for a given attr_type
454 static int __hw_perf_event_init(struct perf_event *event)
456 struct perf_event_attr *attr = &event->attr;
457 struct hw_perf_event *hwc = &event->hw;
461 if (!x86_pmu_initialized())
465 if (!atomic_inc_not_zero(&active_events)) {
466 mutex_lock(&pmc_reserve_mutex);
467 if (atomic_read(&active_events) == 0) {
468 if (!reserve_pmc_hardware())
471 err = reserve_ds_buffers();
473 release_pmc_hardware();
477 atomic_inc(&active_events);
478 mutex_unlock(&pmc_reserve_mutex);
483 event->destroy = hw_perf_event_destroy;
487 hwc->last_tag = ~0ULL;
489 /* Processor specifics */
490 err = x86_pmu.hw_config(event);
494 if (!hwc->sample_period) {
495 hwc->sample_period = x86_pmu.max_period;
496 hwc->last_period = hwc->sample_period;
497 atomic64_set(&hwc->period_left, hwc->sample_period);
500 * If we have a PMU initialized but no APIC
501 * interrupts, we cannot sample hardware
502 * events (user-space has to fall back and
503 * sample via a hrtimer based software event):
509 if (attr->type == PERF_TYPE_RAW)
512 if (attr->type == PERF_TYPE_HW_CACHE)
513 return set_ext_hw_attr(hwc, attr);
515 if (attr->config >= x86_pmu.max_events)
521 config = x86_pmu.event_map(attr->config);
532 if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
533 (hwc->sample_period == 1)) {
534 /* BTS is not supported by this architecture. */
538 /* BTS is currently only allowed for user-mode. */
539 if (!attr->exclude_kernel)
543 hwc->config |= config;
548 static void x86_pmu_disable_all(void)
550 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
553 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
556 if (!test_bit(idx, cpuc->active_mask))
558 rdmsrl(x86_pmu.eventsel + idx, val);
559 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
561 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
562 wrmsrl(x86_pmu.eventsel + idx, val);
566 void hw_perf_disable(void)
568 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
570 if (!x86_pmu_initialized())
580 x86_pmu.disable_all();
583 static void x86_pmu_enable_all(int added)
585 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
588 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
589 struct perf_event *event = cpuc->events[idx];
592 if (!test_bit(idx, cpuc->active_mask))
595 val = event->hw.config;
596 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
597 wrmsrl(x86_pmu.eventsel + idx, val);
601 static const struct pmu pmu;
603 static inline int is_x86_event(struct perf_event *event)
605 return event->pmu == &pmu;
608 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
610 struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
611 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
612 int i, j, w, wmax, num = 0;
613 struct hw_perf_event *hwc;
615 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
617 for (i = 0; i < n; i++) {
618 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
623 * fastpath, try to reuse previous register
625 for (i = 0; i < n; i++) {
626 hwc = &cpuc->event_list[i]->hw;
633 /* constraint still honored */
634 if (!test_bit(hwc->idx, c->idxmsk))
637 /* not already used */
638 if (test_bit(hwc->idx, used_mask))
641 __set_bit(hwc->idx, used_mask);
643 assign[i] = hwc->idx;
652 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
655 * weight = number of possible counters
657 * 1 = most constrained, only works on one counter
658 * wmax = least constrained, works on any counter
660 * assign events to counters starting with most
661 * constrained events.
663 wmax = x86_pmu.num_counters;
666 * when fixed event counters are present,
667 * wmax is incremented by 1 to account
668 * for one more choice
670 if (x86_pmu.num_counters_fixed)
673 for (w = 1, num = n; num && w <= wmax; w++) {
675 for (i = 0; num && i < n; i++) {
677 hwc = &cpuc->event_list[i]->hw;
682 for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
683 if (!test_bit(j, used_mask))
687 if (j == X86_PMC_IDX_MAX)
690 __set_bit(j, used_mask);
699 * scheduling failed or is just a simulation,
700 * free resources if necessary
702 if (!assign || num) {
703 for (i = 0; i < n; i++) {
704 if (x86_pmu.put_event_constraints)
705 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
708 return num ? -ENOSPC : 0;
712 * dogrp: true if must collect siblings events (group)
713 * returns total number of events and error code
715 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
717 struct perf_event *event;
720 max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
722 /* current number of events already accepted */
725 if (is_x86_event(leader)) {
728 cpuc->event_list[n] = leader;
734 list_for_each_entry(event, &leader->sibling_list, group_entry) {
735 if (!is_x86_event(event) ||
736 event->state <= PERF_EVENT_STATE_OFF)
742 cpuc->event_list[n] = event;
748 static inline void x86_assign_hw_event(struct perf_event *event,
749 struct cpu_hw_events *cpuc, int i)
751 struct hw_perf_event *hwc = &event->hw;
753 hwc->idx = cpuc->assign[i];
754 hwc->last_cpu = smp_processor_id();
755 hwc->last_tag = ++cpuc->tags[i];
757 if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
758 hwc->config_base = 0;
760 } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
761 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
763 * We set it so that event_base + idx in wrmsr/rdmsr maps to
764 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
767 MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
769 hwc->config_base = x86_pmu.eventsel;
770 hwc->event_base = x86_pmu.perfctr;
774 static inline int match_prev_assignment(struct hw_perf_event *hwc,
775 struct cpu_hw_events *cpuc,
778 return hwc->idx == cpuc->assign[i] &&
779 hwc->last_cpu == smp_processor_id() &&
780 hwc->last_tag == cpuc->tags[i];
783 static int x86_pmu_start(struct perf_event *event);
784 static void x86_pmu_stop(struct perf_event *event);
786 void hw_perf_enable(void)
788 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
789 struct perf_event *event;
790 struct hw_perf_event *hwc;
791 int i, added = cpuc->n_added;
793 if (!x86_pmu_initialized())
800 int n_running = cpuc->n_events - cpuc->n_added;
802 * apply assignment obtained either from
803 * hw_perf_group_sched_in() or x86_pmu_enable()
805 * step1: save events moving to new counters
806 * step2: reprogram moved events into new counters
808 for (i = 0; i < n_running; i++) {
809 event = cpuc->event_list[i];
813 * we can avoid reprogramming counter if:
814 * - assigned same counter as last time
815 * - running on same CPU as last time
816 * - no other event has used the counter since
818 if (hwc->idx == -1 ||
819 match_prev_assignment(hwc, cpuc, i))
825 for (i = 0; i < cpuc->n_events; i++) {
826 event = cpuc->event_list[i];
829 if (!match_prev_assignment(hwc, cpuc, i))
830 x86_assign_hw_event(event, cpuc, i);
831 else if (i < n_running)
834 x86_pmu_start(event);
837 perf_events_lapic_init();
843 x86_pmu.enable_all(added);
846 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc)
848 wrmsrl(hwc->config_base + hwc->idx,
849 hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE);
852 static inline void x86_pmu_disable_event(struct perf_event *event)
854 struct hw_perf_event *hwc = &event->hw;
856 wrmsrl(hwc->config_base + hwc->idx, hwc->config);
859 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
862 * Set the next IRQ period, based on the hwc->period_left value.
863 * To be called with the event disabled in hw:
866 x86_perf_event_set_period(struct perf_event *event)
868 struct hw_perf_event *hwc = &event->hw;
869 s64 left = atomic64_read(&hwc->period_left);
870 s64 period = hwc->sample_period;
871 int ret = 0, idx = hwc->idx;
873 if (idx == X86_PMC_IDX_FIXED_BTS)
877 * If we are way outside a reasonable range then just skip forward:
879 if (unlikely(left <= -period)) {
881 atomic64_set(&hwc->period_left, left);
882 hwc->last_period = period;
886 if (unlikely(left <= 0)) {
888 atomic64_set(&hwc->period_left, left);
889 hwc->last_period = period;
893 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
895 if (unlikely(left < 2))
898 if (left > x86_pmu.max_period)
899 left = x86_pmu.max_period;
901 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
904 * The hw event starts counting from this event offset,
905 * mark it to be able to extra future deltas:
907 atomic64_set(&hwc->prev_count, (u64)-left);
909 wrmsrl(hwc->event_base + idx,
910 (u64)(-left) & x86_pmu.cntval_mask);
912 perf_event_update_userpage(event);
917 static void x86_pmu_enable_event(struct perf_event *event)
919 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
921 __x86_pmu_enable_event(&event->hw);
925 * activate a single event
927 * The event is added to the group of enabled events
928 * but only if it can be scehduled with existing events.
930 * Called with PMU disabled. If successful and return value 1,
931 * then guaranteed to call perf_enable() and hw_perf_enable()
933 static int x86_pmu_enable(struct perf_event *event)
935 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
936 struct hw_perf_event *hwc;
937 int assign[X86_PMC_IDX_MAX];
943 n = collect_events(cpuc, event, false);
947 ret = x86_pmu.schedule_events(cpuc, n, assign);
951 * copy new assignment, now we know it is possible
952 * will be used by hw_perf_enable()
954 memcpy(cpuc->assign, assign, n*sizeof(int));
957 cpuc->n_added += n - n0;
962 static int x86_pmu_start(struct perf_event *event)
964 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
965 int idx = event->hw.idx;
970 x86_perf_event_set_period(event);
971 cpuc->events[idx] = event;
972 __set_bit(idx, cpuc->active_mask);
973 x86_pmu.enable(event);
974 perf_event_update_userpage(event);
979 static void x86_pmu_unthrottle(struct perf_event *event)
981 int ret = x86_pmu_start(event);
985 void perf_event_print_debug(void)
987 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
989 struct cpu_hw_events *cpuc;
993 if (!x86_pmu.num_counters)
996 local_irq_save(flags);
998 cpu = smp_processor_id();
999 cpuc = &per_cpu(cpu_hw_events, cpu);
1001 if (x86_pmu.version >= 2) {
1002 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1003 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1004 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1005 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1006 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1009 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1010 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1011 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1012 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1013 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1015 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1017 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1018 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1019 rdmsrl(x86_pmu.perfctr + idx, pmc_count);
1021 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1023 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1024 cpu, idx, pmc_ctrl);
1025 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1026 cpu, idx, pmc_count);
1027 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1028 cpu, idx, prev_left);
1030 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1031 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1033 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1034 cpu, idx, pmc_count);
1036 local_irq_restore(flags);
1039 static void x86_pmu_stop(struct perf_event *event)
1041 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1042 struct hw_perf_event *hwc = &event->hw;
1045 if (!__test_and_clear_bit(idx, cpuc->active_mask))
1048 x86_pmu.disable(event);
1051 * Drain the remaining delta count out of a event
1052 * that we are disabling:
1054 x86_perf_event_update(event);
1056 cpuc->events[idx] = NULL;
1059 static void x86_pmu_disable(struct perf_event *event)
1061 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1064 x86_pmu_stop(event);
1066 for (i = 0; i < cpuc->n_events; i++) {
1067 if (event == cpuc->event_list[i]) {
1069 if (x86_pmu.put_event_constraints)
1070 x86_pmu.put_event_constraints(cpuc, event);
1072 while (++i < cpuc->n_events)
1073 cpuc->event_list[i-1] = cpuc->event_list[i];
1079 perf_event_update_userpage(event);
1082 static int x86_pmu_handle_irq(struct pt_regs *regs)
1084 struct perf_sample_data data;
1085 struct cpu_hw_events *cpuc;
1086 struct perf_event *event;
1087 struct hw_perf_event *hwc;
1088 int idx, handled = 0;
1091 perf_sample_data_init(&data, 0);
1093 cpuc = &__get_cpu_var(cpu_hw_events);
1095 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1096 if (!test_bit(idx, cpuc->active_mask))
1099 event = cpuc->events[idx];
1102 val = x86_perf_event_update(event);
1103 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1110 data.period = event->hw.last_period;
1112 if (!x86_perf_event_set_period(event))
1115 if (perf_event_overflow(event, 1, &data, regs))
1116 x86_pmu_stop(event);
1120 inc_irq_stat(apic_perf_irqs);
1125 void smp_perf_pending_interrupt(struct pt_regs *regs)
1129 inc_irq_stat(apic_pending_irqs);
1130 perf_event_do_pending();
1134 void set_perf_event_pending(void)
1136 #ifdef CONFIG_X86_LOCAL_APIC
1137 if (!x86_pmu.apic || !x86_pmu_initialized())
1140 apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1144 void perf_events_lapic_init(void)
1146 if (!x86_pmu.apic || !x86_pmu_initialized())
1150 * Always use NMI for PMU
1152 apic_write(APIC_LVTPC, APIC_DM_NMI);
1155 static int __kprobes
1156 perf_event_nmi_handler(struct notifier_block *self,
1157 unsigned long cmd, void *__args)
1159 struct die_args *args = __args;
1160 struct pt_regs *regs;
1162 if (!atomic_read(&active_events))
1176 apic_write(APIC_LVTPC, APIC_DM_NMI);
1178 * Can't rely on the handled return value to say it was our NMI, two
1179 * events could trigger 'simultaneously' raising two back-to-back NMIs.
1181 * If the first NMI handles both, the latter will be empty and daze
1184 x86_pmu.handle_irq(regs);
1189 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1190 .notifier_call = perf_event_nmi_handler,
1195 static struct event_constraint unconstrained;
1196 static struct event_constraint emptyconstraint;
1198 static struct event_constraint *
1199 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1201 struct event_constraint *c;
1203 if (x86_pmu.event_constraints) {
1204 for_each_event_constraint(c, x86_pmu.event_constraints) {
1205 if ((event->hw.config & c->cmask) == c->code)
1210 return &unconstrained;
1213 static int x86_event_sched_in(struct perf_event *event,
1214 struct perf_cpu_context *cpuctx)
1218 event->state = PERF_EVENT_STATE_ACTIVE;
1219 event->oncpu = smp_processor_id();
1220 event->tstamp_running += event->ctx->time - event->tstamp_stopped;
1222 if (!is_x86_event(event))
1223 ret = event->pmu->enable(event);
1225 if (!ret && !is_software_event(event))
1226 cpuctx->active_oncpu++;
1228 if (!ret && event->attr.exclusive)
1229 cpuctx->exclusive = 1;
1234 static void x86_event_sched_out(struct perf_event *event,
1235 struct perf_cpu_context *cpuctx)
1237 event->state = PERF_EVENT_STATE_INACTIVE;
1240 if (!is_x86_event(event))
1241 event->pmu->disable(event);
1243 event->tstamp_running -= event->ctx->time - event->tstamp_stopped;
1245 if (!is_software_event(event))
1246 cpuctx->active_oncpu--;
1248 if (event->attr.exclusive || !cpuctx->active_oncpu)
1249 cpuctx->exclusive = 0;
1253 * Called to enable a whole group of events.
1254 * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
1255 * Assumes the caller has disabled interrupts and has
1256 * frozen the PMU with hw_perf_save_disable.
1258 * called with PMU disabled. If successful and return value 1,
1259 * then guaranteed to call perf_enable() and hw_perf_enable()
1261 int hw_perf_group_sched_in(struct perf_event *leader,
1262 struct perf_cpu_context *cpuctx,
1263 struct perf_event_context *ctx)
1265 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1266 struct perf_event *sub;
1267 int assign[X86_PMC_IDX_MAX];
1270 if (!x86_pmu_initialized())
1273 /* n0 = total number of events */
1274 n0 = collect_events(cpuc, leader, true);
1278 ret = x86_pmu.schedule_events(cpuc, n0, assign);
1282 ret = x86_event_sched_in(leader, cpuctx);
1287 list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1288 if (sub->state > PERF_EVENT_STATE_OFF) {
1289 ret = x86_event_sched_in(sub, cpuctx);
1296 * copy new assignment, now we know it is possible
1297 * will be used by hw_perf_enable()
1299 memcpy(cpuc->assign, assign, n0*sizeof(int));
1301 cpuc->n_events = n0;
1302 cpuc->n_added += n1;
1303 ctx->nr_active += n1;
1306 * 1 means successful and events are active
1307 * This is not quite true because we defer
1308 * actual activation until hw_perf_enable() but
1309 * this way we* ensure caller won't try to enable
1314 x86_event_sched_out(leader, cpuctx);
1316 list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1317 if (sub->state == PERF_EVENT_STATE_ACTIVE) {
1318 x86_event_sched_out(sub, cpuctx);
1326 #include "perf_event_amd.c"
1327 #include "perf_event_p6.c"
1328 #include "perf_event_p4.c"
1329 #include "perf_event_intel_lbr.c"
1330 #include "perf_event_intel_ds.c"
1331 #include "perf_event_intel.c"
1333 static int __cpuinit
1334 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1336 unsigned int cpu = (long)hcpu;
1337 int ret = NOTIFY_OK;
1339 switch (action & ~CPU_TASKS_FROZEN) {
1340 case CPU_UP_PREPARE:
1341 if (x86_pmu.cpu_prepare)
1342 ret = x86_pmu.cpu_prepare(cpu);
1346 if (x86_pmu.cpu_starting)
1347 x86_pmu.cpu_starting(cpu);
1351 if (x86_pmu.cpu_dying)
1352 x86_pmu.cpu_dying(cpu);
1355 case CPU_UP_CANCELED:
1357 if (x86_pmu.cpu_dead)
1358 x86_pmu.cpu_dead(cpu);
1368 static void __init pmu_check_apic(void)
1374 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1375 pr_info("no hardware sampling interrupt available.\n");
1378 void __init init_hw_perf_events(void)
1380 struct event_constraint *c;
1383 pr_info("Performance Events: ");
1385 switch (boot_cpu_data.x86_vendor) {
1386 case X86_VENDOR_INTEL:
1387 err = intel_pmu_init();
1389 case X86_VENDOR_AMD:
1390 err = amd_pmu_init();
1396 pr_cont("no PMU driver, software events only.\n");
1402 pr_cont("%s PMU driver.\n", x86_pmu.name);
1407 if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1408 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1409 x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1410 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1412 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1413 perf_max_events = x86_pmu.num_counters;
1415 if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1416 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1417 x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1418 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1421 x86_pmu.intel_ctrl |=
1422 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1424 perf_events_lapic_init();
1425 register_die_notifier(&perf_event_nmi_notifier);
1427 unconstrained = (struct event_constraint)
1428 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1429 0, x86_pmu.num_counters);
1431 if (x86_pmu.event_constraints) {
1432 for_each_event_constraint(c, x86_pmu.event_constraints) {
1433 if (c->cmask != X86_RAW_EVENT_MASK)
1436 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1437 c->weight += x86_pmu.num_counters;
1441 pr_info("... version: %d\n", x86_pmu.version);
1442 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
1443 pr_info("... generic registers: %d\n", x86_pmu.num_counters);
1444 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
1445 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1446 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed);
1447 pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl);
1449 perf_cpu_notifier(x86_pmu_notifier);
1452 static inline void x86_pmu_read(struct perf_event *event)
1454 x86_perf_event_update(event);
1457 static const struct pmu pmu = {
1458 .enable = x86_pmu_enable,
1459 .disable = x86_pmu_disable,
1460 .start = x86_pmu_start,
1461 .stop = x86_pmu_stop,
1462 .read = x86_pmu_read,
1463 .unthrottle = x86_pmu_unthrottle,
1467 * validate that we can schedule this event
1469 static int validate_event(struct perf_event *event)
1471 struct cpu_hw_events *fake_cpuc;
1472 struct event_constraint *c;
1475 fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1479 c = x86_pmu.get_event_constraints(fake_cpuc, event);
1481 if (!c || !c->weight)
1484 if (x86_pmu.put_event_constraints)
1485 x86_pmu.put_event_constraints(fake_cpuc, event);
1493 * validate a single event group
1495 * validation include:
1496 * - check events are compatible which each other
1497 * - events do not compete for the same counter
1498 * - number of events <= number of counters
1500 * validation ensures the group can be loaded onto the
1501 * PMU if it was the only group available.
1503 static int validate_group(struct perf_event *event)
1505 struct perf_event *leader = event->group_leader;
1506 struct cpu_hw_events *fake_cpuc;
1510 fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1515 * the event is not yet connected with its
1516 * siblings therefore we must first collect
1517 * existing siblings, then add the new event
1518 * before we can simulate the scheduling
1521 n = collect_events(fake_cpuc, leader, true);
1525 fake_cpuc->n_events = n;
1526 n = collect_events(fake_cpuc, event, false);
1530 fake_cpuc->n_events = n;
1532 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1540 const struct pmu *hw_perf_event_init(struct perf_event *event)
1542 const struct pmu *tmp;
1545 err = __hw_perf_event_init(event);
1548 * we temporarily connect event to its pmu
1549 * such that validate_group() can classify
1550 * it as an x86 event using is_x86_event()
1555 if (event->group_leader != event)
1556 err = validate_group(event);
1558 err = validate_event(event);
1564 event->destroy(event);
1565 return ERR_PTR(err);
1576 void callchain_store(struct perf_callchain_entry *entry, u64 ip)
1578 if (entry->nr < PERF_MAX_STACK_DEPTH)
1579 entry->ip[entry->nr++] = ip;
1582 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
1583 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry);
1587 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1589 /* Ignore warnings */
1592 static void backtrace_warning(void *data, char *msg)
1594 /* Ignore warnings */
1597 static int backtrace_stack(void *data, char *name)
1602 static void backtrace_address(void *data, unsigned long addr, int reliable)
1604 struct perf_callchain_entry *entry = data;
1606 callchain_store(entry, addr);
1609 static const struct stacktrace_ops backtrace_ops = {
1610 .warning = backtrace_warning,
1611 .warning_symbol = backtrace_warning_symbol,
1612 .stack = backtrace_stack,
1613 .address = backtrace_address,
1614 .walk_stack = print_context_stack_bp,
1617 #include "../dumpstack.h"
1620 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1622 callchain_store(entry, PERF_CONTEXT_KERNEL);
1623 callchain_store(entry, regs->ip);
1625 dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
1628 #ifdef CONFIG_COMPAT
1630 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1632 /* 32-bit process in 64-bit kernel. */
1633 struct stack_frame_ia32 frame;
1634 const void __user *fp;
1636 if (!test_thread_flag(TIF_IA32))
1639 fp = compat_ptr(regs->bp);
1640 while (entry->nr < PERF_MAX_STACK_DEPTH) {
1641 unsigned long bytes;
1642 frame.next_frame = 0;
1643 frame.return_address = 0;
1645 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1646 if (bytes != sizeof(frame))
1649 if (fp < compat_ptr(regs->sp))
1652 callchain_store(entry, frame.return_address);
1653 fp = compat_ptr(frame.next_frame);
1659 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1666 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1668 struct stack_frame frame;
1669 const void __user *fp;
1671 if (!user_mode(regs))
1672 regs = task_pt_regs(current);
1674 fp = (void __user *)regs->bp;
1676 callchain_store(entry, PERF_CONTEXT_USER);
1677 callchain_store(entry, regs->ip);
1679 if (perf_callchain_user32(regs, entry))
1682 while (entry->nr < PERF_MAX_STACK_DEPTH) {
1683 unsigned long bytes;
1684 frame.next_frame = NULL;
1685 frame.return_address = 0;
1687 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1688 if (bytes != sizeof(frame))
1691 if ((unsigned long)fp < regs->sp)
1694 callchain_store(entry, frame.return_address);
1695 fp = frame.next_frame;
1700 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1707 is_user = user_mode(regs);
1709 if (is_user && current->state != TASK_RUNNING)
1713 perf_callchain_kernel(regs, entry);
1716 perf_callchain_user(regs, entry);
1719 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1721 struct perf_callchain_entry *entry;
1723 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1724 /* TODO: We don't support guest os callchain now */
1729 entry = &__get_cpu_var(pmc_nmi_entry);
1731 entry = &__get_cpu_var(pmc_irq_entry);
1735 perf_do_callchain(regs, entry);
1740 void perf_arch_fetch_caller_regs(struct pt_regs *regs, unsigned long ip, int skip)
1744 * perf_arch_fetch_caller_regs adds another call, we need to increment
1747 regs->bp = rewind_frame_pointer(skip + 1);
1748 regs->cs = __KERNEL_CS;
1749 local_save_flags(regs->flags);
1752 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1755 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1756 ip = perf_guest_cbs->get_guest_ip();
1758 ip = instruction_pointer(regs);
1762 unsigned long perf_misc_flags(struct pt_regs *regs)
1765 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1766 misc |= perf_guest_cbs->is_user_mode() ?
1767 PERF_RECORD_MISC_GUEST_USER :
1768 PERF_RECORD_MISC_GUEST_KERNEL;
1770 misc |= user_mode(regs) ? PERF_RECORD_MISC_USER :
1771 PERF_RECORD_MISC_KERNEL;
1772 if (regs->flags & PERF_EFLAGS_EXACT)
1773 misc |= PERF_RECORD_MISC_EXACT;