arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/highmem.h>
  26 #include <linux/cpu.h>
  27 #include <linux/bitops.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/compat.h>
  33 #include <asm/smp.h>
  34
  35 #if 0
  36 #undef wrmsrl
  37 #define wrmsrl(msr, val)                                        \
  38 do {                                                            \
  39         trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
  40                         (unsigned long)(val));                  \
  41         native_write_msr((msr), (u32)((u64)(val)),              \
  42                         (u32)((u64)(val) >> 32));               \
  43 } while (0)
  44 #endif
  45
  46 /*
  47  * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
  48  */
  49 static unsigned long
  50 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
  51 {
  52         unsigned long offset, addr = (unsigned long)from;
  53         unsigned long size, len = 0;
  54         struct page *page;
  55         void *map;
  56         int ret;
  57
  58         do {
  59                 ret = __get_user_pages_fast(addr, 1, 0, &page);
  60                 if (!ret)
  61                         break;
  62
  63                 offset = addr & (PAGE_SIZE - 1);
  64                 size = min(PAGE_SIZE - offset, n - len);
  65
  66                 map = kmap_atomic(page);
  67                 memcpy(to, map+offset, size);
  68                 kunmap_atomic(map);
  69                 put_page(page);
  70
  71                 len  += size;
  72                 to   += size;
  73                 addr += size;
  74
  75         } while (len < n);
  76
  77         return len;
  78 }
  79
  80 struct event_constraint {
  81         union {
  82                 unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  83                 u64             idxmsk64;
  84         };
  85         u64     code;
  86         u64     cmask;
  87         int     weight;
  88 };
  89
  90 struct amd_nb {
  91         int nb_id;  /* NorthBridge id */
  92         int refcnt; /* reference count */
  93         struct perf_event *owners[X86_PMC_IDX_MAX];
  94         struct event_constraint event_constraints[X86_PMC_IDX_MAX];
  95 };
  96
  97 struct intel_percore;
  98
  99 #define MAX_LBR_ENTRIES         16
 100
 101 struct cpu_hw_events {
 102         /*
 103          * Generic x86 PMC bits
 104          */
 105         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
 106         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 107         unsigned long           running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 108         int                     enabled;
 109
 110         int                     n_events;
 111         int                     n_added;
 112         int                     n_txn;
 113         int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
 114         u64                     tags[X86_PMC_IDX_MAX];
 115         struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
 116
 117         unsigned int            group_flag;
 118
 119         /*
 120          * Intel DebugStore bits
 121          */
 122         struct debug_store      *ds;
 123         u64                     pebs_enabled;
 124
 125         /*
 126          * Intel LBR bits
 127          */
 128         int                             lbr_users;
 129         void                            *lbr_context;
 130         struct perf_branch_stack        lbr_stack;
 131         struct perf_branch_entry        lbr_entries[MAX_LBR_ENTRIES];
 132
 133         /*
 134          * Intel percore register state.
 135          * Coordinate shared resources between HT threads.
 136          */
 137         int                             percore_used; /* Used by this CPU? */
 138         struct intel_percore            *per_core;
 139
 140         /*
 141          * AMD specific bits
 142          */
 143         struct amd_nb           *amd_nb;
 144 };
 145
 146 #define __EVENT_CONSTRAINT(c, n, m, w) {\
 147         { .idxmsk64 = (n) },            \
 148         .code = (c),                    \
 149         .cmask = (m),                   \
 150         .weight = (w),                  \
 151 }
 152
 153 #define EVENT_CONSTRAINT(c, n, m)       \
 154         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
 155
 156 /*
 157  * Constraint on the Event code.
 158  */
 159 #define INTEL_EVENT_CONSTRAINT(c, n)    \
 160         EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
 161
 162 /*
 163  * Constraint on the Event code + UMask + fixed-mask
 164  *
 165  * filter mask to validate fixed counter events.
 166  * the following filters disqualify for fixed counters:
 167  *  - inv
 168  *  - edge
 169  *  - cnt-mask
 170  *  The other filters are supported by fixed counters.
 171  *  The any-thread option is supported starting with v3.
 172  */
 173 #define FIXED_EVENT_CONSTRAINT(c, n)    \
 174         EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
 175
 176 /*
 177  * Constraint on the Event code + UMask
 178  */
 179 #define INTEL_UEVENT_CONSTRAINT(c, n)   \
 180         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
 181
 182 #define EVENT_CONSTRAINT_END            \
 183         EVENT_CONSTRAINT(0, 0, 0)
 184
 185 #define for_each_event_constraint(e, c) \
 186         for ((e) = (c); (e)->weight; (e)++)
 187
 188 /*
 189  * Extra registers for specific events.
 190  * Some events need large masks and require external MSRs.
 191  * Define a mapping to these extra registers.
 192  */
 193 struct extra_reg {
 194         unsigned int            event;
 195         unsigned int            msr;
 196         u64                     config_mask;
 197         u64                     valid_mask;
 198 };
 199
 200 #define EVENT_EXTRA_REG(e, ms, m, vm) { \
 201         .event = (e),           \
 202         .msr = (ms),            \
 203         .config_mask = (m),     \
 204         .valid_mask = (vm),     \
 205         }
 206 #define INTEL_EVENT_EXTRA_REG(event, msr, vm)   \
 207         EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm)
 208 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0)
 209
 210 union perf_capabilities {
 211         struct {
 212                 u64     lbr_format    : 6;
 213                 u64     pebs_trap     : 1;
 214                 u64     pebs_arch_reg : 1;
 215                 u64     pebs_format   : 4;
 216                 u64     smm_freeze    : 1;
 217         };
 218         u64     capabilities;
 219 };
 220
 221 /*
 222  * struct x86_pmu - generic x86 pmu
 223  */
 224 struct x86_pmu {
 225         /*
 226          * Generic x86 PMC bits
 227          */
 228         const char      *name;
 229         int             version;
 230         int             (*handle_irq)(struct pt_regs *);
 231         void            (*disable_all)(void);
 232         void            (*enable_all)(int added);
 233         void            (*enable)(struct perf_event *);
 234         void            (*disable)(struct perf_event *);
 235         int             (*hw_config)(struct perf_event *event);
 236         int             (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
 237         unsigned        eventsel;
 238         unsigned        perfctr;
 239         u64             (*event_map)(int);
 240         int             max_events;
 241         int             num_counters;
 242         int             num_counters_fixed;
 243         int             cntval_bits;
 244         u64             cntval_mask;
 245         int             apic;
 246         u64             max_period;
 247         struct event_constraint *
 248                         (*get_event_constraints)(struct cpu_hw_events *cpuc,
 249                                                  struct perf_event *event);
 250
 251         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
 252                                                  struct perf_event *event);
 253         struct event_constraint *event_constraints;
 254         struct event_constraint *percore_constraints;
 255         void            (*quirks)(void);
 256         int             perfctr_second_write;
 257
 258         int             (*cpu_prepare)(int cpu);
 259         void            (*cpu_starting)(int cpu);
 260         void            (*cpu_dying)(int cpu);
 261         void            (*cpu_dead)(int cpu);
 262
 263         /*
 264          * Intel Arch Perfmon v2+
 265          */
 266         u64                     intel_ctrl;
 267         union perf_capabilities intel_cap;
 268
 269         /*
 270          * Intel DebugStore bits
 271          */
 272         int             bts, pebs;
 273         int             bts_active, pebs_active;
 274         int             pebs_record_size;
 275         void            (*drain_pebs)(struct pt_regs *regs);
 276         struct event_constraint *pebs_constraints;
 277
 278         /*
 279          * Intel LBR
 280          */
 281         unsigned long   lbr_tos, lbr_from, lbr_to; /* MSR base regs       */
 282         int             lbr_nr;                    /* hardware stack size */
 283
 284         /*
 285          * Extra registers for events
 286          */
 287         struct extra_reg *extra_regs;
 288 };
 289
 290 static struct x86_pmu x86_pmu __read_mostly;
 291
 292 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
 293         .enabled = 1,
 294 };
 295
 296 static int x86_perf_event_set_period(struct perf_event *event);
 297
 298 /*
 299  * Generalized hw caching related hw_event table, filled
 300  * in on a per model basis. A value of 0 means
 301  * 'not supported', -1 means 'hw_event makes no sense on
 302  * this CPU', any other value means the raw hw_event
 303  * ID.
 304  */
 305
 306 #define C(x) PERF_COUNT_HW_CACHE_##x
 307
 308 static u64 __read_mostly hw_cache_event_ids
 309                                 [PERF_COUNT_HW_CACHE_MAX]
 310                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 311                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 312 static u64 __read_mostly hw_cache_extra_regs
 313                                 [PERF_COUNT_HW_CACHE_MAX]
 314                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 315                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 316
 317 /*
 318  * Propagate event elapsed time into the generic event.
 319  * Can only be executed on the CPU where the event is active.
 320  * Returns the delta events processed.
 321  */
 322 static u64
 323 x86_perf_event_update(struct perf_event *event)
 324 {
 325         struct hw_perf_event *hwc = &event->hw;
 326         int shift = 64 - x86_pmu.cntval_bits;
 327         u64 prev_raw_count, new_raw_count;
 328         int idx = hwc->idx;
 329         s64 delta;
 330
 331         if (idx == X86_PMC_IDX_FIXED_BTS)
 332                 return 0;
 333
 334         /*
 335          * Careful: an NMI might modify the previous event value.
 336          *
 337          * Our tactic to handle this is to first atomically read and
 338          * exchange a new raw count - then add that new-prev delta
 339          * count to the generic event atomically:
 340          */
 341 again:
 342         prev_raw_count = local64_read(&hwc->prev_count);
 343         rdmsrl(hwc->event_base, new_raw_count);
 344
 345         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 346                                         new_raw_count) != prev_raw_count)
 347                 goto again;
 348
 349         /*
 350          * Now we have the new raw value and have updated the prev
 351          * timestamp already. We can now calculate the elapsed delta
 352          * (event-)time and add that to the generic event.
 353          *
 354          * Careful, not all hw sign-extends above the physical width
 355          * of the count.
 356          */
 357         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 358         delta >>= shift;
 359
 360         local64_add(delta, &event->count);
 361         local64_sub(delta, &hwc->period_left);
 362
 363         return new_raw_count;
 364 }
 365
 366 /* using X86_FEATURE_PERFCTR_CORE to later implement ALTERNATIVE() here */
 367 static inline int x86_pmu_addr_offset(int index)
 368 {
 369         if (boot_cpu_has(X86_FEATURE_PERFCTR_CORE))
 370                 return index << 1;
 371         return index;
 372 }
 373
 374 static inline unsigned int x86_pmu_config_addr(int index)
 375 {
 376         return x86_pmu.eventsel + x86_pmu_addr_offset(index);
 377 }
 378
 379 static inline unsigned int x86_pmu_event_addr(int index)
 380 {
 381         return x86_pmu.perfctr + x86_pmu_addr_offset(index);
 382 }
 383
 384 /*
 385  * Find and validate any extra registers to set up.
 386  */
 387 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
 388 {
 389         struct extra_reg *er;
 390
 391         event->hw.extra_reg = 0;
 392         event->hw.extra_config = 0;
 393
 394         if (!x86_pmu.extra_regs)
 395                 return 0;
 396
 397         for (er = x86_pmu.extra_regs; er->msr; er++) {
 398                 if (er->event != (config & er->config_mask))
 399                         continue;
 400                 if (event->attr.config1 & ~er->valid_mask)
 401                         return -EINVAL;
 402                 event->hw.extra_reg = er->msr;
 403                 event->hw.extra_config = event->attr.config1;
 404                 break;
 405         }
 406         return 0;
 407 }
 408
 409 static atomic_t active_events;
 410 static DEFINE_MUTEX(pmc_reserve_mutex);
 411
 412 #ifdef CONFIG_X86_LOCAL_APIC
 413
 414 static bool reserve_pmc_hardware(void)
 415 {
 416         int i;
 417
 418         for (i = 0; i < x86_pmu.num_counters; i++) {
 419                 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
 420                         goto perfctr_fail;
 421         }
 422
 423         for (i = 0; i < x86_pmu.num_counters; i++) {
 424                 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
 425                         goto eventsel_fail;
 426         }
 427
 428         return true;
 429
 430 eventsel_fail:
 431         for (i--; i >= 0; i--)
 432                 release_evntsel_nmi(x86_pmu_config_addr(i));
 433
 434         i = x86_pmu.num_counters;
 435
 436 perfctr_fail:
 437         for (i--; i >= 0; i--)
 438                 release_perfctr_nmi(x86_pmu_event_addr(i));
 439
 440         return false;
 441 }
 442
 443 static void release_pmc_hardware(void)
 444 {
 445         int i;
 446
 447         for (i = 0; i < x86_pmu.num_counters; i++) {
 448                 release_perfctr_nmi(x86_pmu_event_addr(i));
 449                 release_evntsel_nmi(x86_pmu_config_addr(i));
 450         }
 451 }
 452
 453 #else
 454
 455 static bool reserve_pmc_hardware(void) { return true; }
 456 static void release_pmc_hardware(void) {}
 457
 458 #endif
 459
 460 static bool check_hw_exists(void)
 461 {
 462         u64 val, val_new = 0;
 463         int i, reg, ret = 0;
 464
 465         /*
 466          * Check to see if the BIOS enabled any of the counters, if so
 467          * complain and bail.
 468          */
 469         for (i = 0; i < x86_pmu.num_counters; i++) {
 470                 reg = x86_pmu_config_addr(i);
 471                 ret = rdmsrl_safe(reg, &val);
 472                 if (ret)
 473                         goto msr_fail;
 474                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
 475                         goto bios_fail;
 476         }
 477
 478         if (x86_pmu.num_counters_fixed) {
 479                 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 480                 ret = rdmsrl_safe(reg, &val);
 481                 if (ret)
 482                         goto msr_fail;
 483                 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
 484                         if (val & (0x03 << i*4))
 485                                 goto bios_fail;
 486                 }
 487         }
 488
 489         /*
 490          * Now write a value and read it back to see if it matches,
 491          * this is needed to detect certain hardware emulators (qemu/kvm)
 492          * that don't trap on the MSR access and always return 0s.
 493          */
 494         val = 0xabcdUL;
 495         ret = checking_wrmsrl(x86_pmu_event_addr(0), val);
 496         ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new);
 497         if (ret || val != val_new)
 498                 goto msr_fail;
 499
 500         return true;
 501
 502 bios_fail:
 503         /*
 504          * We still allow the PMU driver to operate:
 505          */
 506         printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
 507         printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val);
 508
 509         return true;
 510
 511 msr_fail:
 512         printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
 513
 514         return false;
 515 }
 516
 517 static void reserve_ds_buffers(void);
 518 static void release_ds_buffers(void);
 519
 520 static void hw_perf_event_destroy(struct perf_event *event)
 521 {
 522         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 523                 release_pmc_hardware();
 524                 release_ds_buffers();
 525                 mutex_unlock(&pmc_reserve_mutex);
 526         }
 527 }
 528
 529 static inline int x86_pmu_initialized(void)
 530 {
 531         return x86_pmu.handle_irq != NULL;
 532 }
 533
 534 static inline int
 535 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
 536 {
 537         struct perf_event_attr *attr = &event->attr;
 538         unsigned int cache_type, cache_op, cache_result;
 539         u64 config, val;
 540
 541         config = attr->config;
 542
 543         cache_type = (config >>  0) & 0xff;
 544         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 545                 return -EINVAL;
 546
 547         cache_op = (config >>  8) & 0xff;
 548         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 549                 return -EINVAL;
 550
 551         cache_result = (config >> 16) & 0xff;
 552         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 553                 return -EINVAL;
 554
 555         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 556
 557         if (val == 0)
 558                 return -ENOENT;
 559
 560         if (val == -1)
 561                 return -EINVAL;
 562
 563         hwc->config |= val;
 564         attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
 565         return x86_pmu_extra_regs(val, event);
 566 }
 567
 568 static int x86_setup_perfctr(struct perf_event *event)
 569 {
 570         struct perf_event_attr *attr = &event->attr;
 571         struct hw_perf_event *hwc = &event->hw;
 572         u64 config;
 573
 574         if (!is_sampling_event(event)) {
 575                 hwc->sample_period = x86_pmu.max_period;
 576                 hwc->last_period = hwc->sample_period;
 577                 local64_set(&hwc->period_left, hwc->sample_period);
 578         } else {
 579                 /*
 580                  * If we have a PMU initialized but no APIC
 581                  * interrupts, we cannot sample hardware
 582                  * events (user-space has to fall back and
 583                  * sample via a hrtimer based software event):
 584                  */
 585                 if (!x86_pmu.apic)
 586                         return -EOPNOTSUPP;
 587         }
 588
 589         /*
 590          * Do not allow config1 (extended registers) to propagate,
 591          * there's no sane user-space generalization yet:
 592          */
 593         if (attr->type == PERF_TYPE_RAW)
 594                 return 0;
 595
 596         if (attr->type == PERF_TYPE_HW_CACHE)
 597                 return set_ext_hw_attr(hwc, event);
 598
 599         if (attr->config >= x86_pmu.max_events)
 600                 return -EINVAL;
 601
 602         /*
 603          * The generic map:
 604          */
 605         config = x86_pmu.event_map(attr->config);
 606
 607         if (config == 0)
 608                 return -ENOENT;
 609
 610         if (config == -1LL)
 611                 return -EINVAL;
 612
 613         /*
 614          * Branch tracing:
 615          */
 616         if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
 617             (hwc->sample_period == 1)) {
 618                 /* BTS is not supported by this architecture. */
 619                 if (!x86_pmu.bts_active)
 620                         return -EOPNOTSUPP;
 621
 622                 /* BTS is currently only allowed for user-mode. */
 623                 if (!attr->exclude_kernel)
 624                         return -EOPNOTSUPP;
 625         }
 626
 627         hwc->config |= config;
 628
 629         return 0;
 630 }
 631
 632 static int x86_pmu_hw_config(struct perf_event *event)
 633 {
 634         if (event->attr.precise_ip) {
 635                 int precise = 0;
 636
 637                 /* Support for constant skid */
 638                 if (x86_pmu.pebs_active) {
 639                         precise++;
 640
 641                         /* Support for IP fixup */
 642                         if (x86_pmu.lbr_nr)
 643                                 precise++;
 644                 }
 645
 646                 if (event->attr.precise_ip > precise)
 647                         return -EOPNOTSUPP;
 648         }
 649
 650         /*
 651          * Generate PMC IRQs:
 652          * (keep 'enabled' bit clear for now)
 653          */
 654         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 655
 656         /*
 657          * Count user and OS events unless requested not to
 658          */
 659         if (!event->attr.exclude_user)
 660                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 661         if (!event->attr.exclude_kernel)
 662                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 663
 664         if (event->attr.type == PERF_TYPE_RAW)
 665                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 666
 667         return x86_setup_perfctr(event);
 668 }
 669
 670 /*
 671  * Setup the hardware configuration for a given attr_type
 672  */
 673 static int __x86_pmu_event_init(struct perf_event *event)
 674 {
 675         int err;
 676
 677         if (!x86_pmu_initialized())
 678                 return -ENODEV;
 679
 680         err = 0;
 681         if (!atomic_inc_not_zero(&active_events)) {
 682                 mutex_lock(&pmc_reserve_mutex);
 683                 if (atomic_read(&active_events) == 0) {
 684                         if (!reserve_pmc_hardware())
 685                                 err = -EBUSY;
 686                         else
 687                                 reserve_ds_buffers();
 688                 }
 689                 if (!err)
 690                         atomic_inc(&active_events);
 691                 mutex_unlock(&pmc_reserve_mutex);
 692         }
 693         if (err)
 694                 return err;
 695
 696         event->destroy = hw_perf_event_destroy;
 697
 698         event->hw.idx = -1;
 699         event->hw.last_cpu = -1;
 700         event->hw.last_tag = ~0ULL;
 701
 702         return x86_pmu.hw_config(event);
 703 }
 704
 705 static void x86_pmu_disable_all(void)
 706 {
 707         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 708         int idx;
 709
 710         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 711                 u64 val;
 712
 713                 if (!test_bit(idx, cpuc->active_mask))
 714                         continue;
 715                 rdmsrl(x86_pmu_config_addr(idx), val);
 716                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 717                         continue;
 718                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 719                 wrmsrl(x86_pmu_config_addr(idx), val);
 720         }
 721 }
 722
 723 static void x86_pmu_disable(struct pmu *pmu)
 724 {
 725         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 726
 727         if (!x86_pmu_initialized())
 728                 return;
 729
 730         if (!cpuc->enabled)
 731                 return;
 732
 733         cpuc->n_added = 0;
 734         cpuc->enabled = 0;
 735         barrier();
 736
 737         x86_pmu.disable_all();
 738 }
 739
 740 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
 741                                           u64 enable_mask)
 742 {
 743         if (hwc->extra_reg)
 744                 wrmsrl(hwc->extra_reg, hwc->extra_config);
 745         wrmsrl(hwc->config_base, hwc->config | enable_mask);
 746 }
 747
 748 static void x86_pmu_enable_all(int added)
 749 {
 750         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 751         int idx;
 752
 753         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 754                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
 755
 756                 if (!test_bit(idx, cpuc->active_mask))
 757                         continue;
 758
 759                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
 760         }
 761 }
 762
 763 static struct pmu pmu;
 764
 765 static inline int is_x86_event(struct perf_event *event)
 766 {
 767         return event->pmu == &pmu;
 768 }
 769
 770 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 771 {
 772         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
 773         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 774         int i, j, w, wmax, num = 0;
 775         struct hw_perf_event *hwc;
 776
 777         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 778
 779         for (i = 0; i < n; i++) {
 780                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 781                 constraints[i] = c;
 782         }
 783
 784         /*
 785          * fastpath, try to reuse previous register
 786          */
 787         for (i = 0; i < n; i++) {
 788                 hwc = &cpuc->event_list[i]->hw;
 789                 c = constraints[i];
 790
 791                 /* never assigned */
 792                 if (hwc->idx == -1)
 793                         break;
 794
 795                 /* constraint still honored */
 796                 if (!test_bit(hwc->idx, c->idxmsk))
 797                         break;
 798
 799                 /* not already used */
 800                 if (test_bit(hwc->idx, used_mask))
 801                         break;
 802
 803                 __set_bit(hwc->idx, used_mask);
 804                 if (assign)
 805                         assign[i] = hwc->idx;
 806         }
 807         if (i == n)
 808                 goto done;
 809
 810         /*
 811          * begin slow path
 812          */
 813
 814         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 815
 816         /*
 817          * weight = number of possible counters
 818          *
 819          * 1    = most constrained, only works on one counter
 820          * wmax = least constrained, works on any counter
 821          *
 822          * assign events to counters starting with most
 823          * constrained events.
 824          */
 825         wmax = x86_pmu.num_counters;
 826
 827         /*
 828          * when fixed event counters are present,
 829          * wmax is incremented by 1 to account
 830          * for one more choice
 831          */
 832         if (x86_pmu.num_counters_fixed)
 833                 wmax++;
 834
 835         for (w = 1, num = n; num && w <= wmax; w++) {
 836                 /* for each event */
 837                 for (i = 0; num && i < n; i++) {
 838                         c = constraints[i];
 839                         hwc = &cpuc->event_list[i]->hw;
 840
 841                         if (c->weight != w)
 842                                 continue;
 843
 844                         for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
 845                                 if (!test_bit(j, used_mask))
 846                                         break;
 847                         }
 848
 849                         if (j == X86_PMC_IDX_MAX)
 850                                 break;
 851
 852                         __set_bit(j, used_mask);
 853
 854                         if (assign)
 855                                 assign[i] = j;
 856                         num--;
 857                 }
 858         }
 859 done:
 860         /*
 861          * scheduling failed or is just a simulation,
 862          * free resources if necessary
 863          */
 864         if (!assign || num) {
 865                 for (i = 0; i < n; i++) {
 866                         if (x86_pmu.put_event_constraints)
 867                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
 868                 }
 869         }
 870         return num ? -ENOSPC : 0;
 871 }
 872
 873 /*
 874  * dogrp: true if must collect siblings events (group)
 875  * returns total number of events and error code
 876  */
 877 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 878 {
 879         struct perf_event *event;
 880         int n, max_count;
 881
 882         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 883
 884         /* current number of events already accepted */
 885         n = cpuc->n_events;
 886
 887         if (is_x86_event(leader)) {
 888                 if (n >= max_count)
 889                         return -ENOSPC;
 890                 cpuc->event_list[n] = leader;
 891                 n++;
 892         }
 893         if (!dogrp)
 894                 return n;
 895
 896         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 897                 if (!is_x86_event(event) ||
 898                     event->state <= PERF_EVENT_STATE_OFF)
 899                         continue;
 900
 901                 if (n >= max_count)
 902                         return -ENOSPC;
 903
 904                 cpuc->event_list[n] = event;
 905                 n++;
 906         }
 907         return n;
 908 }
 909
 910 static inline void x86_assign_hw_event(struct perf_event *event,
 911                                 struct cpu_hw_events *cpuc, int i)
 912 {
 913         struct hw_perf_event *hwc = &event->hw;
 914
 915         hwc->idx = cpuc->assign[i];
 916         hwc->last_cpu = smp_processor_id();
 917         hwc->last_tag = ++cpuc->tags[i];
 918
 919         if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
 920                 hwc->config_base = 0;
 921                 hwc->event_base = 0;
 922         } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
 923                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 924                 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - X86_PMC_IDX_FIXED);
 925         } else {
 926                 hwc->config_base = x86_pmu_config_addr(hwc->idx);
 927                 hwc->event_base  = x86_pmu_event_addr(hwc->idx);
 928         }
 929 }
 930
 931 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 932                                         struct cpu_hw_events *cpuc,
 933                                         int i)
 934 {
 935         return hwc->idx == cpuc->assign[i] &&
 936                 hwc->last_cpu == smp_processor_id() &&
 937                 hwc->last_tag == cpuc->tags[i];
 938 }
 939
 940 static void x86_pmu_start(struct perf_event *event, int flags);
 941 static void x86_pmu_stop(struct perf_event *event, int flags);
 942
 943 static void x86_pmu_enable(struct pmu *pmu)
 944 {
 945         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 946         struct perf_event *event;
 947         struct hw_perf_event *hwc;
 948         int i, added = cpuc->n_added;
 949
 950         if (!x86_pmu_initialized())
 951                 return;
 952
 953         if (cpuc->enabled)
 954                 return;
 955
 956         if (cpuc->n_added) {
 957                 int n_running = cpuc->n_events - cpuc->n_added;
 958                 /*
 959                  * apply assignment obtained either from
 960                  * hw_perf_group_sched_in() or x86_pmu_enable()
 961                  *
 962                  * step1: save events moving to new counters
 963                  * step2: reprogram moved events into new counters
 964                  */
 965                 for (i = 0; i < n_running; i++) {
 966                         event = cpuc->event_list[i];
 967                         hwc = &event->hw;
 968
 969                         /*
 970                          * we can avoid reprogramming counter if:
 971                          * - assigned same counter as last time
 972                          * - running on same CPU as last time
 973                          * - no other event has used the counter since
 974                          */
 975                         if (hwc->idx == -1 ||
 976                             match_prev_assignment(hwc, cpuc, i))
 977                                 continue;
 978
 979                         /*
 980                          * Ensure we don't accidentally enable a stopped
 981                          * counter simply because we rescheduled.
 982                          */
 983                         if (hwc->state & PERF_HES_STOPPED)
 984                                 hwc->state |= PERF_HES_ARCH;
 985
 986                         x86_pmu_stop(event, PERF_EF_UPDATE);
 987                 }
 988
 989                 for (i = 0; i < cpuc->n_events; i++) {
 990                         event = cpuc->event_list[i];
 991                         hwc = &event->hw;
 992
 993                         if (!match_prev_assignment(hwc, cpuc, i))
 994                                 x86_assign_hw_event(event, cpuc, i);
 995                         else if (i < n_running)
 996                                 continue;
 997
 998                         if (hwc->state & PERF_HES_ARCH)
 999                                 continue;
1000
1001                         x86_pmu_start(event, PERF_EF_RELOAD);
1002                 }
1003                 cpuc->n_added = 0;
1004                 perf_events_lapic_init();
1005         }
1006
1007         cpuc->enabled = 1;
1008         barrier();
1009
1010         x86_pmu.enable_all(added);
1011 }
1012
1013 static inline void x86_pmu_disable_event(struct perf_event *event)
1014 {
1015         struct hw_perf_event *hwc = &event->hw;
1016
1017         wrmsrl(hwc->config_base, hwc->config);
1018 }
1019
1020 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1021
1022 /*
1023  * Set the next IRQ period, based on the hwc->period_left value.
1024  * To be called with the event disabled in hw:
1025  */
1026 static int
1027 x86_perf_event_set_period(struct perf_event *event)
1028 {
1029         struct hw_perf_event *hwc = &event->hw;
1030         s64 left = local64_read(&hwc->period_left);
1031         s64 period = hwc->sample_period;
1032         int ret = 0, idx = hwc->idx;
1033
1034         if (idx == X86_PMC_IDX_FIXED_BTS)
1035                 return 0;
1036
1037         /*
1038          * If we are way outside a reasonable range then just skip forward:
1039          */
1040         if (unlikely(left <= -period)) {
1041                 left = period;
1042                 local64_set(&hwc->period_left, left);
1043                 hwc->last_period = period;
1044                 ret = 1;
1045         }
1046
1047         if (unlikely(left <= 0)) {
1048                 left += period;
1049                 local64_set(&hwc->period_left, left);
1050                 hwc->last_period = period;
1051                 ret = 1;
1052         }
1053         /*
1054          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1055          */
1056         if (unlikely(left < 2))
1057                 left = 2;
1058
1059         if (left > x86_pmu.max_period)
1060                 left = x86_pmu.max_period;
1061
1062         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1063
1064         /*
1065          * The hw event starts counting from this event offset,
1066          * mark it to be able to extra future deltas:
1067          */
1068         local64_set(&hwc->prev_count, (u64)-left);
1069
1070         wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1071
1072         /*
1073          * Due to erratum on certan cpu we need
1074          * a second write to be sure the register
1075          * is updated properly
1076          */
1077         if (x86_pmu.perfctr_second_write) {
1078                 wrmsrl(hwc->event_base,
1079                         (u64)(-left) & x86_pmu.cntval_mask);
1080         }
1081
1082         perf_event_update_userpage(event);
1083
1084         return ret;
1085 }
1086
1087 static void x86_pmu_enable_event(struct perf_event *event)
1088 {
1089         if (__this_cpu_read(cpu_hw_events.enabled))
1090                 __x86_pmu_enable_event(&event->hw,
1091                                        ARCH_PERFMON_EVENTSEL_ENABLE);
1092 }
1093
1094 /*
1095  * Add a single event to the PMU.
1096  *
1097  * The event is added to the group of enabled events
1098  * but only if it can be scehduled with existing events.
1099  */
1100 static int x86_pmu_add(struct perf_event *event, int flags)
1101 {
1102         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1103         struct hw_perf_event *hwc;
1104         int assign[X86_PMC_IDX_MAX];
1105         int n, n0, ret;
1106
1107         hwc = &event->hw;
1108
1109         perf_pmu_disable(event->pmu);
1110         n0 = cpuc->n_events;
1111         ret = n = collect_events(cpuc, event, false);
1112         if (ret < 0)
1113                 goto out;
1114
1115         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1116         if (!(flags & PERF_EF_START))
1117                 hwc->state |= PERF_HES_ARCH;
1118
1119         /*
1120          * If group events scheduling transaction was started,
1121          * skip the schedulability test here, it will be performed
1122          * at commit time (->commit_txn) as a whole
1123          */
1124         if (cpuc->group_flag & PERF_EVENT_TXN)
1125                 goto done_collect;
1126
1127         ret = x86_pmu.schedule_events(cpuc, n, assign);
1128         if (ret)
1129                 goto out;
1130         /*
1131          * copy new assignment, now we know it is possible
1132          * will be used by hw_perf_enable()
1133          */
1134         memcpy(cpuc->assign, assign, n*sizeof(int));
1135
1136 done_collect:
1137         cpuc->n_events = n;
1138         cpuc->n_added += n - n0;
1139         cpuc->n_txn += n - n0;
1140
1141         ret = 0;
1142 out:
1143         perf_pmu_enable(event->pmu);
1144         return ret;
1145 }
1146
1147 static void x86_pmu_start(struct perf_event *event, int flags)
1148 {
1149         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1150         int idx = event->hw.idx;
1151
1152         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1153                 return;
1154
1155         if (WARN_ON_ONCE(idx == -1))
1156                 return;
1157
1158         if (flags & PERF_EF_RELOAD) {
1159                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1160                 x86_perf_event_set_period(event);
1161         }
1162
1163         event->hw.state = 0;
1164
1165         cpuc->events[idx] = event;
1166         __set_bit(idx, cpuc->active_mask);
1167         __set_bit(idx, cpuc->running);
1168         x86_pmu.enable(event);
1169         perf_event_update_userpage(event);
1170 }
1171
1172 void perf_event_print_debug(void)
1173 {
1174         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1175         u64 pebs;
1176         struct cpu_hw_events *cpuc;
1177         unsigned long flags;
1178         int cpu, idx;
1179
1180         if (!x86_pmu.num_counters)
1181                 return;
1182
1183         local_irq_save(flags);
1184
1185         cpu = smp_processor_id();
1186         cpuc = &per_cpu(cpu_hw_events, cpu);
1187
1188         if (x86_pmu.version >= 2) {
1189                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1190                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1191                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1192                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1193                 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1194
1195                 pr_info("\n");
1196                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1197                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1198                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1199                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1200                 pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1201         }
1202         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1203
1204         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1205                 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1206                 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1207
1208                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1209
1210                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1211                         cpu, idx, pmc_ctrl);
1212                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1213                         cpu, idx, pmc_count);
1214                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1215                         cpu, idx, prev_left);
1216         }
1217         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1218                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1219
1220                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1221                         cpu, idx, pmc_count);
1222         }
1223         local_irq_restore(flags);
1224 }
1225
1226 static void x86_pmu_stop(struct perf_event *event, int flags)
1227 {
1228         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1229         struct hw_perf_event *hwc = &event->hw;
1230
1231         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1232                 x86_pmu.disable(event);
1233                 cpuc->events[hwc->idx] = NULL;
1234                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1235                 hwc->state |= PERF_HES_STOPPED;
1236         }
1237
1238         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1239                 /*
1240                  * Drain the remaining delta count out of a event
1241                  * that we are disabling:
1242                  */
1243                 x86_perf_event_update(event);
1244                 hwc->state |= PERF_HES_UPTODATE;
1245         }
1246 }
1247
1248 static void x86_pmu_del(struct perf_event *event, int flags)
1249 {
1250         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1251         int i;
1252
1253         /*
1254          * If we're called during a txn, we don't need to do anything.
1255          * The events never got scheduled and ->cancel_txn will truncate
1256          * the event_list.
1257          */
1258         if (cpuc->group_flag & PERF_EVENT_TXN)
1259                 return;
1260
1261         x86_pmu_stop(event, PERF_EF_UPDATE);
1262
1263         for (i = 0; i < cpuc->n_events; i++) {
1264                 if (event == cpuc->event_list[i]) {
1265
1266                         if (x86_pmu.put_event_constraints)
1267                                 x86_pmu.put_event_constraints(cpuc, event);
1268
1269                         while (++i < cpuc->n_events)
1270                                 cpuc->event_list[i-1] = cpuc->event_list[i];
1271
1272                         --cpuc->n_events;
1273                         break;
1274                 }
1275         }
1276         perf_event_update_userpage(event);
1277 }
1278
1279 static int x86_pmu_handle_irq(struct pt_regs *regs)
1280 {
1281         struct perf_sample_data data;
1282         struct cpu_hw_events *cpuc;
1283         struct perf_event *event;
1284         int idx, handled = 0;
1285         u64 val;
1286
1287         perf_sample_data_init(&data, 0);
1288
1289         cpuc = &__get_cpu_var(cpu_hw_events);
1290
1291         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1292                 if (!test_bit(idx, cpuc->active_mask)) {
1293                         /*
1294                          * Though we deactivated the counter some cpus
1295                          * might still deliver spurious interrupts still
1296                          * in flight. Catch them:
1297                          */
1298                         if (__test_and_clear_bit(idx, cpuc->running))
1299                                 handled++;
1300                         continue;
1301                 }
1302
1303                 event = cpuc->events[idx];
1304
1305                 val = x86_perf_event_update(event);
1306                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1307                         continue;
1308
1309                 /*
1310                  * event overflow
1311                  */
1312                 handled++;
1313                 data.period     = event->hw.last_period;
1314
1315                 if (!x86_perf_event_set_period(event))
1316                         continue;
1317
1318                 if (perf_event_overflow(event, 1, &data, regs))
1319                         x86_pmu_stop(event, 0);
1320         }
1321
1322         if (handled)
1323                 inc_irq_stat(apic_perf_irqs);
1324
1325         return handled;
1326 }
1327
1328 void perf_events_lapic_init(void)
1329 {
1330         if (!x86_pmu.apic || !x86_pmu_initialized())
1331                 return;
1332
1333         /*
1334          * Always use NMI for PMU
1335          */
1336         apic_write(APIC_LVTPC, APIC_DM_NMI);
1337 }
1338
1339 struct pmu_nmi_state {
1340         unsigned int    marked;
1341         int             handled;
1342 };
1343
1344 static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi);
1345
1346 static int __kprobes
1347 perf_event_nmi_handler(struct notifier_block *self,
1348                          unsigned long cmd, void *__args)
1349 {
1350         struct die_args *args = __args;
1351         unsigned int this_nmi;
1352         int handled;
1353
1354         if (!atomic_read(&active_events))
1355                 return NOTIFY_DONE;
1356
1357         switch (cmd) {
1358         case DIE_NMI:
1359                 break;
1360         case DIE_NMIUNKNOWN:
1361                 this_nmi = percpu_read(irq_stat.__nmi_count);
1362                 if (this_nmi != __this_cpu_read(pmu_nmi.marked))
1363                         /* let the kernel handle the unknown nmi */
1364                         return NOTIFY_DONE;
1365                 /*
1366                  * This one is a PMU back-to-back nmi. Two events
1367                  * trigger 'simultaneously' raising two back-to-back
1368                  * NMIs. If the first NMI handles both, the latter
1369                  * will be empty and daze the CPU. So, we drop it to
1370                  * avoid false-positive 'unknown nmi' messages.
1371                  */
1372                 return NOTIFY_STOP;
1373         default:
1374                 return NOTIFY_DONE;
1375         }
1376
1377         apic_write(APIC_LVTPC, APIC_DM_NMI);
1378
1379         handled = x86_pmu.handle_irq(args->regs);
1380         if (!handled)
1381                 return NOTIFY_DONE;
1382
1383         this_nmi = percpu_read(irq_stat.__nmi_count);
1384         if ((handled > 1) ||
1385                 /* the next nmi could be a back-to-back nmi */
1386             ((__this_cpu_read(pmu_nmi.marked) == this_nmi) &&
1387              (__this_cpu_read(pmu_nmi.handled) > 1))) {
1388                 /*
1389                  * We could have two subsequent back-to-back nmis: The
1390                  * first handles more than one counter, the 2nd
1391                  * handles only one counter and the 3rd handles no
1392                  * counter.
1393                  *
1394                  * This is the 2nd nmi because the previous was
1395                  * handling more than one counter. We will mark the
1396                  * next (3rd) and then drop it if unhandled.
1397                  */
1398                 __this_cpu_write(pmu_nmi.marked, this_nmi + 1);
1399                 __this_cpu_write(pmu_nmi.handled, handled);
1400         }
1401
1402         return NOTIFY_STOP;
1403 }
1404
1405 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1406         .notifier_call          = perf_event_nmi_handler,
1407         .next                   = NULL,
1408         .priority               = NMI_LOCAL_LOW_PRIOR,
1409 };
1410
1411 static struct event_constraint unconstrained;
1412 static struct event_constraint emptyconstraint;
1413
1414 static struct event_constraint *
1415 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1416 {
1417         struct event_constraint *c;
1418
1419         if (x86_pmu.event_constraints) {
1420                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1421                         if ((event->hw.config & c->cmask) == c->code)
1422                                 return c;
1423                 }
1424         }
1425
1426         return &unconstrained;
1427 }
1428
1429 #include "perf_event_amd.c"
1430 #include "perf_event_p6.c"
1431 #include "perf_event_p4.c"
1432 #include "perf_event_intel_lbr.c"
1433 #include "perf_event_intel_ds.c"
1434 #include "perf_event_intel.c"
1435
1436 static int __cpuinit
1437 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1438 {
1439         unsigned int cpu = (long)hcpu;
1440         int ret = NOTIFY_OK;
1441
1442         switch (action & ~CPU_TASKS_FROZEN) {
1443         case CPU_UP_PREPARE:
1444                 if (x86_pmu.cpu_prepare)
1445                         ret = x86_pmu.cpu_prepare(cpu);
1446                 break;
1447
1448         case CPU_STARTING:
1449                 if (x86_pmu.cpu_starting)
1450                         x86_pmu.cpu_starting(cpu);
1451                 break;
1452
1453         case CPU_DYING:
1454                 if (x86_pmu.cpu_dying)
1455                         x86_pmu.cpu_dying(cpu);
1456                 break;
1457
1458         case CPU_UP_CANCELED:
1459         case CPU_DEAD:
1460                 if (x86_pmu.cpu_dead)
1461                         x86_pmu.cpu_dead(cpu);
1462                 break;
1463
1464         default:
1465                 break;
1466         }
1467
1468         return ret;
1469 }
1470
1471 static void __init pmu_check_apic(void)
1472 {
1473         if (cpu_has_apic)
1474                 return;
1475
1476         x86_pmu.apic = 0;
1477         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1478         pr_info("no hardware sampling interrupt available.\n");
1479 }
1480
1481 static int __init init_hw_perf_events(void)
1482 {
1483         struct event_constraint *c;
1484         int err;
1485
1486         pr_info("Performance Events: ");
1487
1488         switch (boot_cpu_data.x86_vendor) {
1489         case X86_VENDOR_INTEL:
1490                 err = intel_pmu_init();
1491                 break;
1492         case X86_VENDOR_AMD:
1493                 err = amd_pmu_init();
1494                 break;
1495         default:
1496                 return 0;
1497         }
1498         if (err != 0) {
1499                 pr_cont("no PMU driver, software events only.\n");
1500                 return 0;
1501         }
1502
1503         pmu_check_apic();
1504
1505         /* sanity check that the hardware exists or is emulated */
1506         if (!check_hw_exists())
1507                 return 0;
1508
1509         pr_cont("%s PMU driver.\n", x86_pmu.name);
1510
1511         if (x86_pmu.quirks)
1512                 x86_pmu.quirks();
1513
1514         if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1515                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1516                      x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1517                 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1518         }
1519         x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1520
1521         if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1522                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1523                      x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1524                 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1525         }
1526
1527         x86_pmu.intel_ctrl |=
1528                 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1529
1530         perf_events_lapic_init();
1531         register_die_notifier(&perf_event_nmi_notifier);
1532
1533         unconstrained = (struct event_constraint)
1534                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1535                                    0, x86_pmu.num_counters);
1536
1537         if (x86_pmu.event_constraints) {
1538                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1539                         if (c->cmask != X86_RAW_EVENT_MASK)
1540                                 continue;
1541
1542                         c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1543                         c->weight += x86_pmu.num_counters;
1544                 }
1545         }
1546
1547         pr_info("... version:                %d\n",     x86_pmu.version);
1548         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1549         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1550         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1551         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1552         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1553         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1554
1555         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1556         perf_cpu_notifier(x86_pmu_notifier);
1557
1558         return 0;
1559 }
1560 early_initcall(init_hw_perf_events);
1561
1562 static inline void x86_pmu_read(struct perf_event *event)
1563 {
1564         x86_perf_event_update(event);
1565 }
1566
1567 /*
1568  * Start group events scheduling transaction
1569  * Set the flag to make pmu::enable() not perform the
1570  * schedulability test, it will be performed at commit time
1571  */
1572 static void x86_pmu_start_txn(struct pmu *pmu)
1573 {
1574         perf_pmu_disable(pmu);
1575         __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
1576         __this_cpu_write(cpu_hw_events.n_txn, 0);
1577 }
1578
1579 /*
1580  * Stop group events scheduling transaction
1581  * Clear the flag and pmu::enable() will perform the
1582  * schedulability test.
1583  */
1584 static void x86_pmu_cancel_txn(struct pmu *pmu)
1585 {
1586         __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1587         /*
1588          * Truncate the collected events.
1589          */
1590         __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1591         __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1592         perf_pmu_enable(pmu);
1593 }
1594
1595 /*
1596  * Commit group events scheduling transaction
1597  * Perform the group schedulability test as a whole
1598  * Return 0 if success
1599  */
1600 static int x86_pmu_commit_txn(struct pmu *pmu)
1601 {
1602         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1603         int assign[X86_PMC_IDX_MAX];
1604         int n, ret;
1605
1606         n = cpuc->n_events;
1607
1608         if (!x86_pmu_initialized())
1609                 return -EAGAIN;
1610
1611         ret = x86_pmu.schedule_events(cpuc, n, assign);
1612         if (ret)
1613                 return ret;
1614
1615         /*
1616          * copy new assignment, now we know it is possible
1617          * will be used by hw_perf_enable()
1618          */
1619         memcpy(cpuc->assign, assign, n*sizeof(int));
1620
1621         cpuc->group_flag &= ~PERF_EVENT_TXN;
1622         perf_pmu_enable(pmu);
1623         return 0;
1624 }
1625
1626 /*
1627  * validate that we can schedule this event
1628  */
1629 static int validate_event(struct perf_event *event)
1630 {
1631         struct cpu_hw_events *fake_cpuc;
1632         struct event_constraint *c;
1633         int ret = 0;
1634
1635         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1636         if (!fake_cpuc)
1637                 return -ENOMEM;
1638
1639         c = x86_pmu.get_event_constraints(fake_cpuc, event);
1640
1641         if (!c || !c->weight)
1642                 ret = -ENOSPC;
1643
1644         if (x86_pmu.put_event_constraints)
1645                 x86_pmu.put_event_constraints(fake_cpuc, event);
1646
1647         kfree(fake_cpuc);
1648
1649         return ret;
1650 }
1651
1652 /*
1653  * validate a single event group
1654  *
1655  * validation include:
1656  *      - check events are compatible which each other
1657  *      - events do not compete for the same counter
1658  *      - number of events <= number of counters
1659  *
1660  * validation ensures the group can be loaded onto the
1661  * PMU if it was the only group available.
1662  */
1663 static int validate_group(struct perf_event *event)
1664 {
1665         struct perf_event *leader = event->group_leader;
1666         struct cpu_hw_events *fake_cpuc;
1667         int ret, n;
1668
1669         ret = -ENOMEM;
1670         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1671         if (!fake_cpuc)
1672                 goto out;
1673
1674         /*
1675          * the event is not yet connected with its
1676          * siblings therefore we must first collect
1677          * existing siblings, then add the new event
1678          * before we can simulate the scheduling
1679          */
1680         ret = -ENOSPC;
1681         n = collect_events(fake_cpuc, leader, true);
1682         if (n < 0)
1683                 goto out_free;
1684
1685         fake_cpuc->n_events = n;
1686         n = collect_events(fake_cpuc, event, false);
1687         if (n < 0)
1688                 goto out_free;
1689
1690         fake_cpuc->n_events = n;
1691
1692         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1693
1694 out_free:
1695         kfree(fake_cpuc);
1696 out:
1697         return ret;
1698 }
1699
1700 static int x86_pmu_event_init(struct perf_event *event)
1701 {
1702         struct pmu *tmp;
1703         int err;
1704
1705         switch (event->attr.type) {
1706         case PERF_TYPE_RAW:
1707         case PERF_TYPE_HARDWARE:
1708         case PERF_TYPE_HW_CACHE:
1709                 break;
1710
1711         default:
1712                 return -ENOENT;
1713         }
1714
1715         err = __x86_pmu_event_init(event);
1716         if (!err) {
1717                 /*
1718                  * we temporarily connect event to its pmu
1719                  * such that validate_group() can classify
1720                  * it as an x86 event using is_x86_event()
1721                  */
1722                 tmp = event->pmu;
1723                 event->pmu = &pmu;
1724
1725                 if (event->group_leader != event)
1726                         err = validate_group(event);
1727                 else
1728                         err = validate_event(event);
1729
1730                 event->pmu = tmp;
1731         }
1732         if (err) {
1733                 if (event->destroy)
1734                         event->destroy(event);
1735         }
1736
1737         return err;
1738 }
1739
1740 static struct pmu pmu = {
1741         .pmu_enable     = x86_pmu_enable,
1742         .pmu_disable    = x86_pmu_disable,
1743
1744         .event_init     = x86_pmu_event_init,
1745
1746         .add            = x86_pmu_add,
1747         .del            = x86_pmu_del,
1748         .start          = x86_pmu_start,
1749         .stop           = x86_pmu_stop,
1750         .read           = x86_pmu_read,
1751
1752         .start_txn      = x86_pmu_start_txn,
1753         .cancel_txn     = x86_pmu_cancel_txn,
1754         .commit_txn     = x86_pmu_commit_txn,
1755 };
1756
1757 /*
1758  * callchain support
1759  */
1760
1761 static void
1762 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1763 {
1764         /* Ignore warnings */
1765 }
1766
1767 static void backtrace_warning(void *data, char *msg)
1768 {
1769         /* Ignore warnings */
1770 }
1771
1772 static int backtrace_stack(void *data, char *name)
1773 {
1774         return 0;
1775 }
1776
1777 static void backtrace_address(void *data, unsigned long addr, int reliable)
1778 {
1779         struct perf_callchain_entry *entry = data;
1780
1781         perf_callchain_store(entry, addr);
1782 }
1783
1784 static const struct stacktrace_ops backtrace_ops = {
1785         .warning                = backtrace_warning,
1786         .warning_symbol         = backtrace_warning_symbol,
1787         .stack                  = backtrace_stack,
1788         .address                = backtrace_address,
1789         .walk_stack             = print_context_stack_bp,
1790 };
1791
1792 void
1793 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1794 {
1795         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1796                 /* TODO: We don't support guest os callchain now */
1797                 return;
1798         }
1799
1800         perf_callchain_store(entry, regs->ip);
1801
1802         dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
1803 }
1804
1805 #ifdef CONFIG_COMPAT
1806 static inline int
1807 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1808 {
1809         /* 32-bit process in 64-bit kernel. */
1810         struct stack_frame_ia32 frame;
1811         const void __user *fp;
1812
1813         if (!test_thread_flag(TIF_IA32))
1814                 return 0;
1815
1816         fp = compat_ptr(regs->bp);
1817         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1818                 unsigned long bytes;
1819                 frame.next_frame     = 0;
1820                 frame.return_address = 0;
1821
1822                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1823                 if (bytes != sizeof(frame))
1824                         break;
1825
1826                 if (fp < compat_ptr(regs->sp))
1827                         break;
1828
1829                 perf_callchain_store(entry, frame.return_address);
1830                 fp = compat_ptr(frame.next_frame);
1831         }
1832         return 1;
1833 }
1834 #else
1835 static inline int
1836 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1837 {
1838     return 0;
1839 }
1840 #endif
1841
1842 void
1843 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1844 {
1845         struct stack_frame frame;
1846         const void __user *fp;
1847
1848         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1849                 /* TODO: We don't support guest os callchain now */
1850                 return;
1851         }
1852
1853         fp = (void __user *)regs->bp;
1854
1855         perf_callchain_store(entry, regs->ip);
1856
1857         if (perf_callchain_user32(regs, entry))
1858                 return;
1859
1860         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1861                 unsigned long bytes;
1862                 frame.next_frame             = NULL;
1863                 frame.return_address = 0;
1864
1865                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1866                 if (bytes != sizeof(frame))
1867                         break;
1868
1869                 if ((unsigned long)fp < regs->sp)
1870                         break;
1871
1872                 perf_callchain_store(entry, frame.return_address);
1873                 fp = frame.next_frame;
1874         }
1875 }
1876
1877 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1878 {
1879         unsigned long ip;
1880
1881         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1882                 ip = perf_guest_cbs->get_guest_ip();
1883         else
1884                 ip = instruction_pointer(regs);
1885
1886         return ip;
1887 }
1888
1889 unsigned long perf_misc_flags(struct pt_regs *regs)
1890 {
1891         int misc = 0;
1892
1893         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1894                 if (perf_guest_cbs->is_user_mode())
1895                         misc |= PERF_RECORD_MISC_GUEST_USER;
1896                 else
1897                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1898         } else {
1899                 if (user_mode(regs))
1900                         misc |= PERF_RECORD_MISC_USER;
1901                 else
1902                         misc |= PERF_RECORD_MISC_KERNEL;
1903         }
1904
1905         if (regs->flags & PERF_EFLAGS_EXACT)
1906                 misc |= PERF_RECORD_MISC_EXACT_IP;
1907
1908         return misc;
1909 }