2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/cpu.h>
26 #include <linux/bitops.h>
29 #include <asm/stacktrace.h>
31 #include <asm/compat.h>
33 #include <asm/alternative.h>
35 #include "perf_event.h"
39 #define wrmsrl(msr, val) \
41 trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
42 (unsigned long)(val)); \
43 native_write_msr((msr), (u32)((u64)(val)), \
44 (u32)((u64)(val) >> 32)); \
48 struct x86_pmu x86_pmu __read_mostly;
50 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
54 u64 __read_mostly hw_cache_event_ids
55 [PERF_COUNT_HW_CACHE_MAX]
56 [PERF_COUNT_HW_CACHE_OP_MAX]
57 [PERF_COUNT_HW_CACHE_RESULT_MAX];
58 u64 __read_mostly hw_cache_extra_regs
59 [PERF_COUNT_HW_CACHE_MAX]
60 [PERF_COUNT_HW_CACHE_OP_MAX]
61 [PERF_COUNT_HW_CACHE_RESULT_MAX];
64 * Propagate event elapsed time into the generic event.
65 * Can only be executed on the CPU where the event is active.
66 * Returns the delta events processed.
68 u64 x86_perf_event_update(struct perf_event *event)
70 struct hw_perf_event *hwc = &event->hw;
71 int shift = 64 - x86_pmu.cntval_bits;
72 u64 prev_raw_count, new_raw_count;
76 if (idx == X86_PMC_IDX_FIXED_BTS)
80 * Careful: an NMI might modify the previous event value.
82 * Our tactic to handle this is to first atomically read and
83 * exchange a new raw count - then add that new-prev delta
84 * count to the generic event atomically:
87 prev_raw_count = local64_read(&hwc->prev_count);
88 rdmsrl(hwc->event_base, new_raw_count);
90 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
91 new_raw_count) != prev_raw_count)
95 * Now we have the new raw value and have updated the prev
96 * timestamp already. We can now calculate the elapsed delta
97 * (event-)time and add that to the generic event.
99 * Careful, not all hw sign-extends above the physical width
102 delta = (new_raw_count << shift) - (prev_raw_count << shift);
105 local64_add(delta, &event->count);
106 local64_sub(delta, &hwc->period_left);
108 return new_raw_count;
112 * Find and validate any extra registers to set up.
114 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
116 struct hw_perf_event_extra *reg;
117 struct extra_reg *er;
119 reg = &event->hw.extra_reg;
121 if (!x86_pmu.extra_regs)
124 for (er = x86_pmu.extra_regs; er->msr; er++) {
125 if (er->event != (config & er->config_mask))
127 if (event->attr.config1 & ~er->valid_mask)
131 reg->config = event->attr.config1;
138 static atomic_t active_events;
139 static DEFINE_MUTEX(pmc_reserve_mutex);
141 #ifdef CONFIG_X86_LOCAL_APIC
143 static bool reserve_pmc_hardware(void)
147 for (i = 0; i < x86_pmu.num_counters; i++) {
148 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
152 for (i = 0; i < x86_pmu.num_counters; i++) {
153 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
160 for (i--; i >= 0; i--)
161 release_evntsel_nmi(x86_pmu_config_addr(i));
163 i = x86_pmu.num_counters;
166 for (i--; i >= 0; i--)
167 release_perfctr_nmi(x86_pmu_event_addr(i));
172 static void release_pmc_hardware(void)
176 for (i = 0; i < x86_pmu.num_counters; i++) {
177 release_perfctr_nmi(x86_pmu_event_addr(i));
178 release_evntsel_nmi(x86_pmu_config_addr(i));
184 static bool reserve_pmc_hardware(void) { return true; }
185 static void release_pmc_hardware(void) {}
189 static bool check_hw_exists(void)
191 u64 val, val_new = 0;
195 * Check to see if the BIOS enabled any of the counters, if so
198 for (i = 0; i < x86_pmu.num_counters; i++) {
199 reg = x86_pmu_config_addr(i);
200 ret = rdmsrl_safe(reg, &val);
203 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
207 if (x86_pmu.num_counters_fixed) {
208 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
209 ret = rdmsrl_safe(reg, &val);
212 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
213 if (val & (0x03 << i*4))
219 * Now write a value and read it back to see if it matches,
220 * this is needed to detect certain hardware emulators (qemu/kvm)
221 * that don't trap on the MSR access and always return 0s.
224 ret = checking_wrmsrl(x86_pmu_event_addr(0), val);
225 ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new);
226 if (ret || val != val_new)
233 * We still allow the PMU driver to operate:
235 printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
236 printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val);
241 printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
246 static void hw_perf_event_destroy(struct perf_event *event)
248 if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
249 release_pmc_hardware();
250 release_ds_buffers();
251 mutex_unlock(&pmc_reserve_mutex);
255 static inline int x86_pmu_initialized(void)
257 return x86_pmu.handle_irq != NULL;
261 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
263 struct perf_event_attr *attr = &event->attr;
264 unsigned int cache_type, cache_op, cache_result;
267 config = attr->config;
269 cache_type = (config >> 0) & 0xff;
270 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
273 cache_op = (config >> 8) & 0xff;
274 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
277 cache_result = (config >> 16) & 0xff;
278 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
281 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
290 attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
291 return x86_pmu_extra_regs(val, event);
294 int x86_setup_perfctr(struct perf_event *event)
296 struct perf_event_attr *attr = &event->attr;
297 struct hw_perf_event *hwc = &event->hw;
300 if (!is_sampling_event(event)) {
301 hwc->sample_period = x86_pmu.max_period;
302 hwc->last_period = hwc->sample_period;
303 local64_set(&hwc->period_left, hwc->sample_period);
306 * If we have a PMU initialized but no APIC
307 * interrupts, we cannot sample hardware
308 * events (user-space has to fall back and
309 * sample via a hrtimer based software event):
315 if (attr->type == PERF_TYPE_RAW)
316 return x86_pmu_extra_regs(event->attr.config, event);
318 if (attr->type == PERF_TYPE_HW_CACHE)
319 return set_ext_hw_attr(hwc, event);
321 if (attr->config >= x86_pmu.max_events)
327 config = x86_pmu.event_map(attr->config);
338 if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
339 !attr->freq && hwc->sample_period == 1) {
340 /* BTS is not supported by this architecture. */
341 if (!x86_pmu.bts_active)
344 /* BTS is currently only allowed for user-mode. */
345 if (!attr->exclude_kernel)
349 hwc->config |= config;
354 int x86_pmu_hw_config(struct perf_event *event)
356 if (event->attr.precise_ip) {
359 /* Support for constant skid */
360 if (x86_pmu.pebs_active) {
363 /* Support for IP fixup */
368 if (event->attr.precise_ip > precise)
374 * (keep 'enabled' bit clear for now)
376 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
379 * Count user and OS events unless requested not to
381 if (!event->attr.exclude_user)
382 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
383 if (!event->attr.exclude_kernel)
384 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
386 if (event->attr.type == PERF_TYPE_RAW)
387 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
389 return x86_setup_perfctr(event);
393 * Setup the hardware configuration for a given attr_type
395 static int __x86_pmu_event_init(struct perf_event *event)
399 if (!x86_pmu_initialized())
403 if (!atomic_inc_not_zero(&active_events)) {
404 mutex_lock(&pmc_reserve_mutex);
405 if (atomic_read(&active_events) == 0) {
406 if (!reserve_pmc_hardware())
409 reserve_ds_buffers();
412 atomic_inc(&active_events);
413 mutex_unlock(&pmc_reserve_mutex);
418 event->destroy = hw_perf_event_destroy;
421 event->hw.last_cpu = -1;
422 event->hw.last_tag = ~0ULL;
425 event->hw.extra_reg.idx = EXTRA_REG_NONE;
427 return x86_pmu.hw_config(event);
430 void x86_pmu_disable_all(void)
432 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
435 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
438 if (!test_bit(idx, cpuc->active_mask))
440 rdmsrl(x86_pmu_config_addr(idx), val);
441 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
443 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
444 wrmsrl(x86_pmu_config_addr(idx), val);
448 static void x86_pmu_disable(struct pmu *pmu)
450 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
452 if (!x86_pmu_initialized())
462 x86_pmu.disable_all();
465 void x86_pmu_enable_all(int added)
467 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
470 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
471 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
473 if (!test_bit(idx, cpuc->active_mask))
476 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
480 static struct pmu pmu;
482 static inline int is_x86_event(struct perf_event *event)
484 return event->pmu == &pmu;
487 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
489 struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
490 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
491 int i, j, w, wmax, num = 0;
492 struct hw_perf_event *hwc;
494 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
496 for (i = 0; i < n; i++) {
497 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
502 * fastpath, try to reuse previous register
504 for (i = 0; i < n; i++) {
505 hwc = &cpuc->event_list[i]->hw;
512 /* constraint still honored */
513 if (!test_bit(hwc->idx, c->idxmsk))
516 /* not already used */
517 if (test_bit(hwc->idx, used_mask))
520 __set_bit(hwc->idx, used_mask);
522 assign[i] = hwc->idx;
531 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
534 * weight = number of possible counters
536 * 1 = most constrained, only works on one counter
537 * wmax = least constrained, works on any counter
539 * assign events to counters starting with most
540 * constrained events.
542 wmax = x86_pmu.num_counters;
545 * when fixed event counters are present,
546 * wmax is incremented by 1 to account
547 * for one more choice
549 if (x86_pmu.num_counters_fixed)
552 for (w = 1, num = n; num && w <= wmax; w++) {
554 for (i = 0; num && i < n; i++) {
556 hwc = &cpuc->event_list[i]->hw;
561 for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
562 if (!test_bit(j, used_mask))
566 if (j == X86_PMC_IDX_MAX)
569 __set_bit(j, used_mask);
578 * scheduling failed or is just a simulation,
579 * free resources if necessary
581 if (!assign || num) {
582 for (i = 0; i < n; i++) {
583 if (x86_pmu.put_event_constraints)
584 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
587 return num ? -EINVAL : 0;
591 * dogrp: true if must collect siblings events (group)
592 * returns total number of events and error code
594 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
596 struct perf_event *event;
599 max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
601 /* current number of events already accepted */
604 if (is_x86_event(leader)) {
607 cpuc->event_list[n] = leader;
613 list_for_each_entry(event, &leader->sibling_list, group_entry) {
614 if (!is_x86_event(event) ||
615 event->state <= PERF_EVENT_STATE_OFF)
621 cpuc->event_list[n] = event;
627 static inline void x86_assign_hw_event(struct perf_event *event,
628 struct cpu_hw_events *cpuc, int i)
630 struct hw_perf_event *hwc = &event->hw;
632 hwc->idx = cpuc->assign[i];
633 hwc->last_cpu = smp_processor_id();
634 hwc->last_tag = ++cpuc->tags[i];
636 if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
637 hwc->config_base = 0;
639 } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
640 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
641 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - X86_PMC_IDX_FIXED);
643 hwc->config_base = x86_pmu_config_addr(hwc->idx);
644 hwc->event_base = x86_pmu_event_addr(hwc->idx);
648 static inline int match_prev_assignment(struct hw_perf_event *hwc,
649 struct cpu_hw_events *cpuc,
652 return hwc->idx == cpuc->assign[i] &&
653 hwc->last_cpu == smp_processor_id() &&
654 hwc->last_tag == cpuc->tags[i];
657 static void x86_pmu_start(struct perf_event *event, int flags);
659 static void x86_pmu_enable(struct pmu *pmu)
661 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
662 struct perf_event *event;
663 struct hw_perf_event *hwc;
664 int i, added = cpuc->n_added;
666 if (!x86_pmu_initialized())
673 int n_running = cpuc->n_events - cpuc->n_added;
675 * apply assignment obtained either from
676 * hw_perf_group_sched_in() or x86_pmu_enable()
678 * step1: save events moving to new counters
679 * step2: reprogram moved events into new counters
681 for (i = 0; i < n_running; i++) {
682 event = cpuc->event_list[i];
686 * we can avoid reprogramming counter if:
687 * - assigned same counter as last time
688 * - running on same CPU as last time
689 * - no other event has used the counter since
691 if (hwc->idx == -1 ||
692 match_prev_assignment(hwc, cpuc, i))
696 * Ensure we don't accidentally enable a stopped
697 * counter simply because we rescheduled.
699 if (hwc->state & PERF_HES_STOPPED)
700 hwc->state |= PERF_HES_ARCH;
702 x86_pmu_stop(event, PERF_EF_UPDATE);
705 for (i = 0; i < cpuc->n_events; i++) {
706 event = cpuc->event_list[i];
709 if (!match_prev_assignment(hwc, cpuc, i))
710 x86_assign_hw_event(event, cpuc, i);
711 else if (i < n_running)
714 if (hwc->state & PERF_HES_ARCH)
717 x86_pmu_start(event, PERF_EF_RELOAD);
720 perf_events_lapic_init();
726 x86_pmu.enable_all(added);
729 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
732 * Set the next IRQ period, based on the hwc->period_left value.
733 * To be called with the event disabled in hw:
735 int x86_perf_event_set_period(struct perf_event *event)
737 struct hw_perf_event *hwc = &event->hw;
738 s64 left = local64_read(&hwc->period_left);
739 s64 period = hwc->sample_period;
740 int ret = 0, idx = hwc->idx;
742 if (idx == X86_PMC_IDX_FIXED_BTS)
746 * If we are way outside a reasonable range then just skip forward:
748 if (unlikely(left <= -period)) {
750 local64_set(&hwc->period_left, left);
751 hwc->last_period = period;
755 if (unlikely(left <= 0)) {
757 local64_set(&hwc->period_left, left);
758 hwc->last_period = period;
762 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
764 if (unlikely(left < 2))
767 if (left > x86_pmu.max_period)
768 left = x86_pmu.max_period;
770 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
773 * The hw event starts counting from this event offset,
774 * mark it to be able to extra future deltas:
776 local64_set(&hwc->prev_count, (u64)-left);
778 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
781 * Due to erratum on certan cpu we need
782 * a second write to be sure the register
783 * is updated properly
785 if (x86_pmu.perfctr_second_write) {
786 wrmsrl(hwc->event_base,
787 (u64)(-left) & x86_pmu.cntval_mask);
790 perf_event_update_userpage(event);
795 void x86_pmu_enable_event(struct perf_event *event)
797 if (__this_cpu_read(cpu_hw_events.enabled))
798 __x86_pmu_enable_event(&event->hw,
799 ARCH_PERFMON_EVENTSEL_ENABLE);
803 * Add a single event to the PMU.
805 * The event is added to the group of enabled events
806 * but only if it can be scehduled with existing events.
808 static int x86_pmu_add(struct perf_event *event, int flags)
810 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
811 struct hw_perf_event *hwc;
812 int assign[X86_PMC_IDX_MAX];
817 perf_pmu_disable(event->pmu);
819 ret = n = collect_events(cpuc, event, false);
823 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
824 if (!(flags & PERF_EF_START))
825 hwc->state |= PERF_HES_ARCH;
828 * If group events scheduling transaction was started,
829 * skip the schedulability test here, it will be performed
830 * at commit time (->commit_txn) as a whole
832 if (cpuc->group_flag & PERF_EVENT_TXN)
835 ret = x86_pmu.schedule_events(cpuc, n, assign);
839 * copy new assignment, now we know it is possible
840 * will be used by hw_perf_enable()
842 memcpy(cpuc->assign, assign, n*sizeof(int));
846 cpuc->n_added += n - n0;
847 cpuc->n_txn += n - n0;
851 perf_pmu_enable(event->pmu);
855 static void x86_pmu_start(struct perf_event *event, int flags)
857 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
858 int idx = event->hw.idx;
860 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
863 if (WARN_ON_ONCE(idx == -1))
866 if (flags & PERF_EF_RELOAD) {
867 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
868 x86_perf_event_set_period(event);
873 cpuc->events[idx] = event;
874 __set_bit(idx, cpuc->active_mask);
875 __set_bit(idx, cpuc->running);
876 x86_pmu.enable(event);
877 perf_event_update_userpage(event);
880 void perf_event_print_debug(void)
882 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
884 struct cpu_hw_events *cpuc;
888 if (!x86_pmu.num_counters)
891 local_irq_save(flags);
893 cpu = smp_processor_id();
894 cpuc = &per_cpu(cpu_hw_events, cpu);
896 if (x86_pmu.version >= 2) {
897 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
898 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
899 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
900 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
901 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
904 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
905 pr_info("CPU#%d: status: %016llx\n", cpu, status);
906 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
907 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
908 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
910 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
912 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
913 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
914 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
916 prev_left = per_cpu(pmc_prev_left[idx], cpu);
918 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
920 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
921 cpu, idx, pmc_count);
922 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
923 cpu, idx, prev_left);
925 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
926 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
928 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
929 cpu, idx, pmc_count);
931 local_irq_restore(flags);
934 void x86_pmu_stop(struct perf_event *event, int flags)
936 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
937 struct hw_perf_event *hwc = &event->hw;
939 if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
940 x86_pmu.disable(event);
941 cpuc->events[hwc->idx] = NULL;
942 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
943 hwc->state |= PERF_HES_STOPPED;
946 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
948 * Drain the remaining delta count out of a event
949 * that we are disabling:
951 x86_perf_event_update(event);
952 hwc->state |= PERF_HES_UPTODATE;
956 static void x86_pmu_del(struct perf_event *event, int flags)
958 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
962 * If we're called during a txn, we don't need to do anything.
963 * The events never got scheduled and ->cancel_txn will truncate
966 if (cpuc->group_flag & PERF_EVENT_TXN)
969 x86_pmu_stop(event, PERF_EF_UPDATE);
971 for (i = 0; i < cpuc->n_events; i++) {
972 if (event == cpuc->event_list[i]) {
974 if (i >= cpuc->n_events - cpuc->n_added)
977 if (x86_pmu.put_event_constraints)
978 x86_pmu.put_event_constraints(cpuc, event);
980 while (++i < cpuc->n_events)
981 cpuc->event_list[i-1] = cpuc->event_list[i];
987 perf_event_update_userpage(event);
990 int x86_pmu_handle_irq(struct pt_regs *regs)
992 struct perf_sample_data data;
993 struct cpu_hw_events *cpuc;
994 struct perf_event *event;
995 int idx, handled = 0;
998 perf_sample_data_init(&data, 0);
1000 cpuc = &__get_cpu_var(cpu_hw_events);
1003 * Some chipsets need to unmask the LVTPC in a particular spot
1004 * inside the nmi handler. As a result, the unmasking was pushed
1005 * into all the nmi handlers.
1007 * This generic handler doesn't seem to have any issues where the
1008 * unmasking occurs so it was left at the top.
1010 apic_write(APIC_LVTPC, APIC_DM_NMI);
1012 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1013 if (!test_bit(idx, cpuc->active_mask)) {
1015 * Though we deactivated the counter some cpus
1016 * might still deliver spurious interrupts still
1017 * in flight. Catch them:
1019 if (__test_and_clear_bit(idx, cpuc->running))
1024 event = cpuc->events[idx];
1026 val = x86_perf_event_update(event);
1027 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1034 data.period = event->hw.last_period;
1036 if (!x86_perf_event_set_period(event))
1039 if (perf_event_overflow(event, &data, regs))
1040 x86_pmu_stop(event, 0);
1044 inc_irq_stat(apic_perf_irqs);
1049 void perf_events_lapic_init(void)
1051 if (!x86_pmu.apic || !x86_pmu_initialized())
1055 * Always use NMI for PMU
1057 apic_write(APIC_LVTPC, APIC_DM_NMI);
1060 static int __kprobes
1061 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1063 if (!atomic_read(&active_events))
1066 return x86_pmu.handle_irq(regs);
1069 struct event_constraint emptyconstraint;
1070 struct event_constraint unconstrained;
1072 static int __cpuinit
1073 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1075 unsigned int cpu = (long)hcpu;
1076 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1077 int ret = NOTIFY_OK;
1079 switch (action & ~CPU_TASKS_FROZEN) {
1080 case CPU_UP_PREPARE:
1081 cpuc->kfree_on_online = NULL;
1082 if (x86_pmu.cpu_prepare)
1083 ret = x86_pmu.cpu_prepare(cpu);
1087 if (x86_pmu.cpu_starting)
1088 x86_pmu.cpu_starting(cpu);
1092 kfree(cpuc->kfree_on_online);
1096 if (x86_pmu.cpu_dying)
1097 x86_pmu.cpu_dying(cpu);
1100 case CPU_UP_CANCELED:
1102 if (x86_pmu.cpu_dead)
1103 x86_pmu.cpu_dead(cpu);
1113 static void __init pmu_check_apic(void)
1119 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1120 pr_info("no hardware sampling interrupt available.\n");
1123 static int __init init_hw_perf_events(void)
1125 struct event_constraint *c;
1128 pr_info("Performance Events: ");
1130 switch (boot_cpu_data.x86_vendor) {
1131 case X86_VENDOR_INTEL:
1132 err = intel_pmu_init();
1134 case X86_VENDOR_AMD:
1135 err = amd_pmu_init();
1141 pr_cont("no PMU driver, software events only.\n");
1147 /* sanity check that the hardware exists or is emulated */
1148 if (!check_hw_exists())
1151 pr_cont("%s PMU driver.\n", x86_pmu.name);
1156 if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1157 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1158 x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1159 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1161 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1163 if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1164 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1165 x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1166 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1169 x86_pmu.intel_ctrl |=
1170 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1172 perf_events_lapic_init();
1173 register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1175 unconstrained = (struct event_constraint)
1176 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1177 0, x86_pmu.num_counters);
1179 if (x86_pmu.event_constraints) {
1180 for_each_event_constraint(c, x86_pmu.event_constraints) {
1181 if (c->cmask != X86_RAW_EVENT_MASK)
1184 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1185 c->weight += x86_pmu.num_counters;
1189 pr_info("... version: %d\n", x86_pmu.version);
1190 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
1191 pr_info("... generic registers: %d\n", x86_pmu.num_counters);
1192 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
1193 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1194 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed);
1195 pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl);
1197 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1198 perf_cpu_notifier(x86_pmu_notifier);
1202 early_initcall(init_hw_perf_events);
1204 static inline void x86_pmu_read(struct perf_event *event)
1206 x86_perf_event_update(event);
1210 * Start group events scheduling transaction
1211 * Set the flag to make pmu::enable() not perform the
1212 * schedulability test, it will be performed at commit time
1214 static void x86_pmu_start_txn(struct pmu *pmu)
1216 perf_pmu_disable(pmu);
1217 __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
1218 __this_cpu_write(cpu_hw_events.n_txn, 0);
1222 * Stop group events scheduling transaction
1223 * Clear the flag and pmu::enable() will perform the
1224 * schedulability test.
1226 static void x86_pmu_cancel_txn(struct pmu *pmu)
1228 __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1230 * Truncate the collected events.
1232 __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1233 __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1234 perf_pmu_enable(pmu);
1238 * Commit group events scheduling transaction
1239 * Perform the group schedulability test as a whole
1240 * Return 0 if success
1242 static int x86_pmu_commit_txn(struct pmu *pmu)
1244 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1245 int assign[X86_PMC_IDX_MAX];
1250 if (!x86_pmu_initialized())
1253 ret = x86_pmu.schedule_events(cpuc, n, assign);
1258 * copy new assignment, now we know it is possible
1259 * will be used by hw_perf_enable()
1261 memcpy(cpuc->assign, assign, n*sizeof(int));
1263 cpuc->group_flag &= ~PERF_EVENT_TXN;
1264 perf_pmu_enable(pmu);
1268 * a fake_cpuc is used to validate event groups. Due to
1269 * the extra reg logic, we need to also allocate a fake
1270 * per_core and per_cpu structure. Otherwise, group events
1271 * using extra reg may conflict without the kernel being
1272 * able to catch this when the last event gets added to
1275 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1277 kfree(cpuc->shared_regs);
1281 static struct cpu_hw_events *allocate_fake_cpuc(void)
1283 struct cpu_hw_events *cpuc;
1284 int cpu = raw_smp_processor_id();
1286 cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1288 return ERR_PTR(-ENOMEM);
1290 /* only needed, if we have extra_regs */
1291 if (x86_pmu.extra_regs) {
1292 cpuc->shared_regs = allocate_shared_regs(cpu);
1293 if (!cpuc->shared_regs)
1298 free_fake_cpuc(cpuc);
1299 return ERR_PTR(-ENOMEM);
1303 * validate that we can schedule this event
1305 static int validate_event(struct perf_event *event)
1307 struct cpu_hw_events *fake_cpuc;
1308 struct event_constraint *c;
1311 fake_cpuc = allocate_fake_cpuc();
1312 if (IS_ERR(fake_cpuc))
1313 return PTR_ERR(fake_cpuc);
1315 c = x86_pmu.get_event_constraints(fake_cpuc, event);
1317 if (!c || !c->weight)
1320 if (x86_pmu.put_event_constraints)
1321 x86_pmu.put_event_constraints(fake_cpuc, event);
1323 free_fake_cpuc(fake_cpuc);
1329 * validate a single event group
1331 * validation include:
1332 * - check events are compatible which each other
1333 * - events do not compete for the same counter
1334 * - number of events <= number of counters
1336 * validation ensures the group can be loaded onto the
1337 * PMU if it was the only group available.
1339 static int validate_group(struct perf_event *event)
1341 struct perf_event *leader = event->group_leader;
1342 struct cpu_hw_events *fake_cpuc;
1343 int ret = -EINVAL, n;
1345 fake_cpuc = allocate_fake_cpuc();
1346 if (IS_ERR(fake_cpuc))
1347 return PTR_ERR(fake_cpuc);
1349 * the event is not yet connected with its
1350 * siblings therefore we must first collect
1351 * existing siblings, then add the new event
1352 * before we can simulate the scheduling
1354 n = collect_events(fake_cpuc, leader, true);
1358 fake_cpuc->n_events = n;
1359 n = collect_events(fake_cpuc, event, false);
1363 fake_cpuc->n_events = n;
1365 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1368 free_fake_cpuc(fake_cpuc);
1372 static int x86_pmu_event_init(struct perf_event *event)
1377 switch (event->attr.type) {
1379 case PERF_TYPE_HARDWARE:
1380 case PERF_TYPE_HW_CACHE:
1387 err = __x86_pmu_event_init(event);
1390 * we temporarily connect event to its pmu
1391 * such that validate_group() can classify
1392 * it as an x86 event using is_x86_event()
1397 if (event->group_leader != event)
1398 err = validate_group(event);
1400 err = validate_event(event);
1406 event->destroy(event);
1412 static struct pmu pmu = {
1413 .pmu_enable = x86_pmu_enable,
1414 .pmu_disable = x86_pmu_disable,
1416 .event_init = x86_pmu_event_init,
1420 .start = x86_pmu_start,
1421 .stop = x86_pmu_stop,
1422 .read = x86_pmu_read,
1424 .start_txn = x86_pmu_start_txn,
1425 .cancel_txn = x86_pmu_cancel_txn,
1426 .commit_txn = x86_pmu_commit_txn,
1433 static int backtrace_stack(void *data, char *name)
1438 static void backtrace_address(void *data, unsigned long addr, int reliable)
1440 struct perf_callchain_entry *entry = data;
1442 perf_callchain_store(entry, addr);
1445 static const struct stacktrace_ops backtrace_ops = {
1446 .stack = backtrace_stack,
1447 .address = backtrace_address,
1448 .walk_stack = print_context_stack_bp,
1452 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1454 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1455 /* TODO: We don't support guest os callchain now */
1459 perf_callchain_store(entry, regs->ip);
1461 dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
1465 valid_user_frame(const void __user *fp, unsigned long size)
1467 return (__range_not_ok(fp, size, TASK_SIZE) == 0);
1470 #ifdef CONFIG_COMPAT
1472 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1474 /* 32-bit process in 64-bit kernel. */
1475 struct stack_frame_ia32 frame;
1476 const void __user *fp;
1478 if (!test_thread_flag(TIF_IA32))
1481 fp = compat_ptr(regs->bp);
1482 while (entry->nr < PERF_MAX_STACK_DEPTH) {
1483 unsigned long bytes;
1484 frame.next_frame = 0;
1485 frame.return_address = 0;
1487 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1488 if (bytes != sizeof(frame))
1491 if (fp < compat_ptr(regs->sp))
1494 if (!valid_user_frame(fp, sizeof(frame)))
1497 perf_callchain_store(entry, frame.return_address);
1498 fp = compat_ptr(frame.next_frame);
1504 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1511 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1513 struct stack_frame frame;
1514 const void __user *fp;
1516 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1517 /* TODO: We don't support guest os callchain now */
1521 fp = (void __user *)regs->bp;
1523 perf_callchain_store(entry, regs->ip);
1528 if (perf_callchain_user32(regs, entry))
1531 while (entry->nr < PERF_MAX_STACK_DEPTH) {
1532 unsigned long bytes;
1533 frame.next_frame = NULL;
1534 frame.return_address = 0;
1536 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1537 if (bytes != sizeof(frame))
1540 if ((unsigned long)fp < regs->sp)
1543 if (!valid_user_frame(fp, sizeof(frame)))
1546 perf_callchain_store(entry, frame.return_address);
1547 fp = frame.next_frame;
1551 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1555 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1556 ip = perf_guest_cbs->get_guest_ip();
1558 ip = instruction_pointer(regs);
1563 unsigned long perf_misc_flags(struct pt_regs *regs)
1567 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1568 if (perf_guest_cbs->is_user_mode())
1569 misc |= PERF_RECORD_MISC_GUEST_USER;
1571 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1573 if (user_mode(regs))
1574 misc |= PERF_RECORD_MISC_USER;
1576 misc |= PERF_RECORD_MISC_KERNEL;
1579 if (regs->flags & PERF_EFLAGS_EXACT)
1580 misc |= PERF_RECORD_MISC_EXACT_IP;