2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/highmem.h>
25 #include <linux/cpu.h>
26 #include <linux/bitops.h>
29 #include <asm/stacktrace.h>
34 #define wrmsrl(msr, val) \
36 trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
37 (unsigned long)(val)); \
38 native_write_msr((msr), (u32)((u64)(val)), \
39 (u32)((u64)(val) >> 32)); \
44 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
47 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
49 unsigned long offset, addr = (unsigned long)from;
50 int type = in_nmi() ? KM_NMI : KM_IRQ0;
51 unsigned long size, len = 0;
57 ret = __get_user_pages_fast(addr, 1, 0, &page);
61 offset = addr & (PAGE_SIZE - 1);
62 size = min(PAGE_SIZE - offset, n - len);
64 map = kmap_atomic(page, type);
65 memcpy(to, map+offset, size);
66 kunmap_atomic(map, type);
78 static u64 perf_event_mask __read_mostly;
80 struct event_constraint {
82 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
91 int nb_id; /* NorthBridge id */
92 int refcnt; /* reference count */
93 struct perf_event *owners[X86_PMC_IDX_MAX];
94 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
97 #define MAX_LBR_ENTRIES 16
99 struct cpu_hw_events {
101 * Generic x86 PMC bits
103 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
104 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
105 unsigned long interrupts;
110 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
111 u64 tags[X86_PMC_IDX_MAX];
112 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
115 * Intel DebugStore bits
117 struct debug_store *ds;
125 struct perf_branch_stack lbr_stack;
126 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
131 struct amd_nb *amd_nb;
134 #define __EVENT_CONSTRAINT(c, n, m, w) {\
135 { .idxmsk64 = (n) }, \
141 #define EVENT_CONSTRAINT(c, n, m) \
142 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
145 * Constraint on the Event code.
147 #define INTEL_EVENT_CONSTRAINT(c, n) \
148 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVTSEL_MASK)
151 * Constraint on the Event code + UMask + fixed-mask
153 #define FIXED_EVENT_CONSTRAINT(c, n) \
154 EVENT_CONSTRAINT(c, (1ULL << (32+n)), INTEL_ARCH_FIXED_MASK)
157 * Constraint on the Event code + UMask
159 #define PEBS_EVENT_CONSTRAINT(c, n) \
160 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
162 #define EVENT_CONSTRAINT_END \
163 EVENT_CONSTRAINT(0, 0, 0)
165 #define for_each_event_constraint(e, c) \
166 for ((e) = (c); (e)->cmask; (e)++)
168 union perf_capabilities {
172 u64 pebs_arch_reg : 1;
180 * struct x86_pmu - generic x86 pmu
184 * Generic x86 PMC bits
188 int (*handle_irq)(struct pt_regs *);
189 void (*disable_all)(void);
190 void (*enable_all)(void);
191 void (*enable)(struct perf_event *);
192 void (*disable)(struct perf_event *);
193 int (*hw_config)(struct perf_event_attr *attr, struct hw_perf_event *hwc);
194 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
197 u64 (*event_map)(int);
198 u64 (*raw_event)(u64);
201 int num_events_fixed;
206 struct event_constraint *
207 (*get_event_constraints)(struct cpu_hw_events *cpuc,
208 struct perf_event *event);
210 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
211 struct perf_event *event);
212 struct event_constraint *event_constraints;
213 void (*quirks)(void);
215 void (*cpu_prepare)(int cpu);
216 void (*cpu_starting)(int cpu);
217 void (*cpu_dying)(int cpu);
218 void (*cpu_dead)(int cpu);
221 * Intel Arch Perfmon v2+
224 union perf_capabilities intel_cap;
227 * Intel DebugStore bits
230 int pebs_record_size;
231 void (*drain_pebs)(struct pt_regs *regs);
232 struct event_constraint *pebs_constraints;
237 unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
238 int lbr_nr; /* hardware stack size */
241 static struct x86_pmu x86_pmu __read_mostly;
243 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
247 static int x86_perf_event_set_period(struct perf_event *event);
250 * Generalized hw caching related hw_event table, filled
251 * in on a per model basis. A value of 0 means
252 * 'not supported', -1 means 'hw_event makes no sense on
253 * this CPU', any other value means the raw hw_event
257 #define C(x) PERF_COUNT_HW_CACHE_##x
259 static u64 __read_mostly hw_cache_event_ids
260 [PERF_COUNT_HW_CACHE_MAX]
261 [PERF_COUNT_HW_CACHE_OP_MAX]
262 [PERF_COUNT_HW_CACHE_RESULT_MAX];
265 * Propagate event elapsed time into the generic event.
266 * Can only be executed on the CPU where the event is active.
267 * Returns the delta events processed.
270 x86_perf_event_update(struct perf_event *event)
272 struct hw_perf_event *hwc = &event->hw;
273 int shift = 64 - x86_pmu.event_bits;
274 u64 prev_raw_count, new_raw_count;
278 if (idx == X86_PMC_IDX_FIXED_BTS)
282 * Careful: an NMI might modify the previous event value.
284 * Our tactic to handle this is to first atomically read and
285 * exchange a new raw count - then add that new-prev delta
286 * count to the generic event atomically:
289 prev_raw_count = atomic64_read(&hwc->prev_count);
290 rdmsrl(hwc->event_base + idx, new_raw_count);
292 if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
293 new_raw_count) != prev_raw_count)
297 * Now we have the new raw value and have updated the prev
298 * timestamp already. We can now calculate the elapsed delta
299 * (event-)time and add that to the generic event.
301 * Careful, not all hw sign-extends above the physical width
304 delta = (new_raw_count << shift) - (prev_raw_count << shift);
307 atomic64_add(delta, &event->count);
308 atomic64_sub(delta, &hwc->period_left);
310 return new_raw_count;
313 static atomic_t active_events;
314 static DEFINE_MUTEX(pmc_reserve_mutex);
316 static bool reserve_pmc_hardware(void)
318 #ifdef CONFIG_X86_LOCAL_APIC
321 if (nmi_watchdog == NMI_LOCAL_APIC)
322 disable_lapic_nmi_watchdog();
324 for (i = 0; i < x86_pmu.num_events; i++) {
325 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
329 for (i = 0; i < x86_pmu.num_events; i++) {
330 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
337 #ifdef CONFIG_X86_LOCAL_APIC
339 for (i--; i >= 0; i--)
340 release_evntsel_nmi(x86_pmu.eventsel + i);
342 i = x86_pmu.num_events;
345 for (i--; i >= 0; i--)
346 release_perfctr_nmi(x86_pmu.perfctr + i);
348 if (nmi_watchdog == NMI_LOCAL_APIC)
349 enable_lapic_nmi_watchdog();
355 static void release_pmc_hardware(void)
357 #ifdef CONFIG_X86_LOCAL_APIC
360 for (i = 0; i < x86_pmu.num_events; i++) {
361 release_perfctr_nmi(x86_pmu.perfctr + i);
362 release_evntsel_nmi(x86_pmu.eventsel + i);
365 if (nmi_watchdog == NMI_LOCAL_APIC)
366 enable_lapic_nmi_watchdog();
370 static int reserve_ds_buffers(void);
371 static void release_ds_buffers(void);
373 static void hw_perf_event_destroy(struct perf_event *event)
375 if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
376 release_pmc_hardware();
377 release_ds_buffers();
378 mutex_unlock(&pmc_reserve_mutex);
382 static inline int x86_pmu_initialized(void)
384 return x86_pmu.handle_irq != NULL;
388 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
390 unsigned int cache_type, cache_op, cache_result;
393 config = attr->config;
395 cache_type = (config >> 0) & 0xff;
396 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
399 cache_op = (config >> 8) & 0xff;
400 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
403 cache_result = (config >> 16) & 0xff;
404 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
407 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
420 static int x86_hw_config(struct perf_event_attr *attr, struct hw_perf_event *hwc)
424 * (keep 'enabled' bit clear for now)
426 hwc->config = ARCH_PERFMON_EVENTSEL_INT;
429 * Count user and OS events unless requested not to
431 if (!attr->exclude_user)
432 hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
433 if (!attr->exclude_kernel)
434 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
440 * Setup the hardware configuration for a given attr_type
442 static int __hw_perf_event_init(struct perf_event *event)
444 struct perf_event_attr *attr = &event->attr;
445 struct hw_perf_event *hwc = &event->hw;
449 if (!x86_pmu_initialized())
453 if (!atomic_inc_not_zero(&active_events)) {
454 mutex_lock(&pmc_reserve_mutex);
455 if (atomic_read(&active_events) == 0) {
456 if (!reserve_pmc_hardware())
459 err = reserve_ds_buffers();
462 atomic_inc(&active_events);
463 mutex_unlock(&pmc_reserve_mutex);
468 event->destroy = hw_perf_event_destroy;
472 hwc->last_tag = ~0ULL;
474 /* Processor specifics */
475 if (x86_pmu.hw_config(attr, hwc))
478 if (!hwc->sample_period) {
479 hwc->sample_period = x86_pmu.max_period;
480 hwc->last_period = hwc->sample_period;
481 atomic64_set(&hwc->period_left, hwc->sample_period);
484 * If we have a PMU initialized but no APIC
485 * interrupts, we cannot sample hardware
486 * events (user-space has to fall back and
487 * sample via a hrtimer based software event):
494 * Raw hw_event type provide the config in the hw_event structure
496 if (attr->type == PERF_TYPE_RAW) {
497 hwc->config |= x86_pmu.raw_event(attr->config);
498 if ((hwc->config & ARCH_PERFMON_EVENTSEL_ANY) &&
499 perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
504 if (attr->type == PERF_TYPE_HW_CACHE)
505 return set_ext_hw_attr(hwc, attr);
507 if (attr->config >= x86_pmu.max_events)
513 config = x86_pmu.event_map(attr->config);
524 if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
525 (hwc->sample_period == 1)) {
526 /* BTS is not supported by this architecture. */
530 /* BTS is currently only allowed for user-mode. */
531 if (!attr->exclude_kernel)
535 hwc->config |= config;
540 static void x86_pmu_disable_all(void)
542 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
545 for (idx = 0; idx < x86_pmu.num_events; idx++) {
548 if (!test_bit(idx, cpuc->active_mask))
550 rdmsrl(x86_pmu.eventsel + idx, val);
551 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
553 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
554 wrmsrl(x86_pmu.eventsel + idx, val);
558 void hw_perf_disable(void)
560 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
562 if (!x86_pmu_initialized())
572 x86_pmu.disable_all();
575 static void x86_pmu_enable_all(void)
577 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
580 for (idx = 0; idx < x86_pmu.num_events; idx++) {
581 struct perf_event *event = cpuc->events[idx];
584 if (!test_bit(idx, cpuc->active_mask))
587 val = event->hw.config;
588 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
589 wrmsrl(x86_pmu.eventsel + idx, val);
593 static const struct pmu pmu;
595 static inline int is_x86_event(struct perf_event *event)
597 return event->pmu == &pmu;
600 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
602 struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
603 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
604 int i, j, w, wmax, num = 0;
605 struct hw_perf_event *hwc;
607 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
609 for (i = 0; i < n; i++) {
610 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
615 * fastpath, try to reuse previous register
617 for (i = 0; i < n; i++) {
618 hwc = &cpuc->event_list[i]->hw;
625 /* constraint still honored */
626 if (!test_bit(hwc->idx, c->idxmsk))
629 /* not already used */
630 if (test_bit(hwc->idx, used_mask))
633 __set_bit(hwc->idx, used_mask);
635 assign[i] = hwc->idx;
644 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
647 * weight = number of possible counters
649 * 1 = most constrained, only works on one counter
650 * wmax = least constrained, works on any counter
652 * assign events to counters starting with most
653 * constrained events.
655 wmax = x86_pmu.num_events;
658 * when fixed event counters are present,
659 * wmax is incremented by 1 to account
660 * for one more choice
662 if (x86_pmu.num_events_fixed)
665 for (w = 1, num = n; num && w <= wmax; w++) {
667 for (i = 0; num && i < n; i++) {
669 hwc = &cpuc->event_list[i]->hw;
674 for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
675 if (!test_bit(j, used_mask))
679 if (j == X86_PMC_IDX_MAX)
682 __set_bit(j, used_mask);
691 * scheduling failed or is just a simulation,
692 * free resources if necessary
694 if (!assign || num) {
695 for (i = 0; i < n; i++) {
696 if (x86_pmu.put_event_constraints)
697 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
700 return num ? -ENOSPC : 0;
704 * dogrp: true if must collect siblings events (group)
705 * returns total number of events and error code
707 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
709 struct perf_event *event;
712 max_count = x86_pmu.num_events + x86_pmu.num_events_fixed;
714 /* current number of events already accepted */
717 if (is_x86_event(leader)) {
720 cpuc->event_list[n] = leader;
726 list_for_each_entry(event, &leader->sibling_list, group_entry) {
727 if (!is_x86_event(event) ||
728 event->state <= PERF_EVENT_STATE_OFF)
734 cpuc->event_list[n] = event;
740 static inline void x86_assign_hw_event(struct perf_event *event,
741 struct cpu_hw_events *cpuc, int i)
743 struct hw_perf_event *hwc = &event->hw;
745 hwc->idx = cpuc->assign[i];
746 hwc->last_cpu = smp_processor_id();
747 hwc->last_tag = ++cpuc->tags[i];
749 if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
750 hwc->config_base = 0;
752 } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
753 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
755 * We set it so that event_base + idx in wrmsr/rdmsr maps to
756 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
759 MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
761 hwc->config_base = x86_pmu.eventsel;
762 hwc->event_base = x86_pmu.perfctr;
766 static inline int match_prev_assignment(struct hw_perf_event *hwc,
767 struct cpu_hw_events *cpuc,
770 return hwc->idx == cpuc->assign[i] &&
771 hwc->last_cpu == smp_processor_id() &&
772 hwc->last_tag == cpuc->tags[i];
775 static int x86_pmu_start(struct perf_event *event);
776 static void x86_pmu_stop(struct perf_event *event);
778 void hw_perf_enable(void)
780 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
781 struct perf_event *event;
782 struct hw_perf_event *hwc;
785 if (!x86_pmu_initialized())
792 int n_running = cpuc->n_events - cpuc->n_added;
794 * apply assignment obtained either from
795 * hw_perf_group_sched_in() or x86_pmu_enable()
797 * step1: save events moving to new counters
798 * step2: reprogram moved events into new counters
800 for (i = 0; i < n_running; i++) {
802 event = cpuc->event_list[i];
806 * we can avoid reprogramming counter if:
807 * - assigned same counter as last time
808 * - running on same CPU as last time
809 * - no other event has used the counter since
811 if (hwc->idx == -1 ||
812 match_prev_assignment(hwc, cpuc, i))
820 for (i = 0; i < cpuc->n_events; i++) {
822 event = cpuc->event_list[i];
826 match_prev_assignment(hwc, cpuc, i))
830 x86_assign_hw_event(event, cpuc, i);
832 x86_pmu_start(event);
835 perf_events_lapic_init();
841 x86_pmu.enable_all();
844 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc)
846 wrmsrl(hwc->config_base + hwc->idx,
847 hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE);
850 static inline void x86_pmu_disable_event(struct perf_event *event)
852 struct hw_perf_event *hwc = &event->hw;
854 wrmsrl(hwc->config_base + hwc->idx, hwc->config);
857 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
860 * Set the next IRQ period, based on the hwc->period_left value.
861 * To be called with the event disabled in hw:
864 x86_perf_event_set_period(struct perf_event *event)
866 struct hw_perf_event *hwc = &event->hw;
867 s64 left = atomic64_read(&hwc->period_left);
868 s64 period = hwc->sample_period;
869 int ret = 0, idx = hwc->idx;
871 if (idx == X86_PMC_IDX_FIXED_BTS)
875 * If we are way outside a reasonable range then just skip forward:
877 if (unlikely(left <= -period)) {
879 atomic64_set(&hwc->period_left, left);
880 hwc->last_period = period;
884 if (unlikely(left <= 0)) {
886 atomic64_set(&hwc->period_left, left);
887 hwc->last_period = period;
891 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
893 if (unlikely(left < 2))
896 if (left > x86_pmu.max_period)
897 left = x86_pmu.max_period;
899 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
902 * The hw event starts counting from this event offset,
903 * mark it to be able to extra future deltas:
905 atomic64_set(&hwc->prev_count, (u64)-left);
907 wrmsrl(hwc->event_base + idx,
908 (u64)(-left) & x86_pmu.event_mask);
910 perf_event_update_userpage(event);
915 static void x86_pmu_enable_event(struct perf_event *event)
917 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
919 __x86_pmu_enable_event(&event->hw);
923 * activate a single event
925 * The event is added to the group of enabled events
926 * but only if it can be scehduled with existing events.
928 * Called with PMU disabled. If successful and return value 1,
929 * then guaranteed to call perf_enable() and hw_perf_enable()
931 static int x86_pmu_enable(struct perf_event *event)
933 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
934 struct hw_perf_event *hwc;
935 int assign[X86_PMC_IDX_MAX];
941 n = collect_events(cpuc, event, false);
945 ret = x86_pmu.schedule_events(cpuc, n, assign);
949 * copy new assignment, now we know it is possible
950 * will be used by hw_perf_enable()
952 memcpy(cpuc->assign, assign, n*sizeof(int));
955 cpuc->n_added += n - n0;
960 static int x86_pmu_start(struct perf_event *event)
962 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
963 int idx = event->hw.idx;
968 x86_perf_event_set_period(event);
969 cpuc->events[idx] = event;
970 __set_bit(idx, cpuc->active_mask);
971 x86_pmu.enable(event);
972 perf_event_update_userpage(event);
977 static void x86_pmu_unthrottle(struct perf_event *event)
979 int ret = x86_pmu_start(event);
983 void perf_event_print_debug(void)
985 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
987 struct cpu_hw_events *cpuc;
991 if (!x86_pmu.num_events)
994 local_irq_save(flags);
996 cpu = smp_processor_id();
997 cpuc = &per_cpu(cpu_hw_events, cpu);
999 if (x86_pmu.version >= 2) {
1000 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1001 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1002 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1003 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1004 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1007 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1008 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1009 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1010 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1011 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1013 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1015 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1016 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1017 rdmsrl(x86_pmu.perfctr + idx, pmc_count);
1019 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1021 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1022 cpu, idx, pmc_ctrl);
1023 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1024 cpu, idx, pmc_count);
1025 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1026 cpu, idx, prev_left);
1028 for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
1029 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1031 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1032 cpu, idx, pmc_count);
1034 local_irq_restore(flags);
1037 static void x86_pmu_stop(struct perf_event *event)
1039 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1040 struct hw_perf_event *hwc = &event->hw;
1043 if (!__test_and_clear_bit(idx, cpuc->active_mask))
1046 x86_pmu.disable(event);
1049 * Drain the remaining delta count out of a event
1050 * that we are disabling:
1052 x86_perf_event_update(event);
1054 cpuc->events[idx] = NULL;
1057 static void x86_pmu_disable(struct perf_event *event)
1059 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1062 x86_pmu_stop(event);
1064 for (i = 0; i < cpuc->n_events; i++) {
1065 if (event == cpuc->event_list[i]) {
1067 if (x86_pmu.put_event_constraints)
1068 x86_pmu.put_event_constraints(cpuc, event);
1070 while (++i < cpuc->n_events)
1071 cpuc->event_list[i-1] = cpuc->event_list[i];
1077 perf_event_update_userpage(event);
1080 static int x86_pmu_handle_irq(struct pt_regs *regs)
1082 struct perf_sample_data data;
1083 struct cpu_hw_events *cpuc;
1084 struct perf_event *event;
1085 struct hw_perf_event *hwc;
1086 int idx, handled = 0;
1089 perf_sample_data_init(&data, 0);
1091 cpuc = &__get_cpu_var(cpu_hw_events);
1093 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1094 if (!test_bit(idx, cpuc->active_mask))
1097 event = cpuc->events[idx];
1100 val = x86_perf_event_update(event);
1101 if (val & (1ULL << (x86_pmu.event_bits - 1)))
1108 data.period = event->hw.last_period;
1110 if (!x86_perf_event_set_period(event))
1113 if (perf_event_overflow(event, 1, &data, regs))
1114 x86_pmu_stop(event);
1118 inc_irq_stat(apic_perf_irqs);
1123 void smp_perf_pending_interrupt(struct pt_regs *regs)
1127 inc_irq_stat(apic_pending_irqs);
1128 perf_event_do_pending();
1132 void set_perf_event_pending(void)
1134 #ifdef CONFIG_X86_LOCAL_APIC
1135 if (!x86_pmu.apic || !x86_pmu_initialized())
1138 apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1142 void perf_events_lapic_init(void)
1144 #ifdef CONFIG_X86_LOCAL_APIC
1145 if (!x86_pmu.apic || !x86_pmu_initialized())
1149 * Always use NMI for PMU
1151 apic_write(APIC_LVTPC, APIC_DM_NMI);
1155 static int __kprobes
1156 perf_event_nmi_handler(struct notifier_block *self,
1157 unsigned long cmd, void *__args)
1159 struct die_args *args = __args;
1160 struct pt_regs *regs;
1162 if (!atomic_read(&active_events))
1176 #ifdef CONFIG_X86_LOCAL_APIC
1177 apic_write(APIC_LVTPC, APIC_DM_NMI);
1180 * Can't rely on the handled return value to say it was our NMI, two
1181 * events could trigger 'simultaneously' raising two back-to-back NMIs.
1183 * If the first NMI handles both, the latter will be empty and daze
1186 x86_pmu.handle_irq(regs);
1191 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1192 .notifier_call = perf_event_nmi_handler,
1197 static struct event_constraint unconstrained;
1198 static struct event_constraint emptyconstraint;
1200 static struct event_constraint *
1201 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1203 struct event_constraint *c;
1205 if (x86_pmu.event_constraints) {
1206 for_each_event_constraint(c, x86_pmu.event_constraints) {
1207 if ((event->hw.config & c->cmask) == c->code)
1212 return &unconstrained;
1215 static int x86_event_sched_in(struct perf_event *event,
1216 struct perf_cpu_context *cpuctx)
1220 event->state = PERF_EVENT_STATE_ACTIVE;
1221 event->oncpu = smp_processor_id();
1222 event->tstamp_running += event->ctx->time - event->tstamp_stopped;
1224 if (!is_x86_event(event))
1225 ret = event->pmu->enable(event);
1227 if (!ret && !is_software_event(event))
1228 cpuctx->active_oncpu++;
1230 if (!ret && event->attr.exclusive)
1231 cpuctx->exclusive = 1;
1236 static void x86_event_sched_out(struct perf_event *event,
1237 struct perf_cpu_context *cpuctx)
1239 event->state = PERF_EVENT_STATE_INACTIVE;
1242 if (!is_x86_event(event))
1243 event->pmu->disable(event);
1245 event->tstamp_running -= event->ctx->time - event->tstamp_stopped;
1247 if (!is_software_event(event))
1248 cpuctx->active_oncpu--;
1250 if (event->attr.exclusive || !cpuctx->active_oncpu)
1251 cpuctx->exclusive = 0;
1255 * Called to enable a whole group of events.
1256 * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
1257 * Assumes the caller has disabled interrupts and has
1258 * frozen the PMU with hw_perf_save_disable.
1260 * called with PMU disabled. If successful and return value 1,
1261 * then guaranteed to call perf_enable() and hw_perf_enable()
1263 int hw_perf_group_sched_in(struct perf_event *leader,
1264 struct perf_cpu_context *cpuctx,
1265 struct perf_event_context *ctx)
1267 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1268 struct perf_event *sub;
1269 int assign[X86_PMC_IDX_MAX];
1272 if (!x86_pmu_initialized())
1275 /* n0 = total number of events */
1276 n0 = collect_events(cpuc, leader, true);
1280 ret = x86_pmu.schedule_events(cpuc, n0, assign);
1284 ret = x86_event_sched_in(leader, cpuctx);
1289 list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1290 if (sub->state > PERF_EVENT_STATE_OFF) {
1291 ret = x86_event_sched_in(sub, cpuctx);
1298 * copy new assignment, now we know it is possible
1299 * will be used by hw_perf_enable()
1301 memcpy(cpuc->assign, assign, n0*sizeof(int));
1303 cpuc->n_events = n0;
1304 cpuc->n_added += n1;
1305 ctx->nr_active += n1;
1308 * 1 means successful and events are active
1309 * This is not quite true because we defer
1310 * actual activation until hw_perf_enable() but
1311 * this way we* ensure caller won't try to enable
1316 x86_event_sched_out(leader, cpuctx);
1318 list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1319 if (sub->state == PERF_EVENT_STATE_ACTIVE) {
1320 x86_event_sched_out(sub, cpuctx);
1328 #include "perf_event_amd.c"
1329 #include "perf_event_p6.c"
1330 #include "perf_event_p4.c"
1331 #include "perf_event_intel_lbr.c"
1332 #include "perf_event_intel_ds.c"
1333 #include "perf_event_intel.c"
1335 static int __cpuinit
1336 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1338 unsigned int cpu = (long)hcpu;
1340 switch (action & ~CPU_TASKS_FROZEN) {
1341 case CPU_UP_PREPARE:
1342 if (x86_pmu.cpu_prepare)
1343 x86_pmu.cpu_prepare(cpu);
1347 if (x86_pmu.cpu_starting)
1348 x86_pmu.cpu_starting(cpu);
1352 if (x86_pmu.cpu_dying)
1353 x86_pmu.cpu_dying(cpu);
1357 if (x86_pmu.cpu_dead)
1358 x86_pmu.cpu_dead(cpu);
1368 static void __init pmu_check_apic(void)
1374 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1375 pr_info("no hardware sampling interrupt available.\n");
1378 void __init init_hw_perf_events(void)
1380 struct event_constraint *c;
1383 pr_info("Performance Events: ");
1385 switch (boot_cpu_data.x86_vendor) {
1386 case X86_VENDOR_INTEL:
1387 err = intel_pmu_init();
1389 case X86_VENDOR_AMD:
1390 err = amd_pmu_init();
1396 pr_cont("no PMU driver, software events only.\n");
1402 pr_cont("%s PMU driver.\n", x86_pmu.name);
1407 if (x86_pmu.num_events > X86_PMC_MAX_GENERIC) {
1408 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1409 x86_pmu.num_events, X86_PMC_MAX_GENERIC);
1410 x86_pmu.num_events = X86_PMC_MAX_GENERIC;
1412 perf_event_mask = (1 << x86_pmu.num_events) - 1;
1413 perf_max_events = x86_pmu.num_events;
1415 if (x86_pmu.num_events_fixed > X86_PMC_MAX_FIXED) {
1416 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1417 x86_pmu.num_events_fixed, X86_PMC_MAX_FIXED);
1418 x86_pmu.num_events_fixed = X86_PMC_MAX_FIXED;
1422 ((1LL << x86_pmu.num_events_fixed)-1) << X86_PMC_IDX_FIXED;
1423 x86_pmu.intel_ctrl = perf_event_mask;
1425 perf_events_lapic_init();
1426 register_die_notifier(&perf_event_nmi_notifier);
1428 unconstrained = (struct event_constraint)
1429 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_events) - 1,
1430 0, x86_pmu.num_events);
1432 if (x86_pmu.event_constraints) {
1433 for_each_event_constraint(c, x86_pmu.event_constraints) {
1434 if (c->cmask != INTEL_ARCH_FIXED_MASK)
1437 c->idxmsk64 |= (1ULL << x86_pmu.num_events) - 1;
1438 c->weight += x86_pmu.num_events;
1442 pr_info("... version: %d\n", x86_pmu.version);
1443 pr_info("... bit width: %d\n", x86_pmu.event_bits);
1444 pr_info("... generic registers: %d\n", x86_pmu.num_events);
1445 pr_info("... value mask: %016Lx\n", x86_pmu.event_mask);
1446 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1447 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_events_fixed);
1448 pr_info("... event mask: %016Lx\n", perf_event_mask);
1450 perf_cpu_notifier(x86_pmu_notifier);
1453 static inline void x86_pmu_read(struct perf_event *event)
1455 x86_perf_event_update(event);
1458 static const struct pmu pmu = {
1459 .enable = x86_pmu_enable,
1460 .disable = x86_pmu_disable,
1461 .start = x86_pmu_start,
1462 .stop = x86_pmu_stop,
1463 .read = x86_pmu_read,
1464 .unthrottle = x86_pmu_unthrottle,
1468 * validate that we can schedule this event
1470 static int validate_event(struct perf_event *event)
1472 struct cpu_hw_events *fake_cpuc;
1473 struct event_constraint *c;
1476 fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1480 c = x86_pmu.get_event_constraints(fake_cpuc, event);
1482 if (!c || !c->weight)
1485 if (x86_pmu.put_event_constraints)
1486 x86_pmu.put_event_constraints(fake_cpuc, event);
1494 * validate a single event group
1496 * validation include:
1497 * - check events are compatible which each other
1498 * - events do not compete for the same counter
1499 * - number of events <= number of counters
1501 * validation ensures the group can be loaded onto the
1502 * PMU if it was the only group available.
1504 static int validate_group(struct perf_event *event)
1506 struct perf_event *leader = event->group_leader;
1507 struct cpu_hw_events *fake_cpuc;
1511 fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1516 * the event is not yet connected with its
1517 * siblings therefore we must first collect
1518 * existing siblings, then add the new event
1519 * before we can simulate the scheduling
1522 n = collect_events(fake_cpuc, leader, true);
1526 fake_cpuc->n_events = n;
1527 n = collect_events(fake_cpuc, event, false);
1531 fake_cpuc->n_events = n;
1533 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1541 const struct pmu *hw_perf_event_init(struct perf_event *event)
1543 const struct pmu *tmp;
1546 err = __hw_perf_event_init(event);
1549 * we temporarily connect event to its pmu
1550 * such that validate_group() can classify
1551 * it as an x86 event using is_x86_event()
1556 if (event->group_leader != event)
1557 err = validate_group(event);
1559 err = validate_event(event);
1565 event->destroy(event);
1566 return ERR_PTR(err);
1577 void callchain_store(struct perf_callchain_entry *entry, u64 ip)
1579 if (entry->nr < PERF_MAX_STACK_DEPTH)
1580 entry->ip[entry->nr++] = ip;
1583 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
1584 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry);
1588 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1590 /* Ignore warnings */
1593 static void backtrace_warning(void *data, char *msg)
1595 /* Ignore warnings */
1598 static int backtrace_stack(void *data, char *name)
1603 static void backtrace_address(void *data, unsigned long addr, int reliable)
1605 struct perf_callchain_entry *entry = data;
1608 callchain_store(entry, addr);
1611 static const struct stacktrace_ops backtrace_ops = {
1612 .warning = backtrace_warning,
1613 .warning_symbol = backtrace_warning_symbol,
1614 .stack = backtrace_stack,
1615 .address = backtrace_address,
1616 .walk_stack = print_context_stack_bp,
1619 #include "../dumpstack.h"
1622 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1624 callchain_store(entry, PERF_CONTEXT_KERNEL);
1625 callchain_store(entry, regs->ip);
1627 dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
1630 static int copy_stack_frame(const void __user *fp, struct stack_frame *frame)
1632 unsigned long bytes;
1634 bytes = copy_from_user_nmi(frame, fp, sizeof(*frame));
1636 return bytes == sizeof(*frame);
1640 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1642 struct stack_frame frame;
1643 const void __user *fp;
1645 if (!user_mode(regs))
1646 regs = task_pt_regs(current);
1648 fp = (void __user *)regs->bp;
1650 callchain_store(entry, PERF_CONTEXT_USER);
1651 callchain_store(entry, regs->ip);
1653 while (entry->nr < PERF_MAX_STACK_DEPTH) {
1654 frame.next_frame = NULL;
1655 frame.return_address = 0;
1657 if (!copy_stack_frame(fp, &frame))
1660 if ((unsigned long)fp < regs->sp)
1663 callchain_store(entry, frame.return_address);
1664 fp = frame.next_frame;
1669 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1676 is_user = user_mode(regs);
1678 if (is_user && current->state != TASK_RUNNING)
1682 perf_callchain_kernel(regs, entry);
1685 perf_callchain_user(regs, entry);
1688 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1690 struct perf_callchain_entry *entry;
1693 entry = &__get_cpu_var(pmc_nmi_entry);
1695 entry = &__get_cpu_var(pmc_irq_entry);
1699 perf_do_callchain(regs, entry);