arch/x86/kernel/cpu/perf_counter.c

   1 /*
   2  * Performance counter x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *
  10  *  For licencing details see kernel-base/COPYING
  11  */
  12
  13 #include <linux/perf_counter.h>
  14 #include <linux/capability.h>
  15 #include <linux/notifier.h>
  16 #include <linux/hardirq.h>
  17 #include <linux/kprobes.h>
  18 #include <linux/module.h>
  19 #include <linux/kdebug.h>
  20 #include <linux/sched.h>
  21 #include <linux/uaccess.h>
  22 #include <linux/highmem.h>
  23
  24 #include <asm/apic.h>
  25 #include <asm/stacktrace.h>
  26 #include <asm/nmi.h>
  27
  28 static u64 perf_counter_mask __read_mostly;
  29
  30 struct cpu_hw_counters {
  31         struct perf_counter     *counters[X86_PMC_IDX_MAX];
  32         unsigned long           used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  33         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  34         unsigned long           interrupts;
  35         int                     enabled;
  36 };
  37
  38 /*
  39  * struct x86_pmu - generic x86 pmu
  40  */
  41 struct x86_pmu {
  42         const char      *name;
  43         int             version;
  44         int             (*handle_irq)(struct pt_regs *);
  45         void            (*disable_all)(void);
  46         void            (*enable_all)(void);
  47         void            (*enable)(struct hw_perf_counter *, int);
  48         void            (*disable)(struct hw_perf_counter *, int);
  49         unsigned        eventsel;
  50         unsigned        perfctr;
  51         u64             (*event_map)(int);
  52         u64             (*raw_event)(u64);
  53         int             max_events;
  54         int             num_counters;
  55         int             num_counters_fixed;
  56         int             counter_bits;
  57         u64             counter_mask;
  58         u64             max_period;
  59         u64             intel_ctrl;
  60 };
  61
  62 static struct x86_pmu x86_pmu __read_mostly;
  63
  64 static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = {
  65         .enabled = 1,
  66 };
  67
  68 /*
  69  * Intel PerfMon v3. Used on Core2 and later.
  70  */
  71 static const u64 intel_perfmon_event_map[] =
  72 {
  73   [PERF_COUNT_HW_CPU_CYCLES]            = 0x003c,
  74   [PERF_COUNT_HW_INSTRUCTIONS]          = 0x00c0,
  75   [PERF_COUNT_HW_CACHE_REFERENCES]      = 0x4f2e,
  76   [PERF_COUNT_HW_CACHE_MISSES]          = 0x412e,
  77   [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]   = 0x00c4,
  78   [PERF_COUNT_HW_BRANCH_MISSES]         = 0x00c5,
  79   [PERF_COUNT_HW_BUS_CYCLES]            = 0x013c,
  80 };
  81
  82 static u64 intel_pmu_event_map(int event)
  83 {
  84         return intel_perfmon_event_map[event];
  85 }
  86
  87 /*
  88  * Generalized hw caching related event table, filled
  89  * in on a per model basis. A value of 0 means
  90  * 'not supported', -1 means 'event makes no sense on
  91  * this CPU', any other value means the raw event
  92  * ID.
  93  */
  94
  95 #define C(x) PERF_COUNT_HW_CACHE_##x
  96
  97 static u64 __read_mostly hw_cache_event_ids
  98                                 [PERF_COUNT_HW_CACHE_MAX]
  99                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 100                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 101
 102 static const u64 nehalem_hw_cache_event_ids
 103                                 [PERF_COUNT_HW_CACHE_MAX]
 104                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 105                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 106 {
 107  [ C(L1D) ] = {
 108         [ C(OP_READ) ] = {
 109                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI            */
 110                 [ C(RESULT_MISS)   ] = 0x0140, /* L1D_CACHE_LD.I_STATE         */
 111         },
 112         [ C(OP_WRITE) ] = {
 113                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI            */
 114                 [ C(RESULT_MISS)   ] = 0x0141, /* L1D_CACHE_ST.I_STATE         */
 115         },
 116         [ C(OP_PREFETCH) ] = {
 117                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
 118                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
 119         },
 120  },
 121  [ C(L1I ) ] = {
 122         [ C(OP_READ) ] = {
 123                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
 124                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
 125         },
 126         [ C(OP_WRITE) ] = {
 127                 [ C(RESULT_ACCESS) ] = -1,
 128                 [ C(RESULT_MISS)   ] = -1,
 129         },
 130         [ C(OP_PREFETCH) ] = {
 131                 [ C(RESULT_ACCESS) ] = 0x0,
 132                 [ C(RESULT_MISS)   ] = 0x0,
 133         },
 134  },
 135  [ C(LL  ) ] = {
 136         [ C(OP_READ) ] = {
 137                 [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS               */
 138                 [ C(RESULT_MISS)   ] = 0x0224, /* L2_RQSTS.LD_MISS             */
 139         },
 140         [ C(OP_WRITE) ] = {
 141                 [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS                */
 142                 [ C(RESULT_MISS)   ] = 0x0824, /* L2_RQSTS.RFO_MISS            */
 143         },
 144         [ C(OP_PREFETCH) ] = {
 145                 [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference                */
 146                 [ C(RESULT_MISS)   ] = 0x412e, /* LLC Misses                   */
 147         },
 148  },
 149  [ C(DTLB) ] = {
 150         [ C(OP_READ) ] = {
 151                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI   (alias)  */
 152                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
 153         },
 154         [ C(OP_WRITE) ] = {
 155                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI   (alias)  */
 156                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
 157         },
 158         [ C(OP_PREFETCH) ] = {
 159                 [ C(RESULT_ACCESS) ] = 0x0,
 160                 [ C(RESULT_MISS)   ] = 0x0,
 161         },
 162  },
 163  [ C(ITLB) ] = {
 164         [ C(OP_READ) ] = {
 165                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
 166                 [ C(RESULT_MISS)   ] = 0x20c8, /* ITLB_MISS_RETIRED            */
 167         },
 168         [ C(OP_WRITE) ] = {
 169                 [ C(RESULT_ACCESS) ] = -1,
 170                 [ C(RESULT_MISS)   ] = -1,
 171         },
 172         [ C(OP_PREFETCH) ] = {
 173                 [ C(RESULT_ACCESS) ] = -1,
 174                 [ C(RESULT_MISS)   ] = -1,
 175         },
 176  },
 177  [ C(BPU ) ] = {
 178         [ C(OP_READ) ] = {
 179                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 180                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
 181         },
 182         [ C(OP_WRITE) ] = {
 183                 [ C(RESULT_ACCESS) ] = -1,
 184                 [ C(RESULT_MISS)   ] = -1,
 185         },
 186         [ C(OP_PREFETCH) ] = {
 187                 [ C(RESULT_ACCESS) ] = -1,
 188                 [ C(RESULT_MISS)   ] = -1,
 189         },
 190  },
 191 };
 192
 193 static const u64 core2_hw_cache_event_ids
 194                                 [PERF_COUNT_HW_CACHE_MAX]
 195                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 196                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 197 {
 198  [ C(L1D) ] = {
 199         [ C(OP_READ) ] = {
 200                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI          */
 201                 [ C(RESULT_MISS)   ] = 0x0140, /* L1D_CACHE_LD.I_STATE       */
 202         },
 203         [ C(OP_WRITE) ] = {
 204                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI          */
 205                 [ C(RESULT_MISS)   ] = 0x0141, /* L1D_CACHE_ST.I_STATE       */
 206         },
 207         [ C(OP_PREFETCH) ] = {
 208                 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS      */
 209                 [ C(RESULT_MISS)   ] = 0,
 210         },
 211  },
 212  [ C(L1I ) ] = {
 213         [ C(OP_READ) ] = {
 214                 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS                  */
 215                 [ C(RESULT_MISS)   ] = 0x0081, /* L1I.MISSES                 */
 216         },
 217         [ C(OP_WRITE) ] = {
 218                 [ C(RESULT_ACCESS) ] = -1,
 219                 [ C(RESULT_MISS)   ] = -1,
 220         },
 221         [ C(OP_PREFETCH) ] = {
 222                 [ C(RESULT_ACCESS) ] = 0,
 223                 [ C(RESULT_MISS)   ] = 0,
 224         },
 225  },
 226  [ C(LL  ) ] = {
 227         [ C(OP_READ) ] = {
 228                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
 229                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
 230         },
 231         [ C(OP_WRITE) ] = {
 232                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
 233                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
 234         },
 235         [ C(OP_PREFETCH) ] = {
 236                 [ C(RESULT_ACCESS) ] = 0,
 237                 [ C(RESULT_MISS)   ] = 0,
 238         },
 239  },
 240  [ C(DTLB) ] = {
 241         [ C(OP_READ) ] = {
 242                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI  (alias) */
 243                 [ C(RESULT_MISS)   ] = 0x0208, /* DTLB_MISSES.MISS_LD        */
 244         },
 245         [ C(OP_WRITE) ] = {
 246                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI  (alias) */
 247                 [ C(RESULT_MISS)   ] = 0x0808, /* DTLB_MISSES.MISS_ST        */
 248         },
 249         [ C(OP_PREFETCH) ] = {
 250                 [ C(RESULT_ACCESS) ] = 0,
 251                 [ C(RESULT_MISS)   ] = 0,
 252         },
 253  },
 254  [ C(ITLB) ] = {
 255         [ C(OP_READ) ] = {
 256                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
 257                 [ C(RESULT_MISS)   ] = 0x1282, /* ITLBMISSES                 */
 258         },
 259         [ C(OP_WRITE) ] = {
 260                 [ C(RESULT_ACCESS) ] = -1,
 261                 [ C(RESULT_MISS)   ] = -1,
 262         },
 263         [ C(OP_PREFETCH) ] = {
 264                 [ C(RESULT_ACCESS) ] = -1,
 265                 [ C(RESULT_MISS)   ] = -1,
 266         },
 267  },
 268  [ C(BPU ) ] = {
 269         [ C(OP_READ) ] = {
 270                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
 271                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
 272         },
 273         [ C(OP_WRITE) ] = {
 274                 [ C(RESULT_ACCESS) ] = -1,
 275                 [ C(RESULT_MISS)   ] = -1,
 276         },
 277         [ C(OP_PREFETCH) ] = {
 278                 [ C(RESULT_ACCESS) ] = -1,
 279                 [ C(RESULT_MISS)   ] = -1,
 280         },
 281  },
 282 };
 283
 284 static const u64 atom_hw_cache_event_ids
 285                                 [PERF_COUNT_HW_CACHE_MAX]
 286                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 287                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 288 {
 289  [ C(L1D) ] = {
 290         [ C(OP_READ) ] = {
 291                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD               */
 292                 [ C(RESULT_MISS)   ] = 0,
 293         },
 294         [ C(OP_WRITE) ] = {
 295                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST               */
 296                 [ C(RESULT_MISS)   ] = 0,
 297         },
 298         [ C(OP_PREFETCH) ] = {
 299                 [ C(RESULT_ACCESS) ] = 0x0,
 300                 [ C(RESULT_MISS)   ] = 0,
 301         },
 302  },
 303  [ C(L1I ) ] = {
 304         [ C(OP_READ) ] = {
 305                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                  */
 306                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                 */
 307         },
 308         [ C(OP_WRITE) ] = {
 309                 [ C(RESULT_ACCESS) ] = -1,
 310                 [ C(RESULT_MISS)   ] = -1,
 311         },
 312         [ C(OP_PREFETCH) ] = {
 313                 [ C(RESULT_ACCESS) ] = 0,
 314                 [ C(RESULT_MISS)   ] = 0,
 315         },
 316  },
 317  [ C(LL  ) ] = {
 318         [ C(OP_READ) ] = {
 319                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
 320                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
 321         },
 322         [ C(OP_WRITE) ] = {
 323                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
 324                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
 325         },
 326         [ C(OP_PREFETCH) ] = {
 327                 [ C(RESULT_ACCESS) ] = 0,
 328                 [ C(RESULT_MISS)   ] = 0,
 329         },
 330  },
 331  [ C(DTLB) ] = {
 332         [ C(OP_READ) ] = {
 333                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI  (alias) */
 334                 [ C(RESULT_MISS)   ] = 0x0508, /* DTLB_MISSES.MISS_LD        */
 335         },
 336         [ C(OP_WRITE) ] = {
 337                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI  (alias) */
 338                 [ C(RESULT_MISS)   ] = 0x0608, /* DTLB_MISSES.MISS_ST        */
 339         },
 340         [ C(OP_PREFETCH) ] = {
 341                 [ C(RESULT_ACCESS) ] = 0,
 342                 [ C(RESULT_MISS)   ] = 0,
 343         },
 344  },
 345  [ C(ITLB) ] = {
 346         [ C(OP_READ) ] = {
 347                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
 348                 [ C(RESULT_MISS)   ] = 0x0282, /* ITLB.MISSES                */
 349         },
 350         [ C(OP_WRITE) ] = {
 351                 [ C(RESULT_ACCESS) ] = -1,
 352                 [ C(RESULT_MISS)   ] = -1,
 353         },
 354         [ C(OP_PREFETCH) ] = {
 355                 [ C(RESULT_ACCESS) ] = -1,
 356                 [ C(RESULT_MISS)   ] = -1,
 357         },
 358  },
 359  [ C(BPU ) ] = {
 360         [ C(OP_READ) ] = {
 361                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
 362                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
 363         },
 364         [ C(OP_WRITE) ] = {
 365                 [ C(RESULT_ACCESS) ] = -1,
 366                 [ C(RESULT_MISS)   ] = -1,
 367         },
 368         [ C(OP_PREFETCH) ] = {
 369                 [ C(RESULT_ACCESS) ] = -1,
 370                 [ C(RESULT_MISS)   ] = -1,
 371         },
 372  },
 373 };
 374
 375 static u64 intel_pmu_raw_event(u64 event)
 376 {
 377 #define CORE_EVNTSEL_EVENT_MASK         0x000000FFULL
 378 #define CORE_EVNTSEL_UNIT_MASK          0x0000FF00ULL
 379 #define CORE_EVNTSEL_EDGE_MASK          0x00040000ULL
 380 #define CORE_EVNTSEL_INV_MASK           0x00800000ULL
 381 #define CORE_EVNTSEL_COUNTER_MASK       0xFF000000ULL
 382
 383 #define CORE_EVNTSEL_MASK               \
 384         (CORE_EVNTSEL_EVENT_MASK |      \
 385          CORE_EVNTSEL_UNIT_MASK  |      \
 386          CORE_EVNTSEL_EDGE_MASK  |      \
 387          CORE_EVNTSEL_INV_MASK  |       \
 388          CORE_EVNTSEL_COUNTER_MASK)
 389
 390         return event & CORE_EVNTSEL_MASK;
 391 }
 392
 393 static const u64 amd_hw_cache_event_ids
 394                                 [PERF_COUNT_HW_CACHE_MAX]
 395                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 396                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 397 {
 398  [ C(L1D) ] = {
 399         [ C(OP_READ) ] = {
 400                 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses        */
 401                 [ C(RESULT_MISS)   ] = 0x0041, /* Data Cache Misses          */
 402         },
 403         [ C(OP_WRITE) ] = {
 404                 [ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */
 405                 [ C(RESULT_MISS)   ] = 0,
 406         },
 407         [ C(OP_PREFETCH) ] = {
 408                 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts  */
 409                 [ C(RESULT_MISS)   ] = 0x0167, /* Data Prefetcher :cancelled */
 410         },
 411  },
 412  [ C(L1I ) ] = {
 413         [ C(OP_READ) ] = {
 414                 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches  */
 415                 [ C(RESULT_MISS)   ] = 0x0081, /* Instruction cache misses   */
 416         },
 417         [ C(OP_WRITE) ] = {
 418                 [ C(RESULT_ACCESS) ] = -1,
 419                 [ C(RESULT_MISS)   ] = -1,
 420         },
 421         [ C(OP_PREFETCH) ] = {
 422                 [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */
 423                 [ C(RESULT_MISS)   ] = 0,
 424         },
 425  },
 426  [ C(LL  ) ] = {
 427         [ C(OP_READ) ] = {
 428                 [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
 429                 [ C(RESULT_MISS)   ] = 0x037E, /* L2 Cache Misses : IC+DC     */
 430         },
 431         [ C(OP_WRITE) ] = {
 432                 [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback           */
 433                 [ C(RESULT_MISS)   ] = 0,
 434         },
 435         [ C(OP_PREFETCH) ] = {
 436                 [ C(RESULT_ACCESS) ] = 0,
 437                 [ C(RESULT_MISS)   ] = 0,
 438         },
 439  },
 440  [ C(DTLB) ] = {
 441         [ C(OP_READ) ] = {
 442                 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses        */
 443                 [ C(RESULT_MISS)   ] = 0x0046, /* L1 DTLB and L2 DLTB Miss   */
 444         },
 445         [ C(OP_WRITE) ] = {
 446                 [ C(RESULT_ACCESS) ] = 0,
 447                 [ C(RESULT_MISS)   ] = 0,
 448         },
 449         [ C(OP_PREFETCH) ] = {
 450                 [ C(RESULT_ACCESS) ] = 0,
 451                 [ C(RESULT_MISS)   ] = 0,
 452         },
 453  },
 454  [ C(ITLB) ] = {
 455         [ C(OP_READ) ] = {
 456                 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes        */
 457                 [ C(RESULT_MISS)   ] = 0x0085, /* Instr. fetch ITLB misses   */
 458         },
 459         [ C(OP_WRITE) ] = {
 460                 [ C(RESULT_ACCESS) ] = -1,
 461                 [ C(RESULT_MISS)   ] = -1,
 462         },
 463         [ C(OP_PREFETCH) ] = {
 464                 [ C(RESULT_ACCESS) ] = -1,
 465                 [ C(RESULT_MISS)   ] = -1,
 466         },
 467  },
 468  [ C(BPU ) ] = {
 469         [ C(OP_READ) ] = {
 470                 [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr.      */
 471                 [ C(RESULT_MISS)   ] = 0x00c3, /* Retired Mispredicted BI    */
 472         },
 473         [ C(OP_WRITE) ] = {
 474                 [ C(RESULT_ACCESS) ] = -1,
 475                 [ C(RESULT_MISS)   ] = -1,
 476         },
 477         [ C(OP_PREFETCH) ] = {
 478                 [ C(RESULT_ACCESS) ] = -1,
 479                 [ C(RESULT_MISS)   ] = -1,
 480         },
 481  },
 482 };
 483
 484 /*
 485  * AMD Performance Monitor K7 and later.
 486  */
 487 static const u64 amd_perfmon_event_map[] =
 488 {
 489   [PERF_COUNT_HW_CPU_CYCLES]            = 0x0076,
 490   [PERF_COUNT_HW_INSTRUCTIONS]          = 0x00c0,
 491   [PERF_COUNT_HW_CACHE_REFERENCES]      = 0x0080,
 492   [PERF_COUNT_HW_CACHE_MISSES]          = 0x0081,
 493   [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]   = 0x00c4,
 494   [PERF_COUNT_HW_BRANCH_MISSES]         = 0x00c5,
 495 };
 496
 497 static u64 amd_pmu_event_map(int event)
 498 {
 499         return amd_perfmon_event_map[event];
 500 }
 501
 502 static u64 amd_pmu_raw_event(u64 event)
 503 {
 504 #define K7_EVNTSEL_EVENT_MASK   0x7000000FFULL
 505 #define K7_EVNTSEL_UNIT_MASK    0x00000FF00ULL
 506 #define K7_EVNTSEL_EDGE_MASK    0x000040000ULL
 507 #define K7_EVNTSEL_INV_MASK     0x000800000ULL
 508 #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL
 509
 510 #define K7_EVNTSEL_MASK                 \
 511         (K7_EVNTSEL_EVENT_MASK |        \
 512          K7_EVNTSEL_UNIT_MASK  |        \
 513          K7_EVNTSEL_EDGE_MASK  |        \
 514          K7_EVNTSEL_INV_MASK   |        \
 515          K7_EVNTSEL_COUNTER_MASK)
 516
 517         return event & K7_EVNTSEL_MASK;
 518 }
 519
 520 /*
 521  * Propagate counter elapsed time into the generic counter.
 522  * Can only be executed on the CPU where the counter is active.
 523  * Returns the delta events processed.
 524  */
 525 static u64
 526 x86_perf_counter_update(struct perf_counter *counter,
 527                         struct hw_perf_counter *hwc, int idx)
 528 {
 529         int shift = 64 - x86_pmu.counter_bits;
 530         u64 prev_raw_count, new_raw_count;
 531         s64 delta;
 532
 533         /*
 534          * Careful: an NMI might modify the previous counter value.
 535          *
 536          * Our tactic to handle this is to first atomically read and
 537          * exchange a new raw count - then add that new-prev delta
 538          * count to the generic counter atomically:
 539          */
 540 again:
 541         prev_raw_count = atomic64_read(&hwc->prev_count);
 542         rdmsrl(hwc->counter_base + idx, new_raw_count);
 543
 544         if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
 545                                         new_raw_count) != prev_raw_count)
 546                 goto again;
 547
 548         /*
 549          * Now we have the new raw value and have updated the prev
 550          * timestamp already. We can now calculate the elapsed delta
 551          * (counter-)time and add that to the generic counter.
 552          *
 553          * Careful, not all hw sign-extends above the physical width
 554          * of the count.
 555          */
 556         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 557         delta >>= shift;
 558
 559         atomic64_add(delta, &counter->count);
 560         atomic64_sub(delta, &hwc->period_left);
 561
 562         return new_raw_count;
 563 }
 564
 565 static atomic_t active_counters;
 566 static DEFINE_MUTEX(pmc_reserve_mutex);
 567
 568 static bool reserve_pmc_hardware(void)
 569 {
 570         int i;
 571
 572         if (nmi_watchdog == NMI_LOCAL_APIC)
 573                 disable_lapic_nmi_watchdog();
 574
 575         for (i = 0; i < x86_pmu.num_counters; i++) {
 576                 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
 577                         goto perfctr_fail;
 578         }
 579
 580         for (i = 0; i < x86_pmu.num_counters; i++) {
 581                 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
 582                         goto eventsel_fail;
 583         }
 584
 585         return true;
 586
 587 eventsel_fail:
 588         for (i--; i >= 0; i--)
 589                 release_evntsel_nmi(x86_pmu.eventsel + i);
 590
 591         i = x86_pmu.num_counters;
 592
 593 perfctr_fail:
 594         for (i--; i >= 0; i--)
 595                 release_perfctr_nmi(x86_pmu.perfctr + i);
 596
 597         if (nmi_watchdog == NMI_LOCAL_APIC)
 598                 enable_lapic_nmi_watchdog();
 599
 600         return false;
 601 }
 602
 603 static void release_pmc_hardware(void)
 604 {
 605         int i;
 606
 607         for (i = 0; i < x86_pmu.num_counters; i++) {
 608                 release_perfctr_nmi(x86_pmu.perfctr + i);
 609                 release_evntsel_nmi(x86_pmu.eventsel + i);
 610         }
 611
 612         if (nmi_watchdog == NMI_LOCAL_APIC)
 613                 enable_lapic_nmi_watchdog();
 614 }
 615
 616 static void hw_perf_counter_destroy(struct perf_counter *counter)
 617 {
 618         if (atomic_dec_and_mutex_lock(&active_counters, &pmc_reserve_mutex)) {
 619                 release_pmc_hardware();
 620                 mutex_unlock(&pmc_reserve_mutex);
 621         }
 622 }
 623
 624 static inline int x86_pmu_initialized(void)
 625 {
 626         return x86_pmu.handle_irq != NULL;
 627 }
 628
 629 static inline int
 630 set_ext_hw_attr(struct hw_perf_counter *hwc, struct perf_counter_attr *attr)
 631 {
 632         unsigned int cache_type, cache_op, cache_result;
 633         u64 config, val;
 634
 635         config = attr->config;
 636
 637         cache_type = (config >>  0) & 0xff;
 638         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 639                 return -EINVAL;
 640
 641         cache_op = (config >>  8) & 0xff;
 642         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 643                 return -EINVAL;
 644
 645         cache_result = (config >> 16) & 0xff;
 646         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 647                 return -EINVAL;
 648
 649         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 650
 651         if (val == 0)
 652                 return -ENOENT;
 653
 654         if (val == -1)
 655                 return -EINVAL;
 656
 657         hwc->config |= val;
 658
 659         return 0;
 660 }
 661
 662 /*
 663  * Setup the hardware configuration for a given attr_type
 664  */
 665 static int __hw_perf_counter_init(struct perf_counter *counter)
 666 {
 667         struct perf_counter_attr *attr = &counter->attr;
 668         struct hw_perf_counter *hwc = &counter->hw;
 669         int err;
 670
 671         if (!x86_pmu_initialized())
 672                 return -ENODEV;
 673
 674         err = 0;
 675         if (!atomic_inc_not_zero(&active_counters)) {
 676                 mutex_lock(&pmc_reserve_mutex);
 677                 if (atomic_read(&active_counters) == 0 && !reserve_pmc_hardware())
 678                         err = -EBUSY;
 679                 else
 680                         atomic_inc(&active_counters);
 681                 mutex_unlock(&pmc_reserve_mutex);
 682         }
 683         if (err)
 684                 return err;
 685
 686         /*
 687          * Generate PMC IRQs:
 688          * (keep 'enabled' bit clear for now)
 689          */
 690         hwc->config = ARCH_PERFMON_EVENTSEL_INT;
 691
 692         /*
 693          * Count user and OS events unless requested not to.
 694          */
 695         if (!attr->exclude_user)
 696                 hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
 697         if (!attr->exclude_kernel)
 698                 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
 699
 700         if (!hwc->sample_period) {
 701                 hwc->sample_period = x86_pmu.max_period;
 702                 hwc->last_period = hwc->sample_period;
 703                 atomic64_set(&hwc->period_left, hwc->sample_period);
 704         }
 705
 706         counter->destroy = hw_perf_counter_destroy;
 707
 708         /*
 709          * Raw event type provide the config in the event structure
 710          */
 711         if (attr->type == PERF_TYPE_RAW) {
 712                 hwc->config |= x86_pmu.raw_event(attr->config);
 713                 return 0;
 714         }
 715
 716         if (attr->type == PERF_TYPE_HW_CACHE)
 717                 return set_ext_hw_attr(hwc, attr);
 718
 719         if (attr->config >= x86_pmu.max_events)
 720                 return -EINVAL;
 721         /*
 722          * The generic map:
 723          */
 724         hwc->config |= x86_pmu.event_map(attr->config);
 725
 726         return 0;
 727 }
 728
 729 static void intel_pmu_disable_all(void)
 730 {
 731         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
 732 }
 733
 734 static void amd_pmu_disable_all(void)
 735 {
 736         struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
 737         int idx;
 738
 739         if (!cpuc->enabled)
 740                 return;
 741
 742         cpuc->enabled = 0;
 743         /*
 744          * ensure we write the disable before we start disabling the
 745          * counters proper, so that amd_pmu_enable_counter() does the
 746          * right thing.
 747          */
 748         barrier();
 749
 750         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 751                 u64 val;
 752
 753                 if (!test_bit(idx, cpuc->active_mask))
 754                         continue;
 755                 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
 756                 if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE))
 757                         continue;
 758                 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
 759                 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
 760         }
 761 }
 762
 763 void hw_perf_disable(void)
 764 {
 765         if (!x86_pmu_initialized())
 766                 return;
 767         return x86_pmu.disable_all();
 768 }
 769
 770 static void intel_pmu_enable_all(void)
 771 {
 772         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
 773 }
 774
 775 static void amd_pmu_enable_all(void)
 776 {
 777         struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
 778         int idx;
 779
 780         if (cpuc->enabled)
 781                 return;
 782
 783         cpuc->enabled = 1;
 784         barrier();
 785
 786         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 787                 u64 val;
 788
 789                 if (!test_bit(idx, cpuc->active_mask))
 790                         continue;
 791                 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
 792                 if (val & ARCH_PERFMON_EVENTSEL0_ENABLE)
 793                         continue;
 794                 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
 795                 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
 796         }
 797 }
 798
 799 void hw_perf_enable(void)
 800 {
 801         if (!x86_pmu_initialized())
 802                 return;
 803         x86_pmu.enable_all();
 804 }
 805
 806 static inline u64 intel_pmu_get_status(void)
 807 {
 808         u64 status;
 809
 810         rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
 811
 812         return status;
 813 }
 814
 815 static inline void intel_pmu_ack_status(u64 ack)
 816 {
 817         wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
 818 }
 819
 820 static inline void x86_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
 821 {
 822         int err;
 823         err = checking_wrmsrl(hwc->config_base + idx,
 824                               hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE);
 825 }
 826
 827 static inline void x86_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
 828 {
 829         int err;
 830         err = checking_wrmsrl(hwc->config_base + idx,
 831                               hwc->config);
 832 }
 833
 834 static inline void
 835 intel_pmu_disable_fixed(struct hw_perf_counter *hwc, int __idx)
 836 {
 837         int idx = __idx - X86_PMC_IDX_FIXED;
 838         u64 ctrl_val, mask;
 839         int err;
 840
 841         mask = 0xfULL << (idx * 4);
 842
 843         rdmsrl(hwc->config_base, ctrl_val);
 844         ctrl_val &= ~mask;
 845         err = checking_wrmsrl(hwc->config_base, ctrl_val);
 846 }
 847
 848 static inline void
 849 intel_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
 850 {
 851         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
 852                 intel_pmu_disable_fixed(hwc, idx);
 853                 return;
 854         }
 855
 856         x86_pmu_disable_counter(hwc, idx);
 857 }
 858
 859 static inline void
 860 amd_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
 861 {
 862         x86_pmu_disable_counter(hwc, idx);
 863 }
 864
 865 static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]);
 866
 867 /*
 868  * Set the next IRQ period, based on the hwc->period_left value.
 869  * To be called with the counter disabled in hw:
 870  */
 871 static int
 872 x86_perf_counter_set_period(struct perf_counter *counter,
 873                              struct hw_perf_counter *hwc, int idx)
 874 {
 875         s64 left = atomic64_read(&hwc->period_left);
 876         s64 period = hwc->sample_period;
 877         int err, ret = 0;
 878
 879         /*
 880          * If we are way outside a reasoable range then just skip forward:
 881          */
 882         if (unlikely(left <= -period)) {
 883                 left = period;
 884                 atomic64_set(&hwc->period_left, left);
 885                 hwc->last_period = period;
 886                 ret = 1;
 887         }
 888
 889         if (unlikely(left <= 0)) {
 890                 left += period;
 891                 atomic64_set(&hwc->period_left, left);
 892                 hwc->last_period = period;
 893                 ret = 1;
 894         }
 895         /*
 896          * Quirk: certain CPUs dont like it if just 1 event is left:
 897          */
 898         if (unlikely(left < 2))
 899                 left = 2;
 900
 901         if (left > x86_pmu.max_period)
 902                 left = x86_pmu.max_period;
 903
 904         per_cpu(prev_left[idx], smp_processor_id()) = left;
 905
 906         /*
 907          * The hw counter starts counting from this counter offset,
 908          * mark it to be able to extra future deltas:
 909          */
 910         atomic64_set(&hwc->prev_count, (u64)-left);
 911
 912         err = checking_wrmsrl(hwc->counter_base + idx,
 913                              (u64)(-left) & x86_pmu.counter_mask);
 914
 915         perf_counter_update_userpage(counter);
 916
 917         return ret;
 918 }
 919
 920 static inline void
 921 intel_pmu_enable_fixed(struct hw_perf_counter *hwc, int __idx)
 922 {
 923         int idx = __idx - X86_PMC_IDX_FIXED;
 924         u64 ctrl_val, bits, mask;
 925         int err;
 926
 927         /*
 928          * Enable IRQ generation (0x8),
 929          * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
 930          * if requested:
 931          */
 932         bits = 0x8ULL;
 933         if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
 934                 bits |= 0x2;
 935         if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
 936                 bits |= 0x1;
 937         bits <<= (idx * 4);
 938         mask = 0xfULL << (idx * 4);
 939
 940         rdmsrl(hwc->config_base, ctrl_val);
 941         ctrl_val &= ~mask;
 942         ctrl_val |= bits;
 943         err = checking_wrmsrl(hwc->config_base, ctrl_val);
 944 }
 945
 946 static void intel_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
 947 {
 948         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
 949                 intel_pmu_enable_fixed(hwc, idx);
 950                 return;
 951         }
 952
 953         x86_pmu_enable_counter(hwc, idx);
 954 }
 955
 956 static void amd_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
 957 {
 958         struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
 959
 960         if (cpuc->enabled)
 961                 x86_pmu_enable_counter(hwc, idx);
 962         else
 963                 x86_pmu_disable_counter(hwc, idx);
 964 }
 965
 966 static int
 967 fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc)
 968 {
 969         unsigned int event;
 970
 971         if (!x86_pmu.num_counters_fixed)
 972                 return -1;
 973
 974         event = hwc->config & ARCH_PERFMON_EVENT_MASK;
 975
 976         if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_INSTRUCTIONS)))
 977                 return X86_PMC_IDX_FIXED_INSTRUCTIONS;
 978         if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_CPU_CYCLES)))
 979                 return X86_PMC_IDX_FIXED_CPU_CYCLES;
 980         if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_BUS_CYCLES)))
 981                 return X86_PMC_IDX_FIXED_BUS_CYCLES;
 982
 983         return -1;
 984 }
 985
 986 /*
 987  * Find a PMC slot for the freshly enabled / scheduled in counter:
 988  */
 989 static int x86_pmu_enable(struct perf_counter *counter)
 990 {
 991         struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
 992         struct hw_perf_counter *hwc = &counter->hw;
 993         int idx;
 994
 995         idx = fixed_mode_idx(counter, hwc);
 996         if (idx >= 0) {
 997                 /*
 998                  * Try to get the fixed counter, if that is already taken
 999                  * then try to get a generic counter:
1000                  */
1001                 if (test_and_set_bit(idx, cpuc->used_mask))
1002                         goto try_generic;
1003
1004                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1005                 /*
1006                  * We set it so that counter_base + idx in wrmsr/rdmsr maps to
1007                  * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
1008                  */
1009                 hwc->counter_base =
1010                         MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
1011                 hwc->idx = idx;
1012         } else {
1013                 idx = hwc->idx;
1014                 /* Try to get the previous generic counter again */
1015                 if (test_and_set_bit(idx, cpuc->used_mask)) {
1016 try_generic:
1017                         idx = find_first_zero_bit(cpuc->used_mask,
1018                                                   x86_pmu.num_counters);
1019                         if (idx == x86_pmu.num_counters)
1020                                 return -EAGAIN;
1021
1022                         set_bit(idx, cpuc->used_mask);
1023                         hwc->idx = idx;
1024                 }
1025                 hwc->config_base  = x86_pmu.eventsel;
1026                 hwc->counter_base = x86_pmu.perfctr;
1027         }
1028
1029         perf_counters_lapic_init();
1030
1031         x86_pmu.disable(hwc, idx);
1032
1033         cpuc->counters[idx] = counter;
1034         set_bit(idx, cpuc->active_mask);
1035
1036         x86_perf_counter_set_period(counter, hwc, idx);
1037         x86_pmu.enable(hwc, idx);
1038
1039         perf_counter_update_userpage(counter);
1040
1041         return 0;
1042 }
1043
1044 static void x86_pmu_unthrottle(struct perf_counter *counter)
1045 {
1046         struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
1047         struct hw_perf_counter *hwc = &counter->hw;
1048
1049         if (WARN_ON_ONCE(hwc->idx >= X86_PMC_IDX_MAX ||
1050                                 cpuc->counters[hwc->idx] != counter))
1051                 return;
1052
1053         x86_pmu.enable(hwc, hwc->idx);
1054 }
1055
1056 void perf_counter_print_debug(void)
1057 {
1058         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1059         struct cpu_hw_counters *cpuc;
1060         unsigned long flags;
1061         int cpu, idx;
1062
1063         if (!x86_pmu.num_counters)
1064                 return;
1065
1066         local_irq_save(flags);
1067
1068         cpu = smp_processor_id();
1069         cpuc = &per_cpu(cpu_hw_counters, cpu);
1070
1071         if (x86_pmu.version >= 2) {
1072                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1073                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1074                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1075                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1076
1077                 pr_info("\n");
1078                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1079                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1080                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1081                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1082         }
1083         pr_info("CPU#%d: used:       %016llx\n", cpu, *(u64 *)cpuc->used_mask);
1084
1085         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1086                 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1087                 rdmsrl(x86_pmu.perfctr  + idx, pmc_count);
1088
1089                 prev_left = per_cpu(prev_left[idx], cpu);
1090
1091                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1092                         cpu, idx, pmc_ctrl);
1093                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1094                         cpu, idx, pmc_count);
1095                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1096                         cpu, idx, prev_left);
1097         }
1098         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1099                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1100
1101                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1102                         cpu, idx, pmc_count);
1103         }
1104         local_irq_restore(flags);
1105 }
1106
1107 static void x86_pmu_disable(struct perf_counter *counter)
1108 {
1109         struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
1110         struct hw_perf_counter *hwc = &counter->hw;
1111         int idx = hwc->idx;
1112
1113         /*
1114          * Must be done before we disable, otherwise the nmi handler
1115          * could reenable again:
1116          */
1117         clear_bit(idx, cpuc->active_mask);
1118         x86_pmu.disable(hwc, idx);
1119
1120         /*
1121          * Make sure the cleared pointer becomes visible before we
1122          * (potentially) free the counter:
1123          */
1124         barrier();
1125
1126         /*
1127          * Drain the remaining delta count out of a counter
1128          * that we are disabling:
1129          */
1130         x86_perf_counter_update(counter, hwc, idx);
1131         cpuc->counters[idx] = NULL;
1132         clear_bit(idx, cpuc->used_mask);
1133
1134         perf_counter_update_userpage(counter);
1135 }
1136
1137 /*
1138  * Save and restart an expired counter. Called by NMI contexts,
1139  * so it has to be careful about preempting normal counter ops:
1140  */
1141 static int intel_pmu_save_and_restart(struct perf_counter *counter)
1142 {
1143         struct hw_perf_counter *hwc = &counter->hw;
1144         int idx = hwc->idx;
1145         int ret;
1146
1147         x86_perf_counter_update(counter, hwc, idx);
1148         ret = x86_perf_counter_set_period(counter, hwc, idx);
1149
1150         if (counter->state == PERF_COUNTER_STATE_ACTIVE)
1151                 intel_pmu_enable_counter(hwc, idx);
1152
1153         return ret;
1154 }
1155
1156 static void intel_pmu_reset(void)
1157 {
1158         unsigned long flags;
1159         int idx;
1160
1161         if (!x86_pmu.num_counters)
1162                 return;
1163
1164         local_irq_save(flags);
1165
1166         printk("clearing PMU state on CPU#%d\n", smp_processor_id());
1167
1168         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1169                 checking_wrmsrl(x86_pmu.eventsel + idx, 0ull);
1170                 checking_wrmsrl(x86_pmu.perfctr  + idx, 0ull);
1171         }
1172         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1173                 checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
1174         }
1175
1176         local_irq_restore(flags);
1177 }
1178
1179
1180 /*
1181  * This handler is triggered by the local APIC, so the APIC IRQ handling
1182  * rules apply:
1183  */
1184 static int intel_pmu_handle_irq(struct pt_regs *regs)
1185 {
1186         struct perf_sample_data data;
1187         struct cpu_hw_counters *cpuc;
1188         int bit, cpu, loops;
1189         u64 ack, status;
1190
1191         data.regs = regs;
1192         data.addr = 0;
1193
1194         cpu = smp_processor_id();
1195         cpuc = &per_cpu(cpu_hw_counters, cpu);
1196
1197         perf_disable();
1198         status = intel_pmu_get_status();
1199         if (!status) {
1200                 perf_enable();
1201                 return 0;
1202         }
1203
1204         loops = 0;
1205 again:
1206         if (++loops > 100) {
1207                 WARN_ONCE(1, "perfcounters: irq loop stuck!\n");
1208                 perf_counter_print_debug();
1209                 intel_pmu_reset();
1210                 perf_enable();
1211                 return 1;
1212         }
1213
1214         inc_irq_stat(apic_perf_irqs);
1215         ack = status;
1216         for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
1217                 struct perf_counter *counter = cpuc->counters[bit];
1218
1219                 clear_bit(bit, (unsigned long *) &status);
1220                 if (!test_bit(bit, cpuc->active_mask))
1221                         continue;
1222
1223                 if (!intel_pmu_save_and_restart(counter))
1224                         continue;
1225
1226                 data.period = counter->hw.last_period;
1227
1228                 if (perf_counter_overflow(counter, 1, &data))
1229                         intel_pmu_disable_counter(&counter->hw, bit);
1230         }
1231
1232         intel_pmu_ack_status(ack);
1233
1234         /*
1235          * Repeat if there is more work to be done:
1236          */
1237         status = intel_pmu_get_status();
1238         if (status)
1239                 goto again;
1240
1241         perf_enable();
1242
1243         return 1;
1244 }
1245
1246 static int amd_pmu_handle_irq(struct pt_regs *regs)
1247 {
1248         struct perf_sample_data data;
1249         struct cpu_hw_counters *cpuc;
1250         struct perf_counter *counter;
1251         struct hw_perf_counter *hwc;
1252         int cpu, idx, handled = 0;
1253         u64 val;
1254
1255         data.regs = regs;
1256         data.addr = 0;
1257
1258         cpu = smp_processor_id();
1259         cpuc = &per_cpu(cpu_hw_counters, cpu);
1260
1261         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1262                 if (!test_bit(idx, cpuc->active_mask))
1263                         continue;
1264
1265                 counter = cpuc->counters[idx];
1266                 hwc = &counter->hw;
1267
1268                 val = x86_perf_counter_update(counter, hwc, idx);
1269                 if (val & (1ULL << (x86_pmu.counter_bits - 1)))
1270                         continue;
1271
1272                 /*
1273                  * counter overflow
1274                  */
1275                 handled         = 1;
1276                 data.period     = counter->hw.last_period;
1277
1278                 if (!x86_perf_counter_set_period(counter, hwc, idx))
1279                         continue;
1280
1281                 if (perf_counter_overflow(counter, 1, &data))
1282                         amd_pmu_disable_counter(hwc, idx);
1283         }
1284
1285         if (handled)
1286                 inc_irq_stat(apic_perf_irqs);
1287
1288         return handled;
1289 }
1290
1291 void smp_perf_pending_interrupt(struct pt_regs *regs)
1292 {
1293         irq_enter();
1294         ack_APIC_irq();
1295         inc_irq_stat(apic_pending_irqs);
1296         perf_counter_do_pending();
1297         irq_exit();
1298 }
1299
1300 void set_perf_counter_pending(void)
1301 {
1302         apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1303 }
1304
1305 void perf_counters_lapic_init(void)
1306 {
1307         if (!x86_pmu_initialized())
1308                 return;
1309
1310         /*
1311          * Always use NMI for PMU
1312          */
1313         apic_write(APIC_LVTPC, APIC_DM_NMI);
1314 }
1315
1316 static int __kprobes
1317 perf_counter_nmi_handler(struct notifier_block *self,
1318                          unsigned long cmd, void *__args)
1319 {
1320         struct die_args *args = __args;
1321         struct pt_regs *regs;
1322
1323         if (!atomic_read(&active_counters))
1324                 return NOTIFY_DONE;
1325
1326         switch (cmd) {
1327         case DIE_NMI:
1328         case DIE_NMI_IPI:
1329                 break;
1330
1331         default:
1332                 return NOTIFY_DONE;
1333         }
1334
1335         regs = args->regs;
1336
1337         apic_write(APIC_LVTPC, APIC_DM_NMI);
1338         /*
1339          * Can't rely on the handled return value to say it was our NMI, two
1340          * counters could trigger 'simultaneously' raising two back-to-back NMIs.
1341          *
1342          * If the first NMI handles both, the latter will be empty and daze
1343          * the CPU.
1344          */
1345         x86_pmu.handle_irq(regs);
1346
1347         return NOTIFY_STOP;
1348 }
1349
1350 static __read_mostly struct notifier_block perf_counter_nmi_notifier = {
1351         .notifier_call          = perf_counter_nmi_handler,
1352         .next                   = NULL,
1353         .priority               = 1
1354 };
1355
1356 static struct x86_pmu intel_pmu = {
1357         .name                   = "Intel",
1358         .handle_irq             = intel_pmu_handle_irq,
1359         .disable_all            = intel_pmu_disable_all,
1360         .enable_all             = intel_pmu_enable_all,
1361         .enable                 = intel_pmu_enable_counter,
1362         .disable                = intel_pmu_disable_counter,
1363         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
1364         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
1365         .event_map              = intel_pmu_event_map,
1366         .raw_event              = intel_pmu_raw_event,
1367         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
1368         /*
1369          * Intel PMCs cannot be accessed sanely above 32 bit width,
1370          * so we install an artificial 1<<31 period regardless of
1371          * the generic counter period:
1372          */
1373         .max_period             = (1ULL << 31) - 1,
1374 };
1375
1376 static struct x86_pmu amd_pmu = {
1377         .name                   = "AMD",
1378         .handle_irq             = amd_pmu_handle_irq,
1379         .disable_all            = amd_pmu_disable_all,
1380         .enable_all             = amd_pmu_enable_all,
1381         .enable                 = amd_pmu_enable_counter,
1382         .disable                = amd_pmu_disable_counter,
1383         .eventsel               = MSR_K7_EVNTSEL0,
1384         .perfctr                = MSR_K7_PERFCTR0,
1385         .event_map              = amd_pmu_event_map,
1386         .raw_event              = amd_pmu_raw_event,
1387         .max_events             = ARRAY_SIZE(amd_perfmon_event_map),
1388         .num_counters           = 4,
1389         .counter_bits           = 48,
1390         .counter_mask           = (1ULL << 48) - 1,
1391         /* use highest bit to detect overflow */
1392         .max_period             = (1ULL << 47) - 1,
1393 };
1394
1395 static int intel_pmu_init(void)
1396 {
1397         union cpuid10_edx edx;
1398         union cpuid10_eax eax;
1399         unsigned int unused;
1400         unsigned int ebx;
1401         int version;
1402
1403         if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
1404                 return -ENODEV;
1405
1406         /*
1407          * Check whether the Architectural PerfMon supports
1408          * Branch Misses Retired Event or not.
1409          */
1410         cpuid(10, &eax.full, &ebx, &unused, &edx.full);
1411         if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
1412                 return -ENODEV;
1413
1414         version = eax.split.version_id;
1415         if (version < 2)
1416                 return -ENODEV;
1417
1418         x86_pmu                         = intel_pmu;
1419         x86_pmu.version                 = version;
1420         x86_pmu.num_counters            = eax.split.num_counters;
1421         x86_pmu.counter_bits            = eax.split.bit_width;
1422         x86_pmu.counter_mask            = (1ULL << eax.split.bit_width) - 1;
1423
1424         /*
1425          * Quirk: v2 perfmon does not report fixed-purpose counters, so
1426          * assume at least 3 counters:
1427          */
1428         x86_pmu.num_counters_fixed      = max((int)edx.split.num_counters_fixed, 3);
1429
1430         /*
1431          * Install the hw-cache-events table:
1432          */
1433         switch (boot_cpu_data.x86_model) {
1434         case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
1435         case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
1436         case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
1437         case 29: /* six-core 45 nm xeon "Dunnington" */
1438                 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
1439                        sizeof(hw_cache_event_ids));
1440
1441                 pr_cont("Core2 events, ");
1442                 break;
1443         default:
1444         case 26:
1445                 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
1446                        sizeof(hw_cache_event_ids));
1447
1448                 pr_cont("Nehalem/Corei7 events, ");
1449                 break;
1450         case 28:
1451                 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
1452                        sizeof(hw_cache_event_ids));
1453
1454                 pr_cont("Atom events, ");
1455                 break;
1456         }
1457         return 0;
1458 }
1459
1460 static int amd_pmu_init(void)
1461 {
1462         /* Performance-monitoring supported from K7 and later: */
1463         if (boot_cpu_data.x86 < 6)
1464                 return -ENODEV;
1465
1466         x86_pmu = amd_pmu;
1467
1468         /* Events are common for all AMDs */
1469         memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
1470                sizeof(hw_cache_event_ids));
1471
1472         return 0;
1473 }
1474
1475 void __init init_hw_perf_counters(void)
1476 {
1477         int err;
1478
1479         pr_info("Performance Counters: ");
1480
1481         switch (boot_cpu_data.x86_vendor) {
1482         case X86_VENDOR_INTEL:
1483                 err = intel_pmu_init();
1484                 break;
1485         case X86_VENDOR_AMD:
1486                 err = amd_pmu_init();
1487                 break;
1488         default:
1489                 return;
1490         }
1491         if (err != 0) {
1492                 pr_cont("no PMU driver, software counters only.\n");
1493                 return;
1494         }
1495
1496         pr_cont("%s PMU driver.\n", x86_pmu.name);
1497
1498         if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1499                 WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!",
1500                      x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1501                 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1502         }
1503         perf_counter_mask = (1 << x86_pmu.num_counters) - 1;
1504         perf_max_counters = x86_pmu.num_counters;
1505
1506         if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1507                 WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!",
1508                      x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1509                 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1510         }
1511
1512         perf_counter_mask |=
1513                 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1514         x86_pmu.intel_ctrl = perf_counter_mask;
1515
1516         perf_counters_lapic_init();
1517         register_die_notifier(&perf_counter_nmi_notifier);
1518
1519         pr_info("... version:                 %d\n",     x86_pmu.version);
1520         pr_info("... bit width:               %d\n",     x86_pmu.counter_bits);
1521         pr_info("... generic counters:        %d\n",     x86_pmu.num_counters);
1522         pr_info("... value mask:              %016Lx\n", x86_pmu.counter_mask);
1523         pr_info("... max period:              %016Lx\n", x86_pmu.max_period);
1524         pr_info("... fixed-purpose counters:  %d\n",     x86_pmu.num_counters_fixed);
1525         pr_info("... counter mask:            %016Lx\n", perf_counter_mask);
1526 }
1527
1528 static inline void x86_pmu_read(struct perf_counter *counter)
1529 {
1530         x86_perf_counter_update(counter, &counter->hw, counter->hw.idx);
1531 }
1532
1533 static const struct pmu pmu = {
1534         .enable         = x86_pmu_enable,
1535         .disable        = x86_pmu_disable,
1536         .read           = x86_pmu_read,
1537         .unthrottle     = x86_pmu_unthrottle,
1538 };
1539
1540 const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
1541 {
1542         int err;
1543
1544         err = __hw_perf_counter_init(counter);
1545         if (err)
1546                 return ERR_PTR(err);
1547
1548         return &pmu;
1549 }
1550
1551 /*
1552  * callchain support
1553  */
1554
1555 static inline
1556 void callchain_store(struct perf_callchain_entry *entry, u64 ip)
1557 {
1558         if (entry->nr < PERF_MAX_STACK_DEPTH)
1559                 entry->ip[entry->nr++] = ip;
1560 }
1561
1562 static DEFINE_PER_CPU(struct perf_callchain_entry, irq_entry);
1563 static DEFINE_PER_CPU(struct perf_callchain_entry, nmi_entry);
1564 static DEFINE_PER_CPU(int, in_nmi_frame);
1565
1566
1567 static void
1568 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1569 {
1570         /* Ignore warnings */
1571 }
1572
1573 static void backtrace_warning(void *data, char *msg)
1574 {
1575         /* Ignore warnings */
1576 }
1577
1578 static int backtrace_stack(void *data, char *name)
1579 {
1580         per_cpu(in_nmi_frame, smp_processor_id()) =
1581                         x86_is_stack_id(NMI_STACK, name);
1582
1583         return 0;
1584 }
1585
1586 static void backtrace_address(void *data, unsigned long addr, int reliable)
1587 {
1588         struct perf_callchain_entry *entry = data;
1589
1590         if (per_cpu(in_nmi_frame, smp_processor_id()))
1591                 return;
1592
1593         if (reliable)
1594                 callchain_store(entry, addr);
1595 }
1596
1597 static const struct stacktrace_ops backtrace_ops = {
1598         .warning                = backtrace_warning,
1599         .warning_symbol         = backtrace_warning_symbol,
1600         .stack                  = backtrace_stack,
1601         .address                = backtrace_address,
1602 };
1603
1604 #include "../dumpstack.h"
1605
1606 static void
1607 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1608 {
1609         callchain_store(entry, PERF_CONTEXT_KERNEL);
1610         callchain_store(entry, regs->ip);
1611
1612         dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
1613 }
1614
1615 /*
1616  * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
1617  */
1618 static unsigned long
1619 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
1620 {
1621         unsigned long offset, addr = (unsigned long)from;
1622         int type = in_nmi() ? KM_NMI : KM_IRQ0;
1623         unsigned long size, len = 0;
1624         struct page *page;
1625         void *map;
1626         int ret;
1627
1628         do {
1629                 ret = __get_user_pages_fast(addr, 1, 0, &page);
1630                 if (!ret)
1631                         break;
1632
1633                 offset = addr & (PAGE_SIZE - 1);
1634                 size = min(PAGE_SIZE - offset, n - len);
1635
1636                 map = kmap_atomic(page, type);
1637                 memcpy(to, map+offset, size);
1638                 kunmap_atomic(map, type);
1639                 put_page(page);
1640
1641                 len  += size;
1642                 to   += size;
1643                 addr += size;
1644
1645         } while (len < n);
1646
1647         return len;
1648 }
1649
1650 static int copy_stack_frame(const void __user *fp, struct stack_frame *frame)
1651 {
1652         unsigned long bytes;
1653
1654         bytes = copy_from_user_nmi(frame, fp, sizeof(*frame));
1655
1656         return bytes == sizeof(*frame);
1657 }
1658
1659 static void
1660 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1661 {
1662         struct stack_frame frame;
1663         const void __user *fp;
1664
1665         if (!user_mode(regs))
1666                 regs = task_pt_regs(current);
1667
1668         fp = (void __user *)regs->bp;
1669
1670         callchain_store(entry, PERF_CONTEXT_USER);
1671         callchain_store(entry, regs->ip);
1672
1673         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1674                 frame.next_frame             = NULL;
1675                 frame.return_address = 0;
1676
1677                 if (!copy_stack_frame(fp, &frame))
1678                         break;
1679
1680                 if ((unsigned long)fp < regs->sp)
1681                         break;
1682
1683                 callchain_store(entry, frame.return_address);
1684                 fp = frame.next_frame;
1685         }
1686 }
1687
1688 static void
1689 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1690 {
1691         int is_user;
1692
1693         if (!regs)
1694                 return;
1695
1696         is_user = user_mode(regs);
1697
1698         if (!current || current->pid == 0)
1699                 return;
1700
1701         if (is_user && current->state != TASK_RUNNING)
1702                 return;
1703
1704         if (!is_user)
1705                 perf_callchain_kernel(regs, entry);
1706
1707         if (current->mm)
1708                 perf_callchain_user(regs, entry);
1709 }
1710
1711 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1712 {
1713         struct perf_callchain_entry *entry;
1714
1715         if (in_nmi())
1716                 entry = &__get_cpu_var(nmi_entry);
1717         else
1718                 entry = &__get_cpu_var(irq_entry);
1719
1720         entry->nr = 0;
1721
1722         perf_do_callchain(regs, entry);
1723
1724         return entry;
1725 }