1 /* Generic MTRR (Memory Type Range Register) driver.
3 Copyright (C) 1997-2000 Richard Gooch
4 Copyright (c) 2002 Patrick Mochel
6 This library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Library General Public
8 License as published by the Free Software Foundation; either
9 version 2 of the License, or (at your option) any later version.
11 This library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Library General Public License for more details.
16 You should have received a copy of the GNU Library General Public
17 License along with this library; if not, write to the Free
18 Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 Richard Gooch may be reached by email at rgooch@atnf.csiro.au
21 The postal address is:
22 Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia.
24 Source: "Pentium Pro Family Developer's Manual, Volume 3:
25 Operating System Writer's Guide" (Intel document number 242692),
28 This was cleaned and made readable by Patrick Mochel <mochel@osdl.org>
30 Source: Intel Architecture Software Developers Manual, Volume 3:
31 System Programming Guide; Section 9.11. (1997 edition - PPro).
36 #include <linux/types.h> /* FIXME: kvm_para.h needs this */
38 #include <linux/stop_machine.h>
39 #include <linux/kvm_para.h>
40 #include <linux/uaccess.h>
41 #include <linux/module.h>
42 #include <linux/mutex.h>
43 #include <linux/init.h>
44 #include <linux/sort.h>
45 #include <linux/cpu.h>
46 #include <linux/pci.h>
47 #include <linux/smp.h>
48 #include <linux/syscore_ops.h>
50 #include <asm/processor.h>
59 unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES];
60 static DEFINE_MUTEX(mtrr_mutex);
62 u64 size_or_mask, size_and_mask;
63 static bool mtrr_aps_delayed_init;
65 static const struct mtrr_ops *mtrr_ops[X86_VENDOR_NUM];
67 const struct mtrr_ops *mtrr_if;
69 static void set_mtrr(unsigned int reg, unsigned long base,
70 unsigned long size, mtrr_type type);
72 void set_mtrr_ops(const struct mtrr_ops *ops)
74 if (ops->vendor && ops->vendor < X86_VENDOR_NUM)
75 mtrr_ops[ops->vendor] = ops;
78 /* Returns non-zero if we have the write-combining memory type */
79 static int have_wrcomb(void)
83 dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL);
86 * ServerWorks LE chipsets < rev 6 have problems with
87 * write-combining. Don't allow it and leave room for other
88 * chipsets to be tagged
90 if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
91 dev->device == PCI_DEVICE_ID_SERVERWORKS_LE &&
93 pr_info("mtrr: Serverworks LE rev < 6 detected. Write-combining disabled.\n");
98 * Intel 450NX errata # 23. Non ascending cacheline evictions to
99 * write combining memory may resulting in data corruption
101 if (dev->vendor == PCI_VENDOR_ID_INTEL &&
102 dev->device == PCI_DEVICE_ID_INTEL_82451NX) {
103 pr_info("mtrr: Intel 450NX MMC detected. Write-combining disabled.\n");
109 return mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0;
112 /* This function returns the number of variable MTRRs */
113 static void __init set_num_var_ranges(void)
115 unsigned long config = 0, dummy;
118 rdmsr(MSR_MTRRcap, config, dummy);
119 else if (is_cpu(AMD))
121 else if (is_cpu(CYRIX) || is_cpu(CENTAUR))
124 num_var_ranges = config & 0xff;
127 static void __init init_table(void)
131 max = num_var_ranges;
132 for (i = 0; i < max; i++)
133 mtrr_usage_table[i] = 1;
136 struct set_mtrr_data {
137 unsigned long smp_base;
138 unsigned long smp_size;
139 unsigned int smp_reg;
144 * mtrr_rendezvous_handler - Work done in the synchronization handler. Executed
146 * @info: pointer to mtrr configuration data
150 static int mtrr_rendezvous_handler(void *info)
153 struct set_mtrr_data *data = info;
156 * We use this same function to initialize the mtrrs during boot,
157 * resume, runtime cpu online and on an explicit request to set a
160 * During boot or suspend, the state of the boot cpu's mtrrs has been
161 * saved, and we want to replicate that across all the cpus that come
162 * online (either at the end of boot or resume or during a runtime cpu
163 * online). If we're doing that, @reg is set to something special and on
164 * all the cpu's we do mtrr_if->set_all() (On the logical cpu that
165 * started the boot/resume sequence, this might be a duplicate
168 if (data->smp_reg != ~0U) {
169 mtrr_if->set(data->smp_reg, data->smp_base,
170 data->smp_size, data->smp_type);
171 } else if (mtrr_aps_delayed_init || !cpu_online(smp_processor_id())) {
178 static inline int types_compatible(mtrr_type type1, mtrr_type type2)
180 return type1 == MTRR_TYPE_UNCACHABLE ||
181 type2 == MTRR_TYPE_UNCACHABLE ||
182 (type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK) ||
183 (type1 == MTRR_TYPE_WRBACK && type2 == MTRR_TYPE_WRTHROUGH);
187 * set_mtrr - update mtrrs on all processors
188 * @reg: mtrr in question
193 * This is kinda tricky, but fortunately, Intel spelled it out for us cleanly:
195 * 1. Queue work to do the following on all processors:
196 * 2. Disable Interrupts
197 * 3. Wait for all procs to do so
198 * 4. Enter no-fill cache mode
202 * 8. Disable all range registers
203 * 9. Update the MTRRs
204 * 10. Enable all range registers
205 * 11. Flush all TLBs and caches again
206 * 12. Enter normal cache mode and reenable caching
208 * 14. Wait for buddies to catch up
209 * 15. Enable interrupts.
211 * What does that mean for us? Well, stop_machine() will ensure that
212 * the rendezvous handler is started on each CPU. And in lockstep they
213 * do the state transition of disabling interrupts, updating MTRR's
214 * (the CPU vendors may each do it differently, so we call mtrr_if->set()
215 * callback and let them take care of it.) and enabling interrupts.
217 * Note that the mechanism is the same for UP systems, too; all the SMP stuff
221 set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type)
223 struct set_mtrr_data data = { .smp_reg = reg,
229 stop_machine(mtrr_rendezvous_handler, &data, cpu_online_mask);
232 static void set_mtrr_from_inactive_cpu(unsigned int reg, unsigned long base,
233 unsigned long size, mtrr_type type)
235 struct set_mtrr_data data = { .smp_reg = reg,
241 stop_machine_from_inactive_cpu(mtrr_rendezvous_handler, &data,
246 * mtrr_add_page - Add a memory type region
247 * @base: Physical base address of region in pages (in units of 4 kB!)
248 * @size: Physical size of region in pages (4 kB)
249 * @type: Type of MTRR desired
250 * @increment: If this is true do usage counting on the region
252 * Memory type region registers control the caching on newer Intel and
253 * non Intel processors. This function allows drivers to request an
254 * MTRR is added. The details and hardware specifics of each processor's
255 * implementation are hidden from the caller, but nevertheless the
256 * caller should expect to need to provide a power of two size on an
257 * equivalent power of two boundary.
259 * If the region cannot be added either because all regions are in use
260 * or the CPU cannot support it a negative value is returned. On success
261 * the register number for this entry is returned, but should be treated
264 * On a multiprocessor machine the changes are made to all processors.
265 * This is required on x86 by the Intel processors.
267 * The available types are
269 * %MTRR_TYPE_UNCACHABLE - No caching
271 * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
273 * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
275 * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
277 * BUGS: Needs a quiet flag for the cases where drivers do not mind
278 * failures and do not wish system log messages to be sent.
280 int mtrr_add_page(unsigned long base, unsigned long size,
281 unsigned int type, bool increment)
283 unsigned long lbase, lsize;
284 int i, replace, error;
290 error = mtrr_if->validate_add_page(base, size, type);
294 if (type >= MTRR_NUM_TYPES) {
295 pr_warning("mtrr: type: %u invalid\n", type);
299 /* If the type is WC, check that this processor supports it */
300 if ((type == MTRR_TYPE_WRCOMB) && !have_wrcomb()) {
301 pr_warning("mtrr: your processor doesn't support write-combining\n");
306 pr_warning("mtrr: zero sized request\n");
310 if (base & size_or_mask || size & size_or_mask) {
311 pr_warning("mtrr: base or size exceeds the MTRR width\n");
318 /* No CPU hotplug when we change MTRR entries */
321 /* Search for existing MTRR */
322 mutex_lock(&mtrr_mutex);
323 for (i = 0; i < num_var_ranges; ++i) {
324 mtrr_if->get(i, &lbase, &lsize, <ype);
325 if (!lsize || base > lbase + lsize - 1 ||
326 base + size - 1 < lbase)
329 * At this point we know there is some kind of
332 if (base < lbase || base + size - 1 > lbase + lsize - 1) {
334 base + size - 1 >= lbase + lsize - 1) {
335 /* New region encloses an existing region */
337 replace = replace == -1 ? i : -2;
339 } else if (types_compatible(type, ltype))
342 pr_warning("mtrr: 0x%lx000,0x%lx000 overlaps existing"
343 " 0x%lx000,0x%lx000\n", base, size, lbase,
347 /* New region is enclosed by an existing region */
349 if (types_compatible(type, ltype))
351 pr_warning("mtrr: type mismatch for %lx000,%lx000 old: %s new: %s\n",
352 base, size, mtrr_attrib_to_str(ltype),
353 mtrr_attrib_to_str(type));
357 ++mtrr_usage_table[i];
361 /* Search for an empty MTRR */
362 i = mtrr_if->get_free_region(base, size, replace);
364 set_mtrr(i, base, size, type);
365 if (likely(replace < 0)) {
366 mtrr_usage_table[i] = 1;
368 mtrr_usage_table[i] = mtrr_usage_table[replace];
370 mtrr_usage_table[i]++;
371 if (unlikely(replace != i)) {
372 set_mtrr(replace, 0, 0, 0);
373 mtrr_usage_table[replace] = 0;
377 pr_info("mtrr: no more MTRRs available\n");
381 mutex_unlock(&mtrr_mutex);
386 static int mtrr_check(unsigned long base, unsigned long size)
388 if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) {
389 pr_warning("mtrr: size and base must be multiples of 4 kiB\n");
390 pr_debug("mtrr: size: 0x%lx base: 0x%lx\n", size, base);
398 * mtrr_add - Add a memory type region
399 * @base: Physical base address of region
400 * @size: Physical size of region
401 * @type: Type of MTRR desired
402 * @increment: If this is true do usage counting on the region
404 * Memory type region registers control the caching on newer Intel and
405 * non Intel processors. This function allows drivers to request an
406 * MTRR is added. The details and hardware specifics of each processor's
407 * implementation are hidden from the caller, but nevertheless the
408 * caller should expect to need to provide a power of two size on an
409 * equivalent power of two boundary.
411 * If the region cannot be added either because all regions are in use
412 * or the CPU cannot support it a negative value is returned. On success
413 * the register number for this entry is returned, but should be treated
416 * On a multiprocessor machine the changes are made to all processors.
417 * This is required on x86 by the Intel processors.
419 * The available types are
421 * %MTRR_TYPE_UNCACHABLE - No caching
423 * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
425 * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
427 * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
429 * BUGS: Needs a quiet flag for the cases where drivers do not mind
430 * failures and do not wish system log messages to be sent.
432 int mtrr_add(unsigned long base, unsigned long size, unsigned int type,
435 if (mtrr_check(base, size))
437 return mtrr_add_page(base >> PAGE_SHIFT, size >> PAGE_SHIFT, type,
440 EXPORT_SYMBOL(mtrr_add);
443 * mtrr_del_page - delete a memory type region
444 * @reg: Register returned by mtrr_add
445 * @base: Physical base address
446 * @size: Size of region
448 * If register is supplied then base and size are ignored. This is
449 * how drivers should call it.
451 * Releases an MTRR region. If the usage count drops to zero the
452 * register is freed and the region returns to default state.
453 * On success the register is returned, on failure a negative error
456 int mtrr_del_page(int reg, unsigned long base, unsigned long size)
460 unsigned long lbase, lsize;
466 max = num_var_ranges;
467 /* No CPU hotplug when we change MTRR entries */
469 mutex_lock(&mtrr_mutex);
471 /* Search for existing MTRR */
472 for (i = 0; i < max; ++i) {
473 mtrr_if->get(i, &lbase, &lsize, <ype);
474 if (lbase == base && lsize == size) {
480 pr_debug("mtrr: no MTRR for %lx000,%lx000 found\n",
486 pr_warning("mtrr: register: %d too big\n", reg);
489 mtrr_if->get(reg, &lbase, &lsize, <ype);
491 pr_warning("mtrr: MTRR %d not used\n", reg);
494 if (mtrr_usage_table[reg] < 1) {
495 pr_warning("mtrr: reg: %d has count=0\n", reg);
498 if (--mtrr_usage_table[reg] < 1)
499 set_mtrr(reg, 0, 0, 0);
502 mutex_unlock(&mtrr_mutex);
508 * mtrr_del - delete a memory type region
509 * @reg: Register returned by mtrr_add
510 * @base: Physical base address
511 * @size: Size of region
513 * If register is supplied then base and size are ignored. This is
514 * how drivers should call it.
516 * Releases an MTRR region. If the usage count drops to zero the
517 * register is freed and the region returns to default state.
518 * On success the register is returned, on failure a negative error
521 int mtrr_del(int reg, unsigned long base, unsigned long size)
523 if (mtrr_check(base, size))
525 return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT);
527 EXPORT_SYMBOL(mtrr_del);
531 * These should be called implicitly, but we can't yet until all the initcall
534 static void __init init_ifs(void)
536 #ifndef CONFIG_X86_64
543 /* The suspend/resume methods are only for CPU without MTRR. CPU using generic
544 * MTRR driver doesn't require this
552 static struct mtrr_value mtrr_value[MTRR_MAX_VAR_RANGES];
554 static int mtrr_save(void)
558 for (i = 0; i < num_var_ranges; i++) {
559 mtrr_if->get(i, &mtrr_value[i].lbase,
560 &mtrr_value[i].lsize,
561 &mtrr_value[i].ltype);
566 static void mtrr_restore(void)
570 for (i = 0; i < num_var_ranges; i++) {
571 if (mtrr_value[i].lsize) {
572 set_mtrr(i, mtrr_value[i].lbase,
574 mtrr_value[i].ltype);
581 static struct syscore_ops mtrr_syscore_ops = {
582 .suspend = mtrr_save,
583 .resume = mtrr_restore,
586 int __initdata changed_by_mtrr_cleanup;
589 * mtrr_bp_init - initialize mtrrs on the boot CPU
591 * This needs to be called early; before any of the other CPUs are
592 * initialized (i.e. before smp_init()).
595 void __init mtrr_bp_init(void)
604 mtrr_if = &generic_mtrr_ops;
605 size_or_mask = 0xff000000; /* 36 bits */
606 size_and_mask = 0x00f00000;
610 * This is an AMD specific MSR, but we assume(hope?) that
611 * Intel will implement it to when they extend the address
614 if (cpuid_eax(0x80000000) >= 0x80000008) {
615 phys_addr = cpuid_eax(0x80000008) & 0xff;
616 /* CPUID workaround for Intel 0F33/0F34 CPU */
617 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
618 boot_cpu_data.x86 == 0xF &&
619 boot_cpu_data.x86_model == 0x3 &&
620 (boot_cpu_data.x86_mask == 0x3 ||
621 boot_cpu_data.x86_mask == 0x4))
624 size_or_mask = ~((1ULL << (phys_addr - PAGE_SHIFT)) - 1);
625 size_and_mask = ~size_or_mask & 0xfffff00000ULL;
626 } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR &&
627 boot_cpu_data.x86 == 6) {
629 * VIA C* family have Intel style MTRRs,
630 * but don't support PAE
632 size_or_mask = 0xfff00000; /* 32 bits */
637 switch (boot_cpu_data.x86_vendor) {
639 if (cpu_has_k6_mtrr) {
640 /* Pre-Athlon (K6) AMD CPU MTRRs */
641 mtrr_if = mtrr_ops[X86_VENDOR_AMD];
642 size_or_mask = 0xfff00000; /* 32 bits */
646 case X86_VENDOR_CENTAUR:
647 if (cpu_has_centaur_mcr) {
648 mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR];
649 size_or_mask = 0xfff00000; /* 32 bits */
653 case X86_VENDOR_CYRIX:
654 if (cpu_has_cyrix_arr) {
655 mtrr_if = mtrr_ops[X86_VENDOR_CYRIX];
656 size_or_mask = 0xfff00000; /* 32 bits */
666 set_num_var_ranges();
671 if (mtrr_cleanup(phys_addr)) {
672 changed_by_mtrr_cleanup = 1;
679 void mtrr_ap_init(void)
681 if (!use_intel() || mtrr_aps_delayed_init)
684 * Ideally we should hold mtrr_mutex here to avoid mtrr entries
685 * changed, but this routine will be called in cpu boot time,
686 * holding the lock breaks it.
688 * This routine is called in two cases:
690 * 1. very earily time of software resume, when there absolutely
691 * isn't mtrr entry changes;
693 * 2. cpu hotadd time. We let mtrr_add/del_page hold cpuhotplug
694 * lock to prevent mtrr entry changes
696 set_mtrr_from_inactive_cpu(~0U, 0, 0, 0);
700 * Save current fixed-range MTRR state of the BSP
702 void mtrr_save_state(void)
704 smp_call_function_single(0, mtrr_save_fixed_ranges, NULL, 1);
707 void set_mtrr_aps_delayed_init(void)
712 mtrr_aps_delayed_init = true;
716 * Delayed MTRR initialization for all AP's
718 void mtrr_aps_init(void)
724 * Check if someone has requested the delay of AP MTRR initialization,
725 * by doing set_mtrr_aps_delayed_init(), prior to this point. If not,
728 if (!mtrr_aps_delayed_init)
731 set_mtrr(~0U, 0, 0, 0);
732 mtrr_aps_delayed_init = false;
735 void mtrr_bp_restore(void)
743 static int __init mtrr_init_finialize(void)
749 if (!changed_by_mtrr_cleanup)
755 * The CPU has no MTRR and seems to not support SMP. They have
756 * specific drivers, we use a tricky method to support
757 * suspend/resume for them.
759 * TBD: is there any system with such CPU which supports
760 * suspend/resume? If no, we should remove the code.
762 register_syscore_ops(&mtrr_syscore_ops);
766 subsys_initcall(mtrr_init_finialize);