2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/ratelimit.h>
14 #include <linux/kallsyms.h>
15 #include <linux/rcupdate.h>
16 #include <linux/kobject.h>
17 #include <linux/uaccess.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/sysdev.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
30 #include <linux/init.h>
31 #include <linux/kmod.h>
32 #include <linux/poll.h>
33 #include <linux/nmi.h>
34 #include <linux/cpu.h>
35 #include <linux/smp.h>
38 #include <linux/debugfs.h>
39 #include <linux/edac_mce.h>
40 #include <linux/irq_work.h>
42 #include <asm/processor.h>
46 #include "mce-internal.h"
48 static DEFINE_MUTEX(mce_chrdev_read_mutex);
50 #define rcu_dereference_check_mce(p) \
51 rcu_dereference_index_check((p), \
52 rcu_read_lock_sched_held() || \
53 lockdep_is_held(&mce_chrdev_read_mutex))
55 #define CREATE_TRACE_POINTS
56 #include <trace/events/mce.h>
58 int mce_disabled __read_mostly;
60 #define MISC_MCELOG_MINOR 227
62 #define SPINUNIT 100 /* 100ns */
66 DEFINE_PER_CPU(unsigned, mce_exception_count);
70 * 0: always panic on uncorrected errors, log corrected errors
71 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
72 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
73 * 3: never panic or SIGBUS, log all errors (for testing only)
75 static int tolerant __read_mostly = 1;
76 static int banks __read_mostly;
77 static int rip_msr __read_mostly;
78 static int mce_bootlog __read_mostly = -1;
79 static int monarch_timeout __read_mostly = -1;
80 static int mce_panic_timeout __read_mostly;
81 static int mce_dont_log_ce __read_mostly;
82 int mce_cmci_disabled __read_mostly;
83 int mce_ignore_ce __read_mostly;
84 int mce_ser __read_mostly;
86 struct mce_bank *mce_banks __read_mostly;
88 /* User mode helper program triggered by machine check event */
89 static unsigned long mce_need_notify;
90 static char mce_helper[128];
91 static char *mce_helper_argv[2] = { mce_helper, NULL };
93 static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait);
95 static DEFINE_PER_CPU(struct mce, mces_seen);
96 static int cpu_missing;
99 * CPU/chipset specific EDAC code can register a notifier call here to print
100 * MCE errors in a human-readable form.
102 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
103 EXPORT_SYMBOL_GPL(x86_mce_decoder_chain);
105 /* MCA banks polled by the period polling timer for corrected events */
106 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
107 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
110 static DEFINE_PER_CPU(struct work_struct, mce_work);
112 /* Do initial initialization of a struct mce */
113 void mce_setup(struct mce *m)
115 memset(m, 0, sizeof(struct mce));
116 m->cpu = m->extcpu = smp_processor_id();
118 /* We hope get_seconds stays lockless */
119 m->time = get_seconds();
120 m->cpuvendor = boot_cpu_data.x86_vendor;
121 m->cpuid = cpuid_eax(1);
123 m->socketid = cpu_data(m->extcpu).phys_proc_id;
125 m->apicid = cpu_data(m->extcpu).initial_apicid;
126 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
129 DEFINE_PER_CPU(struct mce, injectm);
130 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
133 * Lockless MCE logging infrastructure.
134 * This avoids deadlocks on printk locks without having to break locks. Also
135 * separate MCEs from kernel messages to avoid bogus bug reports.
138 static struct mce_log mcelog = {
139 .signature = MCE_LOG_SIGNATURE,
141 .recordlen = sizeof(struct mce),
144 void mce_log(struct mce *mce)
146 unsigned next, entry;
149 /* Emit the trace record: */
150 trace_mce_record(mce);
152 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce);
153 if (ret == NOTIFY_STOP)
159 entry = rcu_dereference_check_mce(mcelog.next);
163 * When the buffer fills up discard new entries.
164 * Assume that the earlier errors are the more
167 if (entry >= MCE_LOG_LEN) {
168 set_bit(MCE_OVERFLOW,
169 (unsigned long *)&mcelog.flags);
172 /* Old left over entry. Skip: */
173 if (mcelog.entry[entry].finished) {
181 if (cmpxchg(&mcelog.next, entry, next) == entry)
184 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
186 mcelog.entry[entry].finished = 1;
190 set_bit(0, &mce_need_notify);
193 static void print_mce(struct mce *m)
197 pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
198 m->extcpu, m->mcgstatus, m->bank, m->status);
201 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
202 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
205 if (m->cs == __KERNEL_CS)
206 print_symbol("{%s}", m->ip);
210 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
212 pr_cont("ADDR %llx ", m->addr);
214 pr_cont("MISC %llx ", m->misc);
217 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
218 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
221 * Print out human-readable details about the MCE error,
222 * (if the CPU has an implementation for that)
224 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
225 if (ret == NOTIFY_STOP)
228 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
231 #define PANIC_TIMEOUT 5 /* 5 seconds */
233 static atomic_t mce_paniced;
235 static int fake_panic;
236 static atomic_t mce_fake_paniced;
238 /* Panic in progress. Enable interrupts and wait for final IPI */
239 static void wait_for_panic(void)
241 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
245 while (timeout-- > 0)
247 if (panic_timeout == 0)
248 panic_timeout = mce_panic_timeout;
249 panic("Panicing machine check CPU died");
252 static void mce_panic(char *msg, struct mce *final, char *exp)
258 * Make sure only one CPU runs in machine check panic
260 if (atomic_inc_return(&mce_paniced) > 1)
267 /* Don't log too much for fake panic */
268 if (atomic_inc_return(&mce_fake_paniced) > 1)
271 /* First print corrected ones that are still unlogged */
272 for (i = 0; i < MCE_LOG_LEN; i++) {
273 struct mce *m = &mcelog.entry[i];
274 if (!(m->status & MCI_STATUS_VAL))
276 if (!(m->status & MCI_STATUS_UC)) {
279 apei_err = apei_write_mce(m);
282 /* Now print uncorrected but with the final one last */
283 for (i = 0; i < MCE_LOG_LEN; i++) {
284 struct mce *m = &mcelog.entry[i];
285 if (!(m->status & MCI_STATUS_VAL))
287 if (!(m->status & MCI_STATUS_UC))
289 if (!final || memcmp(m, final, sizeof(struct mce))) {
292 apei_err = apei_write_mce(m);
298 apei_err = apei_write_mce(final);
301 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
303 pr_emerg(HW_ERR "Machine check: %s\n", exp);
305 if (panic_timeout == 0)
306 panic_timeout = mce_panic_timeout;
309 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
312 /* Support code for software error injection */
314 static int msr_to_offset(u32 msr)
316 unsigned bank = __this_cpu_read(injectm.bank);
319 return offsetof(struct mce, ip);
320 if (msr == MSR_IA32_MCx_STATUS(bank))
321 return offsetof(struct mce, status);
322 if (msr == MSR_IA32_MCx_ADDR(bank))
323 return offsetof(struct mce, addr);
324 if (msr == MSR_IA32_MCx_MISC(bank))
325 return offsetof(struct mce, misc);
326 if (msr == MSR_IA32_MCG_STATUS)
327 return offsetof(struct mce, mcgstatus);
331 /* MSR access wrappers used for error injection */
332 static u64 mce_rdmsrl(u32 msr)
336 if (__this_cpu_read(injectm.finished)) {
337 int offset = msr_to_offset(msr);
341 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
344 if (rdmsrl_safe(msr, &v)) {
345 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
347 * Return zero in case the access faulted. This should
348 * not happen normally but can happen if the CPU does
349 * something weird, or if the code is buggy.
357 static void mce_wrmsrl(u32 msr, u64 v)
359 if (__this_cpu_read(injectm.finished)) {
360 int offset = msr_to_offset(msr);
363 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
370 * Collect all global (w.r.t. this processor) status about this machine
371 * check into our "mce" struct so that we can use it later to assess
372 * the severity of the problem as we read per-bank specific details.
374 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
378 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
381 * Get the address of the instruction at the time of
382 * the machine check error.
384 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
388 /* Use accurate RIP reporting if available. */
390 m->ip = mce_rdmsrl(rip_msr);
395 * Simple lockless ring to communicate PFNs from the exception handler with the
396 * process context work function. This is vastly simplified because there's
397 * only a single reader and a single writer.
399 #define MCE_RING_SIZE 16 /* we use one entry less */
402 unsigned short start;
404 unsigned long ring[MCE_RING_SIZE];
406 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
408 /* Runs with CPU affinity in workqueue */
409 static int mce_ring_empty(void)
411 struct mce_ring *r = &__get_cpu_var(mce_ring);
413 return r->start == r->end;
416 static int mce_ring_get(unsigned long *pfn)
423 r = &__get_cpu_var(mce_ring);
424 if (r->start == r->end)
426 *pfn = r->ring[r->start];
427 r->start = (r->start + 1) % MCE_RING_SIZE;
434 /* Always runs in MCE context with preempt off */
435 static int mce_ring_add(unsigned long pfn)
437 struct mce_ring *r = &__get_cpu_var(mce_ring);
440 next = (r->end + 1) % MCE_RING_SIZE;
441 if (next == r->start)
443 r->ring[r->end] = pfn;
449 int mce_available(struct cpuinfo_x86 *c)
453 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
456 static void mce_schedule_work(void)
458 if (!mce_ring_empty()) {
459 struct work_struct *work = &__get_cpu_var(mce_work);
460 if (!work_pending(work))
465 DEFINE_PER_CPU(struct irq_work, mce_irq_work);
467 static void mce_irq_work_cb(struct irq_work *entry)
473 static void mce_report_event(struct pt_regs *regs)
475 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
478 * Triggering the work queue here is just an insurance
479 * policy in case the syscall exit notify handler
480 * doesn't run soon enough or ends up running on the
481 * wrong CPU (can happen when audit sleeps)
487 irq_work_queue(&__get_cpu_var(mce_irq_work));
490 DEFINE_PER_CPU(unsigned, mce_poll_count);
493 * Poll for corrected events or events that happened before reset.
494 * Those are just logged through /dev/mcelog.
496 * This is executed in standard interrupt context.
498 * Note: spec recommends to panic for fatal unsignalled
499 * errors here. However this would be quite problematic --
500 * we would need to reimplement the Monarch handling and
501 * it would mess up the exclusion between exception handler
502 * and poll hander -- * so we skip this for now.
503 * These cases should not happen anyways, or only when the CPU
504 * is already totally * confused. In this case it's likely it will
505 * not fully execute the machine check handler either.
507 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
512 percpu_inc(mce_poll_count);
514 mce_gather_info(&m, NULL);
516 for (i = 0; i < banks; i++) {
517 if (!mce_banks[i].ctl || !test_bit(i, *b))
526 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
527 if (!(m.status & MCI_STATUS_VAL))
531 * Uncorrected or signalled events are handled by the exception
532 * handler when it is enabled, so don't process those here.
534 * TBD do the same check for MCI_STATUS_EN here?
536 if (!(flags & MCP_UC) &&
537 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
540 if (m.status & MCI_STATUS_MISCV)
541 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
542 if (m.status & MCI_STATUS_ADDRV)
543 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
545 if (!(flags & MCP_TIMESTAMP))
548 * Don't get the IP here because it's unlikely to
549 * have anything to do with the actual error location.
551 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce)
555 * Clear state for this bank.
557 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
561 * Don't clear MCG_STATUS here because it's only defined for
567 EXPORT_SYMBOL_GPL(machine_check_poll);
570 * Do a quick check if any of the events requires a panic.
571 * This decides if we keep the events around or clear them.
573 static int mce_no_way_out(struct mce *m, char **msg)
577 for (i = 0; i < banks; i++) {
578 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
579 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
586 * Variable to establish order between CPUs while scanning.
587 * Each CPU spins initially until executing is equal its number.
589 static atomic_t mce_executing;
592 * Defines order of CPUs on entry. First CPU becomes Monarch.
594 static atomic_t mce_callin;
597 * Check if a timeout waiting for other CPUs happened.
599 static int mce_timed_out(u64 *t)
602 * The others already did panic for some reason.
603 * Bail out like in a timeout.
604 * rmb() to tell the compiler that system_state
605 * might have been modified by someone else.
608 if (atomic_read(&mce_paniced))
610 if (!monarch_timeout)
612 if ((s64)*t < SPINUNIT) {
613 /* CHECKME: Make panic default for 1 too? */
615 mce_panic("Timeout synchronizing machine check over CPUs",
622 touch_nmi_watchdog();
627 * The Monarch's reign. The Monarch is the CPU who entered
628 * the machine check handler first. It waits for the others to
629 * raise the exception too and then grades them. When any
630 * error is fatal panic. Only then let the others continue.
632 * The other CPUs entering the MCE handler will be controlled by the
633 * Monarch. They are called Subjects.
635 * This way we prevent any potential data corruption in a unrecoverable case
636 * and also makes sure always all CPU's errors are examined.
638 * Also this detects the case of a machine check event coming from outer
639 * space (not detected by any CPUs) In this case some external agent wants
640 * us to shut down, so panic too.
642 * The other CPUs might still decide to panic if the handler happens
643 * in a unrecoverable place, but in this case the system is in a semi-stable
644 * state and won't corrupt anything by itself. It's ok to let the others
645 * continue for a bit first.
647 * All the spin loops have timeouts; when a timeout happens a CPU
648 * typically elects itself to be Monarch.
650 static void mce_reign(void)
653 struct mce *m = NULL;
654 int global_worst = 0;
659 * This CPU is the Monarch and the other CPUs have run
660 * through their handlers.
661 * Grade the severity of the errors of all the CPUs.
663 for_each_possible_cpu(cpu) {
664 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
666 if (severity > global_worst) {
668 global_worst = severity;
669 m = &per_cpu(mces_seen, cpu);
674 * Cannot recover? Panic here then.
675 * This dumps all the mces in the log buffer and stops the
678 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
679 mce_panic("Fatal Machine check", m, msg);
682 * For UC somewhere we let the CPU who detects it handle it.
683 * Also must let continue the others, otherwise the handling
684 * CPU could deadlock on a lock.
688 * No machine check event found. Must be some external
689 * source or one CPU is hung. Panic.
691 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
692 mce_panic("Machine check from unknown source", NULL, NULL);
695 * Now clear all the mces_seen so that they don't reappear on
698 for_each_possible_cpu(cpu)
699 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
702 static atomic_t global_nwo;
705 * Start of Monarch synchronization. This waits until all CPUs have
706 * entered the exception handler and then determines if any of them
707 * saw a fatal event that requires panic. Then it executes them
708 * in the entry order.
709 * TBD double check parallel CPU hotunplug
711 static int mce_start(int *no_way_out)
714 int cpus = num_online_cpus();
715 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
720 atomic_add(*no_way_out, &global_nwo);
722 * global_nwo should be updated before mce_callin
725 order = atomic_inc_return(&mce_callin);
730 while (atomic_read(&mce_callin) != cpus) {
731 if (mce_timed_out(&timeout)) {
732 atomic_set(&global_nwo, 0);
739 * mce_callin should be read before global_nwo
745 * Monarch: Starts executing now, the others wait.
747 atomic_set(&mce_executing, 1);
750 * Subject: Now start the scanning loop one by one in
751 * the original callin order.
752 * This way when there are any shared banks it will be
753 * only seen by one CPU before cleared, avoiding duplicates.
755 while (atomic_read(&mce_executing) < order) {
756 if (mce_timed_out(&timeout)) {
757 atomic_set(&global_nwo, 0);
765 * Cache the global no_way_out state.
767 *no_way_out = atomic_read(&global_nwo);
773 * Synchronize between CPUs after main scanning loop.
774 * This invokes the bulk of the Monarch processing.
776 static int mce_end(int order)
779 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
787 * Allow others to run.
789 atomic_inc(&mce_executing);
792 /* CHECKME: Can this race with a parallel hotplug? */
793 int cpus = num_online_cpus();
796 * Monarch: Wait for everyone to go through their scanning
799 while (atomic_read(&mce_executing) <= cpus) {
800 if (mce_timed_out(&timeout))
810 * Subject: Wait for Monarch to finish.
812 while (atomic_read(&mce_executing) != 0) {
813 if (mce_timed_out(&timeout))
819 * Don't reset anything. That's done by the Monarch.
825 * Reset all global state.
828 atomic_set(&global_nwo, 0);
829 atomic_set(&mce_callin, 0);
833 * Let others run again.
835 atomic_set(&mce_executing, 0);
840 * Check if the address reported by the CPU is in a format we can parse.
841 * It would be possible to add code for most other cases, but all would
842 * be somewhat complicated (e.g. segment offset would require an instruction
843 * parser). So only support physical addresses up to page granuality for now.
845 static int mce_usable_address(struct mce *m)
847 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
849 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
851 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
856 static void mce_clear_state(unsigned long *toclear)
860 for (i = 0; i < banks; i++) {
861 if (test_bit(i, toclear))
862 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
867 * The actual machine check handler. This only handles real
868 * exceptions when something got corrupted coming in through int 18.
870 * This is executed in NMI context not subject to normal locking rules. This
871 * implies that most kernel services cannot be safely used. Don't even
872 * think about putting a printk in there!
874 * On Intel systems this is entered on all CPUs in parallel through
875 * MCE broadcast. However some CPUs might be broken beyond repair,
876 * so be always careful when synchronizing with others.
878 void do_machine_check(struct pt_regs *regs, long error_code)
880 struct mce m, *final;
885 * Establish sequential order between the CPUs entering the machine
890 * If no_way_out gets set, there is no safe way to recover from this
891 * MCE. If tolerant is cranked up, we'll try anyway.
895 * If kill_it gets set, there might be a way to recover from this
899 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
900 char *msg = "Unknown";
902 atomic_inc(&mce_entry);
904 percpu_inc(mce_exception_count);
906 if (notify_die(DIE_NMI, "machine check", regs, error_code,
907 18, SIGKILL) == NOTIFY_STOP)
912 mce_gather_info(&m, regs);
914 final = &__get_cpu_var(mces_seen);
917 no_way_out = mce_no_way_out(&m, &msg);
922 * When no restart IP must always kill or panic.
924 if (!(m.mcgstatus & MCG_STATUS_RIPV))
928 * Go through all the banks in exclusion of the other CPUs.
929 * This way we don't report duplicated events on shared banks
930 * because the first one to see it will clear it.
932 order = mce_start(&no_way_out);
933 for (i = 0; i < banks; i++) {
934 __clear_bit(i, toclear);
935 if (!mce_banks[i].ctl)
942 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
943 if ((m.status & MCI_STATUS_VAL) == 0)
947 * Non uncorrected or non signaled errors are handled by
948 * machine_check_poll. Leave them alone, unless this panics.
950 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
955 * Set taint even when machine check was not enabled.
957 add_taint(TAINT_MACHINE_CHECK);
959 severity = mce_severity(&m, tolerant, NULL);
962 * When machine check was for corrected handler don't touch,
963 * unless we're panicing.
965 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
967 __set_bit(i, toclear);
968 if (severity == MCE_NO_SEVERITY) {
970 * Machine check event was not enabled. Clear, but
977 * Kill on action required.
979 if (severity == MCE_AR_SEVERITY)
982 if (m.status & MCI_STATUS_MISCV)
983 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
984 if (m.status & MCI_STATUS_ADDRV)
985 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
988 * Action optional error. Queue address for later processing.
989 * When the ring overflows we just ignore the AO error.
990 * RED-PEN add some logging mechanism when
991 * usable_address or mce_add_ring fails.
992 * RED-PEN don't ignore overflow for tolerant == 0
994 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
995 mce_ring_add(m.addr >> PAGE_SHIFT);
999 if (severity > worst) {
1006 mce_clear_state(toclear);
1009 * Do most of the synchronization with other CPUs.
1010 * When there's any problem use only local no_way_out state.
1012 if (mce_end(order) < 0)
1013 no_way_out = worst >= MCE_PANIC_SEVERITY;
1016 * If we have decided that we just CAN'T continue, and the user
1017 * has not set tolerant to an insane level, give up and die.
1019 * This is mainly used in the case when the system doesn't
1020 * support MCE broadcasting or it has been disabled.
1022 if (no_way_out && tolerant < 3)
1023 mce_panic("Fatal machine check on current CPU", final, msg);
1026 * If the error seems to be unrecoverable, something should be
1027 * done. Try to kill as little as possible. If we can kill just
1028 * one task, do that. If the user has set the tolerance very
1029 * high, don't try to do anything at all.
1032 if (kill_it && tolerant < 3)
1033 force_sig(SIGBUS, current);
1035 /* notify userspace ASAP */
1036 set_thread_flag(TIF_MCE_NOTIFY);
1039 mce_report_event(regs);
1040 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1042 atomic_dec(&mce_entry);
1045 EXPORT_SYMBOL_GPL(do_machine_check);
1047 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1048 void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1050 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1054 * Called after mce notification in process context. This code
1055 * is allowed to sleep. Call the high level VM handler to process
1056 * any corrupted pages.
1057 * Assume that the work queue code only calls this one at a time
1059 * Note we don't disable preemption, so this code might run on the wrong
1060 * CPU. In this case the event is picked up by the scheduled work queue.
1061 * This is merely a fast path to expedite processing in some common
1064 void mce_notify_process(void)
1068 while (mce_ring_get(&pfn))
1069 memory_failure(pfn, MCE_VECTOR);
1072 static void mce_process_work(struct work_struct *dummy)
1074 mce_notify_process();
1077 #ifdef CONFIG_X86_MCE_INTEL
1079 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1080 * @cpu: The CPU on which the event occurred.
1081 * @status: Event status information
1083 * This function should be called by the thermal interrupt after the
1084 * event has been processed and the decision was made to log the event
1087 * The status parameter will be saved to the 'status' field of 'struct mce'
1088 * and historically has been the register value of the
1089 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1091 void mce_log_therm_throt_event(__u64 status)
1096 m.bank = MCE_THERMAL_BANK;
1100 #endif /* CONFIG_X86_MCE_INTEL */
1103 * Periodic polling timer for "silent" machine check errors. If the
1104 * poller finds an MCE, poll 2x faster. When the poller finds no more
1105 * errors, poll 2x slower (up to check_interval seconds).
1107 static int check_interval = 5 * 60; /* 5 minutes */
1109 static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
1110 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1112 static void mce_start_timer(unsigned long data)
1114 struct timer_list *t = &per_cpu(mce_timer, data);
1117 WARN_ON(smp_processor_id() != data);
1119 if (mce_available(__this_cpu_ptr(&cpu_info))) {
1120 machine_check_poll(MCP_TIMESTAMP,
1121 &__get_cpu_var(mce_poll_banks));
1125 * Alert userspace if needed. If we logged an MCE, reduce the
1126 * polling interval, otherwise increase the polling interval.
1128 n = &__get_cpu_var(mce_next_interval);
1129 if (mce_notify_irq())
1130 *n = max(*n/2, HZ/100);
1132 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1134 t->expires = jiffies + *n;
1135 add_timer_on(t, smp_processor_id());
1138 static void mce_do_trigger(struct work_struct *work)
1140 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1143 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1146 * Notify the user(s) about new machine check events.
1147 * Can be called from interrupt context, but not from machine check/NMI
1150 int mce_notify_irq(void)
1152 /* Not more than two messages every minute */
1153 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1155 clear_thread_flag(TIF_MCE_NOTIFY);
1157 if (test_and_clear_bit(0, &mce_need_notify)) {
1158 /* wake processes polling /dev/mcelog */
1159 wake_up_interruptible(&mce_chrdev_wait);
1162 * There is no risk of missing notifications because
1163 * work_pending is always cleared before the function is
1166 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1167 schedule_work(&mce_trigger_work);
1169 if (__ratelimit(&ratelimit))
1170 pr_info(HW_ERR "Machine check events logged\n");
1176 EXPORT_SYMBOL_GPL(mce_notify_irq);
1178 static int __cpuinit __mcheck_cpu_mce_banks_init(void)
1182 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1185 for (i = 0; i < banks; i++) {
1186 struct mce_bank *b = &mce_banks[i];
1195 * Initialize Machine Checks for a CPU.
1197 static int __cpuinit __mcheck_cpu_cap_init(void)
1202 rdmsrl(MSR_IA32_MCG_CAP, cap);
1204 b = cap & MCG_BANKCNT_MASK;
1206 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1208 if (b > MAX_NR_BANKS) {
1210 "MCE: Using only %u machine check banks out of %u\n",
1215 /* Don't support asymmetric configurations today */
1216 WARN_ON(banks != 0 && b != banks);
1219 int err = __mcheck_cpu_mce_banks_init();
1225 /* Use accurate RIP reporting if available. */
1226 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1227 rip_msr = MSR_IA32_MCG_EIP;
1229 if (cap & MCG_SER_P)
1235 static void __mcheck_cpu_init_generic(void)
1237 mce_banks_t all_banks;
1242 * Log the machine checks left over from the previous reset.
1244 bitmap_fill(all_banks, MAX_NR_BANKS);
1245 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1247 set_in_cr4(X86_CR4_MCE);
1249 rdmsrl(MSR_IA32_MCG_CAP, cap);
1250 if (cap & MCG_CTL_P)
1251 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1253 for (i = 0; i < banks; i++) {
1254 struct mce_bank *b = &mce_banks[i];
1258 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1259 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1263 /* Add per CPU specific workarounds here */
1264 static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1266 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1267 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1271 /* This should be disabled by the BIOS, but isn't always */
1272 if (c->x86_vendor == X86_VENDOR_AMD) {
1273 if (c->x86 == 15 && banks > 4) {
1275 * disable GART TBL walk error reporting, which
1276 * trips off incorrectly with the IOMMU & 3ware
1279 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1281 if (c->x86 <= 17 && mce_bootlog < 0) {
1283 * Lots of broken BIOS around that don't clear them
1284 * by default and leave crap in there. Don't log:
1289 * Various K7s with broken bank 0 around. Always disable
1292 if (c->x86 == 6 && banks > 0)
1293 mce_banks[0].ctl = 0;
1296 if (c->x86_vendor == X86_VENDOR_INTEL) {
1298 * SDM documents that on family 6 bank 0 should not be written
1299 * because it aliases to another special BIOS controlled
1301 * But it's not aliased anymore on model 0x1a+
1302 * Don't ignore bank 0 completely because there could be a
1303 * valid event later, merely don't write CTL0.
1306 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1307 mce_banks[0].init = 0;
1310 * All newer Intel systems support MCE broadcasting. Enable
1311 * synchronization with a one second timeout.
1313 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1314 monarch_timeout < 0)
1315 monarch_timeout = USEC_PER_SEC;
1318 * There are also broken BIOSes on some Pentium M and
1321 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1324 if (monarch_timeout < 0)
1325 monarch_timeout = 0;
1326 if (mce_bootlog != 0)
1327 mce_panic_timeout = 30;
1332 static int __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1337 switch (c->x86_vendor) {
1338 case X86_VENDOR_INTEL:
1339 intel_p5_mcheck_init(c);
1342 case X86_VENDOR_CENTAUR:
1343 winchip_mcheck_init(c);
1351 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1353 switch (c->x86_vendor) {
1354 case X86_VENDOR_INTEL:
1355 mce_intel_feature_init(c);
1357 case X86_VENDOR_AMD:
1358 mce_amd_feature_init(c);
1365 static void __mcheck_cpu_init_timer(void)
1367 struct timer_list *t = &__get_cpu_var(mce_timer);
1368 int *n = &__get_cpu_var(mce_next_interval);
1370 setup_timer(t, mce_start_timer, smp_processor_id());
1375 *n = check_interval * HZ;
1378 t->expires = round_jiffies(jiffies + *n);
1379 add_timer_on(t, smp_processor_id());
1382 /* Handle unconfigured int18 (should never happen) */
1383 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1385 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1386 smp_processor_id());
1389 /* Call the installed machine check handler for this CPU setup. */
1390 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1391 unexpected_machine_check;
1394 * Called for each booted CPU to set up machine checks.
1395 * Must be called with preempt off:
1397 void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
1402 if (__mcheck_cpu_ancient_init(c))
1405 if (!mce_available(c))
1408 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1413 machine_check_vector = do_machine_check;
1415 __mcheck_cpu_init_generic();
1416 __mcheck_cpu_init_vendor(c);
1417 __mcheck_cpu_init_timer();
1418 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1419 init_irq_work(&__get_cpu_var(mce_irq_work), &mce_irq_work_cb);
1423 * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.
1426 static DEFINE_SPINLOCK(mce_chrdev_state_lock);
1427 static int mce_chrdev_open_count; /* #times opened */
1428 static int mce_chrdev_open_exclu; /* already open exclusive? */
1430 static int mce_chrdev_open(struct inode *inode, struct file *file)
1432 spin_lock(&mce_chrdev_state_lock);
1434 if (mce_chrdev_open_exclu ||
1435 (mce_chrdev_open_count && (file->f_flags & O_EXCL))) {
1436 spin_unlock(&mce_chrdev_state_lock);
1441 if (file->f_flags & O_EXCL)
1442 mce_chrdev_open_exclu = 1;
1443 mce_chrdev_open_count++;
1445 spin_unlock(&mce_chrdev_state_lock);
1447 return nonseekable_open(inode, file);
1450 static int mce_chrdev_release(struct inode *inode, struct file *file)
1452 spin_lock(&mce_chrdev_state_lock);
1454 mce_chrdev_open_count--;
1455 mce_chrdev_open_exclu = 0;
1457 spin_unlock(&mce_chrdev_state_lock);
1462 static void collect_tscs(void *data)
1464 unsigned long *cpu_tsc = (unsigned long *)data;
1466 rdtscll(cpu_tsc[smp_processor_id()]);
1469 static int mce_apei_read_done;
1471 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1472 static int __mce_read_apei(char __user **ubuf, size_t usize)
1478 if (usize < sizeof(struct mce))
1481 rc = apei_read_mce(&m, &record_id);
1482 /* Error or no more MCE record */
1484 mce_apei_read_done = 1;
1488 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1491 * In fact, we should have cleared the record after that has
1492 * been flushed to the disk or sent to network in
1493 * /sbin/mcelog, but we have no interface to support that now,
1494 * so just clear it to avoid duplication.
1496 rc = apei_clear_mce(record_id);
1498 mce_apei_read_done = 1;
1501 *ubuf += sizeof(struct mce);
1506 static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf,
1507 size_t usize, loff_t *off)
1509 char __user *buf = ubuf;
1510 unsigned long *cpu_tsc;
1511 unsigned prev, next;
1514 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1518 mutex_lock(&mce_chrdev_read_mutex);
1520 if (!mce_apei_read_done) {
1521 err = __mce_read_apei(&buf, usize);
1522 if (err || buf != ubuf)
1526 next = rcu_dereference_check_mce(mcelog.next);
1528 /* Only supports full reads right now */
1530 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1536 for (i = prev; i < next; i++) {
1537 unsigned long start = jiffies;
1538 struct mce *m = &mcelog.entry[i];
1540 while (!m->finished) {
1541 if (time_after_eq(jiffies, start + 2)) {
1542 memset(m, 0, sizeof(*m));
1548 err |= copy_to_user(buf, m, sizeof(*m));
1554 memset(mcelog.entry + prev, 0,
1555 (next - prev) * sizeof(struct mce));
1557 next = cmpxchg(&mcelog.next, prev, 0);
1558 } while (next != prev);
1560 synchronize_sched();
1563 * Collect entries that were still getting written before the
1566 on_each_cpu(collect_tscs, cpu_tsc, 1);
1568 for (i = next; i < MCE_LOG_LEN; i++) {
1569 struct mce *m = &mcelog.entry[i];
1571 if (m->finished && m->tsc < cpu_tsc[m->cpu]) {
1572 err |= copy_to_user(buf, m, sizeof(*m));
1575 memset(m, 0, sizeof(*m));
1583 mutex_unlock(&mce_chrdev_read_mutex);
1586 return err ? err : buf - ubuf;
1589 static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait)
1591 poll_wait(file, &mce_chrdev_wait, wait);
1592 if (rcu_access_index(mcelog.next))
1593 return POLLIN | POLLRDNORM;
1594 if (!mce_apei_read_done && apei_check_mce())
1595 return POLLIN | POLLRDNORM;
1599 static long mce_chrdev_ioctl(struct file *f, unsigned int cmd,
1602 int __user *p = (int __user *)arg;
1604 if (!capable(CAP_SYS_ADMIN))
1608 case MCE_GET_RECORD_LEN:
1609 return put_user(sizeof(struct mce), p);
1610 case MCE_GET_LOG_LEN:
1611 return put_user(MCE_LOG_LEN, p);
1612 case MCE_GETCLEAR_FLAGS: {
1616 flags = mcelog.flags;
1617 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1619 return put_user(flags, p);
1626 /* Modified in mce-inject.c, so not static or const */
1627 struct file_operations mce_chrdev_ops = {
1628 .open = mce_chrdev_open,
1629 .release = mce_chrdev_release,
1630 .read = mce_chrdev_read,
1631 .poll = mce_chrdev_poll,
1632 .unlocked_ioctl = mce_chrdev_ioctl,
1633 .llseek = no_llseek,
1635 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
1637 static struct miscdevice mce_chrdev_device = {
1644 * mce=off Disables machine check
1645 * mce=no_cmci Disables CMCI
1646 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1647 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1648 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1649 * monarchtimeout is how long to wait for other CPUs on machine
1650 * check, or 0 to not wait
1651 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1652 * mce=nobootlog Don't log MCEs from before booting.
1654 static int __init mcheck_enable(char *str)
1662 if (!strcmp(str, "off"))
1664 else if (!strcmp(str, "no_cmci"))
1665 mce_cmci_disabled = 1;
1666 else if (!strcmp(str, "dont_log_ce"))
1667 mce_dont_log_ce = 1;
1668 else if (!strcmp(str, "ignore_ce"))
1670 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1671 mce_bootlog = (str[0] == 'b');
1672 else if (isdigit(str[0])) {
1673 get_option(&str, &tolerant);
1676 get_option(&str, &monarch_timeout);
1679 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1685 __setup("mce", mcheck_enable);
1687 int __init mcheck_init(void)
1689 mcheck_intel_therm_init();
1695 * mce_syscore: PM support
1699 * Disable machine checks on suspend and shutdown. We can't really handle
1702 static int mce_disable_error_reporting(void)
1706 for (i = 0; i < banks; i++) {
1707 struct mce_bank *b = &mce_banks[i];
1710 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1715 static int mce_syscore_suspend(void)
1717 return mce_disable_error_reporting();
1720 static void mce_syscore_shutdown(void)
1722 mce_disable_error_reporting();
1726 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1727 * Only one CPU is active at this time, the others get re-added later using
1730 static void mce_syscore_resume(void)
1732 __mcheck_cpu_init_generic();
1733 __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info));
1736 static struct syscore_ops mce_syscore_ops = {
1737 .suspend = mce_syscore_suspend,
1738 .shutdown = mce_syscore_shutdown,
1739 .resume = mce_syscore_resume,
1743 * mce_sysdev: Sysfs support
1746 static void mce_cpu_restart(void *data)
1748 del_timer_sync(&__get_cpu_var(mce_timer));
1749 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1751 __mcheck_cpu_init_generic();
1752 __mcheck_cpu_init_timer();
1755 /* Reinit MCEs after user configuration changes */
1756 static void mce_restart(void)
1758 on_each_cpu(mce_cpu_restart, NULL, 1);
1761 /* Toggle features for corrected errors */
1762 static void mce_disable_ce(void *all)
1764 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1767 del_timer_sync(&__get_cpu_var(mce_timer));
1771 static void mce_enable_ce(void *all)
1773 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1778 __mcheck_cpu_init_timer();
1781 static struct sysdev_class mce_sysdev_class = {
1782 .name = "machinecheck",
1785 DEFINE_PER_CPU(struct sys_device, mce_sysdev);
1788 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1790 static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1792 return container_of(attr, struct mce_bank, attr);
1795 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1798 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1801 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1802 const char *buf, size_t size)
1806 if (strict_strtoull(buf, 0, &new) < 0)
1809 attr_to_bank(attr)->ctl = new;
1816 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1818 strcpy(buf, mce_helper);
1820 return strlen(mce_helper) + 1;
1823 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1824 const char *buf, size_t siz)
1828 strncpy(mce_helper, buf, sizeof(mce_helper));
1829 mce_helper[sizeof(mce_helper)-1] = 0;
1830 p = strchr(mce_helper, '\n');
1835 return strlen(mce_helper) + !!p;
1838 static ssize_t set_ignore_ce(struct sys_device *s,
1839 struct sysdev_attribute *attr,
1840 const char *buf, size_t size)
1844 if (strict_strtoull(buf, 0, &new) < 0)
1847 if (mce_ignore_ce ^ !!new) {
1849 /* disable ce features */
1850 on_each_cpu(mce_disable_ce, (void *)1, 1);
1853 /* enable ce features */
1855 on_each_cpu(mce_enable_ce, (void *)1, 1);
1861 static ssize_t set_cmci_disabled(struct sys_device *s,
1862 struct sysdev_attribute *attr,
1863 const char *buf, size_t size)
1867 if (strict_strtoull(buf, 0, &new) < 0)
1870 if (mce_cmci_disabled ^ !!new) {
1873 on_each_cpu(mce_disable_ce, NULL, 1);
1874 mce_cmci_disabled = 1;
1877 mce_cmci_disabled = 0;
1878 on_each_cpu(mce_enable_ce, NULL, 1);
1884 static ssize_t store_int_with_restart(struct sys_device *s,
1885 struct sysdev_attribute *attr,
1886 const char *buf, size_t size)
1888 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1893 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1894 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1895 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1896 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1898 static struct sysdev_ext_attribute attr_check_interval = {
1899 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1900 store_int_with_restart),
1904 static struct sysdev_ext_attribute attr_ignore_ce = {
1905 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1909 static struct sysdev_ext_attribute attr_cmci_disabled = {
1910 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1914 static struct sysdev_attribute *mce_sysdev_attrs[] = {
1915 &attr_tolerant.attr,
1916 &attr_check_interval.attr,
1918 &attr_monarch_timeout.attr,
1919 &attr_dont_log_ce.attr,
1920 &attr_ignore_ce.attr,
1921 &attr_cmci_disabled.attr,
1925 static cpumask_var_t mce_sysdev_initialized;
1927 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1928 static __cpuinit int mce_sysdev_create(unsigned int cpu)
1930 struct sys_device *sysdev = &per_cpu(mce_sysdev, cpu);
1934 if (!mce_available(&boot_cpu_data))
1937 memset(&sysdev->kobj, 0, sizeof(struct kobject));
1939 sysdev->cls = &mce_sysdev_class;
1941 err = sysdev_register(sysdev);
1945 for (i = 0; mce_sysdev_attrs[i]; i++) {
1946 err = sysdev_create_file(sysdev, mce_sysdev_attrs[i]);
1950 for (j = 0; j < banks; j++) {
1951 err = sysdev_create_file(sysdev, &mce_banks[j].attr);
1955 cpumask_set_cpu(cpu, mce_sysdev_initialized);
1960 sysdev_remove_file(sysdev, &mce_banks[j].attr);
1963 sysdev_remove_file(sysdev, mce_sysdev_attrs[i]);
1965 sysdev_unregister(sysdev);
1970 static __cpuinit void mce_sysdev_remove(unsigned int cpu)
1972 struct sys_device *sysdev = &per_cpu(mce_sysdev, cpu);
1975 if (!cpumask_test_cpu(cpu, mce_sysdev_initialized))
1978 for (i = 0; mce_sysdev_attrs[i]; i++)
1979 sysdev_remove_file(sysdev, mce_sysdev_attrs[i]);
1981 for (i = 0; i < banks; i++)
1982 sysdev_remove_file(sysdev, &mce_banks[i].attr);
1984 sysdev_unregister(sysdev);
1985 cpumask_clear_cpu(cpu, mce_sysdev_initialized);
1988 /* Make sure there are no machine checks on offlined CPUs. */
1989 static void __cpuinit mce_disable_cpu(void *h)
1991 unsigned long action = *(unsigned long *)h;
1994 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1997 if (!(action & CPU_TASKS_FROZEN))
1999 for (i = 0; i < banks; i++) {
2000 struct mce_bank *b = &mce_banks[i];
2003 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2007 static void __cpuinit mce_reenable_cpu(void *h)
2009 unsigned long action = *(unsigned long *)h;
2012 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2015 if (!(action & CPU_TASKS_FROZEN))
2017 for (i = 0; i < banks; i++) {
2018 struct mce_bank *b = &mce_banks[i];
2021 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
2025 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2026 static int __cpuinit
2027 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2029 unsigned int cpu = (unsigned long)hcpu;
2030 struct timer_list *t = &per_cpu(mce_timer, cpu);
2034 case CPU_ONLINE_FROZEN:
2035 mce_sysdev_create(cpu);
2036 if (threshold_cpu_callback)
2037 threshold_cpu_callback(action, cpu);
2040 case CPU_DEAD_FROZEN:
2041 if (threshold_cpu_callback)
2042 threshold_cpu_callback(action, cpu);
2043 mce_sysdev_remove(cpu);
2045 case CPU_DOWN_PREPARE:
2046 case CPU_DOWN_PREPARE_FROZEN:
2048 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2050 case CPU_DOWN_FAILED:
2051 case CPU_DOWN_FAILED_FROZEN:
2052 if (!mce_ignore_ce && check_interval) {
2053 t->expires = round_jiffies(jiffies +
2054 __get_cpu_var(mce_next_interval));
2055 add_timer_on(t, cpu);
2057 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2060 /* intentionally ignoring frozen here */
2061 cmci_rediscover(cpu);
2067 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2068 .notifier_call = mce_cpu_callback,
2071 static __init void mce_init_banks(void)
2075 for (i = 0; i < banks; i++) {
2076 struct mce_bank *b = &mce_banks[i];
2077 struct sysdev_attribute *a = &b->attr;
2079 sysfs_attr_init(&a->attr);
2080 a->attr.name = b->attrname;
2081 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2083 a->attr.mode = 0644;
2084 a->show = show_bank;
2085 a->store = set_bank;
2089 static __init int mcheck_init_device(void)
2094 if (!mce_available(&boot_cpu_data))
2097 zalloc_cpumask_var(&mce_sysdev_initialized, GFP_KERNEL);
2101 err = sysdev_class_register(&mce_sysdev_class);
2105 for_each_online_cpu(i) {
2106 err = mce_sysdev_create(i);
2111 register_syscore_ops(&mce_syscore_ops);
2112 register_hotcpu_notifier(&mce_cpu_notifier);
2114 /* register character device /dev/mcelog */
2115 misc_register(&mce_chrdev_device);
2119 device_initcall(mcheck_init_device);
2122 * Old style boot options parsing. Only for compatibility.
2124 static int __init mcheck_disable(char *str)
2129 __setup("nomce", mcheck_disable);
2131 #ifdef CONFIG_DEBUG_FS
2132 struct dentry *mce_get_debugfs_dir(void)
2134 static struct dentry *dmce;
2137 dmce = debugfs_create_dir("mce", NULL);
2142 static void mce_reset(void)
2145 atomic_set(&mce_fake_paniced, 0);
2146 atomic_set(&mce_executing, 0);
2147 atomic_set(&mce_callin, 0);
2148 atomic_set(&global_nwo, 0);
2151 static int fake_panic_get(void *data, u64 *val)
2157 static int fake_panic_set(void *data, u64 val)
2164 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2165 fake_panic_set, "%llu\n");
2167 static int __init mcheck_debugfs_init(void)
2169 struct dentry *dmce, *ffake_panic;
2171 dmce = mce_get_debugfs_dir();
2174 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2181 late_initcall(mcheck_debugfs_init);