2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/ratelimit.h>
15 #include <linux/kallsyms.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/sysdev.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/init.h>
30 #include <linux/kmod.h>
31 #include <linux/poll.h>
32 #include <linux/nmi.h>
33 #include <linux/cpu.h>
34 #include <linux/smp.h>
38 #include <asm/processor.h>
39 #include <asm/hw_irq.h>
46 #include "mce-internal.h"
48 /* Handle unconfigured int18 (should never happen) */
49 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
51 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
55 /* Call the installed machine check handler for this CPU setup. */
56 void (*machine_check_vector)(struct pt_regs *, long error_code) =
57 unexpected_machine_check;
59 int mce_disabled __read_mostly;
61 #ifdef CONFIG_X86_NEW_MCE
63 #define MISC_MCELOG_MINOR 227
65 #define SPINUNIT 100 /* 100ns */
69 DEFINE_PER_CPU(unsigned, mce_exception_count);
73 * 0: always panic on uncorrected errors, log corrected errors
74 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
75 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
76 * 3: never panic or SIGBUS, log all errors (for testing only)
78 static int tolerant __read_mostly = 1;
79 static int banks __read_mostly;
80 static u64 *bank __read_mostly;
81 static int rip_msr __read_mostly;
82 static int mce_bootlog __read_mostly = -1;
83 static int monarch_timeout __read_mostly = -1;
84 static int mce_panic_timeout __read_mostly;
85 static int mce_dont_log_ce __read_mostly;
86 int mce_cmci_disabled __read_mostly;
87 int mce_ignore_ce __read_mostly;
88 int mce_ser __read_mostly;
90 /* User mode helper program triggered by machine check event */
91 static unsigned long mce_need_notify;
92 static char mce_helper[128];
93 static char *mce_helper_argv[2] = { mce_helper, NULL };
95 static unsigned long dont_init_banks;
97 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
98 static DEFINE_PER_CPU(struct mce, mces_seen);
99 static int cpu_missing;
102 /* MCA banks polled by the period polling timer for corrected events */
103 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
104 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
107 static inline int skip_bank_init(int i)
109 return i < BITS_PER_LONG && test_bit(i, &dont_init_banks);
112 static DEFINE_PER_CPU(struct work_struct, mce_work);
114 /* Do initial initialization of a struct mce */
115 void mce_setup(struct mce *m)
117 memset(m, 0, sizeof(struct mce));
118 m->cpu = m->extcpu = smp_processor_id();
120 /* We hope get_seconds stays lockless */
121 m->time = get_seconds();
122 m->cpuvendor = boot_cpu_data.x86_vendor;
123 m->cpuid = cpuid_eax(1);
125 m->socketid = cpu_data(m->extcpu).phys_proc_id;
127 m->apicid = cpu_data(m->extcpu).initial_apicid;
128 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
131 DEFINE_PER_CPU(struct mce, injectm);
132 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
135 * Lockless MCE logging infrastructure.
136 * This avoids deadlocks on printk locks without having to break locks. Also
137 * separate MCEs from kernel messages to avoid bogus bug reports.
140 static struct mce_log mcelog = {
141 .signature = MCE_LOG_SIGNATURE,
143 .recordlen = sizeof(struct mce),
146 void mce_log(struct mce *mce)
148 unsigned next, entry;
153 entry = rcu_dereference(mcelog.next);
156 * When the buffer fills up discard new entries.
157 * Assume that the earlier errors are the more
160 if (entry >= MCE_LOG_LEN) {
161 set_bit(MCE_OVERFLOW,
162 (unsigned long *)&mcelog.flags);
165 /* Old left over entry. Skip: */
166 if (mcelog.entry[entry].finished) {
174 if (cmpxchg(&mcelog.next, entry, next) == entry)
177 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
179 mcelog.entry[entry].finished = 1;
183 set_bit(0, &mce_need_notify);
186 void __weak decode_mce(struct mce *m)
191 static void print_mce(struct mce *m)
194 "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
195 m->extcpu, m->mcgstatus, m->bank, m->status);
197 printk(KERN_EMERG "RIP%s %02x:<%016Lx> ",
198 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
200 if (m->cs == __KERNEL_CS)
201 print_symbol("{%s}", m->ip);
202 printk(KERN_CONT "\n");
204 printk(KERN_EMERG "TSC %llx ", m->tsc);
206 printk(KERN_CONT "ADDR %llx ", m->addr);
208 printk(KERN_CONT "MISC %llx ", m->misc);
209 printk(KERN_CONT "\n");
210 printk(KERN_EMERG "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
211 m->cpuvendor, m->cpuid, m->time, m->socketid,
217 static void print_mce_head(void)
219 printk(KERN_EMERG "\nHARDWARE ERROR\n");
222 static void print_mce_tail(void)
224 printk(KERN_EMERG "This is not a software problem!\n"
225 "Run through mcelog --ascii to decode and contact your hardware vendor\n");
228 #define PANIC_TIMEOUT 5 /* 5 seconds */
230 static atomic_t mce_paniced;
232 /* Panic in progress. Enable interrupts and wait for final IPI */
233 static void wait_for_panic(void)
235 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
238 while (timeout-- > 0)
240 if (panic_timeout == 0)
241 panic_timeout = mce_panic_timeout;
242 panic("Panicing machine check CPU died");
245 static void mce_panic(char *msg, struct mce *final, char *exp)
250 * Make sure only one CPU runs in machine check panic
252 if (atomic_add_return(1, &mce_paniced) > 1)
259 /* First print corrected ones that are still unlogged */
260 for (i = 0; i < MCE_LOG_LEN; i++) {
261 struct mce *m = &mcelog.entry[i];
262 if (!(m->status & MCI_STATUS_VAL))
264 if (!(m->status & MCI_STATUS_UC))
267 /* Now print uncorrected but with the final one last */
268 for (i = 0; i < MCE_LOG_LEN; i++) {
269 struct mce *m = &mcelog.entry[i];
270 if (!(m->status & MCI_STATUS_VAL))
272 if (!(m->status & MCI_STATUS_UC))
274 if (!final || memcmp(m, final, sizeof(struct mce)))
280 printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n");
283 printk(KERN_EMERG "Machine check: %s\n", exp);
284 if (panic_timeout == 0)
285 panic_timeout = mce_panic_timeout;
289 /* Support code for software error injection */
291 static int msr_to_offset(u32 msr)
293 unsigned bank = __get_cpu_var(injectm.bank);
295 return offsetof(struct mce, ip);
296 if (msr == MSR_IA32_MC0_STATUS + bank*4)
297 return offsetof(struct mce, status);
298 if (msr == MSR_IA32_MC0_ADDR + bank*4)
299 return offsetof(struct mce, addr);
300 if (msr == MSR_IA32_MC0_MISC + bank*4)
301 return offsetof(struct mce, misc);
302 if (msr == MSR_IA32_MCG_STATUS)
303 return offsetof(struct mce, mcgstatus);
307 /* MSR access wrappers used for error injection */
308 static u64 mce_rdmsrl(u32 msr)
311 if (__get_cpu_var(injectm).finished) {
312 int offset = msr_to_offset(msr);
315 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
321 static void mce_wrmsrl(u32 msr, u64 v)
323 if (__get_cpu_var(injectm).finished) {
324 int offset = msr_to_offset(msr);
326 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
333 * Simple lockless ring to communicate PFNs from the exception handler with the
334 * process context work function. This is vastly simplified because there's
335 * only a single reader and a single writer.
337 #define MCE_RING_SIZE 16 /* we use one entry less */
340 unsigned short start;
342 unsigned long ring[MCE_RING_SIZE];
344 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
346 /* Runs with CPU affinity in workqueue */
347 static int mce_ring_empty(void)
349 struct mce_ring *r = &__get_cpu_var(mce_ring);
351 return r->start == r->end;
354 static int mce_ring_get(unsigned long *pfn)
361 r = &__get_cpu_var(mce_ring);
362 if (r->start == r->end)
364 *pfn = r->ring[r->start];
365 r->start = (r->start + 1) % MCE_RING_SIZE;
372 /* Always runs in MCE context with preempt off */
373 static int mce_ring_add(unsigned long pfn)
375 struct mce_ring *r = &__get_cpu_var(mce_ring);
378 next = (r->end + 1) % MCE_RING_SIZE;
379 if (next == r->start)
381 r->ring[r->end] = pfn;
387 int mce_available(struct cpuinfo_x86 *c)
391 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
394 static void mce_schedule_work(void)
396 if (!mce_ring_empty()) {
397 struct work_struct *work = &__get_cpu_var(mce_work);
398 if (!work_pending(work))
404 * Get the address of the instruction at the time of the machine check
407 static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
410 if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) {
418 m->ip = mce_rdmsrl(rip_msr);
421 #ifdef CONFIG_X86_LOCAL_APIC
423 * Called after interrupts have been reenabled again
424 * when a MCE happened during an interrupts off region
427 asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs)
438 static void mce_report_event(struct pt_regs *regs)
440 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
443 * Triggering the work queue here is just an insurance
444 * policy in case the syscall exit notify handler
445 * doesn't run soon enough or ends up running on the
446 * wrong CPU (can happen when audit sleeps)
452 #ifdef CONFIG_X86_LOCAL_APIC
454 * Without APIC do not notify. The event will be picked
461 * When interrupts are disabled we cannot use
462 * kernel services safely. Trigger an self interrupt
463 * through the APIC to instead do the notification
464 * after interrupts are reenabled again.
466 apic->send_IPI_self(MCE_SELF_VECTOR);
469 * Wait for idle afterwards again so that we don't leave the
470 * APIC in a non idle state because the normal APIC writes
473 apic_wait_icr_idle();
477 DEFINE_PER_CPU(unsigned, mce_poll_count);
480 * Poll for corrected events or events that happened before reset.
481 * Those are just logged through /dev/mcelog.
483 * This is executed in standard interrupt context.
485 * Note: spec recommends to panic for fatal unsignalled
486 * errors here. However this would be quite problematic --
487 * we would need to reimplement the Monarch handling and
488 * it would mess up the exclusion between exception handler
489 * and poll hander -- * so we skip this for now.
490 * These cases should not happen anyways, or only when the CPU
491 * is already totally * confused. In this case it's likely it will
492 * not fully execute the machine check handler either.
494 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
499 __get_cpu_var(mce_poll_count)++;
503 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
504 for (i = 0; i < banks; i++) {
505 if (!bank[i] || !test_bit(i, *b))
514 m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4);
515 if (!(m.status & MCI_STATUS_VAL))
519 * Uncorrected or signalled events are handled by the exception
520 * handler when it is enabled, so don't process those here.
522 * TBD do the same check for MCI_STATUS_EN here?
524 if (!(flags & MCP_UC) &&
525 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
528 if (m.status & MCI_STATUS_MISCV)
529 m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4);
530 if (m.status & MCI_STATUS_ADDRV)
531 m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4);
533 if (!(flags & MCP_TIMESTAMP))
536 * Don't get the IP here because it's unlikely to
537 * have anything to do with the actual error location.
539 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) {
541 add_taint(TAINT_MACHINE_CHECK);
545 * Clear state for this bank.
547 mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
551 * Don't clear MCG_STATUS here because it's only defined for
557 EXPORT_SYMBOL_GPL(machine_check_poll);
560 * Do a quick check if any of the events requires a panic.
561 * This decides if we keep the events around or clear them.
563 static int mce_no_way_out(struct mce *m, char **msg)
567 for (i = 0; i < banks; i++) {
568 m->status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4);
569 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
576 * Variable to establish order between CPUs while scanning.
577 * Each CPU spins initially until executing is equal its number.
579 static atomic_t mce_executing;
582 * Defines order of CPUs on entry. First CPU becomes Monarch.
584 static atomic_t mce_callin;
587 * Check if a timeout waiting for other CPUs happened.
589 static int mce_timed_out(u64 *t)
592 * The others already did panic for some reason.
593 * Bail out like in a timeout.
594 * rmb() to tell the compiler that system_state
595 * might have been modified by someone else.
598 if (atomic_read(&mce_paniced))
600 if (!monarch_timeout)
602 if ((s64)*t < SPINUNIT) {
603 /* CHECKME: Make panic default for 1 too? */
605 mce_panic("Timeout synchronizing machine check over CPUs",
612 touch_nmi_watchdog();
617 * The Monarch's reign. The Monarch is the CPU who entered
618 * the machine check handler first. It waits for the others to
619 * raise the exception too and then grades them. When any
620 * error is fatal panic. Only then let the others continue.
622 * The other CPUs entering the MCE handler will be controlled by the
623 * Monarch. They are called Subjects.
625 * This way we prevent any potential data corruption in a unrecoverable case
626 * and also makes sure always all CPU's errors are examined.
628 * Also this detects the case of an machine check event coming from outer
629 * space (not detected by any CPUs) In this case some external agent wants
630 * us to shut down, so panic too.
632 * The other CPUs might still decide to panic if the handler happens
633 * in a unrecoverable place, but in this case the system is in a semi-stable
634 * state and won't corrupt anything by itself. It's ok to let the others
635 * continue for a bit first.
637 * All the spin loops have timeouts; when a timeout happens a CPU
638 * typically elects itself to be Monarch.
640 static void mce_reign(void)
643 struct mce *m = NULL;
644 int global_worst = 0;
649 * This CPU is the Monarch and the other CPUs have run
650 * through their handlers.
651 * Grade the severity of the errors of all the CPUs.
653 for_each_possible_cpu(cpu) {
654 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
656 if (severity > global_worst) {
658 global_worst = severity;
659 m = &per_cpu(mces_seen, cpu);
664 * Cannot recover? Panic here then.
665 * This dumps all the mces in the log buffer and stops the
668 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
669 mce_panic("Fatal Machine check", m, msg);
672 * For UC somewhere we let the CPU who detects it handle it.
673 * Also must let continue the others, otherwise the handling
674 * CPU could deadlock on a lock.
678 * No machine check event found. Must be some external
679 * source or one CPU is hung. Panic.
681 if (!m && tolerant < 3)
682 mce_panic("Machine check from unknown source", NULL, NULL);
685 * Now clear all the mces_seen so that they don't reappear on
688 for_each_possible_cpu(cpu)
689 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
692 static atomic_t global_nwo;
695 * Start of Monarch synchronization. This waits until all CPUs have
696 * entered the exception handler and then determines if any of them
697 * saw a fatal event that requires panic. Then it executes them
698 * in the entry order.
699 * TBD double check parallel CPU hotunplug
701 static int mce_start(int *no_way_out)
704 int cpus = num_online_cpus();
705 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
710 atomic_add(*no_way_out, &global_nwo);
712 * global_nwo should be updated before mce_callin
715 order = atomic_add_return(1, &mce_callin);
720 while (atomic_read(&mce_callin) != cpus) {
721 if (mce_timed_out(&timeout)) {
722 atomic_set(&global_nwo, 0);
729 * mce_callin should be read before global_nwo
735 * Monarch: Starts executing now, the others wait.
737 atomic_set(&mce_executing, 1);
740 * Subject: Now start the scanning loop one by one in
741 * the original callin order.
742 * This way when there are any shared banks it will be
743 * only seen by one CPU before cleared, avoiding duplicates.
745 while (atomic_read(&mce_executing) < order) {
746 if (mce_timed_out(&timeout)) {
747 atomic_set(&global_nwo, 0);
755 * Cache the global no_way_out state.
757 *no_way_out = atomic_read(&global_nwo);
763 * Synchronize between CPUs after main scanning loop.
764 * This invokes the bulk of the Monarch processing.
766 static int mce_end(int order)
769 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
777 * Allow others to run.
779 atomic_inc(&mce_executing);
782 /* CHECKME: Can this race with a parallel hotplug? */
783 int cpus = num_online_cpus();
786 * Monarch: Wait for everyone to go through their scanning
789 while (atomic_read(&mce_executing) <= cpus) {
790 if (mce_timed_out(&timeout))
800 * Subject: Wait for Monarch to finish.
802 while (atomic_read(&mce_executing) != 0) {
803 if (mce_timed_out(&timeout))
809 * Don't reset anything. That's done by the Monarch.
815 * Reset all global state.
818 atomic_set(&global_nwo, 0);
819 atomic_set(&mce_callin, 0);
823 * Let others run again.
825 atomic_set(&mce_executing, 0);
830 * Check if the address reported by the CPU is in a format we can parse.
831 * It would be possible to add code for most other cases, but all would
832 * be somewhat complicated (e.g. segment offset would require an instruction
833 * parser). So only support physical addresses upto page granuality for now.
835 static int mce_usable_address(struct mce *m)
837 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
839 if ((m->misc & 0x3f) > PAGE_SHIFT)
841 if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS)
846 static void mce_clear_state(unsigned long *toclear)
850 for (i = 0; i < banks; i++) {
851 if (test_bit(i, toclear))
852 mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
857 * The actual machine check handler. This only handles real
858 * exceptions when something got corrupted coming in through int 18.
860 * This is executed in NMI context not subject to normal locking rules. This
861 * implies that most kernel services cannot be safely used. Don't even
862 * think about putting a printk in there!
864 * On Intel systems this is entered on all CPUs in parallel through
865 * MCE broadcast. However some CPUs might be broken beyond repair,
866 * so be always careful when synchronizing with others.
868 void do_machine_check(struct pt_regs *regs, long error_code)
870 struct mce m, *final;
875 * Establish sequential order between the CPUs entering the machine
880 * If no_way_out gets set, there is no safe way to recover from this
881 * MCE. If tolerant is cranked up, we'll try anyway.
885 * If kill_it gets set, there might be a way to recover from this
889 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
890 char *msg = "Unknown";
892 atomic_inc(&mce_entry);
894 __get_cpu_var(mce_exception_count)++;
896 if (notify_die(DIE_NMI, "machine check", regs, error_code,
897 18, SIGKILL) == NOTIFY_STOP)
904 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
905 no_way_out = mce_no_way_out(&m, &msg);
907 final = &__get_cpu_var(mces_seen);
913 * When no restart IP must always kill or panic.
915 if (!(m.mcgstatus & MCG_STATUS_RIPV))
919 * Go through all the banks in exclusion of the other CPUs.
920 * This way we don't report duplicated events on shared banks
921 * because the first one to see it will clear it.
923 order = mce_start(&no_way_out);
924 for (i = 0; i < banks; i++) {
925 __clear_bit(i, toclear);
933 m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4);
934 if ((m.status & MCI_STATUS_VAL) == 0)
938 * Non uncorrected or non signaled errors are handled by
939 * machine_check_poll. Leave them alone, unless this panics.
941 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
946 * Set taint even when machine check was not enabled.
948 add_taint(TAINT_MACHINE_CHECK);
950 severity = mce_severity(&m, tolerant, NULL);
953 * When machine check was for corrected handler don't touch,
954 * unless we're panicing.
956 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
958 __set_bit(i, toclear);
959 if (severity == MCE_NO_SEVERITY) {
961 * Machine check event was not enabled. Clear, but
968 * Kill on action required.
970 if (severity == MCE_AR_SEVERITY)
973 if (m.status & MCI_STATUS_MISCV)
974 m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4);
975 if (m.status & MCI_STATUS_ADDRV)
976 m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4);
979 * Action optional error. Queue address for later processing.
980 * When the ring overflows we just ignore the AO error.
981 * RED-PEN add some logging mechanism when
982 * usable_address or mce_add_ring fails.
983 * RED-PEN don't ignore overflow for tolerant == 0
985 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
986 mce_ring_add(m.addr >> PAGE_SHIFT);
988 mce_get_rip(&m, regs);
991 if (severity > worst) {
998 mce_clear_state(toclear);
1001 * Do most of the synchronization with other CPUs.
1002 * When there's any problem use only local no_way_out state.
1004 if (mce_end(order) < 0)
1005 no_way_out = worst >= MCE_PANIC_SEVERITY;
1008 * If we have decided that we just CAN'T continue, and the user
1009 * has not set tolerant to an insane level, give up and die.
1011 * This is mainly used in the case when the system doesn't
1012 * support MCE broadcasting or it has been disabled.
1014 if (no_way_out && tolerant < 3)
1015 mce_panic("Fatal machine check on current CPU", final, msg);
1018 * If the error seems to be unrecoverable, something should be
1019 * done. Try to kill as little as possible. If we can kill just
1020 * one task, do that. If the user has set the tolerance very
1021 * high, don't try to do anything at all.
1024 if (kill_it && tolerant < 3)
1025 force_sig(SIGBUS, current);
1027 /* notify userspace ASAP */
1028 set_thread_flag(TIF_MCE_NOTIFY);
1031 mce_report_event(regs);
1032 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1034 atomic_dec(&mce_entry);
1037 EXPORT_SYMBOL_GPL(do_machine_check);
1039 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1040 void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1042 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1046 * Called after mce notification in process context. This code
1047 * is allowed to sleep. Call the high level VM handler to process
1048 * any corrupted pages.
1049 * Assume that the work queue code only calls this one at a time
1051 * Note we don't disable preemption, so this code might run on the wrong
1052 * CPU. In this case the event is picked up by the scheduled work queue.
1053 * This is merely a fast path to expedite processing in some common
1056 void mce_notify_process(void)
1060 while (mce_ring_get(&pfn))
1061 memory_failure(pfn, MCE_VECTOR);
1064 static void mce_process_work(struct work_struct *dummy)
1066 mce_notify_process();
1069 #ifdef CONFIG_X86_MCE_INTEL
1071 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1072 * @cpu: The CPU on which the event occurred.
1073 * @status: Event status information
1075 * This function should be called by the thermal interrupt after the
1076 * event has been processed and the decision was made to log the event
1079 * The status parameter will be saved to the 'status' field of 'struct mce'
1080 * and historically has been the register value of the
1081 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1083 void mce_log_therm_throt_event(__u64 status)
1088 m.bank = MCE_THERMAL_BANK;
1092 #endif /* CONFIG_X86_MCE_INTEL */
1095 * Periodic polling timer for "silent" machine check errors. If the
1096 * poller finds an MCE, poll 2x faster. When the poller finds no more
1097 * errors, poll 2x slower (up to check_interval seconds).
1099 static int check_interval = 5 * 60; /* 5 minutes */
1101 static DEFINE_PER_CPU(int, next_interval); /* in jiffies */
1102 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1104 static void mcheck_timer(unsigned long data)
1106 struct timer_list *t = &per_cpu(mce_timer, data);
1109 WARN_ON(smp_processor_id() != data);
1111 if (mce_available(¤t_cpu_data)) {
1112 machine_check_poll(MCP_TIMESTAMP,
1113 &__get_cpu_var(mce_poll_banks));
1117 * Alert userspace if needed. If we logged an MCE, reduce the
1118 * polling interval, otherwise increase the polling interval.
1120 n = &__get_cpu_var(next_interval);
1121 if (mce_notify_irq())
1122 *n = max(*n/2, HZ/100);
1124 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1126 t->expires = jiffies + *n;
1127 add_timer_on(t, smp_processor_id());
1130 static void mce_do_trigger(struct work_struct *work)
1132 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1135 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1138 * Notify the user(s) about new machine check events.
1139 * Can be called from interrupt context, but not from machine check/NMI
1142 int mce_notify_irq(void)
1144 /* Not more than two messages every minute */
1145 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1147 clear_thread_flag(TIF_MCE_NOTIFY);
1149 if (test_and_clear_bit(0, &mce_need_notify)) {
1150 wake_up_interruptible(&mce_wait);
1153 * There is no risk of missing notifications because
1154 * work_pending is always cleared before the function is
1157 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1158 schedule_work(&mce_trigger_work);
1160 if (__ratelimit(&ratelimit))
1161 printk(KERN_INFO "Machine check events logged\n");
1167 EXPORT_SYMBOL_GPL(mce_notify_irq);
1170 * Initialize Machine Checks for a CPU.
1172 static int mce_cap_init(void)
1177 rdmsrl(MSR_IA32_MCG_CAP, cap);
1179 b = cap & MCG_BANKCNT_MASK;
1180 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1182 if (b > MAX_NR_BANKS) {
1184 "MCE: Using only %u machine check banks out of %u\n",
1189 /* Don't support asymmetric configurations today */
1190 WARN_ON(banks != 0 && b != banks);
1193 bank = kmalloc(banks * sizeof(u64), GFP_KERNEL);
1196 memset(bank, 0xff, banks * sizeof(u64));
1199 /* Use accurate RIP reporting if available. */
1200 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1201 rip_msr = MSR_IA32_MCG_EIP;
1203 if (cap & MCG_SER_P)
1209 static void mce_init(void)
1211 mce_banks_t all_banks;
1216 * Log the machine checks left over from the previous reset.
1218 bitmap_fill(all_banks, MAX_NR_BANKS);
1219 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1221 set_in_cr4(X86_CR4_MCE);
1223 rdmsrl(MSR_IA32_MCG_CAP, cap);
1224 if (cap & MCG_CTL_P)
1225 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1227 for (i = 0; i < banks; i++) {
1228 if (skip_bank_init(i))
1230 wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]);
1231 wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
1235 /* Add per CPU specific workarounds here */
1236 static int mce_cpu_quirks(struct cpuinfo_x86 *c)
1238 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1239 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1243 /* This should be disabled by the BIOS, but isn't always */
1244 if (c->x86_vendor == X86_VENDOR_AMD) {
1245 if (c->x86 == 15 && banks > 4) {
1247 * disable GART TBL walk error reporting, which
1248 * trips off incorrectly with the IOMMU & 3ware
1251 clear_bit(10, (unsigned long *)&bank[4]);
1253 if (c->x86 <= 17 && mce_bootlog < 0) {
1255 * Lots of broken BIOS around that don't clear them
1256 * by default and leave crap in there. Don't log:
1261 * Various K7s with broken bank 0 around. Always disable
1264 if (c->x86 == 6 && banks > 0)
1268 if (c->x86_vendor == X86_VENDOR_INTEL) {
1270 * SDM documents that on family 6 bank 0 should not be written
1271 * because it aliases to another special BIOS controlled
1273 * But it's not aliased anymore on model 0x1a+
1274 * Don't ignore bank 0 completely because there could be a
1275 * valid event later, merely don't write CTL0.
1278 if (c->x86 == 6 && c->x86_model < 0x1A)
1279 __set_bit(0, &dont_init_banks);
1282 * All newer Intel systems support MCE broadcasting. Enable
1283 * synchronization with a one second timeout.
1285 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1286 monarch_timeout < 0)
1287 monarch_timeout = USEC_PER_SEC;
1290 * There are also broken BIOSes on some Pentium M and
1293 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1296 if (monarch_timeout < 0)
1297 monarch_timeout = 0;
1298 if (mce_bootlog != 0)
1299 mce_panic_timeout = 30;
1304 static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c)
1308 switch (c->x86_vendor) {
1309 case X86_VENDOR_INTEL:
1310 intel_p5_mcheck_init(c);
1312 case X86_VENDOR_CENTAUR:
1313 winchip_mcheck_init(c);
1318 static void mce_cpu_features(struct cpuinfo_x86 *c)
1320 switch (c->x86_vendor) {
1321 case X86_VENDOR_INTEL:
1322 mce_intel_feature_init(c);
1324 case X86_VENDOR_AMD:
1325 mce_amd_feature_init(c);
1332 static void mce_init_timer(void)
1334 struct timer_list *t = &__get_cpu_var(mce_timer);
1335 int *n = &__get_cpu_var(next_interval);
1340 *n = check_interval * HZ;
1343 setup_timer(t, mcheck_timer, smp_processor_id());
1344 t->expires = round_jiffies(jiffies + *n);
1345 add_timer_on(t, smp_processor_id());
1349 * Called for each booted CPU to set up machine checks.
1350 * Must be called with preempt off:
1352 void __cpuinit mcheck_init(struct cpuinfo_x86 *c)
1357 mce_ancient_init(c);
1359 if (!mce_available(c))
1362 if (mce_cap_init() < 0 || mce_cpu_quirks(c) < 0) {
1367 machine_check_vector = do_machine_check;
1370 mce_cpu_features(c);
1372 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1376 * Character device to read and clear the MCE log.
1379 static DEFINE_SPINLOCK(mce_state_lock);
1380 static int open_count; /* #times opened */
1381 static int open_exclu; /* already open exclusive? */
1383 static int mce_open(struct inode *inode, struct file *file)
1385 spin_lock(&mce_state_lock);
1387 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
1388 spin_unlock(&mce_state_lock);
1393 if (file->f_flags & O_EXCL)
1397 spin_unlock(&mce_state_lock);
1399 return nonseekable_open(inode, file);
1402 static int mce_release(struct inode *inode, struct file *file)
1404 spin_lock(&mce_state_lock);
1409 spin_unlock(&mce_state_lock);
1414 static void collect_tscs(void *data)
1416 unsigned long *cpu_tsc = (unsigned long *)data;
1418 rdtscll(cpu_tsc[smp_processor_id()]);
1421 static DEFINE_MUTEX(mce_read_mutex);
1423 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
1426 char __user *buf = ubuf;
1427 unsigned long *cpu_tsc;
1428 unsigned prev, next;
1431 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1435 mutex_lock(&mce_read_mutex);
1436 next = rcu_dereference(mcelog.next);
1438 /* Only supports full reads right now */
1439 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) {
1440 mutex_unlock(&mce_read_mutex);
1449 for (i = prev; i < next; i++) {
1450 unsigned long start = jiffies;
1452 while (!mcelog.entry[i].finished) {
1453 if (time_after_eq(jiffies, start + 2)) {
1454 memset(mcelog.entry + i, 0,
1455 sizeof(struct mce));
1461 err |= copy_to_user(buf, mcelog.entry + i,
1462 sizeof(struct mce));
1463 buf += sizeof(struct mce);
1468 memset(mcelog.entry + prev, 0,
1469 (next - prev) * sizeof(struct mce));
1471 next = cmpxchg(&mcelog.next, prev, 0);
1472 } while (next != prev);
1474 synchronize_sched();
1477 * Collect entries that were still getting written before the
1480 on_each_cpu(collect_tscs, cpu_tsc, 1);
1482 for (i = next; i < MCE_LOG_LEN; i++) {
1483 if (mcelog.entry[i].finished &&
1484 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
1485 err |= copy_to_user(buf, mcelog.entry+i,
1486 sizeof(struct mce));
1488 buf += sizeof(struct mce);
1489 memset(&mcelog.entry[i], 0, sizeof(struct mce));
1492 mutex_unlock(&mce_read_mutex);
1495 return err ? -EFAULT : buf - ubuf;
1498 static unsigned int mce_poll(struct file *file, poll_table *wait)
1500 poll_wait(file, &mce_wait, wait);
1501 if (rcu_dereference(mcelog.next))
1502 return POLLIN | POLLRDNORM;
1506 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
1508 int __user *p = (int __user *)arg;
1510 if (!capable(CAP_SYS_ADMIN))
1514 case MCE_GET_RECORD_LEN:
1515 return put_user(sizeof(struct mce), p);
1516 case MCE_GET_LOG_LEN:
1517 return put_user(MCE_LOG_LEN, p);
1518 case MCE_GETCLEAR_FLAGS: {
1522 flags = mcelog.flags;
1523 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1525 return put_user(flags, p);
1532 /* Modified in mce-inject.c, so not static or const */
1533 struct file_operations mce_chrdev_ops = {
1535 .release = mce_release,
1538 .unlocked_ioctl = mce_ioctl,
1540 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
1542 static struct miscdevice mce_log_device = {
1549 * mce=off Disables machine check
1550 * mce=no_cmci Disables CMCI
1551 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1552 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1553 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1554 * monarchtimeout is how long to wait for other CPUs on machine
1555 * check, or 0 to not wait
1556 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1557 * mce=nobootlog Don't log MCEs from before booting.
1559 static int __init mcheck_enable(char *str)
1565 if (!strcmp(str, "off"))
1567 else if (!strcmp(str, "no_cmci"))
1568 mce_cmci_disabled = 1;
1569 else if (!strcmp(str, "dont_log_ce"))
1570 mce_dont_log_ce = 1;
1571 else if (!strcmp(str, "ignore_ce"))
1573 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1574 mce_bootlog = (str[0] == 'b');
1575 else if (isdigit(str[0])) {
1576 get_option(&str, &tolerant);
1579 get_option(&str, &monarch_timeout);
1582 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1588 __setup("mce", mcheck_enable);
1595 * Disable machine checks on suspend and shutdown. We can't really handle
1598 static int mce_disable(void)
1602 for (i = 0; i < banks; i++) {
1603 if (!skip_bank_init(i))
1604 wrmsrl(MSR_IA32_MC0_CTL + i*4, 0);
1609 static int mce_suspend(struct sys_device *dev, pm_message_t state)
1611 return mce_disable();
1614 static int mce_shutdown(struct sys_device *dev)
1616 return mce_disable();
1620 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1621 * Only one CPU is active at this time, the others get re-added later using
1624 static int mce_resume(struct sys_device *dev)
1627 mce_cpu_features(¤t_cpu_data);
1632 static void mce_cpu_restart(void *data)
1634 del_timer_sync(&__get_cpu_var(mce_timer));
1635 if (!mce_available(¤t_cpu_data))
1641 /* Reinit MCEs after user configuration changes */
1642 static void mce_restart(void)
1644 on_each_cpu(mce_cpu_restart, NULL, 1);
1647 /* Toggle features for corrected errors */
1648 static void mce_disable_ce(void *all)
1650 if (!mce_available(¤t_cpu_data))
1653 del_timer_sync(&__get_cpu_var(mce_timer));
1657 static void mce_enable_ce(void *all)
1659 if (!mce_available(¤t_cpu_data))
1667 static struct sysdev_class mce_sysclass = {
1668 .suspend = mce_suspend,
1669 .shutdown = mce_shutdown,
1670 .resume = mce_resume,
1671 .name = "machinecheck",
1674 DEFINE_PER_CPU(struct sys_device, mce_dev);
1677 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1679 static struct sysdev_attribute *bank_attrs;
1681 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1684 u64 b = bank[attr - bank_attrs];
1686 return sprintf(buf, "%llx\n", b);
1689 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1690 const char *buf, size_t size)
1694 if (strict_strtoull(buf, 0, &new) < 0)
1697 bank[attr - bank_attrs] = new;
1704 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1706 strcpy(buf, mce_helper);
1708 return strlen(mce_helper) + 1;
1711 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1712 const char *buf, size_t siz)
1716 strncpy(mce_helper, buf, sizeof(mce_helper));
1717 mce_helper[sizeof(mce_helper)-1] = 0;
1718 p = strchr(mce_helper, '\n');
1723 return strlen(mce_helper) + !!p;
1726 static ssize_t set_ignore_ce(struct sys_device *s,
1727 struct sysdev_attribute *attr,
1728 const char *buf, size_t size)
1732 if (strict_strtoull(buf, 0, &new) < 0)
1735 if (mce_ignore_ce ^ !!new) {
1737 /* disable ce features */
1738 on_each_cpu(mce_disable_ce, (void *)1, 1);
1741 /* enable ce features */
1743 on_each_cpu(mce_enable_ce, (void *)1, 1);
1749 static ssize_t set_cmci_disabled(struct sys_device *s,
1750 struct sysdev_attribute *attr,
1751 const char *buf, size_t size)
1755 if (strict_strtoull(buf, 0, &new) < 0)
1758 if (mce_cmci_disabled ^ !!new) {
1761 on_each_cpu(mce_disable_ce, NULL, 1);
1762 mce_cmci_disabled = 1;
1765 mce_cmci_disabled = 0;
1766 on_each_cpu(mce_enable_ce, NULL, 1);
1772 static ssize_t store_int_with_restart(struct sys_device *s,
1773 struct sysdev_attribute *attr,
1774 const char *buf, size_t size)
1776 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1781 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1782 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1783 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1784 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1786 static struct sysdev_ext_attribute attr_check_interval = {
1787 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1788 store_int_with_restart),
1792 static struct sysdev_ext_attribute attr_ignore_ce = {
1793 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1797 static struct sysdev_ext_attribute attr_cmci_disabled = {
1798 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1802 static struct sysdev_attribute *mce_attrs[] = {
1803 &attr_tolerant.attr,
1804 &attr_check_interval.attr,
1806 &attr_monarch_timeout.attr,
1807 &attr_dont_log_ce.attr,
1808 &attr_ignore_ce.attr,
1809 &attr_cmci_disabled.attr,
1813 static cpumask_var_t mce_dev_initialized;
1815 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1816 static __cpuinit int mce_create_device(unsigned int cpu)
1821 if (!mce_available(&boot_cpu_data))
1824 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1825 per_cpu(mce_dev, cpu).id = cpu;
1826 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
1828 err = sysdev_register(&per_cpu(mce_dev, cpu));
1832 for (i = 0; mce_attrs[i]; i++) {
1833 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1837 for (j = 0; j < banks; j++) {
1838 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
1843 cpumask_set_cpu(cpu, mce_dev_initialized);
1848 sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[j]);
1851 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1853 sysdev_unregister(&per_cpu(mce_dev, cpu));
1858 static __cpuinit void mce_remove_device(unsigned int cpu)
1862 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
1865 for (i = 0; mce_attrs[i]; i++)
1866 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1868 for (i = 0; i < banks; i++)
1869 sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]);
1871 sysdev_unregister(&per_cpu(mce_dev, cpu));
1872 cpumask_clear_cpu(cpu, mce_dev_initialized);
1875 /* Make sure there are no machine checks on offlined CPUs. */
1876 static void mce_disable_cpu(void *h)
1878 unsigned long action = *(unsigned long *)h;
1881 if (!mce_available(¤t_cpu_data))
1883 if (!(action & CPU_TASKS_FROZEN))
1885 for (i = 0; i < banks; i++) {
1886 if (!skip_bank_init(i))
1887 wrmsrl(MSR_IA32_MC0_CTL + i*4, 0);
1891 static void mce_reenable_cpu(void *h)
1893 unsigned long action = *(unsigned long *)h;
1896 if (!mce_available(¤t_cpu_data))
1899 if (!(action & CPU_TASKS_FROZEN))
1901 for (i = 0; i < banks; i++) {
1902 if (!skip_bank_init(i))
1903 wrmsrl(MSR_IA32_MC0_CTL + i*4, bank[i]);
1907 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
1908 static int __cpuinit
1909 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
1911 unsigned int cpu = (unsigned long)hcpu;
1912 struct timer_list *t = &per_cpu(mce_timer, cpu);
1916 case CPU_ONLINE_FROZEN:
1917 mce_create_device(cpu);
1918 if (threshold_cpu_callback)
1919 threshold_cpu_callback(action, cpu);
1922 case CPU_DEAD_FROZEN:
1923 if (threshold_cpu_callback)
1924 threshold_cpu_callback(action, cpu);
1925 mce_remove_device(cpu);
1927 case CPU_DOWN_PREPARE:
1928 case CPU_DOWN_PREPARE_FROZEN:
1930 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
1932 case CPU_DOWN_FAILED:
1933 case CPU_DOWN_FAILED_FROZEN:
1934 t->expires = round_jiffies(jiffies +
1935 __get_cpu_var(next_interval));
1936 add_timer_on(t, cpu);
1937 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
1940 /* intentionally ignoring frozen here */
1941 cmci_rediscover(cpu);
1947 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
1948 .notifier_call = mce_cpu_callback,
1951 static __init int mce_init_banks(void)
1955 bank_attrs = kzalloc(sizeof(struct sysdev_attribute) * banks,
1960 for (i = 0; i < banks; i++) {
1961 struct sysdev_attribute *a = &bank_attrs[i];
1963 a->attr.name = kasprintf(GFP_KERNEL, "bank%d", i);
1967 a->attr.mode = 0644;
1968 a->show = show_bank;
1969 a->store = set_bank;
1975 kfree(bank_attrs[i].attr.name);
1982 static __init int mce_init_device(void)
1987 if (!mce_available(&boot_cpu_data))
1990 zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
1992 err = mce_init_banks();
1996 err = sysdev_class_register(&mce_sysclass);
2000 for_each_online_cpu(i) {
2001 err = mce_create_device(i);
2006 register_hotcpu_notifier(&mce_cpu_notifier);
2007 misc_register(&mce_log_device);
2012 device_initcall(mce_init_device);
2014 #else /* CONFIG_X86_OLD_MCE: */
2017 EXPORT_SYMBOL_GPL(nr_mce_banks); /* non-fatal.o */
2019 /* This has to be run for each processor */
2020 void mcheck_init(struct cpuinfo_x86 *c)
2025 switch (c->x86_vendor) {
2026 case X86_VENDOR_AMD:
2030 case X86_VENDOR_INTEL:
2032 intel_p5_mcheck_init(c);
2034 intel_p6_mcheck_init(c);
2036 intel_p4_mcheck_init(c);
2039 case X86_VENDOR_CENTAUR:
2041 winchip_mcheck_init(c);
2047 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", nr_mce_banks);
2050 static int __init mcheck_enable(char *str)
2055 __setup("mce", mcheck_enable);
2057 #endif /* CONFIG_X86_OLD_MCE */
2060 * Old style boot options parsing. Only for compatibility.
2062 static int __init mcheck_disable(char *str)
2067 __setup("nomce", mcheck_disable);