2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/ratelimit.h>
14 #include <linux/kallsyms.h>
15 #include <linux/rcupdate.h>
16 #include <linux/smp_lock.h>
17 #include <linux/kobject.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/sysdev.h>
23 #include <linux/ctype.h>
24 #include <linux/sched.h>
25 #include <linux/sysfs.h>
26 #include <linux/types.h>
27 #include <linux/init.h>
28 #include <linux/kmod.h>
29 #include <linux/poll.h>
30 #include <linux/cpu.h>
33 #include <asm/processor.h>
34 #include <asm/uaccess.h>
42 /* Handle unconfigured int18 (should never happen) */
43 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
45 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
49 /* Call the installed machine check handler for this CPU setup. */
50 void (*machine_check_vector)(struct pt_regs *, long error_code) =
51 unexpected_machine_check;
55 #ifdef CONFIG_X86_NEW_MCE
57 #define MISC_MCELOG_MINOR 227
63 * 0: always panic on uncorrected errors, log corrected errors
64 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
65 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
66 * 3: never panic or SIGBUS, log all errors (for testing only)
68 static int tolerant = 1;
71 static unsigned long notify_user;
73 static int mce_bootlog = -1;
74 static atomic_t mce_events;
76 static char trigger[128];
77 static char *trigger_argv[2] = { trigger, NULL };
79 static unsigned long dont_init_banks;
81 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
83 /* MCA banks polled by the period polling timer for corrected events */
84 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
85 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
88 static inline int skip_bank_init(int i)
90 return i < BITS_PER_LONG && test_bit(i, &dont_init_banks);
93 /* Do initial initialization of a struct mce */
94 void mce_setup(struct mce *m)
96 memset(m, 0, sizeof(struct mce));
97 m->cpu = smp_processor_id();
102 * Lockless MCE logging infrastructure.
103 * This avoids deadlocks on printk locks without having to break locks. Also
104 * separate MCEs from kernel messages to avoid bogus bug reports.
107 static struct mce_log mcelog = {
112 void mce_log(struct mce *mce)
114 unsigned next, entry;
116 atomic_inc(&mce_events);
120 entry = rcu_dereference(mcelog.next);
123 * When the buffer fills up discard new entries.
124 * Assume that the earlier errors are the more
127 if (entry >= MCE_LOG_LEN) {
128 set_bit(MCE_OVERFLOW, (unsigned long *)&mcelog.flags);
131 /* Old left over entry. Skip: */
132 if (mcelog.entry[entry].finished) {
140 if (cmpxchg(&mcelog.next, entry, next) == entry)
143 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
145 mcelog.entry[entry].finished = 1;
148 set_bit(0, ¬ify_user);
151 static void print_mce(struct mce *m)
153 printk(KERN_EMERG "\n"
154 KERN_EMERG "HARDWARE ERROR\n"
156 "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
157 m->cpu, m->mcgstatus, m->bank, m->status);
159 printk(KERN_EMERG "RIP%s %02x:<%016Lx> ",
160 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
162 if (m->cs == __KERNEL_CS)
163 print_symbol("{%s}", m->ip);
166 printk(KERN_EMERG "TSC %llx ", m->tsc);
168 printk("ADDR %llx ", m->addr);
170 printk("MISC %llx ", m->misc);
172 printk(KERN_EMERG "This is not a software problem!\n");
173 printk(KERN_EMERG "Run through mcelog --ascii to decode "
174 "and contact your hardware vendor\n");
177 static void mce_panic(char *msg, struct mce *backup, u64 start)
183 for (i = 0; i < MCE_LOG_LEN; i++) {
184 u64 tsc = mcelog.entry[i].tsc;
186 if ((s64)(tsc - start) < 0)
188 print_mce(&mcelog.entry[i]);
189 if (backup && mcelog.entry[i].tsc == backup->tsc)
197 int mce_available(struct cpuinfo_x86 *c)
201 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
204 static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
206 if (regs && (m->mcgstatus & MCG_STATUS_RIPV)) {
214 /* Assume the RIP in the MSR is exact. Is this true? */
215 m->mcgstatus |= MCG_STATUS_EIPV;
216 rdmsrl(rip_msr, m->ip);
222 * Poll for corrected events or events that happened before reset.
223 * Those are just logged through /dev/mcelog.
225 * This is executed in standard interrupt context.
227 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
234 rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus);
235 for (i = 0; i < banks; i++) {
236 if (!bank[i] || !test_bit(i, *b))
245 rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status);
246 if (!(m.status & MCI_STATUS_VAL))
250 * Uncorrected events are handled by the exception handler
251 * when it is enabled. But when the exception is disabled log
254 * TBD do the same check for MCI_STATUS_EN here?
256 if ((m.status & MCI_STATUS_UC) && !(flags & MCP_UC))
259 if (m.status & MCI_STATUS_MISCV)
260 rdmsrl(MSR_IA32_MC0_MISC + i*4, m.misc);
261 if (m.status & MCI_STATUS_ADDRV)
262 rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr);
264 if (!(flags & MCP_TIMESTAMP))
267 * Don't get the IP here because it's unlikely to
268 * have anything to do with the actual error location.
270 if (!(flags & MCP_DONTLOG)) {
272 add_taint(TAINT_MACHINE_CHECK);
276 * Clear state for this bank.
278 wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
282 * Don't clear MCG_STATUS here because it's only defined for
288 * The actual machine check handler. This only handles real
289 * exceptions when something got corrupted coming in through int 18.
291 * This is executed in NMI context not subject to normal locking rules. This
292 * implies that most kernel services cannot be safely used. Don't even
293 * think about putting a printk in there!
295 void do_machine_check(struct pt_regs *regs, long error_code)
297 struct mce m, panicm;
298 int panicm_found = 0;
302 * If no_way_out gets set, there is no safe way to recover from this
303 * MCE. If tolerant is cranked up, we'll try anyway.
307 * If kill_it gets set, there might be a way to recover from this
311 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
313 atomic_inc(&mce_entry);
315 if (notify_die(DIE_NMI, "machine check", regs, error_code,
316 18, SIGKILL) == NOTIFY_STOP)
323 rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus);
325 /* if the restart IP is not valid, we're done for */
326 if (!(m.mcgstatus & MCG_STATUS_RIPV))
332 for (i = 0; i < banks; i++) {
333 __clear_bit(i, toclear);
341 rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status);
342 if ((m.status & MCI_STATUS_VAL) == 0)
346 * Non uncorrected errors are handled by machine_check_poll
349 if ((m.status & MCI_STATUS_UC) == 0)
353 * Set taint even when machine check was not enabled.
355 add_taint(TAINT_MACHINE_CHECK);
357 __set_bit(i, toclear);
359 if (m.status & MCI_STATUS_EN) {
360 /* if PCC was set, there's no way out */
361 no_way_out |= !!(m.status & MCI_STATUS_PCC);
363 * If this error was uncorrectable and there was
364 * an overflow, we're in trouble. If no overflow,
365 * we might get away with just killing a task.
367 if (m.status & MCI_STATUS_UC) {
368 if (tolerant < 1 || m.status & MCI_STATUS_OVER)
374 * Machine check event was not enabled. Clear, but
380 if (m.status & MCI_STATUS_MISCV)
381 rdmsrl(MSR_IA32_MC0_MISC + i*4, m.misc);
382 if (m.status & MCI_STATUS_ADDRV)
383 rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr);
385 mce_get_rip(&m, regs);
389 * Did this bank cause the exception?
391 * Assume that the bank with uncorrectable errors did it,
392 * and that there is only a single one:
394 if ((m.status & MCI_STATUS_UC) &&
395 (m.status & MCI_STATUS_EN)) {
402 * If we didn't find an uncorrectable error, pick
403 * the last one (shouldn't happen, just being safe).
409 * If we have decided that we just CAN'T continue, and the user
410 * has not set tolerant to an insane level, give up and die.
412 if (no_way_out && tolerant < 3)
413 mce_panic("Machine check", &panicm, mcestart);
416 * If the error seems to be unrecoverable, something should be
417 * done. Try to kill as little as possible. If we can kill just
418 * one task, do that. If the user has set the tolerance very
419 * high, don't try to do anything at all.
421 if (kill_it && tolerant < 3) {
425 * If the EIPV bit is set, it means the saved IP is the
426 * instruction which caused the MCE.
428 if (m.mcgstatus & MCG_STATUS_EIPV)
429 user_space = panicm.ip && (panicm.cs & 3);
432 * If we know that the error was in user space, send a
433 * SIGBUS. Otherwise, panic if tolerance is low.
435 * force_sig() takes an awful lot of locks and has a slight
436 * risk of deadlocking.
439 force_sig(SIGBUS, current);
440 } else if (panic_on_oops || tolerant < 2) {
441 mce_panic("Uncorrected machine check",
446 /* notify userspace ASAP */
447 set_thread_flag(TIF_MCE_NOTIFY);
449 /* the last thing we do is clear state */
450 for (i = 0; i < banks; i++) {
451 if (test_bit(i, toclear))
452 wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
454 wrmsrl(MSR_IA32_MCG_STATUS, 0);
456 atomic_dec(&mce_entry);
459 #ifdef CONFIG_X86_MCE_INTEL
461 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
462 * @cpu: The CPU on which the event occurred.
463 * @status: Event status information
465 * This function should be called by the thermal interrupt after the
466 * event has been processed and the decision was made to log the event
469 * The status parameter will be saved to the 'status' field of 'struct mce'
470 * and historically has been the register value of the
471 * MSR_IA32_THERMAL_STATUS (Intel) msr.
473 void mce_log_therm_throt_event(__u64 status)
478 m.bank = MCE_THERMAL_BANK;
482 #endif /* CONFIG_X86_MCE_INTEL */
485 * Periodic polling timer for "silent" machine check errors. If the
486 * poller finds an MCE, poll 2x faster. When the poller finds no more
487 * errors, poll 2x slower (up to check_interval seconds).
489 static int check_interval = 5 * 60; /* 5 minutes */
491 static DEFINE_PER_CPU(int, next_interval); /* in jiffies */
492 static DEFINE_PER_CPU(struct timer_list, mce_timer);
494 static void mcheck_timer(unsigned long data)
496 struct timer_list *t = &per_cpu(mce_timer, data);
499 WARN_ON(smp_processor_id() != data);
501 if (mce_available(¤t_cpu_data)) {
502 machine_check_poll(MCP_TIMESTAMP,
503 &__get_cpu_var(mce_poll_banks));
507 * Alert userspace if needed. If we logged an MCE, reduce the
508 * polling interval, otherwise increase the polling interval.
510 n = &__get_cpu_var(next_interval);
511 if (mce_notify_user()) {
512 *n = max(*n/2, HZ/100);
514 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
517 t->expires = jiffies + *n;
521 static void mce_do_trigger(struct work_struct *work)
523 call_usermodehelper(trigger, trigger_argv, NULL, UMH_NO_WAIT);
526 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
529 * Notify the user(s) about new machine check events.
530 * Can be called from interrupt context, but not from machine check/NMI
533 int mce_notify_user(void)
535 /* Not more than two messages every minute */
536 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
538 clear_thread_flag(TIF_MCE_NOTIFY);
540 if (test_and_clear_bit(0, ¬ify_user)) {
541 wake_up_interruptible(&mce_wait);
544 * There is no risk of missing notifications because
545 * work_pending is always cleared before the function is
548 if (trigger[0] && !work_pending(&mce_trigger_work))
549 schedule_work(&mce_trigger_work);
551 if (__ratelimit(&ratelimit))
552 printk(KERN_INFO "Machine check events logged\n");
560 * Initialize Machine Checks for a CPU.
562 static int mce_cap_init(void)
567 rdmsrl(MSR_IA32_MCG_CAP, cap);
569 b = cap & MCG_BANKCNT_MASK;
570 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
572 if (b > MAX_NR_BANKS) {
574 "MCE: Using only %u machine check banks out of %u\n",
579 /* Don't support asymmetric configurations today */
580 WARN_ON(banks != 0 && b != banks);
583 bank = kmalloc(banks * sizeof(u64), GFP_KERNEL);
586 memset(bank, 0xff, banks * sizeof(u64));
589 /* Use accurate RIP reporting if available. */
590 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
591 rip_msr = MSR_IA32_MCG_EIP;
596 static void mce_init(void *dummy)
598 mce_banks_t all_banks;
603 * Log the machine checks left over from the previous reset.
605 bitmap_fill(all_banks, MAX_NR_BANKS);
606 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
608 set_in_cr4(X86_CR4_MCE);
610 rdmsrl(MSR_IA32_MCG_CAP, cap);
612 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
614 for (i = 0; i < banks; i++) {
615 if (skip_bank_init(i))
617 wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]);
618 wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
622 /* Add per CPU specific workarounds here */
623 static void mce_cpu_quirks(struct cpuinfo_x86 *c)
625 /* This should be disabled by the BIOS, but isn't always */
626 if (c->x86_vendor == X86_VENDOR_AMD) {
627 if (c->x86 == 15 && banks > 4) {
629 * disable GART TBL walk error reporting, which
630 * trips off incorrectly with the IOMMU & 3ware
633 clear_bit(10, (unsigned long *)&bank[4]);
635 if (c->x86 <= 17 && mce_bootlog < 0) {
637 * Lots of broken BIOS around that don't clear them
638 * by default and leave crap in there. Don't log:
643 * Various K7s with broken bank 0 around. Always disable
650 if (c->x86_vendor == X86_VENDOR_INTEL) {
652 * SDM documents that on family 6 bank 0 should not be written
653 * because it aliases to another special BIOS controlled
655 * But it's not aliased anymore on model 0x1a+
656 * Don't ignore bank 0 completely because there could be a
657 * valid event later, merely don't write CTL0.
660 if (c->x86 == 6 && c->x86_model < 0x1A)
661 __set_bit(0, &dont_init_banks);
665 static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c)
669 switch (c->x86_vendor) {
670 case X86_VENDOR_INTEL:
671 if (mce_p5_enabled())
672 intel_p5_mcheck_init(c);
674 case X86_VENDOR_CENTAUR:
675 winchip_mcheck_init(c);
680 static void mce_cpu_features(struct cpuinfo_x86 *c)
682 switch (c->x86_vendor) {
683 case X86_VENDOR_INTEL:
684 mce_intel_feature_init(c);
687 mce_amd_feature_init(c);
694 static void mce_init_timer(void)
696 struct timer_list *t = &__get_cpu_var(mce_timer);
697 int *n = &__get_cpu_var(next_interval);
699 *n = check_interval * HZ;
702 setup_timer(t, mcheck_timer, smp_processor_id());
703 t->expires = round_jiffies(jiffies + *n);
708 * Called for each booted CPU to set up machine checks.
709 * Must be called with preempt off:
711 void __cpuinit mcheck_init(struct cpuinfo_x86 *c)
718 if (!mce_available(c))
721 if (mce_cap_init() < 0) {
727 machine_check_vector = do_machine_check;
735 * Character device to read and clear the MCE log.
738 static DEFINE_SPINLOCK(mce_state_lock);
739 static int open_count; /* #times opened */
740 static int open_exclu; /* already open exclusive? */
742 static int mce_open(struct inode *inode, struct file *file)
745 spin_lock(&mce_state_lock);
747 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
748 spin_unlock(&mce_state_lock);
754 if (file->f_flags & O_EXCL)
758 spin_unlock(&mce_state_lock);
761 return nonseekable_open(inode, file);
764 static int mce_release(struct inode *inode, struct file *file)
766 spin_lock(&mce_state_lock);
771 spin_unlock(&mce_state_lock);
776 static void collect_tscs(void *data)
778 unsigned long *cpu_tsc = (unsigned long *)data;
780 rdtscll(cpu_tsc[smp_processor_id()]);
783 static DEFINE_MUTEX(mce_read_mutex);
785 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
788 char __user *buf = ubuf;
789 unsigned long *cpu_tsc;
793 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
797 mutex_lock(&mce_read_mutex);
798 next = rcu_dereference(mcelog.next);
800 /* Only supports full reads right now */
801 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) {
802 mutex_unlock(&mce_read_mutex);
811 for (i = prev; i < next; i++) {
812 unsigned long start = jiffies;
814 while (!mcelog.entry[i].finished) {
815 if (time_after_eq(jiffies, start + 2)) {
816 memset(mcelog.entry + i, 0,
823 err |= copy_to_user(buf, mcelog.entry + i,
825 buf += sizeof(struct mce);
830 memset(mcelog.entry + prev, 0,
831 (next - prev) * sizeof(struct mce));
833 next = cmpxchg(&mcelog.next, prev, 0);
834 } while (next != prev);
839 * Collect entries that were still getting written before the
842 on_each_cpu(collect_tscs, cpu_tsc, 1);
844 for (i = next; i < MCE_LOG_LEN; i++) {
845 if (mcelog.entry[i].finished &&
846 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
847 err |= copy_to_user(buf, mcelog.entry+i,
850 buf += sizeof(struct mce);
851 memset(&mcelog.entry[i], 0, sizeof(struct mce));
854 mutex_unlock(&mce_read_mutex);
857 return err ? -EFAULT : buf - ubuf;
860 static unsigned int mce_poll(struct file *file, poll_table *wait)
862 poll_wait(file, &mce_wait, wait);
863 if (rcu_dereference(mcelog.next))
864 return POLLIN | POLLRDNORM;
868 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
870 int __user *p = (int __user *)arg;
872 if (!capable(CAP_SYS_ADMIN))
876 case MCE_GET_RECORD_LEN:
877 return put_user(sizeof(struct mce), p);
878 case MCE_GET_LOG_LEN:
879 return put_user(MCE_LOG_LEN, p);
880 case MCE_GETCLEAR_FLAGS: {
884 flags = mcelog.flags;
885 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
887 return put_user(flags, p);
894 static const struct file_operations mce_chrdev_ops = {
896 .release = mce_release,
899 .unlocked_ioctl = mce_ioctl,
902 static struct miscdevice mce_log_device = {
909 * mce=off disables machine check
910 * mce=TOLERANCELEVEL (number, see above)
911 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
912 * mce=nobootlog Don't log MCEs from before booting.
914 static int __init mcheck_enable(char *str)
920 if (!strcmp(str, "off"))
922 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
923 mce_bootlog = (str[0] == 'b');
924 else if (isdigit(str[0]))
925 get_option(&str, &tolerant);
927 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
933 __setup("mce", mcheck_enable);
940 * Disable machine checks on suspend and shutdown. We can't really handle
943 static int mce_disable(void)
947 for (i = 0; i < banks; i++) {
948 if (!skip_bank_init(i))
949 wrmsrl(MSR_IA32_MC0_CTL + i*4, 0);
954 static int mce_suspend(struct sys_device *dev, pm_message_t state)
956 return mce_disable();
959 static int mce_shutdown(struct sys_device *dev)
961 return mce_disable();
965 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
966 * Only one CPU is active at this time, the others get re-added later using
969 static int mce_resume(struct sys_device *dev)
972 mce_cpu_features(¤t_cpu_data);
977 static void mce_cpu_restart(void *data)
979 del_timer_sync(&__get_cpu_var(mce_timer));
980 if (mce_available(¤t_cpu_data))
985 /* Reinit MCEs after user configuration changes */
986 static void mce_restart(void)
988 on_each_cpu(mce_cpu_restart, NULL, 1);
991 static struct sysdev_class mce_sysclass = {
992 .suspend = mce_suspend,
993 .shutdown = mce_shutdown,
994 .resume = mce_resume,
995 .name = "machinecheck",
998 DEFINE_PER_CPU(struct sys_device, mce_dev);
1001 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1003 /* Why are there no generic functions for this? */
1004 #define ACCESSOR(name, var, start) \
1005 static ssize_t show_ ## name(struct sys_device *s, \
1006 struct sysdev_attribute *attr, \
1008 return sprintf(buf, "%Lx\n", (u64)var); \
1010 static ssize_t set_ ## name(struct sys_device *s, \
1011 struct sysdev_attribute *attr, \
1012 const char *buf, size_t siz) { \
1014 u64 new = simple_strtoull(buf, &end, 0); \
1023 static SYSDEV_ATTR(name, 0644, show_ ## name, set_ ## name);
1025 static struct sysdev_attribute *bank_attrs;
1027 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1030 u64 b = bank[attr - bank_attrs];
1032 return sprintf(buf, "%llx\n", b);
1035 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1036 const char *buf, size_t siz)
1039 u64 new = simple_strtoull(buf, &end, 0);
1044 bank[attr - bank_attrs] = new;
1051 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1053 strcpy(buf, trigger);
1055 return strlen(trigger) + 1;
1058 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1059 const char *buf, size_t siz)
1064 strncpy(trigger, buf, sizeof(trigger));
1065 trigger[sizeof(trigger)-1] = 0;
1066 len = strlen(trigger);
1067 p = strchr(trigger, '\n');
1075 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1076 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1078 ACCESSOR(check_interval, check_interval, mce_restart())
1080 static struct sysdev_attribute *mce_attrs[] = {
1081 &attr_tolerant.attr, &attr_check_interval, &attr_trigger,
1085 static cpumask_var_t mce_dev_initialized;
1087 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1088 static __cpuinit int mce_create_device(unsigned int cpu)
1093 if (!mce_available(&boot_cpu_data))
1096 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1097 per_cpu(mce_dev, cpu).id = cpu;
1098 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
1100 err = sysdev_register(&per_cpu(mce_dev, cpu));
1104 for (i = 0; mce_attrs[i]; i++) {
1105 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1109 for (i = 0; i < banks; i++) {
1110 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
1115 cpumask_set_cpu(cpu, mce_dev_initialized);
1120 sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]);
1123 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1125 sysdev_unregister(&per_cpu(mce_dev, cpu));
1130 static __cpuinit void mce_remove_device(unsigned int cpu)
1134 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
1137 for (i = 0; mce_attrs[i]; i++)
1138 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1140 for (i = 0; i < banks; i++)
1141 sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]);
1143 sysdev_unregister(&per_cpu(mce_dev, cpu));
1144 cpumask_clear_cpu(cpu, mce_dev_initialized);
1147 /* Make sure there are no machine checks on offlined CPUs. */
1148 static void mce_disable_cpu(void *h)
1150 unsigned long action = *(unsigned long *)h;
1153 if (!mce_available(¤t_cpu_data))
1155 if (!(action & CPU_TASKS_FROZEN))
1157 for (i = 0; i < banks; i++) {
1158 if (!skip_bank_init(i))
1159 wrmsrl(MSR_IA32_MC0_CTL + i*4, 0);
1163 static void mce_reenable_cpu(void *h)
1165 unsigned long action = *(unsigned long *)h;
1168 if (!mce_available(¤t_cpu_data))
1171 if (!(action & CPU_TASKS_FROZEN))
1173 for (i = 0; i < banks; i++) {
1174 if (!skip_bank_init(i))
1175 wrmsrl(MSR_IA32_MC0_CTL + i*4, bank[i]);
1179 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
1180 static int __cpuinit
1181 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
1183 unsigned int cpu = (unsigned long)hcpu;
1184 struct timer_list *t = &per_cpu(mce_timer, cpu);
1188 case CPU_ONLINE_FROZEN:
1189 mce_create_device(cpu);
1190 if (threshold_cpu_callback)
1191 threshold_cpu_callback(action, cpu);
1194 case CPU_DEAD_FROZEN:
1195 if (threshold_cpu_callback)
1196 threshold_cpu_callback(action, cpu);
1197 mce_remove_device(cpu);
1199 case CPU_DOWN_PREPARE:
1200 case CPU_DOWN_PREPARE_FROZEN:
1202 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
1204 case CPU_DOWN_FAILED:
1205 case CPU_DOWN_FAILED_FROZEN:
1206 t->expires = round_jiffies(jiffies +
1207 __get_cpu_var(next_interval));
1208 add_timer_on(t, cpu);
1209 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
1212 /* intentionally ignoring frozen here */
1213 cmci_rediscover(cpu);
1219 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
1220 .notifier_call = mce_cpu_callback,
1223 static __init int mce_init_banks(void)
1227 bank_attrs = kzalloc(sizeof(struct sysdev_attribute) * banks,
1232 for (i = 0; i < banks; i++) {
1233 struct sysdev_attribute *a = &bank_attrs[i];
1235 a->attr.name = kasprintf(GFP_KERNEL, "bank%d", i);
1239 a->attr.mode = 0644;
1240 a->show = show_bank;
1241 a->store = set_bank;
1247 kfree(bank_attrs[i].attr.name);
1254 static __init int mce_init_device(void)
1259 if (!mce_available(&boot_cpu_data))
1262 alloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
1264 err = mce_init_banks();
1268 err = sysdev_class_register(&mce_sysclass);
1272 for_each_online_cpu(i) {
1273 err = mce_create_device(i);
1278 register_hotcpu_notifier(&mce_cpu_notifier);
1279 misc_register(&mce_log_device);
1284 device_initcall(mce_init_device);
1286 #else /* CONFIG_X86_OLD_MCE: */
1289 EXPORT_SYMBOL_GPL(nr_mce_banks); /* non-fatal.o */
1291 /* This has to be run for each processor */
1292 void mcheck_init(struct cpuinfo_x86 *c)
1294 if (mce_disabled == 1)
1297 switch (c->x86_vendor) {
1298 case X86_VENDOR_AMD:
1302 case X86_VENDOR_INTEL:
1304 intel_p5_mcheck_init(c);
1306 intel_p6_mcheck_init(c);
1308 intel_p4_mcheck_init(c);
1311 case X86_VENDOR_CENTAUR:
1313 winchip_mcheck_init(c);
1319 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", nr_mce_banks);
1322 static int __init mcheck_enable(char *str)
1328 __setup("mce", mcheck_enable);
1330 #endif /* CONFIG_X86_OLD_MCE */
1333 * Old style boot options parsing. Only for compatibility.
1335 static int __init mcheck_disable(char *str)
1340 __setup("nomce", mcheck_disable);