1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/delay.h>
9 #include <linux/sched.h>
10 #include <linux/init.h>
11 #include <linux/kgdb.h>
12 #include <linux/smp.h>
15 #include <asm/stackprotector.h>
16 #include <asm/perf_event.h>
17 #include <asm/mmu_context.h>
18 #include <asm/archrandom.h>
19 #include <asm/hypervisor.h>
20 #include <asm/processor.h>
21 #include <asm/sections.h>
22 #include <linux/topology.h>
23 #include <linux/cpumask.h>
24 #include <asm/pgtable.h>
25 #include <linux/atomic.h>
26 #include <asm/proto.h>
27 #include <asm/setup.h>
32 #include <linux/numa.h>
39 #ifdef CONFIG_X86_LOCAL_APIC
40 #include <asm/uv/uv.h>
45 /* all of these masks are initialized in setup_cpu_local_masks() */
46 cpumask_var_t cpu_initialized_mask;
47 cpumask_var_t cpu_callout_mask;
48 cpumask_var_t cpu_callin_mask;
50 /* representing cpus for which sibling maps can be computed */
51 cpumask_var_t cpu_sibling_setup_mask;
53 /* correctly size the local cpu masks */
54 void __init setup_cpu_local_masks(void)
56 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
57 alloc_bootmem_cpumask_var(&cpu_callin_mask);
58 alloc_bootmem_cpumask_var(&cpu_callout_mask);
59 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
62 static void __cpuinit default_init(struct cpuinfo_x86 *c)
65 cpu_detect_cache_sizes(c);
67 /* Not much we can do here... */
68 /* Check if at least it has cpuid */
69 if (c->cpuid_level == -1) {
70 /* No cpuid. It must be an ancient CPU */
72 strcpy(c->x86_model_id, "486");
74 strcpy(c->x86_model_id, "386");
79 static const struct cpu_dev __cpuinitconst default_cpu = {
80 .c_init = default_init,
81 .c_vendor = "Unknown",
82 .c_x86_vendor = X86_VENDOR_UNKNOWN,
85 static const struct cpu_dev *this_cpu __cpuinitdata = &default_cpu;
87 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
90 * We need valid kernel segments for data and code in long mode too
91 * IRET will check the segment types kkeil 2000/10/28
92 * Also sysret mandates a special GDT layout
94 * TLS descriptors are currently at a different place compared to i386.
95 * Hopefully nobody expects them at a fixed place (Wine?)
97 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
98 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
99 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
100 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
101 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
102 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
104 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
105 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
106 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
107 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
109 * Segments used for calling PnP BIOS have byte granularity.
110 * They code segments and data segments have fixed 64k limits,
111 * the transfer segment sizes are set at run time.
114 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
116 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
118 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
120 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
122 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
124 * The APM segments have byte granularity and their bases
125 * are set at run time. All have 64k limits.
128 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
130 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
132 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
134 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
135 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
136 GDT_STACK_CANARY_INIT
139 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
141 static int __init x86_xsave_setup(char *s)
145 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
146 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
149 __setup("noxsave", x86_xsave_setup);
151 static int __init x86_xsaveopt_setup(char *s)
153 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
156 __setup("noxsaveopt", x86_xsaveopt_setup);
159 static int __init x86_pcid_setup(char *s)
161 /* require an exact match without trailing characters */
165 /* do not emit a message if the feature is not present */
166 if (!boot_cpu_has(X86_FEATURE_PCID))
169 setup_clear_cpu_cap(X86_FEATURE_PCID);
170 pr_info("nopcid: PCID feature disabled\n");
173 __setup("nopcid", x86_pcid_setup);
176 static int __init x86_noinvpcid_setup(char *s)
178 /* noinvpcid doesn't accept parameters */
182 /* do not emit a message if the feature is not present */
183 if (!boot_cpu_has(X86_FEATURE_INVPCID))
186 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
187 pr_info("noinvpcid: INVPCID feature disabled\n");
190 early_param("noinvpcid", x86_noinvpcid_setup);
193 static int cachesize_override __cpuinitdata = -1;
194 static int disable_x86_serial_nr __cpuinitdata = 1;
196 static int __init cachesize_setup(char *str)
198 get_option(&str, &cachesize_override);
201 __setup("cachesize=", cachesize_setup);
203 static int __init x86_fxsr_setup(char *s)
205 setup_clear_cpu_cap(X86_FEATURE_FXSR);
206 setup_clear_cpu_cap(X86_FEATURE_XMM);
209 __setup("nofxsr", x86_fxsr_setup);
211 static int __init x86_sep_setup(char *s)
213 setup_clear_cpu_cap(X86_FEATURE_SEP);
216 __setup("nosep", x86_sep_setup);
218 /* Standard macro to see if a specific flag is changeable */
219 static inline int flag_is_changeable_p(u32 flag)
224 * Cyrix and IDT cpus allow disabling of CPUID
225 * so the code below may return different results
226 * when it is executed before and after enabling
227 * the CPUID. Add "volatile" to not allow gcc to
228 * optimize the subsequent calls to this function.
230 asm volatile ("pushfl \n\t"
241 : "=&r" (f1), "=&r" (f2)
244 return ((f1^f2) & flag) != 0;
247 /* Probe for the CPUID instruction */
248 static int __cpuinit have_cpuid_p(void)
250 return flag_is_changeable_p(X86_EFLAGS_ID);
253 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
255 unsigned long lo, hi;
257 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
260 /* Disable processor serial number: */
262 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
264 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
266 printk(KERN_NOTICE "CPU serial number disabled.\n");
267 clear_cpu_cap(c, X86_FEATURE_PN);
269 /* Disabling the serial number may affect the cpuid level */
270 c->cpuid_level = cpuid_eax(0);
273 static int __init x86_serial_nr_setup(char *s)
275 disable_x86_serial_nr = 0;
278 __setup("serialnumber", x86_serial_nr_setup);
280 static inline int flag_is_changeable_p(u32 flag)
284 /* Probe for the CPUID instruction */
285 static inline int have_cpuid_p(void)
289 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
294 static int disable_smep __cpuinitdata;
295 static __init int setup_disable_smep(char *arg)
300 __setup("nosmep", setup_disable_smep);
302 static __cpuinit void setup_smep(struct cpuinfo_x86 *c)
304 if (cpu_has(c, X86_FEATURE_SMEP)) {
305 if (unlikely(disable_smep)) {
306 setup_clear_cpu_cap(X86_FEATURE_SMEP);
307 clear_in_cr4(X86_CR4_SMEP);
309 set_in_cr4(X86_CR4_SMEP);
313 static void setup_pcid(struct cpuinfo_x86 *c)
315 if (cpu_has(c, X86_FEATURE_PCID)) {
316 if (cpu_has(c, X86_FEATURE_PGE) && IS_ENABLED(CONFIG_X86_64)) {
318 * Regardless of whether PCID is enumerated, the
319 * SDM says that it can't be enabled in 32-bit mode.
321 set_in_cr4(X86_CR4_PCIDE);
324 * flush_tlb_all(), as currently implemented, won't
325 * work if PCID is on but PGE is not. Since that
326 * combination doesn't exist on real hardware, there's
327 * no reason to try to fully support it, but it's
328 * polite to avoid corrupting data if we're on
329 * an improperly configured VM.
331 clear_cpu_cap(c, X86_FEATURE_PCID);
337 * Some CPU features depend on higher CPUID levels, which may not always
338 * be available due to CPUID level capping or broken virtualization
339 * software. Add those features to this table to auto-disable them.
341 struct cpuid_dependent_feature {
346 static const struct cpuid_dependent_feature __cpuinitconst
347 cpuid_dependent_features[] = {
348 { X86_FEATURE_MWAIT, 0x00000005 },
349 { X86_FEATURE_DCA, 0x00000009 },
350 { X86_FEATURE_XSAVE, 0x0000000d },
354 static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
356 const struct cpuid_dependent_feature *df;
358 for (df = cpuid_dependent_features; df->feature; df++) {
360 if (!cpu_has(c, df->feature))
363 * Note: cpuid_level is set to -1 if unavailable, but
364 * extended_extended_level is set to 0 if unavailable
365 * and the legitimate extended levels are all negative
366 * when signed; hence the weird messing around with
369 if (!((s32)df->level < 0 ?
370 (u32)df->level > (u32)c->extended_cpuid_level :
371 (s32)df->level > (s32)c->cpuid_level))
374 clear_cpu_cap(c, df->feature);
379 "CPU: CPU feature %s disabled, no CPUID level 0x%x\n",
380 x86_cap_flags[df->feature], df->level);
385 * Naming convention should be: <Name> [(<Codename>)]
386 * This table only is used unless init_<vendor>() below doesn't set it;
387 * in particular, if CPUID levels 0x80000002..4 are supported, this
391 /* Look up CPU names by table lookup. */
392 static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c)
394 const struct cpu_model_info *info;
396 if (c->x86_model >= 16)
397 return NULL; /* Range check */
402 info = this_cpu->c_models;
404 while (info && info->family) {
405 if (info->family == c->x86)
406 return info->model_names[c->x86_model];
409 return NULL; /* Not found */
412 __u32 cpu_caps_cleared[NCAPINTS] __cpuinitdata;
413 __u32 cpu_caps_set[NCAPINTS] __cpuinitdata;
415 void load_percpu_segment(int cpu)
418 loadsegment(fs, __KERNEL_PERCPU);
421 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
423 load_stack_canary_segment();
427 * Current gdt points %fs at the "master" per-cpu area: after this,
428 * it's on the real one.
430 void switch_to_new_gdt(int cpu)
432 struct desc_ptr gdt_descr;
434 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
435 gdt_descr.size = GDT_SIZE - 1;
436 load_gdt(&gdt_descr);
437 /* Reload the per-cpu base */
439 load_percpu_segment(cpu);
442 static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {};
444 static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
449 if (c->extended_cpuid_level < 0x80000004)
452 v = (unsigned int *)c->x86_model_id;
453 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
454 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
455 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
456 c->x86_model_id[48] = 0;
459 * Intel chips right-justify this string for some dumb reason;
460 * undo that brain damage:
462 p = q = &c->x86_model_id[0];
468 while (q <= &c->x86_model_id[48])
469 *q++ = '\0'; /* Zero-pad the rest */
473 void __cpuinit cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
475 unsigned int n, dummy, ebx, ecx, edx, l2size;
477 n = c->extended_cpuid_level;
479 if (n >= 0x80000005) {
480 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
481 c->x86_cache_size = (ecx>>24) + (edx>>24);
483 /* On K8 L1 TLB is inclusive, so don't count it */
488 if (n < 0x80000006) /* Some chips just has a large L1. */
491 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
495 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
497 /* do processor-specific cache resizing */
498 if (this_cpu->c_size_cache)
499 l2size = this_cpu->c_size_cache(c, l2size);
501 /* Allow user to override all this if necessary. */
502 if (cachesize_override != -1)
503 l2size = cachesize_override;
506 return; /* Again, no L2 cache is possible */
509 c->x86_cache_size = l2size;
512 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
515 u32 eax, ebx, ecx, edx;
516 int index_msb, core_bits;
519 if (!cpu_has(c, X86_FEATURE_HT))
522 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
525 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
528 cpuid(1, &eax, &ebx, &ecx, &edx);
530 smp_num_siblings = (ebx & 0xff0000) >> 16;
532 if (smp_num_siblings == 1) {
533 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n");
537 if (smp_num_siblings <= 1)
540 index_msb = get_count_order(smp_num_siblings);
541 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
543 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
545 index_msb = get_count_order(smp_num_siblings);
547 core_bits = get_count_order(c->x86_max_cores);
549 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
550 ((1 << core_bits) - 1);
553 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
554 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
556 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
563 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
565 char *v = c->x86_vendor_id;
568 for (i = 0; i < X86_VENDOR_NUM; i++) {
572 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
573 (cpu_devs[i]->c_ident[1] &&
574 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
576 this_cpu = cpu_devs[i];
577 c->x86_vendor = this_cpu->c_x86_vendor;
583 "CPU: vendor_id '%s' unknown, using generic init.\n" \
584 "CPU: Your system may be unstable.\n", v);
586 c->x86_vendor = X86_VENDOR_UNKNOWN;
587 this_cpu = &default_cpu;
590 void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
592 /* Get vendor name */
593 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
594 (unsigned int *)&c->x86_vendor_id[0],
595 (unsigned int *)&c->x86_vendor_id[8],
596 (unsigned int *)&c->x86_vendor_id[4]);
599 /* Intel-defined flags: level 0x00000001 */
600 if (c->cpuid_level >= 0x00000001) {
601 u32 junk, tfms, cap0, misc;
603 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
604 c->x86 = (tfms >> 8) & 0xf;
605 c->x86_model = (tfms >> 4) & 0xf;
606 c->x86_mask = tfms & 0xf;
609 c->x86 += (tfms >> 20) & 0xff;
611 c->x86_model += ((tfms >> 16) & 0xf) << 4;
613 if (cap0 & (1<<19)) {
614 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
615 c->x86_cache_alignment = c->x86_clflush_size;
620 void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
625 /* Intel-defined flags: level 0x00000001 */
626 if (c->cpuid_level >= 0x00000001) {
627 u32 capability, excap;
629 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
630 c->x86_capability[0] = capability;
631 c->x86_capability[4] = excap;
634 /* Additional Intel-defined flags: level 0x00000007 */
635 if (c->cpuid_level >= 0x00000007) {
636 u32 eax, ebx, ecx, edx;
638 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
640 c->x86_capability[9] = ebx;
643 /* AMD-defined flags: level 0x80000001 */
644 xlvl = cpuid_eax(0x80000000);
645 c->extended_cpuid_level = xlvl;
647 if ((xlvl & 0xffff0000) == 0x80000000) {
648 if (xlvl >= 0x80000001) {
649 c->x86_capability[1] = cpuid_edx(0x80000001);
650 c->x86_capability[6] = cpuid_ecx(0x80000001);
654 if (c->extended_cpuid_level >= 0x80000008) {
655 u32 eax = cpuid_eax(0x80000008);
657 c->x86_virt_bits = (eax >> 8) & 0xff;
658 c->x86_phys_bits = eax & 0xff;
661 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
662 c->x86_phys_bits = 36;
665 if (c->extended_cpuid_level >= 0x80000007)
666 c->x86_power = cpuid_edx(0x80000007);
668 init_scattered_cpuid_features(c);
671 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
677 * First of all, decide if this is a 486 or higher
678 * It's a 486 if we can modify the AC flag
680 if (flag_is_changeable_p(X86_EFLAGS_AC))
685 for (i = 0; i < X86_VENDOR_NUM; i++)
686 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
687 c->x86_vendor_id[0] = 0;
688 cpu_devs[i]->c_identify(c);
689 if (c->x86_vendor_id[0]) {
698 * Do minimum CPU detection early.
699 * Fields really needed: vendor, cpuid_level, family, model, mask,
701 * The others are not touched to avoid unwanted side effects.
703 * WARNING: this function is only called on the BP. Don't add code here
704 * that is supposed to run on all CPUs.
706 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
709 c->x86_clflush_size = 64;
710 c->x86_phys_bits = 36;
711 c->x86_virt_bits = 48;
713 c->x86_clflush_size = 32;
714 c->x86_phys_bits = 32;
715 c->x86_virt_bits = 32;
717 c->x86_cache_alignment = c->x86_clflush_size;
719 memset(&c->x86_capability, 0, sizeof c->x86_capability);
720 c->extended_cpuid_level = 0;
723 identify_cpu_without_cpuid(c);
725 /* cyrix could have cpuid enabled via c_identify()*/
735 if (this_cpu->c_early_init)
736 this_cpu->c_early_init(c);
739 filter_cpuid_features(c, false);
743 if (this_cpu->c_bsp_init)
744 this_cpu->c_bsp_init(c);
747 void __init early_cpu_init(void)
749 const struct cpu_dev *const *cdev;
752 #ifdef CONFIG_PROCESSOR_SELECT
753 printk(KERN_INFO "KERNEL supported cpus:\n");
756 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
757 const struct cpu_dev *cpudev = *cdev;
759 if (count >= X86_VENDOR_NUM)
761 cpu_devs[count] = cpudev;
764 #ifdef CONFIG_PROCESSOR_SELECT
768 for (j = 0; j < 2; j++) {
769 if (!cpudev->c_ident[j])
771 printk(KERN_INFO " %s %s\n", cpudev->c_vendor,
777 early_identify_cpu(&boot_cpu_data);
781 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
782 * unfortunately, that's not true in practice because of early VIA
783 * chips and (more importantly) broken virtualizers that are not easy
784 * to detect. In the latter case it doesn't even *fail* reliably, so
785 * probing for it doesn't even work. Disable it completely on 32-bit
786 * unless we can find a reliable way to detect all the broken cases.
787 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
789 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
792 clear_cpu_cap(c, X86_FEATURE_NOPL);
794 set_cpu_cap(c, X86_FEATURE_NOPL);
798 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
800 c->extended_cpuid_level = 0;
803 identify_cpu_without_cpuid(c);
805 /* cyrix could have cpuid enabled via c_identify()*/
815 if (c->cpuid_level >= 0x00000001) {
816 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
818 # ifdef CONFIG_X86_HT
819 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
821 c->apicid = c->initial_apicid;
824 c->phys_proc_id = c->initial_apicid;
829 get_model_name(c); /* Default name */
835 * This does the hard work of actually picking apart the CPU stuff...
837 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
841 c->loops_per_jiffy = loops_per_jiffy;
842 c->x86_cache_size = -1;
843 c->x86_vendor = X86_VENDOR_UNKNOWN;
844 c->x86_model = c->x86_mask = 0; /* So far unknown... */
845 c->x86_vendor_id[0] = '\0'; /* Unset */
846 c->x86_model_id[0] = '\0'; /* Unset */
847 c->x86_max_cores = 1;
848 c->x86_coreid_bits = 0;
850 c->x86_clflush_size = 64;
851 c->x86_phys_bits = 36;
852 c->x86_virt_bits = 48;
854 c->cpuid_level = -1; /* CPUID not detected */
855 c->x86_clflush_size = 32;
856 c->x86_phys_bits = 32;
857 c->x86_virt_bits = 32;
859 c->x86_cache_alignment = c->x86_clflush_size;
860 memset(&c->x86_capability, 0, sizeof c->x86_capability);
864 if (this_cpu->c_identify)
865 this_cpu->c_identify(c);
867 /* Clear/Set all flags overriden by options, after probe */
868 for (i = 0; i < NCAPINTS; i++) {
869 c->x86_capability[i] &= ~cpu_caps_cleared[i];
870 c->x86_capability[i] |= cpu_caps_set[i];
874 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
878 * Vendor-specific initialization. In this section we
879 * canonicalize the feature flags, meaning if there are
880 * features a certain CPU supports which CPUID doesn't
881 * tell us, CPUID claiming incorrect flags, or other bugs,
882 * we handle them here.
884 * At the end of this section, c->x86_capability better
885 * indicate the features this CPU genuinely supports!
887 if (this_cpu->c_init)
890 /* Disable the PN if appropriate */
891 squash_the_stupid_serial_number(c);
897 * The vendor-specific functions might have changed features.
898 * Now we do "generic changes."
901 /* Filter out anything that depends on CPUID levels we don't have */
902 filter_cpuid_features(c, true);
904 /* If the model name is still unset, do table lookup. */
905 if (!c->x86_model_id[0]) {
907 p = table_lookup_model(c);
909 strcpy(c->x86_model_id, p);
912 sprintf(c->x86_model_id, "%02x/%02x",
913 c->x86, c->x86_model);
924 * Clear/Set all flags overriden by options, need do it
925 * before following smp all cpus cap AND.
927 for (i = 0; i < NCAPINTS; i++) {
928 c->x86_capability[i] &= ~cpu_caps_cleared[i];
929 c->x86_capability[i] |= cpu_caps_set[i];
933 * On SMP, boot_cpu_data holds the common feature set between
934 * all CPUs; so make sure that we indicate which features are
935 * common between the CPUs. The first time this routine gets
936 * executed, c == &boot_cpu_data.
938 if (c != &boot_cpu_data) {
939 /* AND the already accumulated flags with these */
940 for (i = 0; i < NCAPINTS; i++)
941 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
944 /* Init Machine Check Exception if available. */
947 select_idle_routine(c);
950 numa_add_cpu(smp_processor_id());
955 static void vgetcpu_set_mode(void)
957 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
958 vgetcpu_mode = VGETCPU_RDTSCP;
960 vgetcpu_mode = VGETCPU_LSL;
964 void __init identify_boot_cpu(void)
966 identify_cpu(&boot_cpu_data);
967 init_amd_e400_c1e_mask();
976 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
978 BUG_ON(c == &boot_cpu_data);
991 static const struct msr_range msr_range_array[] __cpuinitconst = {
992 { 0x00000000, 0x00000418},
993 { 0xc0000000, 0xc000040b},
994 { 0xc0010000, 0xc0010142},
995 { 0xc0011000, 0xc001103b},
998 static void __cpuinit print_cpu_msr(void)
1000 unsigned index_min, index_max;
1005 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
1006 index_min = msr_range_array[i].min;
1007 index_max = msr_range_array[i].max;
1009 for (index = index_min; index < index_max; index++) {
1010 if (rdmsrl_amd_safe(index, &val))
1012 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
1017 static int show_msr __cpuinitdata;
1019 static __init int setup_show_msr(char *arg)
1023 get_option(&arg, &num);
1029 __setup("show_msr=", setup_show_msr);
1031 static __init int setup_noclflush(char *arg)
1033 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
1036 __setup("noclflush", setup_noclflush);
1038 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1040 const char *vendor = NULL;
1042 if (c->x86_vendor < X86_VENDOR_NUM) {
1043 vendor = this_cpu->c_vendor;
1045 if (c->cpuid_level >= 0)
1046 vendor = c->x86_vendor_id;
1049 if (vendor && !strstr(c->x86_model_id, vendor))
1050 printk(KERN_CONT "%s ", vendor);
1052 if (c->x86_model_id[0])
1053 printk(KERN_CONT "%s", c->x86_model_id);
1055 printk(KERN_CONT "%d86", c->x86);
1057 if (c->x86_mask || c->cpuid_level >= 0)
1058 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1060 printk(KERN_CONT "\n");
1063 if (c->cpu_index < show_msr)
1071 static __init int setup_disablecpuid(char *arg)
1075 if (get_option(&arg, &bit) && bit >= 0 && bit < NCAPINTS * 32)
1076 setup_clear_cpu_cap(bit);
1082 __setup("clearcpuid=", setup_disablecpuid);
1084 #ifdef CONFIG_X86_64
1085 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
1087 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1088 irq_stack_union) __aligned(PAGE_SIZE);
1091 * The following four percpu variables are hot. Align current_task to
1092 * cacheline size such that all four fall in the same cacheline.
1094 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1096 EXPORT_PER_CPU_SYMBOL(current_task);
1098 DEFINE_PER_CPU(unsigned long, kernel_stack) =
1099 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE;
1100 EXPORT_PER_CPU_SYMBOL(kernel_stack);
1102 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1103 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
1105 DEFINE_PER_CPU(unsigned int, irq_count) = -1;
1108 * Special IST stacks which the CPU switches to when it calls
1109 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1110 * limit), all of them are 4K, except the debug stack which
1113 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1114 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1115 [DEBUG_STACK - 1] = DEBUG_STKSZ
1118 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1119 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1121 /* May not be marked __init: used by software suspend */
1122 void syscall_init(void)
1125 * LSTAR and STAR live in a bit strange symbiosis.
1126 * They both write to the same internal register. STAR allows to
1127 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1129 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
1130 wrmsrl(MSR_LSTAR, system_call);
1131 wrmsrl(MSR_CSTAR, ignore_sysret);
1133 #ifdef CONFIG_IA32_EMULATION
1134 syscall32_cpu_init();
1137 /* Flags to clear on syscall */
1138 wrmsrl(MSR_SYSCALL_MASK,
1139 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
1142 unsigned long kernel_eflags;
1145 * Copies of the original ist values from the tss are only accessed during
1146 * debugging, no special alignment required.
1148 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1150 #else /* CONFIG_X86_64 */
1152 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1153 EXPORT_PER_CPU_SYMBOL(current_task);
1155 #ifdef CONFIG_CC_STACKPROTECTOR
1156 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1159 /* Make sure %fs and %gs are initialized properly in idle threads */
1160 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
1162 memset(regs, 0, sizeof(struct pt_regs));
1163 regs->fs = __KERNEL_PERCPU;
1164 regs->gs = __KERNEL_STACK_CANARY;
1168 #endif /* CONFIG_X86_64 */
1171 * Clear all 6 debug registers:
1173 static void clear_all_debug_regs(void)
1177 for (i = 0; i < 8; i++) {
1178 /* Ignore db4, db5 */
1179 if ((i == 4) || (i == 5))
1188 * Restore debug regs if using kgdbwait and you have a kernel debugger
1189 * connection established.
1191 static void dbg_restore_debug_regs(void)
1193 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1194 arch_kgdb_ops.correct_hw_break();
1196 #else /* ! CONFIG_KGDB */
1197 #define dbg_restore_debug_regs()
1198 #endif /* ! CONFIG_KGDB */
1201 * cpu_init() initializes state that is per-CPU. Some data is already
1202 * initialized (naturally) in the bootstrap process, such as the GDT
1203 * and IDT. We reload them nevertheless, this function acts as a
1204 * 'CPU state barrier', nothing should get across.
1205 * A lot of state is already set up in PDA init for 64 bit
1207 #ifdef CONFIG_X86_64
1209 void __cpuinit cpu_init(void)
1211 struct orig_ist *oist;
1212 struct task_struct *me;
1213 struct tss_struct *t;
1218 cpu = stack_smp_processor_id();
1219 t = &per_cpu(init_tss, cpu);
1220 oist = &per_cpu(orig_ist, cpu);
1223 if (cpu != 0 && percpu_read(numa_node) == 0 &&
1224 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1225 set_numa_node(early_cpu_to_node(cpu));
1230 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask))
1231 panic("CPU#%d already initialized!\n", cpu);
1233 pr_debug("Initializing CPU#%d\n", cpu);
1235 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1238 * Initialize the per-CPU GDT with the boot GDT,
1239 * and set up the GDT descriptor:
1242 switch_to_new_gdt(cpu);
1245 load_idt((const struct desc_ptr *)&idt_descr);
1247 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1250 wrmsrl(MSR_FS_BASE, 0);
1251 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1259 * set up and load the per-CPU TSS
1261 if (!oist->ist[0]) {
1262 char *estacks = per_cpu(exception_stacks, cpu);
1264 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1265 estacks += exception_stack_sizes[v];
1266 oist->ist[v] = t->x86_tss.ist[v] =
1267 (unsigned long)estacks;
1271 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1274 * <= is required because the CPU will access up to
1275 * 8 bits beyond the end of the IO permission bitmap.
1277 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1278 t->io_bitmap[i] = ~0UL;
1280 atomic_inc(&init_mm.mm_count);
1281 me->active_mm = &init_mm;
1283 enter_lazy_tlb(&init_mm, me);
1285 load_sp0(t, ¤t->thread);
1286 set_tss_desc(cpu, t);
1288 load_mm_ldt(&init_mm);
1290 clear_all_debug_regs();
1291 dbg_restore_debug_regs();
1296 raw_local_save_flags(kernel_eflags);
1304 void __cpuinit cpu_init(void)
1306 int cpu = smp_processor_id();
1307 struct task_struct *curr = current;
1308 struct tss_struct *t = &per_cpu(init_tss, cpu);
1309 struct thread_struct *thread = &curr->thread;
1311 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) {
1312 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1317 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1319 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
1320 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1322 load_idt(&idt_descr);
1323 switch_to_new_gdt(cpu);
1326 * Set up and load the per-CPU TSS and LDT
1328 atomic_inc(&init_mm.mm_count);
1329 curr->active_mm = &init_mm;
1331 enter_lazy_tlb(&init_mm, curr);
1333 load_sp0(t, thread);
1334 set_tss_desc(cpu, t);
1336 load_mm_ldt(&init_mm);
1338 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1340 #ifdef CONFIG_DOUBLEFAULT
1341 /* Set up doublefault TSS pointer in the GDT */
1342 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1345 clear_all_debug_regs();
1346 dbg_restore_debug_regs();