arch/x86/kernel/apic/x2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved.
   9  */
  10 #include <linux/cpumask.h>
  11 #include <linux/hardirq.h>
  12 #include <linux/proc_fs.h>
  13 #include <linux/threads.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/string.h>
  17 #include <linux/ctype.h>
  18 #include <linux/sched.h>
  19 #include <linux/timer.h>
  20 #include <linux/slab.h>
  21 #include <linux/cpu.h>
  22 #include <linux/init.h>
  23 #include <linux/io.h>
  24 #include <linux/pci.h>
  25 #include <linux/kdebug.h>
  26
  27 #include <asm/uv/uv_mmrs.h>
  28 #include <asm/uv/uv_hub.h>
  29 #include <asm/current.h>
  30 #include <asm/pgtable.h>
  31 #include <asm/uv/bios.h>
  32 #include <asm/uv/uv.h>
  33 #include <asm/apic.h>
  34 #include <asm/ipi.h>
  35 #include <asm/smp.h>
  36 #include <asm/x86_init.h>
  37
  38 DEFINE_PER_CPU(int, x2apic_extra_bits);
  39
  40 #define PR_DEVEL(fmt, args...)  pr_devel("%s: " fmt, __func__, args)
  41
  42 static enum uv_system_type uv_system_type;
  43 static u64 gru_start_paddr, gru_end_paddr;
  44 static union uvh_apicid uvh_apicid;
  45 int uv_min_hub_revision_id;
  46 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
  47 static DEFINE_SPINLOCK(uv_nmi_lock);
  48
  49 static inline bool is_GRU_range(u64 start, u64 end)
  50 {
  51         return start >= gru_start_paddr && end <= gru_end_paddr;
  52 }
  53
  54 static bool uv_is_untracked_pat_range(u64 start, u64 end)
  55 {
  56         return is_ISA_range(start, end) || is_GRU_range(start, end);
  57 }
  58
  59 static int early_get_nodeid(void)
  60 {
  61         union uvh_node_id_u node_id;
  62         unsigned long *mmr;
  63
  64         mmr = early_ioremap(UV_LOCAL_MMR_BASE | UVH_NODE_ID, sizeof(*mmr));
  65         node_id.v = *mmr;
  66         early_iounmap(mmr, sizeof(*mmr));
  67
  68         /* Currently, all blades have same revision number */
  69         uv_min_hub_revision_id = node_id.s.revision;
  70
  71         return node_id.s.node_id;
  72 }
  73
  74 static void __init early_get_apic_pnode_shift(void)
  75 {
  76         unsigned long *mmr;
  77
  78         mmr = early_ioremap(UV_LOCAL_MMR_BASE | UVH_APICID, sizeof(*mmr));
  79         uvh_apicid.v = *mmr;
  80         early_iounmap(mmr, sizeof(*mmr));
  81         if (!uvh_apicid.v)
  82                 /*
  83                  * Old bios, use default value
  84                  */
  85                 uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT;
  86 }
  87
  88 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
  89 {
  90         int nodeid;
  91
  92         if (!strcmp(oem_id, "SGI")) {
  93                 nodeid = early_get_nodeid();
  94                 early_get_apic_pnode_shift();
  95                 x86_platform.is_untracked_pat_range =  uv_is_untracked_pat_range;
  96                 x86_platform.nmi_init = uv_nmi_init;
  97                 if (!strcmp(oem_table_id, "UVL"))
  98                         uv_system_type = UV_LEGACY_APIC;
  99                 else if (!strcmp(oem_table_id, "UVX"))
 100                         uv_system_type = UV_X2APIC;
 101                 else if (!strcmp(oem_table_id, "UVH")) {
 102                         __get_cpu_var(x2apic_extra_bits) =
 103                                 nodeid << (uvh_apicid.s.pnode_shift - 1);
 104                         uv_system_type = UV_NON_UNIQUE_APIC;
 105                         return 1;
 106                 }
 107         }
 108         return 0;
 109 }
 110
 111 enum uv_system_type get_uv_system_type(void)
 112 {
 113         return uv_system_type;
 114 }
 115
 116 int is_uv_system(void)
 117 {
 118         return uv_system_type != UV_NONE;
 119 }
 120 EXPORT_SYMBOL_GPL(is_uv_system);
 121
 122 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
 123 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
 124
 125 struct uv_blade_info *uv_blade_info;
 126 EXPORT_SYMBOL_GPL(uv_blade_info);
 127
 128 short *uv_node_to_blade;
 129 EXPORT_SYMBOL_GPL(uv_node_to_blade);
 130
 131 short *uv_cpu_to_blade;
 132 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
 133
 134 short uv_possible_blades;
 135 EXPORT_SYMBOL_GPL(uv_possible_blades);
 136
 137 unsigned long sn_rtc_cycles_per_second;
 138 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
 139
 140 static const struct cpumask *uv_target_cpus(void)
 141 {
 142         return cpu_online_mask;
 143 }
 144
 145 static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
 146 {
 147         cpumask_clear(retmask);
 148         cpumask_set_cpu(cpu, retmask);
 149 }
 150
 151 static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 152 {
 153 #ifdef CONFIG_SMP
 154         unsigned long val;
 155         int pnode;
 156
 157         pnode = uv_apicid_to_pnode(phys_apicid);
 158         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 159             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 160             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 161             APIC_DM_INIT;
 162         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 163         mdelay(10);
 164
 165         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 166             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 167             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 168             APIC_DM_STARTUP;
 169         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 170
 171         atomic_set(&init_deasserted, 1);
 172 #endif
 173         return 0;
 174 }
 175
 176 static void uv_send_IPI_one(int cpu, int vector)
 177 {
 178         unsigned long apicid;
 179         int pnode;
 180
 181         apicid = per_cpu(x86_cpu_to_apicid, cpu);
 182         pnode = uv_apicid_to_pnode(apicid);
 183         uv_hub_send_ipi(pnode, apicid, vector);
 184 }
 185
 186 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
 187 {
 188         unsigned int cpu;
 189
 190         for_each_cpu(cpu, mask)
 191                 uv_send_IPI_one(cpu, vector);
 192 }
 193
 194 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 195 {
 196         unsigned int this_cpu = smp_processor_id();
 197         unsigned int cpu;
 198
 199         for_each_cpu(cpu, mask) {
 200                 if (cpu != this_cpu)
 201                         uv_send_IPI_one(cpu, vector);
 202         }
 203 }
 204
 205 static void uv_send_IPI_allbutself(int vector)
 206 {
 207         unsigned int this_cpu = smp_processor_id();
 208         unsigned int cpu;
 209
 210         for_each_online_cpu(cpu) {
 211                 if (cpu != this_cpu)
 212                         uv_send_IPI_one(cpu, vector);
 213         }
 214 }
 215
 216 static void uv_send_IPI_all(int vector)
 217 {
 218         uv_send_IPI_mask(cpu_online_mask, vector);
 219 }
 220
 221 static int uv_apic_id_registered(void)
 222 {
 223         return 1;
 224 }
 225
 226 static void uv_init_apic_ldr(void)
 227 {
 228 }
 229
 230 static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
 231 {
 232         /*
 233          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 234          * May as well be the first.
 235          */
 236         int cpu = cpumask_first(cpumask);
 237
 238         if ((unsigned)cpu < nr_cpu_ids)
 239                 return per_cpu(x86_cpu_to_apicid, cpu);
 240         else
 241                 return BAD_APICID;
 242 }
 243
 244 static unsigned int
 245 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 246                           const struct cpumask *andmask)
 247 {
 248         int cpu;
 249
 250         /*
 251          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 252          * May as well be the first.
 253          */
 254         for_each_cpu_and(cpu, cpumask, andmask) {
 255                 if (cpumask_test_cpu(cpu, cpu_online_mask))
 256                         break;
 257         }
 258         return per_cpu(x86_cpu_to_apicid, cpu);
 259 }
 260
 261 static unsigned int x2apic_get_apic_id(unsigned long x)
 262 {
 263         unsigned int id;
 264
 265         WARN_ON(preemptible() && num_online_cpus() > 1);
 266         id = x | __get_cpu_var(x2apic_extra_bits);
 267
 268         return id;
 269 }
 270
 271 static unsigned long set_apic_id(unsigned int id)
 272 {
 273         unsigned long x;
 274
 275         /* maskout x2apic_extra_bits ? */
 276         x = id;
 277         return x;
 278 }
 279
 280 static unsigned int uv_read_apic_id(void)
 281 {
 282
 283         return x2apic_get_apic_id(apic_read(APIC_ID));
 284 }
 285
 286 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
 287 {
 288         return uv_read_apic_id() >> index_msb;
 289 }
 290
 291 static void uv_send_IPI_self(int vector)
 292 {
 293         apic_write(APIC_SELF_IPI, vector);
 294 }
 295
 296 struct apic __refdata apic_x2apic_uv_x = {
 297
 298         .name                           = "UV large system",
 299         .probe                          = NULL,
 300         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
 301         .apic_id_registered             = uv_apic_id_registered,
 302
 303         .irq_delivery_mode              = dest_Fixed,
 304         .irq_dest_mode                  = 0, /* physical */
 305
 306         .target_cpus                    = uv_target_cpus,
 307         .disable_esr                    = 0,
 308         .dest_logical                   = APIC_DEST_LOGICAL,
 309         .check_apicid_used              = NULL,
 310         .check_apicid_present           = NULL,
 311
 312         .vector_allocation_domain       = uv_vector_allocation_domain,
 313         .init_apic_ldr                  = uv_init_apic_ldr,
 314
 315         .ioapic_phys_id_map             = NULL,
 316         .setup_apic_routing             = NULL,
 317         .multi_timer_check              = NULL,
 318         .apicid_to_node                 = NULL,
 319         .cpu_to_logical_apicid          = NULL,
 320         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 321         .apicid_to_cpu_present          = NULL,
 322         .setup_portio_remap             = NULL,
 323         .check_phys_apicid_present      = default_check_phys_apicid_present,
 324         .enable_apic_mode               = NULL,
 325         .phys_pkg_id                    = uv_phys_pkg_id,
 326         .mps_oem_check                  = NULL,
 327
 328         .get_apic_id                    = x2apic_get_apic_id,
 329         .set_apic_id                    = set_apic_id,
 330         .apic_id_mask                   = 0xFFFFFFFFu,
 331
 332         .cpu_mask_to_apicid             = uv_cpu_mask_to_apicid,
 333         .cpu_mask_to_apicid_and         = uv_cpu_mask_to_apicid_and,
 334
 335         .send_IPI_mask                  = uv_send_IPI_mask,
 336         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
 337         .send_IPI_allbutself            = uv_send_IPI_allbutself,
 338         .send_IPI_all                   = uv_send_IPI_all,
 339         .send_IPI_self                  = uv_send_IPI_self,
 340
 341         .wakeup_secondary_cpu           = uv_wakeup_secondary,
 342         .trampoline_phys_low            = DEFAULT_TRAMPOLINE_PHYS_LOW,
 343         .trampoline_phys_high           = DEFAULT_TRAMPOLINE_PHYS_HIGH,
 344         .wait_for_init_deassert         = NULL,
 345         .smp_callin_clear_local_apic    = NULL,
 346         .inquire_remote_apic            = NULL,
 347
 348         .read                           = native_apic_msr_read,
 349         .write                          = native_apic_msr_write,
 350         .icr_read                       = native_x2apic_icr_read,
 351         .icr_write                      = native_x2apic_icr_write,
 352         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
 353         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
 354 };
 355
 356 static __cpuinit void set_x2apic_extra_bits(int pnode)
 357 {
 358         __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
 359 }
 360
 361 /*
 362  * Called on boot cpu.
 363  */
 364 static __init int boot_pnode_to_blade(int pnode)
 365 {
 366         int blade;
 367
 368         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 369                 if (pnode == uv_blade_info[blade].pnode)
 370                         return blade;
 371         BUG();
 372 }
 373
 374 struct redir_addr {
 375         unsigned long redirect;
 376         unsigned long alias;
 377 };
 378
 379 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 380
 381 static __initdata struct redir_addr redir_addrs[] = {
 382         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
 383         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
 384         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
 385 };
 386
 387 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 388 {
 389         union uvh_si_alias0_overlay_config_u alias;
 390         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 391         int i;
 392
 393         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
 394                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
 395                 if (alias.s.enable && alias.s.base == 0) {
 396                         *size = (1UL << alias.s.m_alias);
 397                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
 398                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 399                         return;
 400                 }
 401         }
 402         *base = *size = 0;
 403 }
 404
 405 enum map_type {map_wb, map_uc};
 406
 407 static __init void map_high(char *id, unsigned long base, int pshift,
 408                         int bshift, int max_pnode, enum map_type map_type)
 409 {
 410         unsigned long bytes, paddr;
 411
 412         paddr = base << pshift;
 413         bytes = (1UL << bshift) * (max_pnode + 1);
 414         printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
 415                                                 paddr + bytes);
 416         if (map_type == map_uc)
 417                 init_extra_mapping_uc(paddr, bytes);
 418         else
 419                 init_extra_mapping_wb(paddr, bytes);
 420
 421 }
 422 static __init void map_gru_high(int max_pnode)
 423 {
 424         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 425         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 426
 427         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 428         if (gru.s.enable) {
 429                 map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
 430                 gru_start_paddr = ((u64)gru.s.base << shift);
 431                 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
 432
 433         }
 434 }
 435
 436 static __init void map_mmr_high(int max_pnode)
 437 {
 438         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 439         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 440
 441         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 442         if (mmr.s.enable)
 443                 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
 444 }
 445
 446 static __init void map_mmioh_high(int max_pnode)
 447 {
 448         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 449         int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 450
 451         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
 452         if (mmioh.s.enable)
 453                 map_high("MMIOH", mmioh.s.base, shift, mmioh.s.m_io,
 454                         max_pnode, map_uc);
 455 }
 456
 457 static __init void map_low_mmrs(void)
 458 {
 459         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 460         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 461 }
 462
 463 static __init void uv_rtc_init(void)
 464 {
 465         long status;
 466         u64 ticks_per_sec;
 467
 468         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
 469                                         &ticks_per_sec);
 470         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
 471                 printk(KERN_WARNING
 472                         "unable to determine platform RTC clock frequency, "
 473                         "guessing.\n");
 474                 /* BIOS gives wrong value for clock freq. so guess */
 475                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 476         } else
 477                 sn_rtc_cycles_per_second = ticks_per_sec;
 478 }
 479
 480 /*
 481  * percpu heartbeat timer
 482  */
 483 static void uv_heartbeat(unsigned long ignored)
 484 {
 485         struct timer_list *timer = &uv_hub_info->scir.timer;
 486         unsigned char bits = uv_hub_info->scir.state;
 487
 488         /* flip heartbeat bit */
 489         bits ^= SCIR_CPU_HEARTBEAT;
 490
 491         /* is this cpu idle? */
 492         if (idle_cpu(raw_smp_processor_id()))
 493                 bits &= ~SCIR_CPU_ACTIVITY;
 494         else
 495                 bits |= SCIR_CPU_ACTIVITY;
 496
 497         /* update system controller interface reg */
 498         uv_set_scir_bits(bits);
 499
 500         /* enable next timer period */
 501         mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
 502 }
 503
 504 static void __cpuinit uv_heartbeat_enable(int cpu)
 505 {
 506         while (!uv_cpu_hub_info(cpu)->scir.enabled) {
 507                 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
 508
 509                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
 510                 setup_timer(timer, uv_heartbeat, cpu);
 511                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
 512                 add_timer_on(timer, cpu);
 513                 uv_cpu_hub_info(cpu)->scir.enabled = 1;
 514
 515                 /* also ensure that boot cpu is enabled */
 516                 cpu = 0;
 517         }
 518 }
 519
 520 #ifdef CONFIG_HOTPLUG_CPU
 521 static void __cpuinit uv_heartbeat_disable(int cpu)
 522 {
 523         if (uv_cpu_hub_info(cpu)->scir.enabled) {
 524                 uv_cpu_hub_info(cpu)->scir.enabled = 0;
 525                 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
 526         }
 527         uv_set_cpu_scir_bits(cpu, 0xff);
 528 }
 529
 530 /*
 531  * cpu hotplug notifier
 532  */
 533 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
 534                                        unsigned long action, void *hcpu)
 535 {
 536         long cpu = (long)hcpu;
 537
 538         switch (action) {
 539         case CPU_ONLINE:
 540                 uv_heartbeat_enable(cpu);
 541                 break;
 542         case CPU_DOWN_PREPARE:
 543                 uv_heartbeat_disable(cpu);
 544                 break;
 545         default:
 546                 break;
 547         }
 548         return NOTIFY_OK;
 549 }
 550
 551 static __init void uv_scir_register_cpu_notifier(void)
 552 {
 553         hotcpu_notifier(uv_scir_cpu_notify, 0);
 554 }
 555
 556 #else /* !CONFIG_HOTPLUG_CPU */
 557
 558 static __init void uv_scir_register_cpu_notifier(void)
 559 {
 560 }
 561
 562 static __init int uv_init_heartbeat(void)
 563 {
 564         int cpu;
 565
 566         if (is_uv_system())
 567                 for_each_online_cpu(cpu)
 568                         uv_heartbeat_enable(cpu);
 569         return 0;
 570 }
 571
 572 late_initcall(uv_init_heartbeat);
 573
 574 #endif /* !CONFIG_HOTPLUG_CPU */
 575
 576 /* Direct Legacy VGA I/O traffic to designated IOH */
 577 int uv_set_vga_state(struct pci_dev *pdev, bool decode,
 578                       unsigned int command_bits, bool change_bridge)
 579 {
 580         int domain, bus, rc;
 581
 582         PR_DEVEL("devfn %x decode %d cmd %x chg_brdg %d\n",
 583                         pdev->devfn, decode, command_bits, change_bridge);
 584
 585         if (!change_bridge)
 586                 return 0;
 587
 588         if ((command_bits & PCI_COMMAND_IO) == 0)
 589                 return 0;
 590
 591         domain = pci_domain_nr(pdev->bus);
 592         bus = pdev->bus->number;
 593
 594         rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
 595         PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
 596
 597         return rc;
 598 }
 599
 600 /*
 601  * Called on each cpu to initialize the per_cpu UV data area.
 602  * FIXME: hotplug not supported yet
 603  */
 604 void __cpuinit uv_cpu_init(void)
 605 {
 606         /* CPU 0 initilization will be done via uv_system_init. */
 607         if (!uv_blade_info)
 608                 return;
 609
 610         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 611
 612         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
 613                 set_x2apic_extra_bits(uv_hub_info->pnode);
 614 }
 615
 616 /*
 617  * When NMI is received, print a stack trace.
 618  */
 619 int uv_handle_nmi(struct notifier_block *self, unsigned long reason, void *data)
 620 {
 621         if (reason != DIE_NMI_IPI)
 622                 return NOTIFY_OK;
 623
 624         if (in_crash_kexec)
 625                 /* do nothing if entering the crash kernel */
 626                 return NOTIFY_OK;
 627         /*
 628          * Use a lock so only one cpu prints at a time
 629          * to prevent intermixed output.
 630          */
 631         spin_lock(&uv_nmi_lock);
 632         pr_info("NMI stack dump cpu %u:\n", smp_processor_id());
 633         dump_stack();
 634         spin_unlock(&uv_nmi_lock);
 635
 636         return NOTIFY_STOP;
 637 }
 638
 639 static struct notifier_block uv_dump_stack_nmi_nb = {
 640         .notifier_call  = uv_handle_nmi
 641 };
 642
 643 void uv_register_nmi_notifier(void)
 644 {
 645         if (register_die_notifier(&uv_dump_stack_nmi_nb))
 646                 printk(KERN_WARNING "UV NMI handler failed to register\n");
 647 }
 648
 649 void uv_nmi_init(void)
 650 {
 651         unsigned int value;
 652
 653         /*
 654          * Unmask NMI on all cpus
 655          */
 656         value = apic_read(APIC_LVT1) | APIC_DM_NMI;
 657         value &= ~APIC_LVT_MASKED;
 658         apic_write(APIC_LVT1, value);
 659 }
 660
 661 void __init uv_system_init(void)
 662 {
 663         union uvh_si_addr_map_config_u m_n_config;
 664         union uvh_node_id_u node_id;
 665         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
 666         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
 667         int gnode_extra, max_pnode = 0;
 668         unsigned long mmr_base, present, paddr;
 669         unsigned short pnode_mask;
 670
 671         map_low_mmrs();
 672
 673         m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
 674         m_val = m_n_config.s.m_skt;
 675         n_val = m_n_config.s.n_skt;
 676         mmr_base =
 677             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
 678             ~UV_MMR_ENABLE;
 679         pnode_mask = (1 << n_val) - 1;
 680         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
 681         gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
 682         gnode_upper = ((unsigned long)gnode_extra  << m_val);
 683         printk(KERN_DEBUG "UV: N %d, M %d, gnode_upper 0x%lx, gnode_extra 0x%x\n",
 684                         n_val, m_val, gnode_upper, gnode_extra);
 685
 686         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
 687
 688         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
 689                 uv_possible_blades +=
 690                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
 691         printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
 692
 693         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
 694         uv_blade_info = kmalloc(bytes, GFP_KERNEL);
 695         BUG_ON(!uv_blade_info);
 696         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 697                 uv_blade_info[blade].memory_nid = -1;
 698
 699         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
 700
 701         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
 702         uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
 703         BUG_ON(!uv_node_to_blade);
 704         memset(uv_node_to_blade, 255, bytes);
 705
 706         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
 707         uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
 708         BUG_ON(!uv_cpu_to_blade);
 709         memset(uv_cpu_to_blade, 255, bytes);
 710
 711         blade = 0;
 712         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
 713                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
 714                 for (j = 0; j < 64; j++) {
 715                         if (!test_bit(j, &present))
 716                                 continue;
 717                         pnode = (i * 64 + j);
 718                         uv_blade_info[blade].pnode = pnode;
 719                         uv_blade_info[blade].nr_possible_cpus = 0;
 720                         uv_blade_info[blade].nr_online_cpus = 0;
 721                         max_pnode = max(pnode, max_pnode);
 722                         blade++;
 723                 }
 724         }
 725
 726         uv_bios_init();
 727         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
 728                             &sn_region_size, &system_serial_number);
 729         uv_rtc_init();
 730
 731         for_each_present_cpu(cpu) {
 732                 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
 733
 734                 nid = cpu_to_node(cpu);
 735                 /*
 736                  * apic_pnode_shift must be set before calling uv_apicid_to_pnode();
 737                  */
 738                 uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
 739                 pnode = uv_apicid_to_pnode(apicid);
 740                 blade = boot_pnode_to_blade(pnode);
 741                 lcpu = uv_blade_info[blade].nr_possible_cpus;
 742                 uv_blade_info[blade].nr_possible_cpus++;
 743
 744                 /* Any node on the blade, else will contain -1. */
 745                 uv_blade_info[blade].memory_nid = nid;
 746
 747                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
 748                 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
 749                 uv_cpu_hub_info(cpu)->m_val = m_val;
 750                 uv_cpu_hub_info(cpu)->n_val = n_val;
 751                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
 752                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
 753                 uv_cpu_hub_info(cpu)->pnode = pnode;
 754                 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
 755                 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
 756                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
 757                 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
 758                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
 759                 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
 760                 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
 761                 uv_node_to_blade[nid] = blade;
 762                 uv_cpu_to_blade[cpu] = blade;
 763         }
 764
 765         /* Add blade/pnode info for nodes without cpus */
 766         for_each_online_node(nid) {
 767                 if (uv_node_to_blade[nid] >= 0)
 768                         continue;
 769                 paddr = node_start_pfn(nid) << PAGE_SHIFT;
 770                 paddr = uv_soc_phys_ram_to_gpa(paddr);
 771                 pnode = (paddr >> m_val) & pnode_mask;
 772                 blade = boot_pnode_to_blade(pnode);
 773                 uv_node_to_blade[nid] = blade;
 774         }
 775
 776         map_gru_high(max_pnode);
 777         map_mmr_high(max_pnode);
 778         map_mmioh_high(max_pnode);
 779
 780         uv_cpu_init();
 781         uv_scir_register_cpu_notifier();
 782         uv_register_nmi_notifier();
 783         proc_mkdir("sgi_uv", NULL);
 784
 785         /* register Legacy VGA I/O redirection handler */
 786         pci_register_set_vga_state(uv_set_vga_state);
 787 }