2 * Copyright (C) 2007-2009 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/gfp.h>
23 #include <linux/list.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <asm/pci-direct.h>
28 #include <asm/amd_iommu_proto.h>
29 #include <asm/amd_iommu_types.h>
30 #include <asm/amd_iommu.h>
31 #include <asm/iommu.h>
33 #include <asm/x86_init.h>
36 * definitions for the ACPI scanning code
38 #define IVRS_HEADER_LENGTH 48
40 #define ACPI_IVHD_TYPE 0x10
41 #define ACPI_IVMD_TYPE_ALL 0x20
42 #define ACPI_IVMD_TYPE 0x21
43 #define ACPI_IVMD_TYPE_RANGE 0x22
45 #define IVHD_DEV_ALL 0x01
46 #define IVHD_DEV_SELECT 0x02
47 #define IVHD_DEV_SELECT_RANGE_START 0x03
48 #define IVHD_DEV_RANGE_END 0x04
49 #define IVHD_DEV_ALIAS 0x42
50 #define IVHD_DEV_ALIAS_RANGE 0x43
51 #define IVHD_DEV_EXT_SELECT 0x46
52 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
54 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
55 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
56 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
57 #define IVHD_FLAG_ISOC_EN_MASK 0x08
59 #define IVMD_FLAG_EXCL_RANGE 0x08
60 #define IVMD_FLAG_UNITY_MAP 0x01
62 #define ACPI_DEVFLAG_INITPASS 0x01
63 #define ACPI_DEVFLAG_EXTINT 0x02
64 #define ACPI_DEVFLAG_NMI 0x04
65 #define ACPI_DEVFLAG_SYSMGT1 0x10
66 #define ACPI_DEVFLAG_SYSMGT2 0x20
67 #define ACPI_DEVFLAG_LINT0 0x40
68 #define ACPI_DEVFLAG_LINT1 0x80
69 #define ACPI_DEVFLAG_ATSDIS 0x10000000
72 * ACPI table definitions
74 * These data structures are laid over the table to parse the important values
79 * structure describing one IOMMU in the ACPI table. Typically followed by one
80 * or more ivhd_entrys.
92 } __attribute__((packed));
95 * A device entry describing which devices a specific IOMMU translates and
96 * which requestor ids they use.
103 } __attribute__((packed));
106 * An AMD IOMMU memory definition structure. It defines things like exclusion
107 * ranges for devices and regions that should be unity mapped.
118 } __attribute__((packed));
122 static int __initdata amd_iommu_detected;
124 u16 amd_iommu_last_bdf; /* largest PCI device id we have
126 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
128 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
130 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
133 /* Array to assign indices to IOMMUs*/
134 struct amd_iommu *amd_iommus[MAX_IOMMUS];
135 int amd_iommus_present;
137 /* IOMMUs have a non-present cache? */
138 bool amd_iommu_np_cache __read_mostly;
141 * The ACPI table parsing functions set this variable on an error
143 static int __initdata amd_iommu_init_err;
146 * List of protection domains - used during resume
148 LIST_HEAD(amd_iommu_pd_list);
149 spinlock_t amd_iommu_pd_lock;
152 * Pointer to the device table which is shared by all AMD IOMMUs
153 * it is indexed by the PCI device id or the HT unit id and contains
154 * information about the domain the device belongs to as well as the
155 * page table root pointer.
157 struct dev_table_entry *amd_iommu_dev_table;
160 * The alias table is a driver specific data structure which contains the
161 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
162 * More than one device can share the same requestor id.
164 u16 *amd_iommu_alias_table;
167 * The rlookup table is used to find the IOMMU which is responsible
168 * for a specific device. It is also indexed by the PCI device id.
170 struct amd_iommu **amd_iommu_rlookup_table;
173 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
174 * to know which ones are already in use.
176 unsigned long *amd_iommu_pd_alloc_bitmap;
178 static u32 dev_table_size; /* size of the device table */
179 static u32 alias_table_size; /* size of the alias table */
180 static u32 rlookup_table_size; /* size if the rlookup table */
182 static inline void update_last_devid(u16 devid)
184 if (devid > amd_iommu_last_bdf)
185 amd_iommu_last_bdf = devid;
188 static inline unsigned long tbl_size(int entry_size)
190 unsigned shift = PAGE_SHIFT +
191 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
196 /****************************************************************************
198 * AMD IOMMU MMIO register space handling functions
200 * These functions are used to program the IOMMU device registers in
201 * MMIO space required for that driver.
203 ****************************************************************************/
206 * This function set the exclusion range in the IOMMU. DMA accesses to the
207 * exclusion range are passed through untranslated
209 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
211 u64 start = iommu->exclusion_start & PAGE_MASK;
212 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
215 if (!iommu->exclusion_start)
218 entry = start | MMIO_EXCL_ENABLE_MASK;
219 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
220 &entry, sizeof(entry));
223 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
224 &entry, sizeof(entry));
227 /* Programs the physical address of the device table into the IOMMU hardware */
228 static void __init iommu_set_device_table(struct amd_iommu *iommu)
232 BUG_ON(iommu->mmio_base == NULL);
234 entry = virt_to_phys(amd_iommu_dev_table);
235 entry |= (dev_table_size >> 12) - 1;
236 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
237 &entry, sizeof(entry));
240 /* Generic functions to enable/disable certain features of the IOMMU. */
241 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
245 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
247 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
250 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
254 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
256 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
259 /* Function to enable the hardware */
260 static void iommu_enable(struct amd_iommu *iommu)
262 printk(KERN_INFO "AMD-Vi: Enabling IOMMU at %s cap 0x%hx\n",
263 dev_name(&iommu->dev->dev), iommu->cap_ptr);
265 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
268 static void iommu_disable(struct amd_iommu *iommu)
270 /* Disable command buffer */
271 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
273 /* Disable event logging and event interrupts */
274 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
275 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
277 /* Disable IOMMU hardware itself */
278 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
282 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
283 * the system has one.
285 static u8 * __init iommu_map_mmio_space(u64 address)
289 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu"))
292 ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
296 release_mem_region(address, MMIO_REGION_LENGTH);
301 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
303 if (iommu->mmio_base)
304 iounmap(iommu->mmio_base);
305 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
308 /****************************************************************************
310 * The functions below belong to the first pass of AMD IOMMU ACPI table
311 * parsing. In this pass we try to find out the highest device id this
312 * code has to handle. Upon this information the size of the shared data
313 * structures is determined later.
315 ****************************************************************************/
318 * This function calculates the length of a given IVHD entry
320 static inline int ivhd_entry_length(u8 *ivhd)
322 return 0x04 << (*ivhd >> 6);
326 * This function reads the last device id the IOMMU has to handle from the PCI
327 * capability header for this IOMMU
329 static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
333 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
334 update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
340 * After reading the highest device id from the IOMMU PCI capability header
341 * this function looks if there is a higher device id defined in the ACPI table
343 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
345 u8 *p = (void *)h, *end = (void *)h;
346 struct ivhd_entry *dev;
351 find_last_devid_on_pci(PCI_BUS(h->devid),
357 dev = (struct ivhd_entry *)p;
359 case IVHD_DEV_SELECT:
360 case IVHD_DEV_RANGE_END:
362 case IVHD_DEV_EXT_SELECT:
363 /* all the above subfield types refer to device ids */
364 update_last_devid(dev->devid);
369 p += ivhd_entry_length(p);
378 * Iterate over all IVHD entries in the ACPI table and find the highest device
379 * id which we need to handle. This is the first of three functions which parse
380 * the ACPI table. So we check the checksum here.
382 static int __init find_last_devid_acpi(struct acpi_table_header *table)
385 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
386 struct ivhd_header *h;
389 * Validate checksum here so we don't need to do it when
390 * we actually parse the table
392 for (i = 0; i < table->length; ++i)
395 /* ACPI table corrupt */
396 amd_iommu_init_err = -ENODEV;
400 p += IVRS_HEADER_LENGTH;
402 end += table->length;
404 h = (struct ivhd_header *)p;
407 find_last_devid_from_ivhd(h);
419 /****************************************************************************
421 * The following functions belong the the code path which parses the ACPI table
422 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
423 * data structures, initialize the device/alias/rlookup table and also
424 * basically initialize the hardware.
426 ****************************************************************************/
429 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
430 * write commands to that buffer later and the IOMMU will execute them
433 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
435 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
436 get_order(CMD_BUFFER_SIZE));
441 iommu->cmd_buf_size = CMD_BUFFER_SIZE;
447 * This function resets the command buffer if the IOMMU stopped fetching
450 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
452 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
454 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
455 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
457 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
461 * This function writes the command buffer address to the hardware and
464 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
468 BUG_ON(iommu->cmd_buf == NULL);
470 entry = (u64)virt_to_phys(iommu->cmd_buf);
471 entry |= MMIO_CMD_SIZE_512;
473 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
474 &entry, sizeof(entry));
476 amd_iommu_reset_cmd_buffer(iommu);
479 static void __init free_command_buffer(struct amd_iommu *iommu)
481 free_pages((unsigned long)iommu->cmd_buf,
482 get_order(iommu->cmd_buf_size));
485 /* allocates the memory where the IOMMU will log its events to */
486 static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
488 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
489 get_order(EVT_BUFFER_SIZE));
491 if (iommu->evt_buf == NULL)
494 iommu->evt_buf_size = EVT_BUFFER_SIZE;
496 return iommu->evt_buf;
499 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
503 BUG_ON(iommu->evt_buf == NULL);
505 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
507 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
508 &entry, sizeof(entry));
510 /* set head and tail to zero manually */
511 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
512 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
514 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
517 static void __init free_event_buffer(struct amd_iommu *iommu)
519 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
522 /* sets a specific bit in the device table entry. */
523 static void set_dev_entry_bit(u16 devid, u8 bit)
525 int i = (bit >> 5) & 0x07;
526 int _bit = bit & 0x1f;
528 amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
531 static int get_dev_entry_bit(u16 devid, u8 bit)
533 int i = (bit >> 5) & 0x07;
534 int _bit = bit & 0x1f;
536 return (amd_iommu_dev_table[devid].data[i] & (1 << _bit)) >> _bit;
540 void amd_iommu_apply_erratum_63(u16 devid)
544 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
545 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
548 set_dev_entry_bit(devid, DEV_ENTRY_IW);
551 /* Writes the specific IOMMU for a device into the rlookup table */
552 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
554 amd_iommu_rlookup_table[devid] = iommu;
558 * This function takes the device specific flags read from the ACPI
559 * table and sets up the device table entry with that information
561 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
562 u16 devid, u32 flags, u32 ext_flags)
564 if (flags & ACPI_DEVFLAG_INITPASS)
565 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
566 if (flags & ACPI_DEVFLAG_EXTINT)
567 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
568 if (flags & ACPI_DEVFLAG_NMI)
569 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
570 if (flags & ACPI_DEVFLAG_SYSMGT1)
571 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
572 if (flags & ACPI_DEVFLAG_SYSMGT2)
573 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
574 if (flags & ACPI_DEVFLAG_LINT0)
575 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
576 if (flags & ACPI_DEVFLAG_LINT1)
577 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
579 amd_iommu_apply_erratum_63(devid);
581 set_iommu_for_device(iommu, devid);
585 * Reads the device exclusion range from ACPI and initialize IOMMU with
588 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
590 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
592 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
597 * We only can configure exclusion ranges per IOMMU, not
598 * per device. But we can enable the exclusion range per
599 * device. This is done here
601 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
602 iommu->exclusion_start = m->range_start;
603 iommu->exclusion_length = m->range_length;
608 * This function reads some important data from the IOMMU PCI space and
609 * initializes the driver data structure with it. It reads the hardware
610 * capabilities and the first/last device entries
612 static void __init init_iommu_from_pci(struct amd_iommu *iommu)
614 int cap_ptr = iommu->cap_ptr;
617 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
619 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
621 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
624 iommu->first_device = calc_devid(MMIO_GET_BUS(range),
626 iommu->last_device = calc_devid(MMIO_GET_BUS(range),
628 iommu->evt_msi_num = MMIO_MSI_NUM(misc);
632 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
633 * initializes the hardware and our data structures with it.
635 static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
636 struct ivhd_header *h)
639 u8 *end = p, flags = 0;
640 u16 dev_i, devid = 0, devid_start = 0, devid_to = 0;
643 struct ivhd_entry *e;
646 * First set the recommended feature enable bits from ACPI
647 * into the IOMMU control registers
649 h->flags & IVHD_FLAG_HT_TUN_EN_MASK ?
650 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
651 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
653 h->flags & IVHD_FLAG_PASSPW_EN_MASK ?
654 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
655 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
657 h->flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
658 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
659 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
661 h->flags & IVHD_FLAG_ISOC_EN_MASK ?
662 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
663 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
666 * make IOMMU memory accesses cache coherent
668 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
671 * Done. Now parse the device entries
673 p += sizeof(struct ivhd_header);
678 e = (struct ivhd_entry *)p;
682 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
683 " last device %02x:%02x.%x flags: %02x\n",
684 PCI_BUS(iommu->first_device),
685 PCI_SLOT(iommu->first_device),
686 PCI_FUNC(iommu->first_device),
687 PCI_BUS(iommu->last_device),
688 PCI_SLOT(iommu->last_device),
689 PCI_FUNC(iommu->last_device),
692 for (dev_i = iommu->first_device;
693 dev_i <= iommu->last_device; ++dev_i)
694 set_dev_entry_from_acpi(iommu, dev_i,
697 case IVHD_DEV_SELECT:
699 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
707 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
709 case IVHD_DEV_SELECT_RANGE_START:
711 DUMP_printk(" DEV_SELECT_RANGE_START\t "
712 "devid: %02x:%02x.%x flags: %02x\n",
718 devid_start = e->devid;
725 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
726 "flags: %02x devid_to: %02x:%02x.%x\n",
731 PCI_BUS(e->ext >> 8),
732 PCI_SLOT(e->ext >> 8),
733 PCI_FUNC(e->ext >> 8));
736 devid_to = e->ext >> 8;
737 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
738 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
739 amd_iommu_alias_table[devid] = devid_to;
741 case IVHD_DEV_ALIAS_RANGE:
743 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
744 "devid: %02x:%02x.%x flags: %02x "
745 "devid_to: %02x:%02x.%x\n",
750 PCI_BUS(e->ext >> 8),
751 PCI_SLOT(e->ext >> 8),
752 PCI_FUNC(e->ext >> 8));
754 devid_start = e->devid;
756 devid_to = e->ext >> 8;
760 case IVHD_DEV_EXT_SELECT:
762 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
763 "flags: %02x ext: %08x\n",
770 set_dev_entry_from_acpi(iommu, devid, e->flags,
773 case IVHD_DEV_EXT_SELECT_RANGE:
775 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
776 "%02x:%02x.%x flags: %02x ext: %08x\n",
782 devid_start = e->devid;
787 case IVHD_DEV_RANGE_END:
789 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
795 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
797 amd_iommu_alias_table[dev_i] = devid_to;
798 set_dev_entry_from_acpi(iommu,
799 devid_to, flags, ext_flags);
801 set_dev_entry_from_acpi(iommu, dev_i,
809 p += ivhd_entry_length(p);
813 /* Initializes the device->iommu mapping for the driver */
814 static int __init init_iommu_devices(struct amd_iommu *iommu)
818 for (i = iommu->first_device; i <= iommu->last_device; ++i)
819 set_iommu_for_device(iommu, i);
824 static void __init free_iommu_one(struct amd_iommu *iommu)
826 free_command_buffer(iommu);
827 free_event_buffer(iommu);
828 iommu_unmap_mmio_space(iommu);
831 static void __init free_iommu_all(void)
833 struct amd_iommu *iommu, *next;
835 for_each_iommu_safe(iommu, next) {
836 list_del(&iommu->list);
837 free_iommu_one(iommu);
843 * This function clues the initialization function for one IOMMU
844 * together and also allocates the command buffer and programs the
845 * hardware. It does NOT enable the IOMMU. This is done afterwards.
847 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
849 spin_lock_init(&iommu->lock);
851 /* Add IOMMU to internal data structures */
852 list_add_tail(&iommu->list, &amd_iommu_list);
853 iommu->index = amd_iommus_present++;
855 if (unlikely(iommu->index >= MAX_IOMMUS)) {
856 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
860 /* Index is fine - add IOMMU to the array */
861 amd_iommus[iommu->index] = iommu;
864 * Copy data from ACPI table entry to the iommu struct
866 iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff);
870 iommu->cap_ptr = h->cap_ptr;
871 iommu->pci_seg = h->pci_seg;
872 iommu->mmio_phys = h->mmio_phys;
873 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
874 if (!iommu->mmio_base)
877 iommu->cmd_buf = alloc_command_buffer(iommu);
881 iommu->evt_buf = alloc_event_buffer(iommu);
885 iommu->int_enabled = false;
887 init_iommu_from_pci(iommu);
888 init_iommu_from_acpi(iommu, h);
889 init_iommu_devices(iommu);
891 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
892 amd_iommu_np_cache = true;
894 return pci_enable_device(iommu->dev);
898 * Iterates over all IOMMU entries in the ACPI table, allocates the
899 * IOMMU structure and initializes it with init_iommu_one()
901 static int __init init_iommu_all(struct acpi_table_header *table)
903 u8 *p = (u8 *)table, *end = (u8 *)table;
904 struct ivhd_header *h;
905 struct amd_iommu *iommu;
908 end += table->length;
909 p += IVRS_HEADER_LENGTH;
912 h = (struct ivhd_header *)p;
916 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
917 "seg: %d flags: %01x info %04x\n",
918 PCI_BUS(h->devid), PCI_SLOT(h->devid),
919 PCI_FUNC(h->devid), h->cap_ptr,
920 h->pci_seg, h->flags, h->info);
921 DUMP_printk(" mmio-addr: %016llx\n",
924 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
926 amd_iommu_init_err = -ENOMEM;
930 ret = init_iommu_one(iommu, h);
932 amd_iommu_init_err = ret;
947 /****************************************************************************
949 * The following functions initialize the MSI interrupts for all IOMMUs
950 * in the system. Its a bit challenging because there could be multiple
951 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
954 ****************************************************************************/
956 static int iommu_setup_msi(struct amd_iommu *iommu)
960 if (pci_enable_msi(iommu->dev))
963 r = request_irq(iommu->dev->irq, amd_iommu_int_handler,
969 pci_disable_msi(iommu->dev);
973 iommu->int_enabled = true;
974 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
979 static int iommu_init_msi(struct amd_iommu *iommu)
981 if (iommu->int_enabled)
984 if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
985 return iommu_setup_msi(iommu);
990 /****************************************************************************
992 * The next functions belong to the third pass of parsing the ACPI
993 * table. In this last pass the memory mapping requirements are
994 * gathered (like exclusion and unity mapping reanges).
996 ****************************************************************************/
998 static void __init free_unity_maps(void)
1000 struct unity_map_entry *entry, *next;
1002 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1003 list_del(&entry->list);
1008 /* called when we find an exclusion range definition in ACPI */
1009 static int __init init_exclusion_range(struct ivmd_header *m)
1014 case ACPI_IVMD_TYPE:
1015 set_device_exclusion_range(m->devid, m);
1017 case ACPI_IVMD_TYPE_ALL:
1018 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1019 set_device_exclusion_range(i, m);
1021 case ACPI_IVMD_TYPE_RANGE:
1022 for (i = m->devid; i <= m->aux; ++i)
1023 set_device_exclusion_range(i, m);
1032 /* called for unity map ACPI definition */
1033 static int __init init_unity_map_range(struct ivmd_header *m)
1035 struct unity_map_entry *e = 0;
1038 e = kzalloc(sizeof(*e), GFP_KERNEL);
1046 case ACPI_IVMD_TYPE:
1047 s = "IVMD_TYPEi\t\t\t";
1048 e->devid_start = e->devid_end = m->devid;
1050 case ACPI_IVMD_TYPE_ALL:
1051 s = "IVMD_TYPE_ALL\t\t";
1053 e->devid_end = amd_iommu_last_bdf;
1055 case ACPI_IVMD_TYPE_RANGE:
1056 s = "IVMD_TYPE_RANGE\t\t";
1057 e->devid_start = m->devid;
1058 e->devid_end = m->aux;
1061 e->address_start = PAGE_ALIGN(m->range_start);
1062 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1063 e->prot = m->flags >> 1;
1065 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1066 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1067 PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start),
1068 PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end),
1069 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1070 e->address_start, e->address_end, m->flags);
1072 list_add_tail(&e->list, &amd_iommu_unity_map);
1077 /* iterates over all memory definitions we find in the ACPI table */
1078 static int __init init_memory_definitions(struct acpi_table_header *table)
1080 u8 *p = (u8 *)table, *end = (u8 *)table;
1081 struct ivmd_header *m;
1083 end += table->length;
1084 p += IVRS_HEADER_LENGTH;
1087 m = (struct ivmd_header *)p;
1088 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1089 init_exclusion_range(m);
1090 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1091 init_unity_map_range(m);
1100 * Init the device table to not allow DMA access for devices and
1101 * suppress all page faults
1103 static void init_device_table(void)
1107 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1108 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1109 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1114 * This function finally enables all IOMMUs found in the system after
1115 * they have been initialized
1117 static void enable_iommus(void)
1119 struct amd_iommu *iommu;
1121 for_each_iommu(iommu) {
1122 iommu_disable(iommu);
1123 iommu_set_device_table(iommu);
1124 iommu_enable_command_buffer(iommu);
1125 iommu_enable_event_buffer(iommu);
1126 iommu_set_exclusion_range(iommu);
1127 iommu_init_msi(iommu);
1128 iommu_enable(iommu);
1132 static void disable_iommus(void)
1134 struct amd_iommu *iommu;
1136 for_each_iommu(iommu)
1137 iommu_disable(iommu);
1141 * Suspend/Resume support
1142 * disable suspend until real resume implemented
1145 static int amd_iommu_resume(struct sys_device *dev)
1147 /* re-load the hardware */
1151 * we have to flush after the IOMMUs are enabled because a
1152 * disabled IOMMU will never execute the commands we send
1154 amd_iommu_flush_all_devices();
1155 amd_iommu_flush_all_domains();
1160 static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state)
1162 /* disable IOMMUs to go out of the way for BIOS */
1168 static struct sysdev_class amd_iommu_sysdev_class = {
1169 .name = "amd_iommu",
1170 .suspend = amd_iommu_suspend,
1171 .resume = amd_iommu_resume,
1174 static struct sys_device device_amd_iommu = {
1176 .cls = &amd_iommu_sysdev_class,
1180 * This is the core init function for AMD IOMMU hardware in the system.
1181 * This function is called from the generic x86 DMA layer initialization
1184 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1187 * 1 pass) Find the highest PCI device id the driver has to handle.
1188 * Upon this information the size of the data structures is
1189 * determined that needs to be allocated.
1191 * 2 pass) Initialize the data structures just allocated with the
1192 * information in the ACPI table about available AMD IOMMUs
1193 * in the system. It also maps the PCI devices in the
1194 * system to specific IOMMUs
1196 * 3 pass) After the basic data structures are allocated and
1197 * initialized we update them with information about memory
1198 * remapping requirements parsed out of the ACPI table in
1201 * After that the hardware is initialized and ready to go. In the last
1202 * step we do some Linux specific things like registering the driver in
1203 * the dma_ops interface and initializing the suspend/resume support
1204 * functions. Finally it prints some information about AMD IOMMUs and
1205 * the driver state and enables the hardware.
1207 static int __init amd_iommu_init(void)
1212 * First parse ACPI tables to find the largest Bus/Dev/Func
1213 * we need to handle. Upon this information the shared data
1214 * structures for the IOMMUs in the system will be allocated
1216 if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0)
1219 ret = amd_iommu_init_err;
1223 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1224 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1225 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1229 /* Device table - directly used by all IOMMUs */
1230 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1231 get_order(dev_table_size));
1232 if (amd_iommu_dev_table == NULL)
1236 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1237 * IOMMU see for that device
1239 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1240 get_order(alias_table_size));
1241 if (amd_iommu_alias_table == NULL)
1244 /* IOMMU rlookup table - find the IOMMU for a specific device */
1245 amd_iommu_rlookup_table = (void *)__get_free_pages(
1246 GFP_KERNEL | __GFP_ZERO,
1247 get_order(rlookup_table_size));
1248 if (amd_iommu_rlookup_table == NULL)
1251 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1252 GFP_KERNEL | __GFP_ZERO,
1253 get_order(MAX_DOMAIN_ID/8));
1254 if (amd_iommu_pd_alloc_bitmap == NULL)
1257 /* init the device table */
1258 init_device_table();
1261 * let all alias entries point to itself
1263 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1264 amd_iommu_alias_table[i] = i;
1267 * never allocate domain 0 because its used as the non-allocated and
1268 * error value placeholder
1270 amd_iommu_pd_alloc_bitmap[0] = 1;
1272 spin_lock_init(&amd_iommu_pd_lock);
1275 * now the data structures are allocated and basically initialized
1276 * start the real acpi table scan
1279 if (acpi_table_parse("IVRS", init_iommu_all) != 0)
1282 if (amd_iommu_init_err) {
1283 ret = amd_iommu_init_err;
1287 if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
1290 if (amd_iommu_init_err) {
1291 ret = amd_iommu_init_err;
1295 ret = sysdev_class_register(&amd_iommu_sysdev_class);
1299 ret = sysdev_register(&device_amd_iommu);
1303 ret = amd_iommu_init_devices();
1309 if (iommu_pass_through)
1310 ret = amd_iommu_init_passthrough();
1312 ret = amd_iommu_init_dma_ops();
1317 amd_iommu_init_api();
1319 amd_iommu_init_notifier();
1321 if (iommu_pass_through)
1324 if (amd_iommu_unmap_flush)
1325 printk(KERN_INFO "AMD-Vi: IO/TLB flush on unmap enabled\n");
1327 printk(KERN_INFO "AMD-Vi: Lazy IO/TLB flushing enabled\n");
1329 x86_platform.iommu_shutdown = disable_iommus;
1336 amd_iommu_uninit_devices();
1338 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1339 get_order(MAX_DOMAIN_ID/8));
1341 free_pages((unsigned long)amd_iommu_rlookup_table,
1342 get_order(rlookup_table_size));
1344 free_pages((unsigned long)amd_iommu_alias_table,
1345 get_order(alias_table_size));
1347 free_pages((unsigned long)amd_iommu_dev_table,
1348 get_order(dev_table_size));
1357 /****************************************************************************
1359 * Early detect code. This code runs at IOMMU detection time in the DMA
1360 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1363 ****************************************************************************/
1364 static int __init early_amd_iommu_detect(struct acpi_table_header *table)
1369 void __init amd_iommu_detect(void)
1371 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
1374 if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
1376 amd_iommu_detected = 1;
1377 x86_init.iommu.iommu_init = amd_iommu_init;
1379 /* Make sure ACS will be enabled */
1384 /****************************************************************************
1386 * Parsing functions for the AMD IOMMU specific kernel command line
1389 ****************************************************************************/
1391 static int __init parse_amd_iommu_dump(char *str)
1393 amd_iommu_dump = true;
1398 static int __init parse_amd_iommu_options(char *str)
1400 for (; *str; ++str) {
1401 if (strncmp(str, "fullflush", 9) == 0)
1402 amd_iommu_unmap_flush = true;
1408 __setup("amd_iommu_dump", parse_amd_iommu_dump);
1409 __setup("amd_iommu=", parse_amd_iommu_options);